1 /***************************************************************************//**
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3 * @brief External Bus Interface (EBI) Peripheral API
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5 *******************************************************************************
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7 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
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8 *******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
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21 * obligation to support this Software. Silicon Labs is providing the
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22 * Software "AS IS", with no express or implied warranties of any kind,
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23 * including, but not limited to, any implied warranties of merchantability
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24 * or fitness for any particular purpose or warranties against infringement
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25 * of any proprietary rights of a third party.
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27 * Silicon Labs will not be liable for any consequential, incidental, or
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28 * special damages, or any other relief, or for any claim by any third party,
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29 * arising from your use of this Software.
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31 ******************************************************************************/
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34 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
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35 #include "em_assert.h"
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38 /***************************************************************************//**
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39 * @addtogroup EM_Library
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41 ******************************************************************************/
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43 /***************************************************************************//**
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45 * @brief EBI External Bus Interface (EBI) Peripheral API
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47 ******************************************************************************/
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49 /***************************************************************************//**
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51 * Configure and enable External Bus Interface
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53 * @param[in] ebiInit
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54 * EBI configuration structure
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57 * GPIO lines must be configured as PUSH_PULL for correct operation
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58 * GPIO and EBI clocks must be enabled in the CMU
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59 ******************************************************************************/
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60 void EBI_Init(const EBI_Init_TypeDef *ebiInit)
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62 uint32_t ctrl = EBI->CTRL;
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64 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
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65 /* Enable Independent Timing for devices that supports it */
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66 ctrl |= EBI_CTRL_ITS;
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68 /* Set polarity of address ready */
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69 EBI_BankPolaritySet(ebiInit->banks, ebiLineARDY, ebiInit->ardyPolarity);
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70 /* Set polarity of address latch enable */
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71 EBI_BankPolaritySet(ebiInit->banks, ebiLineALE, ebiInit->alePolarity);
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72 /* Set polarity of write enable */
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73 EBI_BankPolaritySet(ebiInit->banks, ebiLineWE, ebiInit->wePolarity);
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74 /* Set polarity of read enable */
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75 EBI_BankPolaritySet(ebiInit->banks, ebiLineRE, ebiInit->rePolarity);
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76 /* Set polarity of chip select lines */
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77 EBI_BankPolaritySet(ebiInit->banks, ebiLineCS, ebiInit->csPolarity);
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78 /* Set polarity of byte lane line */
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79 EBI_BankPolaritySet(ebiInit->banks, ebiLineBL, ebiInit->blPolarity);
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81 /* Set polarity of address ready */
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82 EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity);
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83 /* Set polarity of address latch enable */
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84 EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity);
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85 /* Set polarity of write enable */
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86 EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity);
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87 /* Set polarity of read enable */
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88 EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity);
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89 /* Set polarity of chip select lines */
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90 EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity);
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93 /* Configure EBI mode and control settings */
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94 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
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95 if (ebiInit->banks & EBI_BANK0)
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97 ctrl &= ~(_EBI_CTRL_MODE_MASK
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98 | _EBI_CTRL_ARDYEN_MASK
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99 | _EBI_CTRL_ARDYTODIS_MASK
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100 | _EBI_CTRL_BL_MASK
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101 | _EBI_CTRL_NOIDLE_MASK
\r
102 | _EBI_CTRL_BANK0EN_MASK);
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103 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE_SHIFT);
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104 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
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105 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
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106 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
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107 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
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108 if ( ebiInit->enable)
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110 ctrl |= EBI_CTRL_BANK0EN;
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113 if (ebiInit->banks & EBI_BANK1)
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115 ctrl &= ~(_EBI_CTRL_BL1_MASK
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116 | _EBI_CTRL_MODE1_MASK
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117 | _EBI_CTRL_ARDY1EN_MASK
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118 | _EBI_CTRL_ARDYTO1DIS_MASK
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119 | _EBI_CTRL_NOIDLE1_MASK
\r
120 | _EBI_CTRL_BANK1EN_MASK);
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121 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT);
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122 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
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123 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
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124 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
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125 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
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126 if ( ebiInit->enable)
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128 ctrl |= EBI_CTRL_BANK1EN;
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131 if (ebiInit->banks & EBI_BANK2)
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133 ctrl &= ~(_EBI_CTRL_BL2_MASK
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134 | _EBI_CTRL_MODE2_MASK
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135 | _EBI_CTRL_ARDY2EN_MASK
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136 | _EBI_CTRL_ARDYTO2DIS_MASK
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137 | _EBI_CTRL_NOIDLE2_MASK
\r
138 | _EBI_CTRL_BANK2EN_MASK);
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139 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE2_SHIFT);
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140 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY2EN_SHIFT);
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141 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
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142 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
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143 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
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144 if ( ebiInit->enable)
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146 ctrl |= EBI_CTRL_BANK2EN;
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149 if (ebiInit->banks & EBI_BANK3)
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151 ctrl &= ~(_EBI_CTRL_BL3_MASK
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152 | _EBI_CTRL_MODE3_MASK
\r
153 | _EBI_CTRL_ARDY3EN_MASK
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154 | _EBI_CTRL_ARDYTO3DIS_MASK
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155 | _EBI_CTRL_NOIDLE3_MASK
\r
156 | _EBI_CTRL_BANK3EN_MASK);
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157 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT);
\r
158 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
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159 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
\r
160 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
\r
161 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
\r
162 if ( ebiInit->enable)
\r
164 ctrl |= EBI_CTRL_BANK3EN;
\r
168 ctrl &= ~(_EBI_CTRL_MODE_MASK
\r
169 | _EBI_CTRL_ARDYEN_MASK
\r
170 | _EBI_CTRL_ARDYTODIS_MASK
\r
171 | _EBI_CTRL_BANK0EN_MASK
\r
172 | _EBI_CTRL_BANK1EN_MASK
\r
173 | _EBI_CTRL_BANK2EN_MASK
\r
174 | _EBI_CTRL_BANK3EN_MASK);
\r
175 if ( ebiInit->enable)
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177 if ( ebiInit->banks & EBI_BANK0 )
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179 ctrl |= EBI_CTRL_BANK0EN;
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181 if ( ebiInit->banks & EBI_BANK1 )
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183 ctrl |= EBI_CTRL_BANK1EN;
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185 if ( ebiInit->banks & EBI_BANK2 )
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187 ctrl |= EBI_CTRL_BANK2EN;
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189 if ( ebiInit->banks & EBI_BANK3 )
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191 ctrl |= EBI_CTRL_BANK3EN;
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194 ctrl |= ebiInit->mode;
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195 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
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196 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
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199 /* Configure timing */
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200 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
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201 EBI_BankReadTimingSet(ebiInit->banks,
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202 ebiInit->readSetupCycles,
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203 ebiInit->readStrobeCycles,
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204 ebiInit->readHoldCycles);
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205 EBI_BankReadTimingConfig(ebiInit->banks,
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206 ebiInit->readPageMode,
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207 ebiInit->readPrefetch,
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208 ebiInit->readHalfRE);
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209 EBI_BankWriteTimingSet(ebiInit->banks,
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210 ebiInit->writeSetupCycles,
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211 ebiInit->writeStrobeCycles,
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212 ebiInit->writeHoldCycles);
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213 EBI_BankWriteTimingConfig(ebiInit->banks,
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214 ebiInit->writeBufferDisable,
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215 ebiInit->writeHalfWE);
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216 EBI_BankAddressTimingSet(ebiInit->banks,
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217 ebiInit->addrSetupCycles,
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218 ebiInit->addrHoldCycles);
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219 EBI_BankAddressTimingConfig(ebiInit->banks,
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220 ebiInit->addrHalfALE);
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222 EBI_ReadTimingSet(ebiInit->readSetupCycles,
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223 ebiInit->readStrobeCycles,
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224 ebiInit->readHoldCycles);
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225 EBI_WriteTimingSet(ebiInit->writeSetupCycles,
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226 ebiInit->writeStrobeCycles,
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227 ebiInit->writeHoldCycles);
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228 EBI_AddressTimingSet(ebiInit->addrSetupCycles,
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229 ebiInit->addrHoldCycles);
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232 /* Activate new configuration */
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235 /* Configure Adress Latch Enable */
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236 switch (ebiInit->mode)
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238 case ebiModeD16A16ALE:
\r
239 case ebiModeD8A24ALE:
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240 /* Address Latch Enable */
\r
241 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 1);
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243 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
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247 /* Make sure Address Latch is disabled */
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248 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 0);
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251 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
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252 /* Limit pin enable */
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253 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_ALB_MASK) | ebiInit->aLow;
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254 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_APEN_MASK) | ebiInit->aHigh;
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256 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location;
\r
258 /* Enable EBI BL pin if necessary */
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259 if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK))
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261 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable);
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264 /* Enable EBI pins EBI_WEn and EBI_REn */
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265 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_EBIPEN_SHIFT, 1);
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267 /* Enable chip select lines */
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268 EBI_ChipSelectEnable(ebiInit->csLines, true);
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272 /***************************************************************************//**
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274 * Disable External Bus Interface
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275 ******************************************************************************/
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276 void EBI_Disable(void)
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279 EBI->ROUTE = _EBI_ROUTE_RESETVALUE;
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280 /* Disable banks */
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281 EBI->CTRL = _EBI_CTRL_RESETVALUE;
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285 /***************************************************************************//**
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287 * Enable or disable EBI Bank
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290 * Banks to reconfigure, mask of EBI_BANK<n> flags
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292 * @param[in] enable
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293 * True to enable, false to disable
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294 ******************************************************************************/
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295 void EBI_BankEnable(uint32_t banks, bool enable)
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297 if (banks & EBI_BANK0)
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299 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable);
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301 if (banks & EBI_BANK1)
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303 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable);
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305 if (banks & EBI_BANK2)
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307 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable);
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309 if (banks & EBI_BANK3)
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311 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable);
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316 /***************************************************************************//**
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318 * Return base address of EBI bank
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321 * Bank to return start address for
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324 * Absolute address of bank
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325 ******************************************************************************/
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326 uint32_t EBI_BankAddress(uint32_t bank)
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328 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
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329 if(EBI->CTRL & EBI_CTRL_ALTMAP)
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334 return(EBI_MEM_BASE);
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337 return(EBI_MEM_BASE + 0x10000000UL);
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340 return(EBI_MEM_BASE + 0x20000000UL);
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343 return(EBI_MEM_BASE + 0x30000000UL);
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354 return(EBI_MEM_BASE);
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357 return(EBI_MEM_BASE + 0x04000000UL);
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360 return(EBI_MEM_BASE + 0x08000000UL);
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363 return(EBI_MEM_BASE + 0x0C000000UL);
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373 /***************************************************************************//**
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375 * Enable or disable EBI Chip Select
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378 * ChipSelect lines to reconfigure, mask of EBI_CS<n> flags
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380 * @param[in] enable
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381 * True to enable, false to disable
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382 ******************************************************************************/
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383 void EBI_ChipSelectEnable(uint32_t cs, bool enable)
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387 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS0PEN_SHIFT, enable);
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391 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS1PEN_SHIFT, enable);
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395 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS2PEN_SHIFT, enable);
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399 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS3PEN_SHIFT, enable);
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404 /***************************************************************************//**
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406 * Configure EBI pin polarity
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409 * Which pin/line to configure
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411 * @param[in] polarity
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412 * Active high, or active low
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413 ******************************************************************************/
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414 void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
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419 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
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422 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity);
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425 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity);
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428 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity);
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431 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity);
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433 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
\r
435 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity);
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437 case ebiLineTFTVSync:
\r
438 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
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440 case ebiLineTFTHSync:
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441 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
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443 case ebiLineTFTDataEn:
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444 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
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446 case ebiLineTFTDClk:
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447 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
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450 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
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460 /***************************************************************************//**
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462 * Configure timing values of read bus accesses
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464 * @param[in] setupCycles
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465 * Number of clock cycles for address setup before REn is asserted
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467 * @param[in] strobeCycles
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468 * The number of cycles the REn is held active. After the specified number of
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469 * cycles, data is read. If set to 0, 1 cycle is inserted by HW
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471 * @param[in] holdCycles
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472 * The number of cycles CSn is held active after the REn is dessarted
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473 ******************************************************************************/
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474 void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles)
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476 uint32_t readTiming;
\r
478 /* Check that timings are within limits */
\r
479 EFM_ASSERT(setupCycles < 4);
\r
480 EFM_ASSERT(strobeCycles < 16);
\r
481 EFM_ASSERT(holdCycles < 4);
\r
483 /* Configure timing values */
\r
484 readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
\r
485 | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
\r
486 | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
\r
489 EBI->RDTIMING = (EBI->RDTIMING
\r
490 & ~(_EBI_RDTIMING_RDSETUP_MASK
\r
491 | _EBI_RDTIMING_RDSTRB_MASK
\r
492 | _EBI_RDTIMING_RDHOLD_MASK))
\r
497 /***************************************************************************//**
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499 * Configure timing values of write bus accesses
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501 * @param[in] setupCycles
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502 * Number of clock cycles for address setup before WEn is asserted
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504 * @param[in] strobeCycles
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505 * Number of cycles WEn is held active. If set to 0, 1 cycle is inserted by HW
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507 * @param[in] holdCycles
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508 * Number of cycles CSn is held active after the WEn is deasserted
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509 ******************************************************************************/
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510 void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles)
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512 uint32_t writeTiming;
\r
514 /* Check that timings are within limits */
\r
515 EFM_ASSERT(setupCycles < 4);
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516 EFM_ASSERT(strobeCycles < 16);
\r
517 EFM_ASSERT(holdCycles < 4);
\r
519 /* Configure timing values */
\r
520 writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
\r
521 | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
\r
522 | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
\r
524 EBI->WRTIMING = (EBI->WRTIMING
\r
525 & ~(_EBI_WRTIMING_WRSETUP_MASK
\r
526 | _EBI_WRTIMING_WRSTRB_MASK
\r
527 | _EBI_WRTIMING_WRHOLD_MASK))
\r
532 /***************************************************************************//**
\r
534 * Configure timing values of address latch bus accesses
\r
536 * @param[in] setupCycles
\r
537 * Sets the number of cycles the address is held after ALE is asserted
\r
539 * @param[in] holdCycles
\r
540 * Sets the number of cycles the address is driven onto the ADDRDAT bus before
\r
541 * ALE is asserted. If set 0, 1 cycle is inserted by HW
\r
542 ******************************************************************************/
\r
543 void EBI_AddressTimingSet(int setupCycles, int holdCycles)
\r
545 uint32_t addressLatchTiming;
\r
547 /* Check that timing values are within limits */
\r
548 EFM_ASSERT(setupCycles < 4);
\r
549 EFM_ASSERT(holdCycles < 4);
\r
551 /* Configure address latch timing values */
\r
552 addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
\r
553 | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
\r
555 EBI->ADDRTIMING = (EBI->ADDRTIMING
\r
556 & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
\r
557 | _EBI_ADDRTIMING_ADDRHOLD_MASK))
\r
558 | addressLatchTiming;
\r
561 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
\r
562 /***************************************************************************//**
\r
564 * Configure and initialize TFT Direct Drive
\r
566 * @param[in] ebiTFTInit
\r
567 * TFT Initialization structure
\r
568 ******************************************************************************/
\r
569 void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit)
\r
573 /* Configure base address for frame buffer offset to EBI bank */
\r
574 EBI_TFTFrameBaseSet(ebiTFTInit->addressOffset);
\r
576 /* Configure display size and porch areas */
\r
577 EBI_TFTSizeSet(ebiTFTInit->hsize,
\r
578 ebiTFTInit->vsize);
\r
579 EBI_TFTHPorchSet(ebiTFTInit->hPorchFront,
\r
580 ebiTFTInit->hPorchBack,
\r
581 ebiTFTInit->hPulseWidth);
\r
582 EBI_TFTVPorchSet(ebiTFTInit->vPorchFront,
\r
583 ebiTFTInit->vPorchBack,
\r
584 ebiTFTInit->vPulseWidth);
\r
586 /* Configure timing settings */
\r
587 EBI_TFTTimingSet(ebiTFTInit->dclkPeriod,
\r
588 ebiTFTInit->startPosition,
\r
589 ebiTFTInit->setupCycles,
\r
590 ebiTFTInit->holdCycles);
\r
592 /* Configure line polarity settings */
\r
593 EBI_PolaritySet(ebiLineTFTCS, ebiTFTInit->csPolarity);
\r
594 EBI_PolaritySet(ebiLineTFTDClk, ebiTFTInit->dclkPolarity);
\r
595 EBI_PolaritySet(ebiLineTFTDataEn, ebiTFTInit->dataenPolarity);
\r
596 EBI_PolaritySet(ebiLineTFTVSync, ebiTFTInit->vsyncPolarity);
\r
597 EBI_PolaritySet(ebiLineTFTHSync, ebiTFTInit->hsyncPolarity);
\r
599 /* Main control, EBI bank select, mask and blending configuration */
\r
600 ctrl = (uint32_t)ebiTFTInit->bank
\r
601 | (uint32_t)ebiTFTInit->width
\r
602 | (uint32_t)ebiTFTInit->colSrc
\r
603 | (uint32_t)ebiTFTInit->interleave
\r
604 | (uint32_t)ebiTFTInit->fbTrigger
\r
605 | (uint32_t)(ebiTFTInit->shiftDClk == true
\r
606 ? (1 << _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT) : 0)
\r
607 | (uint32_t)ebiTFTInit->maskBlend
\r
608 | (uint32_t)ebiTFTInit->driveMode;
\r
610 EBI->TFTCTRL = ctrl;
\r
612 /* Enable TFT pins */
\r
613 if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled)
\r
615 EBI->ROUTE |= EBI_ROUTE_TFTPEN;
\r
620 /***************************************************************************//**
\r
622 * Configure and initialize TFT size settings
\r
624 * @param[in] horizontal
\r
625 * TFT display horizontal size in pixels
\r
626 * @param[in] vertical
\r
627 * TFT display vertical size in pixels
\r
628 ******************************************************************************/
\r
629 void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical)
\r
631 EFM_ASSERT((horizontal-1) < 1024);
\r
632 EFM_ASSERT((vertical-1) < 1024);
\r
634 EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT)
\r
635 | ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT);
\r
638 /***************************************************************************//**
\r
640 * Configure and initialize Horizontal Porch Settings
\r
643 * Horizontal front porch size in pixels
\r
645 * Horizontal back porch size in pixels
\r
646 * @param[in] pulseWidth
\r
647 * Horizontal synchronization pulse width. Set to required -1.
\r
648 ******************************************************************************/
\r
649 void EBI_TFTHPorchSet(int front, int back, int pulseWidth)
\r
651 EFM_ASSERT(front < 256);
\r
652 EFM_ASSERT(back < 256);
\r
653 EFM_ASSERT((pulseWidth-1) < 128);
\r
655 EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT)
\r
656 | (back << _EBI_TFTHPORCH_HBPORCH_SHIFT)
\r
657 | ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
\r
661 /***************************************************************************//**
\r
663 * Configure Vertical Porch Settings
\r
666 * Vertical front porch size in pixels
\r
668 * Vertical back porch size in pixels
\r
669 * @param[in] pulseWidth
\r
670 * Vertical synchronization pulse width. Set to required -1.
\r
671 ******************************************************************************/
\r
672 void EBI_TFTVPorchSet(int front, int back, int pulseWidth)
\r
674 EFM_ASSERT(front < 256);
\r
675 EFM_ASSERT(back < 256);
\r
676 EFM_ASSERT((pulseWidth-1) < 128);
\r
678 EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT)
\r
679 | (back << _EBI_TFTVPORCH_VBPORCH_SHIFT)
\r
680 | ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
\r
684 /***************************************************************************//**
\r
686 * Configure TFT Direct Drive Timing Settings
\r
688 * @param[in] dclkPeriod
\r
689 * DCLK period in internal cycles
\r
692 * Starting position of external direct drive, relative to DCLK inactive edge
\r
695 * Number of cycles RGB data is driven before active edge of DCLK
\r
698 * Number of cycles RGB data is held after active edge of DCLK
\r
699 ******************************************************************************/
\r
700 void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold)
\r
702 EFM_ASSERT(dclkPeriod < 2048);
\r
703 EFM_ASSERT(start < 2048);
\r
704 EFM_ASSERT(setup < 4);
\r
705 EFM_ASSERT(hold < 4);
\r
707 EBI->TFTTIMING = (dclkPeriod << _EBI_TFTTIMING_DCLKPERIOD_SHIFT)
\r
708 | (start << _EBI_TFTTIMING_TFTSTART_SHIFT)
\r
709 | (setup << _EBI_TFTTIMING_TFTSETUP_SHIFT)
\r
710 | (hold << _EBI_TFTTIMING_TFTHOLD_SHIFT);
\r
714 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
\r
715 /***************************************************************************//**
\r
717 * Configure read operation parameters for selected bank
\r
720 * Mask of memory bank(s) to configure write timing for
\r
722 * @param[in] pageMode
\r
723 * Enables or disables half cycle WE strobe in last strobe cycle
\r
725 * @param[in] prefetch
\r
726 * Enables or disables half cycle WE strobe in last strobe cycle
\r
728 * @param[in] halfRE
\r
729 * Enables or disables half cycle WE strobe in last strobe cycle
\r
730 ******************************************************************************/
\r
731 void EBI_BankReadTimingConfig(uint32_t banks, bool pageMode, bool prefetch, bool halfRE)
\r
733 /* Verify only valid banks are used */
\r
734 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
\r
736 /* Configure read operation parameters */
\r
737 if( banks & EBI_BANK0 )
\r
739 BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
\r
740 BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
\r
741 BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
\r
743 if( banks & EBI_BANK1 )
\r
745 BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
\r
746 BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
\r
747 BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
\r
749 if( banks & EBI_BANK2 )
\r
751 BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
\r
752 BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
\r
753 BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
\r
755 if( banks & EBI_BANK3 )
\r
757 BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
\r
758 BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
\r
759 BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
\r
763 /***************************************************************************//**
\r
765 * Configure timing values of read bus accesses
\r
768 * Mask of memory bank(s) to configure timing for
\r
770 * @param[in] setupCycles
\r
771 * Number of clock cycles for address setup before REn is asserted
\r
773 * @param[in] strobeCycles
\r
774 * The number of cycles the REn is held active. After the specified number of
\r
775 * cycles, data is read. If set to 0, 1 cycle is inserted by HW
\r
777 * @param[in] holdCycles
\r
778 * The number of cycles CSn is held active after the REn is dessarted
\r
779 ******************************************************************************/
\r
780 void EBI_BankReadTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
\r
782 uint32_t readTiming;
\r
784 /* Verify only valid banks are used */
\r
785 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
\r
787 /* Check that timings are within limits */
\r
788 EFM_ASSERT(setupCycles < 4);
\r
789 EFM_ASSERT(strobeCycles < 64);
\r
790 EFM_ASSERT(holdCycles < 4);
\r
792 /* Configure timing values */
\r
793 readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
\r
794 | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
\r
795 | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
\r
797 if (banks & EBI_BANK0)
\r
799 EBI->RDTIMING = (EBI->RDTIMING
\r
800 & ~(_EBI_RDTIMING_RDSETUP_MASK
\r
801 | _EBI_RDTIMING_RDSTRB_MASK
\r
802 | _EBI_RDTIMING_RDHOLD_MASK))
\r
805 if (banks & EBI_BANK1)
\r
807 EBI->RDTIMING1 = (EBI->RDTIMING1
\r
808 & ~(_EBI_RDTIMING1_RDSETUP_MASK
\r
809 | _EBI_RDTIMING1_RDSTRB_MASK
\r
810 | _EBI_RDTIMING1_RDHOLD_MASK))
\r
813 if (banks & EBI_BANK2)
\r
815 EBI->RDTIMING2 = (EBI->RDTIMING2
\r
816 & ~(_EBI_RDTIMING2_RDSETUP_MASK
\r
817 | _EBI_RDTIMING2_RDSTRB_MASK
\r
818 | _EBI_RDTIMING2_RDHOLD_MASK))
\r
821 if (banks & EBI_BANK3)
\r
823 EBI->RDTIMING3 = (EBI->RDTIMING3
\r
824 & ~(_EBI_RDTIMING3_RDSETUP_MASK
\r
825 | _EBI_RDTIMING3_RDSTRB_MASK
\r
826 | _EBI_RDTIMING3_RDHOLD_MASK))
\r
832 /***************************************************************************//**
\r
834 * Configure write operation parameters for selected bank
\r
837 * Mask of memory bank(s) to configure write timing for
\r
839 * @param[in] writeBufDisable
\r
840 * If true, disable the write buffer
\r
842 * @param[in] halfWE
\r
843 * Enables or disables half cycle WE strobe in last strobe cycle
\r
844 ******************************************************************************/
\r
845 void EBI_BankWriteTimingConfig(uint32_t banks, bool writeBufDisable, bool halfWE)
\r
847 /* Verify only valid banks are used */
\r
848 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
\r
850 /* Configure write operation parameters */
\r
851 if( banks & EBI_BANK0 )
\r
853 BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
\r
854 BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
\r
856 if( banks & EBI_BANK1 )
\r
858 BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
\r
859 BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
\r
861 if( banks & EBI_BANK2 )
\r
863 BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
\r
864 BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
\r
866 if( banks & EBI_BANK3 )
\r
868 BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
\r
869 BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
\r
874 /***************************************************************************//**
\r
876 * Configure timing values of write bus accesses
\r
879 * Mask of memory bank(s) to configure write timing for
\r
881 * @param[in] setupCycles
\r
882 * Number of clock cycles for address setup before WEn is asserted
\r
884 * @param[in] strobeCycles
\r
885 * Number of cycles WEn is held active. If set to 0, 1 cycle is inserted by HW
\r
887 * @param[in] holdCycles
\r
888 * Number of cycles CSn is held active after the WEn is deasserted
\r
889 ******************************************************************************/
\r
890 void EBI_BankWriteTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
\r
892 uint32_t writeTiming;
\r
894 /* Verify only valid banks are used */
\r
895 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
\r
897 /* Check that timings are within limits */
\r
898 EFM_ASSERT(setupCycles < 4);
\r
899 EFM_ASSERT(strobeCycles < 64);
\r
900 EFM_ASSERT(holdCycles < 4);
\r
902 /* Configure timing values */
\r
903 writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
\r
904 | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
\r
905 | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
\r
907 if (banks & EBI_BANK0)
\r
909 EBI->WRTIMING = (EBI->WRTIMING
\r
910 & ~(_EBI_WRTIMING_WRSETUP_MASK
\r
911 | _EBI_WRTIMING_WRSTRB_MASK
\r
912 | _EBI_WRTIMING_WRHOLD_MASK))
\r
915 if (banks & EBI_BANK1)
\r
917 EBI->WRTIMING1 = (EBI->WRTIMING1
\r
918 & ~(_EBI_WRTIMING1_WRSETUP_MASK
\r
919 | _EBI_WRTIMING1_WRSTRB_MASK
\r
920 | _EBI_WRTIMING1_WRHOLD_MASK))
\r
923 if (banks & EBI_BANK2)
\r
925 EBI->WRTIMING2 = (EBI->WRTIMING2
\r
926 & ~(_EBI_WRTIMING2_WRSETUP_MASK
\r
927 | _EBI_WRTIMING2_WRSTRB_MASK
\r
928 | _EBI_WRTIMING2_WRHOLD_MASK))
\r
931 if (banks & EBI_BANK3)
\r
933 EBI->WRTIMING3 = (EBI->WRTIMING3
\r
934 & ~(_EBI_WRTIMING3_WRSETUP_MASK
\r
935 | _EBI_WRTIMING3_WRSTRB_MASK
\r
936 | _EBI_WRTIMING3_WRHOLD_MASK))
\r
942 /***************************************************************************//**
\r
944 * Configure address operation parameters for selected bank
\r
947 * Mask of memory bank(s) to configure write timing for
\r
949 * @param[in] halfALE
\r
950 * Enables or disables half cycle ALE strobe in last strobe cycle
\r
951 ******************************************************************************/
\r
952 void EBI_BankAddressTimingConfig(uint32_t banks, bool halfALE)
\r
954 /* Verify only valid banks are used */
\r
955 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
\r
957 if( banks & EBI_BANK0 )
\r
959 BUS_RegBitWrite(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
\r
961 if( banks & EBI_BANK1 )
\r
963 BUS_RegBitWrite(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
\r
965 if( banks & EBI_BANK2 )
\r
967 BUS_RegBitWrite(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
\r
969 if( banks & EBI_BANK3 )
\r
971 BUS_RegBitWrite(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
\r
976 /***************************************************************************//**
\r
978 * Configure timing values of address latch bus accesses
\r
981 * Mask of memory bank(s) to configure address timing for
\r
983 * @param[in] setupCycles
\r
984 * Sets the number of cycles the address is held after ALE is asserted
\r
986 * @param[in] holdCycles
\r
987 * Sets the number of cycles the address is driven onto the ADDRDAT bus before
\r
988 * ALE is asserted. If set 0, 1 cycle is inserted by HW
\r
989 ******************************************************************************/
\r
990 void EBI_BankAddressTimingSet(uint32_t banks, int setupCycles, int holdCycles)
\r
992 uint32_t addressLatchTiming;
\r
994 /* Verify only valid banks are used */
\r
995 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
\r
997 /* Check that timing values are within limits */
\r
998 EFM_ASSERT(setupCycles < 4);
\r
999 EFM_ASSERT(holdCycles < 4);
\r
1001 /* Configure address latch timing values */
\r
1002 addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
\r
1003 | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
\r
1005 if (banks & EBI_BANK0)
\r
1007 EBI->ADDRTIMING = (EBI->ADDRTIMING
\r
1008 & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
\r
1009 | _EBI_ADDRTIMING_ADDRHOLD_MASK))
\r
1010 | addressLatchTiming;
\r
1012 if (banks & EBI_BANK1)
\r
1014 EBI->ADDRTIMING1 = (EBI->ADDRTIMING1
\r
1015 & ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK
\r
1016 | _EBI_ADDRTIMING1_ADDRHOLD_MASK))
\r
1017 | addressLatchTiming;
\r
1019 if (banks & EBI_BANK2)
\r
1021 EBI->ADDRTIMING2 = (EBI->ADDRTIMING2
\r
1022 & ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK
\r
1023 | _EBI_ADDRTIMING2_ADDRHOLD_MASK))
\r
1024 | addressLatchTiming;
\r
1026 if (banks & EBI_BANK3)
\r
1028 EBI->ADDRTIMING3 = (EBI->ADDRTIMING3
\r
1029 & ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK
\r
1030 | _EBI_ADDRTIMING3_ADDRHOLD_MASK))
\r
1031 | addressLatchTiming;
\r
1036 /***************************************************************************//**
\r
1038 * Configure EBI pin polarity for selected bank(s) for devices with individual
\r
1041 * @param[in] banks
\r
1042 * Mask of memory bank(s) to configure polarity for
\r
1045 * Which pin/line to configure
\r
1047 * @param[in] polarity
\r
1048 * Active high, or active low
\r
1049 ******************************************************************************/
\r
1050 void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
\r
1052 uint32_t bankSet = 0;
\r
1053 volatile uint32_t *polRegister = 0;
\r
1055 /* Verify only valid banks are used */
\r
1056 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
\r
1060 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
\r
1061 if (banks & EBI_BANK0)
\r
1063 polRegister = &EBI->POLARITY;
\r
1064 bankSet = EBI_BANK0;
\r
1066 if (banks & EBI_BANK1)
\r
1068 polRegister = &EBI->POLARITY1;
\r
1069 bankSet = EBI_BANK1;
\r
1071 if (banks & EBI_BANK2)
\r
1073 polRegister = &EBI->POLARITY2;
\r
1074 bankSet = EBI_BANK2;
\r
1076 if (banks & EBI_BANK3)
\r
1078 polRegister = &EBI->POLARITY3;
\r
1079 bankSet = EBI_BANK3;
\r
1082 polRegister = &EBI->POLARITY;
\r
1086 /* What line to configure */
\r
1090 BUS_RegBitWrite(polRegister, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
\r
1093 BUS_RegBitWrite(polRegister, _EBI_POLARITY_ALEPOL_SHIFT, polarity);
\r
1096 BUS_RegBitWrite(polRegister, _EBI_POLARITY_WEPOL_SHIFT, polarity);
\r
1099 BUS_RegBitWrite(polRegister, _EBI_POLARITY_REPOL_SHIFT, polarity);
\r
1102 BUS_RegBitWrite(polRegister, _EBI_POLARITY_CSPOL_SHIFT, polarity);
\r
1104 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
\r
1106 BUS_RegBitWrite(polRegister, _EBI_POLARITY_BLPOL_SHIFT, polarity);
\r
1108 case ebiLineTFTVSync:
\r
1109 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
\r
1111 case ebiLineTFTHSync:
\r
1112 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
\r
1114 case ebiLineTFTDataEn:
\r
1115 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
\r
1117 case ebiLineTFTDClk:
\r
1118 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
\r
1120 case ebiLineTFTCS:
\r
1121 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
\r
1128 banks = banks & ~bankSet;
\r
1133 /***************************************************************************//**
\r
1135 * Configure Byte Lane Enable for select banks
\r
1138 * @param[in] banks
\r
1139 * Mask of memory bank(s) to configure polarity for
\r
1141 * @param[in] enable
\r
1143 ******************************************************************************/
\r
1144 void EBI_BankByteLaneEnable(uint32_t banks, bool enable)
\r
1146 /* Verify only valid banks are used */
\r
1147 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
\r
1149 /* Configure byte lane support for each selected bank */
\r
1150 if (banks & EBI_BANK0)
\r
1152 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable);
\r
1154 if (banks & EBI_BANK1)
\r
1156 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable);
\r
1158 if (banks & EBI_BANK2)
\r
1160 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable);
\r
1162 if (banks & EBI_BANK3)
\r
1164 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable);
\r
1169 /***************************************************************************//**
\r
1171 * Configure Alternate Address Map support
\r
1172 * Enables or disables 256MB address range for all banks
\r
1174 * @param[in] enable
\r
1175 * Set or clear address map extension
\r
1176 ******************************************************************************/
\r
1177 void EBI_AltMapEnable(bool enable)
\r
1179 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_ALTMAP_SHIFT, enable);
\r
1184 /** @} (end addtogroup EBI) */
\r
1185 /** @} (end addtogroup EM_Library) */
\r
1187 #endif /* defined(EBI_COUNT) && (EBI_COUNT > 0) */
\r