1 /******************************************************************************
\r
4 * Purpose: Provide custom interrupt service routines for Kinetis.
\r
6 * NOTE: This vector table is a superset table, so interrupt sources might be
\r
7 * listed that are not available on the specific Kinetis device you are
\r
9 ******************************************************************************/
\r
12 #define __VECTORS_H 1
\r
14 /* The kernel interrupts - in their CMSIS form. */
\r
15 extern void SVC_Handler( void );
\r
16 extern void PendSV_Handler( void );
\r
17 extern void SysTick_Handler( void );
\r
19 /* The button interrupt. */
\r
20 extern void vPort_E_ISRHandler( void );
\r
22 /* Ethernet interrupt handlers. */
\r
23 void vEMAC_TxISRHandler( void );
\r
24 void vEMAC_RxISRHandler( void );
\r
25 void vEMAC_ErrorISRHandler( void );
\r
27 // function prototype for default_isr in vectors.c
\r
28 void default_isr(void);
\r
29 void abort_isr(void);
\r
31 void hard_fault_handler_c(unsigned int * hardfault_args);
\r
33 /* Interrupt Vector Table Function Pointers */
\r
34 typedef void pointer(void);
\r
36 extern void __startup(void);
\r
38 extern unsigned long __BOOT_STACK_ADDRESS[];
\r
39 extern void __iar_program_start(void);
\r
40 // Address Vector IRQ Source module Source description
\r
41 #define VECTOR_000 (pointer*)__BOOT_STACK_ADDRESS // ARM core Initial Supervisor SP
\r
42 #define VECTOR_001 __startup // 0x0000_0004 1 - ARM core Initial Program Counter
\r
43 #define VECTOR_002 default_isr // 0x0000_0008 2 - ARM core Non-maskable Interrupt (NMI)
\r
44 #define VECTOR_003 default_isr // 0x0000_000C 3 - ARM core Hard Fault
\r
45 #define VECTOR_004 default_isr // 0x0000_0010 4 -
\r
46 #define VECTOR_005 default_isr // 0x0000_0014 5 - ARM core Bus Fault
\r
47 #define VECTOR_006 default_isr // 0x0000_0018 6 - ARM core Usage Fault
\r
48 #define VECTOR_007 default_isr // 0x0000_001C 7 -
\r
49 #define VECTOR_008 default_isr // 0x0000_0020 8 -
\r
50 #define VECTOR_009 default_isr // 0x0000_0024 9 -
\r
51 #define VECTOR_010 default_isr // 0x0000_0028 10 -
\r
52 #define VECTOR_011 SVC_Handler // 0x0000_002C 11 - ARM core Supervisor call (SVCall)
\r
53 #define VECTOR_012 default_isr // 0x0000_0030 12 - ARM core Debug Monitor
\r
54 #define VECTOR_013 default_isr // 0x0000_0034 13 -
\r
55 #define VECTOR_014 PendSV_Handler // 0x0000_0038 14 - ARM core Pendable request for system service (PendableSrvReq)
\r
56 #define VECTOR_015 SysTick_Handler // 0x0000_003C 15 - ARM core System tick timer (SysTick)
\r
57 #define VECTOR_016 default_isr // 0x0000_0040 16 0 DMA DMA Channel 0 transfer complete
\r
58 #define VECTOR_017 default_isr // 0x0000_0044 17 1 DMA DMA Channel 1 transfer complete
\r
59 #define VECTOR_018 default_isr // 0x0000_0048 18 2 DMA DMA Channel 2 transfer complete
\r
60 #define VECTOR_019 default_isr // 0x0000_004C 19 3 DMA DMA Channel 3 transfer complete
\r
61 #define VECTOR_020 default_isr // 0x0000_0050 20 4 DMA DMA Channel 4 transfer complete
\r
62 #define VECTOR_021 default_isr // 0x0000_0054 21 5 DMA DMA Channel 5 transfer complete
\r
63 #define VECTOR_022 default_isr // 0x0000_0058 22 6 DMA DMA Channel 6 transfer complete
\r
64 #define VECTOR_023 default_isr // 0x0000_005C 23 7 DMA DMA Channel 7 transfer complete
\r
65 #define VECTOR_024 default_isr // 0x0000_0060 24 8 DMA DMA Channel 8 transfer complete
\r
66 #define VECTOR_025 default_isr // 0x0000_0064 25 9 DMA DMA Channel 9 transfer complete
\r
67 #define VECTOR_026 default_isr // 0x0000_0068 26 10 DMA DMA Channel 10 transfer complete
\r
68 #define VECTOR_027 default_isr // 0x0000_006C 27 11 DMA DMA Channel 11 transfer complete
\r
69 #define VECTOR_028 default_isr // 0x0000_0070 28 12 DMA DMA Channel 12 transfer complete
\r
70 #define VECTOR_029 default_isr // 0x0000_0074 29 13 DMA DMA Channel 13 transfer complete
\r
71 #define VECTOR_030 default_isr // 0x0000_0078 30 14 DMA DMA Channel 14 transfer complete
\r
72 #define VECTOR_031 default_isr // 0x0000_007C 31 15 DMA DMA Channel 15 transfer complete
\r
73 #define VECTOR_032 default_isr // 0x0000_0080 32 16 DMA DMA Error Interrupt Channels 0-15
\r
74 #define VECTOR_033 default_isr // 0x0000_0084 33 17 MCM Normal interrupt
\r
75 #define VECTOR_034 default_isr // 0x0000_0088 34 18 Flash memory Command Complete
\r
76 #define VECTOR_035 default_isr // 0x0000_008C 35 19 Flash memory Read Collision
\r
77 #define VECTOR_036 default_isr // 0x0000_0090 36 20 Mode Controller Low Voltage Detect,Low Voltage Warning, Low Leakage Wakeup
\r
78 #define VECTOR_037 default_isr // 0x0000_0094 37 21 LLWU
\r
79 #define VECTOR_038 default_isr // 0x0000_0098 38 22 WDOG
\r
80 #define VECTOR_039 default_isr // 0x0000_009C 39 23 RNGB
\r
81 #define VECTOR_040 default_isr // 0x0000_00A0 40 24 I2C0
\r
82 #define VECTOR_041 default_isr // 0x0000_00A4 41 25 I2C1
\r
83 #define VECTOR_042 default_isr // 0x0000_00A8 42 26 SPI0 Single interrupt vector for all sources
\r
84 #define VECTOR_043 default_isr // 0x0000_00AC 43 27 SPI1 Single interrupt vector for all sources
\r
85 #define VECTOR_044 default_isr // 0x0000_00B0 44 28 SPI2 Single interrupt vector for all sources
\r
86 #define VECTOR_045 default_isr // 0x0000_00B4 45 29 CAN0 OR'ed Message buffer (0-15)
\r
87 #define VECTOR_046 default_isr // 0x0000_00B8 46 30 CAN0 Bus Off
\r
88 #define VECTOR_047 default_isr // 0x0000_00BC 47 31 CAN0 Error
\r
89 #define VECTOR_048 default_isr // 0x0000_00C0 48 32 CAN0 Transmit Warning
\r
90 #define VECTOR_049 default_isr // 0x0000_00C4 49 33 CAN0 Receive Warning
\r
91 #define VECTOR_050 default_isr // 0x0000_00C8 50 34 CAN0 Wake Up
\r
92 #define VECTOR_051 default_isr // 0x0000_00CC 51 35 CAN0 Individual Matching Elements Update (IMEU)
\r
93 #define VECTOR_052 default_isr // 0x0000_00D0 52 36 CAN0 Lost receive
\r
94 #define VECTOR_053 default_isr // 0x0000_00D4 53 37 CAN1 OR'ed Message buffer (0-15)
\r
95 #define VECTOR_054 default_isr // 0x0000_00D8 54 38 CAN1 Bus off
\r
96 #define VECTOR_055 default_isr // 0x0000_00DC 55 39 CAN1 Error
\r
97 #define VECTOR_056 default_isr // 0x0000_00E0 56 40 CAN1 Transmit Warning
\r
98 #define VECTOR_057 default_isr // 0x0000_00E4 57 41 CAN1 Receive Warning
\r
99 #define VECTOR_058 default_isr // 0x0000_00E8 58 42 CAN1 Wake Up
\r
100 #define VECTOR_059 default_isr // 0x0000_00EC 59 43 CAN1 Individual Matching Elements Update (IMEU)
\r
101 #define VECTOR_060 default_isr // 0x0000_00F0 60 44 CAN1 Lost receive
\r
102 #define VECTOR_061 default_isr // 0x0000_00F4 61 45 UART0 Single interrupt vector for UART status sources
\r
103 #define VECTOR_062 default_isr // 0x0000_00F8 62 46 UART0 Single interrupt vector for UART error sources
\r
104 #define VECTOR_063 default_isr // 0x0000_00FC 63 47 UART1 Single interrupt vector for UART status sources
\r
105 #define VECTOR_064 default_isr // 0x0000_0100 64 48 UART1 Single interrupt vector for UART error sources
\r
106 #define VECTOR_065 default_isr // 0x0000_0104 65 49 UART2 Single interrupt vector for UART status sources
\r
107 #define VECTOR_066 default_isr // 0x0000_0108 66 50 UART2 Single interrupt vector for UART error sources
\r
108 #define VECTOR_067 default_isr // 0x0000_010C 67 51 UART3 Single interrupt vector for UART status sources
\r
109 #define VECTOR_068 default_isr // 0x0000_0110 68 52 UART3 Single interrupt vector for UART error sources
\r
110 #define VECTOR_069 default_isr // 0x0000_0114 69 53 UART4 Single interrupt vector for UART status sources
\r
111 #define VECTOR_070 default_isr // 0x0000_0118 70 54 UART4 Single interrupt vector for UART error sources
\r
112 #define VECTOR_071 default_isr // 0x0000_011C 71 55 UART5 Single interrupt vector for UART status sources
\r
113 #define VECTOR_072 default_isr // 0x0000_0120 72 56 UART5 Single interrupt vector for UART error sources
\r
114 #define VECTOR_073 default_isr // 0x0000_0124 73 57 ADC0
\r
115 #define VECTOR_074 default_isr // 0x0000_0128 74 58 ADC1
\r
116 #define VECTOR_075 default_isr // 0x0000_012C 75 59 CMP0 High-speed comparator
\r
117 #define VECTOR_076 default_isr // 0x0000_0130 76 60 CMP1
\r
118 #define VECTOR_077 default_isr // 0x0000_0134 77 61 CMP2
\r
119 #define VECTOR_078 default_isr // 0x0000_0138 78 62 FTM0 Single interrupt vector for all sources
\r
120 #define VECTOR_079 default_isr // 0x0000_013C 79 63 FTM1 Single interrupt vector for all sources
\r
121 #define VECTOR_080 default_isr // 0x0000_0140 80 64 FTM2 Single interrupt vector for all sources
\r
122 #define VECTOR_081 default_isr // 0x0000_0144 81 65 CMT
\r
123 #define VECTOR_082 default_isr // 0x0000_0148 82 66 RTC Timer interrupt
\r
124 #define VECTOR_083 default_isr // 0x0000_014C 83 67
\r
125 #define VECTOR_084 default_isr // 0x0000_0150 84 68 PIT Channel 0
\r
126 #define VECTOR_085 default_isr // 0x0000_0154 85 69 PIT Channel 1
\r
127 #define VECTOR_086 default_isr // 0x0000_0158 86 70 PIT Channel 2
\r
128 #define VECTOR_087 default_isr // 0x0000_015C 87 71 PIT Channel 3
\r
129 #define VECTOR_088 default_isr // 0x0000_0160 88 72 PDB
\r
130 #define VECTOR_089 default_isr // 0x0000_0164 89 73 USB OTG
\r
131 #define VECTOR_090 default_isr // 0x0000_0168 90 74 USB Charger Detect
\r
132 #define VECTOR_091 default_isr // 0x0000_016C 91 75 ENET IEEE 1588 Timer interrupt
\r
133 #define VECTOR_092 vEMAC_TxISRHandler // 0x0000_0170 92 76 ENET Transmit interrupt
\r
134 #define VECTOR_093 vEMAC_RxISRHandler // 0x0000_0174 93 77 ENET Receive interrupt
\r
135 #define VECTOR_094 vEMAC_ErrorISRHandler // 0x0000_0178 94 78 ENET Error and miscellaneous interrupt
\r
136 #define VECTOR_095 default_isr // 0x0000_017C 95 79 I2S
\r
137 #define VECTOR_096 default_isr // 0x0000_0180 96 80 SDHC
\r
138 #define VECTOR_097 default_isr // 0x0000_0184 97 81 DAC0
\r
139 #define VECTOR_098 default_isr // 0x0000_0188 98 82 DAC1
\r
140 #define VECTOR_099 default_isr // 0x0000_018C 99 83 TSI Single interrupt vector for all sources
\r
141 #define VECTOR_100 default_isr // 0x0000_0190 100 84 MCG
\r
142 #define VECTOR_101 default_isr // 0x0000_0194 101 85 Low Power Timer
\r
143 #define VECTOR_102 default_isr // 0x0000_0198 102 86 Segment LCD Single interrupt vector for all sources
\r
144 #define VECTOR_103 default_isr // 0x0000_019C 103 87 Port control module Pin Detect (Port A)
\r
145 #define VECTOR_104 default_isr // 0x0000_01A0 104 88 Port control module Pin Detect (Port B)
\r
146 #define VECTOR_105 default_isr // 0x0000_01A4 105 89 Port control module Pin Detect (Port C)
\r
147 #define VECTOR_106 default_isr // 0x0000_01A8 106 90 Port control module Pin Detect (Port D)
\r
148 #define VECTOR_107 vPort_E_ISRHandler // 0x0000_01AC 107 91 Port control module Pin Detect (Port E)
\r
149 #define VECTOR_108 default_isr // 0x0000_01B0 108 92
\r
150 #define VECTOR_109 default_isr // 0x0000_01B4 109 93
\r
151 #define VECTOR_110 default_isr // 0x0000_01B8 110 94
\r
152 #define VECTOR_111 default_isr // 0x0000_01BC 111 95
\r
153 #define VECTOR_112 default_isr // 0x0000_01C0 112 96
\r
154 #define VECTOR_113 default_isr // 0x0000_01C4 113 97
\r
155 #define VECTOR_114 default_isr // 0x0000_01C8 114 98
\r
156 #define VECTOR_115 default_isr // 0x0000_01CC 115 99
\r
157 #define VECTOR_116 default_isr // 0x0000_01D0 116 100
\r
158 #define VECTOR_117 default_isr // 0x0000_01D4 117 101
\r
159 #define VECTOR_118 default_isr // 0x0000_01D8 118 102
\r
160 #define VECTOR_119 default_isr // 0x0000_01DC 119 103
\r
161 #define VECTOR_120 default_isr //
\r
162 #define VECTOR_121 default_isr //
\r
163 #define VECTOR_122 default_isr //
\r
164 #define VECTOR_123 default_isr //
\r
165 #define VECTOR_124 default_isr //
\r
166 #define VECTOR_125 default_isr //
\r
167 #define VECTOR_126 default_isr //
\r
168 #define VECTOR_127 default_isr //
\r
169 #define VECTOR_128 default_isr //
\r
170 #define VECTOR_129 default_isr //
\r
171 #define VECTOR_130 default_isr //
\r
172 #define VECTOR_131 default_isr //
\r
173 #define VECTOR_132 default_isr //
\r
174 #define VECTOR_133 default_isr //
\r
175 #define VECTOR_134 default_isr //
\r
176 #define VECTOR_135 default_isr //
\r
177 #define VECTOR_136 default_isr //
\r
178 #define VECTOR_137 default_isr //
\r
179 #define VECTOR_138 default_isr //
\r
180 #define VECTOR_139 default_isr //
\r
181 #define VECTOR_140 default_isr //
\r
182 #define VECTOR_141 default_isr //
\r
183 #define VECTOR_142 default_isr //
\r
184 #define VECTOR_143 default_isr //
\r
185 #define VECTOR_144 default_isr //
\r
186 #define VECTOR_145 default_isr //
\r
187 #define VECTOR_146 default_isr //
\r
188 #define VECTOR_147 default_isr //
\r
189 #define VECTOR_148 default_isr //
\r
190 #define VECTOR_149 default_isr //
\r
191 #define VECTOR_150 default_isr //
\r
192 #define VECTOR_151 default_isr //
\r
193 #define VECTOR_152 default_isr //
\r
194 #define VECTOR_153 default_isr //
\r
195 #define VECTOR_154 default_isr //
\r
196 #define VECTOR_155 default_isr //
\r
197 #define VECTOR_156 default_isr //
\r
198 #define VECTOR_157 default_isr //
\r
199 #define VECTOR_158 default_isr //
\r
200 #define VECTOR_159 default_isr //
\r
201 #define VECTOR_160 default_isr //
\r
202 #define VECTOR_161 default_isr //
\r
203 #define VECTOR_162 default_isr //
\r
204 #define VECTOR_163 default_isr //
\r
205 #define VECTOR_164 default_isr //
\r
206 #define VECTOR_165 default_isr //
\r
207 #define VECTOR_166 default_isr //
\r
208 #define VECTOR_167 default_isr //
\r
209 #define VECTOR_168 default_isr //
\r
210 #define VECTOR_169 default_isr //
\r
211 #define VECTOR_170 default_isr //
\r
212 #define VECTOR_171 default_isr //
\r
213 #define VECTOR_172 default_isr //
\r
214 #define VECTOR_173 default_isr //
\r
215 #define VECTOR_174 default_isr //
\r
216 #define VECTOR_175 default_isr //
\r
217 #define VECTOR_176 default_isr //
\r
218 #define VECTOR_177 default_isr //
\r
219 #define VECTOR_178 default_isr //
\r
220 #define VECTOR_179 default_isr //
\r
221 #define VECTOR_180 default_isr //
\r
222 #define VECTOR_181 default_isr //
\r
223 #define VECTOR_182 default_isr //
\r
224 #define VECTOR_183 default_isr //
\r
225 #define VECTOR_184 default_isr //
\r
226 #define VECTOR_185 default_isr //
\r
227 #define VECTOR_186 default_isr //
\r
228 #define VECTOR_187 default_isr //
\r
229 #define VECTOR_188 default_isr //
\r
230 #define VECTOR_189 default_isr //
\r
231 #define VECTOR_190 default_isr //
\r
232 #define VECTOR_191 default_isr //
\r
233 #define VECTOR_192 default_isr //
\r
234 #define VECTOR_193 default_isr //
\r
235 #define VECTOR_194 default_isr //
\r
236 #define VECTOR_195 default_isr //
\r
237 #define VECTOR_196 default_isr //
\r
238 #define VECTOR_197 default_isr //
\r
239 #define VECTOR_198 default_isr //
\r
240 #define VECTOR_199 default_isr //
\r
241 #define VECTOR_200 default_isr //
\r
242 #define VECTOR_201 default_isr //
\r
243 #define VECTOR_202 default_isr //
\r
244 #define VECTOR_203 default_isr //
\r
245 #define VECTOR_204 default_isr //
\r
246 #define VECTOR_205 default_isr //
\r
247 #define VECTOR_206 default_isr //
\r
248 #define VECTOR_207 default_isr //
\r
249 #define VECTOR_208 default_isr //
\r
250 #define VECTOR_209 default_isr //
\r
251 #define VECTOR_210 default_isr //
\r
252 #define VECTOR_211 default_isr //
\r
253 #define VECTOR_212 default_isr //
\r
254 #define VECTOR_213 default_isr //
\r
255 #define VECTOR_214 default_isr //
\r
256 #define VECTOR_215 default_isr //
\r
257 #define VECTOR_216 default_isr //
\r
258 #define VECTOR_217 default_isr //
\r
259 #define VECTOR_218 default_isr //
\r
260 #define VECTOR_219 default_isr //
\r
261 #define VECTOR_220 default_isr //
\r
262 #define VECTOR_221 default_isr //
\r
263 #define VECTOR_222 default_isr //
\r
264 #define VECTOR_223 default_isr //
\r
265 #define VECTOR_224 default_isr //
\r
266 #define VECTOR_225 default_isr //
\r
267 #define VECTOR_226 default_isr //
\r
268 #define VECTOR_227 default_isr //
\r
269 #define VECTOR_228 default_isr //
\r
270 #define VECTOR_229 default_isr //
\r
271 #define VECTOR_230 default_isr //
\r
272 #define VECTOR_231 default_isr //
\r
273 #define VECTOR_232 default_isr //
\r
274 #define VECTOR_233 default_isr //
\r
275 #define VECTOR_234 default_isr //
\r
276 #define VECTOR_235 default_isr //
\r
277 #define VECTOR_236 default_isr //
\r
278 #define VECTOR_237 default_isr //
\r
279 #define VECTOR_238 default_isr //
\r
280 #define VECTOR_239 default_isr //
\r
281 #define VECTOR_240 default_isr //
\r
282 #define VECTOR_241 default_isr //
\r
283 #define VECTOR_242 default_isr //
\r
284 #define VECTOR_243 default_isr //
\r
285 #define VECTOR_244 default_isr //
\r
286 #define VECTOR_245 default_isr //
\r
287 #define VECTOR_246 default_isr //
\r
288 #define VECTOR_247 default_isr //
\r
289 #define VECTOR_248 default_isr //
\r
290 #define VECTOR_249 default_isr //
\r
291 #define VECTOR_250 default_isr //
\r
292 #define VECTOR_251 default_isr //
\r
293 #define VECTOR_252 default_isr //
\r
294 #define VECTOR_253 default_isr //
\r
295 #define VECTOR_254 default_isr //
\r
296 #define VECTOR_255 default_isr //
\r
297 #define CONFIG_1 (pointer*)0xffffffff
\r
298 #define CONFIG_2 (pointer*)0xffffffff
\r
299 #define CONFIG_3 (pointer*)0xffffffff
\r
300 #define CONFIG_4 (pointer*)0xfffffffe
\r
302 #endif /*__VECTORS_H*/
\r
304 /* End of "vectors.h" */
\r
projects / freertos / blob