1 // ----------------------------------------------------------------------
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3 // Purpose: Definitions for Network Buffer Allocation.
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7 // ----------------------------------------------------------------------
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12 // Define number of MACs
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13 #define NUM_CHANNELS 1/*b06862*/
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15 // Choose Enhanced Buffer Descriptor or Legacy
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18 //b06862: define Endianess for Little Endian architectures like ARM.
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19 //Motorola/Freescale uses Big Endian or Register-Endianess
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20 #define NBUF_LITTLE_ENDIAN
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22 // Transmit packet directly or copy to dedicated buffers. If packets
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23 // are not alligned dedicated Tx buffers can be used
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24 //#define USE_DEDICATED_TX_BUFFERS
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26 // Buffer sizes in bytes (must be divisible by 16)
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27 #define RX_BUFFER_SIZE 256
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28 #define TX_BUFFER_SIZE 256
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30 // Number of Receive and Transmit Buffers and Buffer Descriptors
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31 #define NUM_RXBDS 20//10
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32 #define NUM_TXBDS 20//10
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34 // Buffer Descriptor Format
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38 uint16_t status; /* control and status */
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39 uint16_t length; /* transfer length */
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40 uint8_t *data; /* buffer address */
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41 uint32_t ebd_status;
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42 uint16_t length_proto_type;
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43 uint16_t payload_checksum;
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46 uint32_t reserverd_word1;
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47 uint32_t reserverd_word2;
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52 uint16_t status; /* control and status */
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53 uint16_t length; /* transfer length */
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54 uint8_t *data; /* buffer address */
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56 #endif /* ENHANCED_BD */
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58 // ----------------------------------------------------------------------
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59 // Function Declarations
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60 // ----------------------------------------------------------------------
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75 enet_get_received_packet(int, NBUF *);
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79 enet_fill_txbds(int, NBUF *);
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82 enet_transmit_packet(int,NBUF *);
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84 #ifdef NBUF_LITTLE_ENDIAN
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86 //For Freescale ARM Architecture
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88 // ----------------------------------------------------------------------
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89 // TX Buffer Descriptor Bit Definitions
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90 // ----------------------------------------------------------------------
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91 #define TX_BD_R 0x0080
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92 #define TX_BD_TO1 0x0040
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93 #define TX_BD_W 0x0020
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94 #define TX_BD_TO2 0x0010
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95 #define TX_BD_L 0x0008
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96 #define TX_BD_TC 0x0004
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97 #define TX_BD_ABC 0x0002
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99 // ----------------------------------------------------------------------
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100 // TX Enhanced BD Bit Definitions
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101 // ----------------------------------------------------------------------
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102 #define TX_BD_INT 0x00000040
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103 #define TX_BD_TS 0x00000020
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104 #define TX_BD_PINS 0x00000010
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105 #define TX_BD_IINS 0x00000008
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106 #define TX_BD_TXE 0x00800000
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107 #define TX_BD_UE 0x00200000
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108 #define TX_BD_EE 0x00100000
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109 #define TX_BD_FE 0x00080000
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110 #define TX_BD_LCE 0x00040000
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111 #define TX_BD_OE 0x00020000
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112 #define TX_BD_TSE 0x00010000
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114 #define TX_BD_BDU 0x00000080
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116 // ----------------------------------------------------------------------
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117 // RX Buffer Descriptor Bit Definitions
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118 // ----------------------------------------------------------------------
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120 // Offset 0 flags - status: Big Endian
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121 #define RX_BD_E 0x0080
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122 #define RX_BD_R01 0x0040
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123 #define RX_BD_W 0x0020
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124 #define RX_BD_R02 0x0010
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125 #define RX_BD_L 0x0008
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126 #define RX_BD_M 0x0001
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127 #define RX_BD_BC 0x8000
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128 #define RX_BD_MC 0x4000
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129 #define RX_BD_LG 0x2000
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130 #define RX_BD_NO 0x1000
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131 #define RX_BD_CR 0x0400
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132 #define RX_BD_OV 0x0200
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133 #define RX_BD_TR 0x0100
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135 // ----------------------------------------------------------------------
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136 // RX Enhanced BD Bit Definitions
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137 // ----------------------------------------------------------------------
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138 #define RX_BD_ME 0x00000080
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139 #define RX_BD_PE 0x00000004
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140 #define RX_BD_CE 0x00000002
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141 #define RX_BD_UC 0x00000001
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143 #define RX_BD_INT 0x00008000
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145 #define RX_BD_ICE 0x20000000
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146 #define RX_BD_PCR 0x10000000
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147 #define RX_BD_VLAN 0x04000000
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148 #define RX_BD_IPV6 0x02000000
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149 #define RX_BD_FRAG 0x01000000
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151 #define RX_BD_BDU 0x00000080
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155 //For Freescale ColdFire Architecture
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156 // ----------------------------------------------------------------------
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157 // TX Buffer Descriptor Bit Definitions
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158 // ----------------------------------------------------------------------
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159 #define TX_BD_R 0x8000
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160 #define TX_BD_TO1 0x4000
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161 #define TX_BD_W 0x2000
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162 #define TX_BD_TO2 0x1000
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163 #define TX_BD_L 0x0800
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164 #define TX_BD_TC 0x0400
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165 #define TX_BD_ABC 0x0200
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167 // ----------------------------------------------------------------------
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168 // TX Enhanced BD Bit Definitions
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169 // ----------------------------------------------------------------------
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170 #define TX_BD_INT 0x40000000
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171 #define TX_BD_TS 0x20000000
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172 #define TX_BD_PINS 0x10000000
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173 #define TX_BD_IINS 0x08000000
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174 #define TX_BD_TXE 0x00008000
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175 #define TX_BD_UE 0x00002000
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176 #define TX_BD_EE 0x00001000
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177 #define TX_BD_FE 0x00000800
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178 #define TX_BD_LCE 0x00000400
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179 #define TX_BD_OE 0x00000200
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180 #define TX_BD_TSE 0x00000100
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182 #define TX_BD_BDU 0x80000000
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184 // ----------------------------------------------------------------------
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185 // RX Buffer Descriptor Bit Definitions
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186 // ----------------------------------------------------------------------
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188 // Offset 0 flags - status
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189 #define RX_BD_E 0x8000
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190 #define RX_BD_R01 0x4000
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191 #define RX_BD_W 0x2000
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192 #define RX_BD_R02 0x1000
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193 #define RX_BD_L 0x0800
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194 #define RX_BD_M 0x0100
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195 #define RX_BD_BC 0x0080
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196 #define RX_BD_MC 0x0040
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197 #define RX_BD_LG 0x0020
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198 #define RX_BD_NO 0x0010
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199 #define RX_BD_CR 0x0004
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200 #define RX_BD_OV 0x0002
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201 #define RX_BD_TR 0x0001
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203 // ----------------------------------------------------------------------
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204 // RX Enhanced BD Bit Definitions
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205 // ----------------------------------------------------------------------
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206 #define RX_BD_ME 0x80000000
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207 #define RX_BD_PE 0x04000000
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208 #define RX_BD_CE 0x02000000
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209 #define RX_BD_UC 0x01000000
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210 #define RX_BD_INT 0x00800000
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211 #define RX_BD_ICE 0x00000020
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212 #define RX_BD_PCR 0x00000010
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213 #define RX_BD_VLAN 0x00000004
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214 #define RX_BD_IPV6 0x00000002
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215 #define RX_BD_FRAG 0x00000001
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217 #define RX_BD_BDU 0x80000000
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222 // ----------------------------------------------------------------------
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223 // Defines for word offsets of various fields of RX Enhanced BDs
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224 // ----------------------------------------------------------------------
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225 //#define RX_EBD_HEADER_LENGTH_OFFSET 12
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226 //#define RX_EBD_PROTOCOL_TYPE_OFFSET 12
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227 //#define RX_EBD_PAYLOAD_CHKSM_OFFSET 14
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228 //#define RX_EBD_BDU_OFFSET 16
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229 //#define RX_EBD_TIMESTAMP_MSB_OFFSET 20
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230 //#define RX_EBD_TIMESTAMP_LSB_OFFSET 22
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233 #endif /* _NBUF_H_ */
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