2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Freescale includes. */
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30 #include "eth_phy.h"
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34 /* FreeRTOS includes. */
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35 #include "FreeRTOS.h"
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40 #include "net/uip.h"
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42 /* The time to wait between attempts to obtain a free buffer. */
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43 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_PERIOD_MS )
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45 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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46 up on attempting to obtain a free buffer all together. */
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47 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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49 /* The number of Rx descriptors. */
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50 #define emacNUM_RX_DESCRIPTORS 8
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52 /* The number of Tx descriptors. When using uIP there is not point in having
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54 #define emacNUM_TX_BUFFERS 2
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56 /* The total number of EMAC buffers to allocate. */
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57 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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59 /* The time to wait for the Tx descriptor to become free. */
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60 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_PERIOD_MS )
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62 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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64 #define emacTX_WAIT_ATTEMPTS ( 50 )
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66 /* Constants used for set up and initialisation. */
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67 #define emacTX_INTERRUPT_NO ( 76 )
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68 #define emacRX_INTERRUPT_NO ( 77 )
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69 #define emacERROR_INTERRUPT_NO ( 78 )
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70 #define emacLINK_DELAY ( 500 / portTICK_PERIOD_MS )
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71 #define emacPHY_STATUS ( 0x1F )
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72 #define emacPHY_DUPLEX_STATUS ( 4 << 2 )
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73 #define emacPHY_SPEED_STATUS ( 1 << 2 )
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75 /*-----------------------------------------------------------*/
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78 * Initialise both the Rx and Tx descriptors.
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80 static void prvInitialiseDescriptors( void );
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83 * Return a pointer to a free buffer within xEthernetBuffers.
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85 static unsigned char *prvGetNextBuffer( void );
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88 * Return a buffer to the list of free buffers.
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90 static void prvReturnBuffer( unsigned char *pucBuffer );
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93 * Examine the status of the next Rx descriptor to see if it contains new data.
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95 static unsigned short prvCheckRxStatus( void );
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98 * Something has gone wrong with the descriptor usage. Reset all the buffers
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101 static void prvResetEverything( void );
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103 /*-----------------------------------------------------------*/
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105 /* The buffers and descriptors themselves. */
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106 #pragma data_alignment=16
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107 volatile NBUF xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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109 #pragma data_alignment=16
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110 volatile NBUF xTxDescriptors[ emacNUM_TX_BUFFERS ];
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112 #pragma data_alignment=16
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113 char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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115 /* Used to indicate which buffers are free and which are in use. If an index
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116 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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117 the buffer is in use or about to be used. */
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118 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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120 /* Points to the Rx descriptor currently in use. */
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121 static volatile NBUF *pxCurrentRxDesc = NULL;
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123 /* pxCurrentRxDesc points to descriptor within the xRxDescriptors array that
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124 has an index defined by ulRxDescriptorIndex. */
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125 static unsigned long ulRxDescriptorIndex = 0UL;
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127 /* The buffer used by the uIP stack to both receive and send. This points to
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128 one of the Ethernet buffers when its actually in use. */
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129 unsigned char *uip_buf = NULL;
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131 /*-----------------------------------------------------------*/
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133 void vEMACInit( void )
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136 extern int periph_clk_khz;
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137 const unsigned char ucMACAddress[] =
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139 configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5
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142 /* Enable the ENET clock. */
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143 SIM_SCGC2 |= SIM_SCGC2_ENET_MASK;
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145 /* Allow concurrent access to MPU controller to avoid bus errors. */
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148 prvInitialiseDescriptors();
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150 /* Reset and enable. */
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151 ENET_ECR = ENET_ECR_RESET_MASK;
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153 /* Wait at least 8 clock cycles */
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156 /* Start the MII interface*/
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157 mii_init( 0, periph_clk_khz / 1000L );
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159 /* Configure the transmit interrupt. */
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160 set_irq_priority( emacTX_INTERRUPT_NO, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
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161 enable_irq( emacTX_INTERRUPT_NO );
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163 /* Configure the receive interrupt. */
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164 set_irq_priority( emacRX_INTERRUPT_NO, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
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165 enable_irq( emacRX_INTERRUPT_NO );
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167 /* Configure the error interrupt. */
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168 set_irq_priority( emacERROR_INTERRUPT_NO, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
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169 enable_irq( emacERROR_INTERRUPT_NO );
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171 /* Configure the pins to the PHY - RMII mode used. */
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172 PORTB_PCR0 = PORT_PCR_MUX( 4 ); /* RMII0_MDIO / MII0_MDIO. */
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173 PORTB_PCR1 = PORT_PCR_MUX( 4 ); /* RMII0_MDC / MII0_MDC */
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174 PORTA_PCR14 = PORT_PCR_MUX( 4 ); /* RMII0_CRS_DV / MII0_RXDV */
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175 PORTA_PCR12 = PORT_PCR_MUX( 4 ); /* RMII0_RXD1 / MII0_RXD1 */
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176 PORTA_PCR13 = PORT_PCR_MUX( 4 ); /* RMII0_RXD0/MII0_RXD0 */
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177 PORTA_PCR15 = PORT_PCR_MUX( 4 ); /* RMII0_TXEN/MII0_TXEN */
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178 PORTA_PCR16 = PORT_PCR_MUX( 4 ); /* RMII0_TXD0/MII0_TXD0 */
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179 PORTA_PCR17 = PORT_PCR_MUX( 4 ); /* RMII0_TXD1/MII0_TXD1 */
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181 /* Is there communication with the PHY? */
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184 vTaskDelay( emacLINK_DELAY );
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186 mii_read( 0, configPHY_ADDRESS, PHY_PHYIDR1, &iData );
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188 } while( iData == 0xFFFF );
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190 /* Start to auto negotiate. */
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191 mii_write( 0, configPHY_ADDRESS, PHY_BMCR, ( PHY_BMCR_AN_RESTART | PHY_BMCR_AN_ENABLE ) );
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193 /* Wait for auto negotiate to complete. */
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196 vTaskDelay( emacLINK_DELAY );
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197 mii_read( 0, configPHY_ADDRESS, PHY_BMSR, &iData );
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199 } while( !( iData & PHY_BMSR_AN_COMPLETE ) );
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201 /* A link has been established. What was negotiated? */
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203 mii_read( 0, configPHY_ADDRESS, emacPHY_STATUS, &iData );
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205 /* Clear the Individual and Group Address Hash registers */
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211 /* Set the Physical Address for the selected ENET */
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212 enet_set_address( 0, ucMACAddress );
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214 ENET_RCR = ENET_RCR_MAX_FL( UIP_BUFSIZE ) | ENET_RCR_MII_MODE_MASK | ENET_RCR_CRCFWD_MASK | ENET_RCR_RMII_MODE_MASK;
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216 /* Clear the control registers. */
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219 if( iData & emacPHY_DUPLEX_STATUS )
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222 ENET_RCR &= ( unsigned long )~ENET_RCR_DRT_MASK;
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223 ENET_TCR |= ENET_TCR_FDEN_MASK;
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228 ENET_RCR |= ENET_RCR_DRT_MASK;
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229 ENET_TCR &= (unsigned long)~ENET_TCR_FDEN_MASK;
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232 if( iData & emacPHY_SPEED_STATUS )
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235 ENET_RCR |= ENET_RCR_RMII_10T_MASK;
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238 ENET_ECR = ENET_ECR_EN1588_MASK;
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240 /* Store and forward checksum. */
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241 ENET_TFWR = ENET_TFWR_STRFWD_MASK;
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243 /* Set Rx Buffer Size */
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244 ENET_MRBR = ( unsigned short ) UIP_BUFSIZE;
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246 /* Point to the start of the circular Rx buffer descriptor queue */
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247 ENET_RDSR = ( unsigned long ) &( xRxDescriptors[ 0 ] );
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249 /* Point to the start of the circular Tx buffer descriptor queue */
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250 ENET_TDSR = ( unsigned long ) &( xTxDescriptors[ 0 ] );
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252 /* Clear all ENET interrupt events */
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253 ENET_EIR = ( unsigned long ) -1;
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255 /* Enable interrupts. */
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258 | ENET_EIMR_RXF_MASK/* only for complete frame, not partial buffer descriptor | ENET_EIMR_RXB_MASK*/
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260 | ENET_EIMR_TXF_MASK/* only for complete frame, not partial buffer descriptor | ENET_EIMR_TXB_MASK*/
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262 | ENET_EIMR_UN_MASK | ENET_EIMR_RL_MASK | ENET_EIMR_LC_MASK | ENET_EIMR_BABT_MASK | ENET_EIMR_BABR_MASK | ENET_EIMR_EBERR_MASK
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265 /* Enable the MAC itself. */
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266 ENET_ECR |= ENET_ECR_ETHEREN_MASK;
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268 /* Indicate that there have been empty receive buffers produced */
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269 ENET_RDAR = ENET_RDAR_RDAR_MASK;
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271 /*-----------------------------------------------------------*/
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273 static void prvInitialiseDescriptors( void )
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275 volatile NBUF *pxDescriptor;
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278 for( x = 0; x < emacNUM_BUFFERS; x++ )
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280 /* Ensure none of the buffers are shown as in use at the start. */
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281 ucBufferInUse[ x ] = pdFALSE;
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284 /* Initialise the Rx descriptors. */
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285 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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287 pxDescriptor = &( xRxDescriptors[ x ] );
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288 pxDescriptor->data = ( uint8_t* ) &( xEthernetBuffers[ x ][ 0 ] );
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289 pxDescriptor->data = ( uint8_t* ) __REV( ( unsigned long ) pxDescriptor->data );
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290 pxDescriptor->length = 0;
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291 pxDescriptor->status = RX_BD_E;
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292 pxDescriptor->bdu = 0;
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293 pxDescriptor->ebd_status = RX_BD_INT;
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295 /* Mark this buffer as in use. */
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296 ucBufferInUse[ x ] = pdTRUE;
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299 /* The last descriptor points back to the start. */
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300 pxDescriptor->status |= RX_BD_W;
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302 /* Initialise the Tx descriptors. */
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303 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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305 pxDescriptor = &( xTxDescriptors[ x ] );
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307 /* A buffer is not allocated to the Tx descriptor until a send is
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308 actually required. */
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309 pxDescriptor->data = NULL;
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310 pxDescriptor->length = 0;
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311 pxDescriptor->status = TX_BD_TC;
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312 pxDescriptor->ebd_status = TX_BD_INT;
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315 /* The last descriptor points back to the start. */
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316 pxDescriptor->status |= TX_BD_W;
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318 /* Use the first Rx descriptor to start with. */
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319 ulRxDescriptorIndex = 0UL;
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320 pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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322 /*-----------------------------------------------------------*/
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324 void vEMACWrite( void )
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328 /* Wait until the second transmission of the last packet has completed. */
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329 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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331 if( ( xTxDescriptors[ 1 ].status & TX_BD_R ) != 0 )
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333 /* Descriptor is still active. */
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334 vTaskDelay( emacTX_WAIT_DELAY_ms );
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342 /* Is the descriptor free after waiting for it? */
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343 if( ( xTxDescriptors[ 1 ].status & TX_BD_R ) != 0 )
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345 /* Something has gone wrong. */
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346 prvResetEverything();
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349 /* Setup both descriptors to transmit the frame. */
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350 xTxDescriptors[ 0 ].data = ( uint8_t * ) __REV( ( unsigned long ) uip_buf );
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351 xTxDescriptors[ 0 ].length = __REVSH( uip_len );
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352 xTxDescriptors[ 1 ].data = ( uint8_t * ) __REV( ( unsigned long ) uip_buf );
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353 xTxDescriptors[ 1 ].length = __REVSH( uip_len );
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355 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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356 for use by the stack. */
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357 uip_buf = prvGetNextBuffer();
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359 /* Clear previous settings and go. */
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360 xTxDescriptors[ 0 ].status |= ( TX_BD_R | TX_BD_L );
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361 xTxDescriptors[ 1 ].status |= ( TX_BD_R | TX_BD_L );
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363 /* Start the Tx. */
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364 ENET_TDAR = ENET_TDAR_TDAR_MASK;
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366 /*-----------------------------------------------------------*/
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368 static unsigned char *prvGetNextBuffer( void )
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371 unsigned char *pucReturn = NULL;
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372 unsigned long ulAttempts = 0;
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374 while( pucReturn == NULL )
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376 /* Look through the buffers to find one that is not in use by
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378 for( x = 0; x < emacNUM_BUFFERS; x++ )
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380 if( ucBufferInUse[ x ] == pdFALSE )
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382 ucBufferInUse[ x ] = pdTRUE;
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383 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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388 /* Was a buffer found? */
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389 if( pucReturn == NULL )
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393 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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398 /* Wait then look again. */
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399 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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405 /*-----------------------------------------------------------*/
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407 static void prvResetEverything( void )
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409 /* Temporary code just to see if this gets called. This function has not
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410 been implemented. */
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411 portDISABLE_INTERRUPTS();
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414 /*-----------------------------------------------------------*/
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416 unsigned short usEMACRead( void )
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418 unsigned short usBytesReceived;
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420 usBytesReceived = prvCheckRxStatus();
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421 usBytesReceived = __REVSH( usBytesReceived );
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423 if( usBytesReceived > 0 )
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425 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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426 the buffer that contains the received data. */
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427 prvReturnBuffer( uip_buf );
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429 /* Point uip_buf to the data about to be processed. */
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430 uip_buf = ( void * ) pxCurrentRxDesc->data;
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431 uip_buf = ( void * ) __REV( ( unsigned long ) uip_buf );
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433 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
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435 pxCurrentRxDesc->data = ( uint8_t * ) prvGetNextBuffer();
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436 pxCurrentRxDesc->data = ( uint8_t* ) __REV( ( unsigned long ) pxCurrentRxDesc->data );
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438 /* Prepare the descriptor to go again. */
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439 pxCurrentRxDesc->status |= RX_BD_E;
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441 /* Move onto the next buffer in the ring. */
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442 ulRxDescriptorIndex++;
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443 if( ulRxDescriptorIndex >= emacNUM_RX_DESCRIPTORS )
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445 ulRxDescriptorIndex = 0UL;
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447 pxCurrentRxDesc = &( xRxDescriptors[ ulRxDescriptorIndex ] );
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449 /* Restart Ethernet if it has stopped */
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450 ENET_RDAR = ENET_RDAR_RDAR_MASK;
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453 return usBytesReceived;
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455 /*-----------------------------------------------------------*/
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457 static void prvReturnBuffer( unsigned char *pucBuffer )
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461 /* Return a buffer to the pool of free buffers. */
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462 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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464 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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466 ucBufferInUse[ ul ] = pdFALSE;
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471 /*-----------------------------------------------------------*/
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473 static unsigned short prvCheckRxStatus( void )
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475 unsigned long usReturn = 0;
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477 if( ( pxCurrentRxDesc->status & RX_BD_E ) != 0 )
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479 /* Current descriptor is still active. */
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483 /* The descriptor contains a frame. Because of the size of the buffers
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484 the frame should always be complete. */
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485 usReturn = pxCurrentRxDesc->length;
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490 /*-----------------------------------------------------------*/
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492 void vEMAC_TxISRHandler( void )
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494 /* Clear the interrupt. */
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495 ENET_EIR = ENET_EIR_TXF_MASK;
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497 /* Check the buffers have not already been freed in the first of the
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498 two Tx interrupts - which could potentially happen if the second Tx completed
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499 during the interrupt for the first Tx. */
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500 if( xTxDescriptors[ 0 ].data != NULL )
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502 if( ( ( xTxDescriptors[ 0 ].status & TX_BD_R ) == 0 ) && ( ( xTxDescriptors[ 0 ].status & TX_BD_R ) == 0 ) )
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504 configASSERT( xTxDescriptors[ 0 ].data == xTxDescriptors[ 1 ].data );
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506 xTxDescriptors[ 0 ].data = ( uint8_t* ) __REV( ( unsigned long ) xTxDescriptors[ 0 ].data );
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507 prvReturnBuffer( xTxDescriptors[ 0 ].data );
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509 /* Just to mark the fact that the buffer has already been released. */
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510 xTxDescriptors[ 0 ].data = NULL;
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514 /*-----------------------------------------------------------*/
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516 void vEMAC_RxISRHandler( void )
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518 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
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519 long lHigherPriorityTaskWoken = pdFALSE;
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520 extern QueueHandle_t xEMACEventQueue;
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522 /* Clear the interrupt. */
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523 ENET_EIR = ENET_EIR_RXF_MASK;
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525 /* An Ethernet Rx event has occurred. */
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526 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
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527 portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
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529 /*-----------------------------------------------------------*/
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531 void vEMAC_ErrorISRHandler( void )
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533 /* Clear the interrupt. */
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534 ENET_EIR = ENET_EIR & ENET_EIMR;
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536 /* Attempt recovery. Not very sophisticated. */
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537 prvInitialiseDescriptors();
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538 ENET_RDAR = ENET_RDAR_RDAR_MASK;
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540 /*-----------------------------------------------------------*/
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