1 //*****************************************************************************
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3 // sysctl.c - Driver for the system controller.
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5 // Copyright (c) 2005,2006 Luminary Micro, Inc. ALl rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's Stellaris Family of microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 991 of the Stellaris Driver Library.
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26 //*****************************************************************************
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28 //*****************************************************************************
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30 //! \addtogroup sysctl_api
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33 //*****************************************************************************
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35 #include "../hw_ints.h"
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36 #include "../hw_memmap.h"
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37 #include "../hw_nvic.h"
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38 #include "../hw_sysctl.h"
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39 #include "../hw_types.h"
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42 #include "interrupt.h"
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45 //*****************************************************************************
\r
47 // An array that maps the "peripheral set" number (which is stored in the upper
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48 // nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that
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49 // contains the peripheral present bit for that peripheral.
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51 //*****************************************************************************
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52 #if defined(GROUP_puldcregs) || defined(BUILD_ALL)
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53 const unsigned long g_pulDCRegs[] =
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61 extern const unsigned long g_pulDCRegs[];
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64 //*****************************************************************************
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66 // An array that maps the "peripheral set" number (which is stored in the upper
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67 // nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that
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68 // controls the software reset for that peripheral.
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70 //*****************************************************************************
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71 #if defined(GROUP_pulsrcrregs) || defined(BUILD_ALL)
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72 const unsigned long g_pulSRCRRegs[] =
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79 extern const unsigned long g_pulSRCRRegs[];
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82 //*****************************************************************************
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84 // An array that maps the "peripheral set" number (which is stored in the upper
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85 // nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that
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86 // controls the run-mode enable for that peripheral.
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88 //*****************************************************************************
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89 #if defined(GROUP_pulrcgcregs) || defined(BUILD_ALL)
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90 const unsigned long g_pulRCGCRegs[] =
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97 extern const unsigned long g_pulRCGCRegs[];
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100 //*****************************************************************************
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102 // An array that maps the "peripheral set" number (which is stored in the upper
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103 // nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that
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104 // controls the sleep-mode enable for that peripheral.
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106 //*****************************************************************************
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107 #if defined(GROUP_pulscgcregs) || defined(BUILD_ALL)
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108 const unsigned long g_pulSCGCRegs[] =
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115 extern const unsigned long g_pulSCGCRegs[];
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118 //*****************************************************************************
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120 // An array that maps the "peripheral set" number (which is stored in the upper
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121 // nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that
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122 // controls the deep-sleep-mode enable for that peripheral.
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124 //*****************************************************************************
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125 #if defined(GROUP_pulDCGCregs) || defined(BUILD_ALL)
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126 const unsigned long g_pulDCGCRegs[] =
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133 extern const unsigned long g_pulDCGCRegs[];
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136 //*****************************************************************************
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138 // An array that maps the crystal number in RCC to a frequency.
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140 //*****************************************************************************
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141 #if defined(GROUP_pulxtals) || defined(BUILD_ALL)
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142 const unsigned long g_pulXtals[] =
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158 extern const unsigned long g_pulXtals[];
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161 //*****************************************************************************
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163 //! Gets the size of the SRAM.
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165 //! This function determines the size of the SRAM on the Stellaris device.
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167 //! \return The total number of bytes of SRAM.
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169 //*****************************************************************************
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170 #if defined(GROUP_sramsizeget) || defined(BUILD_ALL) || defined(DOXYGEN)
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172 SysCtlSRAMSizeGet(void)
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175 // Compute the size of the SRAM.
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177 return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_MASK) >> 8) + 0x100);
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181 //*****************************************************************************
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183 //! Gets the size of the flash.
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185 //! This function determines the size of the flash on the Stellaris device.
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187 //! \return The total number of bytes of flash.
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189 //*****************************************************************************
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190 #if defined(GROUP_flashsizeget) || defined(BUILD_ALL) || defined(DOXYGEN)
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192 SysCtlFlashSizeGet(void)
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195 // Compute the size of the flash.
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197 return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_MASK) << 11) + 0x800);
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201 //*****************************************************************************
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203 //! Determines if a pin is present.
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205 //! \param ulPin is the pin in question.
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207 //! Determines if a particular pin is present in the device. The PWM, analog
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208 //! comparators, ADC, and timers have a varying number of pins across members
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209 //! of the Stellaris family; this will determine which are present on this
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212 //! The \b ulPin argument must be only one of the following values:
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213 //! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2,
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214 //! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5,
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215 //! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O,
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216 //! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O,
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217 //! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O,
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218 //! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2,
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219 //! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5,
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220 //! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0,
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221 //! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3,
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222 //! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, or \b SYSCTL_PIN_32KHZ.
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224 //! \return Returns \b true if the specified pin is present and \b false if it
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227 //*****************************************************************************
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228 #if defined(GROUP_pinpresent) || defined(BUILD_ALL) || defined(DOXYGEN)
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230 SysCtlPinPresent(unsigned long ulPin)
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233 // Check the arguments.
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235 ASSERT((ulPin == SYSCTL_PIN_PWM0) ||
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236 (ulPin == SYSCTL_PIN_PWM1) ||
\r
237 (ulPin == SYSCTL_PIN_PWM2) ||
\r
238 (ulPin == SYSCTL_PIN_PWM3) ||
\r
239 (ulPin == SYSCTL_PIN_PWM4) ||
\r
240 (ulPin == SYSCTL_PIN_PWM5) ||
\r
241 (ulPin == SYSCTL_PIN_C0MINUS) ||
\r
242 (ulPin == SYSCTL_PIN_C0PLUS) ||
\r
243 (ulPin == SYSCTL_PIN_C0O) ||
\r
244 (ulPin == SYSCTL_PIN_C1MINUS) ||
\r
245 (ulPin == SYSCTL_PIN_C1PLUS) ||
\r
246 (ulPin == SYSCTL_PIN_C1O) ||
\r
247 (ulPin == SYSCTL_PIN_C2MINUS) ||
\r
248 (ulPin == SYSCTL_PIN_C2PLUS) ||
\r
249 (ulPin == SYSCTL_PIN_C2O) ||
\r
250 (ulPin == SYSCTL_PIN_ADC0) ||
\r
251 (ulPin == SYSCTL_PIN_ADC1) ||
\r
252 (ulPin == SYSCTL_PIN_ADC2) ||
\r
253 (ulPin == SYSCTL_PIN_ADC3) ||
\r
254 (ulPin == SYSCTL_PIN_ADC4) ||
\r
255 (ulPin == SYSCTL_PIN_ADC5) ||
\r
256 (ulPin == SYSCTL_PIN_ADC6) ||
\r
257 (ulPin == SYSCTL_PIN_ADC7) ||
\r
258 (ulPin == SYSCTL_PIN_CCP0) ||
\r
259 (ulPin == SYSCTL_PIN_CCP1) ||
\r
260 (ulPin == SYSCTL_PIN_CCP2) ||
\r
261 (ulPin == SYSCTL_PIN_CCP3) ||
\r
262 (ulPin == SYSCTL_PIN_CCP4) ||
\r
263 (ulPin == SYSCTL_PIN_CCP5) ||
\r
264 (ulPin == SYSCTL_PIN_32KHZ))
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267 // Determine if this pin is present.
\r
269 if(HWREG(SYSCTL_DC3) & ulPin)
\r
280 //*****************************************************************************
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282 //! Determines if a peripheral is present.
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284 //! \param ulPeripheral is the peripheral in question.
\r
286 //! Determines if a particular peripheral is present in the device. Each
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287 //! member of the Stellaris family has a different peripheral set; this will
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288 //! determine which are present on this device.
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290 //! The \b ulPeripheral argument must be only one of the following values:
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291 //! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,
\r
292 //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,
\r
293 //! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,
\r
294 //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,
\r
295 //! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,
\r
296 //! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
\r
297 //! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_TEMP, or
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298 //! \b SYSCTL_PERIPH_PLL.
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300 //! \return Returns \b true if the specified peripheral is present and \b false
\r
303 //*****************************************************************************
\r
304 #if defined(GROUP_peripheralpresent) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
306 SysCtlPeripheralPresent(unsigned long ulPeripheral)
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309 // Check the arguments.
\r
311 ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||
\r
312 (ulPeripheral == SYSCTL_PERIPH_ADC) ||
\r
313 (ulPeripheral == SYSCTL_PERIPH_WDOG) ||
\r
314 (ulPeripheral == SYSCTL_PERIPH_UART0) ||
\r
315 (ulPeripheral == SYSCTL_PERIPH_UART1) ||
\r
316 (ulPeripheral == SYSCTL_PERIPH_SSI) ||
\r
317 (ulPeripheral == SYSCTL_PERIPH_QEI) ||
\r
318 (ulPeripheral == SYSCTL_PERIPH_I2C) ||
\r
319 (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||
\r
320 (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||
\r
321 (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||
\r
322 (ulPeripheral == SYSCTL_PERIPH_COMP0) ||
\r
323 (ulPeripheral == SYSCTL_PERIPH_COMP1) ||
\r
324 (ulPeripheral == SYSCTL_PERIPH_COMP2) ||
\r
325 (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
\r
326 (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
\r
327 (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||
\r
328 (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||
\r
329 (ulPeripheral == SYSCTL_PERIPH_GPIOE) ||
\r
330 (ulPeripheral == SYSCTL_PERIPH_MPU) ||
\r
331 (ulPeripheral == SYSCTL_PERIPH_TEMP) ||
\r
332 (ulPeripheral == SYSCTL_PERIPH_PLL));
\r
335 // Read the correct DC register and determine if this peripheral exists.
\r
337 if(HWREG(g_pulDCRegs[ulPeripheral >> 28]) & ulPeripheral & 0x0fffffff)
\r
348 //*****************************************************************************
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350 //! Performs a software reset of a peripheral.
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352 //! \param ulPeripheral is the peripheral to reset.
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354 //! This function performs a software reset of the specified peripheral. An
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355 //! individual peripheral reset signal is asserted for a brief period and then
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356 //! deasserted, leaving the peripheral in a operating state but in its reset
\r
359 //! The \b ulPeripheral argument must be only one of the following values:
\r
360 //! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,
\r
361 //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,
\r
362 //! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,
\r
363 //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,
\r
364 //! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,
\r
365 //! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or
\r
366 //! \b SYSCTL_PERIPH_GPIOE.
\r
370 //*****************************************************************************
\r
371 #if defined(GROUP_peripheralreset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
373 SysCtlPeripheralReset(unsigned long ulPeripheral)
\r
375 volatile unsigned long ulDelay;
\r
378 // Check the arguments.
\r
380 ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||
\r
381 (ulPeripheral == SYSCTL_PERIPH_ADC) ||
\r
382 (ulPeripheral == SYSCTL_PERIPH_WDOG) ||
\r
383 (ulPeripheral == SYSCTL_PERIPH_UART0) ||
\r
384 (ulPeripheral == SYSCTL_PERIPH_UART1) ||
\r
385 (ulPeripheral == SYSCTL_PERIPH_SSI) ||
\r
386 (ulPeripheral == SYSCTL_PERIPH_QEI) ||
\r
387 (ulPeripheral == SYSCTL_PERIPH_I2C) ||
\r
388 (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||
\r
389 (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||
\r
390 (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||
\r
391 (ulPeripheral == SYSCTL_PERIPH_COMP0) ||
\r
392 (ulPeripheral == SYSCTL_PERIPH_COMP1) ||
\r
393 (ulPeripheral == SYSCTL_PERIPH_COMP2) ||
\r
394 (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
\r
395 (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
\r
396 (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||
\r
397 (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||
\r
398 (ulPeripheral == SYSCTL_PERIPH_GPIOE));
\r
401 // Put the peripheral into the reset state.
\r
403 HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff;
\r
406 // Delay for a little bit.
\r
408 for(ulDelay = 0; ulDelay < 16; ulDelay++)
\r
413 // Take the peripheral out of the reset state.
\r
415 HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) &= ~(ulPeripheral);
\r
419 //*****************************************************************************
\r
421 //! Enables a peripheral.
\r
423 //! \param ulPeripheral is the peripheral to enable.
\r
425 //! Peripherals are enabled with this function. At power-up, all peripherals
\r
426 //! are disabled; they must be enabled in order to operate or respond to
\r
427 //! register reads/writes.
\r
429 //! The \b ulPeripheral argument must be only one of the following values:
\r
430 //! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,
\r
431 //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,
\r
432 //! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,
\r
433 //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,
\r
434 //! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,
\r
435 //! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or
\r
436 //! \b SYSCTL_PERIPH_GPIOE.
\r
440 //*****************************************************************************
\r
441 #if defined(GROUP_peripheralenable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
443 SysCtlPeripheralEnable(unsigned long ulPeripheral)
\r
446 // Check the arguments.
\r
448 ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||
\r
449 (ulPeripheral == SYSCTL_PERIPH_ADC) ||
\r
450 (ulPeripheral == SYSCTL_PERIPH_WDOG) ||
\r
451 (ulPeripheral == SYSCTL_PERIPH_UART0) ||
\r
452 (ulPeripheral == SYSCTL_PERIPH_UART1) ||
\r
453 (ulPeripheral == SYSCTL_PERIPH_SSI) ||
\r
454 (ulPeripheral == SYSCTL_PERIPH_QEI) ||
\r
455 (ulPeripheral == SYSCTL_PERIPH_I2C) ||
\r
456 (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||
\r
457 (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||
\r
458 (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||
\r
459 (ulPeripheral == SYSCTL_PERIPH_COMP0) ||
\r
460 (ulPeripheral == SYSCTL_PERIPH_COMP1) ||
\r
461 (ulPeripheral == SYSCTL_PERIPH_COMP2) ||
\r
462 (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
\r
463 (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
\r
464 (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||
\r
465 (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||
\r
466 (ulPeripheral == SYSCTL_PERIPH_GPIOE));
\r
469 // Enable this peripheral.
\r
471 HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff;
\r
475 //*****************************************************************************
\r
477 //! Disables a peripheral.
\r
479 //! \param ulPeripheral is the peripheral to disable.
\r
481 //! Peripherals are disabled with this function. Once disabled, they will not
\r
482 //! operate or respond to register reads/writes.
\r
484 //! The \b ulPeripheral argument must be only one of the following values:
\r
485 //! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,
\r
486 //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,
\r
487 //! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,
\r
488 //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,
\r
489 //! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,
\r
490 //! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or
\r
491 //! \b SYSCTL_PERIPH_GPIOE.
\r
495 //*****************************************************************************
\r
496 #if defined(GROUP_peripheraldisable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
498 SysCtlPeripheralDisable(unsigned long ulPeripheral)
\r
501 // Check the arguments.
\r
503 ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||
\r
504 (ulPeripheral == SYSCTL_PERIPH_ADC) ||
\r
505 (ulPeripheral == SYSCTL_PERIPH_WDOG) ||
\r
506 (ulPeripheral == SYSCTL_PERIPH_UART0) ||
\r
507 (ulPeripheral == SYSCTL_PERIPH_UART1) ||
\r
508 (ulPeripheral == SYSCTL_PERIPH_SSI) ||
\r
509 (ulPeripheral == SYSCTL_PERIPH_QEI) ||
\r
510 (ulPeripheral == SYSCTL_PERIPH_I2C) ||
\r
511 (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||
\r
512 (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||
\r
513 (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||
\r
514 (ulPeripheral == SYSCTL_PERIPH_COMP0) ||
\r
515 (ulPeripheral == SYSCTL_PERIPH_COMP1) ||
\r
516 (ulPeripheral == SYSCTL_PERIPH_COMP2) ||
\r
517 (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
\r
518 (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
\r
519 (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||
\r
520 (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||
\r
521 (ulPeripheral == SYSCTL_PERIPH_GPIOE));
\r
524 // Disable this peripheral.
\r
526 HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff);
\r
530 //*****************************************************************************
\r
532 //! Enables a peripheral in sleep mode.
\r
534 //! \param ulPeripheral is the peripheral to enable in sleep mode.
\r
536 //! This function allows a peripheral to continue operating when the processor
\r
537 //! goes into sleep mode. Since the clocking configuration of the device does
\r
538 //! not change, any peripheral can safely continue operating while the
\r
539 //! processor is in sleep mode, and can therefore wake the processor from sleep
\r
542 //! Sleep mode clocking of peripherals must be enabled via
\r
543 //! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
\r
544 //! configuration is maintained but has no effect when sleep mode is entered.
\r
546 //! The \b ulPeripheral argument must be only one of the following values:
\r
547 //! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,
\r
548 //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,
\r
549 //! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,
\r
550 //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,
\r
551 //! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,
\r
552 //! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or
\r
553 //! \b SYSCTL_PERIPH_GPIOE.
\r
557 //*****************************************************************************
\r
558 #if defined(GROUP_peripheralsleepenable) || defined(BUILD_ALL) || \
\r
561 SysCtlPeripheralSleepEnable(unsigned long ulPeripheral)
\r
564 // Check the arguments.
\r
566 ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||
\r
567 (ulPeripheral == SYSCTL_PERIPH_ADC) ||
\r
568 (ulPeripheral == SYSCTL_PERIPH_WDOG) ||
\r
569 (ulPeripheral == SYSCTL_PERIPH_UART0) ||
\r
570 (ulPeripheral == SYSCTL_PERIPH_UART1) ||
\r
571 (ulPeripheral == SYSCTL_PERIPH_SSI) ||
\r
572 (ulPeripheral == SYSCTL_PERIPH_QEI) ||
\r
573 (ulPeripheral == SYSCTL_PERIPH_I2C) ||
\r
574 (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||
\r
575 (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||
\r
576 (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||
\r
577 (ulPeripheral == SYSCTL_PERIPH_COMP0) ||
\r
578 (ulPeripheral == SYSCTL_PERIPH_COMP1) ||
\r
579 (ulPeripheral == SYSCTL_PERIPH_COMP2) ||
\r
580 (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
\r
581 (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
\r
582 (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||
\r
583 (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||
\r
584 (ulPeripheral == SYSCTL_PERIPH_GPIOE));
\r
587 // Enable this peripheral in sleep mode.
\r
589 HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff;
\r
593 //*****************************************************************************
\r
595 //! Disables a peripheral in sleep mode.
\r
597 //! \param ulPeripheral is the peripheral to disable in sleep mode.
\r
599 //! This function causes a peripheral to stop operating when the processor goes
\r
600 //! into sleep mode. Disabling peripherals while in sleep mode helps to lower
\r
601 //! the current draw of the device. If enabled (via SysCtlPeripheralEnable()),
\r
602 //! the peripheral will automatically resume operation when the processor
\r
603 //! leaves sleep mode, maintaining its entire state from before sleep mode was
\r
606 //! Sleep mode clocking of peripherals must be enabled via
\r
607 //! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
\r
608 //! configuration is maintained but has no effect when sleep mode is entered.
\r
610 //! The \b ulPeripheral argument must be only one of the following values:
\r
611 //! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,
\r
612 //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,
\r
613 //! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,
\r
614 //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,
\r
615 //! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,
\r
616 //! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or
\r
617 //! \b SYSCTL_PERIPH_GPIOE.
\r
621 //*****************************************************************************
\r
622 #if defined(GROUP_peripheralsleepdisable) || defined(BUILD_ALL) || \
\r
625 SysCtlPeripheralSleepDisable(unsigned long ulPeripheral)
\r
628 // Check the arguments.
\r
630 ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||
\r
631 (ulPeripheral == SYSCTL_PERIPH_ADC) ||
\r
632 (ulPeripheral == SYSCTL_PERIPH_WDOG) ||
\r
633 (ulPeripheral == SYSCTL_PERIPH_UART0) ||
\r
634 (ulPeripheral == SYSCTL_PERIPH_UART1) ||
\r
635 (ulPeripheral == SYSCTL_PERIPH_SSI) ||
\r
636 (ulPeripheral == SYSCTL_PERIPH_QEI) ||
\r
637 (ulPeripheral == SYSCTL_PERIPH_I2C) ||
\r
638 (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||
\r
639 (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||
\r
640 (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||
\r
641 (ulPeripheral == SYSCTL_PERIPH_COMP0) ||
\r
642 (ulPeripheral == SYSCTL_PERIPH_COMP1) ||
\r
643 (ulPeripheral == SYSCTL_PERIPH_COMP2) ||
\r
644 (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
\r
645 (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
\r
646 (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||
\r
647 (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||
\r
648 (ulPeripheral == SYSCTL_PERIPH_GPIOE));
\r
651 // Disable this peripheral in sleep mode.
\r
653 HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff);
\r
657 //*****************************************************************************
\r
659 //! Enables a peripheral in deep-sleep mode.
\r
661 //! \param ulPeripheral is the peripheral to enable in deep-sleep mode.
\r
663 //! This function allows a peripheral to continue operating when the processor
\r
664 //! goes into deep-sleep mode. Since the clocking configuration of the device
\r
665 //! may change, not all peripherals can safely continue operating while the
\r
666 //! processor is in sleep mode. Those that must run at a particular frequency
\r
667 //! (such as a UART) will not work as expected if the clock changes. It is the
\r
668 //! responsibility of the caller to make sensible choices.
\r
670 //! Deep-sleep mode clocking of peripherals must be enabled via
\r
671 //! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
\r
672 //! configuration is maintained but has no effect when deep-sleep mode is
\r
675 //! The \b ulPeripheral argument must be one of the following values:
\r
676 //! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,
\r
677 //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,
\r
678 //! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,
\r
679 //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,
\r
680 //! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,
\r
681 //! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or
\r
682 //! \b SYSCTL_PERIPH_GPIOE.
\r
686 //*****************************************************************************
\r
687 #if defined(GROUP_peripheraldeepsleepenable) || defined(BUILD_ALL) || \
\r
690 SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral)
\r
693 // Check the arguments.
\r
695 ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||
\r
696 (ulPeripheral == SYSCTL_PERIPH_ADC) ||
\r
697 (ulPeripheral == SYSCTL_PERIPH_WDOG) ||
\r
698 (ulPeripheral == SYSCTL_PERIPH_UART0) ||
\r
699 (ulPeripheral == SYSCTL_PERIPH_UART1) ||
\r
700 (ulPeripheral == SYSCTL_PERIPH_SSI) ||
\r
701 (ulPeripheral == SYSCTL_PERIPH_QEI) ||
\r
702 (ulPeripheral == SYSCTL_PERIPH_I2C) ||
\r
703 (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||
\r
704 (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||
\r
705 (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||
\r
706 (ulPeripheral == SYSCTL_PERIPH_COMP0) ||
\r
707 (ulPeripheral == SYSCTL_PERIPH_COMP1) ||
\r
708 (ulPeripheral == SYSCTL_PERIPH_COMP2) ||
\r
709 (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
\r
710 (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
\r
711 (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||
\r
712 (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||
\r
713 (ulPeripheral == SYSCTL_PERIPH_GPIOE));
\r
716 // Enable this peripheral in deep-sleep mode.
\r
718 HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff;
\r
722 //*****************************************************************************
\r
724 //! Disables a peripheral in deep-sleep mode.
\r
726 //! \param ulPeripheral is the peripheral to disable in deep-sleep mode.
\r
728 //! This function causes a peripheral to stop operating when the processor goes
\r
729 //! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps
\r
730 //! to lower the current draw of the device, and can keep peripherals that
\r
731 //! require a particular clock frequency from operating when the clock changes
\r
732 //! as a result of entering deep-sleep mode. If enabled (via
\r
733 //! SysCtlPeripheralEnable()), the peripheral will automatically resume
\r
734 //! operation when the processor leaves deep-sleep mode, maintaining its entire
\r
735 //! state from before deep-sleep mode was entered.
\r
737 //! Deep-sleep mode clocking of peripherals must be enabled via
\r
738 //! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
\r
739 //! configuration is maintained but has no effect when deep-sleep mode is
\r
742 //! The \b ulPeripheral argument must be one of the following values:
\r
743 //! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG,
\r
744 //! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI,
\r
745 //! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0,
\r
746 //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0,
\r
747 //! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA,
\r
748 //! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or
\r
749 //! \b SYSCTL_PERIPH_GPIOE.
\r
753 //*****************************************************************************
\r
754 #if defined(GROUP_peripheraldeepsleepdisable) || defined(BUILD_ALL) || \
\r
757 SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral)
\r
760 // Check the arguments.
\r
762 ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) ||
\r
763 (ulPeripheral == SYSCTL_PERIPH_ADC) ||
\r
764 (ulPeripheral == SYSCTL_PERIPH_WDOG) ||
\r
765 (ulPeripheral == SYSCTL_PERIPH_UART0) ||
\r
766 (ulPeripheral == SYSCTL_PERIPH_UART1) ||
\r
767 (ulPeripheral == SYSCTL_PERIPH_SSI) ||
\r
768 (ulPeripheral == SYSCTL_PERIPH_QEI) ||
\r
769 (ulPeripheral == SYSCTL_PERIPH_I2C) ||
\r
770 (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||
\r
771 (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||
\r
772 (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||
\r
773 (ulPeripheral == SYSCTL_PERIPH_COMP0) ||
\r
774 (ulPeripheral == SYSCTL_PERIPH_COMP1) ||
\r
775 (ulPeripheral == SYSCTL_PERIPH_COMP2) ||
\r
776 (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
\r
777 (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
\r
778 (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||
\r
779 (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||
\r
780 (ulPeripheral == SYSCTL_PERIPH_GPIOE));
\r
783 // Disable this peripheral in deep-sleep mode.
\r
785 HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff);
\r
789 //*****************************************************************************
\r
791 //! Controls peripheral clock gating in sleep and deep-sleep mode.
\r
793 //! \param bEnable is a boolean that is \b true if the sleep and deep-sleep
\r
794 //! peripheral configuration should be used and \b false if not.
\r
796 //! This function controls how peripherals are clocked when the processor goes
\r
797 //! into sleep or deep-sleep mode. By default, the peripherals are clocked the
\r
798 //! same as in run mode; if peripheral clock gating is enabled they are clocked
\r
799 //! according to the configuration set by SysCtlPeripheralSleepEnable(),
\r
800 //! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and
\r
801 //! SysCtlPeripheralDeepSleepDisable().
\r
805 //*****************************************************************************
\r
806 #if defined(GROUP_peripheralclockgating) || defined(BUILD_ALL) || \
\r
809 SysCtlPeripheralClockGating(tBoolean bEnable)
\r
812 // Enable peripheral clock gating as requested.
\r
816 HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG;
\r
820 HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG);
\r
825 //*****************************************************************************
\r
827 //! Registers an interrupt handler for the system control interrupt.
\r
829 //! \param pfnHandler is a pointer to the function to be called when the system
\r
830 //! control interrupt occurs.
\r
832 //! This sets the handler to be called when a system control interrupt occurs.
\r
833 //! This will enable the global interrupt in the interrupt controller; specific
\r
834 //! system control interrupts must be enabled via SysCtlIntEnable(). It is the
\r
835 //! interrupt handler's responsibility to clear the interrupt source via
\r
836 //! SysCtlIntClear().
\r
838 //! System control can generate interrupts when the PLL achieves lock, if the
\r
839 //! internal LDO current limit is exceeded, if the internal oscillator fails,
\r
840 //! if the main oscillator fails, if the internal LDO output voltage droops too
\r
841 //! much, if the external voltage droops too much, or if the PLL fails.
\r
843 //! \sa IntRegister() for important information about registering interrupt
\r
848 //*****************************************************************************
\r
849 #if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
851 SysCtlIntRegister(void (*pfnHandler)(void))
\r
854 // Register the interrupt handler, returning an error if an error occurs.
\r
856 IntRegister(INT_SYSCTL, pfnHandler);
\r
859 // Enable the system control interrupt.
\r
861 IntEnable(INT_SYSCTL);
\r
865 //*****************************************************************************
\r
867 //! Unregisters the interrupt handler for the system control interrupt.
\r
869 //! This function will clear the handler to be called when a system control
\r
870 //! interrupt occurs. This will also mask off the interrupt in the interrupt
\r
871 //! controller so that the interrupt handler no longer is called.
\r
873 //! \sa IntRegister() for important information about registering interrupt
\r
878 //*****************************************************************************
\r
879 #if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
881 SysCtlIntUnregister(void)
\r
884 // Disable the interrupt.
\r
886 IntDisable(INT_SYSCTL);
\r
889 // Unregister the interrupt handler.
\r
891 IntUnregister(INT_SYSCTL);
\r
895 //*****************************************************************************
\r
897 //! Enables individual system control interrupt sources.
\r
899 //! \param ulInts is a bit mask of the interrupt sources to be enabled. Must
\r
900 //! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
\r
901 //! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
\r
902 //! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
\r
904 //! Enables the indicated system control interrupt sources. Only the sources
\r
905 //! that are enabled can be reflected to the processor interrupt; disabled
\r
906 //! sources have no effect on the processor.
\r
910 //*****************************************************************************
\r
911 #if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
913 SysCtlIntEnable(unsigned long ulInts)
\r
916 // Enable the specified interrupts.
\r
918 HWREG(SYSCTL_IMC) |= ulInts;
\r
922 //*****************************************************************************
\r
924 //! Disables individual system control interrupt sources.
\r
926 //! \param ulInts is a bit mask of the interrupt sources to be disabled. Must
\r
927 //! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
\r
928 //! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
\r
929 //! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
\r
931 //! Disables the indicated system control interrupt sources. Only the sources
\r
932 //! that are enabled can be reflected to the processor interrupt; disabled
\r
933 //! sources have no effect on the processor.
\r
937 //*****************************************************************************
\r
938 #if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
940 SysCtlIntDisable(unsigned long ulInts)
\r
943 // Disable the specified interrupts.
\r
945 HWREG(SYSCTL_IMC) &= ~(ulInts);
\r
949 //*****************************************************************************
\r
951 //! Clears system control interrupt sources.
\r
953 //! \param ulInts is a bit mask of the interrupt sources to be cleared. Must
\r
954 //! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
\r
955 //! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
\r
956 //! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
\r
958 //! The specified system control interrupt sources are cleared, so that they no
\r
959 //! longer assert. This must be done in the interrupt handler to keep it from
\r
960 //! being called again immediately upon exit.
\r
964 //*****************************************************************************
\r
965 #if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
967 SysCtlIntClear(unsigned long ulInts)
\r
970 // Clear the requested interrupt sources.
\r
972 HWREG(SYSCTL_MISC) = ulInts;
\r
976 //*****************************************************************************
\r
978 //! Gets the current interrupt status.
\r
980 //! \param bMasked is false if the raw interrupt status is required and true if
\r
981 //! the masked interrupt status is required.
\r
983 //! This returns the interrupt status for the system controller. Either the
\r
984 //! raw interrupt status or the status of interrupts that are allowed to
\r
985 //! reflect to the processor can be returned.
\r
987 //! \return The current interrupt status, enumerated as a bit field of
\r
988 //! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL,
\r
989 //! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and
\r
990 //! \b SYSCTL_INT_PLL_FAIL.
\r
992 //*****************************************************************************
\r
993 #if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
995 SysCtlIntStatus(tBoolean bMasked)
\r
998 // Return either the interrupt status or the raw interrupt status as
\r
1003 return(HWREG(SYSCTL_MISC));
\r
1007 return(HWREG(SYSCTL_RIS));
\r
1012 //*****************************************************************************
\r
1014 //! Sets the output voltage of the LDO.
\r
1016 //! \param ulVoltage is the required output voltage from the LDO. Must be one
\r
1017 //! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V,
\r
1018 //! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V,
\r
1019 //! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V,
\r
1020 //! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V.
\r
1022 //! This function sets the output voltage of the LDO. The default voltage is
\r
1023 //! 2.5 V; it can be adjusted +/- 10%.
\r
1027 //*****************************************************************************
\r
1028 #if defined(GROUP_ldoset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1030 SysCtlLDOSet(unsigned long ulVoltage)
\r
1033 // Check the arguments.
\r
1035 ASSERT((ulVoltage == SYSCTL_LDO_2_25V) ||
\r
1036 (ulVoltage == SYSCTL_LDO_2_30V) ||
\r
1037 (ulVoltage == SYSCTL_LDO_2_35V) ||
\r
1038 (ulVoltage == SYSCTL_LDO_2_40V) ||
\r
1039 (ulVoltage == SYSCTL_LDO_2_45V) ||
\r
1040 (ulVoltage == SYSCTL_LDO_2_50V) ||
\r
1041 (ulVoltage == SYSCTL_LDO_2_55V) ||
\r
1042 (ulVoltage == SYSCTL_LDO_2_60V) ||
\r
1043 (ulVoltage == SYSCTL_LDO_2_65V) ||
\r
1044 (ulVoltage == SYSCTL_LDO_2_70V) ||
\r
1045 (ulVoltage == SYSCTL_LDO_2_75V));
\r
1048 // Set the LDO voltage to the requested value.
\r
1050 HWREG(SYSCTL_LDOPCTL) = ulVoltage;
\r
1054 //*****************************************************************************
\r
1056 //! Gets the output voltage of the LDO.
\r
1058 //! This function determines the output voltage of the LDO, as specified by the
\r
1059 //! control register.
\r
1061 //! \return Returns the current voltage of the LDO; will be one of
\r
1062 //! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V,
\r
1063 //! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V,
\r
1064 //! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V,
\r
1065 //! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V.
\r
1067 //*****************************************************************************
\r
1068 #if defined(GROUP_ldoget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1070 SysCtlLDOGet(void)
\r
1073 // Return the LDO voltage setting.
\r
1075 return(HWREG(SYSCTL_LDOPCTL));
\r
1079 //*****************************************************************************
\r
1081 //! Configures the LDO failure control.
\r
1083 //! \param ulConfig is the required LDO failure control setting; can be either
\r
1084 //! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST.
\r
1086 //! This function allows the LDO to be configured to cause a processor reset
\r
1087 //! when the output voltage becomes unregulated.
\r
1091 //*****************************************************************************
\r
1092 #if defined(GROUP_ldoconfigset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1094 SysCtlLDOConfigSet(unsigned long ulConfig)
\r
1097 // Check hte arguments.
\r
1099 ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) ||
\r
1100 (ulConfig == SYSCTL_LDOCFG_NORST));
\r
1103 // Set the reset control as requested.
\r
1105 HWREG(SYSCTL_LDOARST) = ulConfig;
\r
1109 //*****************************************************************************
\r
1111 //! Resets the device.
\r
1113 //! This function will perform a software reset of the entire device. The
\r
1114 //! processor and all peripherals will be reset and all device registers will
\r
1115 //! return to their default values (with the exception of the reset cause
\r
1116 //! register, which will maintain its current value but have the software reset
\r
1117 //! bit set as well).
\r
1119 //! \return This function does not return.
\r
1121 //*****************************************************************************
\r
1122 #if defined(GROUP_reset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1127 // Perform a software reset request. This will cause the device to reset,
\r
1128 // no further code will be executed.
\r
1130 HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ;
\r
1133 // The device should have reset, so this should never be reached. Just in
\r
1134 // case, loop forever.
\r
1142 //*****************************************************************************
\r
1144 //! Puts the processor into sleep mode.
\r
1146 //! This function places the processor into sleep mode; it will not return
\r
1147 //! until the processor returns to run mode. The peripherals that are enabled
\r
1148 //! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the
\r
1149 //! processor (if automatic clock gating is enabled with
\r
1150 //! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
\r
1155 //*****************************************************************************
\r
1156 #if defined(GROUP_sleep) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1161 // Wait for an interrupt.
\r
1167 //*****************************************************************************
\r
1169 //! Puts the processor into deep-sleep mode.
\r
1171 //! This function places the processor into deep-sleep mode; it will not return
\r
1172 //! until the processor returns to run mode. The peripherals that are enabled
\r
1173 //! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up
\r
1174 //! the processor (if automatic clock gating is enabled with
\r
1175 //! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
\r
1180 //*****************************************************************************
\r
1181 #if defined(GROUP_deepsleep) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1183 SysCtlDeepSleep(void)
\r
1186 // Enable deep-sleep.
\r
1188 HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
\r
1191 // Wait for an interrupt.
\r
1196 // Disable deep-sleep so that a future sleep will work correctly.
\r
1198 HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
\r
1202 //*****************************************************************************
\r
1204 //! Gets the reason for a reset.
\r
1206 //! This function will return the reason(s) for a reset. Since the reset
\r
1207 //! reasons are sticky until either cleared by software or an external reset,
\r
1208 //! multiple reset reasons may be returned if multiple resets have occurred.
\r
1209 //! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO,
\r
1210 //! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR,
\r
1211 //! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
\r
1213 //! \return The reason(s) for a reset.
\r
1215 //*****************************************************************************
\r
1216 #if defined(GROUP_resetcauseget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1218 SysCtlResetCauseGet(void)
\r
1221 // Return the reset reasons.
\r
1223 return(HWREG(SYSCTL_RESC));
\r
1227 //*****************************************************************************
\r
1229 //! Clears reset reasons.
\r
1231 //! \param ulCauses are the reset causes to be cleared; must be a logical OR of
\r
1232 //! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG,
\r
1233 //! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
\r
1235 //! This function clears the specified sticky reset reasons. Once cleared,
\r
1236 //! another reset for the same reason can be detected, and a reset for a
\r
1237 //! different reason can be distinguished (instead of having two reset causes
\r
1238 //! set). If the reset reason is used by an application, all reset causes
\r
1239 //! should be cleared after they are retrieved with SysCtlResetCauseGet().
\r
1243 //*****************************************************************************
\r
1244 #if defined(GROUP_resetcauseclear) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1246 SysCtlResetCauseClear(unsigned long ulCauses)
\r
1249 // Clear the given reset reasons.
\r
1251 HWREG(SYSCTL_RESC) &= ~(ulCauses);
\r
1255 //*****************************************************************************
\r
1257 //! Configures the brown-out control.
\r
1259 //! \param ulConfig is the desired configuration of the brown-out control.
\r
1260 //! Must be the logical OR of \b SYSCTL_BOR_RESET and/or
\r
1261 //! \b SYSCTL_BOR_RESAMPLE.
\r
1262 //! \param ulDelay is the number of internal oscillator cycles to wait before
\r
1263 //! resampling an asserted brown-out signal. This value only has meaning when
\r
1264 //! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192.
\r
1266 //! This function configures how the brown-out control operates. It can detect
\r
1267 //! a brown-out by looking at only the brown-out output, or it can wait for it
\r
1268 //! to be active for two consecutive samples separated by a configurable time.
\r
1269 //! When it detects a brown-out condition, it can either reset the device or
\r
1270 //! generate a processor interrupt.
\r
1274 //*****************************************************************************
\r
1275 #if defined(GROUP_brownoutconfigset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1277 SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay)
\r
1280 // Check the arguments.
\r
1282 ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE)));
\r
1283 ASSERT(ulDelay < 8192);
\r
1286 // Configure the brown-out reset control.
\r
1288 HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BOR_SH) | ulConfig;
\r
1292 //*****************************************************************************
\r
1294 //! Sets the clocking of the device.
\r
1296 //! \param ulConfig is the required configuration of the device clocking.
\r
1298 //! This function configures the clocking of the device. The input crystal
\r
1299 //! frequency, oscillator to be used, use of the PLL, and the system clock
\r
1300 //! divider are all configured with this function.
\r
1302 //! The \b ulConfig parameter is the logical OR of several different values,
\r
1303 //! many of which are grouped into sets where only one can be chosen.
\r
1305 //! The system clock divider is chosen with one of the following values:
\r
1306 //! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3,
\r
1307 //! \b SYSCTL_SYSDIV_4, \b SYSCTL_SYSDIV_5, \b SYSCTL_SYSDIV_6,
\r
1308 //! \b SYSCTL_SYSDIV_7, \b SYSCTL_SYSDIV_8, \b SYSCTL_SYSDIV_9,
\r
1309 //! \b SYSCTL_SYSDIV_10, \b SYSCTL_SYSDIV_11, \b SYSCTL_SYSDIV_12,
\r
1310 //! \b SYSCTL_SYSDIV_13, \b SYSCTL_SYSDIV_14, \b SYSCTL_SYSDIV_15, or
\r
1311 //! \b SYSCTL_SYSDIV_16.
\r
1313 //! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or
\r
1314 //! \b SYSCTL_USE_OSC.
\r
1316 //! The external crystal frequency is chosen with one of the following values:
\r
1317 //! \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ, \b SYSCTL_XTAL_4MHZ,
\r
1318 //! \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, \b SYSCTL_XTAL_5MHZ,
\r
1319 //! \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_6_14MHZ,
\r
1320 //! \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, or \b SYSCTL_XTAL_8_19MHZ.
\r
1322 //! The oscillator source is chosen with one of the following values:
\r
1323 //! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, or \b SYSCTL_OSC_INT4.
\r
1325 //! The internal and main oscillators are disabled with the
\r
1326 //! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively.
\r
1327 //! The external oscillator must be enabled in order to use an external clock
\r
1328 //! source. Note that attempts to disable the oscillator used to clock the
\r
1329 //! device will be prevented by the hardware.
\r
1331 //! To clock the system from an external source (such as an external crystal
\r
1332 //! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the
\r
1333 //! system from the main oscillator, use \b SYSCTL_USE_OSC \b |
\r
1334 //! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use
\r
1335 //! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate
\r
1336 //! crystal with one of the \b SYSCTL_XTAL_xxx values.
\r
1338 //! \note If selecting the PLL as the system clock source (i.e. via
\r
1339 //! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to
\r
1340 //! determine when the PLL has locked. If an interrupt handler for the
\r
1341 //! system control interrupt is in place, and it responds to and clears the
\r
1342 //! PLL lock interrupt, this function will delay until its timeout has occurred
\r
1343 //! instead of completing as soon as PLL lock is achieved.
\r
1347 //*****************************************************************************
\r
1348 #if defined(GROUP_clockset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1350 SysCtlClockSet(unsigned long ulConfig)
\r
1352 volatile unsigned long ulDelay;
\r
1353 unsigned long ulRCC;
\r
1356 // Get the current value of the RCC register.
\r
1358 ulRCC = HWREG(SYSCTL_RCC);
\r
1361 // Bypass the PLL and system clock dividers for now.
\r
1363 ulRCC |= SYSCTL_RCC_BYPASS;
\r
1364 ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV);
\r
1367 // Write the new RCC value.
\r
1369 HWREG(SYSCTL_RCC) = ulRCC;
\r
1372 // Make sure that the PLL and system clock dividers are bypassed for now.
\r
1374 ulRCC |= SYSCTL_RCC_BYPASS;
\r
1375 ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV);
\r
1378 // Make sure that the required oscillators are enabled. For now, the
\r
1379 // previously enabled oscillators must be enabled along with the newly
\r
1380 // requested oscillators.
\r
1382 ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) |
\r
1383 (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS)));
\r
1386 // Set the new crystal value, oscillator source, and PLL configuration.
\r
1388 ulRCC &= ~(SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK |
\r
1389 SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE);
\r
1390 ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK |
\r
1391 SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE);
\r
1394 // Clear the PLL lock interrupt.
\r
1396 HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK;
\r
1399 // Write the new RCC value.
\r
1401 HWREG(SYSCTL_RCC) = ulRCC;
\r
1404 // Wait for a bit so that new crystal value and oscillator source can take
\r
1405 // effect. One of the oscillators may need to be started as well.
\r
1407 for(ulDelay = 0; ulDelay < 16; ulDelay++)
\r
1412 // Disable the appropriate oscillators.
\r
1414 ulRCC &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
\r
1415 ulRCC |= ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
\r
1418 // Write the new RCC value.
\r
1420 HWREG(SYSCTL_RCC) = ulRCC;
\r
1423 // Set the requested system divider. This will not get written
\r
1426 ulRCC &= ~(SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV);
\r
1427 ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV);
\r
1430 // See if the PLL output is being used to clock the system.
\r
1432 if(!(ulConfig & SYSCTL_RCC_BYPASS))
\r
1435 // Wait until the PLL has locked.
\r
1437 for(ulDelay = 32768; ulDelay > 0; ulDelay--)
\r
1439 if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK)
\r
1446 // Enable use of the PLL.
\r
1448 ulRCC &= ~(SYSCTL_RCC_BYPASS);
\r
1452 // Write the final RCC value.
\r
1454 HWREG(SYSCTL_RCC) = ulRCC;
\r
1457 // Delay for a little bit so that the system divider takes effect.
\r
1459 for(ulDelay = 0; ulDelay < 16; ulDelay++)
\r
1465 //*****************************************************************************
\r
1467 //! Gets the processor clock rate.
\r
1469 //! This function determines the clock rate of the processor clock. This is
\r
1470 //! also the clock rate of all the peripheral modules (with the exception of
\r
1471 //! PWM, which has its own clock divider).
\r
1473 //! \note This will not return accurate results if SysCtlClockSet() has not
\r
1474 //! been called to configure the clocking of the device, or if the device is
\r
1475 //! directly clocked from a crystal (or a clock source) that is not one of the
\r
1476 //! supported crystal frequencies. In the later case, this function should be
\r
1477 //! modified to directly return the correct system clock rate.
\r
1479 //! \return The processor clock rate.
\r
1481 //*****************************************************************************
\r
1482 #if defined(GROUP_clockget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1484 SysCtlClockGet(void)
\r
1486 unsigned long ulRCC, ulPLL, ulClk;
\r
1491 ulRCC = HWREG(SYSCTL_RCC);
\r
1494 // Get the base clock rate.
\r
1496 switch(ulRCC & SYSCTL_RCC_OSCSRC_MASK)
\r
1499 // The main oscillator is the clock source. Determine its rate from
\r
1500 // the crystal setting field.
\r
1502 case SYSCTL_RCC_OSCSRC_MAIN:
\r
1504 ulClk = g_pulXtals[((ulRCC & SYSCTL_RCC_XTAL_MASK) >>
\r
1505 SYSCTL_RCC_XTAL_SHIFT) -
\r
1506 (SYSCTL_RCC_XTAL_3_57MHZ >>
\r
1507 SYSCTL_RCC_XTAL_SHIFT)];
\r
1512 // The internal oscillator is the source clock. This is not an
\r
1513 // accurate clock (it is +/- 50%); what is used is the nominal.
\r
1515 case SYSCTL_RCC_OSCSRC_INT:
\r
1522 // The internal oscillator divided by four is the source clock. This
\r
1523 // is not an accurate clock (it is +/- 50%); what is used is the
\r
1526 case SYSCTL_RCC_OSCSRC_INT4:
\r
1528 ulClk = 15000000 / 4;
\r
1533 // An unknown setting, so return a zero clock (i.e. an unknown clock
\r
1543 // See if the PLL is being used.
\r
1545 if(!(ulRCC & SYSCTL_RCC_BYPASS))
\r
1548 // Get the PLL configuration.
\r
1550 ulPLL = HWREG(SYSCTL_PLLCFG);
\r
1553 // Compute the PLL output frequency based on its input frequency.
\r
1555 ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_MASK) >>
\r
1556 SYSCTL_PLLCFG_F_SHIFT) + 2)) /
\r
1557 (((ulPLL & SYSCTL_PLLCFG_R_MASK) >>
\r
1558 SYSCTL_PLLCFG_R_SHIFT) + 2));
\r
1561 // See if the optional output divide by 2 is being used.
\r
1563 if(ulPLL & SYSCTL_PLLCFG_OD_2)
\r
1569 // See if the optional output divide by 4 is being used.
\r
1571 if(ulPLL & SYSCTL_PLLCFG_OD_4)
\r
1578 // See if the system divider is being used.
\r
1580 if(ulRCC & SYSCTL_RCC_USE_SYSDIV)
\r
1583 // Adjust the clock rate by the system clock divider.
\r
1585 ulClk /= ((ulRCC & SYSCTL_RCC_SYSDIV_MASK) >>
\r
1586 SYSCTL_RCC_SYSDIV_SHIFT) + 1;
\r
1590 // Return the computed clock rate.
\r
1596 //*****************************************************************************
\r
1598 //! Sets the PWM clock configuration.
\r
1600 //! \param ulConfig is the configuration for the PWM clock; it must be one of
\r
1601 //! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
\r
1602 //! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
\r
1603 //! \b SYSCTL_PWMDIV_64.
\r
1605 //! This function sets the rate of the clock provided to the PWM module as a
\r
1606 //! ratio of the processor clock. This clock is used by the PWM module to
\r
1607 //! generate PWM signals; its rate forms the basis for all PWM signals.
\r
1609 //! \note The clocking of the PWM is dependent upon the system clock rate as
\r
1610 //! configured by SysCtlClockSet().
\r
1614 //*****************************************************************************
\r
1615 #if defined(GROUP_pwmclockset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1617 SysCtlPWMClockSet(unsigned long ulConfig)
\r
1620 // Check the arguments.
\r
1622 ASSERT((ulConfig == SYSCTL_PWMDIV_1) ||
\r
1623 (ulConfig == SYSCTL_PWMDIV_2) ||
\r
1624 (ulConfig == SYSCTL_PWMDIV_4) ||
\r
1625 (ulConfig == SYSCTL_PWMDIV_8) ||
\r
1626 (ulConfig == SYSCTL_PWMDIV_16) ||
\r
1627 (ulConfig == SYSCTL_PWMDIV_32) ||
\r
1628 (ulConfig == SYSCTL_PWMDIV_64));
\r
1631 // Check that there is a PWM block on this part.
\r
1633 ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM);
\r
1636 // Set the PWM clock configuration into the run-mode clock configuration
\r
1639 HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) &
\r
1640 ~(SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)) |
\r
1645 //*****************************************************************************
\r
1647 //! Gets the current PWM clock configuration.
\r
1649 //! This function returns the current PWM clock configuration.
\r
1651 //! \return The current PWM clock configuration; will be one of
\r
1652 //! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
\r
1653 //! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
\r
1654 //! \b SYSCTL_PWMDIV_64.
\r
1656 //*****************************************************************************
\r
1657 #if defined(GROUP_pwmclockget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1659 SysCtlPWMClockGet(void)
\r
1662 // Check that there is a PWM block on this part.
\r
1664 ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM);
\r
1667 // Return the current PWM clock configuration.
\r
1669 return(HWREG(SYSCTL_RCC) &
\r
1670 (SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK));
\r
1674 //*****************************************************************************
\r
1676 //! Sets the sample rate of the ADC.
\r
1678 //! \param ulSpeed is the desired sample rate of the ADC; must be one of
\r
1679 //! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,
\r
1680 //! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.
\r
1682 //! This function sets the rate at which the ADC samples are captured by the
\r
1683 //! ADC block. The sampling speed may be limited by the hardware, so the
\r
1684 //! sample rate may end up being slower than requested. SysCtlADCSpeedGet()
\r
1685 //! will return the actual speed in use.
\r
1689 //*****************************************************************************
\r
1690 #if defined(GROUP_adcspeedset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1692 SysCtlADCSpeedSet(unsigned long ulSpeed)
\r
1695 // Check the arguments.
\r
1697 ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) ||
\r
1698 (ulSpeed == SYSCTL_ADCSPEED_500KSPS) ||
\r
1699 (ulSpeed == SYSCTL_ADCSPEED_250KSPS) ||
\r
1700 (ulSpeed == SYSCTL_ADCSPEED_125KSPS));
\r
1703 // Check that there is an ADC block on this part.
\r
1705 ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC);
\r
1708 // Set the ADC speed in run, sleep, and deep-sleep mode.
\r
1710 HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) |
\r
1712 HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) |
\r
1714 HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) |
\r
1719 //*****************************************************************************
\r
1721 //! Gets the sample rate of the ADC.
\r
1723 //! This function gets the current sample rate of the ADC.
\r
1725 //! \return Returns the current ADC sample rate; will be one of
\r
1726 //! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,
\r
1727 //! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.
\r
1729 //*****************************************************************************
\r
1730 #if defined(GROUP_adcspeedget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1732 SysCtlADCSpeedGet(void)
\r
1735 // Check that there is an ADC block on this part.
\r
1737 ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC);
\r
1740 // Return the current ADC speed.
\r
1742 return(HWREG(SYSCTL_RCGC0) & SYSCTL_SET0_ADCSPD_MASK);
\r
1746 //*****************************************************************************
\r
1748 //! Configures the internal oscillator verification timer.
\r
1750 //! \param bEnable is a boolean that is \b true if the internal oscillator
\r
1751 //! verification timer should be enabled.
\r
1753 //! This function allows the internal oscillator verification timer to be
\r
1754 //! enabled or disabled. When enabled, an interrupt will be generated if the
\r
1755 //! internal oscillator ceases to operate.
\r
1757 //! \note Both oscillators (main and internal) must be enabled for this
\r
1758 //! verification timer to operate as the main oscillator will verify the
\r
1759 //! internal oscillator.
\r
1763 //*****************************************************************************
\r
1764 #if defined(GROUP_boscverificationset) || defined(BUILD_ALL) || \
\r
1767 SysCtlIOSCVerificationSet(tBoolean bEnable)
\r
1770 // Enable or disable the internal oscillator verification timer as
\r
1775 HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER;
\r
1779 HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER);
\r
1784 //*****************************************************************************
\r
1786 //! Configures the main oscillator verification timer.
\r
1788 //! \param bEnable is a boolean that is \b true if the main oscillator
\r
1789 //! verification timer should be enabled.
\r
1791 //! This function allows the main oscillator verification timer to be enabled
\r
1792 //! or disabled. When enabled, an interrupt will be generated if the main
\r
1793 //! oscillator ceases to operate.
\r
1795 //! \note Both oscillators (main and internal) must be enabled for this
\r
1796 //! verification timer to operate as the internal oscillator will verify the
\r
1797 //! main oscillator.
\r
1801 //*****************************************************************************
\r
1802 #if defined(GROUP_moscverificationset) || defined(BUILD_ALL) || \
\r
1805 SysCtlMOSCVerificationSet(tBoolean bEnable)
\r
1808 // Enable or disable the main oscillator verification timer as requested.
\r
1812 HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER;
\r
1816 HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER);
\r
1821 //*****************************************************************************
\r
1823 //! Configures the PLL verification timer.
\r
1825 //! \param bEnable is a boolean that is \b true if the PLL verification timer
\r
1826 //! should be enabled.
\r
1828 //! This function allows the PLL verification timer to be enabled or disabled.
\r
1829 //! When enabled, an interrupt will be generated if the PLL ceases to operate.
\r
1831 //! \note The main oscillator must be enabled for this verification timer to
\r
1832 //! operate as it is used to check the PLL. Also, the verification timer
\r
1833 //! should be disabled while the PLL is being reconfigured via
\r
1834 //! SysCtlClockSet().
\r
1838 //*****************************************************************************
\r
1839 #if defined(GROUP_pllverificationset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1841 SysCtlPLLVerificationSet(tBoolean bEnable)
\r
1844 // Enable or disable the PLL verification timer as requested.
\r
1848 HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER;
\r
1852 HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER);
\r
1857 //*****************************************************************************
\r
1859 //! Clears the clock verification status.
\r
1861 //! This function clears the status of the clock verification timers, allowing
\r
1862 //! them to assert another failure if detected.
\r
1866 //*****************************************************************************
\r
1867 #if defined(GROUP_clkverificationclear) || defined(BUILD_ALL) || \
\r
1870 SysCtlClkVerificationClear(void)
\r
1873 // Clear the clock verification.
\r
1875 HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_CLR;
\r
1878 // The bit does not self-reset, so clear it.
\r
1880 HWREG(SYSCTL_CLKVCLR) = 0;
\r
1884 //*****************************************************************************
\r
1886 // Close the Doxygen group.
\r
1889 //*****************************************************************************
\r