1 //*****************************************************************************
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3 // timer.c - Driver for the timer module.
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5 // Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's Stellaris Family of microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 991 of the Stellaris Driver Library.
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26 //*****************************************************************************
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28 //*****************************************************************************
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30 //! \addtogroup timer_api
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33 //*****************************************************************************
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35 #include "../hw_ints.h"
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36 #include "../hw_memmap.h"
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37 #include "../hw_timer.h"
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38 #include "../hw_types.h"
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40 #include "interrupt.h"
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43 //*****************************************************************************
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45 //! Enables the timer(s).
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47 //! \param ulBase is the base address of the timer module.
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48 //! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A,
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49 //! \b TIMER_B, or \b TIMER_BOTH.
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51 //! This will enable operation of the timer module. The timer must be
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52 //! configured before it is enabled.
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56 //*****************************************************************************
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57 #if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)
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59 TimerEnable(unsigned long ulBase, unsigned long ulTimer)
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62 // Check the arguments.
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64 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
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65 (ulBase == TIMER2_BASE));
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66 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
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67 (ulTimer == TIMER_BOTH));
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70 // Enable the timer(s) module.
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72 HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN);
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76 //*****************************************************************************
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78 //! Disables the timer(s).
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80 //! \param ulBase is the base address of the timer module.
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81 //! \param ulTimer specifies the timer(s) to disable; must be one of
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82 //! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
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84 //! This will disable operation of the timer module.
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88 //*****************************************************************************
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89 #if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)
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91 TimerDisable(unsigned long ulBase, unsigned long ulTimer)
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94 // Check the arguments.
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96 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
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97 (ulBase == TIMER2_BASE));
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98 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
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99 (ulTimer == TIMER_BOTH));
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102 // Disable the timer module.
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104 HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer &
\r
105 (TIMER_CTL_TAEN | TIMER_CTL_TBEN));
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109 //*****************************************************************************
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111 //! Configures the timer(s).
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113 //! \param ulBase is the base address of the timer module.
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114 //! \param ulConfig is the configuration for the timer.
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116 //! This function configures the operating mode of the timer(s). The timer
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117 //! module is disabled before being configured, and is left in the disabled
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118 //! state. The configuration is specified in \e ulConfig as one of the
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119 //! following values:
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121 //! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer
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122 //! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer
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123 //! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer
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124 //! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers
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126 //! When configured for a pair of 16-bit timers, each timer is separately
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127 //! configured. The first timer is configured by setting \e ulConfig to
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128 //! the result of a logical OR operation between one of the following values
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129 //! and \e ulConfig:
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131 //! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer
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132 //! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer
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133 //! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture
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134 //! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture
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135 //! - \b TIMER_CFG_A_PWM - 16-bit PWM output
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137 //! Similarly, the second timer is configured by setting \e ulConfig to
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138 //! the result of a logical OR operation between one of the corresponding
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139 //! \b TIMER_CFG_B_* values and \e ulConfig.
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143 //*****************************************************************************
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144 #if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN)
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146 TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
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149 // Check the arguments.
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151 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
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152 (ulBase == TIMER2_BASE));
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153 ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) ||
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154 (ulConfig == TIMER_CFG_32_BIT_PER) ||
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155 (ulConfig == TIMER_CFG_32_RTC) ||
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156 ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR));
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157 ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) ||
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158 ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
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159 ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
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160 ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
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161 ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
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162 ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) &&
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163 (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
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164 ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
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165 ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
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166 ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
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167 ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))));
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170 // Disable the timers.
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172 HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN);
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175 // Set the global timer configuration.
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177 HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24;
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180 // Set the configuration of the A and B timers. Note that the B timer
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181 // configuration is ignored by the hardware in 32-bit modes.
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183 HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255;
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184 HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255;
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188 //*****************************************************************************
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190 //! Controls the output level.
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192 //! \param ulBase is the base address of the timer module.
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193 //! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
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194 //! \b TIMER_B, or \b TIMER_BOTH.
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195 //! \param bInvert specifies the output level.
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197 //! This function sets the PWM output level for the specified timer. If the
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198 //! parameter \e bInvert is \b true, then the timer's output will be made
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199 //! active low; otherwise, it will be made active high.
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203 //*****************************************************************************
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204 #if defined(GROUP_controllevel) || defined(BUILD_ALL) || defined(DOXYGEN)
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206 TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
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210 // Check the arguments.
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212 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
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213 (ulBase == TIMER2_BASE));
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214 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
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215 (ulTimer == TIMER_BOTH));
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218 // Set the output levels as requested.
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220 ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML;
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221 HWREG(ulBase + TIMER_O_CTL) = (bInvert ?
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222 (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
\r
223 (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
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227 //*****************************************************************************
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229 //! Enables or disables the trigger output.
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231 //! \param ulBase is the base address of the timer module.
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232 //! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A,
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233 //! \b TIMER_B, or \b TIMER_BOTH.
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234 //! \param bEnable specifies the desired trigger state.
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236 //! This function controls the trigger output for the specified timer. If the
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237 //! parameter \e bEnable is \b true, then the timer's output trigger is
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238 //! enabled; otherwise it is disabled.
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242 //*****************************************************************************
\r
243 #if defined(GROUP_controltrigger) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
245 TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
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249 // Check the arguments.
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251 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
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252 (ulBase == TIMER2_BASE));
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253 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
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254 (ulTimer == TIMER_BOTH));
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257 // Set the trigger output as requested.
\r
259 ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE;
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260 HWREG(ulBase + TIMER_O_CTL) = (bEnable ?
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261 (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
\r
262 (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
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266 //*****************************************************************************
\r
268 //! Controls the event type.
\r
270 //! \param ulBase is the base address of the timer module.
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271 //! \param ulTimer specifies the timer(s) to be adjusted; must be one of
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272 //! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
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273 //! \param ulEvent specifies the type of event; must be one of
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274 //! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or
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275 //! \b TIMER_EVENT_BOTH_EDGES.
\r
277 //! This function sets the signal edge(s) that will trigger the timer when in
\r
282 //*****************************************************************************
\r
283 #if defined(GROUP_controlevent) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
285 TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
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286 unsigned long ulEvent)
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289 // Check the arguments.
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291 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
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292 (ulBase == TIMER2_BASE));
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293 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
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294 (ulTimer == TIMER_BOTH));
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297 // Set the event type.
\r
299 ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_MSK | TIMER_CTL_TBEVENT_MSK);
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300 HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) &
\r
301 ~(TIMER_CTL_TAEVENT_MSK |
\r
302 TIMER_CTL_TBEVENT_MSK)) | ulEvent);
\r
306 //*****************************************************************************
\r
308 //! Controls the stall handling.
\r
310 //! \param ulBase is the base address of the timer module.
\r
311 //! \param ulTimer specifies the timer(s) to be adjusted; must be one of
\r
312 //! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
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313 //! \param bStall specifies the response to a stall signal.
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315 //! This function controls the stall response for the specified timer. If the
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316 //! parameter \e bStall is \b true, then the timer will stop counting if the
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317 //! processor enters debug mode; otherwise the timer will keep running while in
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322 //*****************************************************************************
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323 #if defined(GROUP_controlstall) || defined(BUILD_ALL) || defined(DOXYGEN)
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325 TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
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329 // Check the arguments.
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331 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
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332 (ulBase == TIMER2_BASE));
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333 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
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334 (ulTimer == TIMER_BOTH));
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337 // Set the stall mode.
\r
339 ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL;
\r
340 HWREG(ulBase + TIMER_O_CTL) = (bStall ?
\r
341 (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
\r
342 (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
\r
346 //*****************************************************************************
\r
348 //! Enable RTC counting.
\r
350 //! \param ulBase is the base address of the timer module.
\r
352 //! This function causes the timer to start counting when in RTC mode. If not
\r
353 //! configured for RTC mode, this will do nothing.
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357 //*****************************************************************************
\r
358 #if defined(GROUP_rtcenable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
360 TimerRTCEnable(unsigned long ulBase)
\r
363 // Check the arguments.
\r
365 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
366 (ulBase == TIMER2_BASE));
\r
369 // Enable RTC counting.
\r
371 HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN;
\r
375 //*****************************************************************************
\r
377 //! Disable RTC counting.
\r
379 //! \param ulBase is the base address of the timer module.
\r
381 //! This function causes the timer to stop counting when in RTC mode.
\r
385 //*****************************************************************************
\r
386 #if defined(GROUP_rtcdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
388 TimerRTCDisable(unsigned long ulBase)
\r
391 // Check the arguments.
\r
393 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
394 (ulBase == TIMER2_BASE));
\r
397 // Disable RTC counting.
\r
399 HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN);
\r
403 //*****************************************************************************
\r
405 //! Set the timer prescale value.
\r
407 //! \param ulBase is the base address of the timer module.
\r
408 //! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
\r
409 //! \b TIMER_B, or \b TIMER_BOTH.
\r
410 //! \param ulValue is the timer prescale value; must be between 0 and 255,
\r
413 //! This function sets the value of the input clock prescaler. The prescaler
\r
414 //! is only operational when in 16-bit mode and is used to extend the range of
\r
415 //! the 16-bit timer modes.
\r
419 //*****************************************************************************
\r
420 #if defined(GROUP_prescaleset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
422 TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
\r
423 unsigned long ulValue)
\r
426 // Check the arguments.
\r
428 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
429 (ulBase == TIMER2_BASE));
\r
430 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
\r
431 (ulTimer == TIMER_BOTH));
\r
432 ASSERT(ulValue < 256);
\r
435 // Set the timer A prescaler if requested.
\r
437 if(ulTimer & TIMER_A)
\r
439 HWREG(ulBase + TIMER_O_TAPR) = ulValue;
\r
443 // Set the timer B prescaler if requested.
\r
445 if(ulTimer & TIMER_B)
\r
447 HWREG(ulBase + TIMER_O_TBPR) = ulValue;
\r
452 //*****************************************************************************
\r
454 //! Get the timer prescale value.
\r
456 //! \param ulBase is the base address of the timer module.
\r
457 //! \param ulTimer specifies the timer; must be one of \b TIMER_A or
\r
460 //! This function gets the value of the input clock prescaler. The prescaler
\r
461 //! is only operational when in 16-bit mode and is used to extend the range of
\r
462 //! the 16-bit timer modes.
\r
464 //! \return The value of the timer prescaler.
\r
466 //*****************************************************************************
\r
467 #if defined(GROUP_prescaleget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
469 TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer)
\r
472 // Check the arguments.
\r
474 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
475 (ulBase == TIMER2_BASE));
\r
476 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
\r
477 (ulTimer == TIMER_BOTH));
\r
480 // Return the appropriate prescale value.
\r
482 return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) :
\r
483 HWREG(ulBase + TIMER_O_TBPR));
\r
487 //*****************************************************************************
\r
489 //! Set the timer prescale match value.
\r
491 //! \param ulBase is the base address of the timer module.
\r
492 //! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
\r
493 //! \b TIMER_B, or \b TIMER_BOTH.
\r
494 //! \param ulValue is the timer prescale match value; must be between 0 and
\r
495 //! 255, inclusive.
\r
497 //! This function sets the value of the input clock prescaler match value.
\r
498 //! When in a 16-bit mode that uses the counter match (edge count or PWM), the
\r
499 //! prescale match effectively extends the range of the counter to 24-bits.
\r
503 //*****************************************************************************
\r
504 #if defined(GROUP_prescalematchset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
506 TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
\r
507 unsigned long ulValue)
\r
510 // Check the arguments.
\r
512 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
513 (ulBase == TIMER2_BASE));
\r
514 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
\r
515 (ulTimer == TIMER_BOTH));
\r
516 ASSERT(ulValue < 256);
\r
519 // Set the timer A prescale match if requested.
\r
521 if(ulTimer & TIMER_A)
\r
523 HWREG(ulBase + TIMER_O_TAPMR) = ulValue;
\r
527 // Set the timer B prescale match if requested.
\r
529 if(ulTimer & TIMER_B)
\r
531 HWREG(ulBase + TIMER_O_TBPMR) = ulValue;
\r
536 //*****************************************************************************
\r
538 //! Get the timer prescale match value.
\r
540 //! \param ulBase is the base address of the timer module.
\r
541 //! \param ulTimer specifies the timer; must be one of \b TIMER_A or
\r
544 //! This function gets the value of the input clock prescaler match value.
\r
545 //! When in a 16-bit mode that uses the counter match (edge count or PWM), the
\r
546 //! prescale match effectively extends the range of the counter to 24-bits.
\r
548 //! \return The value of the timer prescale match.
\r
550 //*****************************************************************************
\r
551 #if defined(GROUP_prescalematchget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
553 TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer)
\r
556 // Check the arguments.
\r
558 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
559 (ulBase == TIMER2_BASE));
\r
560 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
\r
561 (ulTimer == TIMER_BOTH));
\r
564 // Return the appropriate prescale match value.
\r
566 return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) :
\r
567 HWREG(ulBase + TIMER_O_TBPMR));
\r
571 //*****************************************************************************
\r
573 //! Sets the timer load value.
\r
575 //! \param ulBase is the base address of the timer module.
\r
576 //! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
\r
577 //! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
\r
578 //! timer is configured for 32-bit operation.
\r
579 //! \param ulValue is the load value.
\r
581 //! This function sets the timer load value; if the timer is running then the
\r
582 //! value will be immediately loaded into the timer.
\r
586 //*****************************************************************************
\r
587 #if defined(GROUP_loadset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
589 TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
\r
590 unsigned long ulValue)
\r
593 // Check the arguments.
\r
595 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
596 (ulBase == TIMER2_BASE));
\r
597 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
\r
598 (ulTimer == TIMER_BOTH));
\r
601 // Set the timer A load value if requested.
\r
603 if(ulTimer & TIMER_A)
\r
605 HWREG(ulBase + TIMER_O_TAILR) = ulValue;
\r
609 // Set the timer B load value if requested.
\r
611 if(ulTimer & TIMER_B)
\r
613 HWREG(ulBase + TIMER_O_TBILR) = ulValue;
\r
618 //*****************************************************************************
\r
620 //! Gets the timer load value.
\r
622 //! \param ulBase is the base address of the timer module.
\r
623 //! \param ulTimer specifies the timer; must be one of \b TIMER_A or
\r
624 //! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
\r
625 //! for 32-bit operation.
\r
627 //! This function gets the currently programmed interval load value for the
\r
628 //! specified timer.
\r
630 //! \return Returns the load value for the timer.
\r
632 //*****************************************************************************
\r
633 #if defined(GROUP_loadget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
635 TimerLoadGet(unsigned long ulBase, unsigned long ulTimer)
\r
638 // Check the arguments.
\r
640 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
641 (ulBase == TIMER2_BASE));
\r
642 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
\r
645 // Return the appropriate load value.
\r
647 return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) :
\r
648 HWREG(ulBase + TIMER_O_TBILR));
\r
652 //*****************************************************************************
\r
654 //! Gets the current timer value.
\r
656 //! \param ulBase is the base address of the timer module.
\r
657 //! \param ulTimer specifies the timer; must be one of \b TIMER_A or
\r
658 //! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
\r
659 //! for 32-bit operation.
\r
661 //! This function reads the current value of the specified timer.
\r
663 //! \return Returns the current value of the timer.
\r
665 //*****************************************************************************
\r
666 #if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
668 TimerValueGet(unsigned long ulBase, unsigned long ulTimer)
\r
671 // Check the arguments.
\r
673 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
674 (ulBase == TIMER2_BASE));
\r
675 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
\r
678 // Return the appropriate timer value.
\r
680 return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) :
\r
681 HWREG(ulBase + TIMER_O_TBR));
\r
685 //*****************************************************************************
\r
687 //! Sets the timer match value.
\r
689 //! \param ulBase is the base address of the timer module.
\r
690 //! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
\r
691 //! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
\r
692 //! timer is configured for 32-bit operation.
\r
693 //! \param ulValue is the match value.
\r
695 //! This function sets the match value for a timer. This is used in capture
\r
696 //! count mode to determine when to interrupt the processor and in PWM mode to
\r
697 //! determine the duty cycle of the output signal.
\r
701 //*****************************************************************************
\r
702 #if defined(GROUP_matchset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
704 TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
\r
705 unsigned long ulValue)
\r
708 // Check the arguments.
\r
710 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
711 (ulBase == TIMER2_BASE));
\r
712 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
\r
713 (ulTimer == TIMER_BOTH));
\r
716 // Set the timer A match value if requested.
\r
718 if(ulTimer & TIMER_A)
\r
720 HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue;
\r
724 // Set the timer B match value if requested.
\r
726 if(ulTimer & TIMER_B)
\r
728 HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue;
\r
733 //*****************************************************************************
\r
735 //! Gets the timer match value.
\r
737 //! \param ulBase is the base address of the timer module.
\r
738 //! \param ulTimer specifies the timer; must be one of \b TIMER_A or
\r
739 //! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
\r
740 //! for 32-bit operation.
\r
742 //! This function gets the match value for the specified timer.
\r
744 //! \return Returns the match value for the timer.
\r
746 //*****************************************************************************
\r
747 #if defined(GROUP_matchget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
749 TimerMatchGet(unsigned long ulBase, unsigned long ulTimer)
\r
752 // Check the arguments.
\r
754 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
755 (ulBase == TIMER2_BASE));
\r
756 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
\r
759 // Return the appropriate match value.
\r
761 return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) :
\r
762 HWREG(ulBase + TIMER_O_TBMATCHR));
\r
766 //*****************************************************************************
\r
768 //! Registers an interrupt handler for the timer interrupt.
\r
770 //! \param ulBase is the base address of the timer module.
\r
771 //! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
\r
772 //! \b TIMER_B, or \b TIMER_BOTH.
\r
773 //! \param pfnHandler is a pointer to the function to be called when the timer
\r
774 //! interrupt occurs.
\r
776 //! This sets the handler to be called when a timer interrupt occurs. This
\r
777 //! will enable the global interrupt in the interrupt controller; specific
\r
778 //! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt
\r
779 //! handler's responsibility to clear the interrupt source via TimerIntClear().
\r
781 //! \sa IntRegister() for important information about registering interrupt
\r
786 //*****************************************************************************
\r
787 #if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
789 TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
\r
790 void (*pfnHandler)(void))
\r
793 // Check the arguments.
\r
795 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
796 (ulBase == TIMER2_BASE));
\r
797 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
\r
798 (ulTimer == TIMER_BOTH));
\r
801 // Get the interrupt number for this timer module.
\r
803 ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :
\r
804 ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A));
\r
807 // Register an interrupt handler for timer A if requested.
\r
809 if(ulTimer & TIMER_A)
\r
812 // Register the interrupt handler.
\r
814 IntRegister(ulBase, pfnHandler);
\r
817 // Enable the interrupt.
\r
823 // Register an interrupt handler for timer B if requested.
\r
825 if(ulTimer & TIMER_B)
\r
828 // Register the interrupt handler.
\r
830 IntRegister(ulBase + 1, pfnHandler);
\r
833 // Enable the interrupt.
\r
835 IntEnable(ulBase + 1);
\r
840 //*****************************************************************************
\r
842 //! Unregisters an interrupt handler for the timer interrupt.
\r
844 //! \param ulBase is the base address of the timer module.
\r
845 //! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
\r
846 //! \b TIMER_B, or \b TIMER_BOTH.
\r
848 //! This function will clear the handler to be called when a timer interrupt
\r
849 //! occurs. This will also mask off the interrupt in the interrupt controller
\r
850 //! so that the interrupt handler no longer is called.
\r
852 //! \sa IntRegister() for important information about registering interrupt
\r
857 //*****************************************************************************
\r
858 #if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
860 TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer)
\r
863 // Check the arguments.
\r
865 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
866 (ulBase == TIMER2_BASE));
\r
867 ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
\r
868 (ulTimer == TIMER_BOTH));
\r
871 // Get the interrupt number for this timer module.
\r
873 ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :
\r
874 ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A));
\r
877 // Unregister the interrupt handler for timer A if requested.
\r
879 if(ulTimer & TIMER_A)
\r
882 // Disable the interrupt.
\r
884 IntDisable(ulBase);
\r
887 // Unregister the interrupt handler.
\r
889 IntUnregister(ulBase);
\r
893 // Unregister the interrupt handler for timer B if requested.
\r
895 if(ulTimer & TIMER_B)
\r
898 // Disable the interrupt.
\r
900 IntDisable(ulBase + 1);
\r
903 // Unregister the interrupt handler.
\r
905 IntUnregister(ulBase + 1);
\r
910 //*****************************************************************************
\r
912 //! Enables individual timer interrupt sources.
\r
914 //! \param ulBase is the base address of the timer module.
\r
915 //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
\r
917 //! Enables the indicated timer interrupt sources. Only the sources that are
\r
918 //! enabled can be reflected to the processor interrupt; disabled sources have
\r
919 //! no effect on the processor.
\r
921 //! The parameter \e ulIntFlags must be the logical OR of any combination of
\r
924 //! - TIMER_CAPB_EVENT - Capture B event interrupt
\r
925 //! - TIMER_CAPB_MATCH - Capture B match interrupt
\r
926 //! - TIMER_TIMB_TIMEOUT - Timer B timeout interrupt
\r
927 //! - TIMER_RTC_MATCH - RTC interrupt mask
\r
928 //! - TIMER_CAPA_EVENT - Capture A event interrupt
\r
929 //! - TIMER_CAPA_MATCH - Capture A match interrupt
\r
930 //! - TIMER_TIMA_TIMEOUT - Timer A timeout interrupt
\r
934 //*****************************************************************************
\r
935 #if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
937 TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
\r
940 // Check the arguments.
\r
942 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
943 (ulBase == TIMER2_BASE));
\r
946 // Enable the specified interrupts.
\r
948 HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags;
\r
952 //*****************************************************************************
\r
954 //! Disables individual timer interrupt sources.
\r
956 //! \param ulBase is the base address of the timer module.
\r
957 //! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
\r
959 //! Disables the indicated timer interrupt sources. Only the sources that are
\r
960 //! enabled can be reflected to the processor interrupt; disabled sources have
\r
961 //! no effect on the processor.
\r
963 //! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags
\r
964 //! parameter to TimerIntEnable().
\r
968 //*****************************************************************************
\r
969 #if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
971 TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
\r
974 // Check the arguments.
\r
976 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
977 (ulBase == TIMER2_BASE));
\r
980 // Disable the specified interrupts.
\r
982 HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags);
\r
986 //*****************************************************************************
\r
988 //! Gets the current interrupt status.
\r
990 //! \param ulBase is the base address of the timer module.
\r
991 //! \param bMasked is false if the raw interrupt status is required and true if
\r
992 //! the masked interrupt status is required.
\r
994 //! This returns the interrupt status for the timer module. Either the raw
\r
995 //! interrupt status or the status of interrupts that are allowed to reflect to
\r
996 //! the processor can be returned.
\r
998 //! \return The current interrupt status, enumerated as a bit field of
\r
999 //! values described in TimerIntEnable().
\r
1001 //*****************************************************************************
\r
1002 #if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1004 TimerIntStatus(unsigned long ulBase, tBoolean bMasked)
\r
1007 // Check the arguments.
\r
1009 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
1010 (ulBase == TIMER2_BASE));
\r
1013 // Return either the interrupt status or the raw interrupt status as
\r
1016 return(bMasked ? HWREG(ulBase + TIMER_O_MIS) :
\r
1017 HWREG(ulBase + TIMER_O_RIS));
\r
1021 //*****************************************************************************
\r
1023 //! Clears timer interrupt sources.
\r
1025 //! \param ulBase is the base address of the timer module.
\r
1026 //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
\r
1028 //! The specified timer interrupt sources are cleared, so that they no longer
\r
1029 //! assert. This must be done in the interrupt handler to keep it from being
\r
1030 //! called again immediately upon exit.
\r
1032 //! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags
\r
1033 //! parameter to TimerIntEnable().
\r
1037 //*****************************************************************************
\r
1038 #if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1040 TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags)
\r
1043 // Check the arguments.
\r
1045 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
1046 (ulBase == TIMER2_BASE));
\r
1049 // Clear the requested interrupt sources.
\r
1051 HWREG(ulBase + TIMER_O_ICR) = ulIntFlags;
\r
1055 //*****************************************************************************
\r
1057 //! Puts the timer into its reset state.
\r
1059 //! \param ulBase is the base address of the timer module.
\r
1061 //! The specified timer is disabled, and all its interrupts are disabled,
\r
1062 //! cleared, and unregistered. Then the timer registers are set to their reset
\r
1067 //*****************************************************************************
\r
1068 #if defined(GROUP_quiesce) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1070 TimerQuiesce(unsigned long ulBase)
\r
1073 // Check the arguments.
\r
1075 ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
\r
1076 (ulBase == TIMER2_BASE));
\r
1079 // Disable the timer.
\r
1081 HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL;
\r
1084 // Disable all the timer interrupts.
\r
1086 HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR;
\r
1089 // Clear all the timer interrupts.
\r
1091 HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF;
\r
1094 // Unregister the interrupt handler. This also disables interrupts to the
\r
1097 TimerIntUnregister(ulBase, TIMER_BOTH);
\r
1100 // Set all the registers to their reset value.
\r
1102 HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG;
\r
1103 HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR;
\r
1104 HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR;
\r
1105 HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS;
\r
1106 HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS;
\r
1107 HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR;
\r
1108 HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR;
\r
1109 HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR;
\r
1110 HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR;
\r
1111 HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR;
\r
1112 HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR;
\r
1113 HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR;
\r
1114 HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR;
\r
1115 HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR;
\r
1116 HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR;
\r
1120 //*****************************************************************************
\r
1122 // Close the Doxygen group.
\r
1125 //*****************************************************************************
\r