2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Scheduler includes. */
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29 #include "FreeRTOS.h"
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31 /* Demo includes. */
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32 #include "IntQueueTimer.h"
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33 #include "IntQueue.h"
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35 /* Library includes. */
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36 #include "hw_ints.h"
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37 #include "hw_memmap.h"
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38 #include "hw_types.h"
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39 #include "interrupt.h"
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41 #include "lmi_timer.h"
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43 #define tmrTIMER_2_FREQUENCY ( 2000UL )
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44 #define tmrTIMER_3_FREQUENCY ( 2001UL )
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46 void vInitialiseTimerForIntQueueTest( void )
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48 unsigned long ulFrequency;
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50 /* Timer 2 and 3 are utilised for this test. */
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51 SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER2 );
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52 SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER3 );
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53 TimerConfigure( TIMER2_BASE, TIMER_CFG_32_BIT_PER );
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54 TimerConfigure( TIMER3_BASE, TIMER_CFG_32_BIT_PER );
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56 /* Set the timer interrupts to be above the kernel. The interrupts are
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57 assigned different priorities so they nest with each other. */
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58 IntPrioritySet( INT_TIMER2A, configMAX_SYSCALL_INTERRUPT_PRIORITY + ( 1 << 5 ) ); /* Shift left 5 as only the top 3 bits are implemented. */
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59 IntPrioritySet( INT_TIMER3A, configMAX_SYSCALL_INTERRUPT_PRIORITY );
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61 /* Ensure interrupts do not start until the scheduler is running. */
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62 portDISABLE_INTERRUPTS();
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64 /* The rate at which the timers will interrupt. */
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65 ulFrequency = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;
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66 TimerLoadSet( TIMER2_BASE, TIMER_A, ulFrequency );
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67 IntEnable( INT_TIMER2A );
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68 TimerIntEnable( TIMER2_BASE, TIMER_TIMA_TIMEOUT );
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70 /* The rate at which the timers will interrupt. */
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71 ulFrequency = configCPU_CLOCK_HZ / tmrTIMER_3_FREQUENCY;
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72 TimerLoadSet( TIMER3_BASE, TIMER_A, ulFrequency );
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73 IntEnable( INT_TIMER3A );
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74 TimerIntEnable( TIMER3_BASE, TIMER_TIMA_TIMEOUT );
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76 /* Enable both timers. */
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77 TimerEnable( TIMER2_BASE, TIMER_A );
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78 TimerEnable( TIMER3_BASE, TIMER_A );
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80 /*-----------------------------------------------------------*/
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82 void vT2InterruptHandler( void )
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84 TimerIntClear( TIMER2_BASE, TIMER_TIMA_TIMEOUT );
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85 portEND_SWITCHING_ISR( xFirstTimerHandler() );
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87 /*-----------------------------------------------------------*/
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89 void vT3InterruptHandler( void )
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91 TimerIntClear( TIMER3_BASE, TIMER_TIMA_TIMEOUT );
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92 portEND_SWITCHING_ISR( xSecondTimerHandler() );
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