2 FreeRTOS V7.5.1 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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6 ***************************************************************************
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8 * FreeRTOS provides completely free yet professionally developed, *
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9 * robust, strictly quality controlled, supported, and cross *
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10 * platform software that has become a de facto standard. *
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12 * Help yourself get started quickly and support the FreeRTOS *
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13 * project by purchasing a FreeRTOS tutorial book, reference *
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14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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18 ***************************************************************************
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20 This file is part of the FreeRTOS distribution.
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22 FreeRTOS is free software; you can redistribute it and/or modify it under
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23 the terms of the GNU General Public License (version 2) as published by the
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24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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26 >>! NOTE: The modification to the GPL is included to allow you to distribute
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27 >>! a combined work that includes FreeRTOS without being obliged to provide
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28 >>! the source code for proprietary components outside of the FreeRTOS
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31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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34 link: http://www.freertos.org/a00114.html
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38 ***************************************************************************
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40 * Having a problem? Start by reading the FAQ "My application does *
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41 * not run, what could be wrong?" *
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43 * http://www.FreeRTOS.org/FAQHelp.html *
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45 ***************************************************************************
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47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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48 license and Real Time Engineers Ltd. contact details.
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50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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56 licenses offer ticketed support, indemnification and middleware.
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58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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59 engineered and independently SIL3 certified version for use in safety and
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60 mission critical applications that require provable dependability.
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65 /* Originally adapted from file written by Andreas Dannenberg. Supplied with permission. */
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67 /* Kernel includes. */
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68 #include "FreeRTOS.h"
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72 /* Hardware specific includes. */
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73 #include "EthDev_LPC17xx.h"
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75 /* Time to wait between each inspection of the link status. */
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76 #define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_RATE_MS )
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78 /* Short delay used in several places during the initialisation process. */
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79 #define emacSHORT_DELAY ( 2 )
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81 /* Hardware specific bit definitions. */
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82 #define emacLINK_ESTABLISHED ( 0x0001 )
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83 #define emacFULL_DUPLEX_ENABLED ( 0x0004 )
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84 #define emac10BASE_T_MODE ( 0x0002 )
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85 #define emacPINSEL2_VALUE 0x50150105
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87 /* If no buffers are available, then wait this long before looking again.... */
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88 #define emacBUFFER_WAIT_DELAY ( 3 / portTICK_RATE_MS )
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90 /* ...and don't look more than this many times. */
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91 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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93 /* Index to the Tx descriptor that is always used first for every Tx. The second
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94 descriptor is then used to re-send in order to speed up the uIP Tx process. */
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95 #define emacTX_DESC_INDEX ( 0 )
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97 #define PCONP_PCENET 0x40000000
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98 /*-----------------------------------------------------------*/
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101 * Configure both the Rx and Tx descriptors during the init process.
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103 static void prvInitDescriptors( void );
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106 * Setup the IO and peripherals required for Ethernet communication.
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108 static void prvSetupEMACHardware( void );
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111 * Control the auto negotiate process.
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113 static void prvConfigurePHY( void );
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116 * Wait for a link to be established, then setup the PHY according to the link
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119 static long prvSetupLinkStatus( void );
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122 * Search the pool of buffers to find one that is free. If a buffer is found
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123 * mark it as in use before returning its address.
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125 static unsigned char *prvGetNextBuffer( void );
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128 * Return an allocated buffer to the pool of free buffers.
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130 static void prvReturnBuffer( unsigned char *pucBuffer );
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133 * Send lValue to the lPhyReg within the PHY.
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135 static long prvWritePHY( long lPhyReg, long lValue );
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138 * Read a value from ucPhyReg within the PHY. *plStatus will be set to
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139 * pdFALSE if there is an error.
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141 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus );
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143 /*-----------------------------------------------------------*/
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145 /* The semaphore used to wake the uIP task when data arrives. */
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146 extern xSemaphoreHandle xEMACSemaphore;
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148 /* Each ucBufferInUse index corresponds to a position in the pool of buffers.
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149 If the index contains a 1 then the buffer within pool is in use, if it
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150 contains a 0 then the buffer is free. */
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151 static unsigned char ucBufferInUse[ ETH_NUM_BUFFERS ] = { pdFALSE };
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153 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
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154 allocated within this file. */
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155 unsigned char * uip_buf;
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157 /* Store the length of the data being sent so the data can be sent twice. The
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158 value will be set back to 0 once the data has been sent twice. */
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159 static unsigned short usSendLen = 0;
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161 /*-----------------------------------------------------------*/
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163 long lEMACInit( void )
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165 long lReturn = pdPASS;
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166 unsigned long ulID1, ulID2;
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168 /* Reset peripherals, configure port pins and registers. */
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169 prvSetupEMACHardware();
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171 /* Check the PHY part number is as expected. */
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172 ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );
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173 ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );
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174 if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFF0UL ) ) == DP83848C_ID )
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176 /* Set the Ethernet MAC Address registers */
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177 LPC_EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
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178 LPC_EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
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179 LPC_EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
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181 /* Initialize Tx and Rx DMA Descriptors */
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182 prvInitDescriptors();
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184 /* Receive broadcast and perfect match packets */
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185 LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
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187 /* Setup the PHY. */
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195 /* Check the link status. */
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196 if( lReturn == pdPASS )
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198 lReturn = prvSetupLinkStatus();
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201 if( lReturn == pdPASS )
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203 /* Initialise uip_buf to ensure it points somewhere valid. */
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204 uip_buf = prvGetNextBuffer();
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206 /* Reset all interrupts */
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207 LPC_EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );
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209 /* Enable receive and transmit mode of MAC Ethernet core */
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210 LPC_EMAC->Command |= ( CR_RX_EN | CR_TX_EN );
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211 LPC_EMAC->MAC1 |= MAC1_REC_EN;
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216 /*-----------------------------------------------------------*/
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218 static unsigned char *prvGetNextBuffer( void )
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221 unsigned char *pucReturn = NULL;
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222 unsigned long ulAttempts = 0;
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224 while( pucReturn == NULL )
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226 /* Look through the buffers to find one that is not in use by
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228 for( x = 0; x < ETH_NUM_BUFFERS; x++ )
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230 if( ucBufferInUse[ x ] == pdFALSE )
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232 ucBufferInUse[ x ] = pdTRUE;
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233 pucReturn = ( unsigned char * ) ETH_BUF( x );
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238 /* Was a buffer found? */
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239 if( pucReturn == NULL )
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243 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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248 /* Wait then look again. */
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249 vTaskDelay( emacBUFFER_WAIT_DELAY );
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255 /*-----------------------------------------------------------*/
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257 static void prvInitDescriptors( void )
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259 long x, lNextBuffer = 0;
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261 for( x = 0; x < NUM_RX_FRAG; x++ )
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263 /* Allocate the next Ethernet buffer to this descriptor. */
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264 RX_DESC_PACKET( x ) = ETH_BUF( lNextBuffer );
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265 RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
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266 RX_STAT_INFO( x ) = 0;
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267 RX_STAT_HASHCRC( x ) = 0;
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269 /* The Ethernet buffer is now in use. */
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270 ucBufferInUse[ lNextBuffer ] = pdTRUE;
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274 /* Set EMAC Receive Descriptor Registers. */
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275 LPC_EMAC->RxDescriptor = RX_DESC_BASE;
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276 LPC_EMAC->RxStatus = RX_STAT_BASE;
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277 LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;
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279 /* Rx Descriptors Point to 0 */
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280 LPC_EMAC->RxConsumeIndex = 0;
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282 /* A buffer is not allocated to the Tx descriptors until they are actually
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284 for( x = 0; x < NUM_TX_FRAG; x++ )
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286 TX_DESC_PACKET( x ) = ( unsigned long ) NULL;
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287 TX_DESC_CTRL( x ) = 0;
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288 TX_STAT_INFO( x ) = 0;
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291 /* Set EMAC Transmit Descriptor Registers. */
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292 LPC_EMAC->TxDescriptor = TX_DESC_BASE;
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293 LPC_EMAC->TxStatus = TX_STAT_BASE;
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294 LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;
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296 /* Tx Descriptors Point to 0 */
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297 LPC_EMAC->TxProduceIndex = 0;
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299 /*-----------------------------------------------------------*/
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301 static void prvSetupEMACHardware( void )
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306 /* Enable P1 Ethernet Pins. */
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307 LPC_PINCON->PINSEL2 = emacPINSEL2_VALUE;
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308 LPC_PINCON->PINSEL3 = ( LPC_PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;
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310 /* Power Up the EMAC controller. */
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311 LPC_SC->PCONP |= PCONP_PCENET;
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312 vTaskDelay( emacSHORT_DELAY );
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314 /* Reset all EMAC internal modules. */
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315 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
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316 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
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318 /* A short delay after reset. */
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319 vTaskDelay( emacSHORT_DELAY );
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321 /* Initialize MAC control registers. */
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322 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
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323 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
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324 LPC_EMAC->MAXF = ETH_MAX_FLEN;
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325 LPC_EMAC->CLRT = CLRT_DEF;
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326 LPC_EMAC->IPGR = IPGR_DEF;
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328 /* Enable Reduced MII interface. */
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329 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
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331 /* Reset Reduced MII Logic. */
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332 LPC_EMAC->SUPP = SUPP_RES_RMII;
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333 vTaskDelay( emacSHORT_DELAY );
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334 LPC_EMAC->SUPP = 0;
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336 /* Put the PHY in reset mode */
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337 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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338 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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340 /* Wait for hardware reset to end. */
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341 for( x = 0; x < 100; x++ )
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343 vTaskDelay( emacSHORT_DELAY * 5 );
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344 us = prvReadPHY( PHY_REG_BMCR, &lDummy );
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345 if( !( us & MCFG_RES_MII ) )
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347 /* Reset complete */
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352 /*-----------------------------------------------------------*/
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354 static void prvConfigurePHY( void )
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359 /* Auto negotiate the configuration. */
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360 if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
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362 vTaskDelay( emacSHORT_DELAY * 5 );
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364 for( x = 0; x < 10; x++ )
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366 us = prvReadPHY( PHY_REG_BMSR, &lDummy );
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368 if( us & PHY_AUTO_NEG_COMPLETE )
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373 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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377 /*-----------------------------------------------------------*/
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379 static long prvSetupLinkStatus( void )
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381 long lReturn = pdFAIL, x;
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382 unsigned short usLinkStatus;
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384 /* Wait with timeout for the link to be established. */
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385 for( x = 0; x < 10; x++ )
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387 usLinkStatus = prvReadPHY( PHY_REG_STS, &lReturn );
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388 if( usLinkStatus & emacLINK_ESTABLISHED )
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390 /* Link is established. */
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395 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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398 if( lReturn == pdPASS )
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400 /* Configure Full/Half Duplex mode. */
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401 if( usLinkStatus & emacFULL_DUPLEX_ENABLED )
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403 /* Full duplex is enabled. */
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404 LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
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405 LPC_EMAC->Command |= CR_FULL_DUP;
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406 LPC_EMAC->IPGT = IPGT_FULL_DUP;
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410 /* Half duplex mode. */
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411 LPC_EMAC->IPGT = IPGT_HALF_DUP;
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414 /* Configure 100MBit/10MBit mode. */
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415 if( usLinkStatus & emac10BASE_T_MODE )
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418 LPC_EMAC->SUPP = 0;
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422 /* 100MBit mode. */
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423 LPC_EMAC->SUPP = SUPP_SPEED;
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429 /*-----------------------------------------------------------*/
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431 static void prvReturnBuffer( unsigned char *pucBuffer )
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435 /* Return a buffer to the pool of free buffers. */
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436 for( ul = 0; ul < ETH_NUM_BUFFERS; ul++ )
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438 if( ETH_BUF( ul ) == ( unsigned long ) pucBuffer )
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440 ucBufferInUse[ ul ] = pdFALSE;
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445 /*-----------------------------------------------------------*/
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447 unsigned long ulGetEMACRxData( void )
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449 unsigned long ulLen = 0;
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452 if( LPC_EMAC->RxProduceIndex != LPC_EMAC->RxConsumeIndex )
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454 /* Mark the current buffer as free as uip_buf is going to be set to
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455 the buffer that contains the received data. */
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456 prvReturnBuffer( uip_buf );
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458 ulLen = ( RX_STAT_INFO( LPC_EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;
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459 uip_buf = ( unsigned char * ) RX_DESC_PACKET( LPC_EMAC->RxConsumeIndex );
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461 /* Allocate a new buffer to the descriptor. */
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462 RX_DESC_PACKET( LPC_EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();
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464 /* Move the consume index onto the next position, ensuring it wraps to
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465 the beginning at the appropriate place. */
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466 lIndex = LPC_EMAC->RxConsumeIndex;
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469 if( lIndex >= NUM_RX_FRAG )
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474 LPC_EMAC->RxConsumeIndex = lIndex;
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479 /*-----------------------------------------------------------*/
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481 void vSendEMACTxData( unsigned short usTxDataLen )
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483 unsigned long ulAttempts = 0UL;
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485 /* Check to see if the Tx descriptor is free, indicated by its buffer being
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487 while( TX_DESC_PACKET( emacTX_DESC_INDEX ) != ( unsigned long ) NULL )
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489 /* Wait for the Tx descriptor to become available. */
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490 vTaskDelay( emacBUFFER_WAIT_DELAY );
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493 if( ulAttempts > emacBUFFER_WAIT_ATTEMPTS )
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495 /* Something has gone wrong as the Tx descriptor is still in use.
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496 Clear it down manually, the data it was sending will probably be
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498 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
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503 /* Setup the Tx descriptor for transmission. Remember the length of the
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504 data being sent so the second descriptor can be used to send it again from
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506 usSendLen = usTxDataLen;
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507 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;
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508 TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );
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509 LPC_EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );
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511 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
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512 uip_buf = prvGetNextBuffer();
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514 /*-----------------------------------------------------------*/
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516 static long prvWritePHY( long lPhyReg, long lValue )
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518 const long lMaxTime = 10;
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521 LPC_EMAC->MADR = DP83848C_DEF_ADR | lPhyReg;
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522 LPC_EMAC->MWTD = lValue;
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525 for( x = 0; x < lMaxTime; x++ )
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527 if( ( LPC_EMAC->MIND & MIND_BUSY ) == 0 )
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529 /* Operation has finished. */
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533 vTaskDelay( emacSHORT_DELAY );
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545 /*-----------------------------------------------------------*/
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547 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
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550 const long lMaxTime = 10;
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552 LPC_EMAC->MADR = DP83848C_DEF_ADR | ucPhyReg;
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553 LPC_EMAC->MCMD = MCMD_READ;
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555 for( x = 0; x < lMaxTime; x++ )
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557 /* Operation has finished. */
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558 if( ( LPC_EMAC->MIND & MIND_BUSY ) == 0 )
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563 vTaskDelay( emacSHORT_DELAY );
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566 LPC_EMAC->MCMD = 0;
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568 if( x >= lMaxTime )
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570 *plStatus = pdFAIL;
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573 return( LPC_EMAC->MRDD );
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575 /*-----------------------------------------------------------*/
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577 void vEMAC_ISR( void )
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579 unsigned long ulStatus;
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580 long lHigherPriorityTaskWoken = pdFALSE;
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582 ulStatus = LPC_EMAC->IntStatus;
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584 /* Clear the interrupt. */
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585 LPC_EMAC->IntClear = ulStatus;
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587 if( ulStatus & INT_RX_DONE )
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589 /* Ensure the uIP task is not blocked as data has arrived. */
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590 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
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593 if( ulStatus & INT_TX_DONE )
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595 if( usSendLen > 0 )
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597 /* Send the data again, using the second descriptor. As there are
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598 only two descriptors the index is set back to 0. */
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599 TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );
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600 TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );
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601 LPC_EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );
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603 /* This is the second Tx so set usSendLen to 0 to indicate that the
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604 Tx descriptors will be free again. */
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609 /* The Tx buffer is no longer required. */
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610 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
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611 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) NULL;
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615 portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
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