4 /* System Control Block (SCB) includes:
\r
5 Flash Accelerator Module, Clocking and Power Control, External Interrupts,
\r
6 Reset, System Control and Status
\r
8 #define SCB_BASE_ADDR 0x400FC000
\r
10 #define PCONP_PCTIM0 0x00000002
\r
11 #define PCONP_PCTIM1 0x00000004
\r
12 #define PCONP_PCUART0 0x00000008
\r
13 #define PCONP_PCUART1 0x00000010
\r
14 #define PCONP_PCPWM1 0x00000040
\r
15 #define PCONP_PCI2C0 0x00000080
\r
16 #define PCONP_PCSPI 0x00000100
\r
17 #define PCONP_PCRTC 0x00000200
\r
18 #define PCONP_PCSSP1 0x00000400
\r
19 #define PCONP_PCAD 0x00001000
\r
20 #define PCONP_PCCAN1 0x00002000
\r
21 #define PCONP_PCCAN2 0x00004000
\r
22 #define PCONP_PCGPIO 0x00008000
\r
23 #define PCONP_PCRIT 0x00010000
\r
24 #define PCONP_PCMCPWM 0x00020000
\r
25 #define PCONP_PCQEI 0x00040000
\r
26 #define PCONP_PCI2C1 0x00080000
\r
27 #define PCONP_PCSSP0 0x00200000
\r
28 #define PCONP_PCTIM2 0x00400000
\r
29 #define PCONP_PCTIM3 0x00800000
\r
30 #define PCONP_PCUART2 0x01000000
\r
31 #define PCONP_PCUART3 0x02000000
\r
32 #define PCONP_PCI2C2 0x04000000
\r
33 #define PCONP_PCI2S 0x08000000
\r
34 #define PCONP_PCGPDMA 0x20000000
\r
35 #define PCONP_PCENET 0x40000000
\r
36 #define PCONP_PCUSB 0x80000000
\r
38 #define PLLCON_PLLE 0x00000001
\r
39 #define PLLCON_PLLC 0x00000002
\r
40 #define PLLCON_MASK 0x00000003
\r
42 #define PLLCFG_MUL1 0x00000000
\r
43 #define PLLCFG_MUL2 0x00000001
\r
44 #define PLLCFG_MUL3 0x00000002
\r
45 #define PLLCFG_MUL4 0x00000003
\r
46 #define PLLCFG_MUL5 0x00000004
\r
47 #define PLLCFG_MUL6 0x00000005
\r
48 #define PLLCFG_MUL7 0x00000006
\r
49 #define PLLCFG_MUL8 0x00000007
\r
50 #define PLLCFG_MUL9 0x00000008
\r
51 #define PLLCFG_MUL10 0x00000009
\r
52 #define PLLCFG_MUL11 0x0000000A
\r
53 #define PLLCFG_MUL12 0x0000000B
\r
54 #define PLLCFG_MUL13 0x0000000C
\r
55 #define PLLCFG_MUL14 0x0000000D
\r
56 #define PLLCFG_MUL15 0x0000000E
\r
57 #define PLLCFG_MUL16 0x0000000F
\r
58 #define PLLCFG_MUL17 0x00000010
\r
59 #define PLLCFG_MUL18 0x00000011
\r
60 #define PLLCFG_MUL19 0x00000012
\r
61 #define PLLCFG_MUL20 0x00000013
\r
62 #define PLLCFG_MUL21 0x00000014
\r
63 #define PLLCFG_MUL22 0x00000015
\r
64 #define PLLCFG_MUL23 0x00000016
\r
65 #define PLLCFG_MUL24 0x00000017
\r
66 #define PLLCFG_MUL25 0x00000018
\r
67 #define PLLCFG_MUL26 0x00000019
\r
68 #define PLLCFG_MUL27 0x0000001A
\r
69 #define PLLCFG_MUL28 0x0000001B
\r
70 #define PLLCFG_MUL29 0x0000001C
\r
71 #define PLLCFG_MUL30 0x0000001D
\r
72 #define PLLCFG_MUL31 0x0000001E
\r
73 #define PLLCFG_MUL32 0x0000001F
\r
74 #define PLLCFG_MUL33 0x00000020
\r
75 #define PLLCFG_MUL34 0x00000021
\r
76 #define PLLCFG_MUL35 0x00000022
\r
77 #define PLLCFG_MUL36 0x00000023
\r
79 #define PLLCFG_DIV1 0x00000000
\r
80 #define PLLCFG_DIV2 0x00010000
\r
81 #define PLLCFG_DIV3 0x00020000
\r
82 #define PLLCFG_DIV4 0x00030000
\r
83 #define PLLCFG_DIV5 0x00040000
\r
84 #define PLLCFG_DIV6 0x00050000
\r
85 #define PLLCFG_DIV7 0x00060000
\r
86 #define PLLCFG_DIV8 0x00070000
\r
87 #define PLLCFG_DIV9 0x00080000
\r
88 #define PLLCFG_DIV10 0x00090000
\r
89 #define PLLCFG_MASK 0x00FF7FFF
\r
91 #define PLLSTAT_MSEL_MASK 0x00007FFF
\r
92 #define PLLSTAT_NSEL_MASK 0x00FF0000
\r
94 #define PLLSTAT_PLLE (1 << 24)
\r
95 #define PLLSTAT_PLLC (1 << 25)
\r
96 #define PLLSTAT_PLOCK (1 << 26)
\r
98 #define PLLFEED_FEED1 0x000000AA
\r
99 #define PLLFEED_FEED2 0x00000055
\r
101 #define NVIC_IRQ_WDT 0u // IRQ0, exception number 16
\r
102 #define NVIC_IRQ_TIMER0 1u // IRQ1, exception number 17
\r
103 #define NVIC_IRQ_TIMER1 2u // IRQ2, exception number 18
\r
104 #define NVIC_IRQ_TIMER2 3u // IRQ3, exception number 19
\r
105 #define NVIC_IRQ_TIMER3 4u // IRQ4, exception number 20
\r
106 #define NVIC_IRQ_UART0 5u // IRQ5, exception number 21
\r
107 #define NVIC_IRQ_UART1 6u // IRQ6, exception number 22
\r
108 #define NVIC_IRQ_UART2 7u // IRQ7, exception number 23
\r
109 #define NVIC_IRQ_UART3 8u // IRQ8, exception number 24
\r
110 #define NVIC_IRQ_PWM1 9u // IRQ9, exception number 25
\r
111 #define NVIC_IRQ_I2C0 10u // IRQ10, exception number 26
\r
112 #define NVIC_IRQ_I2C1 11u // IRQ11, exception number 27
\r
113 #define NVIC_IRQ_I2C2 12u // IRQ12, exception number 28
\r
114 #define NVIC_IRQ_SPI 13u // IRQ13, exception number 29
\r
115 #define NVIC_IRQ_SSP0 14u // IRQ14, exception number 30
\r
116 #define NVIC_IRQ_SSP1 15u // IRQ15, exception number 31
\r
117 #define NVIC_IRQ_PLL0 16u // IRQ16, exception number 32
\r
118 #define NVIC_IRQ_RTC 17u // IRQ17, exception number 33
\r
119 #define NVIC_IRQ_EINT0 18u // IRQ18, exception number 34
\r
120 #define NVIC_IRQ_EINT1 19u // IRQ19, exception number 35
\r
121 #define NVIC_IRQ_EINT2 20u // IRQ20, exception number 36
\r
122 #define NVIC_IRQ_EINT3 21u // IRQ21, exception number 37
\r
123 #define NVIC_IRQ_ADC 22u // IRQ22, exception number 38
\r
124 #define NVIC_IRQ_BOD 23u // IRQ23, exception number 39
\r
125 #define NVIC_IRQ_USB 24u // IRQ24, exception number 40
\r
126 #define NVIC_IRQ_CAN 25u // IRQ25, exception number 41
\r
127 #define NVIC_IRQ_GPDMA 26u // IRQ26, exception number 42
\r
128 #define NVIC_IRQ_I2S 27u // IRQ27, exception number 43
\r
129 #define NVIC_IRQ_ETHERNET 28u // IRQ28, exception number 44
\r
130 #define NVIC_IRQ_RIT 29u // IRQ29, exception number 45
\r
131 #define NVIC_IRQ_MCPWM 30u // IRQ30, exception number 46
\r
132 #define NVIC_IRQ_QE 31u // IRQ31, exception number 47
\r
133 #define NVIC_IRQ_PLL1 32u // IRQ32, exception number 48
\r
134 #define NVIC_IRQ_USB_ACT 33u // IRQ33, exception number 49
\r
135 #define NVIC_IRQ_CAN_ACT 34u // IRQ34, exception number 50
\r
138 #endif // __LPC17xx_H
\r
141 #ifndef CMSIS_17xx_H
\r
142 #define CMSIS_17xx_H
\r
144 /******************************************************************************
\r
146 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
\r
147 * NXP LPC17xx Device Series
\r
149 * @date: 14th May 2009
\r
150 *----------------------------------------------------------------------------
\r
152 * Copyright (C) 2008 ARM Limited. All rights reserved.
\r
154 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
\r
155 * processor based microcontrollers. This file can be freely distributed
\r
156 * within development tools that are supporting such ARM based processors.
\r
158 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
\r
159 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
\r
160 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
\r
161 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
\r
162 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
\r
164 ******************************************************************************/
\r
167 #ifndef __LPC17xx_H__
\r
168 #define __LPC17xx_H__
\r
171 * ==========================================================================
\r
172 * ---------- Interrupt Number Definition -----------------------------------
\r
173 * ==========================================================================
\r
178 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
\r
179 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
\r
180 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
\r
181 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
\r
182 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
\r
183 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
\r
184 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
\r
185 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
\r
186 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
\r
188 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
\r
189 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
\r
190 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
\r
191 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
\r
192 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
\r
193 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
\r
194 UART0_IRQn = 5, /*!< UART0 Interrupt */
\r
195 UART1_IRQn = 6, /*!< UART1 Interrupt */
\r
196 UART2_IRQn = 7, /*!< UART2 Interrupt */
\r
197 UART3_IRQn = 8, /*!< UART3 Interrupt */
\r
198 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
\r
199 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
\r
200 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
\r
201 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
\r
202 SPI_IRQn = 13, /*!< SPI Interrupt */
\r
203 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
\r
204 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
\r
205 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
\r
206 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
\r
207 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
\r
208 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
\r
209 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
\r
210 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
\r
211 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
\r
212 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
\r
213 USB_IRQn = 24, /*!< USB Interrupt */
\r
214 CAN_IRQn = 25, /*!< CAN Interrupt */
\r
215 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
\r
216 I2S_IRQn = 27, /*!< I2S Interrupt */
\r
217 ENET_IRQn = 28, /*!< Ethernet Interrupt */
\r
218 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
\r
219 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
\r
220 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
\r
221 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
\r
226 * ==========================================================================
\r
227 * ----------- Processor and Core Peripheral Section ------------------------
\r
228 * ==========================================================================
\r
231 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
\r
232 #define __MPU_PRESENT 1 /*!< MPU present or not */
\r
233 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
\r
234 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
\r
237 //#include "..\core_cm3.h" /* Cortex-M3 processor and core peripherals */
\r
238 #include "core_cm3.h"
\r
239 #include "system_LPC17xx.h" /* System Header */
\r
244 * Initialize the system clock
\r
249 * @brief Setup the microcontroller system.
\r
250 * Initialize the System and update the SystemFrequency variable.
\r
252 extern void SystemInit (void);
\r
255 /******************************************************************************/
\r
256 /* Device Specific Peripheral registers structures */
\r
257 /******************************************************************************/
\r
259 /*------------- System Control (SC) ------------------------------------------*/
\r
262 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
\r
263 uint32_t RESERVED0[31];
\r
264 __IO uint32_t PLL0CON; /* Clocking and Power Control */
\r
265 __IO uint32_t PLL0CFG;
\r
266 __I uint32_t PLL0STAT;
\r
267 __O uint32_t PLL0FEED;
\r
268 uint32_t RESERVED1[4];
\r
269 __IO uint32_t PLL1CON;
\r
270 __IO uint32_t PLL1CFG;
\r
271 __I uint32_t PLL1STAT;
\r
272 __O uint32_t PLL1FEED;
\r
273 uint32_t RESERVED2[4];
\r
274 __IO uint32_t PCON;
\r
275 __IO uint32_t PCONP;
\r
276 uint32_t RESERVED3[15];
\r
277 __IO uint32_t CCLKCFG;
\r
278 __IO uint32_t USBCLKCFG;
\r
279 __IO uint32_t CLKSRCSEL;
\r
280 uint32_t RESERVED4[12];
\r
281 __IO uint32_t EXTINT; /* External Interrupts */
\r
282 uint32_t RESERVED5;
\r
283 __IO uint32_t EXTMODE;
\r
284 __IO uint32_t EXTPOLAR;
\r
285 uint32_t RESERVED6[12];
\r
286 __IO uint32_t RSID; /* Reset */
\r
287 uint32_t RESERVED7[7];
\r
288 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
\r
289 __IO uint32_t IRCTRIM; /* Clock Dividers */
\r
290 __IO uint32_t PCLKSEL0;
\r
291 __IO uint32_t PCLKSEL1;
\r
292 uint32_t RESERVED8[4];
\r
293 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
\r
294 uint32_t RESERVED9;
\r
295 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
\r
298 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
\r
301 __IO uint32_t PINSEL0;
\r
302 __IO uint32_t PINSEL1;
\r
303 __IO uint32_t PINSEL2;
\r
304 __IO uint32_t PINSEL3;
\r
305 __IO uint32_t PINSEL4;
\r
306 __IO uint32_t PINSEL5;
\r
307 __IO uint32_t PINSEL6;
\r
308 __IO uint32_t PINSEL7;
\r
309 __IO uint32_t PINSEL8;
\r
310 __IO uint32_t PINSEL9;
\r
311 __IO uint32_t PINSEL10;
\r
312 uint32_t RESERVED0[5];
\r
313 __IO uint32_t PINMODE0;
\r
314 __IO uint32_t PINMODE1;
\r
315 __IO uint32_t PINMODE2;
\r
316 __IO uint32_t PINMODE3;
\r
317 __IO uint32_t PINMODE4;
\r
318 __IO uint32_t PINMODE5;
\r
319 __IO uint32_t PINMODE6;
\r
320 __IO uint32_t PINMODE7;
\r
321 __IO uint32_t PINMODE8;
\r
322 __IO uint32_t PINMODE9;
\r
323 __IO uint32_t PINMODE_OD0;
\r
324 __IO uint32_t PINMODE_OD1;
\r
325 __IO uint32_t PINMODE_OD2;
\r
326 __IO uint32_t PINMODE_OD3;
\r
327 __IO uint32_t PINMODE_OD4;
\r
330 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
\r
333 __IO uint32_t FIODIR;
\r
334 uint32_t RESERVED0[3];
\r
335 __IO uint32_t FIOMASK;
\r
336 __IO uint32_t FIOPIN;
\r
337 __IO uint32_t FIOSET;
\r
338 __O uint32_t FIOCLR;
\r
343 __I uint32_t IntStatus;
\r
344 __I uint32_t IO0IntStatR;
\r
345 __I uint32_t IO0IntStatF;
\r
346 __O uint32_t IO0IntClr;
\r
347 __IO uint32_t IO0IntEnR;
\r
348 __IO uint32_t IO0IntEnF;
\r
349 uint32_t RESERVED0[3];
\r
350 __I uint32_t IO2IntStatR;
\r
351 __I uint32_t IO2IntStatF;
\r
352 __O uint32_t IO2IntClr;
\r
353 __IO uint32_t IO2IntEnR;
\r
354 __IO uint32_t IO2IntEnF;
\r
357 /*------------- Timer (TIM) --------------------------------------------------*/
\r
373 uint32_t RESERVED0[2];
\r
375 uint32_t RESERVED1[24];
\r
376 __IO uint32_t CTCR;
\r
379 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
\r
402 uint32_t RESERVED0[7];
\r
403 __IO uint32_t CTCR;
\r
406 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
\r
413 uint32_t RESERVED0;
\r
424 uint8_t RESERVED1[7];
\r
426 uint8_t RESERVED2[7];
\r
428 uint8_t RESERVED3[3];
\r
431 uint8_t RESERVED4[3];
\r
433 uint8_t RESERVED5[7];
\r
435 uint8_t RESERVED6[27];
\r
436 __IO uint8_t RS485CTRL;
\r
437 uint8_t RESERVED7[3];
\r
438 __IO uint8_t ADRMATCH;
\r
447 uint32_t RESERVED0;
\r
458 uint8_t RESERVED1[3];
\r
460 uint8_t RESERVED2[3];
\r
462 uint8_t RESERVED3[3];
\r
464 uint8_t RESERVED4[3];
\r
466 uint8_t RESERVED5[3];
\r
468 uint32_t RESERVED6;
\r
470 uint32_t RESERVED7;
\r
472 uint8_t RESERVED8[27];
\r
473 __IO uint8_t RS485CTRL;
\r
474 uint8_t RESERVED9[3];
\r
475 __IO uint8_t ADRMATCH;
\r
476 uint8_t RESERVED10[3];
\r
477 __IO uint8_t RS485DLY;
\r
480 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
\r
483 __IO uint32_t SPCR;
\r
485 __IO uint32_t SPDR;
\r
486 __IO uint32_t SPCCR;
\r
487 uint32_t RESERVED0[3];
\r
488 __IO uint32_t SPINT;
\r
491 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
\r
498 __IO uint32_t CPSR;
\r
499 __IO uint32_t IMSC;
\r
503 __IO uint32_t DMACR;
\r
506 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
\r
509 __IO uint32_t I2CONSET;
\r
510 __I uint32_t I2STAT;
\r
511 __IO uint32_t I2DAT;
\r
512 __IO uint32_t I2ADR0;
\r
513 __IO uint32_t I2SCLH;
\r
514 __IO uint32_t I2SCLL;
\r
515 __O uint32_t I2CONCLR;
\r
516 __IO uint32_t MMCTRL;
\r
517 __IO uint32_t I2ADR1;
\r
518 __IO uint32_t I2ADR2;
\r
519 __IO uint32_t I2ADR3;
\r
520 __I uint32_t I2DATA_BUFFER;
\r
521 __IO uint32_t I2MASK0;
\r
522 __IO uint32_t I2MASK1;
\r
523 __IO uint32_t I2MASK2;
\r
524 __IO uint32_t I2MASK3;
\r
527 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
\r
530 __IO uint32_t I2SDAO;
\r
531 __IO uint32_t I2SDAI;
\r
532 __O uint32_t I2STXFIFO;
\r
533 __I uint32_t I2SRXFIFO;
\r
534 __I uint32_t I2SSTATE;
\r
535 __IO uint32_t I2SDMA1;
\r
536 __IO uint32_t I2SDMA2;
\r
537 __IO uint32_t I2SIRQ;
\r
538 __IO uint32_t I2STXRATE;
\r
539 __IO uint32_t I2SRXRATE;
\r
540 __IO uint32_t I2STXBITRATE;
\r
541 __IO uint32_t I2SRXBITRATE;
\r
542 __IO uint32_t I2STXMODE;
\r
543 __IO uint32_t I2SRXMODE;
\r
546 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
\r
549 __IO uint32_t RICOMPVAL;
\r
550 __IO uint32_t RIMASK;
\r
551 __IO uint8_t RICTRL;
\r
552 uint8_t RESERVED0[3];
\r
553 __IO uint32_t RICOUNTER;
\r
556 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
\r
560 uint8_t RESERVED0[3];
\r
562 uint8_t RESERVED1[3];
\r
564 uint8_t RESERVED2[3];
\r
566 uint8_t RESERVED3[3];
\r
567 __I uint32_t CTIME0;
\r
568 __I uint32_t CTIME1;
\r
569 __I uint32_t CTIME2;
\r
571 uint8_t RESERVED4[3];
\r
573 uint8_t RESERVED5[3];
\r
575 uint8_t RESERVED6[3];
\r
577 uint8_t RESERVED7[3];
\r
579 uint8_t RESERVED8[3];
\r
581 uint16_t RESERVED9;
\r
582 __IO uint8_t MONTH;
\r
583 uint8_t RESERVED10[3];
\r
584 __IO uint16_t YEAR;
\r
585 uint16_t RESERVED11;
\r
586 __IO uint32_t CALIBRATION;
\r
587 __IO uint32_t GPREG0;
\r
588 __IO uint32_t GPREG1;
\r
589 __IO uint32_t GPREG2;
\r
590 __IO uint32_t GPREG3;
\r
591 __IO uint32_t GPREG4;
\r
592 __IO uint8_t WAKEUPDIS;
\r
593 uint8_t RESERVED12[3];
\r
594 __IO uint8_t PWRCTRL;
\r
595 uint8_t RESERVED13[3];
\r
596 __IO uint8_t ALSEC;
\r
597 uint8_t RESERVED14[3];
\r
598 __IO uint8_t ALMIN;
\r
599 uint8_t RESERVED15[3];
\r
600 __IO uint8_t ALHOUR;
\r
601 uint8_t RESERVED16[3];
\r
602 __IO uint8_t ALDOM;
\r
603 uint8_t RESERVED17[3];
\r
604 __IO uint8_t ALDOW;
\r
605 uint8_t RESERVED18[3];
\r
606 __IO uint16_t ALDOY;
\r
607 uint16_t RESERVED19;
\r
608 __IO uint8_t ALMON;
\r
609 uint8_t RESERVED20[3];
\r
610 __IO uint16_t ALYEAR;
\r
611 uint16_t RESERVED21;
\r
614 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
\r
617 __IO uint8_t WDMOD;
\r
618 uint8_t RESERVED0[3];
\r
619 __IO uint32_t WDTC;
\r
620 __O uint8_t WDFEED;
\r
621 uint8_t RESERVED1[3];
\r
623 __IO uint32_t WDCLKSEL;
\r
626 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
\r
629 __IO uint32_t ADCR;
\r
630 __IO uint32_t ADGDR;
\r
631 uint32_t RESERVED0;
\r
632 __IO uint32_t ADINTEN;
\r
633 __I uint32_t ADDR0;
\r
634 __I uint32_t ADDR1;
\r
635 __I uint32_t ADDR2;
\r
636 __I uint32_t ADDR3;
\r
637 __I uint32_t ADDR4;
\r
638 __I uint32_t ADDR5;
\r
639 __I uint32_t ADDR6;
\r
640 __I uint32_t ADDR7;
\r
641 __I uint32_t ADSTAT;
\r
642 __IO uint32_t ADTRM;
\r
645 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
\r
648 __IO uint32_t DACR;
\r
649 __IO uint32_t DACCTRL;
\r
650 __IO uint16_t DACCNTVAL;
\r
653 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
\r
656 __I uint32_t MCCON;
\r
657 __O uint32_t MCCON_SET;
\r
658 __O uint32_t MCCON_CLR;
\r
659 __I uint32_t MCCAPCON;
\r
660 __O uint32_t MCCAPCON_SET;
\r
661 __O uint32_t MCCAPCON_CLR;
\r
662 __IO uint32_t MCTIM0;
\r
663 __IO uint32_t MCTIM1;
\r
664 __IO uint32_t MCTIM2;
\r
665 __IO uint32_t MCPER0;
\r
666 __IO uint32_t MCPER1;
\r
667 __IO uint32_t MCPER2;
\r
668 __IO uint32_t MCPW0;
\r
669 __IO uint32_t MCPW1;
\r
670 __IO uint32_t MCPW2;
\r
671 __IO uint32_t MCDEADTIME;
\r
672 __IO uint32_t MCCCP;
\r
673 __IO uint32_t MCCR0;
\r
674 __IO uint32_t MCCR1;
\r
675 __IO uint32_t MCCR2;
\r
676 __I uint32_t MCINTEN;
\r
677 __O uint32_t MCINTEN_SET;
\r
678 __O uint32_t MCINTEN_CLR;
\r
679 __I uint32_t MCCNTCON;
\r
680 __O uint32_t MCCNTCON_SET;
\r
681 __O uint32_t MCCNTCON_CLR;
\r
682 __I uint32_t MCINTFLAG;
\r
683 __O uint32_t MCINTFLAG_SET;
\r
684 __O uint32_t MCINTFLAG_CLR;
\r
685 __O uint32_t MCCAP_CLR;
\r
688 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
\r
691 __O uint32_t QEICON;
\r
692 __I uint32_t QEISTAT;
\r
693 __IO uint32_t QEICONF;
\r
694 __I uint32_t QEIPOS;
\r
695 __IO uint32_t QEIMAXPOS;
\r
696 __IO uint32_t CMPOS0;
\r
697 __IO uint32_t CMPOS1;
\r
698 __IO uint32_t CMPOS2;
\r
699 __I uint32_t INXCNT;
\r
700 __IO uint32_t INXCMP;
\r
701 __IO uint32_t QEILOAD;
\r
702 __I uint32_t QEITIME;
\r
703 __I uint32_t QEIVEL;
\r
704 __I uint32_t QEICAP;
\r
705 __IO uint32_t VELCOMP;
\r
706 __IO uint32_t FILTER;
\r
707 uint32_t RESERVED0[998];
\r
708 __O uint32_t QEIIEC;
\r
709 __O uint32_t QEIIES;
\r
710 __I uint32_t QEIINTSTAT;
\r
711 __I uint32_t QEIIE;
\r
712 __O uint32_t QEICLR;
\r
713 __O uint32_t QEISET;
\r
716 /*------------- Controller Area Network (CAN) --------------------------------*/
\r
719 __IO uint32_t mask[512]; /* ID Masks */
\r
720 } CANAF_RAM_TypeDef;
\r
722 typedef struct /* Acceptance Filter Registers */
\r
724 __IO uint32_t AFMR;
\r
725 __IO uint32_t SFF_sa;
\r
726 __IO uint32_t SFF_GRP_sa;
\r
727 __IO uint32_t EFF_sa;
\r
728 __IO uint32_t EFF_GRP_sa;
\r
729 __IO uint32_t ENDofTable;
\r
730 __I uint32_t LUTerrAd;
\r
731 __I uint32_t LUTerr;
\r
734 typedef struct /* Central Registers */
\r
736 __I uint32_t CANTxSR;
\r
737 __I uint32_t CANRxSR;
\r
738 __I uint32_t CANMSR;
\r
741 typedef struct /* Controller Registers */
\r
755 __IO uint32_t TFI1;
\r
756 __IO uint32_t TID1;
\r
757 __IO uint32_t TDA1;
\r
758 __IO uint32_t TDB1;
\r
759 __IO uint32_t TFI2;
\r
760 __IO uint32_t TID2;
\r
761 __IO uint32_t TDA2;
\r
762 __IO uint32_t TDB2;
\r
763 __IO uint32_t TFI3;
\r
764 __IO uint32_t TID3;
\r
765 __IO uint32_t TDA3;
\r
766 __IO uint32_t TDB3;
\r
769 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
\r
770 typedef struct /* Common Registers */
\r
772 __I uint32_t DMACIntStat;
\r
773 __I uint32_t DMACIntTCStat;
\r
774 __O uint32_t DMACIntTCClear;
\r
775 __I uint32_t DMACIntErrStat;
\r
776 __O uint32_t DMACIntErrClr;
\r
777 __I uint32_t DMACRawIntTCStat;
\r
778 __I uint32_t DMACRawIntErrStat;
\r
779 __I uint32_t DMACEnbldChns;
\r
780 __IO uint32_t DMACSoftBReq;
\r
781 __IO uint32_t DMACSoftSReq;
\r
782 __IO uint32_t DMACSoftLBReq;
\r
783 __IO uint32_t DMACSoftLSReq;
\r
784 __IO uint32_t DMACConfig;
\r
785 __IO uint32_t DMACSync;
\r
788 typedef struct /* Channel Registers */
\r
790 __IO uint32_t DMACCSrcAddr;
\r
791 __IO uint32_t DMACCDestAddr;
\r
792 __IO uint32_t DMACCLLI;
\r
793 __IO uint32_t DMACCControl;
\r
794 __IO uint32_t DMACCConfig;
\r
797 /*------------- Universal Serial Bus (USB) -----------------------------------*/
\r
800 __I uint32_t HcRevision; /* USB Host Registers */
\r
801 __IO uint32_t HcControl;
\r
802 __IO uint32_t HcCommandStatus;
\r
803 __IO uint32_t HcInterruptStatus;
\r
804 __IO uint32_t HcInterruptEnable;
\r
805 __IO uint32_t HcInterruptDisable;
\r
806 __IO uint32_t HcHCCA;
\r
807 __I uint32_t HcPeriodCurrentED;
\r
808 __IO uint32_t HcControlHeadED;
\r
809 __IO uint32_t HcControlCurrentED;
\r
810 __IO uint32_t HcBulkHeadED;
\r
811 __IO uint32_t HcBulkCurrentED;
\r
812 __I uint32_t HcDoneHead;
\r
813 __IO uint32_t HcFmInterval;
\r
814 __I uint32_t HcFmRemaining;
\r
815 __I uint32_t HcFmNumber;
\r
816 __IO uint32_t HcPeriodicStart;
\r
817 __IO uint32_t HcLSTreshold;
\r
818 __IO uint32_t HcRhDescriptorA;
\r
819 __IO uint32_t HcRhDescriptorB;
\r
820 __IO uint32_t HcRhStatus;
\r
821 __IO uint32_t HcRhPortStatus1;
\r
822 __IO uint32_t HcRhPortStatus2;
\r
823 uint32_t RESERVED0[40];
\r
824 __I uint32_t Module_ID;
\r
826 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
\r
827 __IO uint32_t OTGIntEn;
\r
828 __O uint32_t OTGIntSet;
\r
829 __O uint32_t OTGIntClr;
\r
830 __IO uint32_t OTGStCtrl;
\r
831 __IO uint32_t OTGTmr;
\r
832 uint32_t RESERVED1[58];
\r
834 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
\r
835 __IO uint32_t USBDevIntEn;
\r
836 __O uint32_t USBDevIntClr;
\r
837 __O uint32_t USBDevIntSet;
\r
839 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
\r
840 __I uint32_t USBCmdData;
\r
842 __I uint32_t USBRxData; /* USB Device Transfer Registers */
\r
843 __O uint32_t USBTxData;
\r
844 __I uint32_t USBRxPLen;
\r
845 __O uint32_t USBTxPLen;
\r
846 __IO uint32_t USBCtrl;
\r
847 __O uint32_t USBDevIntPri;
\r
849 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
\r
850 __IO uint32_t USBEpIntEn;
\r
851 __O uint32_t USBEpIntClr;
\r
852 __O uint32_t USBEpIntSet;
\r
853 __O uint32_t USBEpIntPri;
\r
855 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
\r
856 __O uint32_t USBEpInd;
\r
857 __IO uint32_t USBMaxPSize;
\r
859 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
\r
860 __O uint32_t USBDMARClr;
\r
861 __O uint32_t USBDMARSet;
\r
862 uint32_t RESERVED2[9];
\r
863 __IO uint32_t USBUDCAH;
\r
864 __I uint32_t USBEpDMASt;
\r
865 __O uint32_t USBEpDMAEn;
\r
866 __O uint32_t USBEpDMADis;
\r
867 __I uint32_t USBDMAIntSt;
\r
868 __IO uint32_t USBDMAIntEn;
\r
869 uint32_t RESERVED3[2];
\r
870 __I uint32_t USBEoTIntSt;
\r
871 __O uint32_t USBEoTIntClr;
\r
872 __O uint32_t USBEoTIntSet;
\r
873 __I uint32_t USBNDDRIntSt;
\r
874 __O uint32_t USBNDDRIntClr;
\r
875 __O uint32_t USBNDDRIntSet;
\r
876 __I uint32_t USBSysErrIntSt;
\r
877 __O uint32_t USBSysErrIntClr;
\r
878 __O uint32_t USBSysErrIntSet;
\r
879 uint32_t RESERVED4[15];
\r
881 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
\r
882 __O uint32_t I2C_WO;
\r
883 __I uint32_t I2C_STS;
\r
884 __IO uint32_t I2C_CTL;
\r
885 __IO uint32_t I2C_CLKHI;
\r
886 __O uint32_t I2C_CLKLO;
\r
887 uint32_t RESERVED5[823];
\r
890 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
\r
891 __IO uint32_t OTGClkCtrl;
\r
894 __I uint32_t USBClkSt;
\r
895 __I uint32_t OTGClkSt;
\r
899 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
\r
902 __IO uint32_t MAC1; /* MAC Registers */
\r
903 __IO uint32_t MAC2;
\r
904 __IO uint32_t IPGT;
\r
905 __IO uint32_t IPGR;
\r
906 __IO uint32_t CLRT;
\r
907 __IO uint32_t MAXF;
\r
908 __IO uint32_t SUPP;
\r
909 __IO uint32_t TEST;
\r
910 __IO uint32_t MCFG;
\r
911 __IO uint32_t MCMD;
\r
912 __IO uint32_t MADR;
\r
916 uint32_t RESERVED0[2];
\r
920 uint32_t RESERVED1[45];
\r
921 __IO uint32_t Command; /* Control Registers */
\r
922 __I uint32_t Status;
\r
923 __IO uint32_t RxDescriptor;
\r
924 __IO uint32_t RxStatus;
\r
925 __IO uint32_t RxDescriptorNumber;
\r
926 __I uint32_t RxProduceIndex;
\r
927 __IO uint32_t RxConsumeIndex;
\r
928 __IO uint32_t TxDescriptor;
\r
929 __IO uint32_t TxStatus;
\r
930 __IO uint32_t TxDescriptorNumber;
\r
931 __IO uint32_t TxProduceIndex;
\r
932 __I uint32_t TxConsumeIndex;
\r
933 uint32_t RESERVED2[10];
\r
937 uint32_t RESERVED3[3];
\r
938 __IO uint32_t FlowControlCounter;
\r
939 __I uint32_t FlowControlStatus;
\r
940 uint32_t RESERVED4[34];
\r
941 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
\r
942 __IO uint32_t RxFilterWoLStatus;
\r
943 __IO uint32_t RxFilterWoLClear;
\r
944 uint32_t RESERVED5;
\r
945 __IO uint32_t HashFilterL;
\r
946 __IO uint32_t HashFilterH;
\r
947 uint32_t RESERVED6[882];
\r
948 __I uint32_t IntStatus; /* Module Control Registers */
\r
949 __IO uint32_t IntEnable;
\r
950 __O uint32_t IntClear;
\r
951 __O uint32_t IntSet;
\r
952 uint32_t RESERVED7;
\r
953 __IO uint32_t PowerDown;
\r
954 uint32_t RESERVED8;
\r
955 __IO uint32_t Module_ID;
\r
959 /******************************************************************************/
\r
960 /* Peripheral memory map */
\r
961 /******************************************************************************/
\r
962 /* Base addresses */
\r
963 #define FLASH_BASE (0x00000000UL)
\r
964 #define RAM_BASE (0x10000000UL)
\r
965 #define GPIO_BASE (0x2009C000UL)
\r
966 #define APB0_BASE (0x40000000UL)
\r
967 #define APB1_BASE (0x40080000UL)
\r
968 #define AHB_BASE (0x50000000UL)
\r
969 #define CM3_BASE (0xE0000000UL)
\r
971 /* APB0 peripherals */
\r
972 #define WDT_BASE (APB0_BASE + 0x00000)
\r
973 #define TIM0_BASE (APB0_BASE + 0x04000)
\r
974 #define TIM1_BASE (APB0_BASE + 0x08000)
\r
975 #define UART0_BASE (APB0_BASE + 0x0C000)
\r
976 #define UART1_BASE (APB0_BASE + 0x10000)
\r
977 #define PWM1_BASE (APB0_BASE + 0x18000)
\r
978 #define I2C0_BASE (APB0_BASE + 0x1C000)
\r
979 #define SPI_BASE (APB0_BASE + 0x20000)
\r
980 #define RTC_BASE (APB0_BASE + 0x24000)
\r
981 #define GPIOINT_BASE (APB0_BASE + 0x28080)
\r
982 #define PINCON_BASE (APB0_BASE + 0x2C000)
\r
983 #define SSP1_BASE (APB0_BASE + 0x30000)
\r
984 #define ADC_BASE (APB0_BASE + 0x34000)
\r
985 #define CANAF_RAM_BASE (APB0_BASE + 0x38000)
\r
986 #define CANAF_BASE (APB0_BASE + 0x3C000)
\r
987 #define CANCR_BASE (APB0_BASE + 0x40000)
\r
988 #define CAN1_BASE (APB0_BASE + 0x44000)
\r
989 #define CAN2_BASE (APB0_BASE + 0x48000)
\r
990 #define I2C1_BASE (APB0_BASE + 0x5C000)
\r
992 /* APB1 peripherals */
\r
993 #define SSP0_BASE (APB1_BASE + 0x08000)
\r
994 #define DAC_BASE (APB1_BASE + 0x0C000)
\r
995 #define TIM2_BASE (APB1_BASE + 0x10000)
\r
996 #define TIM3_BASE (APB1_BASE + 0x14000)
\r
997 #define UART2_BASE (APB1_BASE + 0x18000)
\r
998 #define UART3_BASE (APB1_BASE + 0x1C000)
\r
999 #define I2C2_BASE (APB1_BASE + 0x20000)
\r
1000 #define I2S_BASE (APB1_BASE + 0x28000)
\r
1001 #define RIT_BASE (APB1_BASE + 0x30000)
\r
1002 #define MCPWM_BASE (APB1_BASE + 0x38000)
\r
1003 #define QEI_BASE (APB1_BASE + 0x3C000)
\r
1004 #define SC_BASE (APB1_BASE + 0x7C000)
\r
1006 /* AHB peripherals */
\r
1007 #define EMAC_BASE (AHB_BASE + 0x00000)
\r
1008 #define GPDMA_BASE (AHB_BASE + 0x04000)
\r
1009 #define GPDMACH0_BASE (AHB_BASE + 0x04100)
\r
1010 #define GPDMACH1_BASE (AHB_BASE + 0x04120)
\r
1011 #define GPDMACH2_BASE (AHB_BASE + 0x04140)
\r
1012 #define GPDMACH3_BASE (AHB_BASE + 0x04160)
\r
1013 #define GPDMACH4_BASE (AHB_BASE + 0x04180)
\r
1014 #define GPDMACH5_BASE (AHB_BASE + 0x041A0)
\r
1015 #define GPDMACH6_BASE (AHB_BASE + 0x041C0)
\r
1016 #define GPDMACH7_BASE (AHB_BASE + 0x041E0)
\r
1017 #define USB_BASE (AHB_BASE + 0x0C000)
\r
1020 #define GPIO0_BASE (GPIO_BASE + 0x00000)
\r
1021 #define GPIO1_BASE (GPIO_BASE + 0x00020)
\r
1022 #define GPIO2_BASE (GPIO_BASE + 0x00040)
\r
1023 #define GPIO3_BASE (GPIO_BASE + 0x00060)
\r
1024 #define GPIO4_BASE (GPIO_BASE + 0x00080)
\r
1027 /******************************************************************************/
\r
1028 /* Peripheral declaration */
\r
1029 /******************************************************************************/
\r
1030 #define SC (( SC_TypeDef *) SC_BASE)
\r
1031 #define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)
\r
1032 #define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)
\r
1033 #define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)
\r
1034 #define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)
\r
1035 #define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE)
\r
1036 #define WDT (( WDT_TypeDef *) WDT_BASE)
\r
1037 #define TIM0 (( TIM_TypeDef *) TIM0_BASE)
\r
1038 #define TIM1 (( TIM_TypeDef *) TIM1_BASE)
\r
1039 #define TIM2 (( TIM_TypeDef *) TIM2_BASE)
\r
1040 #define TIM3 (( TIM_TypeDef *) TIM3_BASE)
\r
1041 #define RIT (( RIT_TypeDef *) RIT_BASE)
\r
1042 #define UART0 (( UART_TypeDef *) UART0_BASE)
\r
1043 #define UART1 (( UART1_TypeDef *) UART1_BASE)
\r
1044 #define UART2 (( UART_TypeDef *) UART2_BASE)
\r
1045 #define UART3 (( UART_TypeDef *) UART3_BASE)
\r
1046 #define PWM1 (( PWM_TypeDef *) PWM1_BASE)
\r
1047 #define I2C0 (( I2C_TypeDef *) I2C0_BASE)
\r
1048 #define I2C1 (( I2C_TypeDef *) I2C1_BASE)
\r
1049 #define I2C2 (( I2C_TypeDef *) I2C2_BASE)
\r
1050 #define I2S (( I2S_TypeDef *) I2S_BASE)
\r
1051 #define SPI (( SPI_TypeDef *) SPI_BASE)
\r
1052 #define RTC (( RTC_TypeDef *) RTC_BASE)
\r
1053 #define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE)
\r
1054 #define PINCON (( PINCON_TypeDef *) PINCON_BASE)
\r
1055 #define SSP0 (( SSP_TypeDef *) SSP0_BASE)
\r
1056 #define SSP1 (( SSP_TypeDef *) SSP1_BASE)
\r
1057 #define ADC (( ADC_TypeDef *) ADC_BASE)
\r
1058 #define DAC (( DAC_TypeDef *) DAC_BASE)
\r
1059 #define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)
\r
1060 #define CANAF (( CANAF_TypeDef *) CANAF_BASE)
\r
1061 #define CANCR (( CANCR_TypeDef *) CANCR_BASE)
\r
1062 #define CAN1 (( CAN_TypeDef *) CAN1_BASE)
\r
1063 #define CAN2 (( CAN_TypeDef *) CAN2_BASE)
\r
1064 #define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE)
\r
1065 #define QEI (( QEI_TypeDef *) QEI_BASE)
\r
1066 #define EMAC (( EMAC_TypeDef *) EMAC_BASE)
\r
1067 #define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE)
\r
1068 #define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE)
\r
1069 #define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE)
\r
1070 #define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE)
\r
1071 #define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE)
\r
1072 #define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE)
\r
1073 #define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE)
\r
1074 #define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE)
\r
1075 #define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE)
\r
1076 #define USB (( USB_TypeDef *) USB_BASE)
\r
1078 #endif // __LPC17xx_H__
\r