2 FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
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5 ***************************************************************************
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7 * FreeRTOS tutorial books are available in pdf and paperback. *
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8 * Complete, revised, and edited pdf reference manuals are also *
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11 * Purchasing FreeRTOS documentation will not only help you, by *
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12 * ensuring you get running as quickly as possible and with an *
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13 * in-depth knowledge of how to use FreeRTOS, it will also help *
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14 * the FreeRTOS project to continue with its mission of providing *
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15 * professional grade, cross platform, de facto standard solutions *
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16 * for microcontrollers - completely free of charge! *
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18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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20 * Thank you for using FreeRTOS, and thank you for your support! *
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22 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 >>>NOTE<<< The modification to the GPL is included to allow you to
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31 distribute a combined work that includes FreeRTOS without being obliged to
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32 provide the source code for proprietary components outside of the FreeRTOS
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33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 ***************************************************************************
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46 * Having a problem? Start by reading the FAQ "My application does *
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47 * not run, what could be wrong? *
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49 * http://www.FreeRTOS.org/FAQHelp.html *
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51 ***************************************************************************
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54 http://www.FreeRTOS.org - Documentation, training, latest information,
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55 license and contact details.
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57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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58 including FreeRTOS+Trace - an indispensable productivity tool.
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60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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61 the code with commercial support, indemnification, and middleware, under
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62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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63 provide a safety engineered and independently SIL3 certified version under
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64 the SafeRTOS brand: http://www.SafeRTOS.com.
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67 /* Originally adapted from file written by Andreas Dannenberg. Supplied with permission. */
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69 /* Kernel includes. */
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70 #include "FreeRTOS.h"
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74 /* Hardware specific includes. */
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75 #include "EthDev_LPC17xx.h"
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77 /* Time to wait between each inspection of the link status. */
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78 #define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_RATE_MS )
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80 /* Short delay used in several places during the initialisation process. */
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81 #define emacSHORT_DELAY ( 2 )
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83 /* Hardware specific bit definitions. */
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84 #define emacLINK_ESTABLISHED ( 0x0020)
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85 #define emacFULL_DUPLEX_ENABLED ( 0x0010 )
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86 #define emac10BASE_T_MODE ( 0x0004 )
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87 #define emacPINSEL2_VALUE ( 0x50150105 )
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88 #define emacDIV_44 ( 0x28 )
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90 /* If no buffers are available, then wait this long before looking again.... */
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91 #define emacBUFFER_WAIT_DELAY ( 3 / portTICK_RATE_MS )
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93 /* ...and don't look more than this many times. */
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94 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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96 /* Index to the Tx descriptor that is always used first for every Tx. The second
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97 descriptor is then used to re-send in order to speed up the uIP Tx process. */
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98 #define emacTX_DESC_INDEX ( 0 )
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100 /*-----------------------------------------------------------*/
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103 * Configure both the Rx and Tx descriptors during the init process.
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105 static void prvInitDescriptors( void );
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108 * Setup the IO and peripherals required for Ethernet communication.
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110 static void prvSetupEMACHardware( void );
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113 * Control the auto negotiate process.
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115 static void prvConfigurePHY( void );
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118 * Wait for a link to be established, then setup the PHY according to the link
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121 static long prvSetupLinkStatus( void );
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124 * Search the pool of buffers to find one that is free. If a buffer is found
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125 * mark it as in use before returning its address.
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127 static unsigned char *prvGetNextBuffer( void );
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130 * Return an allocated buffer to the pool of free buffers.
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132 static void prvReturnBuffer( unsigned char *pucBuffer );
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135 * Send lValue to the lPhyReg within the PHY.
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137 static long prvWritePHY( long lPhyReg, long lValue );
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140 * Read a value from ucPhyReg within the PHY. *plStatus will be set to
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141 * pdFALSE if there is an error.
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143 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus );
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145 /*-----------------------------------------------------------*/
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147 /* The semaphore used to wake the uIP task when data arrives. */
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148 extern xSemaphoreHandle xEMACSemaphore;
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150 /* Each ucBufferInUse index corresponds to a position in the pool of buffers.
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151 If the index contains a 1 then the buffer within pool is in use, if it
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152 contains a 0 then the buffer is free. */
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153 static unsigned char ucBufferInUse[ ETH_NUM_BUFFERS ] = { pdFALSE };
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155 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
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156 allocated within this file. */
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157 unsigned char * uip_buf;
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159 /* Store the length of the data being sent so the data can be sent twice. The
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160 value will be set back to 0 once the data has been sent twice. */
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161 static unsigned short usSendLen = 0;
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163 /*-----------------------------------------------------------*/
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165 long lEMACInit( void )
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167 long lReturn = pdPASS;
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168 unsigned long ulID1, ulID2;
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170 /* Reset peripherals, configure port pins and registers. */
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171 prvSetupEMACHardware();
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173 /* Check the PHY part number is as expected. */
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174 ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );
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175 ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );
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176 if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFFFUL ) ) == KS8721_ID )
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178 /* Set the Ethernet MAC Address registers */
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179 EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
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180 EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
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181 EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
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183 /* Initialize Tx and Rx DMA Descriptors */
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184 prvInitDescriptors();
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186 /* Receive broadcast and perfect match packets */
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187 EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
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189 /* Setup the PHY. */
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197 /* Check the link status. */
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198 if( lReturn == pdPASS )
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200 lReturn = prvSetupLinkStatus();
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203 if( lReturn == pdPASS )
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205 /* Initialise uip_buf to ensure it points somewhere valid. */
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206 uip_buf = prvGetNextBuffer();
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208 /* Reset all interrupts */
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209 EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );
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211 /* Enable receive and transmit mode of MAC Ethernet core */
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212 EMAC->Command |= ( CR_RX_EN | CR_TX_EN );
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213 EMAC->MAC1 |= MAC1_REC_EN;
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218 /*-----------------------------------------------------------*/
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220 static unsigned char *prvGetNextBuffer( void )
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223 unsigned char *pucReturn = NULL;
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224 unsigned long ulAttempts = 0;
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226 while( pucReturn == NULL )
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228 /* Look through the buffers to find one that is not in use by
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230 for( x = 0; x < ETH_NUM_BUFFERS; x++ )
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232 if( ucBufferInUse[ x ] == pdFALSE )
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234 ucBufferInUse[ x ] = pdTRUE;
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235 pucReturn = ( unsigned char * ) ETH_BUF( x );
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240 /* Was a buffer found? */
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241 if( pucReturn == NULL )
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245 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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250 /* Wait then look again. */
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251 vTaskDelay( emacBUFFER_WAIT_DELAY );
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257 /*-----------------------------------------------------------*/
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259 static void prvInitDescriptors( void )
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261 long x, lNextBuffer = 0;
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263 for( x = 0; x < NUM_RX_FRAG; x++ )
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265 /* Allocate the next Ethernet buffer to this descriptor. */
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266 RX_DESC_PACKET( x ) = ETH_BUF( lNextBuffer );
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267 RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
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268 RX_STAT_INFO( x ) = 0;
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269 RX_STAT_HASHCRC( x ) = 0;
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271 /* The Ethernet buffer is now in use. */
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272 ucBufferInUse[ lNextBuffer ] = pdTRUE;
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276 /* Set EMAC Receive Descriptor Registers. */
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277 EMAC->RxDescriptor = RX_DESC_BASE;
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278 EMAC->RxStatus = RX_STAT_BASE;
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279 EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;
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281 /* Rx Descriptors Point to 0 */
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282 EMAC->RxConsumeIndex = 0;
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284 /* A buffer is not allocated to the Tx descriptors until they are actually
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286 for( x = 0; x < NUM_TX_FRAG; x++ )
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288 TX_DESC_PACKET( x ) = ( unsigned long ) NULL;
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289 TX_DESC_CTRL( x ) = 0;
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290 TX_STAT_INFO( x ) = 0;
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293 /* Set EMAC Transmit Descriptor Registers. */
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294 EMAC->TxDescriptor = TX_DESC_BASE;
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295 EMAC->TxStatus = TX_STAT_BASE;
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296 EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;
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298 /* Tx Descriptors Point to 0 */
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299 EMAC->TxProduceIndex = 0;
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301 /*-----------------------------------------------------------*/
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303 static void prvSetupEMACHardware( void )
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308 /* Enable P1 Ethernet Pins. */
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309 PINCON->PINSEL2 = emacPINSEL2_VALUE;
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310 PINCON->PINSEL3 = ( PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;
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312 /* Power Up the EMAC controller. */
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313 SC->PCONP |= PCONP_PCENET;
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314 vTaskDelay( emacSHORT_DELAY );
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316 /* Reset all EMAC internal modules. */
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317 EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
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318 EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
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320 /* A short delay after reset. */
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321 vTaskDelay( emacSHORT_DELAY );
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323 /* Initialize MAC control registers. */
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324 EMAC->MAC1 = MAC1_PASS_ALL;
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325 EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
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326 EMAC->MAXF = ETH_MAX_FLEN;
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327 EMAC->CLRT = CLRT_DEF;
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328 EMAC->IPGR = IPGR_DEF;
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329 EMAC->MCFG = emacDIV_44;
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331 /* Enable Reduced MII interface. */
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332 EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
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334 /* Reset Reduced MII Logic. */
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335 EMAC->SUPP = SUPP_RES_RMII;
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336 vTaskDelay( emacSHORT_DELAY );
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339 /* Put the PHY in reset mode */
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340 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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341 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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343 /* Wait for hardware reset to end. */
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344 for( x = 0; x < 100; x++ )
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346 vTaskDelay( emacSHORT_DELAY * 5 );
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347 us = prvReadPHY( PHY_REG_BMCR, &lDummy );
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348 if( !( us & MCFG_RES_MII ) )
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350 /* Reset complete */
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355 /*-----------------------------------------------------------*/
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357 static void prvConfigurePHY( void )
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362 /* Auto negotiate the configuration. */
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363 if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
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365 vTaskDelay( emacSHORT_DELAY * 5 );
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367 for( x = 0; x < 10; x++ )
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369 us = prvReadPHY( PHY_REG_BMSR, &lDummy );
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371 if( us & PHY_AUTO_NEG_COMPLETE )
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376 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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380 /*-----------------------------------------------------------*/
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382 static long prvSetupLinkStatus( void )
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384 long lReturn = pdFAIL, x;
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385 unsigned short usLinkStatus;
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387 /* Wait with timeout for the link to be established. */
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388 for( x = 0; x < 10; x++ )
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390 usLinkStatus = prvReadPHY( PHY_CTRLER, &lReturn );
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391 if( usLinkStatus != 0x00 )
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393 /* Link is established. */
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398 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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401 if( lReturn == pdPASS )
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403 /* Configure Full/Half Duplex mode. */
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404 if( usLinkStatus & emacFULL_DUPLEX_ENABLED )
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406 /* Full duplex is enabled. */
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407 EMAC->MAC2 |= MAC2_FULL_DUP;
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408 EMAC->Command |= CR_FULL_DUP;
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409 EMAC->IPGT = IPGT_FULL_DUP;
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413 /* Half duplex mode. */
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414 EMAC->IPGT = IPGT_HALF_DUP;
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417 /* Configure 100MBit/10MBit mode. */
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418 if( usLinkStatus & emac10BASE_T_MODE )
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425 /* 100MBit mode. */
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426 EMAC->SUPP = SUPP_SPEED;
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432 /*-----------------------------------------------------------*/
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434 static void prvReturnBuffer( unsigned char *pucBuffer )
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438 /* Return a buffer to the pool of free buffers. */
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439 for( ul = 0; ul < ETH_NUM_BUFFERS; ul++ )
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441 if( ETH_BUF( ul ) == ( unsigned long ) pucBuffer )
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443 ucBufferInUse[ ul ] = pdFALSE;
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448 /*-----------------------------------------------------------*/
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450 unsigned long ulGetEMACRxData( void )
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452 unsigned long ulLen = 0;
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455 if( EMAC->RxProduceIndex != EMAC->RxConsumeIndex )
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457 /* Mark the current buffer as free as uip_buf is going to be set to
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458 the buffer that contains the received data. */
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459 prvReturnBuffer( uip_buf );
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461 ulLen = ( RX_STAT_INFO( EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;
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462 uip_buf = ( unsigned char * ) RX_DESC_PACKET( EMAC->RxConsumeIndex );
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464 /* Allocate a new buffer to the descriptor. */
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465 RX_DESC_PACKET( EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();
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467 /* Move the consume index onto the next position, ensuring it wraps to
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468 the beginning at the appropriate place. */
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469 lIndex = EMAC->RxConsumeIndex;
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472 if( lIndex >= NUM_RX_FRAG )
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477 EMAC->RxConsumeIndex = lIndex;
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482 /*-----------------------------------------------------------*/
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484 void vSendEMACTxData( unsigned short usTxDataLen )
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486 unsigned long ulAttempts = 0UL;
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488 /* Check to see if the Tx descriptor is free, indicated by its buffer being
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490 while( TX_DESC_PACKET( emacTX_DESC_INDEX ) != ( unsigned long ) NULL )
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492 /* Wait for the Tx descriptor to become available. */
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493 vTaskDelay( emacBUFFER_WAIT_DELAY );
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496 if( ulAttempts > emacBUFFER_WAIT_ATTEMPTS )
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498 /* Something has gone wrong as the Tx descriptor is still in use.
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499 Clear it down manually, the data it was sending will probably be
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501 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
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506 /* Setup the Tx descriptor for transmission. Remember the length of the
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507 data being sent so the second descriptor can be used to send it again from
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509 usSendLen = usTxDataLen;
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510 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;
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511 TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );
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512 EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );
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514 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
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515 uip_buf = prvGetNextBuffer();
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517 /*-----------------------------------------------------------*/
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519 static long prvWritePHY( long lPhyReg, long lValue )
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521 const long lMaxTime = 10;
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524 EMAC->MADR = KS8721_DEF_ADR | lPhyReg;
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525 EMAC->MWTD = lValue;
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528 for( x = 0; x < lMaxTime; x++ )
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530 if( ( EMAC->MIND & MIND_BUSY ) == 0 )
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532 /* Operation has finished. */
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536 vTaskDelay( emacSHORT_DELAY );
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548 /*-----------------------------------------------------------*/
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550 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
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553 const long lMaxTime = 10;
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555 EMAC->MADR = KS8721_DEF_ADR | ucPhyReg;
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556 EMAC->MCMD = MCMD_READ;
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558 for( x = 0; x < lMaxTime; x++ )
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560 /* Operation has finished. */
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561 if( ( EMAC->MIND & MIND_BUSY ) == 0 )
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566 vTaskDelay( emacSHORT_DELAY );
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571 if( x >= lMaxTime )
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573 *plStatus = pdFAIL;
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576 return( EMAC->MRDD );
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578 /*-----------------------------------------------------------*/
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580 void vEMAC_ISR( void )
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582 unsigned long ulStatus;
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583 long lHigherPriorityTaskWoken = pdFALSE;
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585 ulStatus = EMAC->IntStatus;
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587 /* Clear the interrupt. */
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588 EMAC->IntClear = ulStatus;
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590 if( ulStatus & INT_RX_DONE )
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592 /* Ensure the uIP task is not blocked as data has arrived. */
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593 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
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596 if( ulStatus & INT_TX_DONE )
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598 if( usSendLen > 0 )
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600 /* Send the data again, using the second descriptor. As there are
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601 only two descriptors the index is set back to 0. */
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602 TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );
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603 TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );
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604 EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );
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606 /* This is the second Tx so set usSendLen to 0 to indicate that the
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607 Tx descriptors will be free again. */
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612 /* The Tx buffer is no longer required. */
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613 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
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614 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) NULL;
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618 portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
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