2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Scheduler includes. */
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29 #include "FreeRTOS.h"
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32 /* Demo includes. */
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33 #include "IntQueueTimer.h"
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34 #include "IntQueue.h"
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36 /* Hardware includes. */
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37 #include "lpc11xx.h"
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39 /* The two timer frequencies. */
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40 #define tmrTIMER_2_FREQUENCY ( 2000UL )
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41 #define tmrTIMER_3_FREQUENCY ( 2001UL )
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43 /* The priorities for the two timers. Note that a priority of 0 is the highest
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44 possible on Cortex-M devices. */
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45 #define tmrMAX_PRIORITY ( 0UL )
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46 #define trmSECOND_HIGHEST_PRIORITY ( tmrMAX_PRIORITY + 1 )
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48 void vInitialiseTimerForIntQueueTest( void )
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50 /* Enable AHB clock for GPIO and 16-bit timers. */
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51 LPC_SYSCON->SYSAHBCLKCTRL |= ( 7 << 6 );
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53 /* Interrupt and reset on MR0 match. */
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54 LPC_TMR16B0->MCR = 0x03;
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55 LPC_TMR16B1->MCR = 0x03;
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57 /* Configure the frequency of the interrupt generated by MR0 matches. */
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58 LPC_TMR16B0->MR0 = SystemCoreClock / tmrTIMER_2_FREQUENCY;
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59 LPC_TMR16B1->MR0 = SystemCoreClock / tmrTIMER_3_FREQUENCY;
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61 /* Don't generate interrupts until the scheduler has been started.
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62 Interrupts will be automatically enabled when the first task starts
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64 taskDISABLE_INTERRUPTS();
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66 /* Set the timer interrupts to be above the kernel. The interrupts are
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67 assigned different priorities so they nest with each other. */
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68 NVIC_SetPriority( TIMER_16_0_IRQn, trmSECOND_HIGHEST_PRIORITY );
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69 NVIC_SetPriority( TIMER_16_1_IRQn, tmrMAX_PRIORITY );
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71 /* Enable the timer interrupts. */
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72 NVIC_EnableIRQ( TIMER_16_0_IRQn );
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73 NVIC_EnableIRQ( TIMER_16_1_IRQn );
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75 /* Start the timers. */
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76 LPC_TMR16B0->TCR = 0x01;
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77 LPC_TMR16B1->TCR = 0x01;
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79 /*-----------------------------------------------------------*/
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81 void TIMER16_0_IRQHandler(void)
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83 /* Clear the interrupt. */
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84 LPC_TMR16B0->IR = LPC_TMR16B0->IR;
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86 /* Call the standard demo int queue timer function for this first timer. */
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87 portEND_SWITCHING_ISR( xFirstTimerHandler() );
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89 /*-----------------------------------------------------------*/
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91 void TIMER16_1_IRQHandler(void)
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93 /* Clear the interrupt. */
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94 LPC_TMR16B1->IR = LPC_TMR16B1->IR;
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96 /* Call the standard demo int queue timer function for this second timer. */
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97 portEND_SWITCHING_ISR( xSecondTimerHandler() );
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99 /*-----------------------------------------------------------*/
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