2 ******************************************************************************
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3 * @file stm32f0xx_dma.h
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4 * @author MCD Application Team
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6 * @date 27-January-2012
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7 * @brief This file contains all the functions prototypes for the DMA firmware
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9 ******************************************************************************
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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19 * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
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20 * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
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22 * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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23 ******************************************************************************
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26 /* Define to prevent recursive inclusion -------------------------------------*/
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27 #ifndef __STM32F0XX_DMA_H
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28 #define __STM32F0XX_DMA_H
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34 /* Includes ------------------------------------------------------------------*/
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35 #include "stm32f0xx.h"
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37 /** @addtogroup STM32F0xx_StdPeriph_Driver
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44 /* Exported types ------------------------------------------------------------*/
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47 * @brief DMA Init structures definition
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51 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
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53 uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
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55 uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
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56 This parameter can be a value of @ref DMA_data_transfer_direction */
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58 uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
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59 The data unit is equal to the configuration set in DMA_PeripheralDataSize
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60 or DMA_MemoryDataSize members depending in the transfer direction */
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62 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
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63 This parameter can be a value of @ref DMA_peripheral_incremented_mode */
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65 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
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66 This parameter can be a value of @ref DMA_memory_incremented_mode */
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68 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
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69 This parameter can be a value of @ref DMA_peripheral_data_size */
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71 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
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72 This parameter can be a value of @ref DMA_memory_data_size */
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74 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
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75 This parameter can be a value of @ref DMA_circular_normal_mode
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76 @note: The circular buffer mode cannot be used if the memory-to-memory
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77 data transfer is configured on the selected Channel */
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79 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
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80 This parameter can be a value of @ref DMA_priority_level */
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82 uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
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83 This parameter can be a value of @ref DMA_memory_to_memory */
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86 /* Exported constants --------------------------------------------------------*/
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88 /** @defgroup DMA_Exported_Constants
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92 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
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93 ((PERIPH) == DMA1_Channel2) || \
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94 ((PERIPH) == DMA1_Channel3) || \
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95 ((PERIPH) == DMA1_Channel4) || \
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96 ((PERIPH) == DMA1_Channel5))
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98 /** @defgroup DMA_data_transfer_direction
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102 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
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103 #define DMA_DIR_PeripheralDST DMA_CCR_DIR
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105 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
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106 ((DIR) == DMA_DIR_PeripheralDST))
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111 /** @defgroup DMA_peripheral_incremented_mode
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115 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
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116 #define DMA_PeripheralInc_Enable DMA_CCR_PINC
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118 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
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119 ((STATE) == DMA_PeripheralInc_Enable))
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124 /** @defgroup DMA_memory_incremented_mode
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128 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
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129 #define DMA_MemoryInc_Enable DMA_CCR_MINC
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131 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
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132 ((STATE) == DMA_MemoryInc_Enable))
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137 /** @defgroup DMA_peripheral_data_size
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141 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
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142 #define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
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143 #define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
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145 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
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146 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
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147 ((SIZE) == DMA_PeripheralDataSize_Word))
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152 /** @defgroup DMA_memory_data_size
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156 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
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157 #define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
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158 #define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
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160 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
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161 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
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162 ((SIZE) == DMA_MemoryDataSize_Word))
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167 /** @defgroup DMA_circular_normal_mode
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171 #define DMA_Mode_Normal ((uint32_t)0x00000000)
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172 #define DMA_Mode_Circular DMA_CCR_CIRC
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174 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
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179 /** @defgroup DMA_priority_level
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183 #define DMA_Priority_VeryHigh DMA_CCR_PL
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184 #define DMA_Priority_High DMA_CCR_PL_1
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185 #define DMA_Priority_Medium DMA_CCR_PL_0
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186 #define DMA_Priority_Low ((uint32_t)0x00000000)
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188 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
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189 ((PRIORITY) == DMA_Priority_High) || \
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190 ((PRIORITY) == DMA_Priority_Medium) || \
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191 ((PRIORITY) == DMA_Priority_Low))
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196 /** @defgroup DMA_memory_to_memory
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200 #define DMA_M2M_Disable ((uint32_t)0x00000000)
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201 #define DMA_M2M_Enable DMA_CCR_MEM2MEM
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203 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
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209 /** @defgroup DMA_interrupts_definition
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213 #define DMA_IT_TC DMA_CCR_TCIE
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214 #define DMA_IT_HT DMA_CCR_HTIE
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215 #define DMA_IT_TE DMA_CCR_TEIE
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217 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
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219 #define DMA1_IT_GL1 DMA_ISR_GIF1
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220 #define DMA1_IT_TC1 DMA_ISR_TCIF1
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221 #define DMA1_IT_HT1 DMA_ISR_HTIF1
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222 #define DMA1_IT_TE1 DMA_ISR_TEIF1
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223 #define DMA1_IT_GL2 DMA_ISR_GIF2
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224 #define DMA1_IT_TC2 DMA_ISR_TCIF2
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225 #define DMA1_IT_HT2 DMA_ISR_HTIF2
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226 #define DMA1_IT_TE2 DMA_ISR_TEIF2
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227 #define DMA1_IT_GL3 DMA_ISR_GIF3
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228 #define DMA1_IT_TC3 DMA_ISR_TCIF3
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229 #define DMA1_IT_HT3 DMA_ISR_HTIF3
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230 #define DMA1_IT_TE3 DMA_ISR_TEIF3
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231 #define DMA1_IT_GL4 DMA_ISR_GIF4
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232 #define DMA1_IT_TC4 DMA_ISR_TCIF4
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233 #define DMA1_IT_HT4 DMA_ISR_HTIF4
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234 #define DMA1_IT_TE4 DMA_ISR_TEIF4
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235 #define DMA1_IT_GL5 DMA_ISR_GIF5
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236 #define DMA1_IT_TC5 DMA_ISR_TCIF5
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237 #define DMA1_IT_HT5 DMA_ISR_HTIF5
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238 #define DMA1_IT_TE5 DMA_ISR_TEIF5
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240 #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xFFF00000) == 0x00) && ((IT) != 0x00))
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242 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
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243 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
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244 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
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245 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
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246 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
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247 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
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248 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
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249 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
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250 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
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251 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5))
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257 /** @defgroup DMA_flags_definition
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260 #define DMA1_FLAG_GL1 DMA_ISR_GIF1
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261 #define DMA1_FLAG_TC1 DMA_ISR_TCIF1
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262 #define DMA1_FLAG_HT1 DMA_ISR_HTIF1
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263 #define DMA1_FLAG_TE1 DMA_ISR_TEIF1
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264 #define DMA1_FLAG_GL2 DMA_ISR_GIF2
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265 #define DMA1_FLAG_TC2 DMA_ISR_TCIF2
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266 #define DMA1_FLAG_HT2 DMA_ISR_HTIF2
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267 #define DMA1_FLAG_TE2 DMA_ISR_TEIF2
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268 #define DMA1_FLAG_GL3 DMA_ISR_GIF3
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269 #define DMA1_FLAG_TC3 DMA_ISR_TCIF3
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270 #define DMA1_FLAG_HT3 DMA_ISR_HTIF3
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271 #define DMA1_FLAG_TE3 DMA_ISR_TEIF3
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272 #define DMA1_FLAG_GL4 DMA_ISR_GIF4
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273 #define DMA1_FLAG_TC4 DMA_ISR_TCIF4
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274 #define DMA1_FLAG_HT4 DMA_ISR_HTIF4
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275 #define DMA1_FLAG_TE4 DMA_ISR_TEIF4
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276 #define DMA1_FLAG_GL5 DMA_ISR_GIF5
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277 #define DMA1_FLAG_TC5 DMA_ISR_TCIF5
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278 #define DMA1_FLAG_HT5 DMA_ISR_HTIF5
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279 #define DMA1_FLAG_TE5 DMA_ISR_TEIF5
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281 #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFFF00000) == 0x00) && ((FLAG) != 0x00))
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283 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
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284 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
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285 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
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286 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
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287 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
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288 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
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289 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
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290 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
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291 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
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292 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5))
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298 /** @defgroup DMA_Buffer_Size
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302 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
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312 /* Exported macro ------------------------------------------------------------*/
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313 /* Exported functions ------------------------------------------------------- */
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315 /* Function used to set the DMA configuration to the default reset state ******/
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316 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
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318 /* Initialization and Configuration functions *********************************/
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319 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
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320 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
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321 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
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323 /* Data Counter functions******************************************************/
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324 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
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325 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
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327 /* Interrupts and flags management functions **********************************/
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328 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
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329 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
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330 void DMA_ClearFlag(uint32_t DMA_FLAG);
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331 ITStatus DMA_GetITStatus(uint32_t DMA_IT);
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332 void DMA_ClearITPendingBit(uint32_t DMA_IT);
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338 #endif /*__STM32F0XX_DMA_H */
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348 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
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