2 ******************************************************************************
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3 * @file stm32f0xx_spi.h
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4 * @author MCD Application Team
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6 * @date 27-January-2012
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7 * @brief This file contains all the functions prototypes for the SPI
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9 ******************************************************************************
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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19 * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
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20 * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
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22 * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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23 ******************************************************************************
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26 /* Define to prevent recursive inclusion -------------------------------------*/
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27 #ifndef __STM32F0XX_SPI_H
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28 #define __STM32F0XX_SPI_H
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34 /* Includes ------------------------------------------------------------------*/
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35 #include "stm32f0xx.h"
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37 /** @addtogroup STM32F0xx_StdPeriph_Driver
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45 /* Exported types ------------------------------------------------------------*/
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48 * @brief SPI Init structure definition
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53 uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
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54 This parameter can be a value of @ref SPI_data_direction */
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56 uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
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57 This parameter can be a value of @ref SPI_mode */
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59 uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
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60 This parameter can be a value of @ref SPI_data_size */
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62 uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
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63 This parameter can be a value of @ref SPI_Clock_Polarity */
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65 uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
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66 This parameter can be a value of @ref SPI_Clock_Phase */
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68 uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
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69 hardware (NSS pin) or by software using the SSI bit.
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70 This parameter can be a value of @ref SPI_Slave_Select_management */
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72 uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
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73 used to configure the transmit and receive SCK clock.
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74 This parameter can be a value of @ref SPI_BaudRate_Prescaler
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75 @note The communication clock is derived from the master
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76 clock. The slave clock does not need to be set. */
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78 uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
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79 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
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81 uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
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86 * @brief I2S Init structure definition
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91 uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
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92 This parameter can be a value of @ref SPI_I2S_Mode */
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94 uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
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95 This parameter can be a value of @ref SPI_I2S_Standard */
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97 uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
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98 This parameter can be a value of @ref SPI_I2S_Data_Format */
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100 uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
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101 This parameter can be a value of @ref SPI_I2S_MCLK_Output */
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103 uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
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104 This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
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106 uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
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107 This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
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110 /* Exported constants --------------------------------------------------------*/
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112 /** @defgroup SPI_Exported_Constants
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116 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
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117 ((PERIPH) == SPI2))
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119 #define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1))
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121 /** @defgroup SPI_data_direction
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125 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
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126 #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
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127 #define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
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128 #define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
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129 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
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130 ((MODE) == SPI_Direction_2Lines_RxOnly) || \
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131 ((MODE) == SPI_Direction_1Line_Rx) || \
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132 ((MODE) == SPI_Direction_1Line_Tx))
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137 /** @defgroup SPI_mode
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141 #define SPI_Mode_Master ((uint16_t)0x0104)
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142 #define SPI_Mode_Slave ((uint16_t)0x0000)
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143 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
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144 ((MODE) == SPI_Mode_Slave))
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149 /** @defgroup SPI_data_size
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153 #define SPI_DataSize_4b ((uint16_t)0x0300)
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154 #define SPI_DataSize_5b ((uint16_t)0x0400)
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155 #define SPI_DataSize_6b ((uint16_t)0x0500)
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156 #define SPI_DataSize_7b ((uint16_t)0x0600)
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157 #define SPI_DataSize_8b ((uint16_t)0x0700)
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158 #define SPI_DataSize_9b ((uint16_t)0x0800)
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159 #define SPI_DataSize_10b ((uint16_t)0x0900)
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160 #define SPI_DataSize_11b ((uint16_t)0x0A00)
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161 #define SPI_DataSize_12b ((uint16_t)0x0B00)
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162 #define SPI_DataSize_13b ((uint16_t)0x0C00)
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163 #define SPI_DataSize_14b ((uint16_t)0x0D00)
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164 #define SPI_DataSize_15b ((uint16_t)0x0E00)
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165 #define SPI_DataSize_16b ((uint16_t)0x0F00)
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166 #define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
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167 ((SIZE) == SPI_DataSize_5b) || \
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168 ((SIZE) == SPI_DataSize_6b) || \
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169 ((SIZE) == SPI_DataSize_7b) || \
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170 ((SIZE) == SPI_DataSize_8b) || \
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171 ((SIZE) == SPI_DataSize_9b) || \
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172 ((SIZE) == SPI_DataSize_10b) || \
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173 ((SIZE) == SPI_DataSize_11b) || \
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174 ((SIZE) == SPI_DataSize_12b) || \
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175 ((SIZE) == SPI_DataSize_13b) || \
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176 ((SIZE) == SPI_DataSize_14b) || \
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177 ((SIZE) == SPI_DataSize_15b) || \
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178 ((SIZE) == SPI_DataSize_16b))
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183 /** @defgroup SPI_CRC_length
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187 #define SPI_CRCLength_8b ((uint16_t)0x0000)
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188 #define SPI_CRCLength_16b SPI_CR1_CRCL
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189 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
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190 ((LENGTH) == SPI_CRCLength_16b))
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195 /** @defgroup SPI_Clock_Polarity
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199 #define SPI_CPOL_Low ((uint16_t)0x0000)
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200 #define SPI_CPOL_High SPI_CR1_CPOL
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201 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
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202 ((CPOL) == SPI_CPOL_High))
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207 /** @defgroup SPI_Clock_Phase
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211 #define SPI_CPHA_1Edge ((uint16_t)0x0000)
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212 #define SPI_CPHA_2Edge SPI_CR1_CPHA
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213 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
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214 ((CPHA) == SPI_CPHA_2Edge))
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219 /** @defgroup SPI_Slave_Select_management
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223 #define SPI_NSS_Soft SPI_CR1_SSM
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224 #define SPI_NSS_Hard ((uint16_t)0x0000)
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225 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
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226 ((NSS) == SPI_NSS_Hard))
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231 /** @defgroup SPI_BaudRate_Prescaler
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235 #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
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236 #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
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237 #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
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238 #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
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239 #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
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240 #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
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241 #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
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242 #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
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243 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
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244 ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
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245 ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
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246 ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
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247 ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
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248 ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
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249 ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
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250 ((PRESCALER) == SPI_BaudRatePrescaler_256))
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255 /** @defgroup SPI_MSB_LSB_transmission
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259 #define SPI_FirstBit_MSB ((uint16_t)0x0000)
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260 #define SPI_FirstBit_LSB SPI_CR1_LSBFIRST
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261 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
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262 ((BIT) == SPI_FirstBit_LSB))
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267 /** @defgroup SPI_I2S_Mode
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271 #define I2S_Mode_SlaveTx ((uint16_t)0x0000)
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272 #define I2S_Mode_SlaveRx ((uint16_t)0x0100)
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273 #define I2S_Mode_MasterTx ((uint16_t)0x0200)
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274 #define I2S_Mode_MasterRx ((uint16_t)0x0300)
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275 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
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276 ((MODE) == I2S_Mode_SlaveRx) || \
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277 ((MODE) == I2S_Mode_MasterTx)|| \
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278 ((MODE) == I2S_Mode_MasterRx))
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283 /** @defgroup SPI_I2S_Standard
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287 #define I2S_Standard_Phillips ((uint16_t)0x0000)
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288 #define I2S_Standard_MSB ((uint16_t)0x0010)
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289 #define I2S_Standard_LSB ((uint16_t)0x0020)
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290 #define I2S_Standard_PCMShort ((uint16_t)0x0030)
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291 #define I2S_Standard_PCMLong ((uint16_t)0x00B0)
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292 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
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293 ((STANDARD) == I2S_Standard_MSB) || \
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294 ((STANDARD) == I2S_Standard_LSB) || \
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295 ((STANDARD) == I2S_Standard_PCMShort) || \
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296 ((STANDARD) == I2S_Standard_PCMLong))
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301 /** @defgroup SPI_I2S_Data_Format
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305 #define I2S_DataFormat_16b ((uint16_t)0x0000)
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306 #define I2S_DataFormat_16bextended ((uint16_t)0x0001)
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307 #define I2S_DataFormat_24b ((uint16_t)0x0003)
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308 #define I2S_DataFormat_32b ((uint16_t)0x0005)
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309 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
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310 ((FORMAT) == I2S_DataFormat_16bextended) || \
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311 ((FORMAT) == I2S_DataFormat_24b) || \
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312 ((FORMAT) == I2S_DataFormat_32b))
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317 /** @defgroup SPI_I2S_MCLK_Output
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321 #define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE
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322 #define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
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323 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
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324 ((OUTPUT) == I2S_MCLKOutput_Disable))
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329 /** @defgroup SPI_I2S_Audio_Frequency
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333 #define I2S_AudioFreq_192k ((uint32_t)192000)
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334 #define I2S_AudioFreq_96k ((uint32_t)96000)
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335 #define I2S_AudioFreq_48k ((uint32_t)48000)
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336 #define I2S_AudioFreq_44k ((uint32_t)44100)
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337 #define I2S_AudioFreq_32k ((uint32_t)32000)
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338 #define I2S_AudioFreq_22k ((uint32_t)22050)
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339 #define I2S_AudioFreq_16k ((uint32_t)16000)
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340 #define I2S_AudioFreq_11k ((uint32_t)11025)
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341 #define I2S_AudioFreq_8k ((uint32_t)8000)
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342 #define I2S_AudioFreq_Default ((uint32_t)2)
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344 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
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345 ((FREQ) <= I2S_AudioFreq_192k)) || \
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346 ((FREQ) == I2S_AudioFreq_Default))
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351 /** @defgroup SPI_I2S_Clock_Polarity
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355 #define I2S_CPOL_Low ((uint16_t)0x0000)
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356 #define I2S_CPOL_High SPI_I2SCFGR_CKPOL
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357 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
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358 ((CPOL) == I2S_CPOL_High))
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363 /** @defgroup SPI_FIFO_reception_threshold
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367 #define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
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368 #define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH
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369 #define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
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370 ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
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375 /** @defgroup SPI_I2S_DMA_transfer_requests
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379 #define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN
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380 #define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN
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381 #define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
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386 /** @defgroup SPI_last_DMA_transfers
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390 #define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
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391 #define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
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392 #define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
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393 #define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
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394 #define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
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395 ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
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396 ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
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397 ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
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401 /** @defgroup SPI_NSS_internal_software_management
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405 #define SPI_NSSInternalSoft_Set SPI_CR1_SSI
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406 #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
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407 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
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408 ((INTERNAL) == SPI_NSSInternalSoft_Reset))
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413 /** @defgroup SPI_CRC_Transmit_Receive
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417 #define SPI_CRC_Tx ((uint8_t)0x00)
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418 #define SPI_CRC_Rx ((uint8_t)0x01)
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419 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
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424 /** @defgroup SPI_direction_transmit_receive
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428 #define SPI_Direction_Rx ((uint16_t)0xBFFF)
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429 #define SPI_Direction_Tx ((uint16_t)0x4000)
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430 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
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431 ((DIRECTION) == SPI_Direction_Tx))
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436 /** @defgroup SPI_I2S_interrupts_definition
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440 #define SPI_I2S_IT_TXE ((uint8_t)0x71)
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441 #define SPI_I2S_IT_RXNE ((uint8_t)0x60)
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442 #define SPI_I2S_IT_ERR ((uint8_t)0x50)
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444 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
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445 ((IT) == SPI_I2S_IT_RXNE) || \
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446 ((IT) == SPI_I2S_IT_ERR))
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448 #define I2S_IT_UDR ((uint8_t)0x53)
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449 #define SPI_IT_MODF ((uint8_t)0x55)
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450 #define SPI_I2S_IT_OVR ((uint8_t)0x56)
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451 #define SPI_I2S_IT_FRE ((uint8_t)0x58)
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453 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
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454 ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
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455 ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
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461 /** @defgroup SPI_transmission_fifo_status_level
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465 #define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
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466 #define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
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467 #define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
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468 #define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
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474 /** @defgroup SPI_reception_fifo_status_level
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477 #define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
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478 #define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
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479 #define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
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480 #define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
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487 /** @defgroup SPI_I2S_flags_definition
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491 #define SPI_I2S_FLAG_RXNE SPI_SR_RXNE
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492 #define SPI_I2S_FLAG_TXE SPI_SR_TXE
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493 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
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494 #define I2S_FLAG_UDR SPI_SR_UDR
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495 #define SPI_FLAG_CRCERR SPI_SR_CRCERR
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496 #define SPI_FLAG_MODF SPI_SR_MODF
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497 #define SPI_I2S_FLAG_OVR SPI_SR_OVR
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498 #define SPI_I2S_FLAG_BSY SPI_SR_BSY
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499 #define SPI_I2S_FLAG_FRE SPI_SR_FRE
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503 #define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
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504 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
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505 ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
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506 ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
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507 ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
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508 ((FLAG) == I2S_FLAG_UDR))
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513 /** @defgroup SPI_CRC_polynomial
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517 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
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526 /* Exported macro ------------------------------------------------------------*/
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527 /* Exported functions ------------------------------------------------------- */
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529 /* Initialization and Configuration functions *********************************/
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530 void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
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531 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
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532 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
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533 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
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534 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
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535 void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
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536 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
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537 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
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538 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
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539 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
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540 void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
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541 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
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542 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
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543 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
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545 /* Data transfers functions ***************************************************/
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546 void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
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547 void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
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548 uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
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549 uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
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551 /* Hardware CRC Calculation functions *****************************************/
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552 void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
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553 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
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554 void SPI_TransmitCRC(SPI_TypeDef* SPIx);
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555 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
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556 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
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558 /* DMA transfers management functions *****************************************/
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559 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
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560 void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
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562 /* Interrupts and flags management functions **********************************/
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563 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
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564 uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
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565 uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
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566 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
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567 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
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568 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
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574 #endif /*__STM32F0XX_SPI_H */
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584 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
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