git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/LiberoOutput/DevelopmentKit_hardware/DEV_KIT_DEMO_top_DataSheet.xml

   1 <?xml version="1.0" encoding="ISO-8859-1" ?>\r
   2 <?xml-stylesheet type="text/xsl" href="datasheet.xsl"?>\r
   3 <datasheet>\r
   4   <header>DEV_KIT_DEMO_top</header>\r
   5   <project-settings>\r
   6     <fam>SmartFusion2</fam>\r
   7     <die>M2S050T_ES</die>\r
   8     <package>896 FBGA</package>\r
   9     <speed-grade>-1</speed-grade>\r
  10     <voltage>1.2</voltage>\r
  11     <hdl-type>Verilog</hdl-type>\r
  12     <project-description>\r
  13     </project-description>\r
  14     <location>D:/Actelprj/SF2_DEVKIT_DEMO/component/work/DEV_KIT_DEMO_top</location>\r
  15     <state>GENERATED ( Wed Apr 24 17:06:15 2013 )</state>\r
  16     <swide-toolchain>SoftConsole workspace generated to D:\Actelprj\SF2_DEVKIT_DEMO\SoftConsole</swide-toolchain>\r
  17   </project-settings>\r
  18   <site-map>\r
  19   </site-map>\r
  20   <fileset>\r
  21     <name>HDL File(s)</name>\r
  22     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vlog\core_obfuscated\coreapb3.v</file>\r
  23     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vlog\core_obfuscated\coreapb3_iaddr_reg.v</file>\r
  24     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v</file>\r
  25     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\COREAXI\2.0.103\rtl\vlog\core_obfuscated\axi_interconnect.v</file>\r
  26     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\COREAXI\2.0.103\rtl\vlog\core_obfuscated\master_stage.v</file>\r
  27     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\COREAXI\2.0.103\rtl\vlog\core_obfuscated\slave_stage.v</file>\r
  28     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreSF2Config\2.0.100\rtl\vlog\core_obfuscated\coresf2config.v</file>\r
  29     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreSF2Reset\1.0.101\rtl\vlog\core_obfuscated\coresf2reset.v</file>\r
  30     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\SgCore\OSC\1.0.100\osc_comps.v</file>\r
  31     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO\CCC_0\DEV_KIT_DEMO_CCC_0_FCCC.v</file>\r
  32     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO\COREAXI_0\rtl\vlog\core_obfuscated\coreaxi.v</file>\r
  33     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO\DEV_KIT_DEMO.v</file>\r
  34     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO\FABOSC_0\DEV_KIT_DEMO_FABOSC_0_OSC.v</file>\r
  35     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_MSS\DEV_KIT_DEMO_MSS.v</file>\r
  36     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_MSS\DEV_KIT_DEMO_MSS_tmp_syn.v</file>\r
  37     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\coreparameters_tgi.v</file>\r
  38     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\acmtable.v</file>\r
  39     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\coreabc.v</file>\r
  40     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\debugblk.v</file>\r
  41     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\instructions.v</file>\r
  42     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\instructnvm_bb.v</file>\r
  43     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\instructram.v</file>\r
  44     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\iram512x9_rtl.v</file>\r
  45     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\ram128x8_smartfusion2.v</file>\r
  46     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\ram256x16_rtl.v</file>\r
  47     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\ram256x8_rtl.v</file>\r
  48     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\ramblocks.v</file>\r
  49     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\support.v</file>\r
  50     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\DEV_KIT_DEMO_top.v</file>\r
  51     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\SERDES_IF_0\DEV_KIT_DEMO_top_SERDES_IF_0_SERDES_IF.v</file>\r
  52     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\SERDES_IF_0\DEV_KIT_DEMO_top_SERDES_IF_0_SERDES_IF_syn.v</file>\r
  53   </fileset>\r
  54   <fileset>\r
  55     <name>Flash Memory File(s)</name>\r
  56     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\./ENVM/ENVM.efc</file>\r
  57     <file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\./ENVM/ENVM.efc\D:/Actelprj/SF2_DEVKIT_DEMO/component/work/DEV_KIT_DEMO_MSS/ENVM/ENVM.efc</file>\r
  58   </fileset>\r
  59   <io>\r
  60     <port-name>USB_ULPI_DATA[3]</port-name>\r
  61     <direction>INOUT</direction>\r
  62     <pin-number>-</pin-number>\r
  63     <io-standard>LVCMOS25</io-standard>\r
  64   </io>\r
  65   <io>\r
  66     <port-name>MDDR_ADDR[11]</port-name>\r
  67     <direction>OUT</direction>\r
  68     <pin-number>-</pin-number>\r
  69     <io-standard>LVCMOS25</io-standard>\r
  70   </io>\r
  71   <io>\r
  72     <port-name>REFCLK0_P</port-name>\r
  73     <direction>IN</direction>\r
  74     <pin-number>-</pin-number>\r
  75     <io-standard>LVCMOS25</io-standard>\r
  76   </io>\r
  77   <io>\r
  78     <port-name>MDDR_ADDR[3]</port-name>\r
  79     <direction>OUT</direction>\r
  80     <pin-number>-</pin-number>\r
  81     <io-standard>LVCMOS25</io-standard>\r
  82   </io>\r
  83   <io>\r
  84     <port-name>MDDR_ADDR[15]</port-name>\r
  85     <direction>OUT</direction>\r
  86     <pin-number>-</pin-number>\r
  87     <io-standard>LVCMOS25</io-standard>\r
  88   </io>\r
  89   <io>\r
  90     <port-name>MDDR_DQ[10]</port-name>\r
  91     <direction>INOUT</direction>\r
  92     <pin-number>-</pin-number>\r
  93     <io-standard>LVCMOS25</io-standard>\r
  94   </io>\r
  95   <io>\r
  96     <port-name>I2C_0_SCL</port-name>\r
  97     <direction>INOUT</direction>\r
  98     <pin-number>-</pin-number>\r
  99     <io-standard>LVCMOS25</io-standard>\r
 100   </io>\r
 101   <io>\r
 102     <port-name>SPI_0_DI</port-name>\r
 103     <direction>IN</direction>\r
 104     <pin-number>-</pin-number>\r
 105     <io-standard>LVCMOS25</io-standard>\r
 106   </io>\r
 107   <io>\r
 108     <port-name>USB_ULPI_DATA[1]</port-name>\r
 109     <direction>INOUT</direction>\r
 110     <pin-number>-</pin-number>\r
 111     <io-standard>LVCMOS25</io-standard>\r
 112   </io>\r
 113   <io>\r
 114     <port-name>TXD0_N</port-name>\r
 115     <direction>OUT</direction>\r
 116     <pin-number>-</pin-number>\r
 117     <io-standard>LVCMOS25</io-standard>\r
 118   </io>\r
 119   <io>\r
 120     <port-name>MDDR_DQ[6]</port-name>\r
 121     <direction>INOUT</direction>\r
 122     <pin-number>-</pin-number>\r
 123     <io-standard>LVCMOS25</io-standard>\r
 124   </io>\r
 125   <io>\r
 126     <port-name>RXD3_N</port-name>\r
 127     <direction>IN</direction>\r
 128     <pin-number>-</pin-number>\r
 129     <io-standard>LVCMOS25</io-standard>\r
 130   </io>\r
 131   <io>\r
 132     <port-name>MDDR_DQ[0]</port-name>\r
 133     <direction>INOUT</direction>\r
 134     <pin-number>-</pin-number>\r
 135     <io-standard>LVCMOS25</io-standard>\r
 136   </io>\r
 137   <io>\r
 138     <port-name>GPIO_13_F2M</port-name>\r
 139     <direction>IN</direction>\r
 140     <pin-number>-</pin-number>\r
 141     <io-standard>LVCMOS25</io-standard>\r
 142   </io>\r
 143   <io>\r
 144     <port-name>MDDR_DQ[8]</port-name>\r
 145     <direction>INOUT</direction>\r
 146     <pin-number>-</pin-number>\r
 147     <io-standard>LVCMOS25</io-standard>\r
 148   </io>\r
 149   <io>\r
 150     <port-name>LED_6</port-name>\r
 151     <direction>OUT</direction>\r
 152     <pin-number>-</pin-number>\r
 153     <io-standard>LVCMOS25</io-standard>\r
 154   </io>\r
 155   <io>\r
 156     <port-name>FF_EXIT</port-name>\r
 157     <direction>IN</direction>\r
 158     <pin-number>-</pin-number>\r
 159     <io-standard>LVCMOS25</io-standard>\r
 160   </io>\r
 161   <io>\r
 162     <port-name>USB_ULPI_DIR</port-name>\r
 163     <direction>IN</direction>\r
 164     <pin-number>-</pin-number>\r
 165     <io-standard>LVCMOS25</io-standard>\r
 166   </io>\r
 167   <io>\r
 168     <port-name>RXD3_P</port-name>\r
 169     <direction>IN</direction>\r
 170     <pin-number>-</pin-number>\r
 171     <io-standard>LVCMOS25</io-standard>\r
 172   </io>\r
 173   <io>\r
 174     <port-name>MDDR_DQ[15]</port-name>\r
 175     <direction>INOUT</direction>\r
 176     <pin-number>-</pin-number>\r
 177     <io-standard>LVCMOS25</io-standard>\r
 178   </io>\r
 179   <io>\r
 180     <port-name>MDDR_ADDR[6]</port-name>\r
 181     <direction>OUT</direction>\r
 182     <pin-number>-</pin-number>\r
 183     <io-standard>LVCMOS25</io-standard>\r
 184   </io>\r
 185   <io>\r
 186     <port-name>GPIO_15_M2F</port-name>\r
 187     <direction>OUT</direction>\r
 188     <pin-number>-</pin-number>\r
 189     <io-standard>LVCMOS25</io-standard>\r
 190   </io>\r
 191   <io>\r
 192     <port-name>MDDR_ADDR[8]</port-name>\r
 193     <direction>OUT</direction>\r
 194     <pin-number>-</pin-number>\r
 195     <io-standard>LVCMOS25</io-standard>\r
 196   </io>\r
 197   <io>\r
 198     <port-name>SPI_0_SS0</port-name>\r
 199     <direction>INOUT</direction>\r
 200     <pin-number>-</pin-number>\r
 201     <io-standard>LVCMOS25</io-standard>\r
 202   </io>\r
 203   <io>\r
 204     <port-name>TXD1_P</port-name>\r
 205     <direction>OUT</direction>\r
 206     <pin-number>-</pin-number>\r
 207     <io-standard>LVCMOS25</io-standard>\r
 208   </io>\r
 209   <io>\r
 210     <port-name>MDDR_WE_N</port-name>\r
 211     <direction>OUT</direction>\r
 212     <pin-number>-</pin-number>\r
 213     <io-standard>LVCMOS25</io-standard>\r
 214   </io>\r
 215   <io>\r
 216     <port-name>MDDR_CS_N</port-name>\r
 217     <direction>OUT</direction>\r
 218     <pin-number>-</pin-number>\r
 219     <io-standard>LVCMOS25</io-standard>\r
 220   </io>\r
 221   <io>\r
 222     <port-name>USB_RESET_N</port-name>\r
 223     <direction>OUT</direction>\r
 224     <pin-number>-</pin-number>\r
 225     <io-standard>LVCMOS25</io-standard>\r
 226   </io>\r
 227   <io>\r
 228     <port-name>TXD0_P</port-name>\r
 229     <direction>OUT</direction>\r
 230     <pin-number>-</pin-number>\r
 231     <io-standard>LVCMOS25</io-standard>\r
 232   </io>\r
 233   <io>\r
 234     <port-name>MDDR_DQ[1]</port-name>\r
 235     <direction>INOUT</direction>\r
 236     <pin-number>-</pin-number>\r
 237     <io-standard>LVCMOS25</io-standard>\r
 238   </io>\r
 239   <io>\r
 240     <port-name>USB_ULPI_DATA[6]</port-name>\r
 241     <direction>INOUT</direction>\r
 242     <pin-number>-</pin-number>\r
 243     <io-standard>LVCMOS25</io-standard>\r
 244   </io>\r
 245   <io>\r
 246     <port-name>MMUART_1_TXD_M2F</port-name>\r
 247     <direction>OUT</direction>\r
 248     <pin-number>-</pin-number>\r
 249     <io-standard>LVCMOS25</io-standard>\r
 250   </io>\r
 251   <io>\r
 252     <port-name>MDDR_DQS_N[1]</port-name>\r
 253     <direction>INOUT</direction>\r
 254     <pin-number>-</pin-number>\r
 255     <io-standard>LVCMOS25</io-standard>\r
 256   </io>\r
 257   <io>\r
 258     <port-name>MDDR_ADDR[9]</port-name>\r
 259     <direction>OUT</direction>\r
 260     <pin-number>-</pin-number>\r
 261     <io-standard>LVCMOS25</io-standard>\r
 262   </io>\r
 263   <io>\r
 264     <port-name>MDDR_ADDR[0]</port-name>\r
 265     <direction>OUT</direction>\r
 266     <pin-number>-</pin-number>\r
 267     <io-standard>LVCMOS25</io-standard>\r
 268   </io>\r
 269   <io>\r
 270     <port-name>MDDR_DQ[13]</port-name>\r
 271     <direction>INOUT</direction>\r
 272     <pin-number>-</pin-number>\r
 273     <io-standard>LVCMOS25</io-standard>\r
 274   </io>\r
 275   <io>\r
 276     <port-name>MDDR_ADDR[5]</port-name>\r
 277     <direction>OUT</direction>\r
 278     <pin-number>-</pin-number>\r
 279     <io-standard>LVCMOS25</io-standard>\r
 280   </io>\r
 281   <io>\r
 282     <port-name>LED_1</port-name>\r
 283     <direction>OUT</direction>\r
 284     <pin-number>-</pin-number>\r
 285     <io-standard>LVCMOS25</io-standard>\r
 286   </io>\r
 287   <io>\r
 288     <port-name>SPI_0_CLK</port-name>\r
 289     <direction>INOUT</direction>\r
 290     <pin-number>-</pin-number>\r
 291     <io-standard>LVCMOS25</io-standard>\r
 292   </io>\r
 293   <io>\r
 294     <port-name>USB_ULPI_XCLK</port-name>\r
 295     <direction>INOUT</direction>\r
 296     <pin-number>-</pin-number>\r
 297     <io-standard>LVCMOS25</io-standard>\r
 298   </io>\r
 299   <io>\r
 300     <port-name>MDDR_RESET_N</port-name>\r
 301     <direction>OUT</direction>\r
 302     <pin-number>-</pin-number>\r
 303     <io-standard>LVCMOS25</io-standard>\r
 304   </io>\r
 305   <io>\r
 306     <port-name>GPIO_4_F2M</port-name>\r
 307     <direction>IN</direction>\r
 308     <pin-number>-</pin-number>\r
 309     <io-standard>LVCMOS25</io-standard>\r
 310   </io>\r
 311   <io>\r
 312     <port-name>MDDR_ADDR[7]</port-name>\r
 313     <direction>OUT</direction>\r
 314     <pin-number>-</pin-number>\r
 315     <io-standard>LVCMOS25</io-standard>\r
 316   </io>\r
 317   <io>\r
 318     <port-name>MDDR_DQ[3]</port-name>\r
 319     <direction>INOUT</direction>\r
 320     <pin-number>-</pin-number>\r
 321     <io-standard>LVCMOS25</io-standard>\r
 322   </io>\r
 323   <io>\r
 324     <port-name>RXD1_N</port-name>\r
 325     <direction>IN</direction>\r
 326     <pin-number>-</pin-number>\r
 327     <io-standard>LVCMOS25</io-standard>\r
 328   </io>\r
 329   <io>\r
 330     <port-name>MDDR_ADDR[1]</port-name>\r
 331     <direction>OUT</direction>\r
 332     <pin-number>-</pin-number>\r
 333     <io-standard>LVCMOS25</io-standard>\r
 334   </io>\r
 335   <io>\r
 336     <port-name>MDDR_DQ[14]</port-name>\r
 337     <direction>INOUT</direction>\r
 338     <pin-number>-</pin-number>\r
 339     <io-standard>LVCMOS25</io-standard>\r
 340   </io>\r
 341   <io>\r
 342     <port-name>USB_ULPI_STP</port-name>\r
 343     <direction>OUT</direction>\r
 344     <pin-number>-</pin-number>\r
 345     <io-standard>LVCMOS25</io-standard>\r
 346   </io>\r
 347   <io>\r
 348     <port-name>MDDR_DQS[1]</port-name>\r
 349     <direction>INOUT</direction>\r
 350     <pin-number>-</pin-number>\r
 351     <io-standard>LVCMOS25</io-standard>\r
 352   </io>\r
 353   <io>\r
 354     <port-name>MDDR_ODT</port-name>\r
 355     <direction>OUT</direction>\r
 356     <pin-number>-</pin-number>\r
 357     <io-standard>LVCMOS25</io-standard>\r
 358   </io>\r
 359   <io>\r
 360     <port-name>RXD0_N</port-name>\r
 361     <direction>IN</direction>\r
 362     <pin-number>-</pin-number>\r
 363     <io-standard>LVCMOS25</io-standard>\r
 364   </io>\r
 365   <io>\r
 366     <port-name>TXD2_N</port-name>\r
 367     <direction>OUT</direction>\r
 368     <pin-number>-</pin-number>\r
 369     <io-standard>LVCMOS25</io-standard>\r
 370   </io>\r
 371   <io>\r
 372     <port-name>MDDR_DQ[2]</port-name>\r
 373     <direction>INOUT</direction>\r
 374     <pin-number>-</pin-number>\r
 375     <io-standard>LVCMOS25</io-standard>\r
 376   </io>\r
 377   <io>\r
 378     <port-name>GPIO_1_F2M</port-name>\r
 379     <direction>IN</direction>\r
 380     <pin-number>-</pin-number>\r
 381     <io-standard>LVCMOS25</io-standard>\r
 382   </io>\r
 383   <io>\r
 384     <port-name>CLK0_PAD</port-name>\r
 385     <direction>IN</direction>\r
 386     <pin-number>-</pin-number>\r
 387     <io-standard>LVCMOS25</io-standard>\r
 388   </io>\r
 389   <io>\r
 390     <port-name>MDDR_ADDR[12]</port-name>\r
 391     <direction>OUT</direction>\r
 392     <pin-number>-</pin-number>\r
 393     <io-standard>LVCMOS25</io-standard>\r
 394   </io>\r
 395   <io>\r
 396     <port-name>SPI_0_DO</port-name>\r
 397     <direction>OUT</direction>\r
 398     <pin-number>-</pin-number>\r
 399     <io-standard>LVCMOS25</io-standard>\r
 400   </io>\r
 401   <io>\r
 402     <port-name>MDDR_ADDR[14]</port-name>\r
 403     <direction>OUT</direction>\r
 404     <pin-number>-</pin-number>\r
 405     <io-standard>LVCMOS25</io-standard>\r
 406   </io>\r
 407   <io>\r
 408     <port-name>GPIO_2_F2M</port-name>\r
 409     <direction>IN</direction>\r
 410     <pin-number>-</pin-number>\r
 411     <io-standard>LVCMOS25</io-standard>\r
 412   </io>\r
 413   <io>\r
 414     <port-name>MDDR_DQ[5]</port-name>\r
 415     <direction>INOUT</direction>\r
 416     <pin-number>-</pin-number>\r
 417     <io-standard>LVCMOS25</io-standard>\r
 418   </io>\r
 419   <io>\r
 420     <port-name>MDDR_DM_RDQS[1]</port-name>\r
 421     <direction>INOUT</direction>\r
 422     <pin-number>-</pin-number>\r
 423     <io-standard>LVCMOS25</io-standard>\r
 424   </io>\r
 425   <io>\r
 426     <port-name>MDDR_BA[1]</port-name>\r
 427     <direction>OUT</direction>\r
 428     <pin-number>-</pin-number>\r
 429     <io-standard>LVCMOS25</io-standard>\r
 430   </io>\r
 431   <io>\r
 432     <port-name>MDDR_DQS_TMATCH_0_IN</port-name>\r
 433     <direction>IN</direction>\r
 434     <pin-number>-</pin-number>\r
 435     <io-standard>LVCMOS25</io-standard>\r
 436   </io>\r
 437   <io>\r
 438     <port-name>MDDR_CLK_N</port-name>\r
 439     <direction>OUT</direction>\r
 440     <pin-number>-</pin-number>\r
 441     <io-standard>LVCMOS25</io-standard>\r
 442   </io>\r
 443   <io>\r
 444     <port-name>USB_ULPI_DATA[4]</port-name>\r
 445     <direction>INOUT</direction>\r
 446     <pin-number>-</pin-number>\r
 447     <io-standard>LVCMOS25</io-standard>\r
 448   </io>\r
 449   <io>\r
 450     <port-name>MDDR_CAS_N</port-name>\r
 451     <direction>OUT</direction>\r
 452     <pin-number>-</pin-number>\r
 453     <io-standard>LVCMOS25</io-standard>\r
 454   </io>\r
 455   <io>\r
 456     <port-name>GPIO_8_F2M</port-name>\r
 457     <direction>IN</direction>\r
 458     <pin-number>-</pin-number>\r
 459     <io-standard>LVCMOS25</io-standard>\r
 460   </io>\r
 461   <io>\r
 462     <port-name>MDDR_DQS_N[0]</port-name>\r
 463     <direction>INOUT</direction>\r
 464     <pin-number>-</pin-number>\r
 465     <io-standard>LVCMOS25</io-standard>\r
 466   </io>\r
 467   <io>\r
 468     <port-name>I2C_1_SDA</port-name>\r
 469     <direction>INOUT</direction>\r
 470     <pin-number>-</pin-number>\r
 471     <io-standard>LVCMOS25</io-standard>\r
 472   </io>\r
 473   <io>\r
 474     <port-name>MDDR_DQ[11]</port-name>\r
 475     <direction>INOUT</direction>\r
 476     <pin-number>-</pin-number>\r
 477     <io-standard>LVCMOS25</io-standard>\r
 478   </io>\r
 479   <io>\r
 480     <port-name>DEVRST_N</port-name>\r
 481     <direction>IN</direction>\r
 482     <pin-number>-</pin-number>\r
 483     <io-standard>LVCMOS25</io-standard>\r
 484   </io>\r
 485   <io>\r
 486     <port-name>TXD1_N</port-name>\r
 487     <direction>OUT</direction>\r
 488     <pin-number>-</pin-number>\r
 489     <io-standard>LVCMOS25</io-standard>\r
 490   </io>\r
 491   <io>\r
 492     <port-name>MDDR_BA[2]</port-name>\r
 493     <direction>OUT</direction>\r
 494     <pin-number>-</pin-number>\r
 495     <io-standard>LVCMOS25</io-standard>\r
 496   </io>\r
 497   <io>\r
 498     <port-name>GPIO_11_F2M</port-name>\r
 499     <direction>IN</direction>\r
 500     <pin-number>-</pin-number>\r
 501     <io-standard>LVCMOS25</io-standard>\r
 502   </io>\r
 503   <io>\r
 504     <port-name>RXD1_P</port-name>\r
 505     <direction>IN</direction>\r
 506     <pin-number>-</pin-number>\r
 507     <io-standard>LVCMOS25</io-standard>\r
 508   </io>\r
 509   <io>\r
 510     <port-name>MDDR_DM_RDQS[0]</port-name>\r
 511     <direction>INOUT</direction>\r
 512     <pin-number>-</pin-number>\r
 513     <io-standard>LVCMOS25</io-standard>\r
 514   </io>\r
 515   <io>\r
 516     <port-name>MDDR_DQS_TMATCH_0_OUT</port-name>\r
 517     <direction>OUT</direction>\r
 518     <pin-number>-</pin-number>\r
 519     <io-standard>LVCMOS25</io-standard>\r
 520   </io>\r
 521   <io>\r
 522     <port-name>MDDR_CKE</port-name>\r
 523     <direction>OUT</direction>\r
 524     <pin-number>-</pin-number>\r
 525     <io-standard>LVCMOS25</io-standard>\r
 526   </io>\r
 527   <io>\r
 528     <port-name>MMUART_1_RXD_F2M</port-name>\r
 529     <direction>IN</direction>\r
 530     <pin-number>-</pin-number>\r
 531     <io-standard>LVCMOS25</io-standard>\r
 532   </io>\r
 533   <io>\r
 534     <port-name>MDDR_DQS[0]</port-name>\r
 535     <direction>INOUT</direction>\r
 536     <pin-number>-</pin-number>\r
 537     <io-standard>LVCMOS25</io-standard>\r
 538   </io>\r
 539   <io>\r
 540     <port-name>MDDR_BA[0]</port-name>\r
 541     <direction>OUT</direction>\r
 542     <pin-number>-</pin-number>\r
 543     <io-standard>LVCMOS25</io-standard>\r
 544   </io>\r
 545   <io>\r
 546     <port-name>USB_ULPI_DATA[5]</port-name>\r
 547     <direction>INOUT</direction>\r
 548     <pin-number>-</pin-number>\r
 549     <io-standard>LVCMOS25</io-standard>\r
 550   </io>\r
 551   <io>\r
 552     <port-name>I2C_0_SDA</port-name>\r
 553     <direction>INOUT</direction>\r
 554     <pin-number>-</pin-number>\r
 555     <io-standard>LVCMOS25</io-standard>\r
 556   </io>\r
 557   <io>\r
 558     <port-name>MDDR_ADDR[13]</port-name>\r
 559     <direction>OUT</direction>\r
 560     <pin-number>-</pin-number>\r
 561     <io-standard>LVCMOS25</io-standard>\r
 562   </io>\r
 563   <io>\r
 564     <port-name>MDDR_CLK</port-name>\r
 565     <direction>OUT</direction>\r
 566     <pin-number>-</pin-number>\r
 567     <io-standard>LVCMOS25</io-standard>\r
 568   </io>\r
 569   <io>\r
 570     <port-name>RXD2_N</port-name>\r
 571     <direction>IN</direction>\r
 572     <pin-number>-</pin-number>\r
 573     <io-standard>LVCMOS25</io-standard>\r
 574   </io>\r
 575   <io>\r
 576     <port-name>MDDR_ADDR[4]</port-name>\r
 577     <direction>OUT</direction>\r
 578     <pin-number>-</pin-number>\r
 579     <io-standard>LVCMOS25</io-standard>\r
 580   </io>\r
 581   <io>\r
 582     <port-name>MDDR_DQ[12]</port-name>\r
 583     <direction>INOUT</direction>\r
 584     <pin-number>-</pin-number>\r
 585     <io-standard>LVCMOS25</io-standard>\r
 586   </io>\r
 587   <io>\r
 588     <port-name>MDDR_DQ[4]</port-name>\r
 589     <direction>INOUT</direction>\r
 590     <pin-number>-</pin-number>\r
 591     <io-standard>LVCMOS25</io-standard>\r
 592   </io>\r
 593   <io>\r
 594     <port-name>I2C_1_SCL</port-name>\r
 595     <direction>INOUT</direction>\r
 596     <pin-number>-</pin-number>\r
 597     <io-standard>LVCMOS25</io-standard>\r
 598   </io>\r
 599   <io>\r
 600     <port-name>MDDR_RAS_N</port-name>\r
 601     <direction>OUT</direction>\r
 602     <pin-number>-</pin-number>\r
 603     <io-standard>LVCMOS25</io-standard>\r
 604   </io>\r
 605   <io>\r
 606     <port-name>TXD3_N</port-name>\r
 607     <direction>OUT</direction>\r
 608     <pin-number>-</pin-number>\r
 609     <io-standard>LVCMOS25</io-standard>\r
 610   </io>\r
 611   <io>\r
 612     <port-name>REFCLK0_N</port-name>\r
 613     <direction>IN</direction>\r
 614     <pin-number>-</pin-number>\r
 615     <io-standard>LVCMOS25</io-standard>\r
 616   </io>\r
 617   <io>\r
 618     <port-name>GPIO_12_F2M</port-name>\r
 619     <direction>IN</direction>\r
 620     <pin-number>-</pin-number>\r
 621     <io-standard>LVCMOS25</io-standard>\r
 622   </io>\r
 623   <io>\r
 624     <port-name>MDDR_ADDR[10]</port-name>\r
 625     <direction>OUT</direction>\r
 626     <pin-number>-</pin-number>\r
 627     <io-standard>LVCMOS25</io-standard>\r
 628   </io>\r
 629   <io>\r
 630     <port-name>MDDR_ADDR[2]</port-name>\r
 631     <direction>OUT</direction>\r
 632     <pin-number>-</pin-number>\r
 633     <io-standard>LVCMOS25</io-standard>\r
 634   </io>\r
 635   <io>\r
 636     <port-name>RXD2_P</port-name>\r
 637     <direction>IN</direction>\r
 638     <pin-number>-</pin-number>\r
 639     <io-standard>LVCMOS25</io-standard>\r
 640   </io>\r
 641   <io>\r
 642     <port-name>USB_ULPI_DATA[0]</port-name>\r
 643     <direction>INOUT</direction>\r
 644     <pin-number>-</pin-number>\r
 645     <io-standard>LVCMOS25</io-standard>\r
 646   </io>\r
 647   <io>\r
 648     <port-name>TXD2_P</port-name>\r
 649     <direction>OUT</direction>\r
 650     <pin-number>-</pin-number>\r
 651     <io-standard>LVCMOS25</io-standard>\r
 652   </io>\r
 653   <io>\r
 654     <port-name>USB_ULPI_DATA[2]</port-name>\r
 655     <direction>INOUT</direction>\r
 656     <pin-number>-</pin-number>\r
 657     <io-standard>LVCMOS25</io-standard>\r
 658   </io>\r
 659   <io>\r
 660     <port-name>USB_ULPI_NXT</port-name>\r
 661     <direction>IN</direction>\r
 662     <pin-number>-</pin-number>\r
 663     <io-standard>LVCMOS25</io-standard>\r
 664   </io>\r
 665   <io>\r
 666     <port-name>GPIO_14_M2F</port-name>\r
 667     <direction>OUT</direction>\r
 668     <pin-number>-</pin-number>\r
 669     <io-standard>LVCMOS25</io-standard>\r
 670   </io>\r
 671   <io>\r
 672     <port-name>MDDR_DQ[7]</port-name>\r
 673     <direction>INOUT</direction>\r
 674     <pin-number>-</pin-number>\r
 675     <io-standard>LVCMOS25</io-standard>\r
 676   </io>\r
 677   <io>\r
 678     <port-name>MDDR_DQ[9]</port-name>\r
 679     <direction>INOUT</direction>\r
 680     <pin-number>-</pin-number>\r
 681     <io-standard>LVCMOS25</io-standard>\r
 682   </io>\r
 683   <io>\r
 684     <port-name>TXD3_P</port-name>\r
 685     <direction>OUT</direction>\r
 686     <pin-number>-</pin-number>\r
 687     <io-standard>LVCMOS25</io-standard>\r
 688   </io>\r
 689   <io>\r
 690     <port-name>RXD0_P</port-name>\r
 691     <direction>IN</direction>\r
 692     <pin-number>-</pin-number>\r
 693     <io-standard>LVCMOS25</io-standard>\r
 694   </io>\r
 695   <io>\r
 696     <port-name>USB_ULPI_DATA[7]</port-name>\r
 697     <direction>INOUT</direction>\r
 698     <pin-number>-</pin-number>\r
 699     <io-standard>LVCMOS25</io-standard>\r
 700   </io>\r
 701   <core type="SpiritModule">\r
 702     <core-exttype>IP</core-exttype>\r
 703     <core-type>SpiritModule</core-type>\r
 704     <core-vendor>Actel</core-vendor>\r
 705     <core-lib>DirectCore</core-lib>\r
 706     <core-intname>COREABC</core-intname>\r
 707     <core-ver>3.4.101</core-ver>\r
 708     <core-desc>CoreABC (APB Bus Controller) is a simple, configurable, low gate count, programmable state machine/controller primarily targeted towards the implementation of AMBA (Advanced Microcontroller Bus Architecture) APB (Advanced Peripheral Bus) based designs. It is particularly suitable where:\r
 709 \r
 710 - a programmable controller is required but a "full blown" CPU such as a Core8051s or Cortex-M1 is not needed or cannot be justified due to cost or resource/size constraints;\r
 711 - a "full blown" CPU based system requires a CoreABC based programmable "offload engine/coprocessor" subsystem for performance reasons;\r
 712 - an Actel Fusion system using, for example, CoreAI, CorePWM etc. requires programmable control either as a standalone design or as a Fusion analog "offload engine/coprocessor" for a larger CPU based system.\r
 713 \r
 714 CoreABC is available through the Libero IDE IP Catalog through which it can be downloaded from a remote web based repository and installed into the user's local vault ready for use. It operates natively within the SmartDesign design entry environment allowing it to be easily instantiated, configured, connected to other IP core instances and generated ready for simulation, synthesis etc.\r
 715 CoreABC is an AMBA3 APB master which can connect to and manage any APB slave peripherals via an AMBA3 APB bus fabric component such as CoreAPB3.\r
 716 \r
 717 CoreABC supports a comprehensive assembler based configurable instruction set architecture and extensive and flexible configuration of size and feature options allowing it to be tuned to meet the resource constraints and processing power requirements of a wide variety of applications.\r
 718 CoreABC supports three program storage modes:\r
 719 \r
 720 - "Hard" mode: program image stored in an internal ROM implemented in FPGA fabric tiles;\r
 721 - "Soft" mode: program image stored in Actel FPGA RAM blocks which are initialized at runtime from the binary image stored in Fusion NVM or an external flash memory;\r
 722 - "NVM" mode (Fusion only): program image stored in and executed directly from Fusion NVM.\r
 723 </core-desc>\r
 724     <core-param>\r
 725       <param-name>NVM with calibration data:</param-name>\r
 726       <param-value>true</param-value>\r
 727       <param-hdlname>ACT_CALIBRATIONDATA</param-hdlname>\r
 728       <param-hdlvalue>1</param-hdlvalue>\r
 729       <param-tag>spirit:hwParameter</param-tag>\r
 730     </core-param>\r
 731     <core-param>\r
 732       <param-name>APB Slot Size:</param-name>\r
 733       <param-value>64k locations</param-value>\r
 734       <param-hdlname>APB_AWIDTH</param-hdlname>\r
 735       <param-hdlvalue>16</param-hdlvalue>\r
 736       <param-tag>spirit:hwParameter</param-tag>\r
 737     </core-param>\r
 738     <core-param>\r
 739       <param-name>APB Data Bus Width:</param-name>\r
 740       <param-value>32</param-value>\r
 741       <param-hdlname>APB_DWIDTH</param-hdlname>\r
 742       <param-hdlvalue>32</param-hdlvalue>\r
 743       <param-tag>spirit:hwParameter</param-tag>\r
 744     </core-param>\r
 745     <core-param>\r
 746       <param-name>Number of APB Slots:</param-name>\r
 747       <param-value>16</param-value>\r
 748       <param-hdlname>APB_SDEPTH</param-hdlname>\r
 749       <param-hdlvalue>16</param-hdlvalue>\r
 750       <param-tag>spirit:hwParameter</param-tag>\r
 751     </core-param>\r
 752     <core-param>\r
 753       <param-name>Verbose Simulation Log:</param-name>\r
 754       <param-value>true</param-value>\r
 755       <param-hdlname>DEBUG</param-hdlname>\r
 756       <param-hdlvalue>1</param-hdlvalue>\r
 757       <param-tag>spirit:hwParameter</param-tag>\r
 758     </core-param>\r
 759     <core-param>\r
 760       <param-name>APBWRT ACM</param-name>\r
 761       <param-value>false</param-value>\r
 762       <param-hdlname>EN_ACM</param-hdlname>\r
 763       <param-hdlvalue>0</param-hdlvalue>\r
 764       <param-tag>spirit:hwParameter</param-tag>\r
 765     </core-param>\r
 766     <core-param>\r
 767       <param-name>ADD, SUB, DEC, CMPLEQ</param-name>\r
 768       <param-value>true</param-value>\r
 769       <param-hdlname>EN_ADD</param-hdlname>\r
 770       <param-hdlvalue>1</param-hdlvalue>\r
 771       <param-tag>spirit:hwParameter</param-tag>\r
 772     </core-param>\r
 773     <core-param>\r
 774       <param-name>ALU Operations from Memory:</param-name>\r
 775       <param-value>false</param-value>\r
 776       <param-hdlname>EN_ALURAM</param-hdlname>\r
 777       <param-hdlvalue>0</param-hdlvalue>\r
 778       <param-tag>spirit:hwParameter</param-tag>\r
 779     </core-param>\r
 780     <core-param>\r
 781       <param-name>AND, BITCLR, BITTST</param-name>\r
 782       <param-value>true</param-value>\r
 783       <param-hdlname>EN_AND</param-hdlname>\r
 784       <param-hdlvalue>1</param-hdlvalue>\r
 785       <param-tag>spirit:hwParameter</param-tag>\r
 786     </core-param>\r
 787     <core-param>\r
 788       <param-name>CALL, RETURN, RETISR</param-name>\r
 789       <param-value>true</param-value>\r
 790       <param-hdlname>EN_CALL</param-hdlname>\r
 791       <param-hdlvalue>1</param-hdlvalue>\r
 792       <param-tag>spirit:hwParameter</param-tag>\r
 793     </core-param>\r
 794     <core-param>\r
 795       <param-name>Supported Data Sources:</param-name>\r
 796       <param-value>Accumulator and Immediate</param-value>\r
 797       <param-hdlname>EN_DATAM</param-hdlname>\r
 798       <param-hdlvalue>2</param-hdlvalue>\r
 799       <param-tag>spirit:hwParameter</param-tag>\r
 800     </core-param>\r
 801     <core-param>\r
 802       <param-name>INC</param-name>\r
 803       <param-value>true</param-value>\r
 804       <param-hdlname>EN_INC</param-hdlname>\r
 805       <param-hdlvalue>1</param-hdlvalue>\r
 806       <param-tag>spirit:hwParameter</param-tag>\r
 807     </core-param>\r
 808     <core-param>\r
 809       <param-name>APB Indirect Addressing:</param-name>\r
 810       <param-value>false</param-value>\r
 811       <param-hdlname>EN_INDIRECT</param-hdlname>\r
 812       <param-hdlvalue>0</param-hdlvalue>\r
 813       <param-tag>spirit:hwParameter</param-tag>\r
 814     </core-param>\r
 815     <core-param>\r
 816       <param-name>Interrupt Support:</param-name>\r
 817       <param-value>Disabled</param-value>\r
 818       <param-hdlname>EN_INT</param-hdlname>\r
 819       <param-hdlvalue>0</param-hdlvalue>\r
 820       <param-tag>spirit:hwParameter</param-tag>\r
 821     </core-param>\r
 822     <core-param>\r
 823       <param-name>IOREAD</param-name>\r
 824       <param-value>true</param-value>\r
 825       <param-hdlname>EN_IOREAD</param-hdlname>\r
 826       <param-hdlvalue>1</param-hdlvalue>\r
 827       <param-tag>spirit:hwParameter</param-tag>\r
 828     </core-param>\r
 829     <core-param>\r
 830       <param-name>IOWRT</param-name>\r
 831       <param-value>true</param-value>\r
 832       <param-hdlname>EN_IOWRT</param-hdlname>\r
 833       <param-hdlvalue>1</param-hdlvalue>\r
 834       <param-tag>spirit:hwParameter</param-tag>\r
 835     </core-param>\r
 836     <core-param>\r
 837       <param-name>MULT</param-name>\r
 838       <param-value>Not Implemented</param-value>\r
 839       <param-hdlname>EN_MULT</param-hdlname>\r
 840       <param-hdlvalue>0</param-hdlvalue>\r
 841       <param-tag>spirit:hwParameter</param-tag>\r
 842     </core-param>\r
 843     <core-param>\r
 844       <param-name>OR, BITSET</param-name>\r
 845       <param-value>true</param-value>\r
 846       <param-hdlname>EN_OR</param-hdlname>\r
 847       <param-hdlvalue>1</param-hdlvalue>\r
 848       <param-tag>spirit:hwParameter</param-tag>\r
 849     </core-param>\r
 850     <core-param>\r
 851       <param-name>PUSH, POP</param-name>\r
 852       <param-value>true</param-value>\r
 853       <param-hdlname>EN_PUSH</param-hdlname>\r
 854       <param-hdlvalue>1</param-hdlvalue>\r
 855       <param-tag>spirit:hwParameter</param-tag>\r
 856     </core-param>\r
 857     <core-param>\r
 858       <param-name>Internal Data/Stack Memory:</param-name>\r
 859       <param-value>true</param-value>\r
 860       <param-hdlname>EN_RAM</param-hdlname>\r
 861       <param-hdlvalue>1</param-hdlvalue>\r
 862       <param-tag>spirit:hwParameter</param-tag>\r
 863     </core-param>\r
 864     <core-param>\r
 865       <param-name>SHL, ROL</param-name>\r
 866       <param-value>true</param-value>\r
 867       <param-hdlname>EN_SHL</param-hdlname>\r
 868       <param-hdlvalue>1</param-hdlvalue>\r
 869       <param-tag>spirit:hwParameter</param-tag>\r
 870     </core-param>\r
 871     <core-param>\r
 872       <param-name>SHR, ROR</param-name>\r
 873       <param-value>true</param-value>\r
 874       <param-hdlname>EN_SHR</param-hdlname>\r
 875       <param-hdlvalue>1</param-hdlvalue>\r
 876       <param-tag>spirit:hwParameter</param-tag>\r
 877     </core-param>\r
 878     <core-param>\r
 879       <param-name>XOR, CMP</param-name>\r
 880       <param-value>true</param-value>\r
 881       <param-hdlname>EN_XOR</param-hdlname>\r
 882       <param-hdlvalue>1</param-hdlvalue>\r
 883       <param-tag>spirit:hwParameter</param-tag>\r
 884     </core-param>\r
 885     <core-param>\r
 886       <param-name>FPGA Family:</param-name>\r
 887       <param-value>SmartFusion2</param-value>\r
 888       <param-hdlname>FAMILY</param-hdlname>\r
 889       <param-hdlvalue>19</param-hdlvalue>\r
 890       <param-tag>spirit:hwParameter</param-tag>\r
 891     </core-param>\r
 892     <core-param>\r
 893       <param-name>Maximum Number of Instructions:</param-name>\r
 894       <param-value>64</param-value>\r
 895       <param-hdlname>ICWIDTH</param-hdlname>\r
 896       <param-hdlvalue>6</param-hdlvalue>\r
 897       <param-tag>spirit:hwParameter</param-tag>\r
 898     </core-param>\r
 899     <core-param>\r
 900       <param-name>Number of I/O Flags:</param-name>\r
 901       <param-value>0</param-value>\r
 902       <param-hdlname>IFWIDTH</param-hdlname>\r
 903       <param-hdlvalue>0</param-hdlvalue>\r
 904       <param-tag>spirit:hwParameter</param-tag>\r
 905     </core-param>\r
 906     <core-param>\r
 907       <param-name>Number of I/O Inputs:</param-name>\r
 908       <param-value>1</param-value>\r
 909       <param-hdlname>IIWIDTH</param-hdlname>\r
 910       <param-hdlvalue>1</param-hdlvalue>\r
 911       <param-tag>spirit:hwParameter</param-tag>\r
 912     </core-param>\r
 913     <core-param>\r
 914       <param-name>Instruction Memory Access</param-name>\r
 915       <param-value>None</param-value>\r
 916       <param-hdlname>IMEM_APB_ACCESS</param-hdlname>\r
 917       <param-hdlvalue>0</param-hdlvalue>\r
 918       <param-tag>spirit:hwParameter</param-tag>\r
 919     </core-param>\r
 920     <core-param>\r
 921       <param-name>Initialization Width:</param-name>\r
 922       <param-value>11</param-value>\r
 923       <param-hdlname>INITWIDTH</param-hdlname>\r
 924       <param-hdlvalue>11</param-hdlvalue>\r
 925       <param-tag>spirit:hwParameter</param-tag>\r
 926     </core-param>\r
 927     <core-param>\r
 928       <param-name>Instruction Store:</param-name>\r
 929       <param-value>Hard (FPGA Tiles)</param-value>\r
 930       <param-hdlname>INSMODE</param-hdlname>\r
 931       <param-hdlvalue>0</param-hdlvalue>\r
 932       <param-tag>spirit:hwParameter</param-tag>\r
 933     </core-param>\r
 934     <core-param>\r
 935       <param-name>Number of I/O Outputs:</param-name>\r
 936       <param-value>1</param-value>\r
 937       <param-hdlname>IOWIDTH</param-hdlname>\r
 938       <param-hdlvalue>1</param-hdlvalue>\r
 939       <param-tag>spirit:hwParameter</param-tag>\r
 940     </core-param>\r
 941     <core-param>\r
 942       <param-name>ISR Address:</param-name>\r
 943       <param-value>1</param-value>\r
 944       <param-hdlname>ISRADDR</param-hdlname>\r
 945       <param-hdlvalue>1</param-hdlvalue>\r
 946       <param-tag>spirit:hwParameter</param-tag>\r
 947     </core-param>\r
 948     <core-param>\r
 949       <param-name>\r
 950       </param-name>\r
 951       <param-value>32</param-value>\r
 952       <param-hdlname>MAX_NVMDWIDTH</param-hdlname>\r
 953       <param-hdlvalue>32</param-hdlvalue>\r
 954       <param-tag>spirit:hwParameter</param-tag>\r
 955     </core-param>\r
 956     <core-param>\r
 957       <param-name>Stack Size:</param-name>\r
 958       <param-value>16</param-value>\r
 959       <param-hdlname>STWIDTH</param-hdlname>\r
 960       <param-hdlvalue>4</param-hdlvalue>\r
 961       <param-tag>spirit:hwParameter</param-tag>\r
 962     </core-param>\r
 963     <core-param>\r
 964       <param-name>Test Mode:</param-name>\r
 965       <param-value>User  configured code</param-value>\r
 966       <param-hdlname>TESTMODE</param-hdlname>\r
 967       <param-hdlvalue>0</param-hdlvalue>\r
 968       <param-tag>spirit:hwParameter</param-tag>\r
 969     </core-param>\r
 970     <core-param>\r
 971       <param-name>\r
 972       </param-name>\r
 973       <param-value>26</param-value>\r
 974       <param-hdlname>UNIQ_STRING_LENGTH</param-hdlname>\r
 975       <param-hdlvalue>26</param-hdlvalue>\r
 976       <param-tag>spirit:hwParameter</param-tag>\r
 977     </core-param>\r
 978     <core-param>\r
 979       <param-name>Z Register Size (Bits):</param-name>\r
 980       <param-value>Disabled</param-value>\r
 981       <param-hdlname>ZRWIDTH</param-hdlname>\r
 982       <param-hdlvalue>0</param-hdlvalue>\r
 983       <param-tag>spirit:hwParameter</param-tag>\r
 984     </core-param>\r
 985     <core-name>COREABC_0</core-name>\r
 986   </core>\r
 987   <core type="SpiritModule">\r
 988     <core-exttype>IP</core-exttype>\r
 989     <core-type>SpiritModule</core-type>\r
 990     <core-vendor>Actel</core-vendor>\r
 991     <core-lib>DirectCore</core-lib>\r
 992     <core-intname>CoreAPB3</core-intname>\r
 993     <core-ver>4.0.100</core-ver>\r
 994     <core-desc>\r
 995 The CoreAPB3 component implements an APB3 (AMBA3 APB) fabric, which is backwards compatible with APB2 slave peripherals.\r
 996 \r
 997 There is one APB3 Master interface.\r
 998 \r
 999         </core-desc>\r
1000     <core-param>\r
1001       <param-name>APB Master Data Bus Width</param-name>\r
1002       <param-value>32-bit</param-value>\r
1003       <param-hdlname>APB_DWIDTH</param-hdlname>\r
1004       <param-hdlvalue>32</param-hdlvalue>\r
1005       <param-tag>spirit:hwParameter</param-tag>\r
1006     </core-param>\r
1007     <core-param>\r
1008       <param-name>Slot 0:</param-name>\r
1009       <param-value>true</param-value>\r
1010       <param-hdlname>APBSLOT0ENABLE</param-hdlname>\r
1011       <param-hdlvalue>1</param-hdlvalue>\r
1012       <param-tag>spirit:hwParameter</param-tag>\r
1013     </core-param>\r
1014     <core-param>\r
1015       <param-name>Slot 1:</param-name>\r
1016       <param-value>false</param-value>\r
1017       <param-hdlname>APBSLOT1ENABLE</param-hdlname>\r
1018       <param-hdlvalue>0</param-hdlvalue>\r
1019       <param-tag>spirit:hwParameter</param-tag>\r
1020     </core-param>\r
1021     <core-param>\r
1022       <param-name>Slot 2:</param-name>\r
1023       <param-value>false</param-value>\r
1024       <param-hdlname>APBSLOT2ENABLE</param-hdlname>\r
1025       <param-hdlvalue>0</param-hdlvalue>\r
1026       <param-tag>spirit:hwParameter</param-tag>\r
1027     </core-param>\r
1028     <core-param>\r
1029       <param-name>Slot 3:</param-name>\r
1030       <param-value>false</param-value>\r
1031       <param-hdlname>APBSLOT3ENABLE</param-hdlname>\r
1032       <param-hdlvalue>0</param-hdlvalue>\r
1033       <param-tag>spirit:hwParameter</param-tag>\r
1034     </core-param>\r
1035     <core-param>\r
1036       <param-name>Slot 4:</param-name>\r
1037       <param-value>false</param-value>\r
1038       <param-hdlname>APBSLOT4ENABLE</param-hdlname>\r
1039       <param-hdlvalue>0</param-hdlvalue>\r
1040       <param-tag>spirit:hwParameter</param-tag>\r
1041     </core-param>\r
1042     <core-param>\r
1043       <param-name>Slot 5:</param-name>\r
1044       <param-value>false</param-value>\r
1045       <param-hdlname>APBSLOT5ENABLE</param-hdlname>\r
1046       <param-hdlvalue>0</param-hdlvalue>\r
1047       <param-tag>spirit:hwParameter</param-tag>\r
1048     </core-param>\r
1049     <core-param>\r
1050       <param-name>Slot 6:</param-name>\r
1051       <param-value>false</param-value>\r
1052       <param-hdlname>APBSLOT6ENABLE</param-hdlname>\r
1053       <param-hdlvalue>0</param-hdlvalue>\r
1054       <param-tag>spirit:hwParameter</param-tag>\r
1055     </core-param>\r
1056     <core-param>\r
1057       <param-name>Slot 7:</param-name>\r
1058       <param-value>false</param-value>\r
1059       <param-hdlname>APBSLOT7ENABLE</param-hdlname>\r
1060       <param-hdlvalue>0</param-hdlvalue>\r
1061       <param-tag>spirit:hwParameter</param-tag>\r
1062     </core-param>\r
1063     <core-param>\r
1064       <param-name>Slot 8:</param-name>\r
1065       <param-value>false</param-value>\r
1066       <param-hdlname>APBSLOT8ENABLE</param-hdlname>\r
1067       <param-hdlvalue>0</param-hdlvalue>\r
1068       <param-tag>spirit:hwParameter</param-tag>\r
1069     </core-param>\r
1070     <core-param>\r
1071       <param-name>Slot 9:</param-name>\r
1072       <param-value>false</param-value>\r
1073       <param-hdlname>APBSLOT9ENABLE</param-hdlname>\r
1074       <param-hdlvalue>0</param-hdlvalue>\r
1075       <param-tag>spirit:hwParameter</param-tag>\r
1076     </core-param>\r
1077     <core-param>\r
1078       <param-name>Slot 10:</param-name>\r
1079       <param-value>false</param-value>\r
1080       <param-hdlname>APBSLOT10ENABLE</param-hdlname>\r
1081       <param-hdlvalue>0</param-hdlvalue>\r
1082       <param-tag>spirit:hwParameter</param-tag>\r
1083     </core-param>\r
1084     <core-param>\r
1085       <param-name>Slot 11:</param-name>\r
1086       <param-value>false</param-value>\r
1087       <param-hdlname>APBSLOT11ENABLE</param-hdlname>\r
1088       <param-hdlvalue>0</param-hdlvalue>\r
1089       <param-tag>spirit:hwParameter</param-tag>\r
1090     </core-param>\r
1091     <core-param>\r
1092       <param-name>Slot 12:</param-name>\r
1093       <param-value>false</param-value>\r
1094       <param-hdlname>APBSLOT12ENABLE</param-hdlname>\r
1095       <param-hdlvalue>0</param-hdlvalue>\r
1096       <param-tag>spirit:hwParameter</param-tag>\r
1097     </core-param>\r
1098     <core-param>\r
1099       <param-name>Slot 13:</param-name>\r
1100       <param-value>false</param-value>\r
1101       <param-hdlname>APBSLOT13ENABLE</param-hdlname>\r
1102       <param-hdlvalue>0</param-hdlvalue>\r
1103       <param-tag>spirit:hwParameter</param-tag>\r
1104     </core-param>\r
1105     <core-param>\r
1106       <param-name>Slot 14:</param-name>\r
1107       <param-value>false</param-value>\r
1108       <param-hdlname>APBSLOT14ENABLE</param-hdlname>\r
1109       <param-hdlvalue>0</param-hdlvalue>\r
1110       <param-tag>spirit:hwParameter</param-tag>\r
1111     </core-param>\r
1112     <core-param>\r
1113       <param-name>Slot 15:</param-name>\r
1114       <param-value>false</param-value>\r
1115       <param-hdlname>APBSLOT15ENABLE</param-hdlname>\r
1116       <param-hdlvalue>0</param-hdlvalue>\r
1117       <param-tag>spirit:hwParameter</param-tag>\r
1118     </core-param>\r
1119     <core-param>\r
1120       <param-name>Indirect Addressing:</param-name>\r
1121       <param-value>Indirect address sourced from register(s) in slot 4 space</param-value>\r
1122       <param-hdlname>IADDR_OPTION</param-hdlname>\r
1123       <param-hdlvalue>6</param-hdlvalue>\r
1124       <param-tag>spirit:hwParameter</param-tag>\r
1125     </core-param>\r
1126     <core-param>\r
1127       <param-name>Number of address bits driven by master:</param-name>\r
1128       <param-value>20</param-value>\r
1129       <param-hdlname>MADDR_BITS</param-hdlname>\r
1130       <param-hdlvalue>20</param-hdlvalue>\r
1131       <param-tag>spirit:hwParameter</param-tag>\r
1132     </core-param>\r
1133     <core-param>\r
1134       <param-name>Slot 0:</param-name>\r
1135       <param-value>false</param-value>\r
1136       <param-hdlname>SC_0</param-hdlname>\r
1137       <param-hdlvalue>0</param-hdlvalue>\r
1138       <param-tag>spirit:hwParameter</param-tag>\r
1139     </core-param>\r
1140     <core-param>\r
1141       <param-name>Slot 1:</param-name>\r
1142       <param-value>false</param-value>\r
1143       <param-hdlname>SC_1</param-hdlname>\r
1144       <param-hdlvalue>0</param-hdlvalue>\r
1145       <param-tag>spirit:hwParameter</param-tag>\r
1146     </core-param>\r
1147     <core-param>\r
1148       <param-name>Slot 2:</param-name>\r
1149       <param-value>false</param-value>\r
1150       <param-hdlname>SC_2</param-hdlname>\r
1151       <param-hdlvalue>0</param-hdlvalue>\r
1152       <param-tag>spirit:hwParameter</param-tag>\r
1153     </core-param>\r
1154     <core-param>\r
1155       <param-name>Slot 3:</param-name>\r
1156       <param-value>false</param-value>\r
1157       <param-hdlname>SC_3</param-hdlname>\r
1158       <param-hdlvalue>0</param-hdlvalue>\r
1159       <param-tag>spirit:hwParameter</param-tag>\r
1160     </core-param>\r
1161     <core-param>\r
1162       <param-name>Slot 4:</param-name>\r
1163       <param-value>false</param-value>\r
1164       <param-hdlname>SC_4</param-hdlname>\r
1165       <param-hdlvalue>0</param-hdlvalue>\r
1166       <param-tag>spirit:hwParameter</param-tag>\r
1167     </core-param>\r
1168     <core-param>\r
1169       <param-name>Slot 5:</param-name>\r
1170       <param-value>false</param-value>\r
1171       <param-hdlname>SC_5</param-hdlname>\r
1172       <param-hdlvalue>0</param-hdlvalue>\r
1173       <param-tag>spirit:hwParameter</param-tag>\r
1174     </core-param>\r
1175     <core-param>\r
1176       <param-name>Slot 6:</param-name>\r
1177       <param-value>false</param-value>\r
1178       <param-hdlname>SC_6</param-hdlname>\r
1179       <param-hdlvalue>0</param-hdlvalue>\r
1180       <param-tag>spirit:hwParameter</param-tag>\r
1181     </core-param>\r
1182     <core-param>\r
1183       <param-name>Slot 7:</param-name>\r
1184       <param-value>false</param-value>\r
1185       <param-hdlname>SC_7</param-hdlname>\r
1186       <param-hdlvalue>0</param-hdlvalue>\r
1187       <param-tag>spirit:hwParameter</param-tag>\r
1188     </core-param>\r
1189     <core-param>\r
1190       <param-name>Slot 8:</param-name>\r
1191       <param-value>false</param-value>\r
1192       <param-hdlname>SC_8</param-hdlname>\r
1193       <param-hdlvalue>0</param-hdlvalue>\r
1194       <param-tag>spirit:hwParameter</param-tag>\r
1195     </core-param>\r
1196     <core-param>\r
1197       <param-name>Slot 9:</param-name>\r
1198       <param-value>false</param-value>\r
1199       <param-hdlname>SC_9</param-hdlname>\r
1200       <param-hdlvalue>0</param-hdlvalue>\r
1201       <param-tag>spirit:hwParameter</param-tag>\r
1202     </core-param>\r
1203     <core-param>\r
1204       <param-name>Slot 10:</param-name>\r
1205       <param-value>false</param-value>\r
1206       <param-hdlname>SC_10</param-hdlname>\r
1207       <param-hdlvalue>0</param-hdlvalue>\r
1208       <param-tag>spirit:hwParameter</param-tag>\r
1209     </core-param>\r
1210     <core-param>\r
1211       <param-name>Slot 11:</param-name>\r
1212       <param-value>false</param-value>\r
1213       <param-hdlname>SC_11</param-hdlname>\r
1214       <param-hdlvalue>0</param-hdlvalue>\r
1215       <param-tag>spirit:hwParameter</param-tag>\r
1216     </core-param>\r
1217     <core-param>\r
1218       <param-name>Slot 12:</param-name>\r
1219       <param-value>false</param-value>\r
1220       <param-hdlname>SC_12</param-hdlname>\r
1221       <param-hdlvalue>0</param-hdlvalue>\r
1222       <param-tag>spirit:hwParameter</param-tag>\r
1223     </core-param>\r
1224     <core-param>\r
1225       <param-name>Slot 13:</param-name>\r
1226       <param-value>false</param-value>\r
1227       <param-hdlname>SC_13</param-hdlname>\r
1228       <param-hdlvalue>0</param-hdlvalue>\r
1229       <param-tag>spirit:hwParameter</param-tag>\r
1230     </core-param>\r
1231     <core-param>\r
1232       <param-name>Slot 14:</param-name>\r
1233       <param-value>false</param-value>\r
1234       <param-hdlname>SC_14</param-hdlname>\r
1235       <param-hdlvalue>0</param-hdlvalue>\r
1236       <param-tag>spirit:hwParameter</param-tag>\r
1237     </core-param>\r
1238     <core-param>\r
1239       <param-name>Slot 15:</param-name>\r
1240       <param-value>false</param-value>\r
1241       <param-hdlname>SC_15</param-hdlname>\r
1242       <param-hdlvalue>0</param-hdlvalue>\r
1243       <param-tag>spirit:hwParameter</param-tag>\r
1244     </core-param>\r
1245     <core-param>\r
1246       <param-name>Position in slave address of upper 4 bits of master address:</param-name>\r
1247       <param-value>[19:16] (Ignored if master address width >= 24 bits)</param-value>\r
1248       <param-hdlname>UPR_NIBBLE_POSN</param-hdlname>\r
1249       <param-hdlvalue>4</param-hdlvalue>\r
1250       <param-tag>spirit:hwParameter</param-tag>\r
1251     </core-param>\r
1252     <core-name>CoreAPB3_0</core-name>\r
1253   </core>\r
1254   <core type="ComponentModule">\r
1255     <core-type>ComponentModule</core-type>\r
1256     <core-exttype>SmartDesign</core-exttype>\r
1257     <core-location>D:/Actelprj/SF2_DEVKIT_DEMO/component/work/DEV_KIT_DEMO</core-location>\r
1258     <core-name>DEV_KIT_DEMO_0</core-name>\r
1259   </core>\r
1260   <core type="SpiritModule">\r
1261     <core-exttype>IP</core-exttype>\r
1262     <core-type>SpiritModule</core-type>\r
1263     <core-vendor>Actel</core-vendor>\r
1264     <core-lib>SgCore</core-lib>\r
1265     <core-intname>SERDES_IF</core-intname>\r
1266     <core-ver>1.0.100</core-ver>\r
1267     <core-desc>SmartFusion2 High Speed Serial Interface</core-desc>\r
1268     <core-name>SERDES_IF_0</core-name>\r
1269   </core>\r
1270   <firmware_core type="FirmWareModule">\r
1271     <core-exttype>IP</core-exttype>\r
1272     <core-type>FirmWareModule</core-type>\r
1273     <core-vendor>Actel</core-vendor>\r
1274     <core-lib>Firmware</core-lib>\r
1275     <core-intname>SmartFusion2_CMSIS</core-intname>\r
1276     <core-ver>2.1.101</core-ver>\r
1277     <core-desc>SmartFusion2 Cortex Microcontroller Software Interface Standard (CMSIS).\r
1278 \r
1279 The firmware package provides:\r
1280 - Cortex-M3 startup code.\r
1281 - CMSIS standard naming for exception and interrupt handlers.\r
1282 - CMSIS standard functions for controlling the Cortex-M3 Nested Vectored Interrupt Controller (NVIC).\r
1283 - peripherals registers description.\r
1284 - hardware abstraction layer (HAL) for FPGA fabric soft-IP peripherirals.\r
1285 \r
1286 These files are required by the SmartFusion2 bare metal peripheral drivers to build correctly.\r
1287 </core-desc>\r
1288     <core-param>\r
1289       <param-name>Software Tool Chain:</param-name>\r
1290       <param-value>SoftConsole</param-value>\r
1291       <param-hdlname>ToolChain</param-hdlname>\r
1292       <param-hdlvalue>0</param-hdlvalue>\r
1293       <param-tag>actel-cc:variantParameter</param-tag>\r
1294     </core-param>\r
1295     <core-name>SmartFusion2_CMSIS_0</core-name>\r
1296   </firmware_core>\r
1297   <firmware_core type="FirmWareModule">\r
1298     <core-exttype>IP</core-exttype>\r
1299     <core-type>FirmWareModule</core-type>\r
1300     <core-vendor>Actel</core-vendor>\r
1301     <core-lib>Firmware</core-lib>\r
1302     <core-intname>SmartFusion2_MSS_GPIO_Driver</core-intname>\r
1303     <core-ver>2.0.101</core-ver>\r
1304     <core-desc>SmartFusion2 microcontroller subsystem (MSS) GPIO bare metal software driver.\r
1305 \r
1306 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
1307     <core-name>SmartFusion2_MSS_GPIO_Driver_0</core-name>\r
1308   </firmware_core>\r
1309   <firmware_core type="FirmWareModule">\r
1310     <core-exttype>IP</core-exttype>\r
1311     <core-type>FirmWareModule</core-type>\r
1312     <core-vendor>Actel</core-vendor>\r
1313     <core-lib>Firmware</core-lib>\r
1314     <core-intname>SmartFusion2_MSS_HPDMA_Driver</core-intname>\r
1315     <core-ver>2.0.101</core-ver>\r
1316     <core-desc>SmartFusion2 microcontroller subsystem (MSS) High Performance DMA bare metal software driver.\r
1317 \r
1318 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
1319     <core-name>SmartFusion2_MSS_HPDMA_Driver_0</core-name>\r
1320   </firmware_core>\r
1321   <firmware_core type="FirmWareModule">\r
1322     <core-exttype>IP</core-exttype>\r
1323     <core-type>FirmWareModule</core-type>\r
1324     <core-vendor>Actel</core-vendor>\r
1325     <core-lib>Firmware</core-lib>\r
1326     <core-intname>SmartFusion2_MSS_I2C_Driver</core-intname>\r
1327     <core-ver>2.0.100</core-ver>\r
1328     <core-desc>SmartFusion2 microcontroller subsystem (MSS) I2C bare metal software driver.\r
1329 \r
1330 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
1331     <core-name>SmartFusion2_MSS_I2C_Driver_0</core-name>\r
1332   </firmware_core>\r
1333   <firmware_core type="FirmWareModule">\r
1334     <core-exttype>IP</core-exttype>\r
1335     <core-type>FirmWareModule</core-type>\r
1336     <core-vendor>Actel</core-vendor>\r
1337     <core-lib>Firmware</core-lib>\r
1338     <core-intname>SmartFusion2_MSS_I2C_Driver</core-intname>\r
1339     <core-ver>2.0.100</core-ver>\r
1340     <core-desc>SmartFusion2 microcontroller subsystem (MSS) I2C bare metal software driver.\r
1341 \r
1342 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
1343     <core-name>SmartFusion2_MSS_I2C_Driver_1</core-name>\r
1344   </firmware_core>\r
1345   <firmware_core type="FirmWareModule">\r
1346     <core-exttype>IP</core-exttype>\r
1347     <core-type>FirmWareModule</core-type>\r
1348     <core-vendor>Actel</core-vendor>\r
1349     <core-lib>Firmware</core-lib>\r
1350     <core-intname>SmartFusion2_MSS_MMUART_Driver</core-intname>\r
1351     <core-ver>2.0.101</core-ver>\r
1352     <core-desc>SmartFusion2 microcontroller subsystem (MSS) MMUART bare metal software driver.\r
1353 \r
1354 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
1355     <core-name>SmartFusion2_MSS_MMUART_Driver_0</core-name>\r
1356   </firmware_core>\r
1357   <firmware_core type="FirmWareModule">\r
1358     <core-exttype>IP</core-exttype>\r
1359     <core-type>FirmWareModule</core-type>\r
1360     <core-vendor>Actel</core-vendor>\r
1361     <core-lib>Firmware</core-lib>\r
1362     <core-intname>SmartFusion2_MSS_PDMA_Driver</core-intname>\r
1363     <core-ver>2.0.102</core-ver>\r
1364     <core-desc>SmartFusion2 microcontroller subsystem (MSS) Peripheral DMA bare metal software driver.\r
1365 \r
1366 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
1367     <core-name>SmartFusion2_MSS_PDMA_Driver_0</core-name>\r
1368   </firmware_core>\r
1369   <firmware_core type="FirmWareModule">\r
1370     <core-exttype>IP</core-exttype>\r
1371     <core-type>FirmWareModule</core-type>\r
1372     <core-vendor>Actel</core-vendor>\r
1373     <core-lib>Firmware</core-lib>\r
1374     <core-intname>SmartFusion2_MSS_RTC_Driver</core-intname>\r
1375     <core-ver>2.0.101</core-ver>\r
1376     <core-desc>SmartFusion2 microcontroller subsystem (MSS) RTC bare metal software driver.\r
1377 \r
1378 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
1379     <core-name>SmartFusion2_MSS_RTC_Driver_0</core-name>\r
1380   </firmware_core>\r
1381   <firmware_core type="FirmWareModule">\r
1382     <core-exttype>IP</core-exttype>\r
1383     <core-type>FirmWareModule</core-type>\r
1384     <core-vendor>Actel</core-vendor>\r
1385     <core-lib>Firmware</core-lib>\r
1386     <core-intname>SmartFusion2_MSS_SPI_Driver</core-intname>\r
1387     <core-ver>2.0.103</core-ver>\r
1388     <core-desc>SmartFusion2 microcontroller subsystem (MSS) SPI bare metal software driver.\r
1389 \r
1390 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
1391     <core-name>SmartFusion2_MSS_SPI_Driver_0</core-name>\r
1392   </firmware_core>\r
1393   <firmware_core type="FirmWareModule">\r
1394     <core-exttype>IP</core-exttype>\r
1395     <core-type>FirmWareModule</core-type>\r
1396     <core-vendor>Actel</core-vendor>\r
1397     <core-lib>Firmware</core-lib>\r
1398     <core-intname>SmartFusion2_MSS_System_Services_Driver</core-intname>\r
1399     <core-ver>2.0.103</core-ver>\r
1400     <core-desc>SmartFusion2 microsontroller subsystem (MSS) System Services software driver.\r
1401 \r
1402 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
1403     <core-name>SmartFusion2_MSS_System_Services_Driver_0</core-name>\r
1404   </firmware_core>\r
1405   <firmware_core type="FirmWareModule">\r
1406     <core-exttype>IP</core-exttype>\r
1407     <core-type>FirmWareModule</core-type>\r
1408     <core-vendor>Actel</core-vendor>\r
1409     <core-lib>Firmware</core-lib>\r
1410     <core-intname>SmartFusion2_MSS_Timer_Driver</core-intname>\r
1411     <core-ver>2.0.101</core-ver>\r
1412     <core-desc>SmartFusion2 microcontroller subsystem (MSS) Timer bare metal software driver.\r
1413 \r
1414 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
1415     <core-name>SmartFusion2_MSS_Timer_Driver_0</core-name>\r
1416   </firmware_core>\r
1417   <firmware_core type="FirmWareModule">\r
1418     <core-exttype>IP</core-exttype>\r
1419     <core-type>FirmWareModule</core-type>\r
1420     <core-vendor>Actel</core-vendor>\r
1421     <core-lib>Firmware</core-lib>\r
1422     <core-intname>SmartFusion2_MSS_USB_Driver</core-intname>\r
1423     <core-ver>2.1.100</core-ver>\r
1424     <core-desc>SmartFusion2 microcontroller subsystem (MSS) USB bare metal software driver.\r
1425 \r
1426 The firmware package provides:\r
1427 - MSS USB Device Core Driver \r
1428 - USB MSC Device Class driver with example project.\r
1429 - USB CDC Device Class driver with example project.\r
1430 - USB HID Device Class driver with example project.\r
1431 \r
1432 \r
1433 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
1434     <core-name>SmartFusion2_MSS_USB_Driver_0</core-name>\r
1435   </firmware_core>\r
1436   <firmware_core type="FirmWareModule">\r
1437     <core-exttype>IP</core-exttype>\r
1438     <core-type>FirmWareModule</core-type>\r
1439     <core-vendor>Actel</core-vendor>\r
1440     <core-lib>Firmware</core-lib>\r
1441     <core-intname>SmartFusion2_MSS_Watchdog_Driver</core-intname>\r
1442     <core-ver>2.0.102</core-ver>\r
1443     <core-desc>SmartFusion2 microcontroller subsystem (MSS) Watchdog bare metal software driver.\r
1444 \r
1445 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
1446     <core-name>SmartFusion2_MSS_Watchdog_Driver_0</core-name>\r
1447   </firmware_core>\r
1448   <memorysystem>\r
1449     <title>Memory Map for DEV_KIT_DEMO_top</title>\r
1450     <description>The project contains the following subsystems:</description>\r
1451     <subsystems>\r
1452       <subsystem>\r
1453         <name>CM3</name>\r
1454         <master>CM3</master>\r
1455         <master>FABRIC2MSSFIC2</master>\r
1456         <master>FABRICTOMSSFIC0_APB_BRIDGE</master>\r
1457         <addressNames>\r
1458           <count>1</count>\r
1459           <name>\r
1460           </name>\r
1461         </addressNames>\r
1462         <slave>\r
1463           <name>FIC32_REGION5</name>\r
1464           <fullPinName>\r
1465           </fullPinName>\r
1466           <remapAddress>0xF0000000</remapAddress>\r
1467           <fullAddressSpace>0xF0000000 - 0xFFFFFFFF</fullAddressSpace>\r
1468           <range>0x10000000</range>\r
1469         </slave>\r
1470         <slave>\r
1471           <name>DDR_0_SPACE_3</name>\r
1472           <fullPinName>\r
1473           </fullPinName>\r
1474           <remapAddress>0xD0000000</remapAddress>\r
1475           <fullAddressSpace>0xD0000000 - 0xDFFFFFFF</fullAddressSpace>\r
1476           <range>0x10000000</range>\r
1477         </slave>\r
1478         <slave>\r
1479           <name>DDR_0_SPACE_2</name>\r
1480           <fullPinName>\r
1481           </fullPinName>\r
1482           <remapAddress>0xC0000000</remapAddress>\r
1483           <fullAddressSpace>0xC0000000 - 0xCFFFFFFF</fullAddressSpace>\r
1484           <range>0x10000000</range>\r
1485         </slave>\r
1486         <slave>\r
1487           <name>DDR_0_SPACE_1</name>\r
1488           <fullPinName>\r
1489           </fullPinName>\r
1490           <remapAddress>0xB0000000</remapAddress>\r
1491           <fullAddressSpace>0xB0000000 - 0xBFFFFFFF</fullAddressSpace>\r
1492           <range>0x10000000</range>\r
1493         </slave>\r
1494         <slave>\r
1495           <name>DDR_0_SPACE_0</name>\r
1496           <fullPinName>\r
1497           </fullPinName>\r
1498           <remapAddress>0xA0000000</remapAddress>\r
1499           <fullAddressSpace>0xA0000000 - 0xAFFFFFFF</fullAddressSpace>\r
1500           <range>0x10000000</range>\r
1501         </slave>\r
1502         <slave>\r
1503           <name>FIC32_REGION4</name>\r
1504           <fullPinName>\r
1505           </fullPinName>\r
1506           <remapAddress>0x90000000</remapAddress>\r
1507           <fullAddressSpace>0x90000000 - 0x9FFFFFFF</fullAddressSpace>\r
1508           <range>0x10000000</range>\r
1509         </slave>\r
1510         <slave>\r
1511           <name>FIC32_REGION3</name>\r
1512           <fullPinName>\r
1513           </fullPinName>\r
1514           <remapAddress>0x80000000</remapAddress>\r
1515           <fullAddressSpace>0x80000000 - 0x8FFFFFFF</fullAddressSpace>\r
1516           <range>0x10000000</range>\r
1517         </slave>\r
1518         <slave>\r
1519           <name>AHB2ENVM1_REGISTERS</name>\r
1520           <fullPinName>\r
1521           </fullPinName>\r
1522           <remapAddress>0x600C0000</remapAddress>\r
1523           <fullAddressSpace>0x600C0000 - 0x600FFFFF</fullAddressSpace>\r
1524           <range>0x00040000</range>\r
1525         </slave>\r
1526         <slave>\r
1527           <name>AHB2ENVM0_REGISTERS</name>\r
1528           <fullPinName>\r
1529           </fullPinName>\r
1530           <remapAddress>0x60080000</remapAddress>\r
1531           <fullAddressSpace>0x60080000 - 0x600BFFFF</fullAddressSpace>\r
1532           <range>0x00040000</range>\r
1533         </slave>\r
1534         <slave>\r
1535           <name>ENVM1</name>\r
1536           <fullPinName>\r
1537           </fullPinName>\r
1538           <remapAddress>0x60040000</remapAddress>\r
1539           <fullAddressSpace>0x60040000 - 0x6007FFFF</fullAddressSpace>\r
1540           <range>0x00040000</range>\r
1541         </slave>\r
1542         <slave>\r
1543           <name>ENVM0</name>\r
1544           <fullPinName>\r
1545           </fullPinName>\r
1546           <remapAddress>0x60000000</remapAddress>\r
1547           <fullAddressSpace>0x60000000 - 0x6003FFFF</fullAddressSpace>\r
1548           <range>0x00040000</range>\r
1549         </slave>\r
1550         <slave>\r
1551           <name>FIC32_REGION1</name>\r
1552           <fullPinName>\r
1553           </fullPinName>\r
1554           <remapAddress>0x50000000</remapAddress>\r
1555           <fullAddressSpace>0x50000000 - 0x5FFFFFFF</fullAddressSpace>\r
1556           <range>0x10000000</range>\r
1557         </slave>\r
1558         <slave>\r
1559           <name>CACHE_BACKDOOR</name>\r
1560           <fullPinName>\r
1561           </fullPinName>\r
1562           <remapAddress>0x40400000</remapAddress>\r
1563           <fullAddressSpace>0x40400000 - 0x4040FFFF</fullAddressSpace>\r
1564           <range>0x00010000</range>\r
1565         </slave>\r
1566         <slave>\r
1567           <name>USB</name>\r
1568           <fullPinName>\r
1569           </fullPinName>\r
1570           <remapAddress>0x40043000</remapAddress>\r
1571           <fullAddressSpace>0x40043000 - 0x40043FFF</fullAddressSpace>\r
1572           <range>0x00001000</range>\r
1573         </slave>\r
1574         <slave>\r
1575           <name>SYSREG</name>\r
1576           <fullPinName>\r
1577           </fullPinName>\r
1578           <remapAddress>0x40038000</remapAddress>\r
1579           <fullAddressSpace>0x40038000 - 0x40038FFF</fullAddressSpace>\r
1580           <range>0x00001000</range>\r
1581           <memoryMap>\r
1582             <name>RegisterMap</name>\r
1583             <addressBlock>\r
1584               <baseAddress>0x0</baseAddress>\r
1585               <range format="long">0x1000</range>\r
1586               <width format="long" id="width">32</width>\r
1587               <register>\r
1588                 <name>ESRAM_CONFIG</name>\r
1589                 <addressOffset>0x0</addressOffset>\r
1590                 <absoluteAddress>0x40038000</absoluteAddress>\r
1591                 <size>32</size>\r
1592                 <access>R/W</access>\r
1593                 <resetValue>0x0</resetValue>\r
1594                 <field>\r
1595                   <name>F2_ESRAMSIZE</name>\r
1596                   <bitNumber>4:3</bitNumber>\r
1597                   <access>R/W</access>\r
1598                   <description>\r
1599                   </description>\r
1600                 </field>\r
1601                 <field>\r
1602                   <name>F2_TESTESRAM1REMAP_SYNC</name>\r
1603                   <bitNumber>2</bitNumber>\r
1604                   <access>R/W</access>\r
1605                   <description>\r
1606                   </description>\r
1607                 </field>\r
1608                 <field>\r
1609                   <name>F2_TESTREMAPENABLE_SYNC</name>\r
1610                   <bitNumber>1</bitNumber>\r
1611                   <access>R/W</access>\r
1612                   <description>\r
1613                   </description>\r
1614                 </field>\r
1615                 <field>\r
1616                   <name>COM_ESRAMFWREMAP</name>\r
1617                   <bitNumber>0</bitNumber>\r
1618                   <access>R/W</access>\r
1619                   <description>\r
1620                   </description>\r
1621                 </field>\r
1622               </register>\r
1623               <register>\r
1624                 <name>ENVM_CONFIG</name>\r
1625                 <addressOffset>0x4</addressOffset>\r
1626                 <absoluteAddress>0x40038004</absoluteAddress>\r
1627                 <size>32</size>\r
1628                 <access>R/W</access>\r
1629                 <resetValue>0x0</resetValue>\r
1630                 <field>\r
1631                   <name>ENVM_SIX_CYCLE</name>\r
1632                   <bitNumber>7</bitNumber>\r
1633                   <access>R/W</access>\r
1634                   <description>\r
1635                   </description>\r
1636                 </field>\r
1637                 <field>\r
1638                   <name>ENVM_PIPE_BYPASS</name>\r
1639                   <bitNumber>6</bitNumber>\r
1640                   <access>R/W</access>\r
1641                   <description>\r
1642                   </description>\r
1643                 </field>\r
1644                 <field>\r
1645                   <name>F2_ENVMPOWEREDDOWN</name>\r
1646                   <bitNumber>5</bitNumber>\r
1647                   <access>R/W</access>\r
1648                   <description>\r
1649                   </description>\r
1650                 </field>\r
1651                 <field>\r
1652                   <name>COM_ENVMREMAPSIZE</name>\r
1653                   <bitNumber>4:0</bitNumber>\r
1654                   <access>R/W</access>\r
1655                   <description>\r
1656                   </description>\r
1657                 </field>\r
1658               </register>\r
1659               <register>\r
1660                 <name>ENVM_REMAP_BASE</name>\r
1661                 <addressOffset>0x8</addressOffset>\r
1662                 <absoluteAddress>0x40038008</absoluteAddress>\r
1663                 <size>32</size>\r
1664                 <access>R/W</access>\r
1665                 <resetValue>0x0</resetValue>\r
1666                 <field>\r
1667                   <name>COM_ENVMREMAPBASE</name>\r
1668                   <bitNumber>19:0</bitNumber>\r
1669                   <access>R/W</access>\r
1670                   <description>\r
1671                   </description>\r
1672                 </field>\r
1673               </register>\r
1674               <register>\r
1675                 <name>ENVM_FAB_REMAP</name>\r
1676                 <addressOffset>0xC</addressOffset>\r
1677                 <absoluteAddress>0x4003800C</absoluteAddress>\r
1678                 <size>32</size>\r
1679                 <access>R/W</access>\r
1680                 <resetValue>0x0</resetValue>\r
1681                 <field>\r
1682                   <name>COM_ENVMFABREMAPBASE</name>\r
1683                   <bitNumber>19:0</bitNumber>\r
1684                   <access>R/W</access>\r
1685                   <description>\r
1686                   </description>\r
1687                 </field>\r
1688               </register>\r
1689               <register>\r
1690                 <name>FAB_PROT_SIZE</name>\r
1691                 <addressOffset>0x10</addressOffset>\r
1692                 <absoluteAddress>0x40038010</absoluteAddress>\r
1693                 <size>32</size>\r
1694                 <access>R/W</access>\r
1695                 <resetValue>0x0</resetValue>\r
1696                 <field>\r
1697                   <name>COM_PROTREGIONSIZE</name>\r
1698                   <bitNumber>4:0</bitNumber>\r
1699                   <access>R/W</access>\r
1700                   <description>\r
1701                   </description>\r
1702                 </field>\r
1703               </register>\r
1704               <register>\r
1705                 <name>FAB_PROT_BASE</name>\r
1706                 <addressOffset>0x14</addressOffset>\r
1707                 <absoluteAddress>0x40038014</absoluteAddress>\r
1708                 <size>32</size>\r
1709                 <access>R/W</access>\r
1710                 <resetValue>0x0</resetValue>\r
1711                 <field>\r
1712                   <name>COM_PROTREGIONBASE</name>\r
1713                   <bitNumber>31:0</bitNumber>\r
1714                   <access>R/W</access>\r
1715                   <description>\r
1716                   </description>\r
1717                 </field>\r
1718               </register>\r
1719               <register>\r
1720                 <name>MATRIX_CONFIG</name>\r
1721                 <addressOffset>0x18</addressOffset>\r
1722                 <absoluteAddress>0x40038018</absoluteAddress>\r
1723                 <size>32</size>\r
1724                 <access>R/W</access>\r
1725                 <resetValue>0x0</resetValue>\r
1726                 <field>\r
1727                   <name>COM_WEIGHTEDMODE</name>\r
1728                   <bitNumber>3</bitNumber>\r
1729                   <access>R/W</access>\r
1730                   <description>\r
1731                   </description>\r
1732                 </field>\r
1733                 <field>\r
1734                   <name>COM_MASTERENABLE</name>\r
1735                   <bitNumber>2:0</bitNumber>\r
1736                   <access>R/W</access>\r
1737                   <description>\r
1738                   </description>\r
1739                 </field>\r
1740               </register>\r
1741               <register>\r
1742                 <name>DSS_STATUS</name>\r
1743                 <addressOffset>0x1C</addressOffset>\r
1744                 <absoluteAddress>0x4003801C</absoluteAddress>\r
1745                 <size>32</size>\r
1746                 <access>R/W</access>\r
1747                 <resetValue>0x0</resetValue>\r
1748                 <field>\r
1749                   <name>PLLLOCKLOSTINT</name>\r
1750                   <bitNumber>10</bitNumber>\r
1751                   <access>R/W</access>\r
1752                   <description>\r
1753                   </description>\r
1754                 </field>\r
1755                 <field>\r
1756                   <name>PLLLOCKINT</name>\r
1757                   <bitNumber>9</bitNumber>\r
1758                   <access>R/W</access>\r
1759                   <description>\r
1760                   </description>\r
1761                 </field>\r
1762                 <field>\r
1763                   <name>COM_ERRORSTATUS</name>\r
1764                   <bitNumber>8:4</bitNumber>\r
1765                   <access>R/W</access>\r
1766                   <description>\r
1767                   </description>\r
1768                 </field>\r
1769                 <field>\r
1770                   <name>BROWNOUT3_3VINT</name>\r
1771                   <bitNumber>3</bitNumber>\r
1772                   <access>R/W</access>\r
1773                   <description>\r
1774                   </description>\r
1775                 </field>\r
1776                 <field>\r
1777                   <name>BROWNOUT1_5VINT</name>\r
1778                   <bitNumber>2</bitNumber>\r
1779                   <access>R/W</access>\r
1780                   <description>\r
1781                   </description>\r
1782                 </field>\r
1783                 <field>\r
1784                   <name>WDOGTIMEOUTEVENT</name>\r
1785                   <bitNumber>1</bitNumber>\r
1786                   <access>R/W</access>\r
1787                   <description>\r
1788                   </description>\r
1789                 </field>\r
1790                 <field>\r
1791                   <name>RTCMATCHEVENT</name>\r
1792                   <bitNumber>0</bitNumber>\r
1793                   <access>R/W</access>\r
1794                   <description>\r
1795                   </description>\r
1796                 </field>\r
1797               </register>\r
1798               <register>\r
1799                 <name>CLR_DSS_STATUS</name>\r
1800                 <addressOffset>0x20</addressOffset>\r
1801                 <absoluteAddress>0x40038020</absoluteAddress>\r
1802                 <size>32</size>\r
1803                 <access>R/W</access>\r
1804                 <resetValue>0x0</resetValue>\r
1805                 <field>\r
1806                   <name>CLRPLLLOCKLOSTINT</name>\r
1807                   <bitNumber>10</bitNumber>\r
1808                   <access>R/W</access>\r
1809                   <description>\r
1810                   </description>\r
1811                 </field>\r
1812                 <field>\r
1813                   <name>CLRPLLLOCKINT</name>\r
1814                   <bitNumber>9</bitNumber>\r
1815                   <access>R/W</access>\r
1816                   <description>\r
1817                   </description>\r
1818                 </field>\r
1819                 <field>\r
1820                   <name>COM_CLEARSTATUS</name>\r
1821                   <bitNumber>8:4</bitNumber>\r
1822                   <access>R/W</access>\r
1823                   <description>\r
1824                   </description>\r
1825                 </field>\r
1826                 <field>\r
1827                   <name>CLRBROWNOUT3_3VINT</name>\r
1828                   <bitNumber>3</bitNumber>\r
1829                   <access>R/W</access>\r
1830                   <description>\r
1831                   </description>\r
1832                 </field>\r
1833                 <field>\r
1834                   <name>CLRBROWNOUT1_5VINT</name>\r
1835                   <bitNumber>2</bitNumber>\r
1836                   <access>R/W</access>\r
1837                   <description>\r
1838                   </description>\r
1839                 </field>\r
1840                 <field>\r
1841                   <name>CLRWDOGTIMEOUTEVENT</name>\r
1842                   <bitNumber>1</bitNumber>\r
1843                   <access>R/W</access>\r
1844                   <description>\r
1845                   </description>\r
1846                 </field>\r
1847                 <field>\r
1848                   <name>CLRRTCMATCHEVENT</name>\r
1849                   <bitNumber>0</bitNumber>\r
1850                   <access>R/W</access>\r
1851                   <description>\r
1852                   </description>\r
1853                 </field>\r
1854               </register>\r
1855               <register>\r
1856                 <name>FROM_CONFIG</name>\r
1857                 <addressOffset>0x24</addressOffset>\r
1858                 <absoluteAddress>0x40038024</absoluteAddress>\r
1859                 <size>32</size>\r
1860                 <access>R/W</access>\r
1861                 <resetValue>0x0</resetValue>\r
1862                 <field>\r
1863                   <name>SYS_TOPT</name>\r
1864                   <bitNumber>3:0</bitNumber>\r
1865                   <access>R/W</access>\r
1866                   <description>\r
1867                   </description>\r
1868                 </field>\r
1869               </register>\r
1870               <register>\r
1871                 <name>IAP_CONFIG</name>\r
1872                 <addressOffset>0x28</addressOffset>\r
1873                 <absoluteAddress>0x40038028</absoluteAddress>\r
1874                 <size>32</size>\r
1875                 <access>R/W</access>\r
1876                 <resetValue>0x0</resetValue>\r
1877                 <field>\r
1878                   <name>SYS_FCFG</name>\r
1879                   <bitNumber>2:0</bitNumber>\r
1880                   <access>R/W</access>\r
1881                   <description>\r
1882                   </description>\r
1883                 </field>\r
1884               </register>\r
1885               <register>\r
1886                 <name>SOFT_INTERRUPT</name>\r
1887                 <addressOffset>0x2C</addressOffset>\r
1888                 <absoluteAddress>0x4003802C</absoluteAddress>\r
1889                 <size>32</size>\r
1890                 <access>R/W</access>\r
1891                 <resetValue>0x0</resetValue>\r
1892                 <field>\r
1893                   <name>SOFTINTERRUPT</name>\r
1894                   <bitNumber>0</bitNumber>\r
1895                   <access>R/W</access>\r
1896                   <description>\r
1897                   </description>\r
1898                 </field>\r
1899               </register>\r
1900               <register>\r
1901                 <name>SOFT_RESET</name>\r
1902                 <addressOffset>0x30</addressOffset>\r
1903                 <absoluteAddress>0x40038030</absoluteAddress>\r
1904                 <size>32</size>\r
1905                 <access>R/W</access>\r
1906                 <resetValue>0x0</resetValue>\r
1907                 <field>\r
1908                   <name>PADRESETENABLE</name>\r
1909                   <bitNumber>19</bitNumber>\r
1910                   <access>R/W</access>\r
1911                   <description>\r
1912                   </description>\r
1913                 </field>\r
1914                 <field>\r
1915                   <name>USERRESETACTIVE</name>\r
1916                   <bitNumber>18</bitNumber>\r
1917                   <access>R/W</access>\r
1918                   <description>\r
1919                   </description>\r
1920                 </field>\r
1921                 <field>\r
1922                   <name>FPGA_SOFTRESET</name>\r
1923                   <bitNumber>17</bitNumber>\r
1924                   <access>R/W</access>\r
1925                   <description>\r
1926                   </description>\r
1927                 </field>\r
1928                 <field>\r
1929                   <name>EXT_SOFTRESET</name>\r
1930                   <bitNumber>16</bitNumber>\r
1931                   <access>R/W</access>\r
1932                   <description>\r
1933                   </description>\r
1934                 </field>\r
1935                 <field>\r
1936                   <name>IAP_SOFTRESET</name>\r
1937                   <bitNumber>15</bitNumber>\r
1938                   <access>R/W</access>\r
1939                   <description>\r
1940                   </description>\r
1941                 </field>\r
1942                 <field>\r
1943                   <name>GPIO_SOFTRESET</name>\r
1944                   <bitNumber>14</bitNumber>\r
1945                   <access>R/W</access>\r
1946                   <description>\r
1947                   </description>\r
1948                 </field>\r
1949                 <field>\r
1950                   <name>ACE_SOFTRESET</name>\r
1951                   <bitNumber>13</bitNumber>\r
1952                   <access>R/W</access>\r
1953                   <description>\r
1954                   </description>\r
1955                 </field>\r
1956                 <field>\r
1957                   <name>I2C1_SOFTRESET</name>\r
1958                   <bitNumber>12</bitNumber>\r
1959                   <access>R/W</access>\r
1960                   <description>\r
1961                   </description>\r
1962                 </field>\r
1963                 <field>\r
1964                   <name>I2C0_SOFTRESET</name>\r
1965                   <bitNumber>11</bitNumber>\r
1966                   <access>R/W</access>\r
1967                   <description>\r
1968                   </description>\r
1969                 </field>\r
1970                 <field>\r
1971                   <name>SPI1_SOFTRESET</name>\r
1972                   <bitNumber>10</bitNumber>\r
1973                   <access>R/W</access>\r
1974                   <description>\r
1975                   </description>\r
1976                 </field>\r
1977                 <field>\r
1978                   <name>SPI0_SOFTRESET</name>\r
1979                   <bitNumber>9</bitNumber>\r
1980                   <access>R/W</access>\r
1981                   <description>\r
1982                   </description>\r
1983                 </field>\r
1984                 <field>\r
1985                   <name>UART1_SOFTRESET</name>\r
1986                   <bitNumber>8</bitNumber>\r
1987                   <access>R/W</access>\r
1988                   <description>\r
1989                   </description>\r
1990                 </field>\r
1991                 <field>\r
1992                   <name>UART0_SOFTRESET</name>\r
1993                   <bitNumber>7</bitNumber>\r
1994                   <access>R/W</access>\r
1995                   <description>\r
1996                   </description>\r
1997                 </field>\r
1998                 <field>\r
1999                   <name>TIMER_SOFTRESET</name>\r
2000                   <bitNumber>6</bitNumber>\r
2001                   <access>R/W</access>\r
2002                   <description>\r
2003                   </description>\r
2004                 </field>\r
2005                 <field>\r
2006                   <name>PDMA_SOFTRESET</name>\r
2007                   <bitNumber>5</bitNumber>\r
2008                   <access>R/W</access>\r
2009                   <description>\r
2010                   </description>\r
2011                 </field>\r
2012                 <field>\r
2013                   <name>MAC_SOFTRESET</name>\r
2014                   <bitNumber>4</bitNumber>\r
2015                   <access>R/W</access>\r
2016                   <description>\r
2017                   </description>\r
2018                 </field>\r
2019                 <field>\r
2020                   <name>EMC_SOFTRESET</name>\r
2021                   <bitNumber>3</bitNumber>\r
2022                   <access>R/W</access>\r
2023                   <description>\r
2024                   </description>\r
2025                 </field>\r
2026                 <field>\r
2027                   <name>ESRAM1_SOFTRESET</name>\r
2028                   <bitNumber>2</bitNumber>\r
2029                   <access>R/W</access>\r
2030                   <description>\r
2031                   </description>\r
2032                 </field>\r
2033                 <field>\r
2034                   <name>ESRAM0_SOFTRESET</name>\r
2035                   <bitNumber>1</bitNumber>\r
2036                   <access>R/W</access>\r
2037                   <description>\r
2038                   </description>\r
2039                 </field>\r
2040                 <field>\r
2041                   <name>ENVM_SOFTRESET</name>\r
2042                   <bitNumber>0</bitNumber>\r
2043                   <access>R/W</access>\r
2044                   <description>\r
2045                   </description>\r
2046                 </field>\r
2047               </register>\r
2048               <register>\r
2049                 <name>DEVICE_STATUS</name>\r
2050                 <addressOffset>0x34</addressOffset>\r
2051                 <absoluteAddress>0x40038034</absoluteAddress>\r
2052                 <size>32</size>\r
2053                 <access>R/W</access>\r
2054                 <resetValue>0x0</resetValue>\r
2055                 <field>\r
2056                   <name>FPGAGOOD_SYNC</name>\r
2057                   <bitNumber>6</bitNumber>\r
2058                   <access>R/W</access>\r
2059                   <description>\r
2060                   </description>\r
2061                 </field>\r
2062                 <field>\r
2063                   <name>FPGAPROGRAMMING_SYNC</name>\r
2064                   <bitNumber>5</bitNumber>\r
2065                   <access>R/W</access>\r
2066                   <description>\r
2067                   </description>\r
2068                 </field>\r
2069                 <field>\r
2070                   <name>F2_PC_ACCESS_SYNC</name>\r
2071                   <bitNumber>4:3</bitNumber>\r
2072                   <access>R/W</access>\r
2073                   <description>\r
2074                   </description>\r
2075                 </field>\r
2076                 <field>\r
2077                   <name>VCCIBGOOD_SYNC</name>\r
2078                   <bitNumber>2</bitNumber>\r
2079                   <access>R/W</access>\r
2080                   <description>\r
2081                   </description>\r
2082                 </field>\r
2083                 <field>\r
2084                   <name>BROWNOUT3_3V_SYNCN</name>\r
2085                   <bitNumber>1</bitNumber>\r
2086                   <access>R/W</access>\r
2087                   <description>\r
2088                   </description>\r
2089                 </field>\r
2090                 <field>\r
2091                   <name>BROWNOUT1_5V_SYNCN</name>\r
2092                   <bitNumber>0</bitNumber>\r
2093                   <access>R/W</access>\r
2094                   <description>\r
2095                   </description>\r
2096                 </field>\r
2097               </register>\r
2098               <register>\r
2099                 <name>SYSTICK_CONFIG</name>\r
2100                 <addressOffset>0x38</addressOffset>\r
2101                 <absoluteAddress>0x40038038</absoluteAddress>\r
2102                 <size>32</size>\r
2103                 <access>R/W</access>\r
2104                 <resetValue>0x0</resetValue>\r
2105                 <field>\r
2106                   <name>STCLK_DIVISOR</name>\r
2107                   <bitNumber>29:28</bitNumber>\r
2108                   <access>R/W</access>\r
2109                   <description>\r
2110                   </description>\r
2111                 </field>\r
2112                 <field>\r
2113                   <name>STCALIB</name>\r
2114                   <bitNumber>25:0</bitNumber>\r
2115                   <access>R/W</access>\r
2116                   <description>\r
2117                   </description>\r
2118                 </field>\r
2119               </register>\r
2120               <register>\r
2121                 <name>EM_MUX_CONFIG</name>\r
2122                 <addressOffset>0x3C</addressOffset>\r
2123                 <absoluteAddress>0x4003803C</absoluteAddress>\r
2124                 <size>32</size>\r
2125                 <access>R/W</access>\r
2126                 <resetValue>0x0</resetValue>\r
2127                 <field>\r
2128                   <name>EM_SEL</name>\r
2129                   <bitNumber>0</bitNumber>\r
2130                   <access>R/W</access>\r
2131                   <description>\r
2132                   </description>\r
2133                 </field>\r
2134               </register>\r
2135               <register>\r
2136                 <name>EM_CONFIG_0</name>\r
2137                 <addressOffset>0x40</addressOffset>\r
2138                 <absoluteAddress>0x40038040</absoluteAddress>\r
2139                 <size>32</size>\r
2140                 <access>R/W</access>\r
2141                 <resetValue>0x0</resetValue>\r
2142                 <field>\r
2143                   <name>EM_CSFE0</name>\r
2144                   <bitNumber>21</bitNumber>\r
2145                   <access>R/W</access>\r
2146                   <description>\r
2147                   </description>\r
2148                 </field>\r
2149                 <field>\r
2150                   <name>EM_WENBEN0</name>\r
2151                   <bitNumber>20</bitNumber>\r
2152                   <access>R/W</access>\r
2153                   <description>\r
2154                   </description>\r
2155                 </field>\r
2156                 <field>\r
2157                   <name>EM_RWPOL0</name>\r
2158                   <bitNumber>19</bitNumber>\r
2159                   <access>R/W</access>\r
2160                   <description>\r
2161                   </description>\r
2162                 </field>\r
2163                 <field>\r
2164                   <name>EM_PIPEWRN0</name>\r
2165                   <bitNumber>18</bitNumber>\r
2166                   <access>R/W</access>\r
2167                   <description>\r
2168                   </description>\r
2169                 </field>\r
2170                 <field>\r
2171                   <name>EM_PIPERDN0</name>\r
2172                   <bitNumber>17</bitNumber>\r
2173                   <access>R/W</access>\r
2174                   <description>\r
2175                   </description>\r
2176                 </field>\r
2177                 <field>\r
2178                   <name>EM_IDD0</name>\r
2179                   <bitNumber>16:15</bitNumber>\r
2180                   <access>R/W</access>\r
2181                   <description>\r
2182                   </description>\r
2183                 </field>\r
2184                 <field>\r
2185                   <name>EM_WRITELAT0</name>\r
2186                   <bitNumber>14:11</bitNumber>\r
2187                   <access>R/W</access>\r
2188                   <description>\r
2189                   </description>\r
2190                 </field>\r
2191                 <field>\r
2192                   <name>EM_RDLATREST0</name>\r
2193                   <bitNumber>10:7</bitNumber>\r
2194                   <access>R/W</access>\r
2195                   <description>\r
2196                   </description>\r
2197                 </field>\r
2198                 <field>\r
2199                   <name>EM_RDLATFIRST0</name>\r
2200                   <bitNumber>6:3</bitNumber>\r
2201                   <access>R/W</access>\r
2202                   <description>\r
2203                   </description>\r
2204                 </field>\r
2205                 <field>\r
2206                   <name>EM_PORTSIZE0</name>\r
2207                   <bitNumber>2</bitNumber>\r
2208                   <access>R/W</access>\r
2209                   <description>\r
2210                   </description>\r
2211                 </field>\r
2212                 <field>\r
2213                   <name>EM_MEMTYPE0</name>\r
2214                   <bitNumber>1:0</bitNumber>\r
2215                   <access>R/W</access>\r
2216                   <description>\r
2217                   </description>\r
2218                 </field>\r
2219               </register>\r
2220               <register>\r
2221                 <name>EM_CONFIG_1</name>\r
2222                 <addressOffset>0x44</addressOffset>\r
2223                 <absoluteAddress>0x40038044</absoluteAddress>\r
2224                 <size>32</size>\r
2225                 <access>R/W</access>\r
2226                 <resetValue>0x0</resetValue>\r
2227                 <field>\r
2228                   <name>EM_CSFE1</name>\r
2229                   <bitNumber>21</bitNumber>\r
2230                   <access>R/W</access>\r
2231                   <description>\r
2232                   </description>\r
2233                 </field>\r
2234                 <field>\r
2235                   <name>EM_WENBEN1</name>\r
2236                   <bitNumber>20</bitNumber>\r
2237                   <access>R/W</access>\r
2238                   <description>\r
2239                   </description>\r
2240                 </field>\r
2241                 <field>\r
2242                   <name>EM_RWPOL1</name>\r
2243                   <bitNumber>19</bitNumber>\r
2244                   <access>R/W</access>\r
2245                   <description>\r
2246                   </description>\r
2247                 </field>\r
2248                 <field>\r
2249                   <name>EM_PIPEWRN1</name>\r
2250                   <bitNumber>18</bitNumber>\r
2251                   <access>R/W</access>\r
2252                   <description>\r
2253                   </description>\r
2254                 </field>\r
2255                 <field>\r
2256                   <name>EM_PIPERDN1</name>\r
2257                   <bitNumber>17</bitNumber>\r
2258                   <access>R/W</access>\r
2259                   <description>\r
2260                   </description>\r
2261                 </field>\r
2262                 <field>\r
2263                   <name>EM_IDD1</name>\r
2264                   <bitNumber>16:15</bitNumber>\r
2265                   <access>R/W</access>\r
2266                   <description>\r
2267                   </description>\r
2268                 </field>\r
2269                 <field>\r
2270                   <name>EM_WRITELAT1</name>\r
2271                   <bitNumber>14:11</bitNumber>\r
2272                   <access>R/W</access>\r
2273                   <description>\r
2274                   </description>\r
2275                 </field>\r
2276                 <field>\r
2277                   <name>EM_RDLATREST1</name>\r
2278                   <bitNumber>10:7</bitNumber>\r
2279                   <access>R/W</access>\r
2280                   <description>\r
2281                   </description>\r
2282                 </field>\r
2283                 <field>\r
2284                   <name>EM_RDLATFIRST1</name>\r
2285                   <bitNumber>6:3</bitNumber>\r
2286                   <access>R/W</access>\r
2287                   <description>\r
2288                   </description>\r
2289                 </field>\r
2290                 <field>\r
2291                   <name>EM_PORTSIZE1</name>\r
2292                   <bitNumber>2</bitNumber>\r
2293                   <access>R/W</access>\r
2294                   <description>\r
2295                   </description>\r
2296                 </field>\r
2297                 <field>\r
2298                   <name>EM_MEMTYPE1</name>\r
2299                   <bitNumber>1:0</bitNumber>\r
2300                   <access>R/W</access>\r
2301                   <description>\r
2302                   </description>\r
2303                 </field>\r
2304               </register>\r
2305               <register>\r
2306                 <name>CLK_CTRL</name>\r
2307                 <addressOffset>0x48</addressOffset>\r
2308                 <absoluteAddress>0x40038048</absoluteAddress>\r
2309                 <size>32</size>\r
2310                 <access>R/W</access>\r
2311                 <resetValue>0x0</resetValue>\r
2312                 <field>\r
2313                   <name>GLBDIVISOR</name>\r
2314                   <bitNumber>13:12</bitNumber>\r
2315                   <access>R/W</access>\r
2316                   <description>\r
2317                   </description>\r
2318                 </field>\r
2319                 <field>\r
2320                   <name>RTCIF_ACMDIVISOR</name>\r
2321                   <bitNumber>11:8</bitNumber>\r
2322                   <access>R/W</access>\r
2323                   <description>\r
2324                   </description>\r
2325                 </field>\r
2326                 <field>\r
2327                   <name>ACLKDIVISOR</name>\r
2328                   <bitNumber>7:6</bitNumber>\r
2329                   <access>R/W</access>\r
2330                   <description>\r
2331                   </description>\r
2332                 </field>\r
2333                 <field>\r
2334                   <name>PCLK1DIVISOR</name>\r
2335                   <bitNumber>5:4</bitNumber>\r
2336                   <access>R/W</access>\r
2337                   <description>\r
2338                   </description>\r
2339                 </field>\r
2340                 <field>\r
2341                   <name>PCLK0DIVISOR</name>\r
2342                   <bitNumber>3:2</bitNumber>\r
2343                   <access>R/W</access>\r
2344                   <description>\r
2345                   </description>\r
2346                 </field>\r
2347                 <field>\r
2348                   <name>RMIICLKSEL</name>\r
2349                   <bitNumber>1</bitNumber>\r
2350                   <access>R/W</access>\r
2351                   <description>\r
2352                   </description>\r
2353                 </field>\r
2354               </register>\r
2355               <register>\r
2356                 <name>CCC_DIV_CONFIG</name>\r
2357                 <addressOffset>0x4C</addressOffset>\r
2358                 <absoluteAddress>0x4003804C</absoluteAddress>\r
2359                 <size>32</size>\r
2360                 <access>R/W</access>\r
2361                 <resetValue>0x0</resetValue>\r
2362                 <field>\r
2363                   <name>OCDIVRST</name>\r
2364                   <bitNumber>22</bitNumber>\r
2365                   <access>R/W</access>\r
2366                   <description>\r
2367                   </description>\r
2368                 </field>\r
2369                 <field>\r
2370                   <name>OCDIVHALF</name>\r
2371                   <bitNumber>21</bitNumber>\r
2372                   <access>R/W</access>\r
2373                   <description>\r
2374                   </description>\r
2375                 </field>\r
2376                 <field>\r
2377                   <name>OCDIV4</name>\r
2378                   <bitNumber>20</bitNumber>\r
2379                   <access>R/W</access>\r
2380                   <description>\r
2381                   </description>\r
2382                 </field>\r
2383                 <field>\r
2384                   <name>OCDIV3</name>\r
2385                   <bitNumber>19</bitNumber>\r
2386                   <access>R/W</access>\r
2387                   <description>\r
2388                   </description>\r
2389                 </field>\r
2390                 <field>\r
2391                   <name>OCDIV2</name>\r
2392                   <bitNumber>18</bitNumber>\r
2393                   <access>R/W</access>\r
2394                   <description>\r
2395                   </description>\r
2396                 </field>\r
2397                 <field>\r
2398                   <name>OCDIV1</name>\r
2399                   <bitNumber>17</bitNumber>\r
2400                   <access>R/W</access>\r
2401                   <description>\r
2402                   </description>\r
2403                 </field>\r
2404                 <field>\r
2405                   <name>OCDIV0</name>\r
2406                   <bitNumber>16</bitNumber>\r
2407                   <access>R/W</access>\r
2408                   <description>\r
2409                   </description>\r
2410                 </field>\r
2411                 <field>\r
2412                   <name>OBDIVRST</name>\r
2413                   <bitNumber>14</bitNumber>\r
2414                   <access>R/W</access>\r
2415                   <description>\r
2416                   </description>\r
2417                 </field>\r
2418                 <field>\r
2419                   <name>OBDIVHALF</name>\r
2420                   <bitNumber>13</bitNumber>\r
2421                   <access>R/W</access>\r
2422                   <description>\r
2423                   </description>\r
2424                 </field>\r
2425                 <field>\r
2426                   <name>OBDIV4</name>\r
2427                   <bitNumber>12</bitNumber>\r
2428                   <access>R/W</access>\r
2429                   <description>\r
2430                   </description>\r
2431                 </field>\r
2432                 <field>\r
2433                   <name>OBDIV3</name>\r
2434                   <bitNumber>11</bitNumber>\r
2435                   <access>R/W</access>\r
2436                   <description>\r
2437                   </description>\r
2438                 </field>\r
2439                 <field>\r
2440                   <name>OBDIV2</name>\r
2441                   <bitNumber>10</bitNumber>\r
2442                   <access>R/W</access>\r
2443                   <description>\r
2444                   </description>\r
2445                 </field>\r
2446                 <field>\r
2447                   <name>OBDIV1</name>\r
2448                   <bitNumber>9</bitNumber>\r
2449                   <access>R/W</access>\r
2450                   <description>\r
2451                   </description>\r
2452                 </field>\r
2453                 <field>\r
2454                   <name>OBDIV0</name>\r
2455                   <bitNumber>8</bitNumber>\r
2456                   <access>R/W</access>\r
2457                   <description>\r
2458                   </description>\r
2459                 </field>\r
2460                 <field>\r
2461                   <name>OADIVRST</name>\r
2462                   <bitNumber>6</bitNumber>\r
2463                   <access>R/W</access>\r
2464                   <description>\r
2465                   </description>\r
2466                 </field>\r
2467                 <field>\r
2468                   <name>OADIVHALF</name>\r
2469                   <bitNumber>5</bitNumber>\r
2470                   <access>R/W</access>\r
2471                   <description>\r
2472                   </description>\r
2473                 </field>\r
2474                 <field>\r
2475                   <name>OADIV4</name>\r
2476                   <bitNumber>4</bitNumber>\r
2477                   <access>R/W</access>\r
2478                   <description>\r
2479                   </description>\r
2480                 </field>\r
2481                 <field>\r
2482                   <name>OADIV3</name>\r
2483                   <bitNumber>3</bitNumber>\r
2484                   <access>R/W</access>\r
2485                   <description>\r
2486                   </description>\r
2487                 </field>\r
2488                 <field>\r
2489                   <name>OADIV2</name>\r
2490                   <bitNumber>2</bitNumber>\r
2491                   <access>R/W</access>\r
2492                   <description>\r
2493                   </description>\r
2494                 </field>\r
2495                 <field>\r
2496                   <name>OADIV1</name>\r
2497                   <bitNumber>1</bitNumber>\r
2498                   <access>R/W</access>\r
2499                   <description>\r
2500                   </description>\r
2501                 </field>\r
2502                 <field>\r
2503                   <name>OADIV0</name>\r
2504                   <bitNumber>0</bitNumber>\r
2505                   <access>R/W</access>\r
2506                   <description>\r
2507                   </description>\r
2508                 </field>\r
2509               </register>\r
2510               <register>\r
2511                 <name>CCC_MUX_CONFIG</name>\r
2512                 <addressOffset>0x50</addressOffset>\r
2513                 <absoluteAddress>0x40038050</absoluteAddress>\r
2514                 <size>32</size>\r
2515                 <access>R/W</access>\r
2516                 <resetValue>0x0</resetValue>\r
2517                 <field>\r
2518                   <name>MODE</name>\r
2519                   <bitNumber>31:30</bitNumber>\r
2520                   <access>R/W</access>\r
2521                   <description>\r
2522                   </description>\r
2523                 </field>\r
2524                 <field>\r
2525                   <name>EN</name>\r
2526                   <bitNumber>29</bitNumber>\r
2527                   <access>R/W</access>\r
2528                   <description>\r
2529                   </description>\r
2530                 </field>\r
2531                 <field>\r
2532                   <name>GLMUXCFG1</name>\r
2533                   <bitNumber>27</bitNumber>\r
2534                   <access>R/W</access>\r
2535                   <description>\r
2536                   </description>\r
2537                 </field>\r
2538                 <field>\r
2539                   <name>GLMUXCFG0</name>\r
2540                   <bitNumber>26</bitNumber>\r
2541                   <access>R/W</access>\r
2542                   <description>\r
2543                   </description>\r
2544                 </field>\r
2545                 <field>\r
2546                   <name>GLMUXSEL1</name>\r
2547                   <bitNumber>25</bitNumber>\r
2548                   <access>R/W</access>\r
2549                   <description>\r
2550                   </description>\r
2551                 </field>\r
2552                 <field>\r
2553                   <name>GLMUXSEL0</name>\r
2554                   <bitNumber>24</bitNumber>\r
2555                   <access>R/W</access>\r
2556                   <description>\r
2557                   </description>\r
2558                 </field>\r
2559                 <field>\r
2560                   <name>BYPASS_PLL3</name>\r
2561                   <bitNumber>22</bitNumber>\r
2562                   <access>R/W</access>\r
2563                   <description>\r
2564                   </description>\r
2565                 </field>\r
2566                 <field>\r
2567                   <name>OCMUX2</name>\r
2568                   <bitNumber>21</bitNumber>\r
2569                   <access>R/W</access>\r
2570                   <description>\r
2571                   </description>\r
2572                 </field>\r
2573                 <field>\r
2574                   <name>OCMUX1</name>\r
2575                   <bitNumber>20</bitNumber>\r
2576                   <access>R/W</access>\r
2577                   <description>\r
2578                   </description>\r
2579                 </field>\r
2580                 <field>\r
2581                   <name>OCMUX0</name>\r
2582                   <bitNumber>19</bitNumber>\r
2583                   <access>R/W</access>\r
2584                   <description>\r
2585                   </description>\r
2586                 </field>\r
2587                 <field>\r
2588                   <name>DYNCSEL</name>\r
2589                   <bitNumber>18</bitNumber>\r
2590                   <access>R/W</access>\r
2591                   <description>\r
2592                   </description>\r
2593                 </field>\r
2594                 <field>\r
2595                   <name>RXCSEL</name>\r
2596                   <bitNumber>17</bitNumber>\r
2597                   <access>R/W</access>\r
2598                   <description>\r
2599                   </description>\r
2600                 </field>\r
2601                 <field>\r
2602                   <name>STATCSEL</name>\r
2603                   <bitNumber>16</bitNumber>\r
2604                   <access>R/W</access>\r
2605                   <description>\r
2606                   </description>\r
2607                 </field>\r
2608                 <field>\r
2609                   <name>BYPASS_PLL2</name>\r
2610                   <bitNumber>14</bitNumber>\r
2611                   <access>R/W</access>\r
2612                   <description>\r
2613                   </description>\r
2614                 </field>\r
2615                 <field>\r
2616                   <name>OBMUX2</name>\r
2617                   <bitNumber>13</bitNumber>\r
2618                   <access>R/W</access>\r
2619                   <description>\r
2620                   </description>\r
2621                 </field>\r
2622                 <field>\r
2623                   <name>OBMUX1</name>\r
2624                   <bitNumber>12</bitNumber>\r
2625                   <access>R/W</access>\r
2626                   <description>\r
2627                   </description>\r
2628                 </field>\r
2629                 <field>\r
2630                   <name>OBMUX0</name>\r
2631                   <bitNumber>11</bitNumber>\r
2632                   <access>R/W</access>\r
2633                   <description>\r
2634                   </description>\r
2635                 </field>\r
2636                 <field>\r
2637                   <name>DYNBSEL</name>\r
2638                   <bitNumber>10</bitNumber>\r
2639                   <access>R/W</access>\r
2640                   <description>\r
2641                   </description>\r
2642                 </field>\r
2643                 <field>\r
2644                   <name>RXBSEL</name>\r
2645                   <bitNumber>9</bitNumber>\r
2646                   <access>R/W</access>\r
2647                   <description>\r
2648                   </description>\r
2649                 </field>\r
2650                 <field>\r
2651                   <name>STATBSEL</name>\r
2652                   <bitNumber>8</bitNumber>\r
2653                   <access>R/W</access>\r
2654                   <description>\r
2655                   </description>\r
2656                 </field>\r
2657                 <field>\r
2658                   <name>BYPASS_PLL1</name>\r
2659                   <bitNumber>6</bitNumber>\r
2660                   <access>R/W</access>\r
2661                   <description>\r
2662                   </description>\r
2663                 </field>\r
2664                 <field>\r
2665                   <name>OAMUX2</name>\r
2666                   <bitNumber>5</bitNumber>\r
2667                   <access>R/W</access>\r
2668                   <description>\r
2669                   </description>\r
2670                 </field>\r
2671                 <field>\r
2672                   <name>OAMUX1</name>\r
2673                   <bitNumber>4</bitNumber>\r
2674                   <access>R/W</access>\r
2675                   <description>\r
2676                   </description>\r
2677                 </field>\r
2678                 <field>\r
2679                   <name>OAMUX0</name>\r
2680                   <bitNumber>3</bitNumber>\r
2681                   <access>R/W</access>\r
2682                   <description>\r
2683                   </description>\r
2684                 </field>\r
2685                 <field>\r
2686                   <name>DYNASEL</name>\r
2687                   <bitNumber>2</bitNumber>\r
2688                   <access>R/W</access>\r
2689                   <description>\r
2690                   </description>\r
2691                 </field>\r
2692                 <field>\r
2693                   <name>RXASEL</name>\r
2694                   <bitNumber>1</bitNumber>\r
2695                   <access>R/W</access>\r
2696                   <description>\r
2697                   </description>\r
2698                 </field>\r
2699                 <field>\r
2700                   <name>STATASEL</name>\r
2701                   <bitNumber>0</bitNumber>\r
2702                   <access>R/W</access>\r
2703                   <description>\r
2704                   </description>\r
2705                 </field>\r
2706               </register>\r
2707               <register>\r
2708                 <name>CCC_PLL_CONFIG</name>\r
2709                 <addressOffset>0x54</addressOffset>\r
2710                 <absoluteAddress>0x40038054</absoluteAddress>\r
2711                 <size>32</size>\r
2712                 <access>R/W</access>\r
2713                 <resetValue>0x0</resetValue>\r
2714                 <field>\r
2715                   <name>POWERDOWN</name>\r
2716                   <bitNumber>31</bitNumber>\r
2717                   <access>R/W</access>\r
2718                   <description>\r
2719                   </description>\r
2720                 </field>\r
2721                 <field>\r
2722                   <name>VCOSEL2</name>\r
2723                   <bitNumber>24</bitNumber>\r
2724                   <access>R/W</access>\r
2725                   <description>\r
2726                   </description>\r
2727                 </field>\r
2728                 <field>\r
2729                   <name>VCOSEL1</name>\r
2730                   <bitNumber>23</bitNumber>\r
2731                   <access>R/W</access>\r
2732                   <description>\r
2733                   </description>\r
2734                 </field>\r
2735                 <field>\r
2736                   <name>VCOSEL0</name>\r
2737                   <bitNumber>22</bitNumber>\r
2738                   <access>R/W</access>\r
2739                   <description>\r
2740                   </description>\r
2741                 </field>\r
2742                 <field>\r
2743                   <name>XDLYSEL</name>\r
2744                   <bitNumber>21</bitNumber>\r
2745                   <access>R/W</access>\r
2746                   <description>\r
2747                   </description>\r
2748                 </field>\r
2749                 <field>\r
2750                   <name>FBDLY4</name>\r
2751                   <bitNumber>20</bitNumber>\r
2752                   <access>R/W</access>\r
2753                   <description>\r
2754                   </description>\r
2755                 </field>\r
2756                 <field>\r
2757                   <name>FBDLY3</name>\r
2758                   <bitNumber>19</bitNumber>\r
2759                   <access>R/W</access>\r
2760                   <description>\r
2761                   </description>\r
2762                 </field>\r
2763                 <field>\r
2764                   <name>FBDLY2</name>\r
2765                   <bitNumber>18</bitNumber>\r
2766                   <access>R/W</access>\r
2767                   <description>\r
2768                   </description>\r
2769                 </field>\r
2770                 <field>\r
2771                   <name>FBDLY1</name>\r
2772                   <bitNumber>17</bitNumber>\r
2773                   <access>R/W</access>\r
2774                   <description>\r
2775                   </description>\r
2776                 </field>\r
2777                 <field>\r
2778                   <name>FBDLY0</name>\r
2779                   <bitNumber>16</bitNumber>\r
2780                   <access>R/W</access>\r
2781                   <description>\r
2782                   </description>\r
2783                 </field>\r
2784                 <field>\r
2785                   <name>FBSEL1</name>\r
2786                   <bitNumber>15</bitNumber>\r
2787                   <access>R/W</access>\r
2788                   <description>\r
2789                   </description>\r
2790                 </field>\r
2791                 <field>\r
2792                   <name>FBSEL0</name>\r
2793                   <bitNumber>14</bitNumber>\r
2794                   <access>R/W</access>\r
2795                   <description>\r
2796                   </description>\r
2797                 </field>\r
2798                 <field>\r
2799                   <name>FBDIV6</name>\r
2800                   <bitNumber>13</bitNumber>\r
2801                   <access>R/W</access>\r
2802                   <description>\r
2803                   </description>\r
2804                 </field>\r
2805                 <field>\r
2806                   <name>FBDIV5</name>\r
2807                   <bitNumber>12</bitNumber>\r
2808                   <access>R/W</access>\r
2809                   <description>\r
2810                   </description>\r
2811                 </field>\r
2812                 <field>\r
2813                   <name>FBDIV4</name>\r
2814                   <bitNumber>11</bitNumber>\r
2815                   <access>R/W</access>\r
2816                   <description>\r
2817                   </description>\r
2818                 </field>\r
2819                 <field>\r
2820                   <name>FBDIV3</name>\r
2821                   <bitNumber>10</bitNumber>\r
2822                   <access>R/W</access>\r
2823                   <description>\r
2824                   </description>\r
2825                 </field>\r
2826                 <field>\r
2827                   <name>FBDIV2</name>\r
2828                   <bitNumber>9</bitNumber>\r
2829                   <access>R/W</access>\r
2830                   <description>\r
2831                   </description>\r
2832                 </field>\r
2833                 <field>\r
2834                   <name>FBDIV1</name>\r
2835                   <bitNumber>8</bitNumber>\r
2836                   <access>R/W</access>\r
2837                   <description>\r
2838                   </description>\r
2839                 </field>\r
2840                 <field>\r
2841                   <name>FBDIV0</name>\r
2842                   <bitNumber>7</bitNumber>\r
2843                   <access>R/W</access>\r
2844                   <description>\r
2845                   </description>\r
2846                 </field>\r
2847                 <field>\r
2848                   <name>FINDIV6</name>\r
2849                   <bitNumber>6</bitNumber>\r
2850                   <access>R/W</access>\r
2851                   <description>\r
2852                   </description>\r
2853                 </field>\r
2854                 <field>\r
2855                   <name>FINDIV5</name>\r
2856                   <bitNumber>5</bitNumber>\r
2857                   <access>R/W</access>\r
2858                   <description>\r
2859                   </description>\r
2860                 </field>\r
2861                 <field>\r
2862                   <name>FINDIV4</name>\r
2863                   <bitNumber>4</bitNumber>\r
2864                   <access>R/W</access>\r
2865                   <description>\r
2866                   </description>\r
2867                 </field>\r
2868                 <field>\r
2869                   <name>FINDIV3</name>\r
2870                   <bitNumber>3</bitNumber>\r
2871                   <access>R/W</access>\r
2872                   <description>\r
2873                   </description>\r
2874                 </field>\r
2875                 <field>\r
2876                   <name>FINDIV2</name>\r
2877                   <bitNumber>2</bitNumber>\r
2878                   <access>R/W</access>\r
2879                   <description>\r
2880                   </description>\r
2881                 </field>\r
2882                 <field>\r
2883                   <name>FINDIV1</name>\r
2884                   <bitNumber>1</bitNumber>\r
2885                   <access>R/W</access>\r
2886                   <description>\r
2887                   </description>\r
2888                 </field>\r
2889                 <field>\r
2890                   <name>FINDIV0</name>\r
2891                   <bitNumber>0</bitNumber>\r
2892                   <access>R/W</access>\r
2893                   <description>\r
2894                   </description>\r
2895                 </field>\r
2896               </register>\r
2897               <register>\r
2898                 <name>CCC_DLY_CONFIG</name>\r
2899                 <addressOffset>0x58</addressOffset>\r
2900                 <absoluteAddress>0x40038058</absoluteAddress>\r
2901                 <size>32</size>\r
2902                 <access>R/W</access>\r
2903                 <resetValue>0x0</resetValue>\r
2904                 <field>\r
2905                   <name>DLYA14</name>\r
2906                   <bitNumber>24</bitNumber>\r
2907                   <access>R/W</access>\r
2908                   <description>\r
2909                   </description>\r
2910                 </field>\r
2911                 <field>\r
2912                   <name>DLYA13</name>\r
2913                   <bitNumber>23</bitNumber>\r
2914                   <access>R/W</access>\r
2915                   <description>\r
2916                   </description>\r
2917                 </field>\r
2918                 <field>\r
2919                   <name>DLYA12</name>\r
2920                   <bitNumber>22</bitNumber>\r
2921                   <access>R/W</access>\r
2922                   <description>\r
2923                   </description>\r
2924                 </field>\r
2925                 <field>\r
2926                   <name>DLYA11</name>\r
2927                   <bitNumber>21</bitNumber>\r
2928                   <access>R/W</access>\r
2929                   <description>\r
2930                   </description>\r
2931                 </field>\r
2932                 <field>\r
2933                   <name>DLYA10</name>\r
2934                   <bitNumber>20</bitNumber>\r
2935                   <access>R/W</access>\r
2936                   <description>\r
2937                   </description>\r
2938                 </field>\r
2939                 <field>\r
2940                   <name>DLYA04</name>\r
2941                   <bitNumber>19</bitNumber>\r
2942                   <access>R/W</access>\r
2943                   <description>\r
2944                   </description>\r
2945                 </field>\r
2946                 <field>\r
2947                   <name>DLYA03</name>\r
2948                   <bitNumber>18</bitNumber>\r
2949                   <access>R/W</access>\r
2950                   <description>\r
2951                   </description>\r
2952                 </field>\r
2953                 <field>\r
2954                   <name>DLYA02</name>\r
2955                   <bitNumber>17</bitNumber>\r
2956                   <access>R/W</access>\r
2957                   <description>\r
2958                   </description>\r
2959                 </field>\r
2960                 <field>\r
2961                   <name>DLYA01</name>\r
2962                   <bitNumber>16</bitNumber>\r
2963                   <access>R/W</access>\r
2964                   <description>\r
2965                   </description>\r
2966                 </field>\r
2967                 <field>\r
2968                   <name>DLYA00</name>\r
2969                   <bitNumber>15</bitNumber>\r
2970                   <access>R/W</access>\r
2971                   <description>\r
2972                   </description>\r
2973                 </field>\r
2974                 <field>\r
2975                   <name>DLYHCC4</name>\r
2976                   <bitNumber>14</bitNumber>\r
2977                   <access>R/W</access>\r
2978                   <description>\r
2979                   </description>\r
2980                 </field>\r
2981                 <field>\r
2982                   <name>DLYHCC3</name>\r
2983                   <bitNumber>13</bitNumber>\r
2984                   <access>R/W</access>\r
2985                   <description>\r
2986                   </description>\r
2987                 </field>\r
2988                 <field>\r
2989                   <name>DLYHCC2</name>\r
2990                   <bitNumber>12</bitNumber>\r
2991                   <access>R/W</access>\r
2992                   <description>\r
2993                   </description>\r
2994                 </field>\r
2995                 <field>\r
2996                   <name>DLYHCC1</name>\r
2997                   <bitNumber>11</bitNumber>\r
2998                   <access>R/W</access>\r
2999                   <description>\r
3000                   </description>\r
3001                 </field>\r
3002                 <field>\r
3003                   <name>DLYHCC0</name>\r
3004                   <bitNumber>10</bitNumber>\r
3005                   <access>R/W</access>\r
3006                   <description>\r
3007                   </description>\r
3008                 </field>\r
3009                 <field>\r
3010                   <name>DLYHCB4</name>\r
3011                   <bitNumber>9</bitNumber>\r
3012                   <access>R/W</access>\r
3013                   <description>\r
3014                   </description>\r
3015                 </field>\r
3016                 <field>\r
3017                   <name>DLYHCB3</name>\r
3018                   <bitNumber>8</bitNumber>\r
3019                   <access>R/W</access>\r
3020                   <description>\r
3021                   </description>\r
3022                 </field>\r
3023                 <field>\r
3024                   <name>DLYHCB2</name>\r
3025                   <bitNumber>7</bitNumber>\r
3026                   <access>R/W</access>\r
3027                   <description>\r
3028                   </description>\r
3029                 </field>\r
3030                 <field>\r
3031                   <name>DLYHCB1</name>\r
3032                   <bitNumber>6</bitNumber>\r
3033                   <access>R/W</access>\r
3034                   <description>\r
3035                   </description>\r
3036                 </field>\r
3037                 <field>\r
3038                   <name>DLYHCB0</name>\r
3039                   <bitNumber>5</bitNumber>\r
3040                   <access>R/W</access>\r
3041                   <description>\r
3042                   </description>\r
3043                 </field>\r
3044                 <field>\r
3045                   <name>DLYHCA4</name>\r
3046                   <bitNumber>4</bitNumber>\r
3047                   <access>R/W</access>\r
3048                   <description>\r
3049                   </description>\r
3050                 </field>\r
3051                 <field>\r
3052                   <name>DLYHCA3</name>\r
3053                   <bitNumber>3</bitNumber>\r
3054                   <access>R/W</access>\r
3055                   <description>\r
3056                   </description>\r
3057                 </field>\r
3058                 <field>\r
3059                   <name>DLYHCA2</name>\r
3060                   <bitNumber>2</bitNumber>\r
3061                   <access>R/W</access>\r
3062                   <description>\r
3063                   </description>\r
3064                 </field>\r
3065                 <field>\r
3066                   <name>DLYHCA1</name>\r
3067                   <bitNumber>1</bitNumber>\r
3068                   <access>R/W</access>\r
3069                   <description>\r
3070                   </description>\r
3071                 </field>\r
3072                 <field>\r
3073                   <name>DLYHCA0</name>\r
3074                   <bitNumber>0</bitNumber>\r
3075                   <access>R/W</access>\r
3076                   <description>\r
3077                   </description>\r
3078                 </field>\r
3079               </register>\r
3080               <register>\r
3081                 <name>CCC_STATUS</name>\r
3082                 <addressOffset>0x5C</addressOffset>\r
3083                 <absoluteAddress>0x4003805C</absoluteAddress>\r
3084                 <size>32</size>\r
3085                 <access>R/W</access>\r
3086                 <resetValue>0x0</resetValue>\r
3087                 <field>\r
3088                   <name>PLLLOCK_SYNC</name>\r
3089                   <bitNumber>0</bitNumber>\r
3090                   <access>R/W</access>\r
3091                   <description>\r
3092                   </description>\r
3093                 </field>\r
3094               </register>\r
3095               <register>\r
3096                 <name>VTG_CTRL</name>\r
3097                 <addressOffset>0x64</addressOffset>\r
3098                 <absoluteAddress>0x40038064</absoluteAddress>\r
3099                 <size>32</size>\r
3100                 <access>R/W</access>\r
3101                 <resetValue>0x0</resetValue>\r
3102                 <field>\r
3103                   <name>BGPSMENABLE</name>\r
3104                   <bitNumber>4</bitNumber>\r
3105                   <access>R/W</access>\r
3106                   <description>\r
3107                   </description>\r
3108                 </field>\r
3109                 <field>\r
3110                   <name>VBATSELECT</name>\r
3111                   <bitNumber>3</bitNumber>\r
3112                   <access>R/W</access>\r
3113                   <description>\r
3114                   </description>\r
3115                 </field>\r
3116                 <field>\r
3117                   <name>RTCIF_CLRPUBINT</name>\r
3118                   <bitNumber>2</bitNumber>\r
3119                   <access>R/W</access>\r
3120                   <description>\r
3121                   </description>\r
3122                 </field>\r
3123                 <field>\r
3124                   <name>RTCIF_VRONENABLE</name>\r
3125                   <bitNumber>1</bitNumber>\r
3126                   <access>R/W</access>\r
3127                   <description>\r
3128                   </description>\r
3129                 </field>\r
3130                 <field>\r
3131                   <name>RTCIF_FWVRON</name>\r
3132                   <bitNumber>0</bitNumber>\r
3133                   <access>R/W</access>\r
3134                   <description>\r
3135                   </description>\r
3136                 </field>\r
3137               </register>\r
3138               <register>\r
3139                 <name>FAB_IF</name>\r
3140                 <addressOffset>0x6C</addressOffset>\r
3141                 <absoluteAddress>0x4003806C</absoluteAddress>\r
3142                 <size>32</size>\r
3143                 <access>R/W</access>\r
3144                 <resetValue>0x0</resetValue>\r
3145                 <field>\r
3146                   <name>FABCALIBFAIL</name>\r
3147                   <bitNumber>6</bitNumber>\r
3148                   <access>R/W</access>\r
3149                   <description>\r
3150                   </description>\r
3151                 </field>\r
3152                 <field>\r
3153                   <name>FABCALIBSTART</name>\r
3154                   <bitNumber>5</bitNumber>\r
3155                   <access>R/W</access>\r
3156                   <description>\r
3157                   </description>\r
3158                 </field>\r
3159                 <field>\r
3160                   <name>F2_LARGE_CT_XS</name>\r
3161                   <bitNumber>4</bitNumber>\r
3162                   <access>R/W</access>\r
3163                   <description>\r
3164                   </description>\r
3165                 </field>\r
3166                 <field>\r
3167                   <name>FAB_APB32</name>\r
3168                   <bitNumber>3</bitNumber>\r
3169                   <access>R/W</access>\r
3170                   <description>\r
3171                   </description>\r
3172                 </field>\r
3173                 <field>\r
3174                   <name>FAB_AHBIF</name>\r
3175                   <bitNumber>2</bitNumber>\r
3176                   <access>R/W</access>\r
3177                   <description>\r
3178                   </description>\r
3179                 </field>\r
3180                 <field>\r
3181                   <name>F2_AHBCAPABLE</name>\r
3182                   <bitNumber>1</bitNumber>\r
3183                   <access>R/W</access>\r
3184                   <description>\r
3185                   </description>\r
3186                 </field>\r
3187                 <field>\r
3188                   <name>FAB_AHB_BYPASS</name>\r
3189                   <bitNumber>0</bitNumber>\r
3190                   <access>R/W</access>\r
3191                   <description>\r
3192                   </description>\r
3193                 </field>\r
3194               </register>\r
3195               <register>\r
3196                 <name>APB_EXTN</name>\r
3197                 <addressOffset>0x70</addressOffset>\r
3198                 <absoluteAddress>0x40038070</absoluteAddress>\r
3199                 <size>32</size>\r
3200                 <access>R/W</access>\r
3201                 <resetValue>0x0</resetValue>\r
3202                 <field>\r
3203                   <name>APB16_XHOLD</name>\r
3204                   <bitNumber>15:0</bitNumber>\r
3205                   <access>R/W</access>\r
3206                   <description>\r
3207                   </description>\r
3208                 </field>\r
3209               </register>\r
3210               <register>\r
3211                 <name>LOOPBACK_CTRL</name>\r
3212                 <addressOffset>0x74</addressOffset>\r
3213                 <absoluteAddress>0x40038074</absoluteAddress>\r
3214                 <size>32</size>\r
3215                 <access>R/W</access>\r
3216                 <resetValue>0x0</resetValue>\r
3217                 <field>\r
3218                   <name>DSS_EMACLOOPBACK</name>\r
3219                   <bitNumber>4</bitNumber>\r
3220                   <access>R/W</access>\r
3221                   <description>\r
3222                   </description>\r
3223                 </field>\r
3224                 <field>\r
3225                   <name>DSS_GPIOLOOPBACK</name>\r
3226                   <bitNumber>3</bitNumber>\r
3227                   <access>R/W</access>\r
3228                   <description>\r
3229                   </description>\r
3230                 </field>\r
3231                 <field>\r
3232                   <name>DSS_I2CLOOPBACK</name>\r
3233                   <bitNumber>2</bitNumber>\r
3234                   <access>R/W</access>\r
3235                   <description>\r
3236                   </description>\r
3237                 </field>\r
3238                 <field>\r
3239                   <name>DSS_SPILOOPBACK</name>\r
3240                   <bitNumber>1</bitNumber>\r
3241                   <access>R/W</access>\r
3242                   <description>\r
3243                   </description>\r
3244                 </field>\r
3245                 <field>\r
3246                   <name>DSS_UARTLOOPBACK</name>\r
3247                   <bitNumber>0</bitNumber>\r
3248                   <access>R/W</access>\r
3249                   <description>\r
3250                   </description>\r
3251                 </field>\r
3252               </register>\r
3253               <register>\r
3254                 <name>IO_BANK_CONFIG</name>\r
3255                 <addressOffset>0x78</addressOffset>\r
3256                 <absoluteAddress>0x40038078</absoluteAddress>\r
3257                 <size>32</size>\r
3258                 <access>R/W</access>\r
3259                 <resetValue>0x0</resetValue>\r
3260                 <field>\r
3261                   <name>BTWEST</name>\r
3262                   <bitNumber>3:2</bitNumber>\r
3263                   <access>R/W</access>\r
3264                   <description>\r
3265                   </description>\r
3266                 </field>\r
3267                 <field>\r
3268                   <name>BTEAST</name>\r
3269                   <bitNumber>1:0</bitNumber>\r
3270                   <access>R/W</access>\r
3271                   <description>\r
3272                   </description>\r
3273                 </field>\r
3274               </register>\r
3275               <register>\r
3276                 <name>GPIN_SRC_SEL</name>\r
3277                 <addressOffset>0x7C</addressOffset>\r
3278                 <absoluteAddress>0x4003807C</absoluteAddress>\r
3279                 <size>32</size>\r
3280                 <access>R/W</access>\r
3281                 <resetValue>0x0</resetValue>\r
3282                 <field>\r
3283                   <name>DSS_GPINSOURCE[15]</name>\r
3284                   <bitNumber>15</bitNumber>\r
3285                   <access>R/W</access>\r
3286                   <description>\r
3287                   </description>\r
3288                 </field>\r
3289                 <field>\r
3290                   <name>DSS_GPINSOURCE[14]</name>\r
3291                   <bitNumber>14</bitNumber>\r
3292                   <access>R/W</access>\r
3293                   <description>\r
3294                   </description>\r
3295                 </field>\r
3296                 <field>\r
3297                   <name>DSS_GPINSOURCE[13]</name>\r
3298                   <bitNumber>13</bitNumber>\r
3299                   <access>R/W</access>\r
3300                   <description>\r
3301                   </description>\r
3302                 </field>\r
3303                 <field>\r
3304                   <name>DSS_GPINSOURCE[12]</name>\r
3305                   <bitNumber>12</bitNumber>\r
3306                   <access>R/W</access>\r
3307                   <description>\r
3308                   </description>\r
3309                 </field>\r
3310                 <field>\r
3311                   <name>DSS_GPINSOURCE[11]</name>\r
3312                   <bitNumber>11</bitNumber>\r
3313                   <access>R/W</access>\r
3314                   <description>\r
3315                   </description>\r
3316                 </field>\r
3317                 <field>\r
3318                   <name>DSS_GPINSOURCE[10]</name>\r
3319                   <bitNumber>10</bitNumber>\r
3320                   <access>R/W</access>\r
3321                   <description>\r
3322                   </description>\r
3323                 </field>\r
3324                 <field>\r
3325                   <name>DSS_GPINSOURCE[9]</name>\r
3326                   <bitNumber>9</bitNumber>\r
3327                   <access>R/W</access>\r
3328                   <description>\r
3329                   </description>\r
3330                 </field>\r
3331                 <field>\r
3332                   <name>DSS_GPINSOURCE[8]</name>\r
3333                   <bitNumber>8</bitNumber>\r
3334                   <access>R/W</access>\r
3335                   <description>\r
3336                   </description>\r
3337                 </field>\r
3338                 <field>\r
3339                   <name>DSS_GPINSOURCE[7]</name>\r
3340                   <bitNumber>7</bitNumber>\r
3341                   <access>R/W</access>\r
3342                   <description>\r
3343                   </description>\r
3344                 </field>\r
3345                 <field>\r
3346                   <name>DSS_GPINSOURCE[6]</name>\r
3347                   <bitNumber>6</bitNumber>\r
3348                   <access>R/W</access>\r
3349                   <description>\r
3350                   </description>\r
3351                 </field>\r
3352                 <field>\r
3353                   <name>DSS_GPINSOURCE[5]</name>\r
3354                   <bitNumber>5</bitNumber>\r
3355                   <access>R/W</access>\r
3356                   <description>\r
3357                   </description>\r
3358                 </field>\r
3359                 <field>\r
3360                   <name>DSS_GPINSOURCE[4]</name>\r
3361                   <bitNumber>4</bitNumber>\r
3362                   <access>R/W</access>\r
3363                   <description>\r
3364                   </description>\r
3365                 </field>\r
3366                 <field>\r
3367                   <name>DSS_GPINSOURCE[3]</name>\r
3368                   <bitNumber>3</bitNumber>\r
3369                   <access>R/W</access>\r
3370                   <description>\r
3371                   </description>\r
3372                 </field>\r
3373                 <field>\r
3374                   <name>DSS_GPINSOURCE[2]</name>\r
3375                   <bitNumber>2</bitNumber>\r
3376                   <access>R/W</access>\r
3377                   <description>\r
3378                   </description>\r
3379                 </field>\r
3380                 <field>\r
3381                   <name>DSS_GPINSOURCE[1]</name>\r
3382                   <bitNumber>1</bitNumber>\r
3383                   <access>R/W</access>\r
3384                   <description>\r
3385                   </description>\r
3386                 </field>\r
3387                 <field>\r
3388                   <name>DSS_GPINSOURCE[0]</name>\r
3389                   <bitNumber>0</bitNumber>\r
3390                   <access>R/W</access>\r
3391                   <description>\r
3392                   </description>\r
3393                 </field>\r
3394               </register>\r
3395             </addressBlock>\r
3396           </memoryMap>\r
3397         </slave>\r
3398         <slave>\r
3399           <name>CFGM</name>\r
3400           <fullPinName>DEV_KIT_DEMO_MSS_0:MDDR_APB_SLAVE</fullPinName>\r
3401           <remapAddress>0x40020800</remapAddress>\r
3402           <fullAddressSpace>0x40020800 - 0x40020FFF</fullAddressSpace>\r
3403           <range>0x800</range>\r
3404         </slave>\r
3405         <slave>\r
3406           <name>CORESF2CONFIG_0</name>\r
3407           <fullPinName>DEV_KIT_DEMO:SDIF1_APBmslave</fullPinName>\r
3408           <remapAddress>0x4002C000</remapAddress>\r
3409           <fullAddressSpace>0x4002C000 - 0x4002E3FF</fullAddressSpace>\r
3410           <range>0x2400</range>\r
3411         </slave>\r
3412         <slave>\r
3413           <name>RTC</name>\r
3414           <fullPinName>\r
3415           </fullPinName>\r
3416           <remapAddress>0x40017000</remapAddress>\r
3417           <fullAddressSpace>0x40017000 - 0x40017FFF</fullAddressSpace>\r
3418           <range>0x1000</range>\r
3419         </slave>\r
3420         <slave>\r
3421           <name>COMBLK</name>\r
3422           <fullPinName>\r
3423           </fullPinName>\r
3424           <remapAddress>0x40016000</remapAddress>\r
3425           <fullAddressSpace>0x40016000 - 0x40016FFF</fullAddressSpace>\r
3426           <range>0x1000</range>\r
3427         </slave>\r
3428         <slave>\r
3429           <name>HDMA</name>\r
3430           <fullPinName>\r
3431           </fullPinName>\r
3432           <remapAddress>0x40014000</remapAddress>\r
3433           <fullAddressSpace>0x40014000 - 0x40014FFF</fullAddressSpace>\r
3434           <range>0x1000</range>\r
3435         </slave>\r
3436         <slave>\r
3437           <name>GPIO</name>\r
3438           <fullPinName>\r
3439           </fullPinName>\r
3440           <remapAddress>0x40013000</remapAddress>\r
3441           <fullAddressSpace>0x40013000 - 0x40013FFF</fullAddressSpace>\r
3442           <range>0x1000</range>\r
3443         </slave>\r
3444         <slave>\r
3445           <name>I2C_1</name>\r
3446           <fullPinName>\r
3447           </fullPinName>\r
3448           <remapAddress>0x40012000</remapAddress>\r
3449           <fullAddressSpace>0x40012000 - 0x40012FFF</fullAddressSpace>\r
3450           <range>0x1000</range>\r
3451         </slave>\r
3452         <slave>\r
3453           <name>MMUART_1</name>\r
3454           <fullPinName>\r
3455           </fullPinName>\r
3456           <remapAddress>0x40010000</remapAddress>\r
3457           <fullAddressSpace>0x40010000 - 0x40010FFF</fullAddressSpace>\r
3458           <range>0x1000</range>\r
3459         </slave>\r
3460         <slave>\r
3461           <name>H2FINTERRUPT</name>\r
3462           <fullPinName>\r
3463           </fullPinName>\r
3464           <remapAddress>0x40006000</remapAddress>\r
3465           <fullAddressSpace>0x40006000 - 0x40006FFF</fullAddressSpace>\r
3466           <range>0x1000</range>\r
3467         </slave>\r
3468         <slave>\r
3469           <name>WATCHDOG</name>\r
3470           <fullPinName>\r
3471           </fullPinName>\r
3472           <remapAddress>0x40005000</remapAddress>\r
3473           <fullAddressSpace>0x40005000 - 0x40005FFF</fullAddressSpace>\r
3474           <range>0x1000</range>\r
3475         </slave>\r
3476         <slave>\r
3477           <name>TIMER</name>\r
3478           <fullPinName>\r
3479           </fullPinName>\r
3480           <remapAddress>0x40004000</remapAddress>\r
3481           <fullAddressSpace>0x40004000 - 0x40004FFF</fullAddressSpace>\r
3482           <range>0x1000</range>\r
3483         </slave>\r
3484         <slave>\r
3485           <name>PDMA</name>\r
3486           <fullPinName>\r
3487           </fullPinName>\r
3488           <remapAddress>0x40003000</remapAddress>\r
3489           <fullAddressSpace>0x40003000 - 0x40003FFF</fullAddressSpace>\r
3490           <range>0x1000</range>\r
3491         </slave>\r
3492         <slave>\r
3493           <name>I2C_0</name>\r
3494           <fullPinName>\r
3495           </fullPinName>\r
3496           <remapAddress>0x40002000</remapAddress>\r
3497           <fullAddressSpace>0x40002000 - 0x40002FFF</fullAddressSpace>\r
3498           <range>0x1000</range>\r
3499         </slave>\r
3500         <slave>\r
3501           <name>SPI_0</name>\r
3502           <fullPinName>\r
3503           </fullPinName>\r
3504           <remapAddress>0x40001000</remapAddress>\r
3505           <fullAddressSpace>0x40001000 - 0x40001FFF</fullAddressSpace>\r
3506           <range>0x1000</range>\r
3507         </slave>\r
3508         <slave>\r
3509           <name>RECYCLED_ESRAM1</name>\r
3510           <fullPinName>\r
3511           </fullPinName>\r
3512           <remapAddress>0x20012000</remapAddress>\r
3513           <fullAddressSpace>0x20012000 - 0x20013FFF</fullAddressSpace>\r
3514           <range>0x00002000</range>\r
3515         </slave>\r
3516         <slave>\r
3517           <name>RECYCLED_ESRAM0</name>\r
3518           <fullPinName>\r
3519           </fullPinName>\r
3520           <remapAddress>0x20010000</remapAddress>\r
3521           <fullAddressSpace>0x20010000 - 0x20011FFF</fullAddressSpace>\r
3522           <range>0x00002000</range>\r
3523         </slave>\r
3524         <slave>\r
3525           <name>ESRAM1</name>\r
3526           <fullPinName>\r
3527           </fullPinName>\r
3528           <remapAddress>0x20008000</remapAddress>\r
3529           <fullAddressSpace>0x20008000 - 0x2000FFFF</fullAddressSpace>\r
3530           <range>0x00008000</range>\r
3531         </slave>\r
3532         <slave>\r
3533           <name>ESRAM0</name>\r
3534           <fullPinName>\r
3535           </fullPinName>\r
3536           <remapAddress>0x00080000</remapAddress>\r
3537           <fullAddressSpace>0x00080000 - 0x00087FFF</fullAddressSpace>\r
3538           <range>0x00008000</range>\r
3539         </slave>\r
3540       </subsystem>\r
3541       <subsystem>\r
3542         <name>COREABC_0</name>\r
3543         <master>COREABC_0</master>\r
3544         <addressNames>\r
3545           <count>1</count>\r
3546           <name>\r
3547           </name>\r
3548         </addressNames>\r
3549         <slave>\r
3550           <name>FIC32_0</name>\r
3551           <fullPinName>DEV_KIT_DEMO_0:FIC_0_APB_SLAVE</fullPinName>\r
3552           <remapAddress>0x00000000</remapAddress>\r
3553           <fullAddressSpace>0x00000000 - 0x0000FFFF</fullAddressSpace>\r
3554           <range>0x00010000</range>\r
3555         </slave>\r
3556       </subsystem>\r
3557     </subsystems>\r
3558   </memorysystem>\r
3559 </datasheet>\r