git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/LiberoOutput/StarterKit_hardware/RTOSDemo_DataSheet.xml

   1 <?xml version="1.0" encoding="ISO-8859-1" ?>\r
   2 <?xml-stylesheet type="text/xsl" href="datasheet.xsl"?>\r
   3 <datasheet>\r
   4   <header>RTOSDemo</header>\r
   5   <project-settings>\r
   6     <fam>SmartFusion2</fam>\r
   7     <die>M2S050T_ES</die>\r
   8     <package>896 FBGA</package>\r
   9     <speed-grade>STD</speed-grade>\r
  10     <voltage>1.2</voltage>\r
  11     <hdl-type>Verilog</hdl-type>\r
  12     <project-description>\r
  13     </project-description>\r
  14     <location>c:/dev/FreeRTOS/SmartFustion2/Libero/RTOSDemo/component/work/RTOSDemo</location>\r
  15     <state>GENERATED ( Sun May 05 13:23:22 2013 )</state>\r
  16     <swide-toolchain>SoftConsole workspace generated to c:\dev\FreeRTOS\SmartFustion2\Libero\RTOSDemo\SoftConsole</swide-toolchain>\r
  17   </project-settings>\r
  18   <site-map>\r
  19   </site-map>\r
  20   <fileset>\r
  21     <name>HDL File(s)</name>\r
  22     <file>c:\dev\FreeRTOS\SmartFustion2\Libero\RTOSDemo\component\Actel\SgCore\OSC\1.0.100\osc_comps.v</file>\r
  23     <file>c:\dev\FreeRTOS\SmartFustion2\Libero\RTOSDemo\component\work\RTOSDemo\FCCC_0\RTOSDemo_FCCC_0_FCCC.v</file>\r
  24     <file>c:\dev\FreeRTOS\SmartFustion2\Libero\RTOSDemo\component\work\RTOSDemo\OSC_0\RTOSDemo_OSC_0_OSC.v</file>\r
  25     <file>c:\dev\FreeRTOS\SmartFustion2\Libero\RTOSDemo\component\work\RTOSDemo\RTOSDemo.v</file>\r
  26     <file>c:\dev\FreeRTOS\SmartFustion2\Libero\RTOSDemo\component\work\RTOSDemo_MSS\RTOSDemo_MSS.v</file>\r
  27     <file>c:\dev\FreeRTOS\SmartFustion2\Libero\RTOSDemo\component\work\RTOSDemo_MSS\RTOSDemo_MSS_tmp_syn.v</file>\r
  28   </fileset>\r
  29   <io>\r
  30     <port-name>GPIO_0_M2F</port-name>\r
  31     <direction>N/A</direction>\r
  32     <pin-number>-</pin-number>\r
  33   </io>\r
  34   <io>\r
  35     <port-name>GPIO_8_F2M</port-name>\r
  36     <direction>IN</direction>\r
  37     <pin-number>-</pin-number>\r
  38   </io>\r
  39   <io>\r
  40     <port-name>GPIO_1_M2F</port-name>\r
  41     <direction>N/A</direction>\r
  42     <pin-number>-</pin-number>\r
  43   </io>\r
  44   <io>\r
  45     <port-name>MMUART_0_RXD</port-name>\r
  46     <direction>IN</direction>\r
  47     <pin-number>-</pin-number>\r
  48   </io>\r
  49   <io>\r
  50     <port-name>MMUART_0_TXD</port-name>\r
  51     <direction>N/A</direction>\r
  52     <pin-number>-</pin-number>\r
  53   </io>\r
  54   <core type="SpiritModule">\r
  55     <core-exttype>IP</core-exttype>\r
  56     <core-type>SpiritModule</core-type>\r
  57     <core-vendor>Actel</core-vendor>\r
  58     <core-lib>SgCore</core-lib>\r
  59     <core-intname>FCCC</core-intname>\r
  60     <core-ver>2.0.100</core-ver>\r
  61     <core-desc>  "SmartFusion2 Clock Conditioning Circuit (CCC)"  </core-desc>\r
  62     <core-name>FCCC_0</core-name>\r
  63   </core>\r
  64   <core type="SpiritModule">\r
  65     <core-exttype>IP</core-exttype>\r
  66     <core-type>SpiritModule</core-type>\r
  67     <core-vendor>Actel</core-vendor>\r
  68     <core-lib>SgCore</core-lib>\r
  69     <core-intname>OSC</core-intname>\r
  70     <core-ver>1.0.100</core-ver>\r
  71     <core-desc>\r
  72     </core-desc>\r
  73     <core-name>OSC_0</core-name>\r
  74   </core>\r
  75   <core type="ComponentModule">\r
  76     <core-type>ComponentModule</core-type>\r
  77     <core-exttype>HierSpiritDesign</core-exttype>\r
  78     <core-location>c:/dev/FreeRTOS/SmartFustion2/Libero/RTOSDemo/component/work/RTOSDemo_MSS</core-location>\r
  79     <core-name>RTOSDemo_MSS_0</core-name>\r
  80   </core>\r
  81   <firmware_core type="FirmWareModule">\r
  82     <core-exttype>IP</core-exttype>\r
  83     <core-type>FirmWareModule</core-type>\r
  84     <core-vendor>Actel</core-vendor>\r
  85     <core-lib>Firmware</core-lib>\r
  86     <core-intname>SmartFusion2_CMSIS</core-intname>\r
  87     <core-ver>2.1.101</core-ver>\r
  88     <core-desc>SmartFusion2 Cortex Microcontroller Software Interface Standard (CMSIS).\r
  89 \r
  90 The firmware package provides:\r
  91 - Cortex-M3 startup code.\r
  92 - CMSIS standard naming for exception and interrupt handlers.\r
  93 - CMSIS standard functions for controlling the Cortex-M3 Nested Vectored Interrupt Controller (NVIC).\r
  94 - peripherals registers description.\r
  95 - hardware abstraction layer (HAL) for FPGA fabric soft-IP peripherirals.\r
  96 \r
  97 These files are required by the SmartFusion2 bare metal peripheral drivers to build correctly.\r
  98 </core-desc>\r
  99     <core-param>\r
 100       <param-name>Software Tool Chain:</param-name>\r
 101       <param-value>SoftConsole</param-value>\r
 102       <param-hdlname>ToolChain</param-hdlname>\r
 103       <param-hdlvalue>0</param-hdlvalue>\r
 104       <param-tag>actel-cc:variantParameter</param-tag>\r
 105     </core-param>\r
 106     <core-name>SmartFusion2_CMSIS_0</core-name>\r
 107   </firmware_core>\r
 108   <firmware_core type="FirmWareModule">\r
 109     <core-exttype>IP</core-exttype>\r
 110     <core-type>FirmWareModule</core-type>\r
 111     <core-vendor>Actel</core-vendor>\r
 112     <core-lib>Firmware</core-lib>\r
 113     <core-intname>SmartFusion2_MSS_GPIO_Driver</core-intname>\r
 114     <core-ver>2.0.101</core-ver>\r
 115     <core-desc>SmartFusion2 microcontroller subsystem (MSS) GPIO bare metal software driver.\r
 116 \r
 117 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
 118     <core-name>SmartFusion2_MSS_GPIO_Driver_0</core-name>\r
 119   </firmware_core>\r
 120   <firmware_core type="FirmWareModule">\r
 121     <core-exttype>IP</core-exttype>\r
 122     <core-type>FirmWareModule</core-type>\r
 123     <core-vendor>Actel</core-vendor>\r
 124     <core-lib>Firmware</core-lib>\r
 125     <core-intname>SmartFusion2_MSS_HPDMA_Driver</core-intname>\r
 126     <core-ver>2.0.101</core-ver>\r
 127     <core-desc>SmartFusion2 microcontroller subsystem (MSS) High Performance DMA bare metal software driver.\r
 128 \r
 129 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
 130     <core-name>SmartFusion2_MSS_HPDMA_Driver_0</core-name>\r
 131   </firmware_core>\r
 132   <firmware_core type="FirmWareModule">\r
 133     <core-exttype>IP</core-exttype>\r
 134     <core-type>FirmWareModule</core-type>\r
 135     <core-vendor>Actel</core-vendor>\r
 136     <core-lib>Firmware</core-lib>\r
 137     <core-intname>SmartFusion2_MSS_MMUART_Driver</core-intname>\r
 138     <core-ver>2.0.101</core-ver>\r
 139     <core-desc>SmartFusion2 microcontroller subsystem (MSS) MMUART bare metal software driver.\r
 140 \r
 141 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
 142     <core-name>SmartFusion2_MSS_MMUART_Driver_0</core-name>\r
 143   </firmware_core>\r
 144   <firmware_core type="FirmWareModule">\r
 145     <core-exttype>IP</core-exttype>\r
 146     <core-type>FirmWareModule</core-type>\r
 147     <core-vendor>Actel</core-vendor>\r
 148     <core-lib>Firmware</core-lib>\r
 149     <core-intname>SmartFusion2_MSS_NVM_Driver</core-intname>\r
 150     <core-ver>2.0.103</core-ver>\r
 151     <core-desc>SmartFusion2 microcontroller subsystem (MSS) eNVM bare metal software driver.\r
 152 \r
 153 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
 154     <core-name>SmartFusion2_MSS_NVM_Driver_0</core-name>\r
 155   </firmware_core>\r
 156   <firmware_core type="FirmWareModule">\r
 157     <core-exttype>IP</core-exttype>\r
 158     <core-type>FirmWareModule</core-type>\r
 159     <core-vendor>Actel</core-vendor>\r
 160     <core-lib>Firmware</core-lib>\r
 161     <core-intname>SmartFusion2_MSS_RTC_Driver</core-intname>\r
 162     <core-ver>2.0.101</core-ver>\r
 163     <core-desc>SmartFusion2 microcontroller subsystem (MSS) RTC bare metal software driver.\r
 164 \r
 165 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
 166     <core-name>SmartFusion2_MSS_RTC_Driver_0</core-name>\r
 167   </firmware_core>\r
 168   <firmware_core type="FirmWareModule">\r
 169     <core-exttype>IP</core-exttype>\r
 170     <core-type>FirmWareModule</core-type>\r
 171     <core-vendor>Actel</core-vendor>\r
 172     <core-lib>Firmware</core-lib>\r
 173     <core-intname>SmartFusion2_MSS_System_Services_Driver</core-intname>\r
 174     <core-ver>2.0.103</core-ver>\r
 175     <core-desc>SmartFusion2 microsontroller subsystem (MSS) System Services software driver.\r
 176 \r
 177 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
 178     <core-name>SmartFusion2_MSS_System_Services_Driver_0</core-name>\r
 179   </firmware_core>\r
 180   <firmware_core type="FirmWareModule">\r
 181     <core-exttype>IP</core-exttype>\r
 182     <core-type>FirmWareModule</core-type>\r
 183     <core-vendor>Actel</core-vendor>\r
 184     <core-lib>Firmware</core-lib>\r
 185     <core-intname>SmartFusion2_MSS_Timer_Driver</core-intname>\r
 186     <core-ver>2.0.101</core-ver>\r
 187     <core-desc>SmartFusion2 microcontroller subsystem (MSS) Timer bare metal software driver.\r
 188 \r
 189 This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>\r
 190     <core-name>SmartFusion2_MSS_Timer_Driver_0</core-name>\r
 191   </firmware_core>\r
 192   <memorysystem>\r
 193     <title>Memory Map for RTOSDemo</title>\r
 194     <description>The project contains the following subsystems:</description>\r
 195     <subsystems>\r
 196       <subsystem>\r
 197         <name>CM3</name>\r
 198         <master>CM3</master>\r
 199         <addressNames>\r
 200           <count>1</count>\r
 201           <name>\r
 202           </name>\r
 203         </addressNames>\r
 204         <slave>\r
 205           <name>FIC32_REGION5</name>\r
 206           <fullPinName>\r
 207           </fullPinName>\r
 208           <remapAddress>0xF0000000</remapAddress>\r
 209           <fullAddressSpace>0xF0000000 - 0xFFFFFFFF</fullAddressSpace>\r
 210           <range>0x10000000</range>\r
 211         </slave>\r
 212         <slave>\r
 213           <name>DDR_0_SPACE_3</name>\r
 214           <fullPinName>\r
 215           </fullPinName>\r
 216           <remapAddress>0xD0000000</remapAddress>\r
 217           <fullAddressSpace>0xD0000000 - 0xDFFFFFFF</fullAddressSpace>\r
 218           <range>0x10000000</range>\r
 219         </slave>\r
 220         <slave>\r
 221           <name>DDR_0_SPACE_2</name>\r
 222           <fullPinName>\r
 223           </fullPinName>\r
 224           <remapAddress>0xC0000000</remapAddress>\r
 225           <fullAddressSpace>0xC0000000 - 0xCFFFFFFF</fullAddressSpace>\r
 226           <range>0x10000000</range>\r
 227         </slave>\r
 228         <slave>\r
 229           <name>DDR_0_SPACE_1</name>\r
 230           <fullPinName>\r
 231           </fullPinName>\r
 232           <remapAddress>0xB0000000</remapAddress>\r
 233           <fullAddressSpace>0xB0000000 - 0xBFFFFFFF</fullAddressSpace>\r
 234           <range>0x10000000</range>\r
 235         </slave>\r
 236         <slave>\r
 237           <name>DDR_0_SPACE_0</name>\r
 238           <fullPinName>\r
 239           </fullPinName>\r
 240           <remapAddress>0xA0000000</remapAddress>\r
 241           <fullAddressSpace>0xA0000000 - 0xAFFFFFFF</fullAddressSpace>\r
 242           <range>0x10000000</range>\r
 243         </slave>\r
 244         <slave>\r
 245           <name>FIC32_REGION4</name>\r
 246           <fullPinName>\r
 247           </fullPinName>\r
 248           <remapAddress>0x90000000</remapAddress>\r
 249           <fullAddressSpace>0x90000000 - 0x9FFFFFFF</fullAddressSpace>\r
 250           <range>0x10000000</range>\r
 251         </slave>\r
 252         <slave>\r
 253           <name>FIC32_REGION3</name>\r
 254           <fullPinName>\r
 255           </fullPinName>\r
 256           <remapAddress>0x80000000</remapAddress>\r
 257           <fullAddressSpace>0x80000000 - 0x8FFFFFFF</fullAddressSpace>\r
 258           <range>0x10000000</range>\r
 259         </slave>\r
 260         <slave>\r
 261           <name>AHB2ENVM1_REGISTERS</name>\r
 262           <fullPinName>\r
 263           </fullPinName>\r
 264           <remapAddress>0x600C0000</remapAddress>\r
 265           <fullAddressSpace>0x600C0000 - 0x600FFFFF</fullAddressSpace>\r
 266           <range>0x00040000</range>\r
 267         </slave>\r
 268         <slave>\r
 269           <name>AHB2ENVM0_REGISTERS</name>\r
 270           <fullPinName>\r
 271           </fullPinName>\r
 272           <remapAddress>0x60080000</remapAddress>\r
 273           <fullAddressSpace>0x60080000 - 0x600BFFFF</fullAddressSpace>\r
 274           <range>0x00040000</range>\r
 275         </slave>\r
 276         <slave>\r
 277           <name>ENVM1</name>\r
 278           <fullPinName>\r
 279           </fullPinName>\r
 280           <remapAddress>0x60040000</remapAddress>\r
 281           <fullAddressSpace>0x60040000 - 0x6007FFFF</fullAddressSpace>\r
 282           <range>0x00040000</range>\r
 283         </slave>\r
 284         <slave>\r
 285           <name>ENVM0</name>\r
 286           <fullPinName>\r
 287           </fullPinName>\r
 288           <remapAddress>0x60000000</remapAddress>\r
 289           <fullAddressSpace>0x60000000 - 0x6003FFFF</fullAddressSpace>\r
 290           <range>0x00040000</range>\r
 291         </slave>\r
 292         <slave>\r
 293           <name>FIC32_REGION1</name>\r
 294           <fullPinName>\r
 295           </fullPinName>\r
 296           <remapAddress>0x50000000</remapAddress>\r
 297           <fullAddressSpace>0x50000000 - 0x5FFFFFFF</fullAddressSpace>\r
 298           <range>0x10000000</range>\r
 299         </slave>\r
 300         <slave>\r
 301           <name>CACHE_BACKDOOR</name>\r
 302           <fullPinName>\r
 303           </fullPinName>\r
 304           <remapAddress>0x40400000</remapAddress>\r
 305           <fullAddressSpace>0x40400000 - 0x4040FFFF</fullAddressSpace>\r
 306           <range>0x00010000</range>\r
 307         </slave>\r
 308         <slave>\r
 309           <name>SYSREG</name>\r
 310           <fullPinName>\r
 311           </fullPinName>\r
 312           <remapAddress>0x40038000</remapAddress>\r
 313           <fullAddressSpace>0x40038000 - 0x40038FFF</fullAddressSpace>\r
 314           <range>0x00001000</range>\r
 315           <memoryMap>\r
 316             <name>RegisterMap</name>\r
 317             <addressBlock>\r
 318               <baseAddress>0x0</baseAddress>\r
 319               <range format="long">0x1000</range>\r
 320               <width format="long" id="width">32</width>\r
 321               <register>\r
 322                 <name>ESRAM_CONFIG</name>\r
 323                 <addressOffset>0x0</addressOffset>\r
 324                 <absoluteAddress>0x40038000</absoluteAddress>\r
 325                 <size>32</size>\r
 326                 <access>R/W</access>\r
 327                 <resetValue>0x0</resetValue>\r
 328                 <field>\r
 329                   <name>F2_ESRAMSIZE</name>\r
 330                   <bitNumber>4:3</bitNumber>\r
 331                   <access>R/W</access>\r
 332                   <description>\r
 333                   </description>\r
 334                 </field>\r
 335                 <field>\r
 336                   <name>F2_TESTESRAM1REMAP_SYNC</name>\r
 337                   <bitNumber>2</bitNumber>\r
 338                   <access>R/W</access>\r
 339                   <description>\r
 340                   </description>\r
 341                 </field>\r
 342                 <field>\r
 343                   <name>F2_TESTREMAPENABLE_SYNC</name>\r
 344                   <bitNumber>1</bitNumber>\r
 345                   <access>R/W</access>\r
 346                   <description>\r
 347                   </description>\r
 348                 </field>\r
 349                 <field>\r
 350                   <name>COM_ESRAMFWREMAP</name>\r
 351                   <bitNumber>0</bitNumber>\r
 352                   <access>R/W</access>\r
 353                   <description>\r
 354                   </description>\r
 355                 </field>\r
 356               </register>\r
 357               <register>\r
 358                 <name>ENVM_CONFIG</name>\r
 359                 <addressOffset>0x4</addressOffset>\r
 360                 <absoluteAddress>0x40038004</absoluteAddress>\r
 361                 <size>32</size>\r
 362                 <access>R/W</access>\r
 363                 <resetValue>0x0</resetValue>\r
 364                 <field>\r
 365                   <name>ENVM_SIX_CYCLE</name>\r
 366                   <bitNumber>7</bitNumber>\r
 367                   <access>R/W</access>\r
 368                   <description>\r
 369                   </description>\r
 370                 </field>\r
 371                 <field>\r
 372                   <name>ENVM_PIPE_BYPASS</name>\r
 373                   <bitNumber>6</bitNumber>\r
 374                   <access>R/W</access>\r
 375                   <description>\r
 376                   </description>\r
 377                 </field>\r
 378                 <field>\r
 379                   <name>F2_ENVMPOWEREDDOWN</name>\r
 380                   <bitNumber>5</bitNumber>\r
 381                   <access>R/W</access>\r
 382                   <description>\r
 383                   </description>\r
 384                 </field>\r
 385                 <field>\r
 386                   <name>COM_ENVMREMAPSIZE</name>\r
 387                   <bitNumber>4:0</bitNumber>\r
 388                   <access>R/W</access>\r
 389                   <description>\r
 390                   </description>\r
 391                 </field>\r
 392               </register>\r
 393               <register>\r
 394                 <name>ENVM_REMAP_BASE</name>\r
 395                 <addressOffset>0x8</addressOffset>\r
 396                 <absoluteAddress>0x40038008</absoluteAddress>\r
 397                 <size>32</size>\r
 398                 <access>R/W</access>\r
 399                 <resetValue>0x0</resetValue>\r
 400                 <field>\r
 401                   <name>COM_ENVMREMAPBASE</name>\r
 402                   <bitNumber>19:0</bitNumber>\r
 403                   <access>R/W</access>\r
 404                   <description>\r
 405                   </description>\r
 406                 </field>\r
 407               </register>\r
 408               <register>\r
 409                 <name>ENVM_FAB_REMAP</name>\r
 410                 <addressOffset>0xC</addressOffset>\r
 411                 <absoluteAddress>0x4003800C</absoluteAddress>\r
 412                 <size>32</size>\r
 413                 <access>R/W</access>\r
 414                 <resetValue>0x0</resetValue>\r
 415                 <field>\r
 416                   <name>COM_ENVMFABREMAPBASE</name>\r
 417                   <bitNumber>19:0</bitNumber>\r
 418                   <access>R/W</access>\r
 419                   <description>\r
 420                   </description>\r
 421                 </field>\r
 422               </register>\r
 423               <register>\r
 424                 <name>FAB_PROT_SIZE</name>\r
 425                 <addressOffset>0x10</addressOffset>\r
 426                 <absoluteAddress>0x40038010</absoluteAddress>\r
 427                 <size>32</size>\r
 428                 <access>R/W</access>\r
 429                 <resetValue>0x0</resetValue>\r
 430                 <field>\r
 431                   <name>COM_PROTREGIONSIZE</name>\r
 432                   <bitNumber>4:0</bitNumber>\r
 433                   <access>R/W</access>\r
 434                   <description>\r
 435                   </description>\r
 436                 </field>\r
 437               </register>\r
 438               <register>\r
 439                 <name>FAB_PROT_BASE</name>\r
 440                 <addressOffset>0x14</addressOffset>\r
 441                 <absoluteAddress>0x40038014</absoluteAddress>\r
 442                 <size>32</size>\r
 443                 <access>R/W</access>\r
 444                 <resetValue>0x0</resetValue>\r
 445                 <field>\r
 446                   <name>COM_PROTREGIONBASE</name>\r
 447                   <bitNumber>31:0</bitNumber>\r
 448                   <access>R/W</access>\r
 449                   <description>\r
 450                   </description>\r
 451                 </field>\r
 452               </register>\r
 453               <register>\r
 454                 <name>MATRIX_CONFIG</name>\r
 455                 <addressOffset>0x18</addressOffset>\r
 456                 <absoluteAddress>0x40038018</absoluteAddress>\r
 457                 <size>32</size>\r
 458                 <access>R/W</access>\r
 459                 <resetValue>0x0</resetValue>\r
 460                 <field>\r
 461                   <name>COM_WEIGHTEDMODE</name>\r
 462                   <bitNumber>3</bitNumber>\r
 463                   <access>R/W</access>\r
 464                   <description>\r
 465                   </description>\r
 466                 </field>\r
 467                 <field>\r
 468                   <name>COM_MASTERENABLE</name>\r
 469                   <bitNumber>2:0</bitNumber>\r
 470                   <access>R/W</access>\r
 471                   <description>\r
 472                   </description>\r
 473                 </field>\r
 474               </register>\r
 475               <register>\r
 476                 <name>DSS_STATUS</name>\r
 477                 <addressOffset>0x1C</addressOffset>\r
 478                 <absoluteAddress>0x4003801C</absoluteAddress>\r
 479                 <size>32</size>\r
 480                 <access>R/W</access>\r
 481                 <resetValue>0x0</resetValue>\r
 482                 <field>\r
 483                   <name>PLLLOCKLOSTINT</name>\r
 484                   <bitNumber>10</bitNumber>\r
 485                   <access>R/W</access>\r
 486                   <description>\r
 487                   </description>\r
 488                 </field>\r
 489                 <field>\r
 490                   <name>PLLLOCKINT</name>\r
 491                   <bitNumber>9</bitNumber>\r
 492                   <access>R/W</access>\r
 493                   <description>\r
 494                   </description>\r
 495                 </field>\r
 496                 <field>\r
 497                   <name>COM_ERRORSTATUS</name>\r
 498                   <bitNumber>8:4</bitNumber>\r
 499                   <access>R/W</access>\r
 500                   <description>\r
 501                   </description>\r
 502                 </field>\r
 503                 <field>\r
 504                   <name>BROWNOUT3_3VINT</name>\r
 505                   <bitNumber>3</bitNumber>\r
 506                   <access>R/W</access>\r
 507                   <description>\r
 508                   </description>\r
 509                 </field>\r
 510                 <field>\r
 511                   <name>BROWNOUT1_5VINT</name>\r
 512                   <bitNumber>2</bitNumber>\r
 513                   <access>R/W</access>\r
 514                   <description>\r
 515                   </description>\r
 516                 </field>\r
 517                 <field>\r
 518                   <name>WDOGTIMEOUTEVENT</name>\r
 519                   <bitNumber>1</bitNumber>\r
 520                   <access>R/W</access>\r
 521                   <description>\r
 522                   </description>\r
 523                 </field>\r
 524                 <field>\r
 525                   <name>RTCMATCHEVENT</name>\r
 526                   <bitNumber>0</bitNumber>\r
 527                   <access>R/W</access>\r
 528                   <description>\r
 529                   </description>\r
 530                 </field>\r
 531               </register>\r
 532               <register>\r
 533                 <name>CLR_DSS_STATUS</name>\r
 534                 <addressOffset>0x20</addressOffset>\r
 535                 <absoluteAddress>0x40038020</absoluteAddress>\r
 536                 <size>32</size>\r
 537                 <access>R/W</access>\r
 538                 <resetValue>0x0</resetValue>\r
 539                 <field>\r
 540                   <name>CLRPLLLOCKLOSTINT</name>\r
 541                   <bitNumber>10</bitNumber>\r
 542                   <access>R/W</access>\r
 543                   <description>\r
 544                   </description>\r
 545                 </field>\r
 546                 <field>\r
 547                   <name>CLRPLLLOCKINT</name>\r
 548                   <bitNumber>9</bitNumber>\r
 549                   <access>R/W</access>\r
 550                   <description>\r
 551                   </description>\r
 552                 </field>\r
 553                 <field>\r
 554                   <name>COM_CLEARSTATUS</name>\r
 555                   <bitNumber>8:4</bitNumber>\r
 556                   <access>R/W</access>\r
 557                   <description>\r
 558                   </description>\r
 559                 </field>\r
 560                 <field>\r
 561                   <name>CLRBROWNOUT3_3VINT</name>\r
 562                   <bitNumber>3</bitNumber>\r
 563                   <access>R/W</access>\r
 564                   <description>\r
 565                   </description>\r
 566                 </field>\r
 567                 <field>\r
 568                   <name>CLRBROWNOUT1_5VINT</name>\r
 569                   <bitNumber>2</bitNumber>\r
 570                   <access>R/W</access>\r
 571                   <description>\r
 572                   </description>\r
 573                 </field>\r
 574                 <field>\r
 575                   <name>CLRWDOGTIMEOUTEVENT</name>\r
 576                   <bitNumber>1</bitNumber>\r
 577                   <access>R/W</access>\r
 578                   <description>\r
 579                   </description>\r
 580                 </field>\r
 581                 <field>\r
 582                   <name>CLRRTCMATCHEVENT</name>\r
 583                   <bitNumber>0</bitNumber>\r
 584                   <access>R/W</access>\r
 585                   <description>\r
 586                   </description>\r
 587                 </field>\r
 588               </register>\r
 589               <register>\r
 590                 <name>FROM_CONFIG</name>\r
 591                 <addressOffset>0x24</addressOffset>\r
 592                 <absoluteAddress>0x40038024</absoluteAddress>\r
 593                 <size>32</size>\r
 594                 <access>R/W</access>\r
 595                 <resetValue>0x0</resetValue>\r
 596                 <field>\r
 597                   <name>SYS_TOPT</name>\r
 598                   <bitNumber>3:0</bitNumber>\r
 599                   <access>R/W</access>\r
 600                   <description>\r
 601                   </description>\r
 602                 </field>\r
 603               </register>\r
 604               <register>\r
 605                 <name>IAP_CONFIG</name>\r
 606                 <addressOffset>0x28</addressOffset>\r
 607                 <absoluteAddress>0x40038028</absoluteAddress>\r
 608                 <size>32</size>\r
 609                 <access>R/W</access>\r
 610                 <resetValue>0x0</resetValue>\r
 611                 <field>\r
 612                   <name>SYS_FCFG</name>\r
 613                   <bitNumber>2:0</bitNumber>\r
 614                   <access>R/W</access>\r
 615                   <description>\r
 616                   </description>\r
 617                 </field>\r
 618               </register>\r
 619               <register>\r
 620                 <name>SOFT_INTERRUPT</name>\r
 621                 <addressOffset>0x2C</addressOffset>\r
 622                 <absoluteAddress>0x4003802C</absoluteAddress>\r
 623                 <size>32</size>\r
 624                 <access>R/W</access>\r
 625                 <resetValue>0x0</resetValue>\r
 626                 <field>\r
 627                   <name>SOFTINTERRUPT</name>\r
 628                   <bitNumber>0</bitNumber>\r
 629                   <access>R/W</access>\r
 630                   <description>\r
 631                   </description>\r
 632                 </field>\r
 633               </register>\r
 634               <register>\r
 635                 <name>SOFT_RESET</name>\r
 636                 <addressOffset>0x30</addressOffset>\r
 637                 <absoluteAddress>0x40038030</absoluteAddress>\r
 638                 <size>32</size>\r
 639                 <access>R/W</access>\r
 640                 <resetValue>0x0</resetValue>\r
 641                 <field>\r
 642                   <name>PADRESETENABLE</name>\r
 643                   <bitNumber>19</bitNumber>\r
 644                   <access>R/W</access>\r
 645                   <description>\r
 646                   </description>\r
 647                 </field>\r
 648                 <field>\r
 649                   <name>USERRESETACTIVE</name>\r
 650                   <bitNumber>18</bitNumber>\r
 651                   <access>R/W</access>\r
 652                   <description>\r
 653                   </description>\r
 654                 </field>\r
 655                 <field>\r
 656                   <name>FPGA_SOFTRESET</name>\r
 657                   <bitNumber>17</bitNumber>\r
 658                   <access>R/W</access>\r
 659                   <description>\r
 660                   </description>\r
 661                 </field>\r
 662                 <field>\r
 663                   <name>EXT_SOFTRESET</name>\r
 664                   <bitNumber>16</bitNumber>\r
 665                   <access>R/W</access>\r
 666                   <description>\r
 667                   </description>\r
 668                 </field>\r
 669                 <field>\r
 670                   <name>IAP_SOFTRESET</name>\r
 671                   <bitNumber>15</bitNumber>\r
 672                   <access>R/W</access>\r
 673                   <description>\r
 674                   </description>\r
 675                 </field>\r
 676                 <field>\r
 677                   <name>GPIO_SOFTRESET</name>\r
 678                   <bitNumber>14</bitNumber>\r
 679                   <access>R/W</access>\r
 680                   <description>\r
 681                   </description>\r
 682                 </field>\r
 683                 <field>\r
 684                   <name>ACE_SOFTRESET</name>\r
 685                   <bitNumber>13</bitNumber>\r
 686                   <access>R/W</access>\r
 687                   <description>\r
 688                   </description>\r
 689                 </field>\r
 690                 <field>\r
 691                   <name>I2C1_SOFTRESET</name>\r
 692                   <bitNumber>12</bitNumber>\r
 693                   <access>R/W</access>\r
 694                   <description>\r
 695                   </description>\r
 696                 </field>\r
 697                 <field>\r
 698                   <name>I2C0_SOFTRESET</name>\r
 699                   <bitNumber>11</bitNumber>\r
 700                   <access>R/W</access>\r
 701                   <description>\r
 702                   </description>\r
 703                 </field>\r
 704                 <field>\r
 705                   <name>SPI1_SOFTRESET</name>\r
 706                   <bitNumber>10</bitNumber>\r
 707                   <access>R/W</access>\r
 708                   <description>\r
 709                   </description>\r
 710                 </field>\r
 711                 <field>\r
 712                   <name>SPI0_SOFTRESET</name>\r
 713                   <bitNumber>9</bitNumber>\r
 714                   <access>R/W</access>\r
 715                   <description>\r
 716                   </description>\r
 717                 </field>\r
 718                 <field>\r
 719                   <name>UART1_SOFTRESET</name>\r
 720                   <bitNumber>8</bitNumber>\r
 721                   <access>R/W</access>\r
 722                   <description>\r
 723                   </description>\r
 724                 </field>\r
 725                 <field>\r
 726                   <name>UART0_SOFTRESET</name>\r
 727                   <bitNumber>7</bitNumber>\r
 728                   <access>R/W</access>\r
 729                   <description>\r
 730                   </description>\r
 731                 </field>\r
 732                 <field>\r
 733                   <name>TIMER_SOFTRESET</name>\r
 734                   <bitNumber>6</bitNumber>\r
 735                   <access>R/W</access>\r
 736                   <description>\r
 737                   </description>\r
 738                 </field>\r
 739                 <field>\r
 740                   <name>PDMA_SOFTRESET</name>\r
 741                   <bitNumber>5</bitNumber>\r
 742                   <access>R/W</access>\r
 743                   <description>\r
 744                   </description>\r
 745                 </field>\r
 746                 <field>\r
 747                   <name>MAC_SOFTRESET</name>\r
 748                   <bitNumber>4</bitNumber>\r
 749                   <access>R/W</access>\r
 750                   <description>\r
 751                   </description>\r
 752                 </field>\r
 753                 <field>\r
 754                   <name>EMC_SOFTRESET</name>\r
 755                   <bitNumber>3</bitNumber>\r
 756                   <access>R/W</access>\r
 757                   <description>\r
 758                   </description>\r
 759                 </field>\r
 760                 <field>\r
 761                   <name>ESRAM1_SOFTRESET</name>\r
 762                   <bitNumber>2</bitNumber>\r
 763                   <access>R/W</access>\r
 764                   <description>\r
 765                   </description>\r
 766                 </field>\r
 767                 <field>\r
 768                   <name>ESRAM0_SOFTRESET</name>\r
 769                   <bitNumber>1</bitNumber>\r
 770                   <access>R/W</access>\r
 771                   <description>\r
 772                   </description>\r
 773                 </field>\r
 774                 <field>\r
 775                   <name>ENVM_SOFTRESET</name>\r
 776                   <bitNumber>0</bitNumber>\r
 777                   <access>R/W</access>\r
 778                   <description>\r
 779                   </description>\r
 780                 </field>\r
 781               </register>\r
 782               <register>\r
 783                 <name>DEVICE_STATUS</name>\r
 784                 <addressOffset>0x34</addressOffset>\r
 785                 <absoluteAddress>0x40038034</absoluteAddress>\r
 786                 <size>32</size>\r
 787                 <access>R/W</access>\r
 788                 <resetValue>0x0</resetValue>\r
 789                 <field>\r
 790                   <name>FPGAGOOD_SYNC</name>\r
 791                   <bitNumber>6</bitNumber>\r
 792                   <access>R/W</access>\r
 793                   <description>\r
 794                   </description>\r
 795                 </field>\r
 796                 <field>\r
 797                   <name>FPGAPROGRAMMING_SYNC</name>\r
 798                   <bitNumber>5</bitNumber>\r
 799                   <access>R/W</access>\r
 800                   <description>\r
 801                   </description>\r
 802                 </field>\r
 803                 <field>\r
 804                   <name>F2_PC_ACCESS_SYNC</name>\r
 805                   <bitNumber>4:3</bitNumber>\r
 806                   <access>R/W</access>\r
 807                   <description>\r
 808                   </description>\r
 809                 </field>\r
 810                 <field>\r
 811                   <name>VCCIBGOOD_SYNC</name>\r
 812                   <bitNumber>2</bitNumber>\r
 813                   <access>R/W</access>\r
 814                   <description>\r
 815                   </description>\r
 816                 </field>\r
 817                 <field>\r
 818                   <name>BROWNOUT3_3V_SYNCN</name>\r
 819                   <bitNumber>1</bitNumber>\r
 820                   <access>R/W</access>\r
 821                   <description>\r
 822                   </description>\r
 823                 </field>\r
 824                 <field>\r
 825                   <name>BROWNOUT1_5V_SYNCN</name>\r
 826                   <bitNumber>0</bitNumber>\r
 827                   <access>R/W</access>\r
 828                   <description>\r
 829                   </description>\r
 830                 </field>\r
 831               </register>\r
 832               <register>\r
 833                 <name>SYSTICK_CONFIG</name>\r
 834                 <addressOffset>0x38</addressOffset>\r
 835                 <absoluteAddress>0x40038038</absoluteAddress>\r
 836                 <size>32</size>\r
 837                 <access>R/W</access>\r
 838                 <resetValue>0x0</resetValue>\r
 839                 <field>\r
 840                   <name>STCLK_DIVISOR</name>\r
 841                   <bitNumber>29:28</bitNumber>\r
 842                   <access>R/W</access>\r
 843                   <description>\r
 844                   </description>\r
 845                 </field>\r
 846                 <field>\r
 847                   <name>STCALIB</name>\r
 848                   <bitNumber>25:0</bitNumber>\r
 849                   <access>R/W</access>\r
 850                   <description>\r
 851                   </description>\r
 852                 </field>\r
 853               </register>\r
 854               <register>\r
 855                 <name>EM_MUX_CONFIG</name>\r
 856                 <addressOffset>0x3C</addressOffset>\r
 857                 <absoluteAddress>0x4003803C</absoluteAddress>\r
 858                 <size>32</size>\r
 859                 <access>R/W</access>\r
 860                 <resetValue>0x0</resetValue>\r
 861                 <field>\r
 862                   <name>EM_SEL</name>\r
 863                   <bitNumber>0</bitNumber>\r
 864                   <access>R/W</access>\r
 865                   <description>\r
 866                   </description>\r
 867                 </field>\r
 868               </register>\r
 869               <register>\r
 870                 <name>EM_CONFIG_0</name>\r
 871                 <addressOffset>0x40</addressOffset>\r
 872                 <absoluteAddress>0x40038040</absoluteAddress>\r
 873                 <size>32</size>\r
 874                 <access>R/W</access>\r
 875                 <resetValue>0x0</resetValue>\r
 876                 <field>\r
 877                   <name>EM_CSFE0</name>\r
 878                   <bitNumber>21</bitNumber>\r
 879                   <access>R/W</access>\r
 880                   <description>\r
 881                   </description>\r
 882                 </field>\r
 883                 <field>\r
 884                   <name>EM_WENBEN0</name>\r
 885                   <bitNumber>20</bitNumber>\r
 886                   <access>R/W</access>\r
 887                   <description>\r
 888                   </description>\r
 889                 </field>\r
 890                 <field>\r
 891                   <name>EM_RWPOL0</name>\r
 892                   <bitNumber>19</bitNumber>\r
 893                   <access>R/W</access>\r
 894                   <description>\r
 895                   </description>\r
 896                 </field>\r
 897                 <field>\r
 898                   <name>EM_PIPEWRN0</name>\r
 899                   <bitNumber>18</bitNumber>\r
 900                   <access>R/W</access>\r
 901                   <description>\r
 902                   </description>\r
 903                 </field>\r
 904                 <field>\r
 905                   <name>EM_PIPERDN0</name>\r
 906                   <bitNumber>17</bitNumber>\r
 907                   <access>R/W</access>\r
 908                   <description>\r
 909                   </description>\r
 910                 </field>\r
 911                 <field>\r
 912                   <name>EM_IDD0</name>\r
 913                   <bitNumber>16:15</bitNumber>\r
 914                   <access>R/W</access>\r
 915                   <description>\r
 916                   </description>\r
 917                 </field>\r
 918                 <field>\r
 919                   <name>EM_WRITELAT0</name>\r
 920                   <bitNumber>14:11</bitNumber>\r
 921                   <access>R/W</access>\r
 922                   <description>\r
 923                   </description>\r
 924                 </field>\r
 925                 <field>\r
 926                   <name>EM_RDLATREST0</name>\r
 927                   <bitNumber>10:7</bitNumber>\r
 928                   <access>R/W</access>\r
 929                   <description>\r
 930                   </description>\r
 931                 </field>\r
 932                 <field>\r
 933                   <name>EM_RDLATFIRST0</name>\r
 934                   <bitNumber>6:3</bitNumber>\r
 935                   <access>R/W</access>\r
 936                   <description>\r
 937                   </description>\r
 938                 </field>\r
 939                 <field>\r
 940                   <name>EM_PORTSIZE0</name>\r
 941                   <bitNumber>2</bitNumber>\r
 942                   <access>R/W</access>\r
 943                   <description>\r
 944                   </description>\r
 945                 </field>\r
 946                 <field>\r
 947                   <name>EM_MEMTYPE0</name>\r
 948                   <bitNumber>1:0</bitNumber>\r
 949                   <access>R/W</access>\r
 950                   <description>\r
 951                   </description>\r
 952                 </field>\r
 953               </register>\r
 954               <register>\r
 955                 <name>EM_CONFIG_1</name>\r
 956                 <addressOffset>0x44</addressOffset>\r
 957                 <absoluteAddress>0x40038044</absoluteAddress>\r
 958                 <size>32</size>\r
 959                 <access>R/W</access>\r
 960                 <resetValue>0x0</resetValue>\r
 961                 <field>\r
 962                   <name>EM_CSFE1</name>\r
 963                   <bitNumber>21</bitNumber>\r
 964                   <access>R/W</access>\r
 965                   <description>\r
 966                   </description>\r
 967                 </field>\r
 968                 <field>\r
 969                   <name>EM_WENBEN1</name>\r
 970                   <bitNumber>20</bitNumber>\r
 971                   <access>R/W</access>\r
 972                   <description>\r
 973                   </description>\r
 974                 </field>\r
 975                 <field>\r
 976                   <name>EM_RWPOL1</name>\r
 977                   <bitNumber>19</bitNumber>\r
 978                   <access>R/W</access>\r
 979                   <description>\r
 980                   </description>\r
 981                 </field>\r
 982                 <field>\r
 983                   <name>EM_PIPEWRN1</name>\r
 984                   <bitNumber>18</bitNumber>\r
 985                   <access>R/W</access>\r
 986                   <description>\r
 987                   </description>\r
 988                 </field>\r
 989                 <field>\r
 990                   <name>EM_PIPERDN1</name>\r
 991                   <bitNumber>17</bitNumber>\r
 992                   <access>R/W</access>\r
 993                   <description>\r
 994                   </description>\r
 995                 </field>\r
 996                 <field>\r
 997                   <name>EM_IDD1</name>\r
 998                   <bitNumber>16:15</bitNumber>\r
 999                   <access>R/W</access>\r
1000                   <description>\r
1001                   </description>\r
1002                 </field>\r
1003                 <field>\r
1004                   <name>EM_WRITELAT1</name>\r
1005                   <bitNumber>14:11</bitNumber>\r
1006                   <access>R/W</access>\r
1007                   <description>\r
1008                   </description>\r
1009                 </field>\r
1010                 <field>\r
1011                   <name>EM_RDLATREST1</name>\r
1012                   <bitNumber>10:7</bitNumber>\r
1013                   <access>R/W</access>\r
1014                   <description>\r
1015                   </description>\r
1016                 </field>\r
1017                 <field>\r
1018                   <name>EM_RDLATFIRST1</name>\r
1019                   <bitNumber>6:3</bitNumber>\r
1020                   <access>R/W</access>\r
1021                   <description>\r
1022                   </description>\r
1023                 </field>\r
1024                 <field>\r
1025                   <name>EM_PORTSIZE1</name>\r
1026                   <bitNumber>2</bitNumber>\r
1027                   <access>R/W</access>\r
1028                   <description>\r
1029                   </description>\r
1030                 </field>\r
1031                 <field>\r
1032                   <name>EM_MEMTYPE1</name>\r
1033                   <bitNumber>1:0</bitNumber>\r
1034                   <access>R/W</access>\r
1035                   <description>\r
1036                   </description>\r
1037                 </field>\r
1038               </register>\r
1039               <register>\r
1040                 <name>CLK_CTRL</name>\r
1041                 <addressOffset>0x48</addressOffset>\r
1042                 <absoluteAddress>0x40038048</absoluteAddress>\r
1043                 <size>32</size>\r
1044                 <access>R/W</access>\r
1045                 <resetValue>0x0</resetValue>\r
1046                 <field>\r
1047                   <name>GLBDIVISOR</name>\r
1048                   <bitNumber>13:12</bitNumber>\r
1049                   <access>R/W</access>\r
1050                   <description>\r
1051                   </description>\r
1052                 </field>\r
1053                 <field>\r
1054                   <name>RTCIF_ACMDIVISOR</name>\r
1055                   <bitNumber>11:8</bitNumber>\r
1056                   <access>R/W</access>\r
1057                   <description>\r
1058                   </description>\r
1059                 </field>\r
1060                 <field>\r
1061                   <name>ACLKDIVISOR</name>\r
1062                   <bitNumber>7:6</bitNumber>\r
1063                   <access>R/W</access>\r
1064                   <description>\r
1065                   </description>\r
1066                 </field>\r
1067                 <field>\r
1068                   <name>PCLK1DIVISOR</name>\r
1069                   <bitNumber>5:4</bitNumber>\r
1070                   <access>R/W</access>\r
1071                   <description>\r
1072                   </description>\r
1073                 </field>\r
1074                 <field>\r
1075                   <name>PCLK0DIVISOR</name>\r
1076                   <bitNumber>3:2</bitNumber>\r
1077                   <access>R/W</access>\r
1078                   <description>\r
1079                   </description>\r
1080                 </field>\r
1081                 <field>\r
1082                   <name>RMIICLKSEL</name>\r
1083                   <bitNumber>1</bitNumber>\r
1084                   <access>R/W</access>\r
1085                   <description>\r
1086                   </description>\r
1087                 </field>\r
1088               </register>\r
1089               <register>\r
1090                 <name>CCC_DIV_CONFIG</name>\r
1091                 <addressOffset>0x4C</addressOffset>\r
1092                 <absoluteAddress>0x4003804C</absoluteAddress>\r
1093                 <size>32</size>\r
1094                 <access>R/W</access>\r
1095                 <resetValue>0x0</resetValue>\r
1096                 <field>\r
1097                   <name>OCDIVRST</name>\r
1098                   <bitNumber>22</bitNumber>\r
1099                   <access>R/W</access>\r
1100                   <description>\r
1101                   </description>\r
1102                 </field>\r
1103                 <field>\r
1104                   <name>OCDIVHALF</name>\r
1105                   <bitNumber>21</bitNumber>\r
1106                   <access>R/W</access>\r
1107                   <description>\r
1108                   </description>\r
1109                 </field>\r
1110                 <field>\r
1111                   <name>OCDIV4</name>\r
1112                   <bitNumber>20</bitNumber>\r
1113                   <access>R/W</access>\r
1114                   <description>\r
1115                   </description>\r
1116                 </field>\r
1117                 <field>\r
1118                   <name>OCDIV3</name>\r
1119                   <bitNumber>19</bitNumber>\r
1120                   <access>R/W</access>\r
1121                   <description>\r
1122                   </description>\r
1123                 </field>\r
1124                 <field>\r
1125                   <name>OCDIV2</name>\r
1126                   <bitNumber>18</bitNumber>\r
1127                   <access>R/W</access>\r
1128                   <description>\r
1129                   </description>\r
1130                 </field>\r
1131                 <field>\r
1132                   <name>OCDIV1</name>\r
1133                   <bitNumber>17</bitNumber>\r
1134                   <access>R/W</access>\r
1135                   <description>\r
1136                   </description>\r
1137                 </field>\r
1138                 <field>\r
1139                   <name>OCDIV0</name>\r
1140                   <bitNumber>16</bitNumber>\r
1141                   <access>R/W</access>\r
1142                   <description>\r
1143                   </description>\r
1144                 </field>\r
1145                 <field>\r
1146                   <name>OBDIVRST</name>\r
1147                   <bitNumber>14</bitNumber>\r
1148                   <access>R/W</access>\r
1149                   <description>\r
1150                   </description>\r
1151                 </field>\r
1152                 <field>\r
1153                   <name>OBDIVHALF</name>\r
1154                   <bitNumber>13</bitNumber>\r
1155                   <access>R/W</access>\r
1156                   <description>\r
1157                   </description>\r
1158                 </field>\r
1159                 <field>\r
1160                   <name>OBDIV4</name>\r
1161                   <bitNumber>12</bitNumber>\r
1162                   <access>R/W</access>\r
1163                   <description>\r
1164                   </description>\r
1165                 </field>\r
1166                 <field>\r
1167                   <name>OBDIV3</name>\r
1168                   <bitNumber>11</bitNumber>\r
1169                   <access>R/W</access>\r
1170                   <description>\r
1171                   </description>\r
1172                 </field>\r
1173                 <field>\r
1174                   <name>OBDIV2</name>\r
1175                   <bitNumber>10</bitNumber>\r
1176                   <access>R/W</access>\r
1177                   <description>\r
1178                   </description>\r
1179                 </field>\r
1180                 <field>\r
1181                   <name>OBDIV1</name>\r
1182                   <bitNumber>9</bitNumber>\r
1183                   <access>R/W</access>\r
1184                   <description>\r
1185                   </description>\r
1186                 </field>\r
1187                 <field>\r
1188                   <name>OBDIV0</name>\r
1189                   <bitNumber>8</bitNumber>\r
1190                   <access>R/W</access>\r
1191                   <description>\r
1192                   </description>\r
1193                 </field>\r
1194                 <field>\r
1195                   <name>OADIVRST</name>\r
1196                   <bitNumber>6</bitNumber>\r
1197                   <access>R/W</access>\r
1198                   <description>\r
1199                   </description>\r
1200                 </field>\r
1201                 <field>\r
1202                   <name>OADIVHALF</name>\r
1203                   <bitNumber>5</bitNumber>\r
1204                   <access>R/W</access>\r
1205                   <description>\r
1206                   </description>\r
1207                 </field>\r
1208                 <field>\r
1209                   <name>OADIV4</name>\r
1210                   <bitNumber>4</bitNumber>\r
1211                   <access>R/W</access>\r
1212                   <description>\r
1213                   </description>\r
1214                 </field>\r
1215                 <field>\r
1216                   <name>OADIV3</name>\r
1217                   <bitNumber>3</bitNumber>\r
1218                   <access>R/W</access>\r
1219                   <description>\r
1220                   </description>\r
1221                 </field>\r
1222                 <field>\r
1223                   <name>OADIV2</name>\r
1224                   <bitNumber>2</bitNumber>\r
1225                   <access>R/W</access>\r
1226                   <description>\r
1227                   </description>\r
1228                 </field>\r
1229                 <field>\r
1230                   <name>OADIV1</name>\r
1231                   <bitNumber>1</bitNumber>\r
1232                   <access>R/W</access>\r
1233                   <description>\r
1234                   </description>\r
1235                 </field>\r
1236                 <field>\r
1237                   <name>OADIV0</name>\r
1238                   <bitNumber>0</bitNumber>\r
1239                   <access>R/W</access>\r
1240                   <description>\r
1241                   </description>\r
1242                 </field>\r
1243               </register>\r
1244               <register>\r
1245                 <name>CCC_MUX_CONFIG</name>\r
1246                 <addressOffset>0x50</addressOffset>\r
1247                 <absoluteAddress>0x40038050</absoluteAddress>\r
1248                 <size>32</size>\r
1249                 <access>R/W</access>\r
1250                 <resetValue>0x0</resetValue>\r
1251                 <field>\r
1252                   <name>MODE</name>\r
1253                   <bitNumber>31:30</bitNumber>\r
1254                   <access>R/W</access>\r
1255                   <description>\r
1256                   </description>\r
1257                 </field>\r
1258                 <field>\r
1259                   <name>EN</name>\r
1260                   <bitNumber>29</bitNumber>\r
1261                   <access>R/W</access>\r
1262                   <description>\r
1263                   </description>\r
1264                 </field>\r
1265                 <field>\r
1266                   <name>GLMUXCFG1</name>\r
1267                   <bitNumber>27</bitNumber>\r
1268                   <access>R/W</access>\r
1269                   <description>\r
1270                   </description>\r
1271                 </field>\r
1272                 <field>\r
1273                   <name>GLMUXCFG0</name>\r
1274                   <bitNumber>26</bitNumber>\r
1275                   <access>R/W</access>\r
1276                   <description>\r
1277                   </description>\r
1278                 </field>\r
1279                 <field>\r
1280                   <name>GLMUXSEL1</name>\r
1281                   <bitNumber>25</bitNumber>\r
1282                   <access>R/W</access>\r
1283                   <description>\r
1284                   </description>\r
1285                 </field>\r
1286                 <field>\r
1287                   <name>GLMUXSEL0</name>\r
1288                   <bitNumber>24</bitNumber>\r
1289                   <access>R/W</access>\r
1290                   <description>\r
1291                   </description>\r
1292                 </field>\r
1293                 <field>\r
1294                   <name>BYPASS_PLL3</name>\r
1295                   <bitNumber>22</bitNumber>\r
1296                   <access>R/W</access>\r
1297                   <description>\r
1298                   </description>\r
1299                 </field>\r
1300                 <field>\r
1301                   <name>OCMUX2</name>\r
1302                   <bitNumber>21</bitNumber>\r
1303                   <access>R/W</access>\r
1304                   <description>\r
1305                   </description>\r
1306                 </field>\r
1307                 <field>\r
1308                   <name>OCMUX1</name>\r
1309                   <bitNumber>20</bitNumber>\r
1310                   <access>R/W</access>\r
1311                   <description>\r
1312                   </description>\r
1313                 </field>\r
1314                 <field>\r
1315                   <name>OCMUX0</name>\r
1316                   <bitNumber>19</bitNumber>\r
1317                   <access>R/W</access>\r
1318                   <description>\r
1319                   </description>\r
1320                 </field>\r
1321                 <field>\r
1322                   <name>DYNCSEL</name>\r
1323                   <bitNumber>18</bitNumber>\r
1324                   <access>R/W</access>\r
1325                   <description>\r
1326                   </description>\r
1327                 </field>\r
1328                 <field>\r
1329                   <name>RXCSEL</name>\r
1330                   <bitNumber>17</bitNumber>\r
1331                   <access>R/W</access>\r
1332                   <description>\r
1333                   </description>\r
1334                 </field>\r
1335                 <field>\r
1336                   <name>STATCSEL</name>\r
1337                   <bitNumber>16</bitNumber>\r
1338                   <access>R/W</access>\r
1339                   <description>\r
1340                   </description>\r
1341                 </field>\r
1342                 <field>\r
1343                   <name>BYPASS_PLL2</name>\r
1344                   <bitNumber>14</bitNumber>\r
1345                   <access>R/W</access>\r
1346                   <description>\r
1347                   </description>\r
1348                 </field>\r
1349                 <field>\r
1350                   <name>OBMUX2</name>\r
1351                   <bitNumber>13</bitNumber>\r
1352                   <access>R/W</access>\r
1353                   <description>\r
1354                   </description>\r
1355                 </field>\r
1356                 <field>\r
1357                   <name>OBMUX1</name>\r
1358                   <bitNumber>12</bitNumber>\r
1359                   <access>R/W</access>\r
1360                   <description>\r
1361                   </description>\r
1362                 </field>\r
1363                 <field>\r
1364                   <name>OBMUX0</name>\r
1365                   <bitNumber>11</bitNumber>\r
1366                   <access>R/W</access>\r
1367                   <description>\r
1368                   </description>\r
1369                 </field>\r
1370                 <field>\r
1371                   <name>DYNBSEL</name>\r
1372                   <bitNumber>10</bitNumber>\r
1373                   <access>R/W</access>\r
1374                   <description>\r
1375                   </description>\r
1376                 </field>\r
1377                 <field>\r
1378                   <name>RXBSEL</name>\r
1379                   <bitNumber>9</bitNumber>\r
1380                   <access>R/W</access>\r
1381                   <description>\r
1382                   </description>\r
1383                 </field>\r
1384                 <field>\r
1385                   <name>STATBSEL</name>\r
1386                   <bitNumber>8</bitNumber>\r
1387                   <access>R/W</access>\r
1388                   <description>\r
1389                   </description>\r
1390                 </field>\r
1391                 <field>\r
1392                   <name>BYPASS_PLL1</name>\r
1393                   <bitNumber>6</bitNumber>\r
1394                   <access>R/W</access>\r
1395                   <description>\r
1396                   </description>\r
1397                 </field>\r
1398                 <field>\r
1399                   <name>OAMUX2</name>\r
1400                   <bitNumber>5</bitNumber>\r
1401                   <access>R/W</access>\r
1402                   <description>\r
1403                   </description>\r
1404                 </field>\r
1405                 <field>\r
1406                   <name>OAMUX1</name>\r
1407                   <bitNumber>4</bitNumber>\r
1408                   <access>R/W</access>\r
1409                   <description>\r
1410                   </description>\r
1411                 </field>\r
1412                 <field>\r
1413                   <name>OAMUX0</name>\r
1414                   <bitNumber>3</bitNumber>\r
1415                   <access>R/W</access>\r
1416                   <description>\r
1417                   </description>\r
1418                 </field>\r
1419                 <field>\r
1420                   <name>DYNASEL</name>\r
1421                   <bitNumber>2</bitNumber>\r
1422                   <access>R/W</access>\r
1423                   <description>\r
1424                   </description>\r
1425                 </field>\r
1426                 <field>\r
1427                   <name>RXASEL</name>\r
1428                   <bitNumber>1</bitNumber>\r
1429                   <access>R/W</access>\r
1430                   <description>\r
1431                   </description>\r
1432                 </field>\r
1433                 <field>\r
1434                   <name>STATASEL</name>\r
1435                   <bitNumber>0</bitNumber>\r
1436                   <access>R/W</access>\r
1437                   <description>\r
1438                   </description>\r
1439                 </field>\r
1440               </register>\r
1441               <register>\r
1442                 <name>CCC_PLL_CONFIG</name>\r
1443                 <addressOffset>0x54</addressOffset>\r
1444                 <absoluteAddress>0x40038054</absoluteAddress>\r
1445                 <size>32</size>\r
1446                 <access>R/W</access>\r
1447                 <resetValue>0x0</resetValue>\r
1448                 <field>\r
1449                   <name>POWERDOWN</name>\r
1450                   <bitNumber>31</bitNumber>\r
1451                   <access>R/W</access>\r
1452                   <description>\r
1453                   </description>\r
1454                 </field>\r
1455                 <field>\r
1456                   <name>VCOSEL2</name>\r
1457                   <bitNumber>24</bitNumber>\r
1458                   <access>R/W</access>\r
1459                   <description>\r
1460                   </description>\r
1461                 </field>\r
1462                 <field>\r
1463                   <name>VCOSEL1</name>\r
1464                   <bitNumber>23</bitNumber>\r
1465                   <access>R/W</access>\r
1466                   <description>\r
1467                   </description>\r
1468                 </field>\r
1469                 <field>\r
1470                   <name>VCOSEL0</name>\r
1471                   <bitNumber>22</bitNumber>\r
1472                   <access>R/W</access>\r
1473                   <description>\r
1474                   </description>\r
1475                 </field>\r
1476                 <field>\r
1477                   <name>XDLYSEL</name>\r
1478                   <bitNumber>21</bitNumber>\r
1479                   <access>R/W</access>\r
1480                   <description>\r
1481                   </description>\r
1482                 </field>\r
1483                 <field>\r
1484                   <name>FBDLY4</name>\r
1485                   <bitNumber>20</bitNumber>\r
1486                   <access>R/W</access>\r
1487                   <description>\r
1488                   </description>\r
1489                 </field>\r
1490                 <field>\r
1491                   <name>FBDLY3</name>\r
1492                   <bitNumber>19</bitNumber>\r
1493                   <access>R/W</access>\r
1494                   <description>\r
1495                   </description>\r
1496                 </field>\r
1497                 <field>\r
1498                   <name>FBDLY2</name>\r
1499                   <bitNumber>18</bitNumber>\r
1500                   <access>R/W</access>\r
1501                   <description>\r
1502                   </description>\r
1503                 </field>\r
1504                 <field>\r
1505                   <name>FBDLY1</name>\r
1506                   <bitNumber>17</bitNumber>\r
1507                   <access>R/W</access>\r
1508                   <description>\r
1509                   </description>\r
1510                 </field>\r
1511                 <field>\r
1512                   <name>FBDLY0</name>\r
1513                   <bitNumber>16</bitNumber>\r
1514                   <access>R/W</access>\r
1515                   <description>\r
1516                   </description>\r
1517                 </field>\r
1518                 <field>\r
1519                   <name>FBSEL1</name>\r
1520                   <bitNumber>15</bitNumber>\r
1521                   <access>R/W</access>\r
1522                   <description>\r
1523                   </description>\r
1524                 </field>\r
1525                 <field>\r
1526                   <name>FBSEL0</name>\r
1527                   <bitNumber>14</bitNumber>\r
1528                   <access>R/W</access>\r
1529                   <description>\r
1530                   </description>\r
1531                 </field>\r
1532                 <field>\r
1533                   <name>FBDIV6</name>\r
1534                   <bitNumber>13</bitNumber>\r
1535                   <access>R/W</access>\r
1536                   <description>\r
1537                   </description>\r
1538                 </field>\r
1539                 <field>\r
1540                   <name>FBDIV5</name>\r
1541                   <bitNumber>12</bitNumber>\r
1542                   <access>R/W</access>\r
1543                   <description>\r
1544                   </description>\r
1545                 </field>\r
1546                 <field>\r
1547                   <name>FBDIV4</name>\r
1548                   <bitNumber>11</bitNumber>\r
1549                   <access>R/W</access>\r
1550                   <description>\r
1551                   </description>\r
1552                 </field>\r
1553                 <field>\r
1554                   <name>FBDIV3</name>\r
1555                   <bitNumber>10</bitNumber>\r
1556                   <access>R/W</access>\r
1557                   <description>\r
1558                   </description>\r
1559                 </field>\r
1560                 <field>\r
1561                   <name>FBDIV2</name>\r
1562                   <bitNumber>9</bitNumber>\r
1563                   <access>R/W</access>\r
1564                   <description>\r
1565                   </description>\r
1566                 </field>\r
1567                 <field>\r
1568                   <name>FBDIV1</name>\r
1569                   <bitNumber>8</bitNumber>\r
1570                   <access>R/W</access>\r
1571                   <description>\r
1572                   </description>\r
1573                 </field>\r
1574                 <field>\r
1575                   <name>FBDIV0</name>\r
1576                   <bitNumber>7</bitNumber>\r
1577                   <access>R/W</access>\r
1578                   <description>\r
1579                   </description>\r
1580                 </field>\r
1581                 <field>\r
1582                   <name>FINDIV6</name>\r
1583                   <bitNumber>6</bitNumber>\r
1584                   <access>R/W</access>\r
1585                   <description>\r
1586                   </description>\r
1587                 </field>\r
1588                 <field>\r
1589                   <name>FINDIV5</name>\r
1590                   <bitNumber>5</bitNumber>\r
1591                   <access>R/W</access>\r
1592                   <description>\r
1593                   </description>\r
1594                 </field>\r
1595                 <field>\r
1596                   <name>FINDIV4</name>\r
1597                   <bitNumber>4</bitNumber>\r
1598                   <access>R/W</access>\r
1599                   <description>\r
1600                   </description>\r
1601                 </field>\r
1602                 <field>\r
1603                   <name>FINDIV3</name>\r
1604                   <bitNumber>3</bitNumber>\r
1605                   <access>R/W</access>\r
1606                   <description>\r
1607                   </description>\r
1608                 </field>\r
1609                 <field>\r
1610                   <name>FINDIV2</name>\r
1611                   <bitNumber>2</bitNumber>\r
1612                   <access>R/W</access>\r
1613                   <description>\r
1614                   </description>\r
1615                 </field>\r
1616                 <field>\r
1617                   <name>FINDIV1</name>\r
1618                   <bitNumber>1</bitNumber>\r
1619                   <access>R/W</access>\r
1620                   <description>\r
1621                   </description>\r
1622                 </field>\r
1623                 <field>\r
1624                   <name>FINDIV0</name>\r
1625                   <bitNumber>0</bitNumber>\r
1626                   <access>R/W</access>\r
1627                   <description>\r
1628                   </description>\r
1629                 </field>\r
1630               </register>\r
1631               <register>\r
1632                 <name>CCC_DLY_CONFIG</name>\r
1633                 <addressOffset>0x58</addressOffset>\r
1634                 <absoluteAddress>0x40038058</absoluteAddress>\r
1635                 <size>32</size>\r
1636                 <access>R/W</access>\r
1637                 <resetValue>0x0</resetValue>\r
1638                 <field>\r
1639                   <name>DLYA14</name>\r
1640                   <bitNumber>24</bitNumber>\r
1641                   <access>R/W</access>\r
1642                   <description>\r
1643                   </description>\r
1644                 </field>\r
1645                 <field>\r
1646                   <name>DLYA13</name>\r
1647                   <bitNumber>23</bitNumber>\r
1648                   <access>R/W</access>\r
1649                   <description>\r
1650                   </description>\r
1651                 </field>\r
1652                 <field>\r
1653                   <name>DLYA12</name>\r
1654                   <bitNumber>22</bitNumber>\r
1655                   <access>R/W</access>\r
1656                   <description>\r
1657                   </description>\r
1658                 </field>\r
1659                 <field>\r
1660                   <name>DLYA11</name>\r
1661                   <bitNumber>21</bitNumber>\r
1662                   <access>R/W</access>\r
1663                   <description>\r
1664                   </description>\r
1665                 </field>\r
1666                 <field>\r
1667                   <name>DLYA10</name>\r
1668                   <bitNumber>20</bitNumber>\r
1669                   <access>R/W</access>\r
1670                   <description>\r
1671                   </description>\r
1672                 </field>\r
1673                 <field>\r
1674                   <name>DLYA04</name>\r
1675                   <bitNumber>19</bitNumber>\r
1676                   <access>R/W</access>\r
1677                   <description>\r
1678                   </description>\r
1679                 </field>\r
1680                 <field>\r
1681                   <name>DLYA03</name>\r
1682                   <bitNumber>18</bitNumber>\r
1683                   <access>R/W</access>\r
1684                   <description>\r
1685                   </description>\r
1686                 </field>\r
1687                 <field>\r
1688                   <name>DLYA02</name>\r
1689                   <bitNumber>17</bitNumber>\r
1690                   <access>R/W</access>\r
1691                   <description>\r
1692                   </description>\r
1693                 </field>\r
1694                 <field>\r
1695                   <name>DLYA01</name>\r
1696                   <bitNumber>16</bitNumber>\r
1697                   <access>R/W</access>\r
1698                   <description>\r
1699                   </description>\r
1700                 </field>\r
1701                 <field>\r
1702                   <name>DLYA00</name>\r
1703                   <bitNumber>15</bitNumber>\r
1704                   <access>R/W</access>\r
1705                   <description>\r
1706                   </description>\r
1707                 </field>\r
1708                 <field>\r
1709                   <name>DLYHCC4</name>\r
1710                   <bitNumber>14</bitNumber>\r
1711                   <access>R/W</access>\r
1712                   <description>\r
1713                   </description>\r
1714                 </field>\r
1715                 <field>\r
1716                   <name>DLYHCC3</name>\r
1717                   <bitNumber>13</bitNumber>\r
1718                   <access>R/W</access>\r
1719                   <description>\r
1720                   </description>\r
1721                 </field>\r
1722                 <field>\r
1723                   <name>DLYHCC2</name>\r
1724                   <bitNumber>12</bitNumber>\r
1725                   <access>R/W</access>\r
1726                   <description>\r
1727                   </description>\r
1728                 </field>\r
1729                 <field>\r
1730                   <name>DLYHCC1</name>\r
1731                   <bitNumber>11</bitNumber>\r
1732                   <access>R/W</access>\r
1733                   <description>\r
1734                   </description>\r
1735                 </field>\r
1736                 <field>\r
1737                   <name>DLYHCC0</name>\r
1738                   <bitNumber>10</bitNumber>\r
1739                   <access>R/W</access>\r
1740                   <description>\r
1741                   </description>\r
1742                 </field>\r
1743                 <field>\r
1744                   <name>DLYHCB4</name>\r
1745                   <bitNumber>9</bitNumber>\r
1746                   <access>R/W</access>\r
1747                   <description>\r
1748                   </description>\r
1749                 </field>\r
1750                 <field>\r
1751                   <name>DLYHCB3</name>\r
1752                   <bitNumber>8</bitNumber>\r
1753                   <access>R/W</access>\r
1754                   <description>\r
1755                   </description>\r
1756                 </field>\r
1757                 <field>\r
1758                   <name>DLYHCB2</name>\r
1759                   <bitNumber>7</bitNumber>\r
1760                   <access>R/W</access>\r
1761                   <description>\r
1762                   </description>\r
1763                 </field>\r
1764                 <field>\r
1765                   <name>DLYHCB1</name>\r
1766                   <bitNumber>6</bitNumber>\r
1767                   <access>R/W</access>\r
1768                   <description>\r
1769                   </description>\r
1770                 </field>\r
1771                 <field>\r
1772                   <name>DLYHCB0</name>\r
1773                   <bitNumber>5</bitNumber>\r
1774                   <access>R/W</access>\r
1775                   <description>\r
1776                   </description>\r
1777                 </field>\r
1778                 <field>\r
1779                   <name>DLYHCA4</name>\r
1780                   <bitNumber>4</bitNumber>\r
1781                   <access>R/W</access>\r
1782                   <description>\r
1783                   </description>\r
1784                 </field>\r
1785                 <field>\r
1786                   <name>DLYHCA3</name>\r
1787                   <bitNumber>3</bitNumber>\r
1788                   <access>R/W</access>\r
1789                   <description>\r
1790                   </description>\r
1791                 </field>\r
1792                 <field>\r
1793                   <name>DLYHCA2</name>\r
1794                   <bitNumber>2</bitNumber>\r
1795                   <access>R/W</access>\r
1796                   <description>\r
1797                   </description>\r
1798                 </field>\r
1799                 <field>\r
1800                   <name>DLYHCA1</name>\r
1801                   <bitNumber>1</bitNumber>\r
1802                   <access>R/W</access>\r
1803                   <description>\r
1804                   </description>\r
1805                 </field>\r
1806                 <field>\r
1807                   <name>DLYHCA0</name>\r
1808                   <bitNumber>0</bitNumber>\r
1809                   <access>R/W</access>\r
1810                   <description>\r
1811                   </description>\r
1812                 </field>\r
1813               </register>\r
1814               <register>\r
1815                 <name>CCC_STATUS</name>\r
1816                 <addressOffset>0x5C</addressOffset>\r
1817                 <absoluteAddress>0x4003805C</absoluteAddress>\r
1818                 <size>32</size>\r
1819                 <access>R/W</access>\r
1820                 <resetValue>0x0</resetValue>\r
1821                 <field>\r
1822                   <name>PLLLOCK_SYNC</name>\r
1823                   <bitNumber>0</bitNumber>\r
1824                   <access>R/W</access>\r
1825                   <description>\r
1826                   </description>\r
1827                 </field>\r
1828               </register>\r
1829               <register>\r
1830                 <name>VTG_CTRL</name>\r
1831                 <addressOffset>0x64</addressOffset>\r
1832                 <absoluteAddress>0x40038064</absoluteAddress>\r
1833                 <size>32</size>\r
1834                 <access>R/W</access>\r
1835                 <resetValue>0x0</resetValue>\r
1836                 <field>\r
1837                   <name>BGPSMENABLE</name>\r
1838                   <bitNumber>4</bitNumber>\r
1839                   <access>R/W</access>\r
1840                   <description>\r
1841                   </description>\r
1842                 </field>\r
1843                 <field>\r
1844                   <name>VBATSELECT</name>\r
1845                   <bitNumber>3</bitNumber>\r
1846                   <access>R/W</access>\r
1847                   <description>\r
1848                   </description>\r
1849                 </field>\r
1850                 <field>\r
1851                   <name>RTCIF_CLRPUBINT</name>\r
1852                   <bitNumber>2</bitNumber>\r
1853                   <access>R/W</access>\r
1854                   <description>\r
1855                   </description>\r
1856                 </field>\r
1857                 <field>\r
1858                   <name>RTCIF_VRONENABLE</name>\r
1859                   <bitNumber>1</bitNumber>\r
1860                   <access>R/W</access>\r
1861                   <description>\r
1862                   </description>\r
1863                 </field>\r
1864                 <field>\r
1865                   <name>RTCIF_FWVRON</name>\r
1866                   <bitNumber>0</bitNumber>\r
1867                   <access>R/W</access>\r
1868                   <description>\r
1869                   </description>\r
1870                 </field>\r
1871               </register>\r
1872               <register>\r
1873                 <name>FAB_IF</name>\r
1874                 <addressOffset>0x6C</addressOffset>\r
1875                 <absoluteAddress>0x4003806C</absoluteAddress>\r
1876                 <size>32</size>\r
1877                 <access>R/W</access>\r
1878                 <resetValue>0x0</resetValue>\r
1879                 <field>\r
1880                   <name>FABCALIBFAIL</name>\r
1881                   <bitNumber>6</bitNumber>\r
1882                   <access>R/W</access>\r
1883                   <description>\r
1884                   </description>\r
1885                 </field>\r
1886                 <field>\r
1887                   <name>FABCALIBSTART</name>\r
1888                   <bitNumber>5</bitNumber>\r
1889                   <access>R/W</access>\r
1890                   <description>\r
1891                   </description>\r
1892                 </field>\r
1893                 <field>\r
1894                   <name>F2_LARGE_CT_XS</name>\r
1895                   <bitNumber>4</bitNumber>\r
1896                   <access>R/W</access>\r
1897                   <description>\r
1898                   </description>\r
1899                 </field>\r
1900                 <field>\r
1901                   <name>FAB_APB32</name>\r
1902                   <bitNumber>3</bitNumber>\r
1903                   <access>R/W</access>\r
1904                   <description>\r
1905                   </description>\r
1906                 </field>\r
1907                 <field>\r
1908                   <name>FAB_AHBIF</name>\r
1909                   <bitNumber>2</bitNumber>\r
1910                   <access>R/W</access>\r
1911                   <description>\r
1912                   </description>\r
1913                 </field>\r
1914                 <field>\r
1915                   <name>F2_AHBCAPABLE</name>\r
1916                   <bitNumber>1</bitNumber>\r
1917                   <access>R/W</access>\r
1918                   <description>\r
1919                   </description>\r
1920                 </field>\r
1921                 <field>\r
1922                   <name>FAB_AHB_BYPASS</name>\r
1923                   <bitNumber>0</bitNumber>\r
1924                   <access>R/W</access>\r
1925                   <description>\r
1926                   </description>\r
1927                 </field>\r
1928               </register>\r
1929               <register>\r
1930                 <name>APB_EXTN</name>\r
1931                 <addressOffset>0x70</addressOffset>\r
1932                 <absoluteAddress>0x40038070</absoluteAddress>\r
1933                 <size>32</size>\r
1934                 <access>R/W</access>\r
1935                 <resetValue>0x0</resetValue>\r
1936                 <field>\r
1937                   <name>APB16_XHOLD</name>\r
1938                   <bitNumber>15:0</bitNumber>\r
1939                   <access>R/W</access>\r
1940                   <description>\r
1941                   </description>\r
1942                 </field>\r
1943               </register>\r
1944               <register>\r
1945                 <name>LOOPBACK_CTRL</name>\r
1946                 <addressOffset>0x74</addressOffset>\r
1947                 <absoluteAddress>0x40038074</absoluteAddress>\r
1948                 <size>32</size>\r
1949                 <access>R/W</access>\r
1950                 <resetValue>0x0</resetValue>\r
1951                 <field>\r
1952                   <name>DSS_EMACLOOPBACK</name>\r
1953                   <bitNumber>4</bitNumber>\r
1954                   <access>R/W</access>\r
1955                   <description>\r
1956                   </description>\r
1957                 </field>\r
1958                 <field>\r
1959                   <name>DSS_GPIOLOOPBACK</name>\r
1960                   <bitNumber>3</bitNumber>\r
1961                   <access>R/W</access>\r
1962                   <description>\r
1963                   </description>\r
1964                 </field>\r
1965                 <field>\r
1966                   <name>DSS_I2CLOOPBACK</name>\r
1967                   <bitNumber>2</bitNumber>\r
1968                   <access>R/W</access>\r
1969                   <description>\r
1970                   </description>\r
1971                 </field>\r
1972                 <field>\r
1973                   <name>DSS_SPILOOPBACK</name>\r
1974                   <bitNumber>1</bitNumber>\r
1975                   <access>R/W</access>\r
1976                   <description>\r
1977                   </description>\r
1978                 </field>\r
1979                 <field>\r
1980                   <name>DSS_UARTLOOPBACK</name>\r
1981                   <bitNumber>0</bitNumber>\r
1982                   <access>R/W</access>\r
1983                   <description>\r
1984                   </description>\r
1985                 </field>\r
1986               </register>\r
1987               <register>\r
1988                 <name>IO_BANK_CONFIG</name>\r
1989                 <addressOffset>0x78</addressOffset>\r
1990                 <absoluteAddress>0x40038078</absoluteAddress>\r
1991                 <size>32</size>\r
1992                 <access>R/W</access>\r
1993                 <resetValue>0x0</resetValue>\r
1994                 <field>\r
1995                   <name>BTWEST</name>\r
1996                   <bitNumber>3:2</bitNumber>\r
1997                   <access>R/W</access>\r
1998                   <description>\r
1999                   </description>\r
2000                 </field>\r
2001                 <field>\r
2002                   <name>BTEAST</name>\r
2003                   <bitNumber>1:0</bitNumber>\r
2004                   <access>R/W</access>\r
2005                   <description>\r
2006                   </description>\r
2007                 </field>\r
2008               </register>\r
2009               <register>\r
2010                 <name>GPIN_SRC_SEL</name>\r
2011                 <addressOffset>0x7C</addressOffset>\r
2012                 <absoluteAddress>0x4003807C</absoluteAddress>\r
2013                 <size>32</size>\r
2014                 <access>R/W</access>\r
2015                 <resetValue>0x0</resetValue>\r
2016                 <field>\r
2017                   <name>DSS_GPINSOURCE[15]</name>\r
2018                   <bitNumber>15</bitNumber>\r
2019                   <access>R/W</access>\r
2020                   <description>\r
2021                   </description>\r
2022                 </field>\r
2023                 <field>\r
2024                   <name>DSS_GPINSOURCE[14]</name>\r
2025                   <bitNumber>14</bitNumber>\r
2026                   <access>R/W</access>\r
2027                   <description>\r
2028                   </description>\r
2029                 </field>\r
2030                 <field>\r
2031                   <name>DSS_GPINSOURCE[13]</name>\r
2032                   <bitNumber>13</bitNumber>\r
2033                   <access>R/W</access>\r
2034                   <description>\r
2035                   </description>\r
2036                 </field>\r
2037                 <field>\r
2038                   <name>DSS_GPINSOURCE[12]</name>\r
2039                   <bitNumber>12</bitNumber>\r
2040                   <access>R/W</access>\r
2041                   <description>\r
2042                   </description>\r
2043                 </field>\r
2044                 <field>\r
2045                   <name>DSS_GPINSOURCE[11]</name>\r
2046                   <bitNumber>11</bitNumber>\r
2047                   <access>R/W</access>\r
2048                   <description>\r
2049                   </description>\r
2050                 </field>\r
2051                 <field>\r
2052                   <name>DSS_GPINSOURCE[10]</name>\r
2053                   <bitNumber>10</bitNumber>\r
2054                   <access>R/W</access>\r
2055                   <description>\r
2056                   </description>\r
2057                 </field>\r
2058                 <field>\r
2059                   <name>DSS_GPINSOURCE[9]</name>\r
2060                   <bitNumber>9</bitNumber>\r
2061                   <access>R/W</access>\r
2062                   <description>\r
2063                   </description>\r
2064                 </field>\r
2065                 <field>\r
2066                   <name>DSS_GPINSOURCE[8]</name>\r
2067                   <bitNumber>8</bitNumber>\r
2068                   <access>R/W</access>\r
2069                   <description>\r
2070                   </description>\r
2071                 </field>\r
2072                 <field>\r
2073                   <name>DSS_GPINSOURCE[7]</name>\r
2074                   <bitNumber>7</bitNumber>\r
2075                   <access>R/W</access>\r
2076                   <description>\r
2077                   </description>\r
2078                 </field>\r
2079                 <field>\r
2080                   <name>DSS_GPINSOURCE[6]</name>\r
2081                   <bitNumber>6</bitNumber>\r
2082                   <access>R/W</access>\r
2083                   <description>\r
2084                   </description>\r
2085                 </field>\r
2086                 <field>\r
2087                   <name>DSS_GPINSOURCE[5]</name>\r
2088                   <bitNumber>5</bitNumber>\r
2089                   <access>R/W</access>\r
2090                   <description>\r
2091                   </description>\r
2092                 </field>\r
2093                 <field>\r
2094                   <name>DSS_GPINSOURCE[4]</name>\r
2095                   <bitNumber>4</bitNumber>\r
2096                   <access>R/W</access>\r
2097                   <description>\r
2098                   </description>\r
2099                 </field>\r
2100                 <field>\r
2101                   <name>DSS_GPINSOURCE[3]</name>\r
2102                   <bitNumber>3</bitNumber>\r
2103                   <access>R/W</access>\r
2104                   <description>\r
2105                   </description>\r
2106                 </field>\r
2107                 <field>\r
2108                   <name>DSS_GPINSOURCE[2]</name>\r
2109                   <bitNumber>2</bitNumber>\r
2110                   <access>R/W</access>\r
2111                   <description>\r
2112                   </description>\r
2113                 </field>\r
2114                 <field>\r
2115                   <name>DSS_GPINSOURCE[1]</name>\r
2116                   <bitNumber>1</bitNumber>\r
2117                   <access>R/W</access>\r
2118                   <description>\r
2119                   </description>\r
2120                 </field>\r
2121                 <field>\r
2122                   <name>DSS_GPINSOURCE[0]</name>\r
2123                   <bitNumber>0</bitNumber>\r
2124                   <access>R/W</access>\r
2125                   <description>\r
2126                   </description>\r
2127                 </field>\r
2128               </register>\r
2129             </addressBlock>\r
2130           </memoryMap>\r
2131         </slave>\r
2132         <slave>\r
2133           <name>RTC</name>\r
2134           <fullPinName>\r
2135           </fullPinName>\r
2136           <remapAddress>0x40017000</remapAddress>\r
2137           <fullAddressSpace>0x40017000 - 0x40017FFF</fullAddressSpace>\r
2138           <range>0x1000</range>\r
2139         </slave>\r
2140         <slave>\r
2141           <name>COMBLK</name>\r
2142           <fullPinName>\r
2143           </fullPinName>\r
2144           <remapAddress>0x40016000</remapAddress>\r
2145           <fullAddressSpace>0x40016000 - 0x40016FFF</fullAddressSpace>\r
2146           <range>0x1000</range>\r
2147         </slave>\r
2148         <slave>\r
2149           <name>HDMA</name>\r
2150           <fullPinName>\r
2151           </fullPinName>\r
2152           <remapAddress>0x40014000</remapAddress>\r
2153           <fullAddressSpace>0x40014000 - 0x40014FFF</fullAddressSpace>\r
2154           <range>0x1000</range>\r
2155         </slave>\r
2156         <slave>\r
2157           <name>GPIO</name>\r
2158           <fullPinName>\r
2159           </fullPinName>\r
2160           <remapAddress>0x40013000</remapAddress>\r
2161           <fullAddressSpace>0x40013000 - 0x40013FFF</fullAddressSpace>\r
2162           <range>0x1000</range>\r
2163         </slave>\r
2164         <slave>\r
2165           <name>H2FINTERRUPT</name>\r
2166           <fullPinName>\r
2167           </fullPinName>\r
2168           <remapAddress>0x40006000</remapAddress>\r
2169           <fullAddressSpace>0x40006000 - 0x40006FFF</fullAddressSpace>\r
2170           <range>0x1000</range>\r
2171         </slave>\r
2172         <slave>\r
2173           <name>TIMER</name>\r
2174           <fullPinName>\r
2175           </fullPinName>\r
2176           <remapAddress>0x40004000</remapAddress>\r
2177           <fullAddressSpace>0x40004000 - 0x40004FFF</fullAddressSpace>\r
2178           <range>0x1000</range>\r
2179         </slave>\r
2180         <slave>\r
2181           <name>MMUART_0</name>\r
2182           <fullPinName>\r
2183           </fullPinName>\r
2184           <remapAddress>0x40000000</remapAddress>\r
2185           <fullAddressSpace>0x40000000 - 0x40000FFF</fullAddressSpace>\r
2186           <range>0x1000</range>\r
2187         </slave>\r
2188         <slave>\r
2189           <name>RECYCLED_ESRAM1</name>\r
2190           <fullPinName>\r
2191           </fullPinName>\r
2192           <remapAddress>0x20012000</remapAddress>\r
2193           <fullAddressSpace>0x20012000 - 0x20013FFF</fullAddressSpace>\r
2194           <range>0x00002000</range>\r
2195         </slave>\r
2196         <slave>\r
2197           <name>RECYCLED_ESRAM0</name>\r
2198           <fullPinName>\r
2199           </fullPinName>\r
2200           <remapAddress>0x20010000</remapAddress>\r
2201           <fullAddressSpace>0x20010000 - 0x20011FFF</fullAddressSpace>\r
2202           <range>0x00002000</range>\r
2203         </slave>\r
2204         <slave>\r
2205           <name>ESRAM1</name>\r
2206           <fullPinName>\r
2207           </fullPinName>\r
2208           <remapAddress>0x20008000</remapAddress>\r
2209           <fullAddressSpace>0x20008000 - 0x2000FFFF</fullAddressSpace>\r
2210           <range>0x00008000</range>\r
2211         </slave>\r
2212         <slave>\r
2213           <name>ESRAM0</name>\r
2214           <fullPinName>\r
2215           </fullPinName>\r
2216           <remapAddress>0x00080000</remapAddress>\r
2217           <fullAddressSpace>0x00080000 - 0x00087FFF</fullAddressSpace>\r
2218           <range>0x00008000</range>\r
2219         </slave>\r
2220       </subsystem>\r
2221     </subsystems>\r
2222   </memorysystem>\r
2223 </datasheet>\r