1 /*****************************************************************************
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2 * © 2015 Microchip Technology Inc. and its subsidiaries.
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3 * You may use this software and any derivatives exclusively with
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4 * Microchip products.
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5 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
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6 * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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7 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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8 * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
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9 * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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10 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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11 * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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12 * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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13 * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
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14 * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
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15 * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
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16 * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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17 * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
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19 ******************************************************************************
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21 Version Control Information (Perforce)
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22 ******************************************************************************
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24 $DateTime: 2016/09/22 08:03:49 $
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26 Last Change: Updated for tabs
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27 ******************************************************************************/
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29 * \brief Power, Clocks, and Resets API Source file
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32 * This file implements the PCR APIs
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33 ******************************************************************************/
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39 #include "common_lib.h"
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43 /* ------------------------------------------------------------------------------- */
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44 /* Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block */
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45 /* ------------------------------------------------------------------------------- */
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47 /** Sets or Clears block specific bit in PCR Sleep Enable Register
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48 * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
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49 * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register
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51 void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)
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54 uint8_t pcr_reg_id;
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56 bit_mask = 1UL<<(pcr_block_id & 0xFFu);
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57 pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu);
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59 p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag);
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63 /** Get Clock Required Status for the block
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64 * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
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65 * @return uint8_t - 1 if Clock Required Status set, else 0
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67 uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id)
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70 uint8_t pcr_reg_id, retVal;
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72 bit_mask = 1UL<<(pcr_block_id & 0xFFu);
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73 pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu);
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76 if (p_pcr_reg_get(pcr_reg_id, bit_mask))
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84 /** Sets or Clears Reset Enable register bit for the block
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85 * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
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86 * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register
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88 void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)
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91 uint8_t pcr_reg_id;
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93 bit_mask = 1UL<<(pcr_block_id & 0xFFu);
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94 pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu);
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96 p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag);
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100 /* ------------------------------------------------------------------------------- */
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101 /* Functions for entering low power modes */
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102 /* ------------------------------------------------------------------------------- */
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104 /** Instructs all blocks to sleep by setting the Sleep Enable bits */
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105 void pcr_all_blocks_sleep(void)
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107 p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_0, 0xFFFFFFFF);
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108 p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_1, 0xFFFFFFFF);
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109 p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF);
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110 p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_3, 0xFFFFFFFF);
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111 p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_4, 0xFFFFFFFF);
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114 /** Clears the Sleep Enable bits for all blocks */
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115 void pcr_all_blocks_wake(void)
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117 p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_0, 0);
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118 p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_1, 0);
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119 p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0);
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120 p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_3, 0);
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121 p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_4, 0);
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124 /** Programs required sleep mode in System Sleep Control Register
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125 * @param sleep_mode - see enum SYSTEM_SLEEP_MODES
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127 void pcr_system_sleep(uint8_t sleep_mode)
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129 p_pcr_system_sleep_ctrl_write(sleep_mode);
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132 /** Reads the value of Power Reset status register
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134 * @return Power Reset Status Reg value
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136 uint16_t pcr_power_reset_status_read(void)
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138 return (p_pcr_pwr_reset_sts_get());
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141 /** Reads the value of Power Reset control register
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143 * @return Power reset control Reg value
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145 uint16_t pcr_power_reset_ctrl_read(void)
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147 return (p_pcr_pwr_reset_ctrl_read());
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150 /** Sets the value of PWR_INV bit to 1 or 0
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151 * @param set_clr: 1 or 0
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154 void pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr)
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156 p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(set_clr);
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159 /** Sets the value of HOST_RESET bit to 1 or 0
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160 * @param set_clr: 1 or 0
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163 void pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr)
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165 p_pcr_pwr_reset_ctrl_host_rst_set_clr(set_clr);
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168 /** Sets the SOFT SYS RESET bit to 1
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172 void pcr_system_reset_set()
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174 p_pcr_system_reset_set();
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177 /** Writes to the PKE Clock register
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178 * @param clock value
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181 void pcr_pke_clock_write(uint8_t pke_clk_val)
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183 p_pcr_pke_clock_write(pke_clk_val);
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186 /** Reads the PKE clock register
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188 * @return clock value
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190 uint8_t pcr_pke_clock_read()
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192 return (p_pcr_pke_clock_read());
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195 /** Writes to the OSC cal register
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196 * @param calibration value: 1 or 0
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199 void pcr_osc_cal_write(uint8_t pke_clk_val)
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201 p_pcr_osc_cal_write(pke_clk_val);
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204 /** Reads the osc cal register
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206 * @return cal value
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208 uint8_t pcr_osc_cal_read()
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210 return (p_pcr_osc_cal_read());
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214 /* end pcr_api.c */
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