1 /*****************************************************************************/
2 /* Startup_XMC4200.s: Startup file for XMC4200 device series */
3 /*****************************************************************************/
5 /* ********************* Version History *********************************** */
6 /* ***************************************************************************
7 V0.1 , Sep, 13, 2012 ES : initial version
8 V0.2 , Oct, 12, 2012 PKB: C++ support
9 V0.3 , Jan, 26, 2013 PKB: Workaround for prefetch bug
10 **************************************************************************** */
12 * @file Startup_XMC4200.s
13 * XMC4000 Device Series
17 Copyright (C) 2013 Infineon Technologies AG. All rights reserved.
21 * Infineon Technologies AG (Infineon) is supplying this software for use with
22 * Infineon's microcontrollers. This file can be freely distributed
23 * within development tools that are supporting such microcontrollers.
26 * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
27 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
29 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
30 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
32 ******************************************************************************/
35 /* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
37 * STEP_AB and below have the prefetch bug. A veneer defined below will first
38 * be executed which in turn branches to the final exception handler.
40 * In addition to defining the veneers, the vector table must for these buggy
41 * devices contain the veneers.
44 /* A macro to setup a vector table entry based on STEP ID */
46 #if (UC_STEP > STEP_AA)
49 .long \Handler\()_Veneer
53 /* A macro to ease definition of the various handlers based on STEP ID */
54 #if (UC_STEP == STEP_AA)
55 /* First define the final exception handler */
56 .macro Insert_ExceptionHandler Handler_Func
58 .type \Handler_Func, %function
61 .size \Handler_Func, . - \Handler_Func
63 /* And then define a veneer that will branch to the final excp handler */
64 .weak \Handler_Func\()_Veneer
65 .type \Handler_Func\()_Veneer, %function
66 \Handler_Func\()_Veneer:
67 LDR R0, =\Handler_Func
71 .size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer
74 /* No prefetch bug, hence define only the final exception handler */
75 .macro Insert_ExceptionHandler Handler_Func
77 .type \Handler_Func, %function
80 .size \Handler_Func, . - \Handler_Func
83 /* =============END : MACRO DEFINITION MACRO DEFINITION ================== */
85 /* ================== START OF VECTOR TABLE DEFINITION ====================== */
86 /* Vector Table - This gets programed into VTOR register by onchip BootROM */
89 .section ".Xmc4200.reset"
90 .globl __Xmc4200_interrupt_vector_cortex_m
91 .type __Xmc4200_interrupt_vector_cortex_m, %object
93 __Xmc4200_interrupt_vector_cortex_m:
94 .long __Xmc4200_stack /* Top of Stack */
95 .long __Xmc4200_reset_cortex_m /* Reset Handler */
97 Entry NMI_Handler /* NMI Handler */
98 Entry HardFault_Handler /* Hard Fault Handler */
99 Entry MemManage_Handler /* MPU Fault Handler */
100 Entry BusFault_Handler /* Bus Fault Handler */
101 Entry UsageFault_Handler /* Usage Fault Handler */
102 .long 0 /* Reserved */
103 .long 0 /* Reserved */
104 .long 0 /* Reserved */
105 .long 0 /* Reserved */
106 Entry SVC_Handler /* SVCall Handler */
107 Entry DebugMon_Handler /* Debug Monitor Handler */
108 .long 0 /* Reserved */
109 .long PendSV_Handler /* PendSV Handler */
110 Entry SysTick_Handler /* SysTick Handler */
112 /* Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals */
113 Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */
114 Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */
115 Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */
116 Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */
117 Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */
118 Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */
119 Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */
120 Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */
121 Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */
122 .long 0 /* Not Available */
123 .long 0 /* Not Available */
124 .long 0 /* Not Available */
125 Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */
126 .long 0 /* Not Available */
127 Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */
128 Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */
129 Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */
130 Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */
131 Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */
132 Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */
133 Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */
134 Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */
135 Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */
136 Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */
137 Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */
138 Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */
139 .long 0 /* Not Available */
140 .long 0 /* Not Available */
141 .long 0 /* Not Available */
142 .long 0 /* Not Available */
143 .long 0 /* Not Available */
144 .long 0 /* Not Available */
145 .long 0 /* Not Available */
146 .long 0 /* Not Available */
147 .long 0 /* Not Available */
148 .long 0 /* Not Available */
149 .long 0 /* Not Available */
150 .long 0 /* Not Available */
151 .long 0 /* Not Available */
152 .long 0 /* Not Available */
153 .long 0 /* Not Available */
154 .long 0 /* Not Available */
155 Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */
156 Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_1 */
157 Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */
158 Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */
159 Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */
160 Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */
161 Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */
162 Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */
163 Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */
164 Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */
165 .long 0 /* Not Available */
166 .long 0 /* Not Available */
167 .long 0 /* Not Available */
168 .long 0 /* Not Available */
169 .long 0 /* Not Available */
170 .long 0 /* Not Available */
171 .long 0 /* Not Available */
172 .long 0 /* Not Available */
173 Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */
174 Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */
175 Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */
176 Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */
177 .long 0 /* Not Available */
178 .long 0 /* Not Available */
179 .long 0 /* Not Available */
180 .long 0 /* Not Available */
181 Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */
182 Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */
183 .long 0 /* Not Available */
184 .long 0 /* Not Available */
185 Entry HRPWM_0_IRQHandler /* Handler name for SR HRPWM_0 */
186 Entry HRPWM_1_IRQHandler /* Handler name for SR HRPWM_1 */
187 Entry HRPWM_2_IRQHandler /* Handler name for SR HRPWM_2 */
188 Entry HRPWM_3_IRQHandler /* Handler name for SR HRPWM_3 */
189 Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */
190 Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */
191 Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */
192 Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */
193 Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */
194 Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */
195 Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */
196 Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */
197 Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */
198 Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */
199 Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */
200 Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */
201 Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */
202 Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */
203 Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */
204 Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */
205 Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */
206 Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */
207 Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */
208 Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */
209 .long 0 /* Not Available */
210 .long 0 /* Not Available */
211 .long 0 /* Not Available */
212 .long 0 /* Not Available */
213 .long 0 /* Not Available */
214 .long 0 /* Not Available */
215 Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */
216 .long 0 /* Not Available */
217 Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */
218 Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */
219 .long 0 /* Not Available */
220 Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */
221 .long 0 /* Not Available */
222 .long 0 /* Not Available */
223 .long 0 /* Not Available */
224 .long 0 /* Not Available */
226 .size __Xmc4200_interrupt_vector_cortex_m, . - __Xmc4200_interrupt_vector_cortex_m
227 /* ================== END OF VECTOR TABLE DEFINITION ======================= */
229 /* ================== START OF VECTOR ROUTINES ============================= */
231 /* ======================================================================== */
235 .globl __Xmc4200_reset_cortex_m
236 .type __Xmc4200_reset_cortex_m, %function
237 __Xmc4200_reset_cortex_m:
240 /* C routines are likely to be called. Setup the stack now */
241 /* This is already setup by BootROM,hence this step is optional */
242 LDR SP,=__Xmc4200_stack
244 /* Clock tree, External memory setup etc may be done here */
249 SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
250 weakly defined here though for a potential override.
252 LDR R0, =SystemInit_DAVE3
255 B __Xmc4200_Program_Loader
260 .size __Xmc4200_reset_cortex_m,.-__Xmc4200_reset_cortex_m
261 /* ======================================================================== */
262 /* __Xmc4200_reset must yield control to __Xmc4200_Program_Loader before control
263 to C land is given */
264 .section .Xmc4200.postreset,"x",%progbits
265 __Xmc4200_Program_Loader:
267 /* Memories are accessible now*/
270 /* R0 = Start address, R1 = Destination address, R2 = Size */
272 LDR R1, =__Xmc4200_sData
273 LDR R2, =__Xmc4200_Data_Size
275 /* Is there anything to be copied? */
279 /* For bytecount less than 4, at least 1 word must be copied */
283 /* Byte count < 4 ; so bump it up */
288 R2 contains byte count. Change it to word count. It is ensured in the
289 linker script that the length is always word aligned.
291 LSR R2,R2,#2 /* Divide by 4 to obtain word count */
293 /* The proverbial loop from the schooldays */
305 LDR R0, =__Xmc4200_sBSS /* Start of BSS */
306 LDR R1, =__Xmc4200_BSS_Size /* BSS size in bytes */
308 /* Find out if there are items assigned to BSS */
312 /* At least 1 word must be copied */
316 /* Byte count < 4 ; so bump it up to a word*/
320 LSR R1,R1,#2 /* BSS size in words */
331 /* Remap vector table */
332 /* This is already setup by BootROM,hence this step is optional */
333 LDR R0, =__Xmc4200_interrupt_vector_cortex_m
337 /* Update System Clock */
338 LDR R0,=SystemCoreClockUpdate
341 /* C++ : Call the global constructor */
342 LDR R0,=__libc_init_array
345 /* Reset stack pointer before zipping off to user application, Optional */
346 LDR SP,=__Xmc4200_stack
353 .size __Xmc4200_Program_Loader,.-__Xmc4200_Program_Loader
354 /* ======================================================================== */
355 /* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
357 /* Default exception Handlers - Users may override this default functionality by
358 defining handlers of the same name in their C code */
362 Insert_ExceptionHandler NMI_Handler
363 /* ======================================================================== */
364 Insert_ExceptionHandler HardFault_Handler
365 /* ======================================================================== */
366 Insert_ExceptionHandler MemManage_Handler
367 /* ======================================================================== */
368 Insert_ExceptionHandler BusFault_Handler
369 /* ======================================================================== */
370 Insert_ExceptionHandler UsageFault_Handler
371 /* ======================================================================== */
372 Insert_ExceptionHandler SVC_Handler
373 /* ======================================================================== */
374 Insert_ExceptionHandler DebugMon_Handler
375 /* ======================================================================== */
376 Insert_ExceptionHandler PendSV_Handler
377 /* ======================================================================== */
378 Insert_ExceptionHandler SysTick_Handler
380 /* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
382 /* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
385 Insert_ExceptionHandler SCU_0_IRQHandler
386 /* ======================================================================== */
387 Insert_ExceptionHandler ERU0_0_IRQHandler
388 /* ======================================================================== */
389 Insert_ExceptionHandler ERU0_1_IRQHandler
390 /* ======================================================================== */
391 Insert_ExceptionHandler ERU0_2_IRQHandler
392 /* ======================================================================== */
393 Insert_ExceptionHandler ERU0_3_IRQHandler
394 /* ======================================================================== */
395 Insert_ExceptionHandler ERU1_0_IRQHandler
396 /* ======================================================================== */
397 Insert_ExceptionHandler ERU1_1_IRQHandler
398 /* ======================================================================== */
399 Insert_ExceptionHandler ERU1_2_IRQHandler
400 /* ======================================================================== */
401 Insert_ExceptionHandler ERU1_3_IRQHandler
402 /* ======================================================================== */
403 Insert_ExceptionHandler PMU0_0_IRQHandler
404 /* ======================================================================== */
405 Insert_ExceptionHandler VADC0_C0_0_IRQHandler
406 /* ======================================================================== */
407 Insert_ExceptionHandler VADC0_C0_1_IRQHandler
408 /* ======================================================================== */
409 Insert_ExceptionHandler VADC0_C0_2_IRQHandler
410 /* ======================================================================== */
411 Insert_ExceptionHandler VADC0_C0_3_IRQHandler
412 /* ======================================================================== */
413 Insert_ExceptionHandler VADC0_G0_0_IRQHandler
414 /* ======================================================================== */
415 Insert_ExceptionHandler VADC0_G0_1_IRQHandler
416 /* ======================================================================== */
417 Insert_ExceptionHandler VADC0_G0_2_IRQHandler
418 /* ======================================================================== */
419 Insert_ExceptionHandler VADC0_G0_3_IRQHandler
420 /* ======================================================================== */
421 Insert_ExceptionHandler VADC0_G1_0_IRQHandler
422 /* ======================================================================== */
423 Insert_ExceptionHandler VADC0_G1_1_IRQHandler
424 /* ======================================================================== */
425 Insert_ExceptionHandler VADC0_G1_2_IRQHandler
426 /* ======================================================================== */
427 Insert_ExceptionHandler VADC0_G1_3_IRQHandler
428 /* ======================================================================== */
429 Insert_ExceptionHandler DAC0_0_IRQHandler
430 /* ======================================================================== */
431 Insert_ExceptionHandler DAC0_1_IRQHandler
432 /* ======================================================================== */
433 Insert_ExceptionHandler CCU40_0_IRQHandler
434 /* ======================================================================== */
435 Insert_ExceptionHandler CCU40_1_IRQHandler
436 /* ======================================================================== */
437 Insert_ExceptionHandler CCU40_2_IRQHandler
438 /* ======================================================================== */
439 Insert_ExceptionHandler CCU40_3_IRQHandler
440 /* ======================================================================== */
441 Insert_ExceptionHandler CCU41_0_IRQHandler
442 /* ======================================================================== */
443 Insert_ExceptionHandler CCU41_1_IRQHandler
444 /* ======================================================================== */
445 Insert_ExceptionHandler CCU41_2_IRQHandler
446 /* ======================================================================== */
447 Insert_ExceptionHandler CCU41_3_IRQHandler
448 /* ======================================================================== */
449 Insert_ExceptionHandler CCU80_0_IRQHandler
450 /* ======================================================================== */
451 Insert_ExceptionHandler CCU80_1_IRQHandler
452 /* ======================================================================== */
453 Insert_ExceptionHandler CCU80_2_IRQHandler
454 /* ======================================================================== */
455 Insert_ExceptionHandler CCU80_3_IRQHandler
456 /* ======================================================================== */
457 Insert_ExceptionHandler POSIF0_0_IRQHandler
458 /* ======================================================================== */
459 Insert_ExceptionHandler POSIF0_1_IRQHandler
460 /* ======================================================================== */
461 Insert_ExceptionHandler HRPWM_0_IRQHandler
462 /* ======================================================================== */
463 Insert_ExceptionHandler HRPWM_1_IRQHandler
464 /* ======================================================================== */
465 Insert_ExceptionHandler HRPWM_2_IRQHandler
466 /* ======================================================================== */
467 Insert_ExceptionHandler HRPWM_3_IRQHandler
468 /* ======================================================================== */
469 Insert_ExceptionHandler CAN0_0_IRQHandler
470 /* ======================================================================== */
471 Insert_ExceptionHandler CAN0_1_IRQHandler
472 /* ======================================================================== */
473 Insert_ExceptionHandler CAN0_2_IRQHandler
474 /* ======================================================================== */
475 Insert_ExceptionHandler CAN0_3_IRQHandler
476 /* ======================================================================== */
477 Insert_ExceptionHandler CAN0_4_IRQHandler
478 /* ======================================================================== */
479 Insert_ExceptionHandler CAN0_5_IRQHandler
480 /* ======================================================================== */
481 Insert_ExceptionHandler CAN0_6_IRQHandler
482 /* ======================================================================== */
483 Insert_ExceptionHandler CAN0_7_IRQHandler
484 /* ======================================================================== */
485 Insert_ExceptionHandler USIC0_0_IRQHandler
486 /* ======================================================================== */
487 Insert_ExceptionHandler USIC0_1_IRQHandler
488 /* ======================================================================== */
489 Insert_ExceptionHandler USIC0_2_IRQHandler
490 /* ======================================================================== */
491 Insert_ExceptionHandler USIC0_3_IRQHandler
492 /* ======================================================================== */
493 Insert_ExceptionHandler USIC0_4_IRQHandler
494 /* ======================================================================== */
495 Insert_ExceptionHandler USIC0_5_IRQHandler
496 /* ======================================================================== */
497 Insert_ExceptionHandler USIC1_0_IRQHandler
498 /* ======================================================================== */
499 Insert_ExceptionHandler USIC1_1_IRQHandler
500 /* ======================================================================== */
501 Insert_ExceptionHandler USIC1_2_IRQHandler
502 /* ======================================================================== */
503 Insert_ExceptionHandler USIC1_3_IRQHandler
504 /* ======================================================================== */
505 Insert_ExceptionHandler USIC1_4_IRQHandler
506 /* ======================================================================== */
507 Insert_ExceptionHandler USIC1_5_IRQHandler
508 /* ======================================================================== */
509 Insert_ExceptionHandler LEDTS0_0_IRQHandler
510 /* ======================================================================== */
511 Insert_ExceptionHandler FCE0_0_IRQHandler
512 /* ======================================================================== */
513 Insert_ExceptionHandler GPDMA0_0_IRQHandler
514 /* ======================================================================== */
515 Insert_ExceptionHandler USB0_0_IRQHandler
516 /* ======================================================================== */
517 /* ======================================================================== */
519 /* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
521 /* ========= Decision function queried by CMSIS startup for PLL setup ======== */
522 /* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock
525 This decision routine defined here will always return TRUE.
527 When overridden by a definition defined in DAVE code engine, this routine
528 returns FALSE indicating that the code engine has performed the clock setup
530 .weak AllowPLLInitByStartup
531 .type AllowPLLInitByStartup, %function
532 AllowPLLInitByStartup:
535 .size AllowPLLInitByStartup, . - AllowPLLInitByStartup
537 /* ====== Definition of the default weak SystemInit_DAVE3 function =========
538 If DAVE3 requires an extended SystemInit it will create its own version of
539 SystemInit_DAVE3 which overrides this weak definition. Example includes
540 setting up of external memory interfaces.
542 .section ".XmcStartup"
543 .weak SystemInit_DAVE3
544 .type SystemInit_DAVE3, %function
548 .size SystemInit_DAVE3, . - SystemInit_DAVE3
549 /* ======================================================================== */
550 /* ======================================================================== */
552 /* ======================== Data references =============================== */
553 .equ SCB_VTOR, 0xE000ED08
554 .equ PREF_PCON, 0x58004000
555 .equ SCU_GCU_PEEN, 0x5000413C
556 .equ SCU_GCU_PEFLAG, 0x50004150
557 .equ FLASH_FCON, 0x58002014