2 /****************************************************************************************************//**
\r
5 * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for
\r
6 * XMC4400 from Infineon.
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8 * @version V1.1.0 (Reference Manual v1.1)
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9 * @date 13. December 2012
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11 * @note Generated with SVDConv V2.78b
\r
12 * from CMSIS SVD File 'XMC4400_Processed_SVD.xml' Version 1.1.0 (Reference Manual v1.1),
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13 *******************************************************************************************************/
\r
17 /** @addtogroup Infineon
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21 /** @addtogroup XMC4400
\r
33 /* ------------------------- Interrupt Number Definition ------------------------ */
\r
36 /* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
\r
37 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
\r
38 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
\r
39 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
\r
40 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
\r
42 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
\r
44 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
\r
45 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
\r
46 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
\r
47 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
\r
48 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
\r
49 /* --------------------- XMC4400 Specific Interrupt Numbers --------------------- */
\r
50 SCU_0_IRQn = 0, /*!< 0 SCU_0 */
\r
51 ERU0_0_IRQn = 1, /*!< 1 ERU0_0 */
\r
52 ERU0_1_IRQn = 2, /*!< 2 ERU0_1 */
\r
53 ERU0_2_IRQn = 3, /*!< 3 ERU0_2 */
\r
54 ERU0_3_IRQn = 4, /*!< 4 ERU0_3 */
\r
55 ERU1_0_IRQn = 5, /*!< 5 ERU1_0 */
\r
56 ERU1_1_IRQn = 6, /*!< 6 ERU1_1 */
\r
57 ERU1_2_IRQn = 7, /*!< 7 ERU1_2 */
\r
58 ERU1_3_IRQn = 8, /*!< 8 ERU1_3 */
\r
59 PMU0_0_IRQn = 12, /*!< 12 PMU0_0 */
\r
60 VADC0_C0_0_IRQn = 14, /*!< 14 VADC0_C0_0 */
\r
61 VADC0_C0_1_IRQn = 15, /*!< 15 VADC0_C0_1 */
\r
62 VADC0_C0_2_IRQn = 16, /*!< 16 VADC0_C0_2 */
\r
63 VADC0_C0_3_IRQn = 17, /*!< 17 VADC0_C0_3 */
\r
64 VADC0_G0_0_IRQn = 18, /*!< 18 VADC0_G0_0 */
\r
65 VADC0_G0_1_IRQn = 19, /*!< 19 VADC0_G0_1 */
\r
66 VADC0_G0_2_IRQn = 20, /*!< 20 VADC0_G0_2 */
\r
67 VADC0_G0_3_IRQn = 21, /*!< 21 VADC0_G0_3 */
\r
68 VADC0_G1_0_IRQn = 22, /*!< 22 VADC0_G1_0 */
\r
69 VADC0_G1_1_IRQn = 23, /*!< 23 VADC0_G1_1 */
\r
70 VADC0_G1_2_IRQn = 24, /*!< 24 VADC0_G1_2 */
\r
71 VADC0_G1_3_IRQn = 25, /*!< 25 VADC0_G1_3 */
\r
72 VADC0_G2_0_IRQn = 26, /*!< 26 VADC0_G2_0 */
\r
73 VADC0_G2_1_IRQn = 27, /*!< 27 VADC0_G2_1 */
\r
74 VADC0_G2_2_IRQn = 28, /*!< 28 VADC0_G2_2 */
\r
75 VADC0_G2_3_IRQn = 29, /*!< 29 VADC0_G2_3 */
\r
76 VADC0_G3_0_IRQn = 30, /*!< 30 VADC0_G3_0 */
\r
77 VADC0_G3_1_IRQn = 31, /*!< 31 VADC0_G3_1 */
\r
78 VADC0_G3_2_IRQn = 32, /*!< 32 VADC0_G3_2 */
\r
79 VADC0_G3_3_IRQn = 33, /*!< 33 VADC0_G3_3 */
\r
80 DSD0_M_0_IRQn = 34, /*!< 34 DSD0_M_0 */
\r
81 DSD0_M_1_IRQn = 35, /*!< 35 DSD0_M_1 */
\r
82 DSD0_M_2_IRQn = 36, /*!< 36 DSD0_M_2 */
\r
83 DSD0_M_3_IRQn = 37, /*!< 37 DSD0_M_3 */
\r
84 DSD0_A_4_IRQn = 38, /*!< 38 DSD0_A_4 */
\r
85 DSD0_A_5_IRQn = 39, /*!< 39 DSD0_A_5 */
\r
86 DSD0_A_6_IRQn = 40, /*!< 40 DSD0_A_6 */
\r
87 DSD0_A_7_IRQn = 41, /*!< 41 DSD0_A_7 */
\r
88 DAC0_0_IRQn = 42, /*!< 42 DAC0_0 */
\r
89 DAC0_1_IRQn = 43, /*!< 43 DAC0_1 */
\r
90 CCU40_0_IRQn = 44, /*!< 44 CCU40_0 */
\r
91 CCU40_1_IRQn = 45, /*!< 45 CCU40_1 */
\r
92 CCU40_2_IRQn = 46, /*!< 46 CCU40_2 */
\r
93 CCU40_3_IRQn = 47, /*!< 47 CCU40_3 */
\r
94 CCU41_0_IRQn = 48, /*!< 48 CCU41_0 */
\r
95 CCU41_1_IRQn = 49, /*!< 49 CCU41_1 */
\r
96 CCU41_2_IRQn = 50, /*!< 50 CCU41_2 */
\r
97 CCU41_3_IRQn = 51, /*!< 51 CCU41_3 */
\r
98 CCU42_0_IRQn = 52, /*!< 52 CCU42_0 */
\r
99 CCU42_1_IRQn = 53, /*!< 53 CCU42_1 */
\r
100 CCU42_2_IRQn = 54, /*!< 54 CCU42_2 */
\r
101 CCU42_3_IRQn = 55, /*!< 55 CCU42_3 */
\r
102 CCU43_0_IRQn = 56, /*!< 56 CCU43_0 */
\r
103 CCU43_1_IRQn = 57, /*!< 57 CCU43_1 */
\r
104 CCU43_2_IRQn = 58, /*!< 58 CCU43_2 */
\r
105 CCU43_3_IRQn = 59, /*!< 59 CCU43_3 */
\r
106 CCU80_0_IRQn = 60, /*!< 60 CCU80_0 */
\r
107 CCU80_1_IRQn = 61, /*!< 61 CCU80_1 */
\r
108 CCU80_2_IRQn = 62, /*!< 62 CCU80_2 */
\r
109 CCU80_3_IRQn = 63, /*!< 63 CCU80_3 */
\r
110 CCU81_0_IRQn = 64, /*!< 64 CCU81_0 */
\r
111 CCU81_1_IRQn = 65, /*!< 65 CCU81_1 */
\r
112 CCU81_2_IRQn = 66, /*!< 66 CCU81_2 */
\r
113 CCU81_3_IRQn = 67, /*!< 67 CCU81_3 */
\r
114 POSIF0_0_IRQn = 68, /*!< 68 POSIF0_0 */
\r
115 POSIF0_1_IRQn = 69, /*!< 69 POSIF0_1 */
\r
116 POSIF1_0_IRQn = 70, /*!< 70 POSIF1_0 */
\r
117 POSIF1_1_IRQn = 71, /*!< 71 POSIF1_1 */
\r
118 HRPWM_0_IRQn = 72, /*!< 72 HRPWM_0 */
\r
119 HRPWM_1_IRQn = 73, /*!< 73 HRPWM_1 */
\r
120 HRPWM_2_IRQn = 74, /*!< 72 HRPWM_2 */
\r
121 HRPWM_3_IRQn = 75, /*!< 73 HRPWM_3 */
\r
122 CAN0_0_IRQn = 76, /*!< 76 CAN0_0 */
\r
123 CAN0_1_IRQn = 77, /*!< 77 CAN0_1 */
\r
124 CAN0_2_IRQn = 78, /*!< 78 CAN0_2 */
\r
125 CAN0_3_IRQn = 79, /*!< 79 CAN0_3 */
\r
126 CAN0_4_IRQn = 80, /*!< 80 CAN0_4 */
\r
127 CAN0_5_IRQn = 81, /*!< 81 CAN0_5 */
\r
128 CAN0_6_IRQn = 82, /*!< 82 CAN0_6 */
\r
129 CAN0_7_IRQn = 83, /*!< 83 CAN0_7 */
\r
130 USIC0_0_IRQn = 84, /*!< 84 USIC0_0 */
\r
131 USIC0_1_IRQn = 85, /*!< 85 USIC0_1 */
\r
132 USIC0_2_IRQn = 86, /*!< 86 USIC0_2 */
\r
133 USIC0_3_IRQn = 87, /*!< 87 USIC0_3 */
\r
134 USIC0_4_IRQn = 88, /*!< 88 USIC0_4 */
\r
135 USIC0_5_IRQn = 89, /*!< 89 USIC0_5 */
\r
136 USIC1_0_IRQn = 90, /*!< 90 USIC1_0 */
\r
137 USIC1_1_IRQn = 91, /*!< 91 USIC1_1 */
\r
138 USIC1_2_IRQn = 92, /*!< 92 USIC1_2 */
\r
139 USIC1_3_IRQn = 93, /*!< 93 USIC1_3 */
\r
140 USIC1_4_IRQn = 94, /*!< 94 USIC1_4 */
\r
141 USIC1_5_IRQn = 95, /*!< 95 USIC1_5 */
\r
142 LEDTS0_0_IRQn = 102, /*!< 102 LEDTS0_0 */
\r
143 FCE0_0_IRQn = 104, /*!< 104 FCE0_0 */
\r
144 GPDMA0_0_IRQn = 105, /*!< 105 GPDMA0_0 */
\r
145 USB0_0_IRQn = 107, /*!< 107 USB0_0 */
\r
146 ETH0_0_IRQn = 108, /*!< 108 ETH0_0 */
\r
150 /** @addtogroup Configuration_of_CMSIS
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155 /* ================================================================================ */
\r
156 /* ================ Processor and Core Peripheral Section ================ */
\r
157 /* ================================================================================ */
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159 /* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
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160 #define __CM4_REV 0x0200 /*!< Cortex-M4 Core Revision */
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161 #define __MPU_PRESENT 1 /*!< MPU present or not */
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162 #define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */
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163 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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164 #define __FPU_PRESENT 1 /*!< FPU present or not */
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165 /** @} */ /* End of group Configuration_of_CMSIS */
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167 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
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168 #include "system_XMC4400.h" /*!< XMC4400 System */
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171 /* ================================================================================ */
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172 /* ================ Device Specific Peripheral Section ================ */
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173 /* ================================================================================ */
\r
174 /* Macro to modify desired bitfields of a register */
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175 #define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \
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176 ((uint32_t)mask)) | \
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177 (reg & ((uint32_t)~((uint32_t)mask)))
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179 /* Macro to modify desired bitfields of a register */
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180 #define WR_REG_SIZE(reg, mask, pos, val, size) { \
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181 uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \
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182 uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \
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183 uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \
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184 uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \
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185 reg = (uint##size##_t) (VAL2 | VAL4);\
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188 /** Macro to read bitfields from a register */
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189 #define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)
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191 /** Macro to read bitfields from a register */
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192 #define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \
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193 (uint32_t)mask) >> pos) )
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195 /** Macro to set a bit in register */
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196 #define SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos))
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198 /** Macro to clear a bit in register */
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199 #define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) )
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201 * ==========================================================================
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202 * ---------- Interrupt Handler Definition ----------------------------------
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203 * ==========================================================================
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205 #define IRQ_Hdlr_0 SCU_0_IRQHandler
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206 #define IRQ_Hdlr_1 ERU0_0_IRQHandler
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207 #define IRQ_Hdlr_2 ERU0_1_IRQHandler
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208 #define IRQ_Hdlr_3 ERU0_2_IRQHandler
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209 #define IRQ_Hdlr_4 ERU0_3_IRQHandler
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210 #define IRQ_Hdlr_5 ERU1_0_IRQHandler
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211 #define IRQ_Hdlr_6 ERU1_1_IRQHandler
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212 #define IRQ_Hdlr_7 ERU1_2_IRQHandler
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213 #define IRQ_Hdlr_8 ERU1_3_IRQHandler
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214 #define IRQ_Hdlr_12 PMU0_0_IRQHandler
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215 #define IRQ_Hdlr_14 VADC0_C0_0_IRQHandler
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216 #define IRQ_Hdlr_15 VADC0_C0_1_IRQHandler
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217 #define IRQ_Hdlr_16 VADC0_C0_2_IRQHandler
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218 #define IRQ_Hdlr_17 VADC0_C0_3_IRQHandler
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219 #define IRQ_Hdlr_18 VADC0_G0_0_IRQHandler
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220 #define IRQ_Hdlr_19 VADC0_G0_1_IRQHandler
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221 #define IRQ_Hdlr_20 VADC0_G0_2_IRQHandler
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222 #define IRQ_Hdlr_21 VADC0_G0_3_IRQHandler
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223 #define IRQ_Hdlr_22 VADC0_G1_0_IRQHandler
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224 #define IRQ_Hdlr_23 VADC0_G1_1_IRQHandler
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225 #define IRQ_Hdlr_24 VADC0_G1_2_IRQHandler
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226 #define IRQ_Hdlr_25 VADC0_G1_3_IRQHandler
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227 #define IRQ_Hdlr_26 VADC0_G2_0_IRQHandler
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228 #define IRQ_Hdlr_27 VADC0_G2_1_IRQHandler
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229 #define IRQ_Hdlr_28 VADC0_G2_2_IRQHandler
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230 #define IRQ_Hdlr_29 VADC0_G2_3_IRQHandler
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231 #define IRQ_Hdlr_30 VADC0_G3_0_IRQHandler
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232 #define IRQ_Hdlr_31 VADC0_G3_1_IRQHandler
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233 #define IRQ_Hdlr_32 VADC0_G3_2_IRQHandler
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234 #define IRQ_Hdlr_33 VADC0_G3_3_IRQHandler
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235 #define IRQ_Hdlr_34 DSD0_0_IRQHandler
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236 #define IRQ_Hdlr_35 DSD0_1_IRQHandler
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237 #define IRQ_Hdlr_36 DSD0_2_IRQHandler
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238 #define IRQ_Hdlr_37 DSD0_3_IRQHandler
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239 #define IRQ_Hdlr_38 DSD0_4_IRQHandler
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240 #define IRQ_Hdlr_39 DSD0_5_IRQHandler
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241 #define IRQ_Hdlr_40 DSD0_6_IRQHandler
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242 #define IRQ_Hdlr_41 DSD0_7_IRQHandler
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243 #define IRQ_Hdlr_42 DAC0_0_IRQHandler
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244 #define IRQ_Hdlr_43 DAC0_1_IRQHandler
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245 #define IRQ_Hdlr_44 CCU40_0_IRQHandler
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246 #define IRQ_Hdlr_45 CCU40_1_IRQHandler
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247 #define IRQ_Hdlr_46 CCU40_2_IRQHandler
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248 #define IRQ_Hdlr_47 CCU40_3_IRQHandler
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249 #define IRQ_Hdlr_48 CCU41_0_IRQHandler
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250 #define IRQ_Hdlr_49 CCU41_1_IRQHandler
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251 #define IRQ_Hdlr_50 CCU41_2_IRQHandler
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252 #define IRQ_Hdlr_51 CCU41_3_IRQHandler
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253 #define IRQ_Hdlr_52 CCU42_0_IRQHandler
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254 #define IRQ_Hdlr_53 CCU42_1_IRQHandler
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255 #define IRQ_Hdlr_54 CCU42_2_IRQHandler
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256 #define IRQ_Hdlr_55 CCU42_3_IRQHandler
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257 #define IRQ_Hdlr_56 CCU43_0_IRQHandler
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258 #define IRQ_Hdlr_57 CCU43_1_IRQHandler
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259 #define IRQ_Hdlr_58 CCU43_2_IRQHandler
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260 #define IRQ_Hdlr_59 CCU43_3_IRQHandler
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261 #define IRQ_Hdlr_60 CCU80_0_IRQHandler
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262 #define IRQ_Hdlr_61 CCU80_1_IRQHandler
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263 #define IRQ_Hdlr_62 CCU80_2_IRQHandler
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264 #define IRQ_Hdlr_63 CCU80_3_IRQHandler
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265 #define IRQ_Hdlr_64 CCU81_0_IRQHandler
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266 #define IRQ_Hdlr_65 CCU81_1_IRQHandler
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267 #define IRQ_Hdlr_66 CCU81_2_IRQHandler
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268 #define IRQ_Hdlr_67 CCU81_3_IRQHandler
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269 #define IRQ_Hdlr_68 POSIF0_0_IRQHandler
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270 #define IRQ_Hdlr_69 POSIF0_1_IRQHandler
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271 #define IRQ_Hdlr_70 POSIF1_0_IRQHandler
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272 #define IRQ_Hdlr_71 POSIF1_1_IRQHandler
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273 #define IRQ_Hdlr_72 HRPWM_0_IRQHandler
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274 #define IRQ_Hdlr_73 HRPWM_1_IRQHandler
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275 #define IRQ_Hdlr_74 HRPWM_2_IRQHandler
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276 #define IRQ_Hdlr_75 HRPWM_3_IRQHandler
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277 #define IRQ_Hdlr_76 CAN0_0_IRQHandler
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278 #define IRQ_Hdlr_77 CAN0_1_IRQHandler
\r
279 #define IRQ_Hdlr_78 CAN0_2_IRQHandler
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280 #define IRQ_Hdlr_79 CAN0_3_IRQHandler
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281 #define IRQ_Hdlr_80 CAN0_4_IRQHandler
\r
282 #define IRQ_Hdlr_81 CAN0_5_IRQHandler
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283 #define IRQ_Hdlr_82 CAN0_6_IRQHandler
\r
284 #define IRQ_Hdlr_83 CAN0_7_IRQHandler
\r
285 #define IRQ_Hdlr_84 USIC0_0_IRQHandler
\r
286 #define IRQ_Hdlr_85 USIC0_1_IRQHandler
\r
287 #define IRQ_Hdlr_86 USIC0_2_IRQHandler
\r
288 #define IRQ_Hdlr_87 USIC0_3_IRQHandler
\r
289 #define IRQ_Hdlr_88 USIC0_4_IRQHandler
\r
290 #define IRQ_Hdlr_89 USIC0_5_IRQHandler
\r
291 #define IRQ_Hdlr_90 USIC1_0_IRQHandler
\r
292 #define IRQ_Hdlr_91 USIC1_1_IRQHandler
\r
293 #define IRQ_Hdlr_92 USIC1_2_IRQHandler
\r
294 #define IRQ_Hdlr_93 USIC1_3_IRQHandler
\r
295 #define IRQ_Hdlr_94 USIC1_4_IRQHandler
\r
296 #define IRQ_Hdlr_95 USIC1_5_IRQHandler
\r
297 #define IRQ_Hdlr_101 USIC2_5_IRQHandler
\r
298 #define IRQ_Hdlr_102 LEDTS0_0_IRQHandler
\r
299 #define IRQ_Hdlr_104 FCE0_0_IRQHandler
\r
300 #define IRQ_Hdlr_105 GPDMA0_0_IRQHandler
\r
301 #define IRQ_Hdlr_107 USB0_0_IRQHandler
\r
302 #define IRQ_Hdlr_108 ETH0_0_IRQHandler
\r
305 * ==========================================================================
\r
306 * ---------- Interrupt Handler retrieval macro -----------------------------
\r
307 * ==========================================================================
\r
309 #define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N
\r
311 /** @addtogroup Device_Peripheral_Registers
\r
316 /* ------------------- Start of section using anonymous unions ------------------ */
\r
317 #if defined(__CC_ARM)
\r
319 #pragma anon_unions
\r
320 #elif defined(__ICCARM__)
\r
321 #pragma language=extended
\r
322 #elif defined(__GNUC__)
\r
323 /* anonymous unions are enabled by default */
\r
324 #elif defined(__TMS470__)
\r
325 /* anonymous unions are enabled by default */
\r
326 #elif defined(__TASKING__)
\r
327 #pragma warning 586
\r
329 #warning Not supported compiler type
\r
334 /* ================================================================================ */
\r
335 /* ================ PPB ================ */
\r
336 /* ================================================================================ */
\r
340 * @brief Cortex-M4 Private Peripheral Block (PPB)
\r
343 typedef struct { /*!< (@ 0xE000E000) PPB Structure */
\r
344 __I uint32_t RESERVED0[2];
\r
345 __IO uint32_t ACTLR; /*!< (@ 0xE000E008) Auxiliary Control Register */
\r
346 __I uint32_t RESERVED1;
\r
347 __IO uint32_t SYST_CSR; /*!< (@ 0xE000E010) SysTick Control and Status Register */
\r
348 __IO uint32_t SYST_RVR; /*!< (@ 0xE000E014) SysTick Reload Value Register */
\r
349 __IO uint32_t SYST_CVR; /*!< (@ 0xE000E018) SysTick Current Value Register */
\r
350 __IO uint32_t SYST_CALIB; /*!< (@ 0xE000E01C) SysTick Calibration Value Register r */
\r
351 __I uint32_t RESERVED2[56];
\r
352 __IO uint32_t NVIC_ISER0; /*!< (@ 0xE000E100) Interrupt Set-enable Register 0 */
\r
353 __IO uint32_t NVIC_ISER1; /*!< (@ 0xE000E104) Interrupt Set-enable Register 1 */
\r
354 __IO uint32_t NVIC_ISER2; /*!< (@ 0xE000E108) Interrupt Set-enable Register 2 */
\r
355 __IO uint32_t NVIC_ISER3; /*!< (@ 0xE000E10C) Interrupt Set-enable Register 3 */
\r
356 __I uint32_t RESERVED3[28];
\r
357 __IO uint32_t NVIC_ICER0; /*!< (@ 0xE000E180) Interrupt Clear-enable Register 0 */
\r
358 __IO uint32_t NVIC_ICER1; /*!< (@ 0xE000E184) Interrupt Clear-enable Register 1 */
\r
359 __IO uint32_t NVIC_ICER2; /*!< (@ 0xE000E188) Interrupt Clear-enable Register 2 */
\r
360 __IO uint32_t NVIC_ICER3; /*!< (@ 0xE000E18C) Interrupt Clear-enable Register 3 */
\r
361 __I uint32_t RESERVED4[28];
\r
362 __IO uint32_t NVIC_ISPR0; /*!< (@ 0xE000E200) Interrupt Set-pending Register 0 */
\r
363 __IO uint32_t NVIC_ISPR1; /*!< (@ 0xE000E204) Interrupt Set-pending Register 1 */
\r
364 __IO uint32_t NVIC_ISPR2; /*!< (@ 0xE000E208) Interrupt Set-pending Register 2 */
\r
365 __IO uint32_t NVIC_ISPR3; /*!< (@ 0xE000E20C) Interrupt Set-pending Register 3 */
\r
366 __I uint32_t RESERVED5[28];
\r
367 __IO uint32_t NVIC_ICPR0; /*!< (@ 0xE000E280) Interrupt Clear-pending Register 0 */
\r
368 __IO uint32_t NVIC_ICPR1; /*!< (@ 0xE000E284) Interrupt Clear-pending Register 1 */
\r
369 __IO uint32_t NVIC_ICPR2; /*!< (@ 0xE000E288) Interrupt Clear-pending Register 2 */
\r
370 __IO uint32_t NVIC_ICPR3; /*!< (@ 0xE000E28C) Interrupt Clear-pending Register 3 */
\r
371 __I uint32_t RESERVED6[28];
\r
372 __IO uint32_t NVIC_IABR0; /*!< (@ 0xE000E300) Interrupt Active Bit Register 0 */
\r
373 __IO uint32_t NVIC_IABR1; /*!< (@ 0xE000E304) Interrupt Active Bit Register 1 */
\r
374 __IO uint32_t NVIC_IABR2; /*!< (@ 0xE000E308) Interrupt Active Bit Register 2 */
\r
375 __IO uint32_t NVIC_IABR3; /*!< (@ 0xE000E30C) Interrupt Active Bit Register 3 */
\r
376 __I uint32_t RESERVED7[60];
\r
377 __IO uint32_t NVIC_IPR0; /*!< (@ 0xE000E400) Interrupt Priority Register 0 */
\r
378 __IO uint32_t NVIC_IPR1; /*!< (@ 0xE000E404) Interrupt Priority Register 1 */
\r
379 __IO uint32_t NVIC_IPR2; /*!< (@ 0xE000E408) Interrupt Priority Register 2 */
\r
380 __IO uint32_t NVIC_IPR3; /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */
\r
381 __IO uint32_t NVIC_IPR4; /*!< (@ 0xE000E410) Interrupt Priority Register 4 */
\r
382 __IO uint32_t NVIC_IPR5; /*!< (@ 0xE000E414) Interrupt Priority Register 5 */
\r
383 __IO uint32_t NVIC_IPR6; /*!< (@ 0xE000E418) Interrupt Priority Register 6 */
\r
384 __IO uint32_t NVIC_IPR7; /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */
\r
385 __IO uint32_t NVIC_IPR8; /*!< (@ 0xE000E420) Interrupt Priority Register 8 */
\r
386 __IO uint32_t NVIC_IPR9; /*!< (@ 0xE000E424) Interrupt Priority Register 9 */
\r
387 __IO uint32_t NVIC_IPR10; /*!< (@ 0xE000E428) Interrupt Priority Register 10 */
\r
388 __IO uint32_t NVIC_IPR11; /*!< (@ 0xE000E42C) Interrupt Priority Register 11 */
\r
389 __IO uint32_t NVIC_IPR12; /*!< (@ 0xE000E430) Interrupt Priority Register 12 */
\r
390 __IO uint32_t NVIC_IPR13; /*!< (@ 0xE000E434) Interrupt Priority Register 13 */
\r
391 __IO uint32_t NVIC_IPR14; /*!< (@ 0xE000E438) Interrupt Priority Register 14 */
\r
392 __IO uint32_t NVIC_IPR15; /*!< (@ 0xE000E43C) Interrupt Priority Register 15 */
\r
393 __IO uint32_t NVIC_IPR16; /*!< (@ 0xE000E440) Interrupt Priority Register 16 */
\r
394 __IO uint32_t NVIC_IPR17; /*!< (@ 0xE000E444) Interrupt Priority Register 17 */
\r
395 __IO uint32_t NVIC_IPR18; /*!< (@ 0xE000E448) Interrupt Priority Register 18 */
\r
396 __IO uint32_t NVIC_IPR19; /*!< (@ 0xE000E44C) Interrupt Priority Register 19 */
\r
397 __IO uint32_t NVIC_IPR20; /*!< (@ 0xE000E450) Interrupt Priority Register 20 */
\r
398 __IO uint32_t NVIC_IPR21; /*!< (@ 0xE000E454) Interrupt Priority Register 21 */
\r
399 __IO uint32_t NVIC_IPR22; /*!< (@ 0xE000E458) Interrupt Priority Register 22 */
\r
400 __IO uint32_t NVIC_IPR23; /*!< (@ 0xE000E45C) Interrupt Priority Register 23 */
\r
401 __IO uint32_t NVIC_IPR24; /*!< (@ 0xE000E460) Interrupt Priority Register 24 */
\r
402 __IO uint32_t NVIC_IPR25; /*!< (@ 0xE000E464) Interrupt Priority Register 25 */
\r
403 __IO uint32_t NVIC_IPR26; /*!< (@ 0xE000E468) Interrupt Priority Register 26 */
\r
404 __IO uint32_t NVIC_IPR27; /*!< (@ 0xE000E46C) Interrupt Priority Register 27 */
\r
405 __I uint32_t RESERVED8[548];
\r
406 __I uint32_t CPUID; /*!< (@ 0xE000ED00) CPUID Base Register */
\r
407 __IO uint32_t ICSR; /*!< (@ 0xE000ED04) Interrupt Control and State Register */
\r
408 __IO uint32_t VTOR; /*!< (@ 0xE000ED08) Vector Table Offset Register */
\r
409 __IO uint32_t AIRCR; /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */
\r
410 __IO uint32_t SCR; /*!< (@ 0xE000ED10) System Control Register */
\r
411 __IO uint32_t CCR; /*!< (@ 0xE000ED14) Configuration and Control Register */
\r
412 __IO uint32_t SHPR1; /*!< (@ 0xE000ED18) System Handler Priority Register 1 */
\r
413 __IO uint32_t SHPR2; /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */
\r
414 __IO uint32_t SHPR3; /*!< (@ 0xE000ED20) System Handler Priority Register 3 */
\r
415 __IO uint32_t SHCSR; /*!< (@ 0xE000ED24) System Handler Control and State Register */
\r
416 __IO uint32_t CFSR; /*!< (@ 0xE000ED28) Configurable Fault Status Register */
\r
417 __IO uint32_t HFSR; /*!< (@ 0xE000ED2C) HardFault Status Register */
\r
418 __I uint32_t RESERVED9;
\r
419 __IO uint32_t MMFAR; /*!< (@ 0xE000ED34) MemManage Fault Address Register */
\r
420 __IO uint32_t BFAR; /*!< (@ 0xE000ED38) BusFault Address Register */
\r
421 __IO uint32_t AFSR; /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register */
\r
422 __I uint32_t RESERVED10[18];
\r
423 __IO uint32_t CPACR; /*!< (@ 0xE000ED88) Coprocessor Access Control Register */
\r
424 __I uint32_t RESERVED11;
\r
425 __I uint32_t MPU_TYPE; /*!< (@ 0xE000ED90) MPU Type Register */
\r
426 __IO uint32_t MPU_CTRL; /*!< (@ 0xE000ED94) MPU Control Register */
\r
427 __IO uint32_t MPU_RNR; /*!< (@ 0xE000ED98) MPU Region Number Register */
\r
428 __IO uint32_t MPU_RBAR; /*!< (@ 0xE000ED9C) MPU Region Base Address Register */
\r
429 __IO uint32_t MPU_RASR; /*!< (@ 0xE000EDA0) MPU Region Attribute and Size Register */
\r
430 __IO uint32_t MPU_RBAR_A1; /*!< (@ 0xE000EDA4) MPU Region Base Address Register A1 */
\r
431 __IO uint32_t MPU_RASR_A1; /*!< (@ 0xE000EDA8) MPU Region Attribute and Size Register A1 */
\r
432 __IO uint32_t MPU_RBAR_A2; /*!< (@ 0xE000EDAC) MPU Region Base Address Register A2 */
\r
433 __IO uint32_t MPU_RASR_A2; /*!< (@ 0xE000EDB0) MPU Region Attribute and Size Register A2 */
\r
434 __IO uint32_t MPU_RBAR_A3; /*!< (@ 0xE000EDB4) MPU Region Base Address Register A3 */
\r
435 __IO uint32_t MPU_RASR_A3; /*!< (@ 0xE000EDB8) MPU Region Attribute and Size Register A3 */
\r
436 __I uint32_t RESERVED12[81];
\r
437 __O uint32_t STIR; /*!< (@ 0xE000EF00) Software Trigger Interrupt Register */
\r
438 __I uint32_t RESERVED13[12];
\r
439 __IO uint32_t FPCCR; /*!< (@ 0xE000EF34) Floating-point Context Control Register */
\r
440 __IO uint32_t FPCAR; /*!< (@ 0xE000EF38) Floating-point Context Address Register */
\r
441 __IO uint32_t FPDSCR; /*!< (@ 0xE000EF3C) Floating-point Default Status Control Register */
\r
445 /* ================================================================================ */
\r
446 /* ================ DLR ================ */
\r
447 /* ================================================================================ */
\r
451 * @brief DMA Line Router (DLR)
\r
454 typedef struct { /*!< (@ 0x50004900) DLR Structure */
\r
455 __I uint32_t OVRSTAT; /*!< (@ 0x50004900) Overrun Status */
\r
456 __O uint32_t OVRCLR; /*!< (@ 0x50004904) Overrun Clear */
\r
457 __IO uint32_t SRSEL0; /*!< (@ 0x50004908) Service Request Selection 0 */
\r
458 __I uint32_t RESERVED0;
\r
459 __IO uint32_t LNEN; /*!< (@ 0x50004910) Line Enable */
\r
460 } DLR_GLOBAL_TypeDef;
\r
463 /* ================================================================================ */
\r
464 /* ================ ERU [ERU0] ================ */
\r
465 /* ================================================================================ */
\r
469 * @brief Event Request Unit 0 (ERU)
\r
472 typedef struct { /*!< (@ 0x50004800) ERU Structure */
\r
473 __IO uint32_t EXISEL; /*!< (@ 0x50004800) Event Input Select */
\r
474 __I uint32_t RESERVED0[3];
\r
475 __IO uint32_t EXICON[4]; /*!< (@ 0x50004810) Event Input Control */
\r
476 __IO uint32_t EXOCON[4]; /*!< (@ 0x50004820) Event Output Trigger Control */
\r
477 } ERU_GLOBAL_TypeDef;
\r
480 /* ================================================================================ */
\r
481 /* ================ GPDMA0 ================ */
\r
482 /* ================================================================================ */
\r
486 * @brief General Purpose DMA Unit 0 (GPDMA0)
\r
489 typedef struct { /*!< (@ 0x500142C0) GPDMA0 Structure */
\r
490 __IO uint32_t RAWTFR; /*!< (@ 0x500142C0) Raw IntTfr Status */
\r
491 __I uint32_t RESERVED0;
\r
492 __IO uint32_t RAWBLOCK; /*!< (@ 0x500142C8) Raw IntBlock Status */
\r
493 __I uint32_t RESERVED1;
\r
494 __IO uint32_t RAWSRCTRAN; /*!< (@ 0x500142D0) Raw IntSrcTran Status */
\r
495 __I uint32_t RESERVED2;
\r
496 __IO uint32_t RAWDSTTRAN; /*!< (@ 0x500142D8) Raw IntBlock Status */
\r
497 __I uint32_t RESERVED3;
\r
498 __IO uint32_t RAWERR; /*!< (@ 0x500142E0) Raw IntErr Status */
\r
499 __I uint32_t RESERVED4;
\r
500 __I uint32_t STATUSTFR; /*!< (@ 0x500142E8) IntTfr Status */
\r
501 __I uint32_t RESERVED5;
\r
502 __I uint32_t STATUSBLOCK; /*!< (@ 0x500142F0) IntBlock Status */
\r
503 __I uint32_t RESERVED6;
\r
504 __I uint32_t STATUSSRCTRAN; /*!< (@ 0x500142F8) IntSrcTran Status */
\r
505 __I uint32_t RESERVED7;
\r
506 __I uint32_t STATUSDSTTRAN; /*!< (@ 0x50014300) IntBlock Status */
\r
507 __I uint32_t RESERVED8;
\r
508 __I uint32_t STATUSERR; /*!< (@ 0x50014308) IntErr Status */
\r
509 __I uint32_t RESERVED9;
\r
510 __IO uint32_t MASKTFR; /*!< (@ 0x50014310) Mask for Raw IntTfr Status */
\r
511 __I uint32_t RESERVED10;
\r
512 __IO uint32_t MASKBLOCK; /*!< (@ 0x50014318) Mask for Raw IntBlock Status */
\r
513 __I uint32_t RESERVED11;
\r
514 __IO uint32_t MASKSRCTRAN; /*!< (@ 0x50014320) Mask for Raw IntSrcTran Status */
\r
515 __I uint32_t RESERVED12;
\r
516 __IO uint32_t MASKDSTTRAN; /*!< (@ 0x50014328) Mask for Raw IntBlock Status */
\r
517 __I uint32_t RESERVED13;
\r
518 __IO uint32_t MASKERR; /*!< (@ 0x50014330) Mask for Raw IntErr Status */
\r
519 __I uint32_t RESERVED14;
\r
520 __O uint32_t CLEARTFR; /*!< (@ 0x50014338) IntTfr Status */
\r
521 __I uint32_t RESERVED15;
\r
522 __O uint32_t CLEARBLOCK; /*!< (@ 0x50014340) IntBlock Status */
\r
523 __I uint32_t RESERVED16;
\r
524 __O uint32_t CLEARSRCTRAN; /*!< (@ 0x50014348) IntSrcTran Status */
\r
525 __I uint32_t RESERVED17;
\r
526 __O uint32_t CLEARDSTTRAN; /*!< (@ 0x50014350) IntBlock Status */
\r
527 __I uint32_t RESERVED18;
\r
528 __O uint32_t CLEARERR; /*!< (@ 0x50014358) IntErr Status */
\r
529 __I uint32_t RESERVED19;
\r
530 __I uint32_t STATUSINT; /*!< (@ 0x50014360) Combined Interrupt Status Register */
\r
531 __I uint32_t RESERVED20;
\r
532 __IO uint32_t REQSRCREG; /*!< (@ 0x50014368) Source Software Transaction Request Register */
\r
533 __I uint32_t RESERVED21;
\r
534 __IO uint32_t REQDSTREG; /*!< (@ 0x50014370) Destination Software Transaction Request Register */
\r
535 __I uint32_t RESERVED22;
\r
536 __IO uint32_t SGLREQSRCREG; /*!< (@ 0x50014378) Single Source Transaction Request Register */
\r
537 __I uint32_t RESERVED23;
\r
538 __IO uint32_t SGLREQDSTREG; /*!< (@ 0x50014380) Single Destination Transaction Request Register */
\r
539 __I uint32_t RESERVED24;
\r
540 __IO uint32_t LSTSRCREG; /*!< (@ 0x50014388) Last Source Transaction Request Register */
\r
541 __I uint32_t RESERVED25;
\r
542 __IO uint32_t LSTDSTREG; /*!< (@ 0x50014390) Last Destination Transaction Request Register */
\r
543 __I uint32_t RESERVED26;
\r
544 __IO uint32_t DMACFGREG; /*!< (@ 0x50014398) GPDMA Configuration Register */
\r
545 __I uint32_t RESERVED27;
\r
546 __IO uint32_t CHENREG; /*!< (@ 0x500143A0) GPDMA Channel Enable Register */
\r
547 __I uint32_t RESERVED28;
\r
548 __I uint32_t ID; /*!< (@ 0x500143A8) GPDMA0 ID Register */
\r
549 __I uint32_t RESERVED29[19];
\r
550 __I uint32_t TYPE; /*!< (@ 0x500143F8) GPDMA Component Type */
\r
551 __I uint32_t VERSION; /*!< (@ 0x500143FC) DMA Component Version */
\r
552 } GPDMA0_GLOBAL_TypeDef;
\r
555 /* ================================================================================ */
\r
556 /* ================ GPDMA0_CH0_1 [GPDMA0_CH0] ================ */
\r
557 /* ================================================================================ */
\r
561 * @brief General Purpose DMA Unit 0 (GPDMA0_CH0_1)
\r
564 typedef struct { /*!< (@ 0x50014000) GPDMA0_CH0_1 Structure */
\r
565 __IO uint32_t SAR; /*!< (@ 0x50014000) Source Address Register */
\r
566 __I uint32_t RESERVED0;
\r
567 __IO uint32_t DAR; /*!< (@ 0x50014008) Destination Address Register */
\r
568 __I uint32_t RESERVED1;
\r
569 __IO uint32_t LLP; /*!< (@ 0x50014010) Linked List Pointer Register */
\r
570 __I uint32_t RESERVED2;
\r
571 __IO uint32_t CTLL; /*!< (@ 0x50014018) Control Register Low */
\r
572 __IO uint32_t CTLH; /*!< (@ 0x5001401C) Control Register High */
\r
573 __IO uint32_t SSTAT; /*!< (@ 0x50014020) Source Status Register */
\r
574 __I uint32_t RESERVED3;
\r
575 __IO uint32_t DSTAT; /*!< (@ 0x50014028) Destination Status Register */
\r
576 __I uint32_t RESERVED4;
\r
577 __IO uint32_t SSTATAR; /*!< (@ 0x50014030) Source Status Address Register */
\r
578 __I uint32_t RESERVED5;
\r
579 __IO uint32_t DSTATAR; /*!< (@ 0x50014038) Destination Status Address Register */
\r
580 __I uint32_t RESERVED6;
\r
581 __IO uint32_t CFGL; /*!< (@ 0x50014040) Configuration Register Low */
\r
582 __IO uint32_t CFGH; /*!< (@ 0x50014044) Configuration Register High */
\r
583 __IO uint32_t SGR; /*!< (@ 0x50014048) Source Gather Register */
\r
584 __I uint32_t RESERVED7;
\r
585 __IO uint32_t DSR; /*!< (@ 0x50014050) Destination Scatter Register */
\r
586 } GPDMA0_CH_TypeDef;
\r
589 /* ================================================================================ */
\r
590 /* ================ GPDMA0_CH2_7 [GPDMA0_CH2] ================ */
\r
591 /* ================================================================================ */
\r
595 * @brief General Purpose DMA Unit 0 (GPDMA0_CH2_7)
\r
598 typedef struct { /*!< (@ 0x500140B0) GPDMA0_CH2_7 Structure */
\r
599 __IO uint32_t SAR; /*!< (@ 0x500140B0) Source Address Register */
\r
600 __I uint32_t RESERVED0;
\r
601 __IO uint32_t DAR; /*!< (@ 0x500140B8) Destination Address Register */
\r
602 __I uint32_t RESERVED1[3];
\r
603 __IO uint32_t CTLL; /*!< (@ 0x500140C8) Control Register Low */
\r
604 __IO uint32_t CTLH; /*!< (@ 0x500140CC) Control Register High */
\r
605 __I uint32_t RESERVED2[8];
\r
606 __IO uint32_t CFGL; /*!< (@ 0x500140F0) Configuration Register Low */
\r
607 __IO uint32_t CFGH; /*!< (@ 0x500140F4) Configuration Register High */
\r
608 } GPDMA0_CH2_7_Type;
\r
611 /* ================================================================================ */
\r
612 /* ================ FCE ================ */
\r
613 /* ================================================================================ */
\r
617 * @brief Flexible CRC Engine (FCE)
\r
620 typedef struct { /*!< (@ 0x50020000) FCE Structure */
\r
621 __IO uint32_t CLC; /*!< (@ 0x50020000) Clock Control Register */
\r
622 __I uint32_t RESERVED0;
\r
623 __I uint32_t ID; /*!< (@ 0x50020008) Module Identification Register */
\r
624 } FCE_GLOBAL_TypeDef;
\r
627 /* ================================================================================ */
\r
628 /* ================ FCE_KE [FCE_KE0] ================ */
\r
629 /* ================================================================================ */
\r
633 * @brief Flexible CRC Engine (FCE_KE)
\r
636 typedef struct { /*!< (@ 0x50020020) FCE_KE Structure */
\r
637 __IO uint32_t IR; /*!< (@ 0x50020020) Input Register */
\r
638 __I uint32_t RES; /*!< (@ 0x50020024) CRC Result Register */
\r
639 __IO uint32_t CFG; /*!< (@ 0x50020028) CRC Configuration Register */
\r
640 __IO uint32_t STS; /*!< (@ 0x5002002C) CRC Status Register */
\r
641 __IO uint32_t LENGTH; /*!< (@ 0x50020030) CRC Length Register */
\r
642 __IO uint32_t CHECK; /*!< (@ 0x50020034) CRC Check Register */
\r
643 __IO uint32_t CRC; /*!< (@ 0x50020038) CRC Register */
\r
644 __IO uint32_t CTR; /*!< (@ 0x5002003C) CRC Test Register */
\r
648 /* ================================================================================ */
\r
649 /* ================ PBA [PBA0] ================ */
\r
650 /* ================================================================================ */
\r
654 * @brief Peripheral Bridge AHB 0 (PBA)
\r
657 typedef struct { /*!< (@ 0x40000000) PBA Structure */
\r
658 __IO uint32_t STS; /*!< (@ 0x40000000) Peripheral Bridge Status Register */
\r
659 __I uint32_t WADDR; /*!< (@ 0x40000004) PBA Write Error Address Register */
\r
660 } PBA_GLOBAL_TypeDef;
\r
663 /* ================================================================================ */
\r
664 /* ================ FLASH [FLASH0] ================ */
\r
665 /* ================================================================================ */
\r
669 * @brief Flash Memory Controller (FLASH)
\r
672 typedef struct { /*!< (@ 0x58001000) FLASH Structure */
\r
673 __I uint32_t RESERVED0[1026];
\r
674 __I uint32_t ID; /*!< (@ 0x58002008) Flash Module Identification Register */
\r
675 __I uint32_t RESERVED1;
\r
676 __I uint32_t FSR; /*!< (@ 0x58002010) Flash Status Register */
\r
677 __IO uint32_t FCON; /*!< (@ 0x58002014) Flash Configuration Register */
\r
678 __IO uint32_t MARP; /*!< (@ 0x58002018) Margin Control Register PFLASH */
\r
679 __I uint32_t RESERVED2;
\r
680 __I uint32_t PROCON0; /*!< (@ 0x58002020) Flash Protection Configuration Register User
\r
682 __I uint32_t PROCON1; /*!< (@ 0x58002024) Flash Protection Configuration Register User
\r
684 __I uint32_t PROCON2; /*!< (@ 0x58002028) Flash Protection Configuration Register User
\r
686 } FLASH0_GLOBAL_TypeDef;
\r
689 /* ================================================================================ */
\r
690 /* ================ PREF ================ */
\r
691 /* ================================================================================ */
\r
695 * @brief Prefetch Unit (PREF)
\r
698 typedef struct { /*!< (@ 0x58004000) PREF Structure */
\r
699 __IO uint32_t PCON; /*!< (@ 0x58004000) Prefetch Configuration Register */
\r
700 } PREF_GLOBAL_TypeDef;
\r
703 /* ================================================================================ */
\r
704 /* ================ PMU [PMU0] ================ */
\r
705 /* ================================================================================ */
\r
709 * @brief Program Management Unit (PMU)
\r
712 typedef struct { /*!< (@ 0x58000508) PMU Structure */
\r
713 __I uint32_t ID; /*!< (@ 0x58000508) PMU0 Identification Register */
\r
714 } PMU0_GLOBAL_TypeDef;
\r
717 /* ================================================================================ */
\r
718 /* ================ WDT ================ */
\r
719 /* ================================================================================ */
\r
723 * @brief Watch Dog Timer (WDT)
\r
726 typedef struct { /*!< (@ 0x50008000) WDT Structure */
\r
727 __I uint32_t ID; /*!< (@ 0x50008000) WDT ID Register */
\r
728 __IO uint32_t CTR; /*!< (@ 0x50008004) WDT Control Register */
\r
729 __O uint32_t SRV; /*!< (@ 0x50008008) WDT Service Register */
\r
730 __I uint32_t TIM; /*!< (@ 0x5000800C) WDT Timer Register */
\r
731 __IO uint32_t WLB; /*!< (@ 0x50008010) WDT Window Lower Bound Register */
\r
732 __IO uint32_t WUB; /*!< (@ 0x50008014) WDT Window Upper Bound Register */
\r
733 __I uint32_t WDTSTS; /*!< (@ 0x50008018) WDT Status Register */
\r
734 __O uint32_t WDTCLR; /*!< (@ 0x5000801C) WDT Clear Register */
\r
735 } WDT_GLOBAL_TypeDef;
\r
738 /* ================================================================================ */
\r
739 /* ================ RTC ================ */
\r
740 /* ================================================================================ */
\r
744 * @brief Real Time Clock (RTC)
\r
747 typedef struct { /*!< (@ 0x50004A00) RTC Structure */
\r
748 __I uint32_t ID; /*!< (@ 0x50004A00) RTC ID Register */
\r
749 __IO uint32_t CTR; /*!< (@ 0x50004A04) RTC Control Register */
\r
750 __I uint32_t RAWSTAT; /*!< (@ 0x50004A08) RTC Raw Service Request Register */
\r
751 __I uint32_t STSSR; /*!< (@ 0x50004A0C) RTC Service Request Status Register */
\r
752 __IO uint32_t MSKSR; /*!< (@ 0x50004A10) RTC Service Request Mask Register */
\r
753 __O uint32_t CLRSR; /*!< (@ 0x50004A14) RTC Clear Service Request Register */
\r
754 __IO uint32_t ATIM0; /*!< (@ 0x50004A18) RTC Alarm Time Register 0 */
\r
755 __IO uint32_t ATIM1; /*!< (@ 0x50004A1C) RTC Alarm Time Register 1 */
\r
756 __IO uint32_t TIM0; /*!< (@ 0x50004A20) RTC Time Register 0 */
\r
757 __IO uint32_t TIM1; /*!< (@ 0x50004A24) RTC Time Register 1 */
\r
758 } RTC_GLOBAL_TypeDef;
\r
761 /* ================================================================================ */
\r
762 /* ================ SCU_CLK ================ */
\r
763 /* ================================================================================ */
\r
767 * @brief System Control Unit (SCU_CLK)
\r
770 typedef struct { /*!< (@ 0x50004600) SCU_CLK Structure */
\r
771 __I uint32_t CLKSTAT; /*!< (@ 0x50004600) Clock Status Register */
\r
772 __O uint32_t CLKSET; /*!< (@ 0x50004604) CLK Set Register */
\r
773 __O uint32_t CLKCLR; /*!< (@ 0x50004608) CLK Clear Register */
\r
774 __IO uint32_t SYSCLKCR; /*!< (@ 0x5000460C) System Clock Control Register */
\r
775 __IO uint32_t CPUCLKCR; /*!< (@ 0x50004610) CPU Clock Control Register */
\r
776 __IO uint32_t PBCLKCR; /*!< (@ 0x50004614) Peripheral Bus Clock Control Register */
\r
777 __IO uint32_t USBCLKCR; /*!< (@ 0x50004618) USB Clock Control Register */
\r
778 __I uint32_t RESERVED0;
\r
779 __IO uint32_t CCUCLKCR; /*!< (@ 0x50004620) CCU Clock Control Register */
\r
780 __IO uint32_t WDTCLKCR; /*!< (@ 0x50004624) WDT Clock Control Register */
\r
781 __IO uint32_t EXTCLKCR; /*!< (@ 0x50004628) External Clock Control */
\r
782 __IO uint32_t MLINKCLKCR; /*!< (@ 0x5000462C) Multi-Link Clock Control */
\r
783 __IO uint32_t SLEEPCR; /*!< (@ 0x50004630) Sleep Control Register */
\r
784 __IO uint32_t DSLEEPCR; /*!< (@ 0x50004634) Deep Sleep Control Register */
\r
785 __I uint32_t RESERVED1[2];
\r
786 __I uint32_t CGATSTAT0; /*!< (@ 0x50004640) Peripheral 0 Clock Gating Status */
\r
787 __O uint32_t CGATSET0; /*!< (@ 0x50004644) Peripheral 0 Clock Gating Set */
\r
788 __O uint32_t CGATCLR0; /*!< (@ 0x50004648) Peripheral 0 Clock Gating Clear */
\r
789 __I uint32_t CGATSTAT1; /*!< (@ 0x5000464C) Peripheral 1 Clock Gating Status */
\r
790 __O uint32_t CGATSET1; /*!< (@ 0x50004650) Peripheral 1 Clock Gating Set */
\r
791 __O uint32_t CGATCLR1; /*!< (@ 0x50004654) Peripheral 1 Clock Gating Clear */
\r
792 __I uint32_t CGATSTAT2; /*!< (@ 0x50004658) Peripheral 2 Clock Gating Status */
\r
793 __O uint32_t CGATSET2; /*!< (@ 0x5000465C) Peripheral 2 Clock Gating Set */
\r
794 __O uint32_t CGATCLR2; /*!< (@ 0x50004660) Peripheral 2 Clock Gating Clear */
\r
798 /* ================================================================================ */
\r
799 /* ================ SCU_OSC ================ */
\r
800 /* ================================================================================ */
\r
804 * @brief System Control Unit (SCU_OSC)
\r
807 typedef struct { /*!< (@ 0x50004700) SCU_OSC Structure */
\r
808 __I uint32_t OSCHPSTAT; /*!< (@ 0x50004700) OSC_HP Status Register */
\r
809 __IO uint32_t OSCHPCTRL; /*!< (@ 0x50004704) OSC_HP Control Register */
\r
810 __I uint32_t RESERVED0;
\r
811 __IO uint32_t CLKCALCONST; /*!< (@ 0x5000470C) Clock Calibration Constant Register */
\r
815 /* ================================================================================ */
\r
816 /* ================ SCU_PLL ================ */
\r
817 /* ================================================================================ */
\r
821 * @brief System Control Unit (SCU_PLL)
\r
824 typedef struct { /*!< (@ 0x50004710) SCU_PLL Structure */
\r
825 __I uint32_t PLLSTAT; /*!< (@ 0x50004710) PLL Status Register */
\r
826 __IO uint32_t PLLCON0; /*!< (@ 0x50004714) PLL Configuration 0 Register */
\r
827 __IO uint32_t PLLCON1; /*!< (@ 0x50004718) PLL Configuration 1 Register */
\r
828 __IO uint32_t PLLCON2; /*!< (@ 0x5000471C) PLL Configuration 2 Register */
\r
829 __I uint32_t USBPLLSTAT; /*!< (@ 0x50004720) USB PLL Status Register */
\r
830 __IO uint32_t USBPLLCON; /*!< (@ 0x50004724) USB PLL Configuration Register */
\r
831 __I uint32_t RESERVED0[4];
\r
832 __I uint32_t CLKMXSTAT; /*!< (@ 0x50004738) Clock Multiplexing Status Register */
\r
836 /* ================================================================================ */
\r
837 /* ================ SCU_GENERAL ================ */
\r
838 /* ================================================================================ */
\r
842 * @brief System Control Unit (SCU_GENERAL)
\r
845 typedef struct { /*!< (@ 0x50004000) SCU_GENERAL Structure */
\r
846 __I uint32_t ID; /*!< (@ 0x50004000) SCU Module ID Register */
\r
847 __I uint32_t IDCHIP; /*!< (@ 0x50004004) Chip ID Register */
\r
848 __I uint32_t IDMANUF; /*!< (@ 0x50004008) Manufactory ID Register */
\r
849 __I uint32_t RESERVED0;
\r
850 __IO uint32_t STCON; /*!< (@ 0x50004010) Startup Configuration Register */
\r
851 __I uint32_t RESERVED1[6];
\r
852 __IO uint32_t GPR[2]; /*!< (@ 0x5000402C) General Purpose Register 0 */
\r
853 __I uint32_t RESERVED2[6];
\r
854 __IO uint32_t CCUCON; /*!< (@ 0x5000404C) CCU Control Register */
\r
855 __I uint32_t RESERVED3[15];
\r
856 __IO uint32_t DTSCON; /*!< (@ 0x5000408C) Die Temperature Sensor Control Register */
\r
857 __I uint32_t DTSSTAT; /*!< (@ 0x50004090) Die Temperature Sensor Status Register */
\r
858 __I uint32_t RESERVED4[3];
\r
859 __IO uint32_t GORCEN[2]; /*!< (@ 0x500040A0) Out of Range Comparator Enable Register 0 */
\r
860 __IO uint32_t DTEMPLIM; /*!< (@ 0x500040A8) Die Temperature Sensor Limit Register */
\r
861 __I uint32_t DTEMPALARM; /*!< (@ 0x500040AC) Die Temperature Sensor Alarm Register */
\r
862 __I uint32_t RESERVED5[5];
\r
863 __I uint32_t MIRRSTS; /*!< (@ 0x500040C4) Mirror Write Status Register */
\r
864 __IO uint32_t RMACR; /*!< (@ 0x500040C8) Retention Memory Access Control Register */
\r
865 __IO uint32_t RMDATA; /*!< (@ 0x500040CC) Retention Memory Access Data Register */
\r
866 __I uint32_t MIRRALLSTAT; /*!< (@ 0x500040D0) Mirror All Status */
\r
867 __O uint32_t MIRRALLREQ; /*!< (@ 0x500040D4) Mirror All Request */
\r
868 } SCU_GENERAL_TypeDef;
\r
871 /* ================================================================================ */
\r
872 /* ================ SCU_INTERRUPT ================ */
\r
873 /* ================================================================================ */
\r
877 * @brief System Control Unit (SCU_INTERRUPT)
\r
880 typedef struct { /*!< (@ 0x50004074) SCU_INTERRUPT Structure */
\r
881 __I uint32_t SRSTAT; /*!< (@ 0x50004074) SCU Service Request Status */
\r
882 __I uint32_t SRRAW; /*!< (@ 0x50004078) SCU Raw Service Request Status */
\r
883 __IO uint32_t SRMSK; /*!< (@ 0x5000407C) SCU Service Request Mask */
\r
884 __O uint32_t SRCLR; /*!< (@ 0x50004080) SCU Service Request Clear */
\r
885 __O uint32_t SRSET; /*!< (@ 0x50004084) SCU Service Request Set */
\r
886 __IO uint32_t NMIREQEN; /*!< (@ 0x50004088) SCU Service Request Mask */
\r
887 } SCU_INTERRUPT_TypeDef;
\r
890 /* ================================================================================ */
\r
891 /* ================ SCU_PARITY ================ */
\r
892 /* ================================================================================ */
\r
896 * @brief System Control Unit (SCU_PARITY)
\r
899 typedef struct { /*!< (@ 0x5000413C) SCU_PARITY Structure */
\r
900 __IO uint32_t PEEN; /*!< (@ 0x5000413C) Parity Error Enable Register */
\r
901 __IO uint32_t MCHKCON; /*!< (@ 0x50004140) Memory Checking Control Register */
\r
902 __IO uint32_t PETE; /*!< (@ 0x50004144) Parity Error Trap Enable Register */
\r
903 __IO uint32_t PERSTEN; /*!< (@ 0x50004148) Parity Error Reset Enable Register */
\r
904 __I uint32_t RESERVED0;
\r
905 __IO uint32_t PEFLAG; /*!< (@ 0x50004150) Parity Error Flag Register */
\r
906 __IO uint32_t PMTPR; /*!< (@ 0x50004154) Parity Memory Test Pattern Register */
\r
907 __IO uint32_t PMTSR; /*!< (@ 0x50004158) Parity Memory Test Select Register */
\r
908 } SCU_PARITY_TypeDef;
\r
911 /* ================================================================================ */
\r
912 /* ================ SCU_TRAP ================ */
\r
913 /* ================================================================================ */
\r
917 * @brief System Control Unit (SCU_TRAP)
\r
920 typedef struct { /*!< (@ 0x50004160) SCU_TRAP Structure */
\r
921 __I uint32_t TRAPSTAT; /*!< (@ 0x50004160) Trap Status Register */
\r
922 __I uint32_t TRAPRAW; /*!< (@ 0x50004164) Trap Raw Status Register */
\r
923 __IO uint32_t TRAPDIS; /*!< (@ 0x50004168) Trap Disable Register */
\r
924 __O uint32_t TRAPCLR; /*!< (@ 0x5000416C) Trap Clear Register */
\r
925 __O uint32_t TRAPSET; /*!< (@ 0x50004170) Trap Set Register */
\r
926 } SCU_TRAP_TypeDef;
\r
929 /* ================================================================================ */
\r
930 /* ================ SCU_HIBERNATE ================ */
\r
931 /* ================================================================================ */
\r
935 * @brief System Control Unit (SCU_HIBERNATE)
\r
938 typedef struct { /*!< (@ 0x50004300) SCU_HIBERNATE Structure */
\r
939 __I uint32_t HDSTAT; /*!< (@ 0x50004300) Hibernate Domain Status Register */
\r
940 __O uint32_t HDCLR; /*!< (@ 0x50004304) Hibernate Domain Status Clear Register */
\r
941 __O uint32_t HDSET; /*!< (@ 0x50004308) Hibernate Domain Status Set Register */
\r
942 __IO uint32_t HDCR; /*!< (@ 0x5000430C) Hibernate Domain Control Register */
\r
943 __I uint32_t RESERVED0;
\r
944 __IO uint32_t OSCSICTRL; /*!< (@ 0x50004314) fOSI Control Register */
\r
945 __I uint32_t OSCULSTAT; /*!< (@ 0x50004318) OSC_ULP Status Register */
\r
946 __IO uint32_t OSCULCTRL; /*!< (@ 0x5000431C) OSC_ULP Control Register */
\r
947 __IO uint32_t LPACCONF; /*!< (@ 0x50004320) Analog Wake-up Configuration Register */
\r
948 __IO uint32_t LPACTH0; /*!< (@ 0x50004324) LPAC Threshold Register 0 */
\r
949 __IO uint32_t LPACTH1; /*!< (@ 0x50004328) LPAC Threshold Register 1 */
\r
950 __I uint32_t LPACST; /*!< (@ 0x5000432C) Hibernate Analog Control State Register */
\r
951 __O uint32_t LPACCLR; /*!< (@ 0x50004330) LPAC Control Clear Register */
\r
952 __O uint32_t LPACSET; /*!< (@ 0x50004334) LPAC Control Set Register */
\r
953 __I uint32_t HINTST; /*!< (@ 0x50004338) Hibernate Internal Control State Register */
\r
954 __O uint32_t HINTCLR; /*!< (@ 0x5000433C) Hibernate Internal Control Clear Register */
\r
955 __O uint32_t HINTSET; /*!< (@ 0x50004340) Hibernate Internal Control Set Register */
\r
956 } SCU_HIBERNATE_TypeDef;
\r
959 /* ================================================================================ */
\r
960 /* ================ SCU_POWER ================ */
\r
961 /* ================================================================================ */
\r
965 * @brief System Control Unit (SCU_POWER)
\r
968 typedef struct { /*!< (@ 0x50004200) SCU_POWER Structure */
\r
969 __I uint32_t PWRSTAT; /*!< (@ 0x50004200) PCU Status Register */
\r
970 __O uint32_t PWRSET; /*!< (@ 0x50004204) PCU Set Control Register */
\r
971 __O uint32_t PWRCLR; /*!< (@ 0x50004208) PCU Clear Control Register */
\r
972 __I uint32_t RESERVED0;
\r
973 __I uint32_t EVRSTAT; /*!< (@ 0x50004210) EVR Status Register */
\r
974 __I uint32_t EVRVADCSTAT; /*!< (@ 0x50004214) EVR VADC Status Register */
\r
975 __I uint32_t RESERVED1[5];
\r
976 __IO uint32_t PWRMON; /*!< (@ 0x5000422C) Power Monitor Control */
\r
977 } SCU_POWER_TypeDef;
\r
980 /* ================================================================================ */
\r
981 /* ================ SCU_RESET ================ */
\r
982 /* ================================================================================ */
\r
986 * @brief System Control Unit (SCU_RESET)
\r
989 typedef struct { /*!< (@ 0x50004400) SCU_RESET Structure */
\r
990 __I uint32_t RSTSTAT; /*!< (@ 0x50004400) RCU Reset Status */
\r
991 __O uint32_t RSTSET; /*!< (@ 0x50004404) RCU Reset Set Register */
\r
992 __O uint32_t RSTCLR; /*!< (@ 0x50004408) RCU Reset Clear Register */
\r
993 __I uint32_t PRSTAT0; /*!< (@ 0x5000440C) RCU Peripheral 0 Reset Status */
\r
994 __O uint32_t PRSET0; /*!< (@ 0x50004410) RCU Peripheral 0 Reset Set */
\r
995 __O uint32_t PRCLR0; /*!< (@ 0x50004414) RCU Peripheral 0 Reset Clear */
\r
996 __I uint32_t PRSTAT1; /*!< (@ 0x50004418) RCU Peripheral 1 Reset Status */
\r
997 __O uint32_t PRSET1; /*!< (@ 0x5000441C) RCU Peripheral 1 Reset Set */
\r
998 __O uint32_t PRCLR1; /*!< (@ 0x50004420) RCU Peripheral 1 Reset Clear */
\r
999 __I uint32_t PRSTAT2; /*!< (@ 0x50004424) RCU Peripheral 2 Reset Status */
\r
1000 __O uint32_t PRSET2; /*!< (@ 0x50004428) RCU Peripheral 2 Reset Set */
\r
1001 __O uint32_t PRCLR2; /*!< (@ 0x5000442C) RCU Peripheral 2 Reset Clear */
\r
1002 } SCU_RESET_TypeDef;
\r
1005 /* ================================================================================ */
\r
1006 /* ================ LEDTS [LEDTS0] ================ */
\r
1007 /* ================================================================================ */
\r
1011 * @brief LED and Touch Sense Unit 0 (LEDTS)
\r
1014 typedef struct { /*!< (@ 0x48010000) LEDTS Structure */
\r
1015 __I uint32_t ID; /*!< (@ 0x48010000) Module Identification Register */
\r
1016 __IO uint32_t GLOBCTL; /*!< (@ 0x48010004) Global Control Register */
\r
1017 __IO uint32_t FNCTL; /*!< (@ 0x48010008) Function Control Register */
\r
1018 __O uint32_t EVFR; /*!< (@ 0x4801000C) Event Flag Register */
\r
1019 __IO uint32_t TSVAL; /*!< (@ 0x48010010) Touch-sense TS-Counter Value */
\r
1020 __IO uint32_t LINE0; /*!< (@ 0x48010014) Line Pattern Register 0 */
\r
1021 __IO uint32_t LINE1; /*!< (@ 0x48010018) Line Pattern Register 1 */
\r
1022 __IO uint32_t LDCMP0; /*!< (@ 0x4801001C) LED Compare Register 0 */
\r
1023 __IO uint32_t LDCMP1; /*!< (@ 0x48010020) LED Compare Register 1 */
\r
1024 __IO uint32_t TSCMP0; /*!< (@ 0x48010024) Touch-sense Compare Register 0 */
\r
1025 __IO uint32_t TSCMP1; /*!< (@ 0x48010028) Touch-sense Compare Register 1 */
\r
1026 } LEDTS0_GLOBAL_TypeDef;
\r
1029 /* ================================================================================ */
\r
1030 /* ================ ETH0_CON ================ */
\r
1031 /* ================================================================================ */
\r
1035 * @brief Ethernet Control Register (ETH0_CON)
\r
1038 typedef struct { /*!< (@ 0x50004040) ETH0_CON Structure */
\r
1039 __IO uint32_t CON; /*!< (@ 0x50004040) Ethernet 0 Port Control Register */
\r
1040 } ETH0_CON_GLOBAL_TypeDef;
\r
1043 /* ================================================================================ */
\r
1044 /* ================ ETH [ETH0] ================ */
\r
1045 /* ================================================================================ */
\r
1049 * @brief Ethernet Unit 0 (ETH)
\r
1052 typedef struct { /*!< (@ 0x5000C000) ETH Structure */
\r
1053 __IO uint32_t MAC_CONFIGURATION; /*!< (@ 0x5000C000) MAC Configuration Register */
\r
1054 __IO uint32_t MAC_FRAME_FILTER; /*!< (@ 0x5000C004) MAC Frame Filter */
\r
1055 __IO uint32_t HASH_TABLE_HIGH; /*!< (@ 0x5000C008) Hash Table High Register */
\r
1056 __IO uint32_t HASH_TABLE_LOW; /*!< (@ 0x5000C00C) Hash Table Low Register */
\r
1057 __IO uint32_t GMII_ADDRESS; /*!< (@ 0x5000C010) MII Address Register */
\r
1058 __IO uint32_t GMII_DATA; /*!< (@ 0x5000C014) MII Data Register */
\r
1059 __IO uint32_t FLOW_CONTROL; /*!< (@ 0x5000C018) Flow Control Register */
\r
1060 __IO uint32_t VLAN_TAG; /*!< (@ 0x5000C01C) VLAN Tag Register */
\r
1061 __I uint32_t VERSION; /*!< (@ 0x5000C020) Version Register */
\r
1062 __I uint32_t DEBUG; /*!< (@ 0x5000C024) Debug Register */
\r
1063 __IO uint32_t REMOTE_WAKE_UP_FRAME_FILTER; /*!< (@ 0x5000C028) Remote Wake Up Frame Filter Register */
\r
1064 __IO uint32_t PMT_CONTROL_STATUS; /*!< (@ 0x5000C02C) PMT Control and Status Register */
\r
1065 __I uint32_t RESERVED0[2];
\r
1066 __I uint32_t INTERRUPT_STATUS; /*!< (@ 0x5000C038) Interrupt Register */
\r
1067 __IO uint32_t INTERRUPT_MASK; /*!< (@ 0x5000C03C) Interrupt Mask Register */
\r
1068 __IO uint32_t MAC_ADDRESS0_HIGH; /*!< (@ 0x5000C040) MAC Address0 High Register */
\r
1069 __IO uint32_t MAC_ADDRESS0_LOW; /*!< (@ 0x5000C044) MAC Address0 Low Register */
\r
1070 __IO uint32_t MAC_ADDRESS1_HIGH; /*!< (@ 0x5000C048) MAC Address1 High Register */
\r
1071 __IO uint32_t MAC_ADDRESS1_LOW; /*!< (@ 0x5000C04C) MAC Address1 Low Register */
\r
1072 __IO uint32_t MAC_ADDRESS2_HIGH; /*!< (@ 0x5000C050) MAC Address2 High Register */
\r
1073 __IO uint32_t MAC_ADDRESS2_LOW; /*!< (@ 0x5000C054) MAC Address2 Low Register */
\r
1074 __IO uint32_t MAC_ADDRESS3_HIGH; /*!< (@ 0x5000C058) MAC Address3 High Register */
\r
1075 __IO uint32_t MAC_ADDRESS3_LOW; /*!< (@ 0x5000C05C) MAC Address3 Low Register */
\r
1076 __I uint32_t RESERVED1[40];
\r
1077 __IO uint32_t MMC_CONTROL; /*!< (@ 0x5000C100) MMC Control Register */
\r
1078 __I uint32_t MMC_RECEIVE_INTERRUPT; /*!< (@ 0x5000C104) MMC Receive Interrupt Register */
\r
1079 __I uint32_t MMC_TRANSMIT_INTERRUPT; /*!< (@ 0x5000C108) MMC Transmit Interrupt Register */
\r
1080 __IO uint32_t MMC_RECEIVE_INTERRUPT_MASK; /*!< (@ 0x5000C10C) MMC Reveive Interrupt Mask Register */
\r
1081 __IO uint32_t MMC_TRANSMIT_INTERRUPT_MASK; /*!< (@ 0x5000C110) MMC Transmit Interrupt Mask Register */
\r
1082 __I uint32_t TX_OCTET_COUNT_GOOD_BAD; /*!< (@ 0x5000C114) Transmit Octet Count for Good and Bad Frames
\r
1084 __I uint32_t TX_FRAME_COUNT_GOOD_BAD; /*!< (@ 0x5000C118) Transmit Frame Count for Goodand Bad Frames Register */
\r
1085 __I uint32_t TX_BROADCAST_FRAMES_GOOD; /*!< (@ 0x5000C11C) Transmit Frame Count for Good Broadcast Frames */
\r
1086 __I uint32_t TX_MULTICAST_FRAMES_GOOD; /*!< (@ 0x5000C120) Transmit Frame Count for Good Multicast Frames */
\r
1087 __I uint32_t TX_64OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C124) Transmit Octet Count for Good and Bad 64 Byte
\r
1089 __I uint32_t TX_65TO127OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C128) Transmit Octet Count for Good and Bad 65 to 127
\r
1091 __I uint32_t TX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C12C) Transmit Octet Count for Good and Bad 128 to
\r
1092 255 Bytes Frames */
\r
1093 __I uint32_t TX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C130) Transmit Octet Count for Good and Bad 256 to
\r
1094 511 Bytes Frames */
\r
1095 __I uint32_t TX_512TO1023OCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C134) Transmit Octet Count for Good and Bad 512 to
\r
1096 1023 Bytes Frames */
\r
1097 __I uint32_t TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C138) Transmit Octet Count for Good and Bad 1024 to
\r
1098 Maxsize Bytes Frames */
\r
1099 __I uint32_t TX_UNICAST_FRAMES_GOOD_BAD; /*!< (@ 0x5000C13C) Transmit Frame Count for Good and Bad Unicast
\r
1101 __I uint32_t TX_MULTICAST_FRAMES_GOOD_BAD; /*!< (@ 0x5000C140) Transmit Frame Count for Good and Bad Multicast
\r
1103 __I uint32_t TX_BROADCAST_FRAMES_GOOD_BAD; /*!< (@ 0x5000C144) Transmit Frame Count for Good and Bad Broadcast
\r
1105 __I uint32_t TX_UNDERFLOW_ERROR_FRAMES; /*!< (@ 0x5000C148) Transmit Frame Count for Underflow Error Frames */
\r
1106 __I uint32_t TX_SINGLE_COLLISION_GOOD_FRAMES; /*!< (@ 0x5000C14C) Transmit Frame Count for Frames Transmitted after
\r
1107 Single Collision */
\r
1108 __I uint32_t TX_MULTIPLE_COLLISION_GOOD_FRAMES; /*!< (@ 0x5000C150) Transmit Frame Count for Frames Transmitted after
\r
1109 Multiple Collision */
\r
1110 __I uint32_t TX_DEFERRED_FRAMES; /*!< (@ 0x5000C154) Tx Deferred Frames Register */
\r
1111 __I uint32_t TX_LATE_COLLISION_FRAMES; /*!< (@ 0x5000C158) Transmit Frame Count for Late Collision Error
\r
1113 __I uint32_t TX_EXCESSIVE_COLLISION_FRAMES; /*!< (@ 0x5000C15C) Transmit Frame Count for Excessive Collision
\r
1115 __I uint32_t TX_CARRIER_ERROR_FRAMES; /*!< (@ 0x5000C160) Transmit Frame Count for Carrier Sense Error
\r
1117 __I uint32_t TX_OCTET_COUNT_GOOD; /*!< (@ 0x5000C164) Tx Octet Count Good Register */
\r
1118 __I uint32_t TX_FRAME_COUNT_GOOD; /*!< (@ 0x5000C168) Tx Frame Count Good Register */
\r
1119 __I uint32_t TX_EXCESSIVE_DEFERRAL_ERROR; /*!< (@ 0x5000C16C) Transmit Frame Count for Excessive Deferral Error
\r
1121 __I uint32_t TX_PAUSE_FRAMES; /*!< (@ 0x5000C170) Transmit Frame Count for Good PAUSE Frames */
\r
1122 __I uint32_t TX_VLAN_FRAMES_GOOD; /*!< (@ 0x5000C174) Transmit Frame Count for Good VLAN Frames */
\r
1123 __I uint32_t TX_OSIZE_FRAMES_GOOD; /*!< (@ 0x5000C178) Transmit Frame Count for Good Oversize Frames */
\r
1124 __I uint32_t RESERVED2;
\r
1125 __I uint32_t RX_FRAMES_COUNT_GOOD_BAD; /*!< (@ 0x5000C180) Receive Frame Count for Good and Bad Frames */
\r
1126 __I uint32_t RX_OCTET_COUNT_GOOD_BAD; /*!< (@ 0x5000C184) Receive Octet Count for Good and Bad Frames */
\r
1127 __I uint32_t RX_OCTET_COUNT_GOOD; /*!< (@ 0x5000C188) Rx Octet Count Good Register */
\r
1128 __I uint32_t RX_BROADCAST_FRAMES_GOOD; /*!< (@ 0x5000C18C) Receive Frame Count for Good Broadcast Frames */
\r
1129 __I uint32_t RX_MULTICAST_FRAMES_GOOD; /*!< (@ 0x5000C190) Receive Frame Count for Good Multicast Frames */
\r
1130 __I uint32_t RX_CRC_ERROR_FRAMES; /*!< (@ 0x5000C194) Receive Frame Count for CRC Error Frames */
\r
1131 __I uint32_t RX_ALIGNMENT_ERROR_FRAMES; /*!< (@ 0x5000C198) Receive Frame Count for Alignment Error Frames */
\r
1132 __I uint32_t RX_RUNT_ERROR_FRAMES; /*!< (@ 0x5000C19C) Receive Frame Count for Runt Error Frames */
\r
1133 __I uint32_t RX_JABBER_ERROR_FRAMES; /*!< (@ 0x5000C1A0) Receive Frame Count for Jabber Error Frames */
\r
1134 __I uint32_t RX_UNDERSIZE_FRAMES_GOOD; /*!< (@ 0x5000C1A4) Receive Frame Count for Undersize Frames */
\r
1135 __I uint32_t RX_OVERSIZE_FRAMES_GOOD; /*!< (@ 0x5000C1A8) Rx Oversize Frames Good Register */
\r
1136 __I uint32_t RX_64OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1AC) Receive Frame Count for Good and Bad 64 Byte
\r
1138 __I uint32_t RX_65TO127OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B0) Receive Frame Count for Good and Bad 65 to 127
\r
1140 __I uint32_t RX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B4) Receive Frame Count for Good and Bad 128 to 255
\r
1142 __I uint32_t RX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B8) Receive Frame Count for Good and Bad 256 to 511
\r
1144 __I uint32_t RX_512TO1023OCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C1BC) Receive Frame Count for Good and Bad 512 to 1,023
\r
1146 __I uint32_t RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C1C0) Receive Frame Count for Good and Bad 1,024 to
\r
1147 Maxsize Bytes Frames */
\r
1148 __I uint32_t RX_UNICAST_FRAMES_GOOD; /*!< (@ 0x5000C1C4) Receive Frame Count for Good Unicast Frames */
\r
1149 __I uint32_t RX_LENGTH_ERROR_FRAMES; /*!< (@ 0x5000C1C8) Receive Frame Count for Length Error Frames */
\r
1150 __I uint32_t RX_OUT_OF_RANGE_TYPE_FRAMES; /*!< (@ 0x5000C1CC) Receive Frame Count for Out of Range Frames */
\r
1151 __I uint32_t RX_PAUSE_FRAMES; /*!< (@ 0x5000C1D0) Receive Frame Count for PAUSE Frames */
\r
1152 __I uint32_t RX_FIFO_OVERFLOW_FRAMES; /*!< (@ 0x5000C1D4) Receive Frame Count for FIFO Overflow Frames */
\r
1153 __I uint32_t RX_VLAN_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1D8) Receive Frame Count for Good and Bad VLAN Frames */
\r
1154 __I uint32_t RX_WATCHDOG_ERROR_FRAMES; /*!< (@ 0x5000C1DC) Receive Frame Count for Watchdog Error Frames */
\r
1155 __I uint32_t RX_RECEIVE_ERROR_FRAMES; /*!< (@ 0x5000C1E0) Receive Frame Count for Receive Error Frames */
\r
1156 __I uint32_t RX_CONTROL_FRAMES_GOOD; /*!< (@ 0x5000C1E4) Receive Frame Count for Good Control Frames Frames */
\r
1157 __I uint32_t RESERVED3[6];
\r
1158 __IO uint32_t MMC_IPC_RECEIVE_INTERRUPT_MASK; /*!< (@ 0x5000C200) MMC Receive Checksum Offload Interrupt Mask Register */
\r
1159 __I uint32_t RESERVED4;
\r
1160 __I uint32_t MMC_IPC_RECEIVE_INTERRUPT; /*!< (@ 0x5000C208) MMC Receive Checksum Offload Interrupt Register */
\r
1161 __I uint32_t RESERVED5;
\r
1162 __I uint32_t RXIPV4_GOOD_FRAMES; /*!< (@ 0x5000C210) RxIPv4 Good Frames Register */
\r
1163 __I uint32_t RXIPV4_HEADER_ERROR_FRAMES; /*!< (@ 0x5000C214) Receive IPV4 Header Error Frame Counter Register */
\r
1164 __I uint32_t RXIPV4_NO_PAYLOAD_FRAMES; /*!< (@ 0x5000C218) Receive IPV4 No Payload Frame Counter Register */
\r
1165 __I uint32_t RXIPV4_FRAGMENTED_FRAMES; /*!< (@ 0x5000C21C) Receive IPV4 Fragmented Frame Counter Register */
\r
1166 __I uint32_t RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES;/*!< (@ 0x5000C220) Receive IPV4 UDP Checksum Disabled Frame Counter
\r
1168 __I uint32_t RXIPV6_GOOD_FRAMES; /*!< (@ 0x5000C224) RxIPv6 Good Frames Register */
\r
1169 __I uint32_t RXIPV6_HEADER_ERROR_FRAMES; /*!< (@ 0x5000C228) Receive IPV6 Header Error Frame Counter Register */
\r
1170 __I uint32_t RXIPV6_NO_PAYLOAD_FRAMES; /*!< (@ 0x5000C22C) Receive IPV6 No Payload Frame Counter Register */
\r
1171 __I uint32_t RXUDP_GOOD_FRAMES; /*!< (@ 0x5000C230) RxUDP Good Frames Register */
\r
1172 __I uint32_t RXUDP_ERROR_FRAMES; /*!< (@ 0x5000C234) RxUDP Error Frames Register */
\r
1173 __I uint32_t RXTCP_GOOD_FRAMES; /*!< (@ 0x5000C238) RxTCP Good Frames Register */
\r
1174 __I uint32_t RXTCP_ERROR_FRAMES; /*!< (@ 0x5000C23C) RxTCP Error Frames Register */
\r
1175 __I uint32_t RXICMP_GOOD_FRAMES; /*!< (@ 0x5000C240) RxICMP Good Frames Register */
\r
1176 __I uint32_t RXICMP_ERROR_FRAMES; /*!< (@ 0x5000C244) RxICMP Error Frames Register */
\r
1177 __I uint32_t RESERVED6[2];
\r
1178 __I uint32_t RXIPV4_GOOD_OCTETS; /*!< (@ 0x5000C250) RxIPv4 Good Octets Register */
\r
1179 __I uint32_t RXIPV4_HEADER_ERROR_OCTETS; /*!< (@ 0x5000C254) Receive IPV4 Header Error Octet Counter Register */
\r
1180 __I uint32_t RXIPV4_NO_PAYLOAD_OCTETS; /*!< (@ 0x5000C258) Receive IPV4 No Payload Octet Counter Register */
\r
1181 __I uint32_t RXIPV4_FRAGMENTED_OCTETS; /*!< (@ 0x5000C25C) Receive IPV4 Fragmented Octet Counter Register */
\r
1182 __I uint32_t RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS;/*!< (@ 0x5000C260) Receive IPV4 Fragmented Octet Counter Register */
\r
1183 __I uint32_t RXIPV6_GOOD_OCTETS; /*!< (@ 0x5000C264) RxIPv6 Good Octets Register */
\r
1184 __I uint32_t RXIPV6_HEADER_ERROR_OCTETS; /*!< (@ 0x5000C268) Receive IPV6 Header Error Octet Counter Register */
\r
1185 __I uint32_t RXIPV6_NO_PAYLOAD_OCTETS; /*!< (@ 0x5000C26C) Receive IPV6 No Payload Octet Counter Register */
\r
1186 __I uint32_t RXUDP_GOOD_OCTETS; /*!< (@ 0x5000C270) Receive UDP Good Octets Register */
\r
1187 __I uint32_t RXUDP_ERROR_OCTETS; /*!< (@ 0x5000C274) Receive UDP Error Octets Register */
\r
1188 __I uint32_t RXTCP_GOOD_OCTETS; /*!< (@ 0x5000C278) Receive TCP Good Octets Register */
\r
1189 __I uint32_t RXTCP_ERROR_OCTETS; /*!< (@ 0x5000C27C) Receive TCP Error Octets Register */
\r
1190 __I uint32_t RXICMP_GOOD_OCTETS; /*!< (@ 0x5000C280) Receive ICMP Good Octets Register */
\r
1191 __I uint32_t RXICMP_ERROR_OCTETS; /*!< (@ 0x5000C284) Receive ICMP Error Octets Register */
\r
1192 __I uint32_t RESERVED7[286];
\r
1193 __IO uint32_t TIMESTAMP_CONTROL; /*!< (@ 0x5000C700) Timestamp Control Register */
\r
1194 __IO uint32_t SUB_SECOND_INCREMENT; /*!< (@ 0x5000C704) Sub-Second Increment Register */
\r
1195 __I uint32_t SYSTEM_TIME_SECONDS; /*!< (@ 0x5000C708) System Time - Seconds Register */
\r
1196 __I uint32_t SYSTEM_TIME_NANOSECONDS; /*!< (@ 0x5000C70C) System Time Nanoseconds Register */
\r
1197 __IO uint32_t SYSTEM_TIME_SECONDS_UPDATE; /*!< (@ 0x5000C710) System Time - Seconds Update Register */
\r
1198 __IO uint32_t SYSTEM_TIME_NANOSECONDS_UPDATE; /*!< (@ 0x5000C714) System Time Nanoseconds Update Register */
\r
1199 __IO uint32_t TIMESTAMP_ADDEND; /*!< (@ 0x5000C718) Timestamp Addend Register */
\r
1200 __IO uint32_t TARGET_TIME_SECONDS; /*!< (@ 0x5000C71C) Target Time Seconds Register */
\r
1201 __IO uint32_t TARGET_TIME_NANOSECONDS; /*!< (@ 0x5000C720) Target Time Nanoseconds Register */
\r
1202 __IO uint32_t SYSTEM_TIME_HIGHER_WORD_SECONDS; /*!< (@ 0x5000C724) System Time - Higher Word Seconds Register */
\r
1203 __I uint32_t TIMESTAMP_STATUS; /*!< (@ 0x5000C728) Timestamp Status Register */
\r
1204 __IO uint32_t PPS_CONTROL; /*!< (@ 0x5000C72C) PPS Control Register */
\r
1205 __I uint32_t RESERVED8[564];
\r
1206 __IO uint32_t BUS_MODE; /*!< (@ 0x5000D000) Bus Mode Register */
\r
1207 __IO uint32_t TRANSMIT_POLL_DEMAND; /*!< (@ 0x5000D004) Transmit Poll Demand Register */
\r
1208 __IO uint32_t RECEIVE_POLL_DEMAND; /*!< (@ 0x5000D008) Receive Poll Demand Register */
\r
1209 __IO uint32_t RECEIVE_DESCRIPTOR_LIST_ADDRESS; /*!< (@ 0x5000D00C) Receive Descriptor Address Register */
\r
1210 __IO uint32_t TRANSMIT_DESCRIPTOR_LIST_ADDRESS; /*!< (@ 0x5000D010) Transmit descripter Address Register */
\r
1211 __IO uint32_t STATUS; /*!< (@ 0x5000D014) Status Register */
\r
1212 __IO uint32_t OPERATION_MODE; /*!< (@ 0x5000D018) Operation Mode Register */
\r
1213 __IO uint32_t INTERRUPT_ENABLE; /*!< (@ 0x5000D01C) Interrupt Enable Register */
\r
1214 __I uint32_t MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER;/*!< (@ 0x5000D020) Missed Frame and Buffer Overflow Counter Register */
\r
1215 __IO uint32_t RECEIVE_INTERRUPT_WATCHDOG_TIMER; /*!< (@ 0x5000D024) Receive Interrupt Watchdog Timer Register */
\r
1216 __I uint32_t RESERVED9;
\r
1217 __I uint32_t AHB_STATUS; /*!< (@ 0x5000D02C) AHB Status Register */
\r
1218 __I uint32_t RESERVED10[6];
\r
1219 __I uint32_t CURRENT_HOST_TRANSMIT_DESCRIPTOR; /*!< (@ 0x5000D048) Current Host Transmit Descriptor Register */
\r
1220 __I uint32_t CURRENT_HOST_RECEIVE_DESCRIPTOR; /*!< (@ 0x5000D04C) Current Host Receive Descriptor Register */
\r
1221 __I uint32_t CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS;/*!< (@ 0x5000D050) Current Host Transmit Buffer Address Register */
\r
1222 __I uint32_t CURRENT_HOST_RECEIVE_BUFFER_ADDRESS;/*!< (@ 0x5000D054) Current Host Receive Buffer Address Register */
\r
1223 __IO uint32_t HW_FEATURE; /*!< (@ 0x5000D058) HW Feature Register */
\r
1224 } ETH_GLOBAL_TypeDef;
\r
1227 /* ================================================================================ */
\r
1228 /* ================ USB [USB0] ================ */
\r
1229 /* ================================================================================ */
\r
1233 * @brief Universal Serial Bus (USB)
\r
1236 typedef struct { /*!< (@ 0x50040000) USB Structure */
\r
1237 __IO uint32_t GOTGCTL; /*!< (@ 0x50040000) Control and Status Register */
\r
1238 __IO uint32_t GOTGINT; /*!< (@ 0x50040004) OTG Interrupt Register */
\r
1239 __IO uint32_t GAHBCFG; /*!< (@ 0x50040008) AHB Configuration Register */
\r
1240 __IO uint32_t GUSBCFG; /*!< (@ 0x5004000C) USB Configuration Register */
\r
1241 __IO uint32_t GRSTCTL; /*!< (@ 0x50040010) Reset Register */
\r
1244 __IO uint32_t GINTSTS_DEVICEMODE; /*!< (@ 0x50040014) Interrupt Register [DEVICEMODE] */
\r
1245 __IO uint32_t GINTSTS_HOSTMODE; /*!< (@ 0x50040014) Interrupt Register [HOSTMODE] */
\r
1249 __IO uint32_t GINTMSK_DEVICEMODE; /*!< (@ 0x50040018) Interrupt Mask Register [DEVICEMODE] */
\r
1250 __IO uint32_t GINTMSK_HOSTMODE; /*!< (@ 0x50040018) Interrupt Mask Register [HOSTMODE] */
\r
1254 __I uint32_t GRXSTSR_DEVICEMODE; /*!< (@ 0x5004001C) Receive Status Debug Read Register [DEVICEMODE] */
\r
1255 __I uint32_t GRXSTSR_HOSTMODE; /*!< (@ 0x5004001C) Receive Status Debug Read Register [HOSTMODE] */
\r
1259 __I uint32_t GRXSTSP_HOSTMODE; /*!< (@ 0x50040020) Receive Status Read and Pop Register [HOSTMODE] */
\r
1260 __I uint32_t GRXSTSP_DEVICEMODE; /*!< (@ 0x50040020) Receive Status Read and Pop Register [DEVICEMODE] */
\r
1262 __IO uint32_t GRXFSIZ; /*!< (@ 0x50040024) Receive FIFO Size Register */
\r
1265 __IO uint32_t GNPTXFSIZ_DEVICEMODE; /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register [DEVICEMODE] */
\r
1266 __IO uint32_t GNPTXFSIZ_HOSTMODE; /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register [HOSTMODE] */
\r
1268 __I uint32_t GNPTXSTS; /*!< (@ 0x5004002C) Non-Periodic Transmit FIFO/Queue Status Register */
\r
1269 __I uint32_t RESERVED0[3];
\r
1270 __IO uint32_t GUID; /*!< (@ 0x5004003C) USB Module Identification Register */
\r
1271 __I uint32_t RESERVED1[7];
\r
1272 __IO uint32_t GDFIFOCFG; /*!< (@ 0x5004005C) Global DFIFO Software Config Register */
\r
1273 __I uint32_t RESERVED2[40];
\r
1274 __IO uint32_t HPTXFSIZ; /*!< (@ 0x50040100) Host Periodic Transmit FIFO Size Register */
\r
1275 __IO uint32_t DIEPTXF1; /*!< (@ 0x50040104) Device IN Endpoint Transmit FIFO Size Register */
\r
1276 __IO uint32_t DIEPTXF2; /*!< (@ 0x50040108) Device IN Endpoint Transmit FIFO Size Register */
\r
1277 __IO uint32_t DIEPTXF3; /*!< (@ 0x5004010C) Device IN Endpoint Transmit FIFO Size Register */
\r
1278 __IO uint32_t DIEPTXF4; /*!< (@ 0x50040110) Device IN Endpoint Transmit FIFO Size Register */
\r
1279 __IO uint32_t DIEPTXF5; /*!< (@ 0x50040114) Device IN Endpoint Transmit FIFO Size Register */
\r
1280 __IO uint32_t DIEPTXF6; /*!< (@ 0x50040118) Device IN Endpoint Transmit FIFO Size Register */
\r
1281 __I uint32_t RESERVED3[185];
\r
1282 __IO uint32_t HCFG; /*!< (@ 0x50040400) Host Configuration Register */
\r
1283 __IO uint32_t HFIR; /*!< (@ 0x50040404) Host Frame Interval Register */
\r
1284 __IO uint32_t HFNUM; /*!< (@ 0x50040408) Host Frame Number/Frame Time Remaining Register */
\r
1285 __I uint32_t RESERVED4;
\r
1286 __IO uint32_t HPTXSTS; /*!< (@ 0x50040410) Host Periodic Transmit FIFO/ Queue Status Register */
\r
1287 __I uint32_t HAINT; /*!< (@ 0x50040414) Host All Channels Interrupt Register */
\r
1288 __IO uint32_t HAINTMSK; /*!< (@ 0x50040418) Host All Channels Interrupt Mask Register */
\r
1289 __IO uint32_t HFLBADDR; /*!< (@ 0x5004041C) Host Frame List Base Address Register */
\r
1290 __I uint32_t RESERVED5[8];
\r
1291 __IO uint32_t HPRT; /*!< (@ 0x50040440) Host Port Control and Status Register */
\r
1292 __I uint32_t RESERVED6[239];
\r
1293 __IO uint32_t DCFG; /*!< (@ 0x50040800) Device Configuration Register */
\r
1294 __IO uint32_t DCTL; /*!< (@ 0x50040804) Device Control Register */
\r
1295 __I uint32_t DSTS; /*!< (@ 0x50040808) Device Status Register */
\r
1296 __I uint32_t RESERVED7;
\r
1297 __IO uint32_t DIEPMSK; /*!< (@ 0x50040810) Device IN Endpoint Common Interrupt Mask Register */
\r
1298 __IO uint32_t DOEPMSK; /*!< (@ 0x50040814) Device OUT Endpoint Common Interrupt Mask Register */
\r
1299 __I uint32_t DAINT; /*!< (@ 0x50040818) Device All Endpoints Interrupt Register */
\r
1300 __IO uint32_t DAINTMSK; /*!< (@ 0x5004081C) Device All Endpoints Interrupt Mask Register */
\r
1301 __I uint32_t RESERVED8[2];
\r
1302 __IO uint32_t DVBUSDIS; /*!< (@ 0x50040828) Device VBUS Discharge Time Register */
\r
1303 __IO uint32_t DVBUSPULSE; /*!< (@ 0x5004082C) Device VBUS Pulsing Time Register */
\r
1304 __I uint32_t RESERVED9;
\r
1305 __IO uint32_t DIEPEMPMSK; /*!< (@ 0x50040834) Device IN Endpoint FIFO Empty Interrupt Mask
\r
1307 __I uint32_t RESERVED10[370];
\r
1308 __IO uint32_t PCGCCTL; /*!< (@ 0x50040E00) Power and Clock Gating Control Register */
\r
1309 } USB0_GLOBAL_TypeDef;
\r
1312 /* ================================================================================ */
\r
1313 /* ================ USB0_EP0 ================ */
\r
1314 /* ================================================================================ */
\r
1318 * @brief Universal Serial Bus (USB0_EP0)
\r
1321 typedef struct { /*!< (@ 0x50040900) USB0_EP0 Structure */
\r
1322 __IO uint32_t DIEPCTL0; /*!< (@ 0x50040900) Device Control IN Endpoint Control Register */
\r
1323 __I uint32_t RESERVED0;
\r
1324 __IO uint32_t DIEPINT0; /*!< (@ 0x50040908) Device Endpoint Interrupt Register */
\r
1325 __I uint32_t RESERVED1;
\r
1326 __IO uint32_t DIEPTSIZ0; /*!< (@ 0x50040910) Device IN Endpoint Transfer Size Register */
\r
1327 __IO uint32_t DIEPDMA0; /*!< (@ 0x50040914) Device Endpoint DMA Address Register */
\r
1328 __I uint32_t DTXFSTS0; /*!< (@ 0x50040918) Device IN Endpoint Transmit FIFO Status Register */
\r
1329 __I uint32_t DIEPDMAB0; /*!< (@ 0x5004091C) Device Endpoint DMA Buffer Address Register */
\r
1330 __I uint32_t RESERVED2[120];
\r
1331 __IO uint32_t DOEPCTL0; /*!< (@ 0x50040B00) Device Control OUT Endpoint Control Register */
\r
1332 __I uint32_t RESERVED3;
\r
1333 __IO uint32_t DOEPINT0; /*!< (@ 0x50040B08) Device Endpoint Interrupt Register */
\r
1334 __I uint32_t RESERVED4;
\r
1335 __IO uint32_t DOEPTSIZ0; /*!< (@ 0x50040B10) Device OUT Endpoint Transfer Size Register */
\r
1336 __IO uint32_t DOEPDMA0; /*!< (@ 0x50040B14) Device Endpoint DMA Address Register */
\r
1337 __I uint32_t RESERVED5;
\r
1338 __I uint32_t DOEPDMAB0; /*!< (@ 0x50040B1C) Device Endpoint DMA Buffer Address Register */
\r
1339 } USB0_EP0_TypeDef;
\r
1342 /* ================================================================================ */
\r
1343 /* ================ USB_EP [USB0_EP1] ================ */
\r
1344 /* ================================================================================ */
\r
1348 * @brief Universal Serial Bus (USB_EP)
\r
1351 typedef struct { /*!< (@ 0x50040920) USB_EP Structure */
\r
1354 __IO uint32_t DIEPCTL_INTBULK; /*!< (@ 0x50040920) Device Endpoint Control Register [INTBULK] */
\r
1355 __IO uint32_t DIEPCTL_ISOCONT; /*!< (@ 0x50040920) Device Endpoint Control Register [ISOCONT] */
\r
1357 __I uint32_t RESERVED0;
\r
1358 __IO uint32_t DIEPINT; /*!< (@ 0x50040928) Device Endpoint Interrupt Register */
\r
1359 __I uint32_t RESERVED1;
\r
1360 __IO uint32_t DIEPTSIZ; /*!< (@ 0x50040930) Device Endpoint Transfer Size Register */
\r
1361 __IO uint32_t DIEPDMA; /*!< (@ 0x50040934) Device Endpoint DMA Address Register */
\r
1362 __I uint32_t DTXFSTS; /*!< (@ 0x50040938) Device IN Endpoint Transmit FIFO Status Register */
\r
1363 __I uint32_t DIEPDMAB; /*!< (@ 0x5004093C) Device Endpoint DMA Buffer Address Register */
\r
1364 __I uint32_t RESERVED2[120];
\r
1367 __IO uint32_t DOEPCTL_INTBULK; /*!< (@ 0x50040B20) Device Endpoint Control Register [INTBULK] */
\r
1368 __IO uint32_t DOEPCTL_ISOCONT; /*!< (@ 0x50040B20) Device Endpoint Control Register [ISOCONT] */
\r
1370 __I uint32_t RESERVED3;
\r
1371 __IO uint32_t DOEPINT; /*!< (@ 0x50040B28) Device Endpoint Interrupt Register */
\r
1372 __I uint32_t RESERVED4;
\r
1375 __IO uint32_t DOEPTSIZ_CONTROL; /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [CONT] */
\r
1376 __IO uint32_t DOEPTSIZ_ISO; /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [ISO] */
\r
1378 __IO uint32_t DOEPDMA; /*!< (@ 0x50040B34) Device Endpoint DMA Address Register */
\r
1379 __I uint32_t RESERVED5;
\r
1380 __I uint32_t DOEPDMAB; /*!< (@ 0x50040B3C) Device Endpoint DMA Buffer Address Register */
\r
1381 } USB0_EP_TypeDef;
\r
1384 /* ================================================================================ */
\r
1385 /* ================ USB_CH [USB0_CH0] ================ */
\r
1386 /* ================================================================================ */
\r
1390 * @brief Universal Serial Bus (USB_CH)
\r
1393 typedef struct { /*!< (@ 0x50040500) USB_CH Structure */
\r
1394 __IO uint32_t HCCHAR; /*!< (@ 0x50040500) Host Channel Characteristics Register */
\r
1395 __I uint32_t RESERVED0;
\r
1396 __IO uint32_t HCINT; /*!< (@ 0x50040508) Host Channel Interrupt Register */
\r
1397 __IO uint32_t HCINTMSK; /*!< (@ 0x5004050C) Host Channel Interrupt Mask Register */
\r
1400 __IO uint32_t HCTSIZ_SCATGATHER; /*!< (@ 0x50040510) Host Channel Transfer Size Register [SCATGATHER] */
\r
1401 __IO uint32_t HCTSIZ_BUFFERMODE; /*!< (@ 0x50040510) Host Channel Transfer Size Register [BUFFERMODE] */
\r
1405 __IO uint32_t HCDMA_SCATGATHER; /*!< (@ 0x50040514) Host Channel DMA Address Register [SCATGATHER] */
\r
1406 __IO uint32_t HCDMA_BUFFERMODE; /*!< (@ 0x50040514) Host Channel DMA Address Register [BUFFERMODE] */
\r
1408 __I uint32_t RESERVED1;
\r
1409 __I uint32_t HCDMAB; /*!< (@ 0x5004051C) Host Channel DMA Buffer Address Register */
\r
1410 } USB0_CH_TypeDef;
\r
1413 /* ================================================================================ */
\r
1414 /* ================ USIC [USIC0] ================ */
\r
1415 /* ================================================================================ */
\r
1419 * @brief Universal Serial Interface Controller 0 (USIC)
\r
1422 typedef struct { /*!< (@ 0x40030008) USIC Structure */
\r
1423 __I uint32_t ID; /*!< (@ 0x40030008) Module Identification Register */
\r
1424 } USIC_GLOBAL_TypeDef;
\r
1427 /* ================================================================================ */
\r
1428 /* ================ USIC_CH [USIC0_CH0] ================ */
\r
1429 /* ================================================================================ */
\r
1433 * @brief Universal Serial Interface Controller 0 (USIC_CH)
\r
1436 typedef struct { /*!< (@ 0x40030000) USIC_CH Structure */
\r
1437 __I uint32_t RESERVED0;
\r
1438 __I uint32_t CCFG; /*!< (@ 0x40030004) Channel Configuration Register */
\r
1439 __I uint32_t RESERVED1;
\r
1440 __IO uint32_t KSCFG; /*!< (@ 0x4003000C) Kernel State Configuration Register */
\r
1441 __IO uint32_t FDR; /*!< (@ 0x40030010) Fractional Divider Register */
\r
1442 __IO uint32_t BRG; /*!< (@ 0x40030014) Baud Rate Generator Register */
\r
1443 __IO uint32_t INPR; /*!< (@ 0x40030018) Interrupt Node Pointer Register */
\r
1444 __IO uint32_t DX0CR; /*!< (@ 0x4003001C) Input Control Register 0 */
\r
1445 __IO uint32_t DX1CR; /*!< (@ 0x40030020) Input Control Register 1 */
\r
1446 __IO uint32_t DX2CR; /*!< (@ 0x40030024) Input Control Register 2 */
\r
1447 __IO uint32_t DX3CR; /*!< (@ 0x40030028) Input Control Register 3 */
\r
1448 __IO uint32_t DX4CR; /*!< (@ 0x4003002C) Input Control Register 4 */
\r
1449 __IO uint32_t DX5CR; /*!< (@ 0x40030030) Input Control Register 5 */
\r
1450 __IO uint32_t SCTR; /*!< (@ 0x40030034) Shift Control Register */
\r
1451 __IO uint32_t TCSR; /*!< (@ 0x40030038) Transmit Control/Status Register */
\r
1454 __IO uint32_t PCR_IICMode; /*!< (@ 0x4003003C) Protocol Control Register [IIC Mode] */
\r
1455 __IO uint32_t PCR_IISMode; /*!< (@ 0x4003003C) Protocol Control Register [IIS Mode] */
\r
1456 __IO uint32_t PCR_SSCMode; /*!< (@ 0x4003003C) Protocol Control Register [SSC Mode] */
\r
1457 __IO uint32_t PCR; /*!< (@ 0x4003003C) Protocol Control Register */
\r
1458 __IO uint32_t PCR_ASCMode; /*!< (@ 0x4003003C) Protocol Control Register [ASC Mode] */
\r
1460 __IO uint32_t CCR; /*!< (@ 0x40030040) Channel Control Register */
\r
1461 __IO uint32_t CMTR; /*!< (@ 0x40030044) Capture Mode Timer Register */
\r
1464 __IO uint32_t PSR_IICMode; /*!< (@ 0x40030048) Protocol Status Register [IIC Mode] */
\r
1465 __IO uint32_t PSR_IISMode; /*!< (@ 0x40030048) Protocol Status Register [IIS Mode] */
\r
1466 __IO uint32_t PSR_SSCMode; /*!< (@ 0x40030048) Protocol Status Register [SSC Mode] */
\r
1467 __IO uint32_t PSR; /*!< (@ 0x40030048) Protocol Status Register */
\r
1468 __IO uint32_t PSR_ASCMode; /*!< (@ 0x40030048) Protocol Status Register [ASC Mode] */
\r
1470 __O uint32_t PSCR; /*!< (@ 0x4003004C) Protocol Status Clear Register */
\r
1471 __I uint32_t RBUFSR; /*!< (@ 0x40030050) Receiver Buffer Status Register */
\r
1472 __I uint32_t RBUF; /*!< (@ 0x40030054) Receiver Buffer Register */
\r
1473 __I uint32_t RBUFD; /*!< (@ 0x40030058) Receiver Buffer Register for Debugger */
\r
1474 __I uint32_t RBUF0; /*!< (@ 0x4003005C) Receiver Buffer Register 0 */
\r
1475 __I uint32_t RBUF1; /*!< (@ 0x40030060) Receiver Buffer Register 1 */
\r
1476 __I uint32_t RBUF01SR; /*!< (@ 0x40030064) Receiver Buffer 01 Status Register */
\r
1477 __O uint32_t FMR; /*!< (@ 0x40030068) Flag Modification Register */
\r
1478 __I uint32_t RESERVED2[5];
\r
1479 __IO uint32_t TBUF[32]; /*!< (@ 0x40030080) Transmit Buffer */
\r
1480 __IO uint32_t BYP; /*!< (@ 0x40030100) Bypass Data Register */
\r
1481 __IO uint32_t BYPCR; /*!< (@ 0x40030104) Bypass Control Register */
\r
1482 __IO uint32_t TBCTR; /*!< (@ 0x40030108) Transmitter Buffer Control Register */
\r
1483 __IO uint32_t RBCTR; /*!< (@ 0x4003010C) Receiver Buffer Control Register */
\r
1484 __I uint32_t TRBPTR; /*!< (@ 0x40030110) Transmit/Receive Buffer Pointer Register */
\r
1485 __IO uint32_t TRBSR; /*!< (@ 0x40030114) Transmit/Receive Buffer Status Register */
\r
1486 __O uint32_t TRBSCR; /*!< (@ 0x40030118) Transmit/Receive Buffer Status Clear Register */
\r
1487 __I uint32_t OUTR; /*!< (@ 0x4003011C) Receiver Buffer Output Register */
\r
1488 __I uint32_t OUTDR; /*!< (@ 0x40030120) Receiver Buffer Output Register L for Debugger */
\r
1489 __I uint32_t RESERVED3[23];
\r
1490 __O uint32_t IN[32]; /*!< (@ 0x40030180) Transmit FIFO Buffer */
\r
1491 } USIC_CH_TypeDef;
\r
1494 /* ================================================================================ */
\r
1495 /* ================ CAN ================ */
\r
1496 /* ================================================================================ */
\r
1500 * @brief Controller Area Networks (CAN)
\r
1503 typedef struct { /*!< (@ 0x48014000) CAN Structure */
\r
1504 __IO uint32_t CLC; /*!< (@ 0x48014000) CAN Clock Control Register */
\r
1505 __I uint32_t RESERVED0;
\r
1506 __I uint32_t ID; /*!< (@ 0x48014008) Module Identification Register */
\r
1507 __IO uint32_t FDR; /*!< (@ 0x4801400C) CAN Fractional Divider Register */
\r
1508 __I uint32_t RESERVED1[60];
\r
1509 __I uint32_t LIST[8]; /*!< (@ 0x48014100) List Register */
\r
1510 __I uint32_t RESERVED2[8];
\r
1511 __IO uint32_t MSPND[8]; /*!< (@ 0x48014140) Message Pending Register */
\r
1512 __I uint32_t RESERVED3[8];
\r
1513 __I uint32_t MSID[8]; /*!< (@ 0x48014180) Message Index Register */
\r
1514 __I uint32_t RESERVED4[8];
\r
1515 __IO uint32_t MSIMASK; /*!< (@ 0x480141C0) Message Index Mask Register */
\r
1516 __IO uint32_t PANCTR; /*!< (@ 0x480141C4) Panel Control Register */
\r
1517 __IO uint32_t MCR; /*!< (@ 0x480141C8) Module Control Register */
\r
1518 __O uint32_t MITR; /*!< (@ 0x480141CC) Module Interrupt Trigger Register */
\r
1519 } CAN_GLOBAL_TypeDef;
\r
1522 /* ================================================================================ */
\r
1523 /* ================ CAN_NODE [CAN_NODE0] ================ */
\r
1524 /* ================================================================================ */
\r
1528 * @brief Controller Area Networks (CAN_NODE)
\r
1531 typedef struct { /*!< (@ 0x48014200) CAN_NODE Structure */
\r
1532 __IO uint32_t NCR; /*!< (@ 0x48014200) Node Control Register */
\r
1533 __IO uint32_t NSR; /*!< (@ 0x48014204) Node Status Register */
\r
1534 __IO uint32_t NIPR; /*!< (@ 0x48014208) Node Interrupt Pointer Register */
\r
1535 __IO uint32_t NPCR; /*!< (@ 0x4801420C) Node Port Control Register */
\r
1536 __IO uint32_t NBTR; /*!< (@ 0x48014210) Node Bit Timing Register */
\r
1537 __IO uint32_t NECNT; /*!< (@ 0x48014214) Node Error Counter Register */
\r
1538 __IO uint32_t NFCR; /*!< (@ 0x48014218) Node Frame Counter Register */
\r
1539 } CAN_NODE_TypeDef;
\r
1542 /* ================================================================================ */
\r
1543 /* ================ CAN_MO [CAN_MO0] ================ */
\r
1544 /* ================================================================================ */
\r
1548 * @brief Controller Area Networks (CAN_MO)
\r
1551 typedef struct { /*!< (@ 0x48015000) CAN_MO Structure */
\r
1552 __IO uint32_t MOFCR; /*!< (@ 0x48015000) Message Object Function Control Register */
\r
1553 __IO uint32_t MOFGPR; /*!< (@ 0x48015004) Message Object FIFO/Gateway Pointer Register */
\r
1554 __IO uint32_t MOIPR; /*!< (@ 0x48015008) Message Object Interrupt Pointer Register */
\r
1555 __IO uint32_t MOAMR; /*!< (@ 0x4801500C) Message Object Acceptance Mask Register */
\r
1556 __IO uint32_t MODATAL; /*!< (@ 0x48015010) Message Object Data Register Low */
\r
1557 __IO uint32_t MODATAH; /*!< (@ 0x48015014) Message Object Data Register High */
\r
1558 __IO uint32_t MOAR; /*!< (@ 0x48015018) Message Object Arbitration Register */
\r
1561 __I uint32_t MOSTAT; /*!< (@ 0x4801501C) Message Object Status Register */
\r
1562 __O uint32_t MOCTR; /*!< (@ 0x4801501C) Message Object Control Register */
\r
1567 /* ================================================================================ */
\r
1568 /* ================ VADC ================ */
\r
1569 /* ================================================================================ */
\r
1573 * @brief Analog to Digital Converter (VADC)
\r
1576 typedef struct { /*!< (@ 0x40004000) VADC Structure */
\r
1577 __IO uint32_t CLC; /*!< (@ 0x40004000) Clock Control Register */
\r
1578 __I uint32_t RESERVED0;
\r
1579 __I uint32_t ID; /*!< (@ 0x40004008) Module Identification Register */
\r
1580 __I uint32_t RESERVED1[7];
\r
1581 __IO uint32_t OCS; /*!< (@ 0x40004028) OCDS Control and Status Register */
\r
1582 __I uint32_t RESERVED2[21];
\r
1583 __IO uint32_t GLOBCFG; /*!< (@ 0x40004080) Global Configuration Register */
\r
1584 __I uint32_t RESERVED3[7];
\r
1585 __IO uint32_t GLOBICLASS[2]; /*!< (@ 0x400040A0) Input Class Register, Global */
\r
1586 __I uint32_t RESERVED4[4];
\r
1587 __IO uint32_t GLOBBOUND; /*!< (@ 0x400040B8) Global Boundary Select Register */
\r
1588 __I uint32_t RESERVED5[9];
\r
1589 __IO uint32_t GLOBEFLAG; /*!< (@ 0x400040E0) Global Event Flag Register */
\r
1590 __I uint32_t RESERVED6[23];
\r
1591 __IO uint32_t GLOBEVNP; /*!< (@ 0x40004140) Global Event Node Pointer Register */
\r
1592 __I uint32_t RESERVED7[7];
\r
1593 __IO uint32_t GLOBTF; /*!< (@ 0x40004160) Global Test Functions Register */
\r
1594 __I uint32_t RESERVED8[7];
\r
1595 __IO uint32_t BRSSEL[4]; /*!< (@ 0x40004180) Background Request Source Channel Select Register */
\r
1596 __I uint32_t RESERVED9[12];
\r
1597 __IO uint32_t BRSPND[4]; /*!< (@ 0x400041C0) Background Request Source Pending Register */
\r
1598 __I uint32_t RESERVED10[12];
\r
1599 __IO uint32_t BRSCTRL; /*!< (@ 0x40004200) Background Request Source Control Register */
\r
1600 __IO uint32_t BRSMR; /*!< (@ 0x40004204) Background Request Source Mode Register */
\r
1601 __I uint32_t RESERVED11[30];
\r
1602 __IO uint32_t GLOBRCR; /*!< (@ 0x40004280) Global Result Control Register */
\r
1603 __I uint32_t RESERVED12[31];
\r
1604 __IO uint32_t GLOBRES; /*!< (@ 0x40004300) Global Result Register */
\r
1605 __I uint32_t RESERVED13[31];
\r
1606 __IO uint32_t GLOBRESD; /*!< (@ 0x40004380) Global Result Register, Debug */
\r
1607 __I uint32_t RESERVED14[27];
\r
1608 __IO uint32_t EMUXSEL; /*!< (@ 0x400043F0) External Multiplexer Select Register */
\r
1609 } VADC_GLOBAL_TypeDef;
\r
1612 /* ================================================================================ */
\r
1613 /* ================ VADC_G [VADC_G0] ================ */
\r
1614 /* ================================================================================ */
\r
1618 * @brief Analog to Digital Converter (VADC_G)
\r
1621 typedef struct { /*!< (@ 0x40004400) VADC_G Structure */
\r
1622 __I uint32_t RESERVED0[32];
\r
1623 __IO uint32_t ARBCFG; /*!< (@ 0x40004480) Arbitration Configuration Register */
\r
1624 __IO uint32_t ARBPR; /*!< (@ 0x40004484) Arbitration Priority Register */
\r
1625 __IO uint32_t CHASS; /*!< (@ 0x40004488) Channel Assignment Register */
\r
1626 __I uint32_t RESERVED1[5];
\r
1627 __IO uint32_t ICLASS[2]; /*!< (@ 0x400044A0) Input Class Register */
\r
1628 __I uint32_t RESERVED2[2];
\r
1629 __IO uint32_t ALIAS; /*!< (@ 0x400044B0) Alias Register */
\r
1630 __I uint32_t RESERVED3;
\r
1631 __IO uint32_t BOUND; /*!< (@ 0x400044B8) Boundary Select Register */
\r
1632 __I uint32_t RESERVED4;
\r
1633 __IO uint32_t SYNCTR; /*!< (@ 0x400044C0) Synchronization Control Register */
\r
1634 __I uint32_t RESERVED5;
\r
1635 __IO uint32_t BFL; /*!< (@ 0x400044C8) Boundary Flag Register */
\r
1636 __I uint32_t RESERVED6[13];
\r
1637 __IO uint32_t QCTRL0; /*!< (@ 0x40004500) Queue 0 Source Control Register */
\r
1638 __IO uint32_t QMR0; /*!< (@ 0x40004504) Queue 0 Mode Register */
\r
1639 __I uint32_t QSR0; /*!< (@ 0x40004508) Queue 0 Status Register */
\r
1640 __I uint32_t Q0R0; /*!< (@ 0x4000450C) Queue 0 Register 0 */
\r
1643 __I uint32_t QBUR0; /*!< (@ 0x40004510) Queue 0 Backup Register */
\r
1644 __O uint32_t QINR0; /*!< (@ 0x40004510) Queue 0 Input Register */
\r
1646 __I uint32_t RESERVED7[3];
\r
1647 __IO uint32_t ASCTRL; /*!< (@ 0x40004520) Autoscan Source Control Register */
\r
1648 __IO uint32_t ASMR; /*!< (@ 0x40004524) Autoscan Source Mode Register */
\r
1649 __IO uint32_t ASSEL; /*!< (@ 0x40004528) Autoscan Source Channel Select Register */
\r
1650 __IO uint32_t ASPND; /*!< (@ 0x4000452C) Autoscan Source Pending Register */
\r
1651 __I uint32_t RESERVED8[20];
\r
1652 __IO uint32_t CEFLAG; /*!< (@ 0x40004580) Channel Event Flag Register */
\r
1653 __IO uint32_t REFLAG; /*!< (@ 0x40004584) Result Event Flag Register */
\r
1654 __IO uint32_t SEFLAG; /*!< (@ 0x40004588) Source Event Flag Register */
\r
1655 __I uint32_t RESERVED9;
\r
1656 __O uint32_t CEFCLR; /*!< (@ 0x40004590) Channel Event Flag Clear Register */
\r
1657 __O uint32_t REFCLR; /*!< (@ 0x40004594) Result Event Flag Clear Register */
\r
1658 __O uint32_t SEFCLR; /*!< (@ 0x40004598) Source Event Flag Clear Register */
\r
1659 __I uint32_t RESERVED10;
\r
1660 __IO uint32_t CEVNP0; /*!< (@ 0x400045A0) Channel Event Node Pointer Register 0 */
\r
1661 __I uint32_t RESERVED11[3];
\r
1662 __IO uint32_t REVNP0; /*!< (@ 0x400045B0) Result Event Node Pointer Register 0 */
\r
1663 __IO uint32_t REVNP1; /*!< (@ 0x400045B4) Result Event Node Pointer Register 1 */
\r
1664 __I uint32_t RESERVED12[2];
\r
1665 __IO uint32_t SEVNP; /*!< (@ 0x400045C0) Source Event Node Pointer Register */
\r
1666 __I uint32_t RESERVED13;
\r
1667 __O uint32_t SRACT; /*!< (@ 0x400045C8) Service Request Software Activation Trigger */
\r
1668 __I uint32_t RESERVED14[9];
\r
1669 __IO uint32_t EMUXCTR; /*!< (@ 0x400045F0) E0ternal Multiplexer Control Register */
\r
1670 __I uint32_t RESERVED15;
\r
1671 __IO uint32_t VFR; /*!< (@ 0x400045F8) Valid Flag Register */
\r
1672 __I uint32_t RESERVED16;
\r
1673 __IO uint32_t CHCTR[8]; /*!< (@ 0x40004600) Channel Ctrl. Reg. */
\r
1674 __I uint32_t RESERVED17[24];
\r
1675 __IO uint32_t RCR[16]; /*!< (@ 0x40004680) Result Control Register */
\r
1676 __I uint32_t RESERVED18[16];
\r
1677 __IO uint32_t RES[16]; /*!< (@ 0x40004700) Result Register */
\r
1678 __I uint32_t RESERVED19[16];
\r
1679 __I uint32_t RESD[16]; /*!< (@ 0x40004780) Result Register, Debug */
\r
1683 /* ================================================================================ */
\r
1684 /* ================ DSD ================ */
\r
1685 /* ================================================================================ */
\r
1689 * @brief Delta Sigma Demodulator (DSD)
\r
1692 typedef struct { /*!< (@ 0x40008000) DSD Structure */
\r
1693 __IO uint32_t CLC; /*!< (@ 0x40008000) Clock Control Register */
\r
1694 __I uint32_t RESERVED0;
\r
1695 __I uint32_t ID; /*!< (@ 0x40008008) Module Identification Register */
\r
1696 __I uint32_t RESERVED1[7];
\r
1697 __IO uint32_t OCS; /*!< (@ 0x40008028) OCDS Control and Status Register */
\r
1698 __I uint32_t RESERVED2[21];
\r
1699 __IO uint32_t GLOBCFG; /*!< (@ 0x40008080) Global Configuration Register */
\r
1700 __I uint32_t RESERVED3;
\r
1701 __IO uint32_t GLOBRC; /*!< (@ 0x40008088) Global Run Control Register */
\r
1702 __I uint32_t RESERVED4[5];
\r
1703 __IO uint32_t CGCFG; /*!< (@ 0x400080A0) Carrier Generator Configuration Register */
\r
1704 __I uint32_t RESERVED5[15];
\r
1705 __IO uint32_t EVFLAG; /*!< (@ 0x400080E0) Event Flag Register */
\r
1706 __O uint32_t EVFLAGCLR; /*!< (@ 0x400080E4) Event Flag Clear Register */
\r
1707 } DSD_GLOBAL_TypeDef;
\r
1710 /* ================================================================================ */
\r
1711 /* ================ DSD_CH [DSD_CH0] ================ */
\r
1712 /* ================================================================================ */
\r
1716 * @brief Delta Sigma Demodulator (DSD_CH)
\r
1719 typedef struct { /*!< (@ 0x40008100) DSD_CH Structure */
\r
1720 __IO uint32_t MODCFG; /*!< (@ 0x40008100) Modulator Configuration Register */
\r
1721 __I uint32_t RESERVED0;
\r
1722 __IO uint32_t DICFG; /*!< (@ 0x40008108) Demodulator Input Configuration Register */
\r
1723 __I uint32_t RESERVED1[2];
\r
1724 __IO uint32_t FCFGC; /*!< (@ 0x40008114) Filter Configuration Register, Main CIC Filter */
\r
1725 __IO uint32_t FCFGA; /*!< (@ 0x40008118) Filter Configuration Register, Auxiliary Filter */
\r
1726 __I uint32_t RESERVED2;
\r
1727 __IO uint32_t IWCTR; /*!< (@ 0x40008120) Integration Window Control Register */
\r
1728 __I uint32_t RESERVED3;
\r
1729 __IO uint32_t BOUNDSEL; /*!< (@ 0x40008128) Boundary Select Register */
\r
1730 __I uint32_t RESERVED4;
\r
1731 __I uint32_t RESM; /*!< (@ 0x40008130) Result Register, Main Filter */
\r
1732 __I uint32_t RESERVED5;
\r
1733 __IO uint32_t OFFM; /*!< (@ 0x40008138) Offset Register, Main Filter */
\r
1734 __I uint32_t RESERVED6;
\r
1735 __I uint32_t RESA; /*!< (@ 0x40008140) Result Register, Auxiliary Filter */
\r
1736 __I uint32_t RESERVED7[3];
\r
1737 __I uint32_t TSTMP; /*!< (@ 0x40008150) Time-Stamp Register */
\r
1738 __I uint32_t RESERVED8[19];
\r
1739 __IO uint32_t CGSYNC; /*!< (@ 0x400081A0) Carrier Generator Synchronization Register */
\r
1740 __I uint32_t RESERVED9;
\r
1741 __IO uint32_t RECTCFG; /*!< (@ 0x400081A8) Rectification Configuration Register */
\r
1745 /* ================================================================================ */
\r
1746 /* ================ DAC ================ */
\r
1747 /* ================================================================================ */
\r
1751 * @brief Digital to Analog Converter (DAC)
\r
1754 typedef struct { /*!< (@ 0x48018000) DAC Structure */
\r
1755 __I uint32_t ID; /*!< (@ 0x48018000) Module Identification Register */
\r
1756 __IO uint32_t DAC0CFG0; /*!< (@ 0x48018004) DAC0 Configuration Register 0 */
\r
1757 __IO uint32_t DAC0CFG1; /*!< (@ 0x48018008) DAC0 Configuration Register 1 */
\r
1758 __IO uint32_t DAC1CFG0; /*!< (@ 0x4801800C) DAC1 Configuration Register 0 */
\r
1759 __IO uint32_t DAC1CFG1; /*!< (@ 0x48018010) DAC1 Configuration Register 1 */
\r
1760 __IO uint32_t DAC0DATA; /*!< (@ 0x48018014) DAC0 Data Register */
\r
1761 __IO uint32_t DAC1DATA; /*!< (@ 0x48018018) DAC1 Data Register */
\r
1762 __IO uint32_t DAC01DATA; /*!< (@ 0x4801801C) DAC01 Data Register */
\r
1763 __IO uint32_t DAC0PATL; /*!< (@ 0x48018020) DAC0 Lower Pattern Register */
\r
1764 __IO uint32_t DAC0PATH; /*!< (@ 0x48018024) DAC0 Higher Pattern Register */
\r
1765 __IO uint32_t DAC1PATL; /*!< (@ 0x48018028) DAC1 Lower Pattern Register */
\r
1766 __IO uint32_t DAC1PATH; /*!< (@ 0x4801802C) DAC1 Higher Pattern Register */
\r
1767 } DAC_GLOBAL_TypeDef;
\r
1770 /* ================================================================================ */
\r
1771 /* ================ CCU4 [CCU40] ================ */
\r
1772 /* ================================================================================ */
\r
1776 * @brief Capture Compare Unit 4 - Unit 0 (CCU4)
\r
1779 typedef struct { /*!< (@ 0x4000C000) CCU4 Structure */
\r
1780 __IO uint32_t GCTRL; /*!< (@ 0x4000C000) Global Control Register */
\r
1781 __I uint32_t GSTAT; /*!< (@ 0x4000C004) Global Status Register */
\r
1782 __O uint32_t GIDLS; /*!< (@ 0x4000C008) Global Idle Set */
\r
1783 __O uint32_t GIDLC; /*!< (@ 0x4000C00C) Global Idle Clear */
\r
1784 __O uint32_t GCSS; /*!< (@ 0x4000C010) Global Channel Set */
\r
1785 __O uint32_t GCSC; /*!< (@ 0x4000C014) Global Channel Clear */
\r
1786 __I uint32_t GCST; /*!< (@ 0x4000C018) Global Channel Status */
\r
1787 __I uint32_t RESERVED0[13];
\r
1788 __I uint32_t ECRD; /*!< (@ 0x4000C050) Extended Capture Mode Read */
\r
1789 __I uint32_t RESERVED1[11];
\r
1790 __I uint32_t MIDR; /*!< (@ 0x4000C080) Module Identification */
\r
1791 } CCU4_GLOBAL_TypeDef;
\r
1794 /* ================================================================================ */
\r
1795 /* ================ CCU4_CC4 [CCU40_CC40] ================ */
\r
1796 /* ================================================================================ */
\r
1800 * @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4)
\r
1803 typedef struct { /*!< (@ 0x4000C100) CCU4_CC4 Structure */
\r
1804 __IO uint32_t INS; /*!< (@ 0x4000C100) Input Selector Configuration */
\r
1805 __IO uint32_t CMC; /*!< (@ 0x4000C104) Connection Matrix Control */
\r
1806 __I uint32_t TCST; /*!< (@ 0x4000C108) Slice Timer Status */
\r
1807 __O uint32_t TCSET; /*!< (@ 0x4000C10C) Slice Timer Run Set */
\r
1808 __O uint32_t TCCLR; /*!< (@ 0x4000C110) Slice Timer Clear */
\r
1809 __IO uint32_t TC; /*!< (@ 0x4000C114) Slice Timer Control */
\r
1810 __IO uint32_t PSL; /*!< (@ 0x4000C118) Passive Level Config */
\r
1811 __I uint32_t DIT; /*!< (@ 0x4000C11C) Dither Config */
\r
1812 __IO uint32_t DITS; /*!< (@ 0x4000C120) Dither Shadow Register */
\r
1813 __IO uint32_t PSC; /*!< (@ 0x4000C124) Prescaler Control */
\r
1814 __IO uint32_t FPC; /*!< (@ 0x4000C128) Floating Prescaler Control */
\r
1815 __IO uint32_t FPCS; /*!< (@ 0x4000C12C) Floating Prescaler Shadow */
\r
1816 __I uint32_t PR; /*!< (@ 0x4000C130) Timer Period Value */
\r
1817 __IO uint32_t PRS; /*!< (@ 0x4000C134) Timer Shadow Period Value */
\r
1818 __I uint32_t CR; /*!< (@ 0x4000C138) Timer Compare Value */
\r
1819 __IO uint32_t CRS; /*!< (@ 0x4000C13C) Timer Shadow Compare Value */
\r
1820 __I uint32_t RESERVED0[12];
\r
1821 __IO uint32_t TIMER; /*!< (@ 0x4000C170) Timer Value */
\r
1822 __I uint32_t CV[4]; /*!< (@ 0x4000C174) Capture Register 0 */
\r
1823 __I uint32_t RESERVED1[7];
\r
1824 __I uint32_t INTS; /*!< (@ 0x4000C1A0) Interrupt Status */
\r
1825 __IO uint32_t INTE; /*!< (@ 0x4000C1A4) Interrupt Enable Control */
\r
1826 __IO uint32_t SRS; /*!< (@ 0x4000C1A8) Service Request Selector */
\r
1827 __O uint32_t SWS; /*!< (@ 0x4000C1AC) Interrupt Status Set */
\r
1828 __O uint32_t SWR; /*!< (@ 0x4000C1B0) Interrupt Status Clear */
\r
1829 } CCU4_CC4_TypeDef;
\r
1832 /* ================================================================================ */
\r
1833 /* ================ CCU8 [CCU80] ================ */
\r
1834 /* ================================================================================ */
\r
1838 * @brief Capture Compare Unit 8 - Unit 0 (CCU8)
\r
1841 typedef struct { /*!< (@ 0x40020000) CCU8 Structure */
\r
1842 __IO uint32_t GCTRL; /*!< (@ 0x40020000) Global Control Register */
\r
1843 __I uint32_t GSTAT; /*!< (@ 0x40020004) Global Status Register */
\r
1844 __O uint32_t GIDLS; /*!< (@ 0x40020008) Global Idle Set */
\r
1845 __O uint32_t GIDLC; /*!< (@ 0x4002000C) Global Idle Clear */
\r
1846 __O uint32_t GCSS; /*!< (@ 0x40020010) Global Channel Set */
\r
1847 __O uint32_t GCSC; /*!< (@ 0x40020014) Global Channel Clear */
\r
1848 __I uint32_t GCST; /*!< (@ 0x40020018) Global Channel status */
\r
1849 __IO uint32_t GPCHK; /*!< (@ 0x4002001C) Parity Checker Configuration */
\r
1850 __I uint32_t RESERVED0[12];
\r
1851 __I uint32_t ECRD; /*!< (@ 0x40020050) Extended Capture Mode Read */
\r
1852 __I uint32_t RESERVED1[11];
\r
1853 __I uint32_t MIDR; /*!< (@ 0x40020080) Module Identification */
\r
1854 } CCU8_GLOBAL_TypeDef;
\r
1857 /* ================================================================================ */
\r
1858 /* ================ CCU8_CC8 [CCU80_CC80] ================ */
\r
1859 /* ================================================================================ */
\r
1863 * @brief Capture Compare Unit 8 - Unit 0 (CCU8_CC8)
\r
1866 typedef struct { /*!< (@ 0x40020100) CCU8_CC8 Structure */
\r
1867 __IO uint32_t INS; /*!< (@ 0x40020100) Input Selector Configuration */
\r
1868 __IO uint32_t CMC; /*!< (@ 0x40020104) Connection Matrix Control */
\r
1869 __I uint32_t TCST; /*!< (@ 0x40020108) Slice Timer Status */
\r
1870 __O uint32_t TCSET; /*!< (@ 0x4002010C) Slice Timer Run Set */
\r
1871 __O uint32_t TCCLR; /*!< (@ 0x40020110) Slice Timer Clear */
\r
1872 __IO uint32_t TC; /*!< (@ 0x40020114) Slice Timer Control */
\r
1873 __IO uint32_t PSL; /*!< (@ 0x40020118) Passive Level Config */
\r
1874 __I uint32_t DIT; /*!< (@ 0x4002011C) Dither Config */
\r
1875 __IO uint32_t DITS; /*!< (@ 0x40020120) Dither Shadow Register */
\r
1876 __IO uint32_t PSC; /*!< (@ 0x40020124) Prescaler Control */
\r
1877 __IO uint32_t FPC; /*!< (@ 0x40020128) Floating Prescaler Control */
\r
1878 __IO uint32_t FPCS; /*!< (@ 0x4002012C) Floating Prescaler Shadow */
\r
1879 __I uint32_t PR; /*!< (@ 0x40020130) Timer Period Value */
\r
1880 __IO uint32_t PRS; /*!< (@ 0x40020134) Timer Shadow Period Value */
\r
1881 __I uint32_t CR1; /*!< (@ 0x40020138) Channel 1 Compare Value */
\r
1882 __IO uint32_t CR1S; /*!< (@ 0x4002013C) Channel 1 Compare Shadow Value */
\r
1883 __I uint32_t CR2; /*!< (@ 0x40020140) Channel 2 Compare Value */
\r
1884 __IO uint32_t CR2S; /*!< (@ 0x40020144) Channel 2 Compare Shadow Value */
\r
1885 __IO uint32_t CHC; /*!< (@ 0x40020148) Channel Control */
\r
1886 __IO uint32_t DTC; /*!< (@ 0x4002014C) Dead Time Control */
\r
1887 __IO uint32_t DC1R; /*!< (@ 0x40020150) Channel 1 Dead Time Values */
\r
1888 __IO uint32_t DC2R; /*!< (@ 0x40020154) Channel 2 Dead Time Values */
\r
1889 __I uint32_t RESERVED0[6];
\r
1890 __IO uint32_t TIMER; /*!< (@ 0x40020170) Timer Value */
\r
1891 __I uint32_t CV[4]; /*!< (@ 0x40020174) Capture Register 0 */
\r
1892 __I uint32_t RESERVED1[7];
\r
1893 __I uint32_t INTS; /*!< (@ 0x400201A0) Interrupt Status */
\r
1894 __IO uint32_t INTE; /*!< (@ 0x400201A4) Interrupt Enable Control */
\r
1895 __IO uint32_t SRS; /*!< (@ 0x400201A8) Service Request Selector */
\r
1896 __O uint32_t SWS; /*!< (@ 0x400201AC) Interrupt Status Set */
\r
1897 __O uint32_t SWR; /*!< (@ 0x400201B0) Interrupt Status Clear */
\r
1898 } CCU8_CC8_TypeDef;
\r
1901 /* ================================================================================ */
\r
1902 /* ================ HRPWM0 ================ */
\r
1903 /* ================================================================================ */
\r
1907 * @brief High Resolution PWM Unit (HRPWM0)
\r
1910 typedef struct { /*!< (@ 0x40020900) HRPWM0 Structure */
\r
1911 __IO uint32_t HRBSC; /*!< (@ 0x40020900) Bias and suspend configuration */
\r
1912 __I uint32_t RESERVED0;
\r
1913 __I uint32_t MIDR; /*!< (@ 0x40020908) Module identification register */
\r
1914 __I uint32_t RESERVED1[2];
\r
1915 __IO uint32_t GLBANA; /*!< (@ 0x40020914) Global Analog Configuration */
\r
1916 __I uint32_t RESERVED2[2];
\r
1917 __IO uint32_t CSGCFG; /*!< (@ 0x40020920) Global CSG configuration */
\r
1918 __O uint32_t CSGSETG; /*!< (@ 0x40020924) Global CSG run bit set */
\r
1919 __O uint32_t CSGCLRG; /*!< (@ 0x40020928) Global CSG run bit clear */
\r
1920 __I uint32_t CSGSTATG; /*!< (@ 0x4002092C) Global CSG run bit status */
\r
1921 __O uint32_t CSGFCG; /*!< (@ 0x40020930) Global CSG slope/prescaler control */
\r
1922 __I uint32_t CSGFSG; /*!< (@ 0x40020934) Global CSG slope/prescaler status */
\r
1923 __O uint32_t CSGTRG; /*!< (@ 0x40020938) Global CSG shadow/switch trigger */
\r
1924 __O uint32_t CSGTRC; /*!< (@ 0x4002093C) Global CSG shadow trigger clear */
\r
1925 __I uint32_t CSGTRSG; /*!< (@ 0x40020940) Global CSG shadow/switch status */
\r
1926 __I uint32_t RESERVED3[7];
\r
1927 __IO uint32_t HRCCFG; /*!< (@ 0x40020960) Global HRC configuration */
\r
1928 __O uint32_t HRCSTRG; /*!< (@ 0x40020964) Global HRC shadow trigger set */
\r
1929 __O uint32_t HRCCTRG; /*!< (@ 0x40020968) Global HRC shadow trigger clear */
\r
1930 __I uint32_t HRCSTSG; /*!< (@ 0x4002096C) Global HRC shadow transfer status */
\r
1931 __I uint32_t HRGHRS; /*!< (@ 0x40020970) High Resolution Generation Status */
\r
1935 /* ================================================================================ */
\r
1936 /* ================ HRPWM0_CSG [HRPWM0_CSG0] ================ */
\r
1937 /* ================================================================================ */
\r
1941 * @brief High Resolution PWM Unit (HRPWM0_CSG)
\r
1944 typedef struct { /*!< (@ 0x40020A00) HRPWM0_CSG Structure */
\r
1945 __IO uint32_t DCI; /*!< (@ 0x40020A00) External input selection */
\r
1946 __IO uint32_t IES; /*!< (@ 0x40020A04) External input selection */
\r
1947 __IO uint32_t SC; /*!< (@ 0x40020A08) Slope generation control */
\r
1948 __I uint32_t PC; /*!< (@ 0x40020A0C) Pulse swallow configuration */
\r
1949 __I uint32_t DSV1; /*!< (@ 0x40020A10) DAC reference value 1 */
\r
1950 __IO uint32_t DSV2; /*!< (@ 0x40020A14) DAC reference value 1 */
\r
1951 __IO uint32_t SDSV1; /*!< (@ 0x40020A18) Shadow reference value 1 */
\r
1952 __IO uint32_t SPC; /*!< (@ 0x40020A1C) Shadow Pulse swallow value */
\r
1953 __IO uint32_t CC; /*!< (@ 0x40020A20) Comparator configuration */
\r
1954 __IO uint32_t PLC; /*!< (@ 0x40020A24) Passive level configuration */
\r
1955 __IO uint32_t BLV; /*!< (@ 0x40020A28) Comparator blanking value */
\r
1956 __IO uint32_t SRE; /*!< (@ 0x40020A2C) Service request enable */
\r
1957 __IO uint32_t SRS; /*!< (@ 0x40020A30) Service request line selector */
\r
1958 __O uint32_t SWS; /*!< (@ 0x40020A34) Service request SW set */
\r
1959 __O uint32_t SWC; /*!< (@ 0x40020A38) Service request SW clear */
\r
1960 __I uint32_t ISTAT; /*!< (@ 0x40020A3C) Service request status */
\r
1961 } HRPWM0_CSG_Type;
\r
1964 /* ================================================================================ */
\r
1965 /* ================ HRPWM0_HRC [HRPWM0_HRC0] ================ */
\r
1966 /* ================================================================================ */
\r
1970 * @brief High Resolution PWM Unit (HRPWM0_HRC)
\r
1973 typedef struct { /*!< (@ 0x40021300) HRPWM0_HRC Structure */
\r
1974 __IO uint32_t GC; /*!< (@ 0x40021300) HRC mode configuration */
\r
1975 __IO uint32_t PL; /*!< (@ 0x40021304) HRC output passive level */
\r
1976 __IO uint32_t GSEL; /*!< (@ 0x40021308) HRC global control selection */
\r
1977 __IO uint32_t TSEL; /*!< (@ 0x4002130C) HRC timer selection */
\r
1978 __I uint32_t SC; /*!< (@ 0x40021310) HRC current source for shadow */
\r
1979 __I uint32_t DCR; /*!< (@ 0x40021314) HRC dead time rising value */
\r
1980 __I uint32_t DCF; /*!< (@ 0x40021318) HRC dead time falling value */
\r
1981 __I uint32_t CR1; /*!< (@ 0x4002131C) HRC rising edge value */
\r
1982 __I uint32_t CR2; /*!< (@ 0x40021320) HRC falling edge value */
\r
1983 __IO uint32_t SSC; /*!< (@ 0x40021324) HRC next source for shadow */
\r
1984 __IO uint32_t SDCR; /*!< (@ 0x40021328) HRC shadow dead time rising */
\r
1985 __IO uint32_t SDCF; /*!< (@ 0x4002132C) HRC shadow dead time falling */
\r
1986 __IO uint32_t SCR1; /*!< (@ 0x40021330) HRC shadow rising edge value */
\r
1987 __IO uint32_t SCR2; /*!< (@ 0x40021334) HRC shadow falling edge value */
\r
1988 } HRPWM0_HRC_Type;
\r
1991 /* ================================================================================ */
\r
1992 /* ================ POSIF [POSIF0] ================ */
\r
1993 /* ================================================================================ */
\r
1997 * @brief Position Interface 0 (POSIF)
\r
2000 typedef struct { /*!< (@ 0x40028000) POSIF Structure */
\r
2001 __IO uint32_t PCONF; /*!< (@ 0x40028000) Service Request Processing configuration */
\r
2002 __IO uint32_t PSUS; /*!< (@ 0x40028004) Service Request Processing Suspend Config */
\r
2003 __O uint32_t PRUNS; /*!< (@ 0x40028008) Service Request Processing Run Bit Set */
\r
2004 __O uint32_t PRUNC; /*!< (@ 0x4002800C) Service Request Processing Run Bit Clear */
\r
2005 __I uint32_t PRUN; /*!< (@ 0x40028010) Service Request Processing Run Bit Status */
\r
2006 __I uint32_t RESERVED0[3];
\r
2007 __I uint32_t MIDR; /*!< (@ 0x40028020) Module Identification register */
\r
2008 __I uint32_t RESERVED1[3];
\r
2009 __I uint32_t HALP; /*!< (@ 0x40028030) Hall Sensor Patterns */
\r
2010 __IO uint32_t HALPS; /*!< (@ 0x40028034) Hall Sensor Shadow Patterns */
\r
2011 __I uint32_t RESERVED2[2];
\r
2012 __I uint32_t MCM; /*!< (@ 0x40028040) Multi-Channel Pattern */
\r
2013 __IO uint32_t MCSM; /*!< (@ 0x40028044) Multi-Channel Shadow Pattern */
\r
2014 __O uint32_t MCMS; /*!< (@ 0x40028048) Multi-Channel Pattern Control set */
\r
2015 __O uint32_t MCMC; /*!< (@ 0x4002804C) Multi-Channel Pattern Control clear */
\r
2016 __I uint32_t MCMF; /*!< (@ 0x40028050) Multi-Channel Pattern Control flag */
\r
2017 __I uint32_t RESERVED3[3];
\r
2018 __IO uint32_t QDC; /*!< (@ 0x40028060) Quadrature Decoder Control */
\r
2019 __I uint32_t RESERVED4[3];
\r
2020 __I uint32_t PFLG; /*!< (@ 0x40028070) Service Request Processing Interrupt Flags */
\r
2021 __IO uint32_t PFLGE; /*!< (@ 0x40028074) Service Request Processing Interrupt Enable */
\r
2022 __O uint32_t SPFLG; /*!< (@ 0x40028078) Service Request Processing Interrupt Set */
\r
2023 __O uint32_t RPFLG; /*!< (@ 0x4002807C) Service Request Processing Interrupt Clear */
\r
2024 __I uint32_t RESERVED5[32];
\r
2025 __I uint32_t PDBG; /*!< (@ 0x40028100) POSIF Debug register */
\r
2026 } POSIF_GLOBAL_TypeDef;
\r
2029 /* ================================================================================ */
\r
2030 /* ================ PORT0 ================ */
\r
2031 /* ================================================================================ */
\r
2035 * @brief Port 0 (PORT0)
\r
2038 typedef struct { /*!< (@ 0x48028000) PORT0 Structure */
\r
2039 __IO uint32_t OUT; /*!< (@ 0x48028000) Port 0 Output Register */
\r
2040 __O uint32_t OMR; /*!< (@ 0x48028004) Port 0 Output Modification Register */
\r
2041 __I uint32_t RESERVED0[2];
\r
2042 __IO uint32_t IOCR0; /*!< (@ 0x48028010) Port 0 Input/Output Control Register 0 */
\r
2043 __IO uint32_t IOCR4; /*!< (@ 0x48028014) Port 0 Input/Output Control Register 4 */
\r
2044 __IO uint32_t IOCR8; /*!< (@ 0x48028018) Port 0 Input/Output Control Register 8 */
\r
2045 __IO uint32_t IOCR12; /*!< (@ 0x4802801C) Port 0 Input/Output Control Register 12 */
\r
2046 __I uint32_t RESERVED1;
\r
2047 __I uint32_t IN; /*!< (@ 0x48028024) Port 0 Input Register */
\r
2048 __I uint32_t RESERVED2[6];
\r
2049 __IO uint32_t PDR0; /*!< (@ 0x48028040) Port 0 Pad Driver Mode 0 Register */
\r
2050 __IO uint32_t PDR1; /*!< (@ 0x48028044) Port 0 Pad Driver Mode 1 Register */
\r
2051 __I uint32_t RESERVED3[6];
\r
2052 __I uint32_t PDISC; /*!< (@ 0x48028060) Port 0 Pin Function Decision Control Register */
\r
2053 __I uint32_t RESERVED4[3];
\r
2054 __IO uint32_t PPS; /*!< (@ 0x48028070) Port 0 Pin Power Save Register */
\r
2055 __IO uint32_t HWSEL; /*!< (@ 0x48028074) Port 0 Pin Hardware Select Register */
\r
2059 /* ================================================================================ */
\r
2060 /* ================ PORT1 ================ */
\r
2061 /* ================================================================================ */
\r
2065 * @brief Port 1 (PORT1)
\r
2068 typedef struct { /*!< (@ 0x48028100) PORT1 Structure */
\r
2069 __IO uint32_t OUT; /*!< (@ 0x48028100) Port 1 Output Register */
\r
2070 __O uint32_t OMR; /*!< (@ 0x48028104) Port 1 Output Modification Register */
\r
2071 __I uint32_t RESERVED0[2];
\r
2072 __IO uint32_t IOCR0; /*!< (@ 0x48028110) Port 1 Input/Output Control Register 0 */
\r
2073 __IO uint32_t IOCR4; /*!< (@ 0x48028114) Port 1 Input/Output Control Register 4 */
\r
2074 __IO uint32_t IOCR8; /*!< (@ 0x48028118) Port 1 Input/Output Control Register 8 */
\r
2075 __IO uint32_t IOCR12; /*!< (@ 0x4802811C) Port 1 Input/Output Control Register 12 */
\r
2076 __I uint32_t RESERVED1;
\r
2077 __I uint32_t IN; /*!< (@ 0x48028124) Port 1 Input Register */
\r
2078 __I uint32_t RESERVED2[6];
\r
2079 __IO uint32_t PDR0; /*!< (@ 0x48028140) Port 1 Pad Driver Mode 0 Register */
\r
2080 __IO uint32_t PDR1; /*!< (@ 0x48028144) Port 1 Pad Driver Mode 1 Register */
\r
2081 __I uint32_t RESERVED3[6];
\r
2082 __I uint32_t PDISC; /*!< (@ 0x48028160) Port 1 Pin Function Decision Control Register */
\r
2083 __I uint32_t RESERVED4[3];
\r
2084 __IO uint32_t PPS; /*!< (@ 0x48028170) Port 1 Pin Power Save Register */
\r
2085 __IO uint32_t HWSEL; /*!< (@ 0x48028174) Port 1 Pin Hardware Select Register */
\r
2089 /* ================================================================================ */
\r
2090 /* ================ PORT2 ================ */
\r
2091 /* ================================================================================ */
\r
2095 * @brief Port 2 (PORT2)
\r
2098 typedef struct { /*!< (@ 0x48028200) PORT2 Structure */
\r
2099 __IO uint32_t OUT; /*!< (@ 0x48028200) Port 2 Output Register */
\r
2100 __O uint32_t OMR; /*!< (@ 0x48028204) Port 2 Output Modification Register */
\r
2101 __I uint32_t RESERVED0[2];
\r
2102 __IO uint32_t IOCR0; /*!< (@ 0x48028210) Port 2 Input/Output Control Register 0 */
\r
2103 __IO uint32_t IOCR4; /*!< (@ 0x48028214) Port 2 Input/Output Control Register 4 */
\r
2104 __IO uint32_t IOCR8; /*!< (@ 0x48028218) Port 2 Input/Output Control Register 8 */
\r
2105 __IO uint32_t IOCR12; /*!< (@ 0x4802821C) Port 2 Input/Output Control Register 12 */
\r
2106 __I uint32_t RESERVED1;
\r
2107 __I uint32_t IN; /*!< (@ 0x48028224) Port 2 Input Register */
\r
2108 __I uint32_t RESERVED2[6];
\r
2109 __IO uint32_t PDR0; /*!< (@ 0x48028240) Port 2 Pad Driver Mode 0 Register */
\r
2110 __IO uint32_t PDR1; /*!< (@ 0x48028244) Port 2 Pad Driver Mode 1 Register */
\r
2111 __I uint32_t RESERVED3[6];
\r
2112 __I uint32_t PDISC; /*!< (@ 0x48028260) Port 2 Pin Function Decision Control Register */
\r
2113 __I uint32_t RESERVED4[3];
\r
2114 __IO uint32_t PPS; /*!< (@ 0x48028270) Port 2 Pin Power Save Register */
\r
2115 __IO uint32_t HWSEL; /*!< (@ 0x48028274) Port 2 Pin Hardware Select Register */
\r
2119 /* ================================================================================ */
\r
2120 /* ================ PORT3 ================ */
\r
2121 /* ================================================================================ */
\r
2125 * @brief Port 3 (PORT3)
\r
2128 typedef struct { /*!< (@ 0x48028300) PORT3 Structure */
\r
2129 __IO uint32_t OUT; /*!< (@ 0x48028300) Port 3 Output Register */
\r
2130 __O uint32_t OMR; /*!< (@ 0x48028304) Port 3 Output Modification Register */
\r
2131 __I uint32_t RESERVED0[2];
\r
2132 __IO uint32_t IOCR0; /*!< (@ 0x48028310) Port 3 Input/Output Control Register 0 */
\r
2133 __IO uint32_t IOCR4; /*!< (@ 0x48028314) Port 3 Input/Output Control Register 4 */
\r
2134 __I uint32_t RESERVED1[3];
\r
2135 __I uint32_t IN; /*!< (@ 0x48028324) Port 3 Input Register */
\r
2136 __I uint32_t RESERVED2[6];
\r
2137 __IO uint32_t PDR0; /*!< (@ 0x48028340) Port 3 Pad Driver Mode 0 Register */
\r
2138 __I uint32_t RESERVED3[7];
\r
2139 __I uint32_t PDISC; /*!< (@ 0x48028360) Port 3 Pin Function Decision Control Register */
\r
2140 __I uint32_t RESERVED4[3];
\r
2141 __IO uint32_t PPS; /*!< (@ 0x48028370) Port 3 Pin Power Save Register */
\r
2142 __IO uint32_t HWSEL; /*!< (@ 0x48028374) Port 3 Pin Hardware Select Register */
\r
2146 /* ================================================================================ */
\r
2147 /* ================ PORT4 ================ */
\r
2148 /* ================================================================================ */
\r
2152 * @brief Port 4 (PORT4)
\r
2155 typedef struct { /*!< (@ 0x48028400) PORT4 Structure */
\r
2156 __IO uint32_t OUT; /*!< (@ 0x48028400) Port 4 Output Register */
\r
2157 __O uint32_t OMR; /*!< (@ 0x48028404) Port 4 Output Modification Register */
\r
2158 __I uint32_t RESERVED0[2];
\r
2159 __IO uint32_t IOCR0; /*!< (@ 0x48028410) Port 4 Input/Output Control Register 0 */
\r
2160 __I uint32_t RESERVED1[4];
\r
2161 __I uint32_t IN; /*!< (@ 0x48028424) Port 4 Input Register */
\r
2162 __I uint32_t RESERVED2[6];
\r
2163 __IO uint32_t PDR0; /*!< (@ 0x48028440) Port 4 Pad Driver Mode 0 Register */
\r
2164 __I uint32_t RESERVED3[7];
\r
2165 __I uint32_t PDISC; /*!< (@ 0x48028460) Port 4 Pin Function Decision Control Register */
\r
2166 __I uint32_t RESERVED4[3];
\r
2167 __IO uint32_t PPS; /*!< (@ 0x48028470) Port 4 Pin Power Save Register */
\r
2168 __IO uint32_t HWSEL; /*!< (@ 0x48028474) Port 4 Pin Hardware Select Register */
\r
2172 /* ================================================================================ */
\r
2173 /* ================ PORT5 ================ */
\r
2174 /* ================================================================================ */
\r
2178 * @brief Port 5 (PORT5)
\r
2181 typedef struct { /*!< (@ 0x48028500) PORT5 Structure */
\r
2182 __IO uint32_t OUT; /*!< (@ 0x48028500) Port 5 Output Register */
\r
2183 __O uint32_t OMR; /*!< (@ 0x48028504) Port 5 Output Modification Register */
\r
2184 __I uint32_t RESERVED0[2];
\r
2185 __IO uint32_t IOCR0; /*!< (@ 0x48028510) Port 5 Input/Output Control Register 0 */
\r
2186 __IO uint32_t IOCR4; /*!< (@ 0x48028514) Port 5 Input/Output Control Register 4 */
\r
2187 __I uint32_t RESERVED1[3];
\r
2188 __I uint32_t IN; /*!< (@ 0x48028524) Port 5 Input Register */
\r
2189 __I uint32_t RESERVED2[6];
\r
2190 __IO uint32_t PDR0; /*!< (@ 0x48028540) Port 5 Pad Driver Mode 0 Register */
\r
2191 __I uint32_t RESERVED3[7];
\r
2192 __I uint32_t PDISC; /*!< (@ 0x48028560) Port 5 Pin Function Decision Control Register */
\r
2193 __I uint32_t RESERVED4[3];
\r
2194 __IO uint32_t PPS; /*!< (@ 0x48028570) Port 5 Pin Power Save Register */
\r
2195 __IO uint32_t HWSEL; /*!< (@ 0x48028574) Port 5 Pin Hardware Select Register */
\r
2199 /* ================================================================================ */
\r
2200 /* ================ PORT14 ================ */
\r
2201 /* ================================================================================ */
\r
2205 * @brief Port 14 (PORT14)
\r
2208 typedef struct { /*!< (@ 0x48028E00) PORT14 Structure */
\r
2209 __IO uint32_t OUT; /*!< (@ 0x48028E00) Port 14 Output Register */
\r
2210 __O uint32_t OMR; /*!< (@ 0x48028E04) Port 14 Output Modification Register */
\r
2211 __I uint32_t RESERVED0[2];
\r
2212 __IO uint32_t IOCR0; /*!< (@ 0x48028E10) Port 14 Input/Output Control Register 0 */
\r
2213 __IO uint32_t IOCR4; /*!< (@ 0x48028E14) Port 14 Input/Output Control Register 4 */
\r
2214 __IO uint32_t IOCR8; /*!< (@ 0x48028E18) Port 14 Input/Output Control Register 8 */
\r
2215 __IO uint32_t IOCR12; /*!< (@ 0x48028E1C) Port 14 Input/Output Control Register 12 */
\r
2216 __I uint32_t RESERVED1;
\r
2217 __I uint32_t IN; /*!< (@ 0x48028E24) Port 14 Input Register */
\r
2218 __I uint32_t RESERVED2[14];
\r
2219 __IO uint32_t PDISC; /*!< (@ 0x48028E60) Port 14 Pin Function Decision Control Register */
\r
2220 __I uint32_t RESERVED3[3];
\r
2221 __IO uint32_t PPS; /*!< (@ 0x48028E70) Port 14 Pin Power Save Register */
\r
2222 __IO uint32_t HWSEL; /*!< (@ 0x48028E74) Port 14 Pin Hardware Select Register */
\r
2226 /* ================================================================================ */
\r
2227 /* ================ PORT15 ================ */
\r
2228 /* ================================================================================ */
\r
2232 * @brief Port 15 (PORT15)
\r
2235 typedef struct { /*!< (@ 0x48028F00) PORT15 Structure */
\r
2236 __IO uint32_t OUT; /*!< (@ 0x48028F00) Port 15 Output Register */
\r
2237 __O uint32_t OMR; /*!< (@ 0x48028F04) Port 15 Output Modification Register */
\r
2238 __I uint32_t RESERVED0[2];
\r
2239 __IO uint32_t IOCR0; /*!< (@ 0x48028F10) Port 15 Input/Output Control Register 0 */
\r
2240 __IO uint32_t IOCR4; /*!< (@ 0x48028F14) Port 15 Input/Output Control Register 4 */
\r
2241 __IO uint32_t IOCR8; /*!< (@ 0x48028F18) Port 15 Input/Output Control Register 8 */
\r
2242 __I uint32_t RESERVED1[2];
\r
2243 __I uint32_t IN; /*!< (@ 0x48028F24) Port 15 Input Register */
\r
2244 __I uint32_t RESERVED2[14];
\r
2245 __IO uint32_t PDISC; /*!< (@ 0x48028F60) Port 15 Pin Function Decision Control Register */
\r
2246 __I uint32_t RESERVED3[3];
\r
2247 __IO uint32_t PPS; /*!< (@ 0x48028F70) Port 15 Pin Power Save Register */
\r
2248 __IO uint32_t HWSEL; /*!< (@ 0x48028F74) Port 15 Pin Hardware Select Register */
\r
2252 /* -------------------- End of section using anonymous unions ------------------- */
\r
2253 #if defined(__CC_ARM)
\r
2255 #elif defined(__ICCARM__)
\r
2256 /* leave anonymous unions enabled */
\r
2257 #elif defined(__GNUC__)
\r
2258 /* anonymous unions are enabled by default */
\r
2259 #elif defined(__TMS470__)
\r
2260 /* anonymous unions are enabled by default */
\r
2261 #elif defined(__TASKING__)
\r
2262 #pragma warning restore
\r
2264 #warning Not supported compiler type
\r
2269 /* ================================================================================ */
\r
2270 /* ================ struct 'PPB' Position & Mask ================ */
\r
2271 /* ================================================================================ */
\r
2274 /* ---------------------------------- PPB_ACTLR --------------------------------- */
\r
2275 #define PPB_ACTLR_DISMCYCINT_Pos 0 /*!< PPB ACTLR: DISMCYCINT Position */
\r
2276 #define PPB_ACTLR_DISMCYCINT_Msk (0x01UL << PPB_ACTLR_DISMCYCINT_Pos) /*!< PPB ACTLR: DISMCYCINT Mask */
\r
2277 #define PPB_ACTLR_DISDEFWBUF_Pos 1 /*!< PPB ACTLR: DISDEFWBUF Position */
\r
2278 #define PPB_ACTLR_DISDEFWBUF_Msk (0x01UL << PPB_ACTLR_DISDEFWBUF_Pos) /*!< PPB ACTLR: DISDEFWBUF Mask */
\r
2279 #define PPB_ACTLR_DISFOLD_Pos 2 /*!< PPB ACTLR: DISFOLD Position */
\r
2280 #define PPB_ACTLR_DISFOLD_Msk (0x01UL << PPB_ACTLR_DISFOLD_Pos) /*!< PPB ACTLR: DISFOLD Mask */
\r
2281 #define PPB_ACTLR_DISFPCA_Pos 8 /*!< PPB ACTLR: DISFPCA Position */
\r
2282 #define PPB_ACTLR_DISFPCA_Msk (0x01UL << PPB_ACTLR_DISFPCA_Pos) /*!< PPB ACTLR: DISFPCA Mask */
\r
2283 #define PPB_ACTLR_DISOOFP_Pos 9 /*!< PPB ACTLR: DISOOFP Position */
\r
2284 #define PPB_ACTLR_DISOOFP_Msk (0x01UL << PPB_ACTLR_DISOOFP_Pos) /*!< PPB ACTLR: DISOOFP Mask */
\r
2286 /* -------------------------------- PPB_SYST_CSR -------------------------------- */
\r
2287 #define PPB_SYST_CSR_ENABLE_Pos 0 /*!< PPB SYST_CSR: ENABLE Position */
\r
2288 #define PPB_SYST_CSR_ENABLE_Msk (0x01UL << PPB_SYST_CSR_ENABLE_Pos) /*!< PPB SYST_CSR: ENABLE Mask */
\r
2289 #define PPB_SYST_CSR_TICKINT_Pos 1 /*!< PPB SYST_CSR: TICKINT Position */
\r
2290 #define PPB_SYST_CSR_TICKINT_Msk (0x01UL << PPB_SYST_CSR_TICKINT_Pos) /*!< PPB SYST_CSR: TICKINT Mask */
\r
2291 #define PPB_SYST_CSR_CLKSOURCE_Pos 2 /*!< PPB SYST_CSR: CLKSOURCE Position */
\r
2292 #define PPB_SYST_CSR_CLKSOURCE_Msk (0x01UL << PPB_SYST_CSR_CLKSOURCE_Pos) /*!< PPB SYST_CSR: CLKSOURCE Mask */
\r
2293 #define PPB_SYST_CSR_COUNTFLAG_Pos 16 /*!< PPB SYST_CSR: COUNTFLAG Position */
\r
2294 #define PPB_SYST_CSR_COUNTFLAG_Msk (0x01UL << PPB_SYST_CSR_COUNTFLAG_Pos) /*!< PPB SYST_CSR: COUNTFLAG Mask */
\r
2296 /* -------------------------------- PPB_SYST_RVR -------------------------------- */
\r
2297 #define PPB_SYST_RVR_RELOAD_Pos 0 /*!< PPB SYST_RVR: RELOAD Position */
\r
2298 #define PPB_SYST_RVR_RELOAD_Msk (0x00ffffffUL << PPB_SYST_RVR_RELOAD_Pos) /*!< PPB SYST_RVR: RELOAD Mask */
\r
2300 /* -------------------------------- PPB_SYST_CVR -------------------------------- */
\r
2301 #define PPB_SYST_CVR_CURRENT_Pos 0 /*!< PPB SYST_CVR: CURRENT Position */
\r
2302 #define PPB_SYST_CVR_CURRENT_Msk (0x00ffffffUL << PPB_SYST_CVR_CURRENT_Pos) /*!< PPB SYST_CVR: CURRENT Mask */
\r
2304 /* ------------------------------- PPB_SYST_CALIB ------------------------------- */
\r
2305 #define PPB_SYST_CALIB_TENMS_Pos 0 /*!< PPB SYST_CALIB: TENMS Position */
\r
2306 #define PPB_SYST_CALIB_TENMS_Msk (0x00ffffffUL << PPB_SYST_CALIB_TENMS_Pos) /*!< PPB SYST_CALIB: TENMS Mask */
\r
2307 #define PPB_SYST_CALIB_SKEW_Pos 30 /*!< PPB SYST_CALIB: SKEW Position */
\r
2308 #define PPB_SYST_CALIB_SKEW_Msk (0x01UL << PPB_SYST_CALIB_SKEW_Pos) /*!< PPB SYST_CALIB: SKEW Mask */
\r
2309 #define PPB_SYST_CALIB_NOREF_Pos 31 /*!< PPB SYST_CALIB: NOREF Position */
\r
2310 #define PPB_SYST_CALIB_NOREF_Msk (0x01UL << PPB_SYST_CALIB_NOREF_Pos) /*!< PPB SYST_CALIB: NOREF Mask */
\r
2312 /* ------------------------------- PPB_NVIC_ISER0 ------------------------------- */
\r
2313 #define PPB_NVIC_ISER0_SETENA_Pos 0 /*!< PPB NVIC_ISER0: SETENA Position */
\r
2314 #define PPB_NVIC_ISER0_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER0_SETENA_Pos) /*!< PPB NVIC_ISER0: SETENA Mask */
\r
2316 /* ------------------------------- PPB_NVIC_ISER1 ------------------------------- */
\r
2317 #define PPB_NVIC_ISER1_SETENA_Pos 0 /*!< PPB NVIC_ISER1: SETENA Position */
\r
2318 #define PPB_NVIC_ISER1_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER1_SETENA_Pos) /*!< PPB NVIC_ISER1: SETENA Mask */
\r
2320 /* ------------------------------- PPB_NVIC_ISER2 ------------------------------- */
\r
2321 #define PPB_NVIC_ISER2_SETENA_Pos 0 /*!< PPB NVIC_ISER2: SETENA Position */
\r
2322 #define PPB_NVIC_ISER2_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER2_SETENA_Pos) /*!< PPB NVIC_ISER2: SETENA Mask */
\r
2324 /* ------------------------------- PPB_NVIC_ISER3 ------------------------------- */
\r
2325 #define PPB_NVIC_ISER3_SETENA_Pos 0 /*!< PPB NVIC_ISER3: SETENA Position */
\r
2326 #define PPB_NVIC_ISER3_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER3_SETENA_Pos) /*!< PPB NVIC_ISER3: SETENA Mask */
\r
2328 /* ------------------------------- PPB_NVIC_ICER0 ------------------------------- */
\r
2329 #define PPB_NVIC_ICER0_CLRENA_Pos 0 /*!< PPB NVIC_ICER0: CLRENA Position */
\r
2330 #define PPB_NVIC_ICER0_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER0_CLRENA_Pos) /*!< PPB NVIC_ICER0: CLRENA Mask */
\r
2332 /* ------------------------------- PPB_NVIC_ICER1 ------------------------------- */
\r
2333 #define PPB_NVIC_ICER1_CLRENA_Pos 0 /*!< PPB NVIC_ICER1: CLRENA Position */
\r
2334 #define PPB_NVIC_ICER1_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER1_CLRENA_Pos) /*!< PPB NVIC_ICER1: CLRENA Mask */
\r
2336 /* ------------------------------- PPB_NVIC_ICER2 ------------------------------- */
\r
2337 #define PPB_NVIC_ICER2_CLRENA_Pos 0 /*!< PPB NVIC_ICER2: CLRENA Position */
\r
2338 #define PPB_NVIC_ICER2_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER2_CLRENA_Pos) /*!< PPB NVIC_ICER2: CLRENA Mask */
\r
2340 /* ------------------------------- PPB_NVIC_ICER3 ------------------------------- */
\r
2341 #define PPB_NVIC_ICER3_CLRENA_Pos 0 /*!< PPB NVIC_ICER3: CLRENA Position */
\r
2342 #define PPB_NVIC_ICER3_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER3_CLRENA_Pos) /*!< PPB NVIC_ICER3: CLRENA Mask */
\r
2344 /* ------------------------------- PPB_NVIC_ISPR0 ------------------------------- */
\r
2345 #define PPB_NVIC_ISPR0_SETPEND_Pos 0 /*!< PPB NVIC_ISPR0: SETPEND Position */
\r
2346 #define PPB_NVIC_ISPR0_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR0_SETPEND_Pos) /*!< PPB NVIC_ISPR0: SETPEND Mask */
\r
2348 /* ------------------------------- PPB_NVIC_ISPR1 ------------------------------- */
\r
2349 #define PPB_NVIC_ISPR1_SETPEND_Pos 0 /*!< PPB NVIC_ISPR1: SETPEND Position */
\r
2350 #define PPB_NVIC_ISPR1_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR1_SETPEND_Pos) /*!< PPB NVIC_ISPR1: SETPEND Mask */
\r
2352 /* ------------------------------- PPB_NVIC_ISPR2 ------------------------------- */
\r
2353 #define PPB_NVIC_ISPR2_SETPEND_Pos 0 /*!< PPB NVIC_ISPR2: SETPEND Position */
\r
2354 #define PPB_NVIC_ISPR2_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR2_SETPEND_Pos) /*!< PPB NVIC_ISPR2: SETPEND Mask */
\r
2356 /* ------------------------------- PPB_NVIC_ISPR3 ------------------------------- */
\r
2357 #define PPB_NVIC_ISPR3_SETPEND_Pos 0 /*!< PPB NVIC_ISPR3: SETPEND Position */
\r
2358 #define PPB_NVIC_ISPR3_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR3_SETPEND_Pos) /*!< PPB NVIC_ISPR3: SETPEND Mask */
\r
2360 /* ------------------------------- PPB_NVIC_ICPR0 ------------------------------- */
\r
2361 #define PPB_NVIC_ICPR0_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR0: CLRPEND Position */
\r
2362 #define PPB_NVIC_ICPR0_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR0_CLRPEND_Pos) /*!< PPB NVIC_ICPR0: CLRPEND Mask */
\r
2364 /* ------------------------------- PPB_NVIC_ICPR1 ------------------------------- */
\r
2365 #define PPB_NVIC_ICPR1_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR1: CLRPEND Position */
\r
2366 #define PPB_NVIC_ICPR1_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR1_CLRPEND_Pos) /*!< PPB NVIC_ICPR1: CLRPEND Mask */
\r
2368 /* ------------------------------- PPB_NVIC_ICPR2 ------------------------------- */
\r
2369 #define PPB_NVIC_ICPR2_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR2: CLRPEND Position */
\r
2370 #define PPB_NVIC_ICPR2_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR2_CLRPEND_Pos) /*!< PPB NVIC_ICPR2: CLRPEND Mask */
\r
2372 /* ------------------------------- PPB_NVIC_ICPR3 ------------------------------- */
\r
2373 #define PPB_NVIC_ICPR3_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR3: CLRPEND Position */
\r
2374 #define PPB_NVIC_ICPR3_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR3_CLRPEND_Pos) /*!< PPB NVIC_ICPR3: CLRPEND Mask */
\r
2376 /* ------------------------------- PPB_NVIC_IABR0 ------------------------------- */
\r
2377 #define PPB_NVIC_IABR0_ACTIVE_Pos 0 /*!< PPB NVIC_IABR0: ACTIVE Position */
\r
2378 #define PPB_NVIC_IABR0_ACTIVE_Msk (0xffffffffUL << PPB_NVIC_IABR0_ACTIVE_Pos) /*!< PPB NVIC_IABR0: ACTIVE Mask */
\r
2380 /* ------------------------------- PPB_NVIC_IABR1 ------------------------------- */
\r
2381 #define PPB_NVIC_IABR1_ACTIVE_Pos 0 /*!< PPB NVIC_IABR1: ACTIVE Position */
\r
2382 #define PPB_NVIC_IABR1_ACTIVE_Msk (0xffffffffUL << PPB_NVIC_IABR1_ACTIVE_Pos) /*!< PPB NVIC_IABR1: ACTIVE Mask */
\r
2384 /* ------------------------------- PPB_NVIC_IABR2 ------------------------------- */
\r
2385 #define PPB_NVIC_IABR2_ACTIVE_Pos 0 /*!< PPB NVIC_IABR2: ACTIVE Position */
\r
2386 #define PPB_NVIC_IABR2_ACTIVE_Msk (0xffffffffUL << PPB_NVIC_IABR2_ACTIVE_Pos) /*!< PPB NVIC_IABR2: ACTIVE Mask */
\r
2388 /* ------------------------------- PPB_NVIC_IABR3 ------------------------------- */
\r
2389 #define PPB_NVIC_IABR3_ACTIVE_Pos 0 /*!< PPB NVIC_IABR3: ACTIVE Position */
\r
2390 #define PPB_NVIC_IABR3_ACTIVE_Msk (0xffffffffUL << PPB_NVIC_IABR3_ACTIVE_Pos) /*!< PPB NVIC_IABR3: ACTIVE Mask */
\r
2392 /* -------------------------------- PPB_NVIC_IPR0 ------------------------------- */
\r
2393 #define PPB_NVIC_IPR0_PRI_0_Pos 0 /*!< PPB NVIC_IPR0: PRI_0 Position */
\r
2394 #define PPB_NVIC_IPR0_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_0_Pos) /*!< PPB NVIC_IPR0: PRI_0 Mask */
\r
2395 #define PPB_NVIC_IPR0_PRI_1_Pos 8 /*!< PPB NVIC_IPR0: PRI_1 Position */
\r
2396 #define PPB_NVIC_IPR0_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_1_Pos) /*!< PPB NVIC_IPR0: PRI_1 Mask */
\r
2397 #define PPB_NVIC_IPR0_PRI_2_Pos 16 /*!< PPB NVIC_IPR0: PRI_2 Position */
\r
2398 #define PPB_NVIC_IPR0_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_2_Pos) /*!< PPB NVIC_IPR0: PRI_2 Mask */
\r
2399 #define PPB_NVIC_IPR0_PRI_3_Pos 24 /*!< PPB NVIC_IPR0: PRI_3 Position */
\r
2400 #define PPB_NVIC_IPR0_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_3_Pos) /*!< PPB NVIC_IPR0: PRI_3 Mask */
\r
2402 /* -------------------------------- PPB_NVIC_IPR1 ------------------------------- */
\r
2403 #define PPB_NVIC_IPR1_PRI_0_Pos 0 /*!< PPB NVIC_IPR1: PRI_0 Position */
\r
2404 #define PPB_NVIC_IPR1_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_0_Pos) /*!< PPB NVIC_IPR1: PRI_0 Mask */
\r
2405 #define PPB_NVIC_IPR1_PRI_1_Pos 8 /*!< PPB NVIC_IPR1: PRI_1 Position */
\r
2406 #define PPB_NVIC_IPR1_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_1_Pos) /*!< PPB NVIC_IPR1: PRI_1 Mask */
\r
2407 #define PPB_NVIC_IPR1_PRI_2_Pos 16 /*!< PPB NVIC_IPR1: PRI_2 Position */
\r
2408 #define PPB_NVIC_IPR1_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_2_Pos) /*!< PPB NVIC_IPR1: PRI_2 Mask */
\r
2409 #define PPB_NVIC_IPR1_PRI_3_Pos 24 /*!< PPB NVIC_IPR1: PRI_3 Position */
\r
2410 #define PPB_NVIC_IPR1_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_3_Pos) /*!< PPB NVIC_IPR1: PRI_3 Mask */
\r
2412 /* -------------------------------- PPB_NVIC_IPR2 ------------------------------- */
\r
2413 #define PPB_NVIC_IPR2_PRI_0_Pos 0 /*!< PPB NVIC_IPR2: PRI_0 Position */
\r
2414 #define PPB_NVIC_IPR2_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_0_Pos) /*!< PPB NVIC_IPR2: PRI_0 Mask */
\r
2415 #define PPB_NVIC_IPR2_PRI_1_Pos 8 /*!< PPB NVIC_IPR2: PRI_1 Position */
\r
2416 #define PPB_NVIC_IPR2_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_1_Pos) /*!< PPB NVIC_IPR2: PRI_1 Mask */
\r
2417 #define PPB_NVIC_IPR2_PRI_2_Pos 16 /*!< PPB NVIC_IPR2: PRI_2 Position */
\r
2418 #define PPB_NVIC_IPR2_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_2_Pos) /*!< PPB NVIC_IPR2: PRI_2 Mask */
\r
2419 #define PPB_NVIC_IPR2_PRI_3_Pos 24 /*!< PPB NVIC_IPR2: PRI_3 Position */
\r
2420 #define PPB_NVIC_IPR2_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_3_Pos) /*!< PPB NVIC_IPR2: PRI_3 Mask */
\r
2422 /* -------------------------------- PPB_NVIC_IPR3 ------------------------------- */
\r
2423 #define PPB_NVIC_IPR3_PRI_0_Pos 0 /*!< PPB NVIC_IPR3: PRI_0 Position */
\r
2424 #define PPB_NVIC_IPR3_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_0_Pos) /*!< PPB NVIC_IPR3: PRI_0 Mask */
\r
2425 #define PPB_NVIC_IPR3_PRI_1_Pos 8 /*!< PPB NVIC_IPR3: PRI_1 Position */
\r
2426 #define PPB_NVIC_IPR3_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_1_Pos) /*!< PPB NVIC_IPR3: PRI_1 Mask */
\r
2427 #define PPB_NVIC_IPR3_PRI_2_Pos 16 /*!< PPB NVIC_IPR3: PRI_2 Position */
\r
2428 #define PPB_NVIC_IPR3_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_2_Pos) /*!< PPB NVIC_IPR3: PRI_2 Mask */
\r
2429 #define PPB_NVIC_IPR3_PRI_3_Pos 24 /*!< PPB NVIC_IPR3: PRI_3 Position */
\r
2430 #define PPB_NVIC_IPR3_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_3_Pos) /*!< PPB NVIC_IPR3: PRI_3 Mask */
\r
2432 /* -------------------------------- PPB_NVIC_IPR4 ------------------------------- */
\r
2433 #define PPB_NVIC_IPR4_PRI_0_Pos 0 /*!< PPB NVIC_IPR4: PRI_0 Position */
\r
2434 #define PPB_NVIC_IPR4_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_0_Pos) /*!< PPB NVIC_IPR4: PRI_0 Mask */
\r
2435 #define PPB_NVIC_IPR4_PRI_1_Pos 8 /*!< PPB NVIC_IPR4: PRI_1 Position */
\r
2436 #define PPB_NVIC_IPR4_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_1_Pos) /*!< PPB NVIC_IPR4: PRI_1 Mask */
\r
2437 #define PPB_NVIC_IPR4_PRI_2_Pos 16 /*!< PPB NVIC_IPR4: PRI_2 Position */
\r
2438 #define PPB_NVIC_IPR4_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_2_Pos) /*!< PPB NVIC_IPR4: PRI_2 Mask */
\r
2439 #define PPB_NVIC_IPR4_PRI_3_Pos 24 /*!< PPB NVIC_IPR4: PRI_3 Position */
\r
2440 #define PPB_NVIC_IPR4_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_3_Pos) /*!< PPB NVIC_IPR4: PRI_3 Mask */
\r
2442 /* -------------------------------- PPB_NVIC_IPR5 ------------------------------- */
\r
2443 #define PPB_NVIC_IPR5_PRI_0_Pos 0 /*!< PPB NVIC_IPR5: PRI_0 Position */
\r
2444 #define PPB_NVIC_IPR5_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_0_Pos) /*!< PPB NVIC_IPR5: PRI_0 Mask */
\r
2445 #define PPB_NVIC_IPR5_PRI_1_Pos 8 /*!< PPB NVIC_IPR5: PRI_1 Position */
\r
2446 #define PPB_NVIC_IPR5_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_1_Pos) /*!< PPB NVIC_IPR5: PRI_1 Mask */
\r
2447 #define PPB_NVIC_IPR5_PRI_2_Pos 16 /*!< PPB NVIC_IPR5: PRI_2 Position */
\r
2448 #define PPB_NVIC_IPR5_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_2_Pos) /*!< PPB NVIC_IPR5: PRI_2 Mask */
\r
2449 #define PPB_NVIC_IPR5_PRI_3_Pos 24 /*!< PPB NVIC_IPR5: PRI_3 Position */
\r
2450 #define PPB_NVIC_IPR5_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_3_Pos) /*!< PPB NVIC_IPR5: PRI_3 Mask */
\r
2452 /* -------------------------------- PPB_NVIC_IPR6 ------------------------------- */
\r
2453 #define PPB_NVIC_IPR6_PRI_0_Pos 0 /*!< PPB NVIC_IPR6: PRI_0 Position */
\r
2454 #define PPB_NVIC_IPR6_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_0_Pos) /*!< PPB NVIC_IPR6: PRI_0 Mask */
\r
2455 #define PPB_NVIC_IPR6_PRI_1_Pos 8 /*!< PPB NVIC_IPR6: PRI_1 Position */
\r
2456 #define PPB_NVIC_IPR6_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_1_Pos) /*!< PPB NVIC_IPR6: PRI_1 Mask */
\r
2457 #define PPB_NVIC_IPR6_PRI_2_Pos 16 /*!< PPB NVIC_IPR6: PRI_2 Position */
\r
2458 #define PPB_NVIC_IPR6_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_2_Pos) /*!< PPB NVIC_IPR6: PRI_2 Mask */
\r
2459 #define PPB_NVIC_IPR6_PRI_3_Pos 24 /*!< PPB NVIC_IPR6: PRI_3 Position */
\r
2460 #define PPB_NVIC_IPR6_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_3_Pos) /*!< PPB NVIC_IPR6: PRI_3 Mask */
\r
2462 /* -------------------------------- PPB_NVIC_IPR7 ------------------------------- */
\r
2463 #define PPB_NVIC_IPR7_PRI_0_Pos 0 /*!< PPB NVIC_IPR7: PRI_0 Position */
\r
2464 #define PPB_NVIC_IPR7_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_0_Pos) /*!< PPB NVIC_IPR7: PRI_0 Mask */
\r
2465 #define PPB_NVIC_IPR7_PRI_1_Pos 8 /*!< PPB NVIC_IPR7: PRI_1 Position */
\r
2466 #define PPB_NVIC_IPR7_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_1_Pos) /*!< PPB NVIC_IPR7: PRI_1 Mask */
\r
2467 #define PPB_NVIC_IPR7_PRI_2_Pos 16 /*!< PPB NVIC_IPR7: PRI_2 Position */
\r
2468 #define PPB_NVIC_IPR7_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_2_Pos) /*!< PPB NVIC_IPR7: PRI_2 Mask */
\r
2469 #define PPB_NVIC_IPR7_PRI_3_Pos 24 /*!< PPB NVIC_IPR7: PRI_3 Position */
\r
2470 #define PPB_NVIC_IPR7_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_3_Pos) /*!< PPB NVIC_IPR7: PRI_3 Mask */
\r
2472 /* -------------------------------- PPB_NVIC_IPR8 ------------------------------- */
\r
2473 #define PPB_NVIC_IPR8_PRI_0_Pos 0 /*!< PPB NVIC_IPR8: PRI_0 Position */
\r
2474 #define PPB_NVIC_IPR8_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR8_PRI_0_Pos) /*!< PPB NVIC_IPR8: PRI_0 Mask */
\r
2475 #define PPB_NVIC_IPR8_PRI_1_Pos 8 /*!< PPB NVIC_IPR8: PRI_1 Position */
\r
2476 #define PPB_NVIC_IPR8_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR8_PRI_1_Pos) /*!< PPB NVIC_IPR8: PRI_1 Mask */
\r
2477 #define PPB_NVIC_IPR8_PRI_2_Pos 16 /*!< PPB NVIC_IPR8: PRI_2 Position */
\r
2478 #define PPB_NVIC_IPR8_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR8_PRI_2_Pos) /*!< PPB NVIC_IPR8: PRI_2 Mask */
\r
2479 #define PPB_NVIC_IPR8_PRI_3_Pos 24 /*!< PPB NVIC_IPR8: PRI_3 Position */
\r
2480 #define PPB_NVIC_IPR8_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR8_PRI_3_Pos) /*!< PPB NVIC_IPR8: PRI_3 Mask */
\r
2482 /* -------------------------------- PPB_NVIC_IPR9 ------------------------------- */
\r
2483 #define PPB_NVIC_IPR9_PRI_0_Pos 0 /*!< PPB NVIC_IPR9: PRI_0 Position */
\r
2484 #define PPB_NVIC_IPR9_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR9_PRI_0_Pos) /*!< PPB NVIC_IPR9: PRI_0 Mask */
\r
2485 #define PPB_NVIC_IPR9_PRI_1_Pos 8 /*!< PPB NVIC_IPR9: PRI_1 Position */
\r
2486 #define PPB_NVIC_IPR9_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR9_PRI_1_Pos) /*!< PPB NVIC_IPR9: PRI_1 Mask */
\r
2487 #define PPB_NVIC_IPR9_PRI_2_Pos 16 /*!< PPB NVIC_IPR9: PRI_2 Position */
\r
2488 #define PPB_NVIC_IPR9_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR9_PRI_2_Pos) /*!< PPB NVIC_IPR9: PRI_2 Mask */
\r
2489 #define PPB_NVIC_IPR9_PRI_3_Pos 24 /*!< PPB NVIC_IPR9: PRI_3 Position */
\r
2490 #define PPB_NVIC_IPR9_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR9_PRI_3_Pos) /*!< PPB NVIC_IPR9: PRI_3 Mask */
\r
2492 /* ------------------------------- PPB_NVIC_IPR10 ------------------------------- */
\r
2493 #define PPB_NVIC_IPR10_PRI_0_Pos 0 /*!< PPB NVIC_IPR10: PRI_0 Position */
\r
2494 #define PPB_NVIC_IPR10_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR10_PRI_0_Pos) /*!< PPB NVIC_IPR10: PRI_0 Mask */
\r
2495 #define PPB_NVIC_IPR10_PRI_1_Pos 8 /*!< PPB NVIC_IPR10: PRI_1 Position */
\r
2496 #define PPB_NVIC_IPR10_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR10_PRI_1_Pos) /*!< PPB NVIC_IPR10: PRI_1 Mask */
\r
2497 #define PPB_NVIC_IPR10_PRI_2_Pos 16 /*!< PPB NVIC_IPR10: PRI_2 Position */
\r
2498 #define PPB_NVIC_IPR10_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR10_PRI_2_Pos) /*!< PPB NVIC_IPR10: PRI_2 Mask */
\r
2499 #define PPB_NVIC_IPR10_PRI_3_Pos 24 /*!< PPB NVIC_IPR10: PRI_3 Position */
\r
2500 #define PPB_NVIC_IPR10_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR10_PRI_3_Pos) /*!< PPB NVIC_IPR10: PRI_3 Mask */
\r
2502 /* ------------------------------- PPB_NVIC_IPR11 ------------------------------- */
\r
2503 #define PPB_NVIC_IPR11_PRI_0_Pos 0 /*!< PPB NVIC_IPR11: PRI_0 Position */
\r
2504 #define PPB_NVIC_IPR11_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR11_PRI_0_Pos) /*!< PPB NVIC_IPR11: PRI_0 Mask */
\r
2505 #define PPB_NVIC_IPR11_PRI_1_Pos 8 /*!< PPB NVIC_IPR11: PRI_1 Position */
\r
2506 #define PPB_NVIC_IPR11_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR11_PRI_1_Pos) /*!< PPB NVIC_IPR11: PRI_1 Mask */
\r
2507 #define PPB_NVIC_IPR11_PRI_2_Pos 16 /*!< PPB NVIC_IPR11: PRI_2 Position */
\r
2508 #define PPB_NVIC_IPR11_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR11_PRI_2_Pos) /*!< PPB NVIC_IPR11: PRI_2 Mask */
\r
2509 #define PPB_NVIC_IPR11_PRI_3_Pos 24 /*!< PPB NVIC_IPR11: PRI_3 Position */
\r
2510 #define PPB_NVIC_IPR11_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR11_PRI_3_Pos) /*!< PPB NVIC_IPR11: PRI_3 Mask */
\r
2512 /* ------------------------------- PPB_NVIC_IPR12 ------------------------------- */
\r
2513 #define PPB_NVIC_IPR12_PRI_0_Pos 0 /*!< PPB NVIC_IPR12: PRI_0 Position */
\r
2514 #define PPB_NVIC_IPR12_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR12_PRI_0_Pos) /*!< PPB NVIC_IPR12: PRI_0 Mask */
\r
2515 #define PPB_NVIC_IPR12_PRI_1_Pos 8 /*!< PPB NVIC_IPR12: PRI_1 Position */
\r
2516 #define PPB_NVIC_IPR12_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR12_PRI_1_Pos) /*!< PPB NVIC_IPR12: PRI_1 Mask */
\r
2517 #define PPB_NVIC_IPR12_PRI_2_Pos 16 /*!< PPB NVIC_IPR12: PRI_2 Position */
\r
2518 #define PPB_NVIC_IPR12_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR12_PRI_2_Pos) /*!< PPB NVIC_IPR12: PRI_2 Mask */
\r
2519 #define PPB_NVIC_IPR12_PRI_3_Pos 24 /*!< PPB NVIC_IPR12: PRI_3 Position */
\r
2520 #define PPB_NVIC_IPR12_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR12_PRI_3_Pos) /*!< PPB NVIC_IPR12: PRI_3 Mask */
\r
2522 /* ------------------------------- PPB_NVIC_IPR13 ------------------------------- */
\r
2523 #define PPB_NVIC_IPR13_PRI_0_Pos 0 /*!< PPB NVIC_IPR13: PRI_0 Position */
\r
2524 #define PPB_NVIC_IPR13_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR13_PRI_0_Pos) /*!< PPB NVIC_IPR13: PRI_0 Mask */
\r
2525 #define PPB_NVIC_IPR13_PRI_1_Pos 8 /*!< PPB NVIC_IPR13: PRI_1 Position */
\r
2526 #define PPB_NVIC_IPR13_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR13_PRI_1_Pos) /*!< PPB NVIC_IPR13: PRI_1 Mask */
\r
2527 #define PPB_NVIC_IPR13_PRI_2_Pos 16 /*!< PPB NVIC_IPR13: PRI_2 Position */
\r
2528 #define PPB_NVIC_IPR13_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR13_PRI_2_Pos) /*!< PPB NVIC_IPR13: PRI_2 Mask */
\r
2529 #define PPB_NVIC_IPR13_PRI_3_Pos 24 /*!< PPB NVIC_IPR13: PRI_3 Position */
\r
2530 #define PPB_NVIC_IPR13_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR13_PRI_3_Pos) /*!< PPB NVIC_IPR13: PRI_3 Mask */
\r
2532 /* ------------------------------- PPB_NVIC_IPR14 ------------------------------- */
\r
2533 #define PPB_NVIC_IPR14_PRI_0_Pos 0 /*!< PPB NVIC_IPR14: PRI_0 Position */
\r
2534 #define PPB_NVIC_IPR14_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR14_PRI_0_Pos) /*!< PPB NVIC_IPR14: PRI_0 Mask */
\r
2535 #define PPB_NVIC_IPR14_PRI_1_Pos 8 /*!< PPB NVIC_IPR14: PRI_1 Position */
\r
2536 #define PPB_NVIC_IPR14_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR14_PRI_1_Pos) /*!< PPB NVIC_IPR14: PRI_1 Mask */
\r
2537 #define PPB_NVIC_IPR14_PRI_2_Pos 16 /*!< PPB NVIC_IPR14: PRI_2 Position */
\r
2538 #define PPB_NVIC_IPR14_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR14_PRI_2_Pos) /*!< PPB NVIC_IPR14: PRI_2 Mask */
\r
2539 #define PPB_NVIC_IPR14_PRI_3_Pos 24 /*!< PPB NVIC_IPR14: PRI_3 Position */
\r
2540 #define PPB_NVIC_IPR14_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR14_PRI_3_Pos) /*!< PPB NVIC_IPR14: PRI_3 Mask */
\r
2542 /* ------------------------------- PPB_NVIC_IPR15 ------------------------------- */
\r
2543 #define PPB_NVIC_IPR15_PRI_0_Pos 0 /*!< PPB NVIC_IPR15: PRI_0 Position */
\r
2544 #define PPB_NVIC_IPR15_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR15_PRI_0_Pos) /*!< PPB NVIC_IPR15: PRI_0 Mask */
\r
2545 #define PPB_NVIC_IPR15_PRI_1_Pos 8 /*!< PPB NVIC_IPR15: PRI_1 Position */
\r
2546 #define PPB_NVIC_IPR15_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR15_PRI_1_Pos) /*!< PPB NVIC_IPR15: PRI_1 Mask */
\r
2547 #define PPB_NVIC_IPR15_PRI_2_Pos 16 /*!< PPB NVIC_IPR15: PRI_2 Position */
\r
2548 #define PPB_NVIC_IPR15_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR15_PRI_2_Pos) /*!< PPB NVIC_IPR15: PRI_2 Mask */
\r
2549 #define PPB_NVIC_IPR15_PRI_3_Pos 24 /*!< PPB NVIC_IPR15: PRI_3 Position */
\r
2550 #define PPB_NVIC_IPR15_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR15_PRI_3_Pos) /*!< PPB NVIC_IPR15: PRI_3 Mask */
\r
2552 /* ------------------------------- PPB_NVIC_IPR16 ------------------------------- */
\r
2553 #define PPB_NVIC_IPR16_PRI_0_Pos 0 /*!< PPB NVIC_IPR16: PRI_0 Position */
\r
2554 #define PPB_NVIC_IPR16_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR16_PRI_0_Pos) /*!< PPB NVIC_IPR16: PRI_0 Mask */
\r
2555 #define PPB_NVIC_IPR16_PRI_1_Pos 8 /*!< PPB NVIC_IPR16: PRI_1 Position */
\r
2556 #define PPB_NVIC_IPR16_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR16_PRI_1_Pos) /*!< PPB NVIC_IPR16: PRI_1 Mask */
\r
2557 #define PPB_NVIC_IPR16_PRI_2_Pos 16 /*!< PPB NVIC_IPR16: PRI_2 Position */
\r
2558 #define PPB_NVIC_IPR16_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR16_PRI_2_Pos) /*!< PPB NVIC_IPR16: PRI_2 Mask */
\r
2559 #define PPB_NVIC_IPR16_PRI_3_Pos 24 /*!< PPB NVIC_IPR16: PRI_3 Position */
\r
2560 #define PPB_NVIC_IPR16_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR16_PRI_3_Pos) /*!< PPB NVIC_IPR16: PRI_3 Mask */
\r
2562 /* ------------------------------- PPB_NVIC_IPR17 ------------------------------- */
\r
2563 #define PPB_NVIC_IPR17_PRI_0_Pos 0 /*!< PPB NVIC_IPR17: PRI_0 Position */
\r
2564 #define PPB_NVIC_IPR17_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR17_PRI_0_Pos) /*!< PPB NVIC_IPR17: PRI_0 Mask */
\r
2565 #define PPB_NVIC_IPR17_PRI_1_Pos 8 /*!< PPB NVIC_IPR17: PRI_1 Position */
\r
2566 #define PPB_NVIC_IPR17_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR17_PRI_1_Pos) /*!< PPB NVIC_IPR17: PRI_1 Mask */
\r
2567 #define PPB_NVIC_IPR17_PRI_2_Pos 16 /*!< PPB NVIC_IPR17: PRI_2 Position */
\r
2568 #define PPB_NVIC_IPR17_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR17_PRI_2_Pos) /*!< PPB NVIC_IPR17: PRI_2 Mask */
\r
2569 #define PPB_NVIC_IPR17_PRI_3_Pos 24 /*!< PPB NVIC_IPR17: PRI_3 Position */
\r
2570 #define PPB_NVIC_IPR17_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR17_PRI_3_Pos) /*!< PPB NVIC_IPR17: PRI_3 Mask */
\r
2572 /* ------------------------------- PPB_NVIC_IPR18 ------------------------------- */
\r
2573 #define PPB_NVIC_IPR18_PRI_0_Pos 0 /*!< PPB NVIC_IPR18: PRI_0 Position */
\r
2574 #define PPB_NVIC_IPR18_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR18_PRI_0_Pos) /*!< PPB NVIC_IPR18: PRI_0 Mask */
\r
2575 #define PPB_NVIC_IPR18_PRI_1_Pos 8 /*!< PPB NVIC_IPR18: PRI_1 Position */
\r
2576 #define PPB_NVIC_IPR18_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR18_PRI_1_Pos) /*!< PPB NVIC_IPR18: PRI_1 Mask */
\r
2577 #define PPB_NVIC_IPR18_PRI_2_Pos 16 /*!< PPB NVIC_IPR18: PRI_2 Position */
\r
2578 #define PPB_NVIC_IPR18_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR18_PRI_2_Pos) /*!< PPB NVIC_IPR18: PRI_2 Mask */
\r
2579 #define PPB_NVIC_IPR18_PRI_3_Pos 24 /*!< PPB NVIC_IPR18: PRI_3 Position */
\r
2580 #define PPB_NVIC_IPR18_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR18_PRI_3_Pos) /*!< PPB NVIC_IPR18: PRI_3 Mask */
\r
2582 /* ------------------------------- PPB_NVIC_IPR19 ------------------------------- */
\r
2583 #define PPB_NVIC_IPR19_PRI_0_Pos 0 /*!< PPB NVIC_IPR19: PRI_0 Position */
\r
2584 #define PPB_NVIC_IPR19_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR19_PRI_0_Pos) /*!< PPB NVIC_IPR19: PRI_0 Mask */
\r
2585 #define PPB_NVIC_IPR19_PRI_1_Pos 8 /*!< PPB NVIC_IPR19: PRI_1 Position */
\r
2586 #define PPB_NVIC_IPR19_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR19_PRI_1_Pos) /*!< PPB NVIC_IPR19: PRI_1 Mask */
\r
2587 #define PPB_NVIC_IPR19_PRI_2_Pos 16 /*!< PPB NVIC_IPR19: PRI_2 Position */
\r
2588 #define PPB_NVIC_IPR19_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR19_PRI_2_Pos) /*!< PPB NVIC_IPR19: PRI_2 Mask */
\r
2589 #define PPB_NVIC_IPR19_PRI_3_Pos 24 /*!< PPB NVIC_IPR19: PRI_3 Position */
\r
2590 #define PPB_NVIC_IPR19_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR19_PRI_3_Pos) /*!< PPB NVIC_IPR19: PRI_3 Mask */
\r
2592 /* ------------------------------- PPB_NVIC_IPR20 ------------------------------- */
\r
2593 #define PPB_NVIC_IPR20_PRI_0_Pos 0 /*!< PPB NVIC_IPR20: PRI_0 Position */
\r
2594 #define PPB_NVIC_IPR20_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR20_PRI_0_Pos) /*!< PPB NVIC_IPR20: PRI_0 Mask */
\r
2595 #define PPB_NVIC_IPR20_PRI_1_Pos 8 /*!< PPB NVIC_IPR20: PRI_1 Position */
\r
2596 #define PPB_NVIC_IPR20_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR20_PRI_1_Pos) /*!< PPB NVIC_IPR20: PRI_1 Mask */
\r
2597 #define PPB_NVIC_IPR20_PRI_2_Pos 16 /*!< PPB NVIC_IPR20: PRI_2 Position */
\r
2598 #define PPB_NVIC_IPR20_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR20_PRI_2_Pos) /*!< PPB NVIC_IPR20: PRI_2 Mask */
\r
2599 #define PPB_NVIC_IPR20_PRI_3_Pos 24 /*!< PPB NVIC_IPR20: PRI_3 Position */
\r
2600 #define PPB_NVIC_IPR20_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR20_PRI_3_Pos) /*!< PPB NVIC_IPR20: PRI_3 Mask */
\r
2602 /* ------------------------------- PPB_NVIC_IPR21 ------------------------------- */
\r
2603 #define PPB_NVIC_IPR21_PRI_0_Pos 0 /*!< PPB NVIC_IPR21: PRI_0 Position */
\r
2604 #define PPB_NVIC_IPR21_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR21_PRI_0_Pos) /*!< PPB NVIC_IPR21: PRI_0 Mask */
\r
2605 #define PPB_NVIC_IPR21_PRI_1_Pos 8 /*!< PPB NVIC_IPR21: PRI_1 Position */
\r
2606 #define PPB_NVIC_IPR21_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR21_PRI_1_Pos) /*!< PPB NVIC_IPR21: PRI_1 Mask */
\r
2607 #define PPB_NVIC_IPR21_PRI_2_Pos 16 /*!< PPB NVIC_IPR21: PRI_2 Position */
\r
2608 #define PPB_NVIC_IPR21_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR21_PRI_2_Pos) /*!< PPB NVIC_IPR21: PRI_2 Mask */
\r
2609 #define PPB_NVIC_IPR21_PRI_3_Pos 24 /*!< PPB NVIC_IPR21: PRI_3 Position */
\r
2610 #define PPB_NVIC_IPR21_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR21_PRI_3_Pos) /*!< PPB NVIC_IPR21: PRI_3 Mask */
\r
2612 /* ------------------------------- PPB_NVIC_IPR22 ------------------------------- */
\r
2613 #define PPB_NVIC_IPR22_PRI_0_Pos 0 /*!< PPB NVIC_IPR22: PRI_0 Position */
\r
2614 #define PPB_NVIC_IPR22_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR22_PRI_0_Pos) /*!< PPB NVIC_IPR22: PRI_0 Mask */
\r
2615 #define PPB_NVIC_IPR22_PRI_1_Pos 8 /*!< PPB NVIC_IPR22: PRI_1 Position */
\r
2616 #define PPB_NVIC_IPR22_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR22_PRI_1_Pos) /*!< PPB NVIC_IPR22: PRI_1 Mask */
\r
2617 #define PPB_NVIC_IPR22_PRI_2_Pos 16 /*!< PPB NVIC_IPR22: PRI_2 Position */
\r
2618 #define PPB_NVIC_IPR22_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR22_PRI_2_Pos) /*!< PPB NVIC_IPR22: PRI_2 Mask */
\r
2619 #define PPB_NVIC_IPR22_PRI_3_Pos 24 /*!< PPB NVIC_IPR22: PRI_3 Position */
\r
2620 #define PPB_NVIC_IPR22_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR22_PRI_3_Pos) /*!< PPB NVIC_IPR22: PRI_3 Mask */
\r
2622 /* ------------------------------- PPB_NVIC_IPR23 ------------------------------- */
\r
2623 #define PPB_NVIC_IPR23_PRI_0_Pos 0 /*!< PPB NVIC_IPR23: PRI_0 Position */
\r
2624 #define PPB_NVIC_IPR23_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR23_PRI_0_Pos) /*!< PPB NVIC_IPR23: PRI_0 Mask */
\r
2625 #define PPB_NVIC_IPR23_PRI_1_Pos 8 /*!< PPB NVIC_IPR23: PRI_1 Position */
\r
2626 #define PPB_NVIC_IPR23_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR23_PRI_1_Pos) /*!< PPB NVIC_IPR23: PRI_1 Mask */
\r
2627 #define PPB_NVIC_IPR23_PRI_2_Pos 16 /*!< PPB NVIC_IPR23: PRI_2 Position */
\r
2628 #define PPB_NVIC_IPR23_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR23_PRI_2_Pos) /*!< PPB NVIC_IPR23: PRI_2 Mask */
\r
2629 #define PPB_NVIC_IPR23_PRI_3_Pos 24 /*!< PPB NVIC_IPR23: PRI_3 Position */
\r
2630 #define PPB_NVIC_IPR23_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR23_PRI_3_Pos) /*!< PPB NVIC_IPR23: PRI_3 Mask */
\r
2632 /* ------------------------------- PPB_NVIC_IPR24 ------------------------------- */
\r
2633 #define PPB_NVIC_IPR24_PRI_0_Pos 0 /*!< PPB NVIC_IPR24: PRI_0 Position */
\r
2634 #define PPB_NVIC_IPR24_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR24_PRI_0_Pos) /*!< PPB NVIC_IPR24: PRI_0 Mask */
\r
2635 #define PPB_NVIC_IPR24_PRI_1_Pos 8 /*!< PPB NVIC_IPR24: PRI_1 Position */
\r
2636 #define PPB_NVIC_IPR24_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR24_PRI_1_Pos) /*!< PPB NVIC_IPR24: PRI_1 Mask */
\r
2637 #define PPB_NVIC_IPR24_PRI_2_Pos 16 /*!< PPB NVIC_IPR24: PRI_2 Position */
\r
2638 #define PPB_NVIC_IPR24_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR24_PRI_2_Pos) /*!< PPB NVIC_IPR24: PRI_2 Mask */
\r
2639 #define PPB_NVIC_IPR24_PRI_3_Pos 24 /*!< PPB NVIC_IPR24: PRI_3 Position */
\r
2640 #define PPB_NVIC_IPR24_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR24_PRI_3_Pos) /*!< PPB NVIC_IPR24: PRI_3 Mask */
\r
2642 /* ------------------------------- PPB_NVIC_IPR25 ------------------------------- */
\r
2643 #define PPB_NVIC_IPR25_PRI_0_Pos 0 /*!< PPB NVIC_IPR25: PRI_0 Position */
\r
2644 #define PPB_NVIC_IPR25_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR25_PRI_0_Pos) /*!< PPB NVIC_IPR25: PRI_0 Mask */
\r
2645 #define PPB_NVIC_IPR25_PRI_1_Pos 8 /*!< PPB NVIC_IPR25: PRI_1 Position */
\r
2646 #define PPB_NVIC_IPR25_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR25_PRI_1_Pos) /*!< PPB NVIC_IPR25: PRI_1 Mask */
\r
2647 #define PPB_NVIC_IPR25_PRI_2_Pos 16 /*!< PPB NVIC_IPR25: PRI_2 Position */
\r
2648 #define PPB_NVIC_IPR25_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR25_PRI_2_Pos) /*!< PPB NVIC_IPR25: PRI_2 Mask */
\r
2649 #define PPB_NVIC_IPR25_PRI_3_Pos 24 /*!< PPB NVIC_IPR25: PRI_3 Position */
\r
2650 #define PPB_NVIC_IPR25_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR25_PRI_3_Pos) /*!< PPB NVIC_IPR25: PRI_3 Mask */
\r
2652 /* ------------------------------- PPB_NVIC_IPR26 ------------------------------- */
\r
2653 #define PPB_NVIC_IPR26_PRI_0_Pos 0 /*!< PPB NVIC_IPR26: PRI_0 Position */
\r
2654 #define PPB_NVIC_IPR26_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR26_PRI_0_Pos) /*!< PPB NVIC_IPR26: PRI_0 Mask */
\r
2655 #define PPB_NVIC_IPR26_PRI_1_Pos 8 /*!< PPB NVIC_IPR26: PRI_1 Position */
\r
2656 #define PPB_NVIC_IPR26_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR26_PRI_1_Pos) /*!< PPB NVIC_IPR26: PRI_1 Mask */
\r
2657 #define PPB_NVIC_IPR26_PRI_2_Pos 16 /*!< PPB NVIC_IPR26: PRI_2 Position */
\r
2658 #define PPB_NVIC_IPR26_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR26_PRI_2_Pos) /*!< PPB NVIC_IPR26: PRI_2 Mask */
\r
2659 #define PPB_NVIC_IPR26_PRI_3_Pos 24 /*!< PPB NVIC_IPR26: PRI_3 Position */
\r
2660 #define PPB_NVIC_IPR26_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR26_PRI_3_Pos) /*!< PPB NVIC_IPR26: PRI_3 Mask */
\r
2662 /* ------------------------------- PPB_NVIC_IPR27 ------------------------------- */
\r
2663 #define PPB_NVIC_IPR27_PRI_0_Pos 0 /*!< PPB NVIC_IPR27: PRI_0 Position */
\r
2664 #define PPB_NVIC_IPR27_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR27_PRI_0_Pos) /*!< PPB NVIC_IPR27: PRI_0 Mask */
\r
2665 #define PPB_NVIC_IPR27_PRI_1_Pos 8 /*!< PPB NVIC_IPR27: PRI_1 Position */
\r
2666 #define PPB_NVIC_IPR27_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR27_PRI_1_Pos) /*!< PPB NVIC_IPR27: PRI_1 Mask */
\r
2667 #define PPB_NVIC_IPR27_PRI_2_Pos 16 /*!< PPB NVIC_IPR27: PRI_2 Position */
\r
2668 #define PPB_NVIC_IPR27_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR27_PRI_2_Pos) /*!< PPB NVIC_IPR27: PRI_2 Mask */
\r
2669 #define PPB_NVIC_IPR27_PRI_3_Pos 24 /*!< PPB NVIC_IPR27: PRI_3 Position */
\r
2670 #define PPB_NVIC_IPR27_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR27_PRI_3_Pos) /*!< PPB NVIC_IPR27: PRI_3 Mask */
\r
2672 /* ---------------------------------- PPB_CPUID --------------------------------- */
\r
2673 #define PPB_CPUID_Revision_Pos 0 /*!< PPB CPUID: Revision Position */
\r
2674 #define PPB_CPUID_Revision_Msk (0x0fUL << PPB_CPUID_Revision_Pos) /*!< PPB CPUID: Revision Mask */
\r
2675 #define PPB_CPUID_PartNo_Pos 4 /*!< PPB CPUID: PartNo Position */
\r
2676 #define PPB_CPUID_PartNo_Msk (0x00000fffUL << PPB_CPUID_PartNo_Pos) /*!< PPB CPUID: PartNo Mask */
\r
2677 #define PPB_CPUID_Constant_Pos 16 /*!< PPB CPUID: Constant Position */
\r
2678 #define PPB_CPUID_Constant_Msk (0x0fUL << PPB_CPUID_Constant_Pos) /*!< PPB CPUID: Constant Mask */
\r
2679 #define PPB_CPUID_Variant_Pos 20 /*!< PPB CPUID: Variant Position */
\r
2680 #define PPB_CPUID_Variant_Msk (0x0fUL << PPB_CPUID_Variant_Pos) /*!< PPB CPUID: Variant Mask */
\r
2681 #define PPB_CPUID_Implementer_Pos 24 /*!< PPB CPUID: Implementer Position */
\r
2682 #define PPB_CPUID_Implementer_Msk (0x000000ffUL << PPB_CPUID_Implementer_Pos) /*!< PPB CPUID: Implementer Mask */
\r
2684 /* ---------------------------------- PPB_ICSR ---------------------------------- */
\r
2685 #define PPB_ICSR_VECTACTIVE_Pos 0 /*!< PPB ICSR: VECTACTIVE Position */
\r
2686 #define PPB_ICSR_VECTACTIVE_Msk (0x000001ffUL << PPB_ICSR_VECTACTIVE_Pos) /*!< PPB ICSR: VECTACTIVE Mask */
\r
2687 #define PPB_ICSR_RETTOBASE_Pos 11 /*!< PPB ICSR: RETTOBASE Position */
\r
2688 #define PPB_ICSR_RETTOBASE_Msk (0x01UL << PPB_ICSR_RETTOBASE_Pos) /*!< PPB ICSR: RETTOBASE Mask */
\r
2689 #define PPB_ICSR_VECTPENDING_Pos 12 /*!< PPB ICSR: VECTPENDING Position */
\r
2690 #define PPB_ICSR_VECTPENDING_Msk (0x3fUL << PPB_ICSR_VECTPENDING_Pos) /*!< PPB ICSR: VECTPENDING Mask */
\r
2691 #define PPB_ICSR_ISRPENDING_Pos 22 /*!< PPB ICSR: ISRPENDING Position */
\r
2692 #define PPB_ICSR_ISRPENDING_Msk (0x01UL << PPB_ICSR_ISRPENDING_Pos) /*!< PPB ICSR: ISRPENDING Mask */
\r
2693 #define PPB_ICSR_Res_Pos 23 /*!< PPB ICSR: Res Position */
\r
2694 #define PPB_ICSR_Res_Msk (0x01UL << PPB_ICSR_Res_Pos) /*!< PPB ICSR: Res Mask */
\r
2695 #define PPB_ICSR_PENDSTCLR_Pos 25 /*!< PPB ICSR: PENDSTCLR Position */
\r
2696 #define PPB_ICSR_PENDSTCLR_Msk (0x01UL << PPB_ICSR_PENDSTCLR_Pos) /*!< PPB ICSR: PENDSTCLR Mask */
\r
2697 #define PPB_ICSR_PENDSTSET_Pos 26 /*!< PPB ICSR: PENDSTSET Position */
\r
2698 #define PPB_ICSR_PENDSTSET_Msk (0x01UL << PPB_ICSR_PENDSTSET_Pos) /*!< PPB ICSR: PENDSTSET Mask */
\r
2699 #define PPB_ICSR_PENDSVCLR_Pos 27 /*!< PPB ICSR: PENDSVCLR Position */
\r
2700 #define PPB_ICSR_PENDSVCLR_Msk (0x01UL << PPB_ICSR_PENDSVCLR_Pos) /*!< PPB ICSR: PENDSVCLR Mask */
\r
2701 #define PPB_ICSR_PENDSVSET_Pos 28 /*!< PPB ICSR: PENDSVSET Position */
\r
2702 #define PPB_ICSR_PENDSVSET_Msk (0x01UL << PPB_ICSR_PENDSVSET_Pos) /*!< PPB ICSR: PENDSVSET Mask */
\r
2703 #define PPB_ICSR_NMIPENDSET_Pos 31 /*!< PPB ICSR: NMIPENDSET Position */
\r
2704 #define PPB_ICSR_NMIPENDSET_Msk (0x01UL << PPB_ICSR_NMIPENDSET_Pos) /*!< PPB ICSR: NMIPENDSET Mask */
\r
2706 /* ---------------------------------- PPB_VTOR ---------------------------------- */
\r
2707 #define PPB_VTOR_TBLOFF_Pos 10 /*!< PPB VTOR: TBLOFF Position */
\r
2708 #define PPB_VTOR_TBLOFF_Msk (0x003fffffUL << PPB_VTOR_TBLOFF_Pos) /*!< PPB VTOR: TBLOFF Mask */
\r
2710 /* ---------------------------------- PPB_AIRCR --------------------------------- */
\r
2711 #define PPB_AIRCR_VECTRESET_Pos 0 /*!< PPB AIRCR: VECTRESET Position */
\r
2712 #define PPB_AIRCR_VECTRESET_Msk (0x01UL << PPB_AIRCR_VECTRESET_Pos) /*!< PPB AIRCR: VECTRESET Mask */
\r
2713 #define PPB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< PPB AIRCR: VECTCLRACTIVE Position */
\r
2714 #define PPB_AIRCR_VECTCLRACTIVE_Msk (0x01UL << PPB_AIRCR_VECTCLRACTIVE_Pos) /*!< PPB AIRCR: VECTCLRACTIVE Mask */
\r
2715 #define PPB_AIRCR_SYSRESETREQ_Pos 2 /*!< PPB AIRCR: SYSRESETREQ Position */
\r
2716 #define PPB_AIRCR_SYSRESETREQ_Msk (0x01UL << PPB_AIRCR_SYSRESETREQ_Pos) /*!< PPB AIRCR: SYSRESETREQ Mask */
\r
2717 #define PPB_AIRCR_PRIGROUP_Pos 8 /*!< PPB AIRCR: PRIGROUP Position */
\r
2718 #define PPB_AIRCR_PRIGROUP_Msk (0x07UL << PPB_AIRCR_PRIGROUP_Pos) /*!< PPB AIRCR: PRIGROUP Mask */
\r
2719 #define PPB_AIRCR_ENDIANNESS_Pos 15 /*!< PPB AIRCR: ENDIANNESS Position */
\r
2720 #define PPB_AIRCR_ENDIANNESS_Msk (0x01UL << PPB_AIRCR_ENDIANNESS_Pos) /*!< PPB AIRCR: ENDIANNESS Mask */
\r
2721 #define PPB_AIRCR_VECTKEY_Pos 16 /*!< PPB AIRCR: VECTKEY Position */
\r
2722 #define PPB_AIRCR_VECTKEY_Msk (0x0000ffffUL << PPB_AIRCR_VECTKEY_Pos) /*!< PPB AIRCR: VECTKEY Mask */
\r
2724 /* ----------------------------------- PPB_SCR ---------------------------------- */
\r
2725 #define PPB_SCR_SLEEPONEXIT_Pos 1 /*!< PPB SCR: SLEEPONEXIT Position */
\r
2726 #define PPB_SCR_SLEEPONEXIT_Msk (0x01UL << PPB_SCR_SLEEPONEXIT_Pos) /*!< PPB SCR: SLEEPONEXIT Mask */
\r
2727 #define PPB_SCR_SLEEPDEEP_Pos 2 /*!< PPB SCR: SLEEPDEEP Position */
\r
2728 #define PPB_SCR_SLEEPDEEP_Msk (0x01UL << PPB_SCR_SLEEPDEEP_Pos) /*!< PPB SCR: SLEEPDEEP Mask */
\r
2729 #define PPB_SCR_SEVONPEND_Pos 4 /*!< PPB SCR: SEVONPEND Position */
\r
2730 #define PPB_SCR_SEVONPEND_Msk (0x01UL << PPB_SCR_SEVONPEND_Pos) /*!< PPB SCR: SEVONPEND Mask */
\r
2732 /* ----------------------------------- PPB_CCR ---------------------------------- */
\r
2733 #define PPB_CCR_NONBASETHRDENA_Pos 0 /*!< PPB CCR: NONBASETHRDENA Position */
\r
2734 #define PPB_CCR_NONBASETHRDENA_Msk (0x01UL << PPB_CCR_NONBASETHRDENA_Pos) /*!< PPB CCR: NONBASETHRDENA Mask */
\r
2735 #define PPB_CCR_USERSETMPEND_Pos 1 /*!< PPB CCR: USERSETMPEND Position */
\r
2736 #define PPB_CCR_USERSETMPEND_Msk (0x01UL << PPB_CCR_USERSETMPEND_Pos) /*!< PPB CCR: USERSETMPEND Mask */
\r
2737 #define PPB_CCR_UNALIGN_TRP_Pos 3 /*!< PPB CCR: UNALIGN_TRP Position */
\r
2738 #define PPB_CCR_UNALIGN_TRP_Msk (0x01UL << PPB_CCR_UNALIGN_TRP_Pos) /*!< PPB CCR: UNALIGN_TRP Mask */
\r
2739 #define PPB_CCR_DIV_0_TRP_Pos 4 /*!< PPB CCR: DIV_0_TRP Position */
\r
2740 #define PPB_CCR_DIV_0_TRP_Msk (0x01UL << PPB_CCR_DIV_0_TRP_Pos) /*!< PPB CCR: DIV_0_TRP Mask */
\r
2741 #define PPB_CCR_BFHFNMIGN_Pos 8 /*!< PPB CCR: BFHFNMIGN Position */
\r
2742 #define PPB_CCR_BFHFNMIGN_Msk (0x01UL << PPB_CCR_BFHFNMIGN_Pos) /*!< PPB CCR: BFHFNMIGN Mask */
\r
2743 #define PPB_CCR_STKALIGN_Pos 9 /*!< PPB CCR: STKALIGN Position */
\r
2744 #define PPB_CCR_STKALIGN_Msk (0x01UL << PPB_CCR_STKALIGN_Pos) /*!< PPB CCR: STKALIGN Mask */
\r
2746 /* ---------------------------------- PPB_SHPR1 --------------------------------- */
\r
2747 #define PPB_SHPR1_PRI_4_Pos 0 /*!< PPB SHPR1: PRI_4 Position */
\r
2748 #define PPB_SHPR1_PRI_4_Msk (0x000000ffUL << PPB_SHPR1_PRI_4_Pos) /*!< PPB SHPR1: PRI_4 Mask */
\r
2749 #define PPB_SHPR1_PRI_5_Pos 8 /*!< PPB SHPR1: PRI_5 Position */
\r
2750 #define PPB_SHPR1_PRI_5_Msk (0x000000ffUL << PPB_SHPR1_PRI_5_Pos) /*!< PPB SHPR1: PRI_5 Mask */
\r
2751 #define PPB_SHPR1_PRI_6_Pos 16 /*!< PPB SHPR1: PRI_6 Position */
\r
2752 #define PPB_SHPR1_PRI_6_Msk (0x000000ffUL << PPB_SHPR1_PRI_6_Pos) /*!< PPB SHPR1: PRI_6 Mask */
\r
2754 /* ---------------------------------- PPB_SHPR2 --------------------------------- */
\r
2755 #define PPB_SHPR2_PRI_11_Pos 24 /*!< PPB SHPR2: PRI_11 Position */
\r
2756 #define PPB_SHPR2_PRI_11_Msk (0x000000ffUL << PPB_SHPR2_PRI_11_Pos) /*!< PPB SHPR2: PRI_11 Mask */
\r
2758 /* ---------------------------------- PPB_SHPR3 --------------------------------- */
\r
2759 #define PPB_SHPR3_PRI_14_Pos 16 /*!< PPB SHPR3: PRI_14 Position */
\r
2760 #define PPB_SHPR3_PRI_14_Msk (0x000000ffUL << PPB_SHPR3_PRI_14_Pos) /*!< PPB SHPR3: PRI_14 Mask */
\r
2761 #define PPB_SHPR3_PRI_15_Pos 24 /*!< PPB SHPR3: PRI_15 Position */
\r
2762 #define PPB_SHPR3_PRI_15_Msk (0x000000ffUL << PPB_SHPR3_PRI_15_Pos) /*!< PPB SHPR3: PRI_15 Mask */
\r
2764 /* ---------------------------------- PPB_SHCSR --------------------------------- */
\r
2765 #define PPB_SHCSR_MEMFAULTACT_Pos 0 /*!< PPB SHCSR: MEMFAULTACT Position */
\r
2766 #define PPB_SHCSR_MEMFAULTACT_Msk (0x01UL << PPB_SHCSR_MEMFAULTACT_Pos) /*!< PPB SHCSR: MEMFAULTACT Mask */
\r
2767 #define PPB_SHCSR_BUSFAULTACT_Pos 1 /*!< PPB SHCSR: BUSFAULTACT Position */
\r
2768 #define PPB_SHCSR_BUSFAULTACT_Msk (0x01UL << PPB_SHCSR_BUSFAULTACT_Pos) /*!< PPB SHCSR: BUSFAULTACT Mask */
\r
2769 #define PPB_SHCSR_USGFAULTACT_Pos 3 /*!< PPB SHCSR: USGFAULTACT Position */
\r
2770 #define PPB_SHCSR_USGFAULTACT_Msk (0x01UL << PPB_SHCSR_USGFAULTACT_Pos) /*!< PPB SHCSR: USGFAULTACT Mask */
\r
2771 #define PPB_SHCSR_SVCALLACT_Pos 7 /*!< PPB SHCSR: SVCALLACT Position */
\r
2772 #define PPB_SHCSR_SVCALLACT_Msk (0x01UL << PPB_SHCSR_SVCALLACT_Pos) /*!< PPB SHCSR: SVCALLACT Mask */
\r
2773 #define PPB_SHCSR_MONITORACT_Pos 8 /*!< PPB SHCSR: MONITORACT Position */
\r
2774 #define PPB_SHCSR_MONITORACT_Msk (0x01UL << PPB_SHCSR_MONITORACT_Pos) /*!< PPB SHCSR: MONITORACT Mask */
\r
2775 #define PPB_SHCSR_PENDSVACT_Pos 10 /*!< PPB SHCSR: PENDSVACT Position */
\r
2776 #define PPB_SHCSR_PENDSVACT_Msk (0x01UL << PPB_SHCSR_PENDSVACT_Pos) /*!< PPB SHCSR: PENDSVACT Mask */
\r
2777 #define PPB_SHCSR_SYSTICKACT_Pos 11 /*!< PPB SHCSR: SYSTICKACT Position */
\r
2778 #define PPB_SHCSR_SYSTICKACT_Msk (0x01UL << PPB_SHCSR_SYSTICKACT_Pos) /*!< PPB SHCSR: SYSTICKACT Mask */
\r
2779 #define PPB_SHCSR_USGFAULTPENDED_Pos 12 /*!< PPB SHCSR: USGFAULTPENDED Position */
\r
2780 #define PPB_SHCSR_USGFAULTPENDED_Msk (0x01UL << PPB_SHCSR_USGFAULTPENDED_Pos) /*!< PPB SHCSR: USGFAULTPENDED Mask */
\r
2781 #define PPB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< PPB SHCSR: MEMFAULTPENDED Position */
\r
2782 #define PPB_SHCSR_MEMFAULTPENDED_Msk (0x01UL << PPB_SHCSR_MEMFAULTPENDED_Pos) /*!< PPB SHCSR: MEMFAULTPENDED Mask */
\r
2783 #define PPB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< PPB SHCSR: BUSFAULTPENDED Position */
\r
2784 #define PPB_SHCSR_BUSFAULTPENDED_Msk (0x01UL << PPB_SHCSR_BUSFAULTPENDED_Pos) /*!< PPB SHCSR: BUSFAULTPENDED Mask */
\r
2785 #define PPB_SHCSR_SVCALLPENDED_Pos 15 /*!< PPB SHCSR: SVCALLPENDED Position */
\r
2786 #define PPB_SHCSR_SVCALLPENDED_Msk (0x01UL << PPB_SHCSR_SVCALLPENDED_Pos) /*!< PPB SHCSR: SVCALLPENDED Mask */
\r
2787 #define PPB_SHCSR_MEMFAULTENA_Pos 16 /*!< PPB SHCSR: MEMFAULTENA Position */
\r
2788 #define PPB_SHCSR_MEMFAULTENA_Msk (0x01UL << PPB_SHCSR_MEMFAULTENA_Pos) /*!< PPB SHCSR: MEMFAULTENA Mask */
\r
2789 #define PPB_SHCSR_BUSFAULTENA_Pos 17 /*!< PPB SHCSR: BUSFAULTENA Position */
\r
2790 #define PPB_SHCSR_BUSFAULTENA_Msk (0x01UL << PPB_SHCSR_BUSFAULTENA_Pos) /*!< PPB SHCSR: BUSFAULTENA Mask */
\r
2791 #define PPB_SHCSR_USGFAULTENA_Pos 18 /*!< PPB SHCSR: USGFAULTENA Position */
\r
2792 #define PPB_SHCSR_USGFAULTENA_Msk (0x01UL << PPB_SHCSR_USGFAULTENA_Pos) /*!< PPB SHCSR: USGFAULTENA Mask */
\r
2794 /* ---------------------------------- PPB_CFSR ---------------------------------- */
\r
2795 #define PPB_CFSR_IACCVIOL_Pos 0 /*!< PPB CFSR: IACCVIOL Position */
\r
2796 #define PPB_CFSR_IACCVIOL_Msk (0x01UL << PPB_CFSR_IACCVIOL_Pos) /*!< PPB CFSR: IACCVIOL Mask */
\r
2797 #define PPB_CFSR_DACCVIOL_Pos 1 /*!< PPB CFSR: DACCVIOL Position */
\r
2798 #define PPB_CFSR_DACCVIOL_Msk (0x01UL << PPB_CFSR_DACCVIOL_Pos) /*!< PPB CFSR: DACCVIOL Mask */
\r
2799 #define PPB_CFSR_MUNSTKERR_Pos 3 /*!< PPB CFSR: MUNSTKERR Position */
\r
2800 #define PPB_CFSR_MUNSTKERR_Msk (0x01UL << PPB_CFSR_MUNSTKERR_Pos) /*!< PPB CFSR: MUNSTKERR Mask */
\r
2801 #define PPB_CFSR_MSTKERR_Pos 4 /*!< PPB CFSR: MSTKERR Position */
\r
2802 #define PPB_CFSR_MSTKERR_Msk (0x01UL << PPB_CFSR_MSTKERR_Pos) /*!< PPB CFSR: MSTKERR Mask */
\r
2803 #define PPB_CFSR_MLSPERR_Pos 5 /*!< PPB CFSR: MLSPERR Position */
\r
2804 #define PPB_CFSR_MLSPERR_Msk (0x01UL << PPB_CFSR_MLSPERR_Pos) /*!< PPB CFSR: MLSPERR Mask */
\r
2805 #define PPB_CFSR_MMARVALID_Pos 7 /*!< PPB CFSR: MMARVALID Position */
\r
2806 #define PPB_CFSR_MMARVALID_Msk (0x01UL << PPB_CFSR_MMARVALID_Pos) /*!< PPB CFSR: MMARVALID Mask */
\r
2807 #define PPB_CFSR_IBUSERR_Pos 8 /*!< PPB CFSR: IBUSERR Position */
\r
2808 #define PPB_CFSR_IBUSERR_Msk (0x01UL << PPB_CFSR_IBUSERR_Pos) /*!< PPB CFSR: IBUSERR Mask */
\r
2809 #define PPB_CFSR_PRECISERR_Pos 9 /*!< PPB CFSR: PRECISERR Position */
\r
2810 #define PPB_CFSR_PRECISERR_Msk (0x01UL << PPB_CFSR_PRECISERR_Pos) /*!< PPB CFSR: PRECISERR Mask */
\r
2811 #define PPB_CFSR_IMPRECISERR_Pos 10 /*!< PPB CFSR: IMPRECISERR Position */
\r
2812 #define PPB_CFSR_IMPRECISERR_Msk (0x01UL << PPB_CFSR_IMPRECISERR_Pos) /*!< PPB CFSR: IMPRECISERR Mask */
\r
2813 #define PPB_CFSR_UNSTKERR_Pos 11 /*!< PPB CFSR: UNSTKERR Position */
\r
2814 #define PPB_CFSR_UNSTKERR_Msk (0x01UL << PPB_CFSR_UNSTKERR_Pos) /*!< PPB CFSR: UNSTKERR Mask */
\r
2815 #define PPB_CFSR_STKERR_Pos 12 /*!< PPB CFSR: STKERR Position */
\r
2816 #define PPB_CFSR_STKERR_Msk (0x01UL << PPB_CFSR_STKERR_Pos) /*!< PPB CFSR: STKERR Mask */
\r
2817 #define PPB_CFSR_LSPERR_Pos 13 /*!< PPB CFSR: LSPERR Position */
\r
2818 #define PPB_CFSR_LSPERR_Msk (0x01UL << PPB_CFSR_LSPERR_Pos) /*!< PPB CFSR: LSPERR Mask */
\r
2819 #define PPB_CFSR_BFARVALID_Pos 15 /*!< PPB CFSR: BFARVALID Position */
\r
2820 #define PPB_CFSR_BFARVALID_Msk (0x01UL << PPB_CFSR_BFARVALID_Pos) /*!< PPB CFSR: BFARVALID Mask */
\r
2821 #define PPB_CFSR_UNDEFINSTR_Pos 16 /*!< PPB CFSR: UNDEFINSTR Position */
\r
2822 #define PPB_CFSR_UNDEFINSTR_Msk (0x01UL << PPB_CFSR_UNDEFINSTR_Pos) /*!< PPB CFSR: UNDEFINSTR Mask */
\r
2823 #define PPB_CFSR_INVSTATE_Pos 17 /*!< PPB CFSR: INVSTATE Position */
\r
2824 #define PPB_CFSR_INVSTATE_Msk (0x01UL << PPB_CFSR_INVSTATE_Pos) /*!< PPB CFSR: INVSTATE Mask */
\r
2825 #define PPB_CFSR_INVPC_Pos 18 /*!< PPB CFSR: INVPC Position */
\r
2826 #define PPB_CFSR_INVPC_Msk (0x01UL << PPB_CFSR_INVPC_Pos) /*!< PPB CFSR: INVPC Mask */
\r
2827 #define PPB_CFSR_NOCP_Pos 19 /*!< PPB CFSR: NOCP Position */
\r
2828 #define PPB_CFSR_NOCP_Msk (0x01UL << PPB_CFSR_NOCP_Pos) /*!< PPB CFSR: NOCP Mask */
\r
2829 #define PPB_CFSR_UNALIGNED_Pos 24 /*!< PPB CFSR: UNALIGNED Position */
\r
2830 #define PPB_CFSR_UNALIGNED_Msk (0x01UL << PPB_CFSR_UNALIGNED_Pos) /*!< PPB CFSR: UNALIGNED Mask */
\r
2831 #define PPB_CFSR_DIVBYZERO_Pos 25 /*!< PPB CFSR: DIVBYZERO Position */
\r
2832 #define PPB_CFSR_DIVBYZERO_Msk (0x01UL << PPB_CFSR_DIVBYZERO_Pos) /*!< PPB CFSR: DIVBYZERO Mask */
\r
2834 /* ---------------------------------- PPB_HFSR ---------------------------------- */
\r
2835 #define PPB_HFSR_VECTTBL_Pos 1 /*!< PPB HFSR: VECTTBL Position */
\r
2836 #define PPB_HFSR_VECTTBL_Msk (0x01UL << PPB_HFSR_VECTTBL_Pos) /*!< PPB HFSR: VECTTBL Mask */
\r
2837 #define PPB_HFSR_FORCED_Pos 30 /*!< PPB HFSR: FORCED Position */
\r
2838 #define PPB_HFSR_FORCED_Msk (0x01UL << PPB_HFSR_FORCED_Pos) /*!< PPB HFSR: FORCED Mask */
\r
2839 #define PPB_HFSR_DEBUGEVT_Pos 31 /*!< PPB HFSR: DEBUGEVT Position */
\r
2840 #define PPB_HFSR_DEBUGEVT_Msk (0x01UL << PPB_HFSR_DEBUGEVT_Pos) /*!< PPB HFSR: DEBUGEVT Mask */
\r
2842 /* ---------------------------------- PPB_MMFAR --------------------------------- */
\r
2843 #define PPB_MMFAR_ADDRESS_Pos 0 /*!< PPB MMFAR: ADDRESS Position */
\r
2844 #define PPB_MMFAR_ADDRESS_Msk (0xffffffffUL << PPB_MMFAR_ADDRESS_Pos) /*!< PPB MMFAR: ADDRESS Mask */
\r
2846 /* ---------------------------------- PPB_BFAR ---------------------------------- */
\r
2847 #define PPB_BFAR_ADDRESS_Pos 0 /*!< PPB BFAR: ADDRESS Position */
\r
2848 #define PPB_BFAR_ADDRESS_Msk (0xffffffffUL << PPB_BFAR_ADDRESS_Pos) /*!< PPB BFAR: ADDRESS Mask */
\r
2850 /* ---------------------------------- PPB_AFSR ---------------------------------- */
\r
2851 #define PPB_AFSR_VALUE_Pos 0 /*!< PPB AFSR: VALUE Position */
\r
2852 #define PPB_AFSR_VALUE_Msk (0xffffffffUL << PPB_AFSR_VALUE_Pos) /*!< PPB AFSR: VALUE Mask */
\r
2854 /* ---------------------------------- PPB_CPACR --------------------------------- */
\r
2855 #define PPB_CPACR_CP10_Pos 20 /*!< PPB CPACR: CP10 Position */
\r
2856 #define PPB_CPACR_CP10_Msk (0x03UL << PPB_CPACR_CP10_Pos) /*!< PPB CPACR: CP10 Mask */
\r
2857 #define PPB_CPACR_CP11_Pos 22 /*!< PPB CPACR: CP11 Position */
\r
2858 #define PPB_CPACR_CP11_Msk (0x03UL << PPB_CPACR_CP11_Pos) /*!< PPB CPACR: CP11 Mask */
\r
2860 /* -------------------------------- PPB_MPU_TYPE -------------------------------- */
\r
2861 #define PPB_MPU_TYPE_SEPARATE_Pos 0 /*!< PPB MPU_TYPE: SEPARATE Position */
\r
2862 #define PPB_MPU_TYPE_SEPARATE_Msk (0x01UL << PPB_MPU_TYPE_SEPARATE_Pos) /*!< PPB MPU_TYPE: SEPARATE Mask */
\r
2863 #define PPB_MPU_TYPE_DREGION_Pos 8 /*!< PPB MPU_TYPE: DREGION Position */
\r
2864 #define PPB_MPU_TYPE_DREGION_Msk (0x000000ffUL << PPB_MPU_TYPE_DREGION_Pos) /*!< PPB MPU_TYPE: DREGION Mask */
\r
2865 #define PPB_MPU_TYPE_IREGION_Pos 16 /*!< PPB MPU_TYPE: IREGION Position */
\r
2866 #define PPB_MPU_TYPE_IREGION_Msk (0x000000ffUL << PPB_MPU_TYPE_IREGION_Pos) /*!< PPB MPU_TYPE: IREGION Mask */
\r
2868 /* -------------------------------- PPB_MPU_CTRL -------------------------------- */
\r
2869 #define PPB_MPU_CTRL_ENABLE_Pos 0 /*!< PPB MPU_CTRL: ENABLE Position */
\r
2870 #define PPB_MPU_CTRL_ENABLE_Msk (0x01UL << PPB_MPU_CTRL_ENABLE_Pos) /*!< PPB MPU_CTRL: ENABLE Mask */
\r
2871 #define PPB_MPU_CTRL_HFNMIENA_Pos 1 /*!< PPB MPU_CTRL: HFNMIENA Position */
\r
2872 #define PPB_MPU_CTRL_HFNMIENA_Msk (0x01UL << PPB_MPU_CTRL_HFNMIENA_Pos) /*!< PPB MPU_CTRL: HFNMIENA Mask */
\r
2873 #define PPB_MPU_CTRL_PRIVDEFENA_Pos 2 /*!< PPB MPU_CTRL: PRIVDEFENA Position */
\r
2874 #define PPB_MPU_CTRL_PRIVDEFENA_Msk (0x01UL << PPB_MPU_CTRL_PRIVDEFENA_Pos) /*!< PPB MPU_CTRL: PRIVDEFENA Mask */
\r
2876 /* --------------------------------- PPB_MPU_RNR -------------------------------- */
\r
2877 #define PPB_MPU_RNR_REGION_Pos 0 /*!< PPB MPU_RNR: REGION Position */
\r
2878 #define PPB_MPU_RNR_REGION_Msk (0x000000ffUL << PPB_MPU_RNR_REGION_Pos) /*!< PPB MPU_RNR: REGION Mask */
\r
2880 /* -------------------------------- PPB_MPU_RBAR -------------------------------- */
\r
2881 #define PPB_MPU_RBAR_REGION_Pos 0 /*!< PPB MPU_RBAR: REGION Position */
\r
2882 #define PPB_MPU_RBAR_REGION_Msk (0x0fUL << PPB_MPU_RBAR_REGION_Pos) /*!< PPB MPU_RBAR: REGION Mask */
\r
2883 #define PPB_MPU_RBAR_VALID_Pos 4 /*!< PPB MPU_RBAR: VALID Position */
\r
2884 #define PPB_MPU_RBAR_VALID_Msk (0x01UL << PPB_MPU_RBAR_VALID_Pos) /*!< PPB MPU_RBAR: VALID Mask */
\r
2885 #define PPB_MPU_RBAR_ADDR_Pos 9 /*!< PPB MPU_RBAR: ADDR Position */
\r
2886 #define PPB_MPU_RBAR_ADDR_Msk (0x007fffffUL << PPB_MPU_RBAR_ADDR_Pos) /*!< PPB MPU_RBAR: ADDR Mask */
\r
2888 /* -------------------------------- PPB_MPU_RASR -------------------------------- */
\r
2889 #define PPB_MPU_RASR_ENABLE_Pos 0 /*!< PPB MPU_RASR: ENABLE Position */
\r
2890 #define PPB_MPU_RASR_ENABLE_Msk (0x01UL << PPB_MPU_RASR_ENABLE_Pos) /*!< PPB MPU_RASR: ENABLE Mask */
\r
2891 #define PPB_MPU_RASR_SIZE_Pos 1 /*!< PPB MPU_RASR: SIZE Position */
\r
2892 #define PPB_MPU_RASR_SIZE_Msk (0x1fUL << PPB_MPU_RASR_SIZE_Pos) /*!< PPB MPU_RASR: SIZE Mask */
\r
2893 #define PPB_MPU_RASR_SRD_Pos 8 /*!< PPB MPU_RASR: SRD Position */
\r
2894 #define PPB_MPU_RASR_SRD_Msk (0x000000ffUL << PPB_MPU_RASR_SRD_Pos) /*!< PPB MPU_RASR: SRD Mask */
\r
2895 #define PPB_MPU_RASR_B_Pos 16 /*!< PPB MPU_RASR: B Position */
\r
2896 #define PPB_MPU_RASR_B_Msk (0x01UL << PPB_MPU_RASR_B_Pos) /*!< PPB MPU_RASR: B Mask */
\r
2897 #define PPB_MPU_RASR_C_Pos 17 /*!< PPB MPU_RASR: C Position */
\r
2898 #define PPB_MPU_RASR_C_Msk (0x01UL << PPB_MPU_RASR_C_Pos) /*!< PPB MPU_RASR: C Mask */
\r
2899 #define PPB_MPU_RASR_S_Pos 18 /*!< PPB MPU_RASR: S Position */
\r
2900 #define PPB_MPU_RASR_S_Msk (0x01UL << PPB_MPU_RASR_S_Pos) /*!< PPB MPU_RASR: S Mask */
\r
2901 #define PPB_MPU_RASR_TEX_Pos 19 /*!< PPB MPU_RASR: TEX Position */
\r
2902 #define PPB_MPU_RASR_TEX_Msk (0x07UL << PPB_MPU_RASR_TEX_Pos) /*!< PPB MPU_RASR: TEX Mask */
\r
2903 #define PPB_MPU_RASR_AP_Pos 24 /*!< PPB MPU_RASR: AP Position */
\r
2904 #define PPB_MPU_RASR_AP_Msk (0x07UL << PPB_MPU_RASR_AP_Pos) /*!< PPB MPU_RASR: AP Mask */
\r
2905 #define PPB_MPU_RASR_XN_Pos 28 /*!< PPB MPU_RASR: XN Position */
\r
2906 #define PPB_MPU_RASR_XN_Msk (0x01UL << PPB_MPU_RASR_XN_Pos) /*!< PPB MPU_RASR: XN Mask */
\r
2908 /* ------------------------------- PPB_MPU_RBAR_A1 ------------------------------ */
\r
2909 #define PPB_MPU_RBAR_A1_REGION_Pos 0 /*!< PPB MPU_RBAR_A1: REGION Position */
\r
2910 #define PPB_MPU_RBAR_A1_REGION_Msk (0x0fUL << PPB_MPU_RBAR_A1_REGION_Pos) /*!< PPB MPU_RBAR_A1: REGION Mask */
\r
2911 #define PPB_MPU_RBAR_A1_VALID_Pos 4 /*!< PPB MPU_RBAR_A1: VALID Position */
\r
2912 #define PPB_MPU_RBAR_A1_VALID_Msk (0x01UL << PPB_MPU_RBAR_A1_VALID_Pos) /*!< PPB MPU_RBAR_A1: VALID Mask */
\r
2913 #define PPB_MPU_RBAR_A1_ADDR_Pos 9 /*!< PPB MPU_RBAR_A1: ADDR Position */
\r
2914 #define PPB_MPU_RBAR_A1_ADDR_Msk (0x007fffffUL << PPB_MPU_RBAR_A1_ADDR_Pos) /*!< PPB MPU_RBAR_A1: ADDR Mask */
\r
2916 /* ------------------------------- PPB_MPU_RASR_A1 ------------------------------ */
\r
2917 #define PPB_MPU_RASR_A1_ENABLE_Pos 0 /*!< PPB MPU_RASR_A1: ENABLE Position */
\r
2918 #define PPB_MPU_RASR_A1_ENABLE_Msk (0x01UL << PPB_MPU_RASR_A1_ENABLE_Pos) /*!< PPB MPU_RASR_A1: ENABLE Mask */
\r
2919 #define PPB_MPU_RASR_A1_SIZE_Pos 1 /*!< PPB MPU_RASR_A1: SIZE Position */
\r
2920 #define PPB_MPU_RASR_A1_SIZE_Msk (0x1fUL << PPB_MPU_RASR_A1_SIZE_Pos) /*!< PPB MPU_RASR_A1: SIZE Mask */
\r
2921 #define PPB_MPU_RASR_A1_SRD_Pos 8 /*!< PPB MPU_RASR_A1: SRD Position */
\r
2922 #define PPB_MPU_RASR_A1_SRD_Msk (0x000000ffUL << PPB_MPU_RASR_A1_SRD_Pos) /*!< PPB MPU_RASR_A1: SRD Mask */
\r
2923 #define PPB_MPU_RASR_A1_B_Pos 16 /*!< PPB MPU_RASR_A1: B Position */
\r
2924 #define PPB_MPU_RASR_A1_B_Msk (0x01UL << PPB_MPU_RASR_A1_B_Pos) /*!< PPB MPU_RASR_A1: B Mask */
\r
2925 #define PPB_MPU_RASR_A1_C_Pos 17 /*!< PPB MPU_RASR_A1: C Position */
\r
2926 #define PPB_MPU_RASR_A1_C_Msk (0x01UL << PPB_MPU_RASR_A1_C_Pos) /*!< PPB MPU_RASR_A1: C Mask */
\r
2927 #define PPB_MPU_RASR_A1_S_Pos 18 /*!< PPB MPU_RASR_A1: S Position */
\r
2928 #define PPB_MPU_RASR_A1_S_Msk (0x01UL << PPB_MPU_RASR_A1_S_Pos) /*!< PPB MPU_RASR_A1: S Mask */
\r
2929 #define PPB_MPU_RASR_A1_TEX_Pos 19 /*!< PPB MPU_RASR_A1: TEX Position */
\r
2930 #define PPB_MPU_RASR_A1_TEX_Msk (0x07UL << PPB_MPU_RASR_A1_TEX_Pos) /*!< PPB MPU_RASR_A1: TEX Mask */
\r
2931 #define PPB_MPU_RASR_A1_AP_Pos 24 /*!< PPB MPU_RASR_A1: AP Position */
\r
2932 #define PPB_MPU_RASR_A1_AP_Msk (0x07UL << PPB_MPU_RASR_A1_AP_Pos) /*!< PPB MPU_RASR_A1: AP Mask */
\r
2933 #define PPB_MPU_RASR_A1_XN_Pos 28 /*!< PPB MPU_RASR_A1: XN Position */
\r
2934 #define PPB_MPU_RASR_A1_XN_Msk (0x01UL << PPB_MPU_RASR_A1_XN_Pos) /*!< PPB MPU_RASR_A1: XN Mask */
\r
2936 /* ------------------------------- PPB_MPU_RBAR_A2 ------------------------------ */
\r
2937 #define PPB_MPU_RBAR_A2_REGION_Pos 0 /*!< PPB MPU_RBAR_A2: REGION Position */
\r
2938 #define PPB_MPU_RBAR_A2_REGION_Msk (0x0fUL << PPB_MPU_RBAR_A2_REGION_Pos) /*!< PPB MPU_RBAR_A2: REGION Mask */
\r
2939 #define PPB_MPU_RBAR_A2_VALID_Pos 4 /*!< PPB MPU_RBAR_A2: VALID Position */
\r
2940 #define PPB_MPU_RBAR_A2_VALID_Msk (0x01UL << PPB_MPU_RBAR_A2_VALID_Pos) /*!< PPB MPU_RBAR_A2: VALID Mask */
\r
2941 #define PPB_MPU_RBAR_A2_ADDR_Pos 9 /*!< PPB MPU_RBAR_A2: ADDR Position */
\r
2942 #define PPB_MPU_RBAR_A2_ADDR_Msk (0x007fffffUL << PPB_MPU_RBAR_A2_ADDR_Pos) /*!< PPB MPU_RBAR_A2: ADDR Mask */
\r
2944 /* ------------------------------- PPB_MPU_RASR_A2 ------------------------------ */
\r
2945 #define PPB_MPU_RASR_A2_ENABLE_Pos 0 /*!< PPB MPU_RASR_A2: ENABLE Position */
\r
2946 #define PPB_MPU_RASR_A2_ENABLE_Msk (0x01UL << PPB_MPU_RASR_A2_ENABLE_Pos) /*!< PPB MPU_RASR_A2: ENABLE Mask */
\r
2947 #define PPB_MPU_RASR_A2_SIZE_Pos 1 /*!< PPB MPU_RASR_A2: SIZE Position */
\r
2948 #define PPB_MPU_RASR_A2_SIZE_Msk (0x1fUL << PPB_MPU_RASR_A2_SIZE_Pos) /*!< PPB MPU_RASR_A2: SIZE Mask */
\r
2949 #define PPB_MPU_RASR_A2_SRD_Pos 8 /*!< PPB MPU_RASR_A2: SRD Position */
\r
2950 #define PPB_MPU_RASR_A2_SRD_Msk (0x000000ffUL << PPB_MPU_RASR_A2_SRD_Pos) /*!< PPB MPU_RASR_A2: SRD Mask */
\r
2951 #define PPB_MPU_RASR_A2_B_Pos 16 /*!< PPB MPU_RASR_A2: B Position */
\r
2952 #define PPB_MPU_RASR_A2_B_Msk (0x01UL << PPB_MPU_RASR_A2_B_Pos) /*!< PPB MPU_RASR_A2: B Mask */
\r
2953 #define PPB_MPU_RASR_A2_C_Pos 17 /*!< PPB MPU_RASR_A2: C Position */
\r
2954 #define PPB_MPU_RASR_A2_C_Msk (0x01UL << PPB_MPU_RASR_A2_C_Pos) /*!< PPB MPU_RASR_A2: C Mask */
\r
2955 #define PPB_MPU_RASR_A2_S_Pos 18 /*!< PPB MPU_RASR_A2: S Position */
\r
2956 #define PPB_MPU_RASR_A2_S_Msk (0x01UL << PPB_MPU_RASR_A2_S_Pos) /*!< PPB MPU_RASR_A2: S Mask */
\r
2957 #define PPB_MPU_RASR_A2_TEX_Pos 19 /*!< PPB MPU_RASR_A2: TEX Position */
\r
2958 #define PPB_MPU_RASR_A2_TEX_Msk (0x07UL << PPB_MPU_RASR_A2_TEX_Pos) /*!< PPB MPU_RASR_A2: TEX Mask */
\r
2959 #define PPB_MPU_RASR_A2_AP_Pos 24 /*!< PPB MPU_RASR_A2: AP Position */
\r
2960 #define PPB_MPU_RASR_A2_AP_Msk (0x07UL << PPB_MPU_RASR_A2_AP_Pos) /*!< PPB MPU_RASR_A2: AP Mask */
\r
2961 #define PPB_MPU_RASR_A2_XN_Pos 28 /*!< PPB MPU_RASR_A2: XN Position */
\r
2962 #define PPB_MPU_RASR_A2_XN_Msk (0x01UL << PPB_MPU_RASR_A2_XN_Pos) /*!< PPB MPU_RASR_A2: XN Mask */
\r
2964 /* ------------------------------- PPB_MPU_RBAR_A3 ------------------------------ */
\r
2965 #define PPB_MPU_RBAR_A3_REGION_Pos 0 /*!< PPB MPU_RBAR_A3: REGION Position */
\r
2966 #define PPB_MPU_RBAR_A3_REGION_Msk (0x0fUL << PPB_MPU_RBAR_A3_REGION_Pos) /*!< PPB MPU_RBAR_A3: REGION Mask */
\r
2967 #define PPB_MPU_RBAR_A3_VALID_Pos 4 /*!< PPB MPU_RBAR_A3: VALID Position */
\r
2968 #define PPB_MPU_RBAR_A3_VALID_Msk (0x01UL << PPB_MPU_RBAR_A3_VALID_Pos) /*!< PPB MPU_RBAR_A3: VALID Mask */
\r
2969 #define PPB_MPU_RBAR_A3_ADDR_Pos 9 /*!< PPB MPU_RBAR_A3: ADDR Position */
\r
2970 #define PPB_MPU_RBAR_A3_ADDR_Msk (0x007fffffUL << PPB_MPU_RBAR_A3_ADDR_Pos) /*!< PPB MPU_RBAR_A3: ADDR Mask */
\r
2972 /* ------------------------------- PPB_MPU_RASR_A3 ------------------------------ */
\r
2973 #define PPB_MPU_RASR_A3_ENABLE_Pos 0 /*!< PPB MPU_RASR_A3: ENABLE Position */
\r
2974 #define PPB_MPU_RASR_A3_ENABLE_Msk (0x01UL << PPB_MPU_RASR_A3_ENABLE_Pos) /*!< PPB MPU_RASR_A3: ENABLE Mask */
\r
2975 #define PPB_MPU_RASR_A3_SIZE_Pos 1 /*!< PPB MPU_RASR_A3: SIZE Position */
\r
2976 #define PPB_MPU_RASR_A3_SIZE_Msk (0x1fUL << PPB_MPU_RASR_A3_SIZE_Pos) /*!< PPB MPU_RASR_A3: SIZE Mask */
\r
2977 #define PPB_MPU_RASR_A3_SRD_Pos 8 /*!< PPB MPU_RASR_A3: SRD Position */
\r
2978 #define PPB_MPU_RASR_A3_SRD_Msk (0x000000ffUL << PPB_MPU_RASR_A3_SRD_Pos) /*!< PPB MPU_RASR_A3: SRD Mask */
\r
2979 #define PPB_MPU_RASR_A3_B_Pos 16 /*!< PPB MPU_RASR_A3: B Position */
\r
2980 #define PPB_MPU_RASR_A3_B_Msk (0x01UL << PPB_MPU_RASR_A3_B_Pos) /*!< PPB MPU_RASR_A3: B Mask */
\r
2981 #define PPB_MPU_RASR_A3_C_Pos 17 /*!< PPB MPU_RASR_A3: C Position */
\r
2982 #define PPB_MPU_RASR_A3_C_Msk (0x01UL << PPB_MPU_RASR_A3_C_Pos) /*!< PPB MPU_RASR_A3: C Mask */
\r
2983 #define PPB_MPU_RASR_A3_S_Pos 18 /*!< PPB MPU_RASR_A3: S Position */
\r
2984 #define PPB_MPU_RASR_A3_S_Msk (0x01UL << PPB_MPU_RASR_A3_S_Pos) /*!< PPB MPU_RASR_A3: S Mask */
\r
2985 #define PPB_MPU_RASR_A3_TEX_Pos 19 /*!< PPB MPU_RASR_A3: TEX Position */
\r
2986 #define PPB_MPU_RASR_A3_TEX_Msk (0x07UL << PPB_MPU_RASR_A3_TEX_Pos) /*!< PPB MPU_RASR_A3: TEX Mask */
\r
2987 #define PPB_MPU_RASR_A3_AP_Pos 24 /*!< PPB MPU_RASR_A3: AP Position */
\r
2988 #define PPB_MPU_RASR_A3_AP_Msk (0x07UL << PPB_MPU_RASR_A3_AP_Pos) /*!< PPB MPU_RASR_A3: AP Mask */
\r
2989 #define PPB_MPU_RASR_A3_XN_Pos 28 /*!< PPB MPU_RASR_A3: XN Position */
\r
2990 #define PPB_MPU_RASR_A3_XN_Msk (0x01UL << PPB_MPU_RASR_A3_XN_Pos) /*!< PPB MPU_RASR_A3: XN Mask */
\r
2992 /* ---------------------------------- PPB_STIR ---------------------------------- */
\r
2993 #define PPB_STIR_INTID_Pos 0 /*!< PPB STIR: INTID Position */
\r
2994 #define PPB_STIR_INTID_Msk (0x000001ffUL << PPB_STIR_INTID_Pos) /*!< PPB STIR: INTID Mask */
\r
2996 /* ---------------------------------- PPB_FPCCR --------------------------------- */
\r
2997 #define PPB_FPCCR_LSPACT_Pos 0 /*!< PPB FPCCR: LSPACT Position */
\r
2998 #define PPB_FPCCR_LSPACT_Msk (0x01UL << PPB_FPCCR_LSPACT_Pos) /*!< PPB FPCCR: LSPACT Mask */
\r
2999 #define PPB_FPCCR_USER_Pos 1 /*!< PPB FPCCR: USER Position */
\r
3000 #define PPB_FPCCR_USER_Msk (0x01UL << PPB_FPCCR_USER_Pos) /*!< PPB FPCCR: USER Mask */
\r
3001 #define PPB_FPCCR_THREAD_Pos 3 /*!< PPB FPCCR: THREAD Position */
\r
3002 #define PPB_FPCCR_THREAD_Msk (0x01UL << PPB_FPCCR_THREAD_Pos) /*!< PPB FPCCR: THREAD Mask */
\r
3003 #define PPB_FPCCR_HFRDY_Pos 4 /*!< PPB FPCCR: HFRDY Position */
\r
3004 #define PPB_FPCCR_HFRDY_Msk (0x01UL << PPB_FPCCR_HFRDY_Pos) /*!< PPB FPCCR: HFRDY Mask */
\r
3005 #define PPB_FPCCR_MMRDY_Pos 5 /*!< PPB FPCCR: MMRDY Position */
\r
3006 #define PPB_FPCCR_MMRDY_Msk (0x01UL << PPB_FPCCR_MMRDY_Pos) /*!< PPB FPCCR: MMRDY Mask */
\r
3007 #define PPB_FPCCR_BFRDY_Pos 6 /*!< PPB FPCCR: BFRDY Position */
\r
3008 #define PPB_FPCCR_BFRDY_Msk (0x01UL << PPB_FPCCR_BFRDY_Pos) /*!< PPB FPCCR: BFRDY Mask */
\r
3009 #define PPB_FPCCR_MONRDY_Pos 8 /*!< PPB FPCCR: MONRDY Position */
\r
3010 #define PPB_FPCCR_MONRDY_Msk (0x01UL << PPB_FPCCR_MONRDY_Pos) /*!< PPB FPCCR: MONRDY Mask */
\r
3011 #define PPB_FPCCR_LSPEN_Pos 30 /*!< PPB FPCCR: LSPEN Position */
\r
3012 #define PPB_FPCCR_LSPEN_Msk (0x01UL << PPB_FPCCR_LSPEN_Pos) /*!< PPB FPCCR: LSPEN Mask */
\r
3013 #define PPB_FPCCR_ASPEN_Pos 31 /*!< PPB FPCCR: ASPEN Position */
\r
3014 #define PPB_FPCCR_ASPEN_Msk (0x01UL << PPB_FPCCR_ASPEN_Pos) /*!< PPB FPCCR: ASPEN Mask */
\r
3016 /* ---------------------------------- PPB_FPCAR --------------------------------- */
\r
3017 #define PPB_FPCAR_ADDRESS_Pos 3 /*!< PPB FPCAR: ADDRESS Position */
\r
3018 #define PPB_FPCAR_ADDRESS_Msk (0x1fffffffUL << PPB_FPCAR_ADDRESS_Pos) /*!< PPB FPCAR: ADDRESS Mask */
\r
3020 /* --------------------------------- PPB_FPDSCR --------------------------------- */
\r
3021 #define PPB_FPDSCR_RMode_Pos 22 /*!< PPB FPDSCR: RMode Position */
\r
3022 #define PPB_FPDSCR_RMode_Msk (0x03UL << PPB_FPDSCR_RMode_Pos) /*!< PPB FPDSCR: RMode Mask */
\r
3023 #define PPB_FPDSCR_FZ_Pos 24 /*!< PPB FPDSCR: FZ Position */
\r
3024 #define PPB_FPDSCR_FZ_Msk (0x01UL << PPB_FPDSCR_FZ_Pos) /*!< PPB FPDSCR: FZ Mask */
\r
3025 #define PPB_FPDSCR_DN_Pos 25 /*!< PPB FPDSCR: DN Position */
\r
3026 #define PPB_FPDSCR_DN_Msk (0x01UL << PPB_FPDSCR_DN_Pos) /*!< PPB FPDSCR: DN Mask */
\r
3027 #define PPB_FPDSCR_AHP_Pos 26 /*!< PPB FPDSCR: AHP Position */
\r
3028 #define PPB_FPDSCR_AHP_Msk (0x01UL << PPB_FPDSCR_AHP_Pos) /*!< PPB FPDSCR: AHP Mask */
\r
3031 /* ================================================================================ */
\r
3032 /* ================ struct 'DLR' Position & Mask ================ */
\r
3033 /* ================================================================================ */
\r
3036 /* --------------------------------- DLR_OVRSTAT -------------------------------- */
\r
3037 #define DLR_OVRSTAT_LN0_Pos 0 /*!< DLR OVRSTAT: LN0 Position */
\r
3038 #define DLR_OVRSTAT_LN0_Msk (0x01UL << DLR_OVRSTAT_LN0_Pos) /*!< DLR OVRSTAT: LN0 Mask */
\r
3039 #define DLR_OVRSTAT_LN1_Pos 1 /*!< DLR OVRSTAT: LN1 Position */
\r
3040 #define DLR_OVRSTAT_LN1_Msk (0x01UL << DLR_OVRSTAT_LN1_Pos) /*!< DLR OVRSTAT: LN1 Mask */
\r
3041 #define DLR_OVRSTAT_LN2_Pos 2 /*!< DLR OVRSTAT: LN2 Position */
\r
3042 #define DLR_OVRSTAT_LN2_Msk (0x01UL << DLR_OVRSTAT_LN2_Pos) /*!< DLR OVRSTAT: LN2 Mask */
\r
3043 #define DLR_OVRSTAT_LN3_Pos 3 /*!< DLR OVRSTAT: LN3 Position */
\r
3044 #define DLR_OVRSTAT_LN3_Msk (0x01UL << DLR_OVRSTAT_LN3_Pos) /*!< DLR OVRSTAT: LN3 Mask */
\r
3045 #define DLR_OVRSTAT_LN4_Pos 4 /*!< DLR OVRSTAT: LN4 Position */
\r
3046 #define DLR_OVRSTAT_LN4_Msk (0x01UL << DLR_OVRSTAT_LN4_Pos) /*!< DLR OVRSTAT: LN4 Mask */
\r
3047 #define DLR_OVRSTAT_LN5_Pos 5 /*!< DLR OVRSTAT: LN5 Position */
\r
3048 #define DLR_OVRSTAT_LN5_Msk (0x01UL << DLR_OVRSTAT_LN5_Pos) /*!< DLR OVRSTAT: LN5 Mask */
\r
3049 #define DLR_OVRSTAT_LN6_Pos 6 /*!< DLR OVRSTAT: LN6 Position */
\r
3050 #define DLR_OVRSTAT_LN6_Msk (0x01UL << DLR_OVRSTAT_LN6_Pos) /*!< DLR OVRSTAT: LN6 Mask */
\r
3051 #define DLR_OVRSTAT_LN7_Pos 7 /*!< DLR OVRSTAT: LN7 Position */
\r
3052 #define DLR_OVRSTAT_LN7_Msk (0x01UL << DLR_OVRSTAT_LN7_Pos) /*!< DLR OVRSTAT: LN7 Mask */
\r
3054 /* --------------------------------- DLR_OVRCLR --------------------------------- */
\r
3055 #define DLR_OVRCLR_LN0_Pos 0 /*!< DLR OVRCLR: LN0 Position */
\r
3056 #define DLR_OVRCLR_LN0_Msk (0x01UL << DLR_OVRCLR_LN0_Pos) /*!< DLR OVRCLR: LN0 Mask */
\r
3057 #define DLR_OVRCLR_LN1_Pos 1 /*!< DLR OVRCLR: LN1 Position */
\r
3058 #define DLR_OVRCLR_LN1_Msk (0x01UL << DLR_OVRCLR_LN1_Pos) /*!< DLR OVRCLR: LN1 Mask */
\r
3059 #define DLR_OVRCLR_LN2_Pos 2 /*!< DLR OVRCLR: LN2 Position */
\r
3060 #define DLR_OVRCLR_LN2_Msk (0x01UL << DLR_OVRCLR_LN2_Pos) /*!< DLR OVRCLR: LN2 Mask */
\r
3061 #define DLR_OVRCLR_LN3_Pos 3 /*!< DLR OVRCLR: LN3 Position */
\r
3062 #define DLR_OVRCLR_LN3_Msk (0x01UL << DLR_OVRCLR_LN3_Pos) /*!< DLR OVRCLR: LN3 Mask */
\r
3063 #define DLR_OVRCLR_LN4_Pos 4 /*!< DLR OVRCLR: LN4 Position */
\r
3064 #define DLR_OVRCLR_LN4_Msk (0x01UL << DLR_OVRCLR_LN4_Pos) /*!< DLR OVRCLR: LN4 Mask */
\r
3065 #define DLR_OVRCLR_LN5_Pos 5 /*!< DLR OVRCLR: LN5 Position */
\r
3066 #define DLR_OVRCLR_LN5_Msk (0x01UL << DLR_OVRCLR_LN5_Pos) /*!< DLR OVRCLR: LN5 Mask */
\r
3067 #define DLR_OVRCLR_LN6_Pos 6 /*!< DLR OVRCLR: LN6 Position */
\r
3068 #define DLR_OVRCLR_LN6_Msk (0x01UL << DLR_OVRCLR_LN6_Pos) /*!< DLR OVRCLR: LN6 Mask */
\r
3069 #define DLR_OVRCLR_LN7_Pos 7 /*!< DLR OVRCLR: LN7 Position */
\r
3070 #define DLR_OVRCLR_LN7_Msk (0x01UL << DLR_OVRCLR_LN7_Pos) /*!< DLR OVRCLR: LN7 Mask */
\r
3072 /* --------------------------------- DLR_SRSEL0 --------------------------------- */
\r
3073 #define DLR_SRSEL0_RS0_Pos 0 /*!< DLR SRSEL0: RS0 Position */
\r
3074 #define DLR_SRSEL0_RS0_Msk (0x0fUL << DLR_SRSEL0_RS0_Pos) /*!< DLR SRSEL0: RS0 Mask */
\r
3075 #define DLR_SRSEL0_RS1_Pos 4 /*!< DLR SRSEL0: RS1 Position */
\r
3076 #define DLR_SRSEL0_RS1_Msk (0x0fUL << DLR_SRSEL0_RS1_Pos) /*!< DLR SRSEL0: RS1 Mask */
\r
3077 #define DLR_SRSEL0_RS2_Pos 8 /*!< DLR SRSEL0: RS2 Position */
\r
3078 #define DLR_SRSEL0_RS2_Msk (0x0fUL << DLR_SRSEL0_RS2_Pos) /*!< DLR SRSEL0: RS2 Mask */
\r
3079 #define DLR_SRSEL0_RS3_Pos 12 /*!< DLR SRSEL0: RS3 Position */
\r
3080 #define DLR_SRSEL0_RS3_Msk (0x0fUL << DLR_SRSEL0_RS3_Pos) /*!< DLR SRSEL0: RS3 Mask */
\r
3081 #define DLR_SRSEL0_RS4_Pos 16 /*!< DLR SRSEL0: RS4 Position */
\r
3082 #define DLR_SRSEL0_RS4_Msk (0x0fUL << DLR_SRSEL0_RS4_Pos) /*!< DLR SRSEL0: RS4 Mask */
\r
3083 #define DLR_SRSEL0_RS5_Pos 20 /*!< DLR SRSEL0: RS5 Position */
\r
3084 #define DLR_SRSEL0_RS5_Msk (0x0fUL << DLR_SRSEL0_RS5_Pos) /*!< DLR SRSEL0: RS5 Mask */
\r
3085 #define DLR_SRSEL0_RS6_Pos 24 /*!< DLR SRSEL0: RS6 Position */
\r
3086 #define DLR_SRSEL0_RS6_Msk (0x0fUL << DLR_SRSEL0_RS6_Pos) /*!< DLR SRSEL0: RS6 Mask */
\r
3087 #define DLR_SRSEL0_RS7_Pos 28 /*!< DLR SRSEL0: RS7 Position */
\r
3088 #define DLR_SRSEL0_RS7_Msk (0x0fUL << DLR_SRSEL0_RS7_Pos) /*!< DLR SRSEL0: RS7 Mask */
\r
3090 /* ---------------------------------- DLR_LNEN ---------------------------------- */
\r
3091 #define DLR_LNEN_LN0_Pos 0 /*!< DLR LNEN: LN0 Position */
\r
3092 #define DLR_LNEN_LN0_Msk (0x01UL << DLR_LNEN_LN0_Pos) /*!< DLR LNEN: LN0 Mask */
\r
3093 #define DLR_LNEN_LN1_Pos 1 /*!< DLR LNEN: LN1 Position */
\r
3094 #define DLR_LNEN_LN1_Msk (0x01UL << DLR_LNEN_LN1_Pos) /*!< DLR LNEN: LN1 Mask */
\r
3095 #define DLR_LNEN_LN2_Pos 2 /*!< DLR LNEN: LN2 Position */
\r
3096 #define DLR_LNEN_LN2_Msk (0x01UL << DLR_LNEN_LN2_Pos) /*!< DLR LNEN: LN2 Mask */
\r
3097 #define DLR_LNEN_LN3_Pos 3 /*!< DLR LNEN: LN3 Position */
\r
3098 #define DLR_LNEN_LN3_Msk (0x01UL << DLR_LNEN_LN3_Pos) /*!< DLR LNEN: LN3 Mask */
\r
3099 #define DLR_LNEN_LN4_Pos 4 /*!< DLR LNEN: LN4 Position */
\r
3100 #define DLR_LNEN_LN4_Msk (0x01UL << DLR_LNEN_LN4_Pos) /*!< DLR LNEN: LN4 Mask */
\r
3101 #define DLR_LNEN_LN5_Pos 5 /*!< DLR LNEN: LN5 Position */
\r
3102 #define DLR_LNEN_LN5_Msk (0x01UL << DLR_LNEN_LN5_Pos) /*!< DLR LNEN: LN5 Mask */
\r
3103 #define DLR_LNEN_LN6_Pos 6 /*!< DLR LNEN: LN6 Position */
\r
3104 #define DLR_LNEN_LN6_Msk (0x01UL << DLR_LNEN_LN6_Pos) /*!< DLR LNEN: LN6 Mask */
\r
3105 #define DLR_LNEN_LN7_Pos 7 /*!< DLR LNEN: LN7 Position */
\r
3106 #define DLR_LNEN_LN7_Msk (0x01UL << DLR_LNEN_LN7_Pos) /*!< DLR LNEN: LN7 Mask */
\r
3109 /* ================================================================================ */
\r
3110 /* ================ Group 'ERU' Position & Mask ================ */
\r
3111 /* ================================================================================ */
\r
3114 /* --------------------------------- ERU_EXISEL --------------------------------- */
\r
3115 #define ERU_EXISEL_EXS0A_Pos 0 /*!< ERU EXISEL: EXS0A Position */
\r
3116 #define ERU_EXISEL_EXS0A_Msk (0x03UL << ERU_EXISEL_EXS0A_Pos) /*!< ERU EXISEL: EXS0A Mask */
\r
3117 #define ERU_EXISEL_EXS0B_Pos 2 /*!< ERU EXISEL: EXS0B Position */
\r
3118 #define ERU_EXISEL_EXS0B_Msk (0x03UL << ERU_EXISEL_EXS0B_Pos) /*!< ERU EXISEL: EXS0B Mask */
\r
3119 #define ERU_EXISEL_EXS1A_Pos 4 /*!< ERU EXISEL: EXS1A Position */
\r
3120 #define ERU_EXISEL_EXS1A_Msk (0x03UL << ERU_EXISEL_EXS1A_Pos) /*!< ERU EXISEL: EXS1A Mask */
\r
3121 #define ERU_EXISEL_EXS1B_Pos 6 /*!< ERU EXISEL: EXS1B Position */
\r
3122 #define ERU_EXISEL_EXS1B_Msk (0x03UL << ERU_EXISEL_EXS1B_Pos) /*!< ERU EXISEL: EXS1B Mask */
\r
3123 #define ERU_EXISEL_EXS2A_Pos 8 /*!< ERU EXISEL: EXS2A Position */
\r
3124 #define ERU_EXISEL_EXS2A_Msk (0x03UL << ERU_EXISEL_EXS2A_Pos) /*!< ERU EXISEL: EXS2A Mask */
\r
3125 #define ERU_EXISEL_EXS2B_Pos 10 /*!< ERU EXISEL: EXS2B Position */
\r
3126 #define ERU_EXISEL_EXS2B_Msk (0x03UL << ERU_EXISEL_EXS2B_Pos) /*!< ERU EXISEL: EXS2B Mask */
\r
3127 #define ERU_EXISEL_EXS3A_Pos 12 /*!< ERU EXISEL: EXS3A Position */
\r
3128 #define ERU_EXISEL_EXS3A_Msk (0x03UL << ERU_EXISEL_EXS3A_Pos) /*!< ERU EXISEL: EXS3A Mask */
\r
3129 #define ERU_EXISEL_EXS3B_Pos 14 /*!< ERU EXISEL: EXS3B Position */
\r
3130 #define ERU_EXISEL_EXS3B_Msk (0x03UL << ERU_EXISEL_EXS3B_Pos) /*!< ERU EXISEL: EXS3B Mask */
\r
3132 /* --------------------------------- ERU_EXICON --------------------------------- */
\r
3133 #define ERU_EXICON_PE_Pos 0 /*!< ERU EXICON: PE Position */
\r
3134 #define ERU_EXICON_PE_Msk (0x01UL << ERU_EXICON_PE_Pos) /*!< ERU EXICON: PE Mask */
\r
3135 #define ERU_EXICON_LD_Pos 1 /*!< ERU EXICON: LD Position */
\r
3136 #define ERU_EXICON_LD_Msk (0x01UL << ERU_EXICON_LD_Pos) /*!< ERU EXICON: LD Mask */
\r
3137 #define ERU_EXICON_RE_Pos 2 /*!< ERU EXICON: RE Position */
\r
3138 #define ERU_EXICON_RE_Msk (0x01UL << ERU_EXICON_RE_Pos) /*!< ERU EXICON: RE Mask */
\r
3139 #define ERU_EXICON_FE_Pos 3 /*!< ERU EXICON: FE Position */
\r
3140 #define ERU_EXICON_FE_Msk (0x01UL << ERU_EXICON_FE_Pos) /*!< ERU EXICON: FE Mask */
\r
3141 #define ERU_EXICON_OCS_Pos 4 /*!< ERU EXICON: OCS Position */
\r
3142 #define ERU_EXICON_OCS_Msk (0x07UL << ERU_EXICON_OCS_Pos) /*!< ERU EXICON: OCS Mask */
\r
3143 #define ERU_EXICON_FL_Pos 7 /*!< ERU EXICON: FL Position */
\r
3144 #define ERU_EXICON_FL_Msk (0x01UL << ERU_EXICON_FL_Pos) /*!< ERU EXICON: FL Mask */
\r
3145 #define ERU_EXICON_SS_Pos 8 /*!< ERU EXICON: SS Position */
\r
3146 #define ERU_EXICON_SS_Msk (0x03UL << ERU_EXICON_SS_Pos) /*!< ERU EXICON: SS Mask */
\r
3147 #define ERU_EXICON_NA_Pos 10 /*!< ERU EXICON: NA Position */
\r
3148 #define ERU_EXICON_NA_Msk (0x01UL << ERU_EXICON_NA_Pos) /*!< ERU EXICON: NA Mask */
\r
3149 #define ERU_EXICON_NB_Pos 11 /*!< ERU EXICON: NB Position */
\r
3150 #define ERU_EXICON_NB_Msk (0x01UL << ERU_EXICON_NB_Pos) /*!< ERU EXICON: NB Mask */
\r
3152 /* --------------------------------- ERU_EXOCON --------------------------------- */
\r
3153 #define ERU_EXOCON_ISS_Pos 0 /*!< ERU EXOCON: ISS Position */
\r
3154 #define ERU_EXOCON_ISS_Msk (0x03UL << ERU_EXOCON_ISS_Pos) /*!< ERU EXOCON: ISS Mask */
\r
3155 #define ERU_EXOCON_GEEN_Pos 2 /*!< ERU EXOCON: GEEN Position */
\r
3156 #define ERU_EXOCON_GEEN_Msk (0x01UL << ERU_EXOCON_GEEN_Pos) /*!< ERU EXOCON: GEEN Mask */
\r
3157 #define ERU_EXOCON_PDR_Pos 3 /*!< ERU EXOCON: PDR Position */
\r
3158 #define ERU_EXOCON_PDR_Msk (0x01UL << ERU_EXOCON_PDR_Pos) /*!< ERU EXOCON: PDR Mask */
\r
3159 #define ERU_EXOCON_GP_Pos 4 /*!< ERU EXOCON: GP Position */
\r
3160 #define ERU_EXOCON_GP_Msk (0x03UL << ERU_EXOCON_GP_Pos) /*!< ERU EXOCON: GP Mask */
\r
3161 #define ERU_EXOCON_IPEN0_Pos 12 /*!< ERU EXOCON: IPEN0 Position */
\r
3162 #define ERU_EXOCON_IPEN0_Msk (0x01UL << ERU_EXOCON_IPEN0_Pos) /*!< ERU EXOCON: IPEN0 Mask */
\r
3163 #define ERU_EXOCON_IPEN1_Pos 13 /*!< ERU EXOCON: IPEN1 Position */
\r
3164 #define ERU_EXOCON_IPEN1_Msk (0x01UL << ERU_EXOCON_IPEN1_Pos) /*!< ERU EXOCON: IPEN1 Mask */
\r
3165 #define ERU_EXOCON_IPEN2_Pos 14 /*!< ERU EXOCON: IPEN2 Position */
\r
3166 #define ERU_EXOCON_IPEN2_Msk (0x01UL << ERU_EXOCON_IPEN2_Pos) /*!< ERU EXOCON: IPEN2 Mask */
\r
3167 #define ERU_EXOCON_IPEN3_Pos 15 /*!< ERU EXOCON: IPEN3 Position */
\r
3168 #define ERU_EXOCON_IPEN3_Msk (0x01UL << ERU_EXOCON_IPEN3_Pos) /*!< ERU EXOCON: IPEN3 Mask */
\r
3171 /* ================================================================================ */
\r
3172 /* ================ struct 'GPDMA0' Position & Mask ================ */
\r
3173 /* ================================================================================ */
\r
3176 /* -------------------------------- GPDMA0_RAWTFR ------------------------------- */
\r
3177 #define GPDMA0_RAWTFR_CH0_Pos 0 /*!< GPDMA0 RAWTFR: CH0 Position */
\r
3178 #define GPDMA0_RAWTFR_CH0_Msk (0x01UL << GPDMA0_RAWTFR_CH0_Pos) /*!< GPDMA0 RAWTFR: CH0 Mask */
\r
3179 #define GPDMA0_RAWTFR_CH1_Pos 1 /*!< GPDMA0 RAWTFR: CH1 Position */
\r
3180 #define GPDMA0_RAWTFR_CH1_Msk (0x01UL << GPDMA0_RAWTFR_CH1_Pos) /*!< GPDMA0 RAWTFR: CH1 Mask */
\r
3181 #define GPDMA0_RAWTFR_CH2_Pos 2 /*!< GPDMA0 RAWTFR: CH2 Position */
\r
3182 #define GPDMA0_RAWTFR_CH2_Msk (0x01UL << GPDMA0_RAWTFR_CH2_Pos) /*!< GPDMA0 RAWTFR: CH2 Mask */
\r
3183 #define GPDMA0_RAWTFR_CH3_Pos 3 /*!< GPDMA0 RAWTFR: CH3 Position */
\r
3184 #define GPDMA0_RAWTFR_CH3_Msk (0x01UL << GPDMA0_RAWTFR_CH3_Pos) /*!< GPDMA0 RAWTFR: CH3 Mask */
\r
3185 #define GPDMA0_RAWTFR_CH4_Pos 4 /*!< GPDMA0 RAWTFR: CH4 Position */
\r
3186 #define GPDMA0_RAWTFR_CH4_Msk (0x01UL << GPDMA0_RAWTFR_CH4_Pos) /*!< GPDMA0 RAWTFR: CH4 Mask */
\r
3187 #define GPDMA0_RAWTFR_CH5_Pos 5 /*!< GPDMA0 RAWTFR: CH5 Position */
\r
3188 #define GPDMA0_RAWTFR_CH5_Msk (0x01UL << GPDMA0_RAWTFR_CH5_Pos) /*!< GPDMA0 RAWTFR: CH5 Mask */
\r
3189 #define GPDMA0_RAWTFR_CH6_Pos 6 /*!< GPDMA0 RAWTFR: CH6 Position */
\r
3190 #define GPDMA0_RAWTFR_CH6_Msk (0x01UL << GPDMA0_RAWTFR_CH6_Pos) /*!< GPDMA0 RAWTFR: CH6 Mask */
\r
3191 #define GPDMA0_RAWTFR_CH7_Pos 7 /*!< GPDMA0 RAWTFR: CH7 Position */
\r
3192 #define GPDMA0_RAWTFR_CH7_Msk (0x01UL << GPDMA0_RAWTFR_CH7_Pos) /*!< GPDMA0 RAWTFR: CH7 Mask */
\r
3194 /* ------------------------------- GPDMA0_RAWBLOCK ------------------------------ */
\r
3195 #define GPDMA0_RAWBLOCK_CH0_Pos 0 /*!< GPDMA0 RAWBLOCK: CH0 Position */
\r
3196 #define GPDMA0_RAWBLOCK_CH0_Msk (0x01UL << GPDMA0_RAWBLOCK_CH0_Pos) /*!< GPDMA0 RAWBLOCK: CH0 Mask */
\r
3197 #define GPDMA0_RAWBLOCK_CH1_Pos 1 /*!< GPDMA0 RAWBLOCK: CH1 Position */
\r
3198 #define GPDMA0_RAWBLOCK_CH1_Msk (0x01UL << GPDMA0_RAWBLOCK_CH1_Pos) /*!< GPDMA0 RAWBLOCK: CH1 Mask */
\r
3199 #define GPDMA0_RAWBLOCK_CH2_Pos 2 /*!< GPDMA0 RAWBLOCK: CH2 Position */
\r
3200 #define GPDMA0_RAWBLOCK_CH2_Msk (0x01UL << GPDMA0_RAWBLOCK_CH2_Pos) /*!< GPDMA0 RAWBLOCK: CH2 Mask */
\r
3201 #define GPDMA0_RAWBLOCK_CH3_Pos 3 /*!< GPDMA0 RAWBLOCK: CH3 Position */
\r
3202 #define GPDMA0_RAWBLOCK_CH3_Msk (0x01UL << GPDMA0_RAWBLOCK_CH3_Pos) /*!< GPDMA0 RAWBLOCK: CH3 Mask */
\r
3203 #define GPDMA0_RAWBLOCK_CH4_Pos 4 /*!< GPDMA0 RAWBLOCK: CH4 Position */
\r
3204 #define GPDMA0_RAWBLOCK_CH4_Msk (0x01UL << GPDMA0_RAWBLOCK_CH4_Pos) /*!< GPDMA0 RAWBLOCK: CH4 Mask */
\r
3205 #define GPDMA0_RAWBLOCK_CH5_Pos 5 /*!< GPDMA0 RAWBLOCK: CH5 Position */
\r
3206 #define GPDMA0_RAWBLOCK_CH5_Msk (0x01UL << GPDMA0_RAWBLOCK_CH5_Pos) /*!< GPDMA0 RAWBLOCK: CH5 Mask */
\r
3207 #define GPDMA0_RAWBLOCK_CH6_Pos 6 /*!< GPDMA0 RAWBLOCK: CH6 Position */
\r
3208 #define GPDMA0_RAWBLOCK_CH6_Msk (0x01UL << GPDMA0_RAWBLOCK_CH6_Pos) /*!< GPDMA0 RAWBLOCK: CH6 Mask */
\r
3209 #define GPDMA0_RAWBLOCK_CH7_Pos 7 /*!< GPDMA0 RAWBLOCK: CH7 Position */
\r
3210 #define GPDMA0_RAWBLOCK_CH7_Msk (0x01UL << GPDMA0_RAWBLOCK_CH7_Pos) /*!< GPDMA0 RAWBLOCK: CH7 Mask */
\r
3212 /* ------------------------------ GPDMA0_RAWSRCTRAN ----------------------------- */
\r
3213 #define GPDMA0_RAWSRCTRAN_CH0_Pos 0 /*!< GPDMA0 RAWSRCTRAN: CH0 Position */
\r
3214 #define GPDMA0_RAWSRCTRAN_CH0_Msk (0x01UL << GPDMA0_RAWSRCTRAN_CH0_Pos) /*!< GPDMA0 RAWSRCTRAN: CH0 Mask */
\r
3215 #define GPDMA0_RAWSRCTRAN_CH1_Pos 1 /*!< GPDMA0 RAWSRCTRAN: CH1 Position */
\r
3216 #define GPDMA0_RAWSRCTRAN_CH1_Msk (0x01UL << GPDMA0_RAWSRCTRAN_CH1_Pos) /*!< GPDMA0 RAWSRCTRAN: CH1 Mask */
\r
3217 #define GPDMA0_RAWSRCTRAN_CH2_Pos 2 /*!< GPDMA0 RAWSRCTRAN: CH2 Position */
\r
3218 #define GPDMA0_RAWSRCTRAN_CH2_Msk (0x01UL << GPDMA0_RAWSRCTRAN_CH2_Pos) /*!< GPDMA0 RAWSRCTRAN: CH2 Mask */
\r
3219 #define GPDMA0_RAWSRCTRAN_CH3_Pos 3 /*!< GPDMA0 RAWSRCTRAN: CH3 Position */
\r
3220 #define GPDMA0_RAWSRCTRAN_CH3_Msk (0x01UL << GPDMA0_RAWSRCTRAN_CH3_Pos) /*!< GPDMA0 RAWSRCTRAN: CH3 Mask */
\r
3221 #define GPDMA0_RAWSRCTRAN_CH4_Pos 4 /*!< GPDMA0 RAWSRCTRAN: CH4 Position */
\r
3222 #define GPDMA0_RAWSRCTRAN_CH4_Msk (0x01UL << GPDMA0_RAWSRCTRAN_CH4_Pos) /*!< GPDMA0 RAWSRCTRAN: CH4 Mask */
\r
3223 #define GPDMA0_RAWSRCTRAN_CH5_Pos 5 /*!< GPDMA0 RAWSRCTRAN: CH5 Position */
\r
3224 #define GPDMA0_RAWSRCTRAN_CH5_Msk (0x01UL << GPDMA0_RAWSRCTRAN_CH5_Pos) /*!< GPDMA0 RAWSRCTRAN: CH5 Mask */
\r
3225 #define GPDMA0_RAWSRCTRAN_CH6_Pos 6 /*!< GPDMA0 RAWSRCTRAN: CH6 Position */
\r
3226 #define GPDMA0_RAWSRCTRAN_CH6_Msk (0x01UL << GPDMA0_RAWSRCTRAN_CH6_Pos) /*!< GPDMA0 RAWSRCTRAN: CH6 Mask */
\r
3227 #define GPDMA0_RAWSRCTRAN_CH7_Pos 7 /*!< GPDMA0 RAWSRCTRAN: CH7 Position */
\r
3228 #define GPDMA0_RAWSRCTRAN_CH7_Msk (0x01UL << GPDMA0_RAWSRCTRAN_CH7_Pos) /*!< GPDMA0 RAWSRCTRAN: CH7 Mask */
\r
3230 /* ------------------------------ GPDMA0_RAWDSTTRAN ----------------------------- */
\r
3231 #define GPDMA0_RAWDSTTRAN_CH0_Pos 0 /*!< GPDMA0 RAWDSTTRAN: CH0 Position */
\r
3232 #define GPDMA0_RAWDSTTRAN_CH0_Msk (0x01UL << GPDMA0_RAWDSTTRAN_CH0_Pos) /*!< GPDMA0 RAWDSTTRAN: CH0 Mask */
\r
3233 #define GPDMA0_RAWDSTTRAN_CH1_Pos 1 /*!< GPDMA0 RAWDSTTRAN: CH1 Position */
\r
3234 #define GPDMA0_RAWDSTTRAN_CH1_Msk (0x01UL << GPDMA0_RAWDSTTRAN_CH1_Pos) /*!< GPDMA0 RAWDSTTRAN: CH1 Mask */
\r
3235 #define GPDMA0_RAWDSTTRAN_CH2_Pos 2 /*!< GPDMA0 RAWDSTTRAN: CH2 Position */
\r
3236 #define GPDMA0_RAWDSTTRAN_CH2_Msk (0x01UL << GPDMA0_RAWDSTTRAN_CH2_Pos) /*!< GPDMA0 RAWDSTTRAN: CH2 Mask */
\r
3237 #define GPDMA0_RAWDSTTRAN_CH3_Pos 3 /*!< GPDMA0 RAWDSTTRAN: CH3 Position */
\r
3238 #define GPDMA0_RAWDSTTRAN_CH3_Msk (0x01UL << GPDMA0_RAWDSTTRAN_CH3_Pos) /*!< GPDMA0 RAWDSTTRAN: CH3 Mask */
\r
3239 #define GPDMA0_RAWDSTTRAN_CH4_Pos 4 /*!< GPDMA0 RAWDSTTRAN: CH4 Position */
\r
3240 #define GPDMA0_RAWDSTTRAN_CH4_Msk (0x01UL << GPDMA0_RAWDSTTRAN_CH4_Pos) /*!< GPDMA0 RAWDSTTRAN: CH4 Mask */
\r
3241 #define GPDMA0_RAWDSTTRAN_CH5_Pos 5 /*!< GPDMA0 RAWDSTTRAN: CH5 Position */
\r
3242 #define GPDMA0_RAWDSTTRAN_CH5_Msk (0x01UL << GPDMA0_RAWDSTTRAN_CH5_Pos) /*!< GPDMA0 RAWDSTTRAN: CH5 Mask */
\r
3243 #define GPDMA0_RAWDSTTRAN_CH6_Pos 6 /*!< GPDMA0 RAWDSTTRAN: CH6 Position */
\r
3244 #define GPDMA0_RAWDSTTRAN_CH6_Msk (0x01UL << GPDMA0_RAWDSTTRAN_CH6_Pos) /*!< GPDMA0 RAWDSTTRAN: CH6 Mask */
\r
3245 #define GPDMA0_RAWDSTTRAN_CH7_Pos 7 /*!< GPDMA0 RAWDSTTRAN: CH7 Position */
\r
3246 #define GPDMA0_RAWDSTTRAN_CH7_Msk (0x01UL << GPDMA0_RAWDSTTRAN_CH7_Pos) /*!< GPDMA0 RAWDSTTRAN: CH7 Mask */
\r
3248 /* -------------------------------- GPDMA0_RAWERR ------------------------------- */
\r
3249 #define GPDMA0_RAWERR_CH0_Pos 0 /*!< GPDMA0 RAWERR: CH0 Position */
\r
3250 #define GPDMA0_RAWERR_CH0_Msk (0x01UL << GPDMA0_RAWERR_CH0_Pos) /*!< GPDMA0 RAWERR: CH0 Mask */
\r
3251 #define GPDMA0_RAWERR_CH1_Pos 1 /*!< GPDMA0 RAWERR: CH1 Position */
\r
3252 #define GPDMA0_RAWERR_CH1_Msk (0x01UL << GPDMA0_RAWERR_CH1_Pos) /*!< GPDMA0 RAWERR: CH1 Mask */
\r
3253 #define GPDMA0_RAWERR_CH2_Pos 2 /*!< GPDMA0 RAWERR: CH2 Position */
\r
3254 #define GPDMA0_RAWERR_CH2_Msk (0x01UL << GPDMA0_RAWERR_CH2_Pos) /*!< GPDMA0 RAWERR: CH2 Mask */
\r
3255 #define GPDMA0_RAWERR_CH3_Pos 3 /*!< GPDMA0 RAWERR: CH3 Position */
\r
3256 #define GPDMA0_RAWERR_CH3_Msk (0x01UL << GPDMA0_RAWERR_CH3_Pos) /*!< GPDMA0 RAWERR: CH3 Mask */
\r
3257 #define GPDMA0_RAWERR_CH4_Pos 4 /*!< GPDMA0 RAWERR: CH4 Position */
\r
3258 #define GPDMA0_RAWERR_CH4_Msk (0x01UL << GPDMA0_RAWERR_CH4_Pos) /*!< GPDMA0 RAWERR: CH4 Mask */
\r
3259 #define GPDMA0_RAWERR_CH5_Pos 5 /*!< GPDMA0 RAWERR: CH5 Position */
\r
3260 #define GPDMA0_RAWERR_CH5_Msk (0x01UL << GPDMA0_RAWERR_CH5_Pos) /*!< GPDMA0 RAWERR: CH5 Mask */
\r
3261 #define GPDMA0_RAWERR_CH6_Pos 6 /*!< GPDMA0 RAWERR: CH6 Position */
\r
3262 #define GPDMA0_RAWERR_CH6_Msk (0x01UL << GPDMA0_RAWERR_CH6_Pos) /*!< GPDMA0 RAWERR: CH6 Mask */
\r
3263 #define GPDMA0_RAWERR_CH7_Pos 7 /*!< GPDMA0 RAWERR: CH7 Position */
\r
3264 #define GPDMA0_RAWERR_CH7_Msk (0x01UL << GPDMA0_RAWERR_CH7_Pos) /*!< GPDMA0 RAWERR: CH7 Mask */
\r
3266 /* ------------------------------ GPDMA0_STATUSTFR ------------------------------ */
\r
3267 #define GPDMA0_STATUSTFR_CH0_Pos 0 /*!< GPDMA0 STATUSTFR: CH0 Position */
\r
3268 #define GPDMA0_STATUSTFR_CH0_Msk (0x01UL << GPDMA0_STATUSTFR_CH0_Pos) /*!< GPDMA0 STATUSTFR: CH0 Mask */
\r
3269 #define GPDMA0_STATUSTFR_CH1_Pos 1 /*!< GPDMA0 STATUSTFR: CH1 Position */
\r
3270 #define GPDMA0_STATUSTFR_CH1_Msk (0x01UL << GPDMA0_STATUSTFR_CH1_Pos) /*!< GPDMA0 STATUSTFR: CH1 Mask */
\r
3271 #define GPDMA0_STATUSTFR_CH2_Pos 2 /*!< GPDMA0 STATUSTFR: CH2 Position */
\r
3272 #define GPDMA0_STATUSTFR_CH2_Msk (0x01UL << GPDMA0_STATUSTFR_CH2_Pos) /*!< GPDMA0 STATUSTFR: CH2 Mask */
\r
3273 #define GPDMA0_STATUSTFR_CH3_Pos 3 /*!< GPDMA0 STATUSTFR: CH3 Position */
\r
3274 #define GPDMA0_STATUSTFR_CH3_Msk (0x01UL << GPDMA0_STATUSTFR_CH3_Pos) /*!< GPDMA0 STATUSTFR: CH3 Mask */
\r
3275 #define GPDMA0_STATUSTFR_CH4_Pos 4 /*!< GPDMA0 STATUSTFR: CH4 Position */
\r
3276 #define GPDMA0_STATUSTFR_CH4_Msk (0x01UL << GPDMA0_STATUSTFR_CH4_Pos) /*!< GPDMA0 STATUSTFR: CH4 Mask */
\r
3277 #define GPDMA0_STATUSTFR_CH5_Pos 5 /*!< GPDMA0 STATUSTFR: CH5 Position */
\r
3278 #define GPDMA0_STATUSTFR_CH5_Msk (0x01UL << GPDMA0_STATUSTFR_CH5_Pos) /*!< GPDMA0 STATUSTFR: CH5 Mask */
\r
3279 #define GPDMA0_STATUSTFR_CH6_Pos 6 /*!< GPDMA0 STATUSTFR: CH6 Position */
\r
3280 #define GPDMA0_STATUSTFR_CH6_Msk (0x01UL << GPDMA0_STATUSTFR_CH6_Pos) /*!< GPDMA0 STATUSTFR: CH6 Mask */
\r
3281 #define GPDMA0_STATUSTFR_CH7_Pos 7 /*!< GPDMA0 STATUSTFR: CH7 Position */
\r
3282 #define GPDMA0_STATUSTFR_CH7_Msk (0x01UL << GPDMA0_STATUSTFR_CH7_Pos) /*!< GPDMA0 STATUSTFR: CH7 Mask */
\r
3284 /* ----------------------------- GPDMA0_STATUSBLOCK ----------------------------- */
\r
3285 #define GPDMA0_STATUSBLOCK_CH0_Pos 0 /*!< GPDMA0 STATUSBLOCK: CH0 Position */
\r
3286 #define GPDMA0_STATUSBLOCK_CH0_Msk (0x01UL << GPDMA0_STATUSBLOCK_CH0_Pos) /*!< GPDMA0 STATUSBLOCK: CH0 Mask */
\r
3287 #define GPDMA0_STATUSBLOCK_CH1_Pos 1 /*!< GPDMA0 STATUSBLOCK: CH1 Position */
\r
3288 #define GPDMA0_STATUSBLOCK_CH1_Msk (0x01UL << GPDMA0_STATUSBLOCK_CH1_Pos) /*!< GPDMA0 STATUSBLOCK: CH1 Mask */
\r
3289 #define GPDMA0_STATUSBLOCK_CH2_Pos 2 /*!< GPDMA0 STATUSBLOCK: CH2 Position */
\r
3290 #define GPDMA0_STATUSBLOCK_CH2_Msk (0x01UL << GPDMA0_STATUSBLOCK_CH2_Pos) /*!< GPDMA0 STATUSBLOCK: CH2 Mask */
\r
3291 #define GPDMA0_STATUSBLOCK_CH3_Pos 3 /*!< GPDMA0 STATUSBLOCK: CH3 Position */
\r
3292 #define GPDMA0_STATUSBLOCK_CH3_Msk (0x01UL << GPDMA0_STATUSBLOCK_CH3_Pos) /*!< GPDMA0 STATUSBLOCK: CH3 Mask */
\r
3293 #define GPDMA0_STATUSBLOCK_CH4_Pos 4 /*!< GPDMA0 STATUSBLOCK: CH4 Position */
\r
3294 #define GPDMA0_STATUSBLOCK_CH4_Msk (0x01UL << GPDMA0_STATUSBLOCK_CH4_Pos) /*!< GPDMA0 STATUSBLOCK: CH4 Mask */
\r
3295 #define GPDMA0_STATUSBLOCK_CH5_Pos 5 /*!< GPDMA0 STATUSBLOCK: CH5 Position */
\r
3296 #define GPDMA0_STATUSBLOCK_CH5_Msk (0x01UL << GPDMA0_STATUSBLOCK_CH5_Pos) /*!< GPDMA0 STATUSBLOCK: CH5 Mask */
\r
3297 #define GPDMA0_STATUSBLOCK_CH6_Pos 6 /*!< GPDMA0 STATUSBLOCK: CH6 Position */
\r
3298 #define GPDMA0_STATUSBLOCK_CH6_Msk (0x01UL << GPDMA0_STATUSBLOCK_CH6_Pos) /*!< GPDMA0 STATUSBLOCK: CH6 Mask */
\r
3299 #define GPDMA0_STATUSBLOCK_CH7_Pos 7 /*!< GPDMA0 STATUSBLOCK: CH7 Position */
\r
3300 #define GPDMA0_STATUSBLOCK_CH7_Msk (0x01UL << GPDMA0_STATUSBLOCK_CH7_Pos) /*!< GPDMA0 STATUSBLOCK: CH7 Mask */
\r
3302 /* ---------------------------- GPDMA0_STATUSSRCTRAN ---------------------------- */
\r
3303 #define GPDMA0_STATUSSRCTRAN_CH0_Pos 0 /*!< GPDMA0 STATUSSRCTRAN: CH0 Position */
\r
3304 #define GPDMA0_STATUSSRCTRAN_CH0_Msk (0x01UL << GPDMA0_STATUSSRCTRAN_CH0_Pos) /*!< GPDMA0 STATUSSRCTRAN: CH0 Mask */
\r
3305 #define GPDMA0_STATUSSRCTRAN_CH1_Pos 1 /*!< GPDMA0 STATUSSRCTRAN: CH1 Position */
\r
3306 #define GPDMA0_STATUSSRCTRAN_CH1_Msk (0x01UL << GPDMA0_STATUSSRCTRAN_CH1_Pos) /*!< GPDMA0 STATUSSRCTRAN: CH1 Mask */
\r
3307 #define GPDMA0_STATUSSRCTRAN_CH2_Pos 2 /*!< GPDMA0 STATUSSRCTRAN: CH2 Position */
\r
3308 #define GPDMA0_STATUSSRCTRAN_CH2_Msk (0x01UL << GPDMA0_STATUSSRCTRAN_CH2_Pos) /*!< GPDMA0 STATUSSRCTRAN: CH2 Mask */
\r
3309 #define GPDMA0_STATUSSRCTRAN_CH3_Pos 3 /*!< GPDMA0 STATUSSRCTRAN: CH3 Position */
\r
3310 #define GPDMA0_STATUSSRCTRAN_CH3_Msk (0x01UL << GPDMA0_STATUSSRCTRAN_CH3_Pos) /*!< GPDMA0 STATUSSRCTRAN: CH3 Mask */
\r
3311 #define GPDMA0_STATUSSRCTRAN_CH4_Pos 4 /*!< GPDMA0 STATUSSRCTRAN: CH4 Position */
\r
3312 #define GPDMA0_STATUSSRCTRAN_CH4_Msk (0x01UL << GPDMA0_STATUSSRCTRAN_CH4_Pos) /*!< GPDMA0 STATUSSRCTRAN: CH4 Mask */
\r
3313 #define GPDMA0_STATUSSRCTRAN_CH5_Pos 5 /*!< GPDMA0 STATUSSRCTRAN: CH5 Position */
\r
3314 #define GPDMA0_STATUSSRCTRAN_CH5_Msk (0x01UL << GPDMA0_STATUSSRCTRAN_CH5_Pos) /*!< GPDMA0 STATUSSRCTRAN: CH5 Mask */
\r
3315 #define GPDMA0_STATUSSRCTRAN_CH6_Pos 6 /*!< GPDMA0 STATUSSRCTRAN: CH6 Position */
\r
3316 #define GPDMA0_STATUSSRCTRAN_CH6_Msk (0x01UL << GPDMA0_STATUSSRCTRAN_CH6_Pos) /*!< GPDMA0 STATUSSRCTRAN: CH6 Mask */
\r
3317 #define GPDMA0_STATUSSRCTRAN_CH7_Pos 7 /*!< GPDMA0 STATUSSRCTRAN: CH7 Position */
\r
3318 #define GPDMA0_STATUSSRCTRAN_CH7_Msk (0x01UL << GPDMA0_STATUSSRCTRAN_CH7_Pos) /*!< GPDMA0 STATUSSRCTRAN: CH7 Mask */
\r
3320 /* ---------------------------- GPDMA0_STATUSDSTTRAN ---------------------------- */
\r
3321 #define GPDMA0_STATUSDSTTRAN_CH0_Pos 0 /*!< GPDMA0 STATUSDSTTRAN: CH0 Position */
\r
3322 #define GPDMA0_STATUSDSTTRAN_CH0_Msk (0x01UL << GPDMA0_STATUSDSTTRAN_CH0_Pos) /*!< GPDMA0 STATUSDSTTRAN: CH0 Mask */
\r
3323 #define GPDMA0_STATUSDSTTRAN_CH1_Pos 1 /*!< GPDMA0 STATUSDSTTRAN: CH1 Position */
\r
3324 #define GPDMA0_STATUSDSTTRAN_CH1_Msk (0x01UL << GPDMA0_STATUSDSTTRAN_CH1_Pos) /*!< GPDMA0 STATUSDSTTRAN: CH1 Mask */
\r
3325 #define GPDMA0_STATUSDSTTRAN_CH2_Pos 2 /*!< GPDMA0 STATUSDSTTRAN: CH2 Position */
\r
3326 #define GPDMA0_STATUSDSTTRAN_CH2_Msk (0x01UL << GPDMA0_STATUSDSTTRAN_CH2_Pos) /*!< GPDMA0 STATUSDSTTRAN: CH2 Mask */
\r
3327 #define GPDMA0_STATUSDSTTRAN_CH3_Pos 3 /*!< GPDMA0 STATUSDSTTRAN: CH3 Position */
\r
3328 #define GPDMA0_STATUSDSTTRAN_CH3_Msk (0x01UL << GPDMA0_STATUSDSTTRAN_CH3_Pos) /*!< GPDMA0 STATUSDSTTRAN: CH3 Mask */
\r
3329 #define GPDMA0_STATUSDSTTRAN_CH4_Pos 4 /*!< GPDMA0 STATUSDSTTRAN: CH4 Position */
\r
3330 #define GPDMA0_STATUSDSTTRAN_CH4_Msk (0x01UL << GPDMA0_STATUSDSTTRAN_CH4_Pos) /*!< GPDMA0 STATUSDSTTRAN: CH4 Mask */
\r
3331 #define GPDMA0_STATUSDSTTRAN_CH5_Pos 5 /*!< GPDMA0 STATUSDSTTRAN: CH5 Position */
\r
3332 #define GPDMA0_STATUSDSTTRAN_CH5_Msk (0x01UL << GPDMA0_STATUSDSTTRAN_CH5_Pos) /*!< GPDMA0 STATUSDSTTRAN: CH5 Mask */
\r
3333 #define GPDMA0_STATUSDSTTRAN_CH6_Pos 6 /*!< GPDMA0 STATUSDSTTRAN: CH6 Position */
\r
3334 #define GPDMA0_STATUSDSTTRAN_CH6_Msk (0x01UL << GPDMA0_STATUSDSTTRAN_CH6_Pos) /*!< GPDMA0 STATUSDSTTRAN: CH6 Mask */
\r
3335 #define GPDMA0_STATUSDSTTRAN_CH7_Pos 7 /*!< GPDMA0 STATUSDSTTRAN: CH7 Position */
\r
3336 #define GPDMA0_STATUSDSTTRAN_CH7_Msk (0x01UL << GPDMA0_STATUSDSTTRAN_CH7_Pos) /*!< GPDMA0 STATUSDSTTRAN: CH7 Mask */
\r
3338 /* ------------------------------ GPDMA0_STATUSERR ------------------------------ */
\r
3339 #define GPDMA0_STATUSERR_CH0_Pos 0 /*!< GPDMA0 STATUSERR: CH0 Position */
\r
3340 #define GPDMA0_STATUSERR_CH0_Msk (0x01UL << GPDMA0_STATUSERR_CH0_Pos) /*!< GPDMA0 STATUSERR: CH0 Mask */
\r
3341 #define GPDMA0_STATUSERR_CH1_Pos 1 /*!< GPDMA0 STATUSERR: CH1 Position */
\r
3342 #define GPDMA0_STATUSERR_CH1_Msk (0x01UL << GPDMA0_STATUSERR_CH1_Pos) /*!< GPDMA0 STATUSERR: CH1 Mask */
\r
3343 #define GPDMA0_STATUSERR_CH2_Pos 2 /*!< GPDMA0 STATUSERR: CH2 Position */
\r
3344 #define GPDMA0_STATUSERR_CH2_Msk (0x01UL << GPDMA0_STATUSERR_CH2_Pos) /*!< GPDMA0 STATUSERR: CH2 Mask */
\r
3345 #define GPDMA0_STATUSERR_CH3_Pos 3 /*!< GPDMA0 STATUSERR: CH3 Position */
\r
3346 #define GPDMA0_STATUSERR_CH3_Msk (0x01UL << GPDMA0_STATUSERR_CH3_Pos) /*!< GPDMA0 STATUSERR: CH3 Mask */
\r
3347 #define GPDMA0_STATUSERR_CH4_Pos 4 /*!< GPDMA0 STATUSERR: CH4 Position */
\r
3348 #define GPDMA0_STATUSERR_CH4_Msk (0x01UL << GPDMA0_STATUSERR_CH4_Pos) /*!< GPDMA0 STATUSERR: CH4 Mask */
\r
3349 #define GPDMA0_STATUSERR_CH5_Pos 5 /*!< GPDMA0 STATUSERR: CH5 Position */
\r
3350 #define GPDMA0_STATUSERR_CH5_Msk (0x01UL << GPDMA0_STATUSERR_CH5_Pos) /*!< GPDMA0 STATUSERR: CH5 Mask */
\r
3351 #define GPDMA0_STATUSERR_CH6_Pos 6 /*!< GPDMA0 STATUSERR: CH6 Position */
\r
3352 #define GPDMA0_STATUSERR_CH6_Msk (0x01UL << GPDMA0_STATUSERR_CH6_Pos) /*!< GPDMA0 STATUSERR: CH6 Mask */
\r
3353 #define GPDMA0_STATUSERR_CH7_Pos 7 /*!< GPDMA0 STATUSERR: CH7 Position */
\r
3354 #define GPDMA0_STATUSERR_CH7_Msk (0x01UL << GPDMA0_STATUSERR_CH7_Pos) /*!< GPDMA0 STATUSERR: CH7 Mask */
\r
3356 /* ------------------------------- GPDMA0_MASKTFR ------------------------------- */
\r
3357 #define GPDMA0_MASKTFR_CH0_Pos 0 /*!< GPDMA0 MASKTFR: CH0 Position */
\r
3358 #define GPDMA0_MASKTFR_CH0_Msk (0x01UL << GPDMA0_MASKTFR_CH0_Pos) /*!< GPDMA0 MASKTFR: CH0 Mask */
\r
3359 #define GPDMA0_MASKTFR_CH1_Pos 1 /*!< GPDMA0 MASKTFR: CH1 Position */
\r
3360 #define GPDMA0_MASKTFR_CH1_Msk (0x01UL << GPDMA0_MASKTFR_CH1_Pos) /*!< GPDMA0 MASKTFR: CH1 Mask */
\r
3361 #define GPDMA0_MASKTFR_CH2_Pos 2 /*!< GPDMA0 MASKTFR: CH2 Position */
\r
3362 #define GPDMA0_MASKTFR_CH2_Msk (0x01UL << GPDMA0_MASKTFR_CH2_Pos) /*!< GPDMA0 MASKTFR: CH2 Mask */
\r
3363 #define GPDMA0_MASKTFR_CH3_Pos 3 /*!< GPDMA0 MASKTFR: CH3 Position */
\r
3364 #define GPDMA0_MASKTFR_CH3_Msk (0x01UL << GPDMA0_MASKTFR_CH3_Pos) /*!< GPDMA0 MASKTFR: CH3 Mask */
\r
3365 #define GPDMA0_MASKTFR_CH4_Pos 4 /*!< GPDMA0 MASKTFR: CH4 Position */
\r
3366 #define GPDMA0_MASKTFR_CH4_Msk (0x01UL << GPDMA0_MASKTFR_CH4_Pos) /*!< GPDMA0 MASKTFR: CH4 Mask */
\r
3367 #define GPDMA0_MASKTFR_CH5_Pos 5 /*!< GPDMA0 MASKTFR: CH5 Position */
\r
3368 #define GPDMA0_MASKTFR_CH5_Msk (0x01UL << GPDMA0_MASKTFR_CH5_Pos) /*!< GPDMA0 MASKTFR: CH5 Mask */
\r
3369 #define GPDMA0_MASKTFR_CH6_Pos 6 /*!< GPDMA0 MASKTFR: CH6 Position */
\r
3370 #define GPDMA0_MASKTFR_CH6_Msk (0x01UL << GPDMA0_MASKTFR_CH6_Pos) /*!< GPDMA0 MASKTFR: CH6 Mask */
\r
3371 #define GPDMA0_MASKTFR_CH7_Pos 7 /*!< GPDMA0 MASKTFR: CH7 Position */
\r
3372 #define GPDMA0_MASKTFR_CH7_Msk (0x01UL << GPDMA0_MASKTFR_CH7_Pos) /*!< GPDMA0 MASKTFR: CH7 Mask */
\r
3373 #define GPDMA0_MASKTFR_WE_CH0_Pos 8 /*!< GPDMA0 MASKTFR: WE_CH0 Position */
\r
3374 #define GPDMA0_MASKTFR_WE_CH0_Msk (0x01UL << GPDMA0_MASKTFR_WE_CH0_Pos) /*!< GPDMA0 MASKTFR: WE_CH0 Mask */
\r
3375 #define GPDMA0_MASKTFR_WE_CH1_Pos 9 /*!< GPDMA0 MASKTFR: WE_CH1 Position */
\r
3376 #define GPDMA0_MASKTFR_WE_CH1_Msk (0x01UL << GPDMA0_MASKTFR_WE_CH1_Pos) /*!< GPDMA0 MASKTFR: WE_CH1 Mask */
\r
3377 #define GPDMA0_MASKTFR_WE_CH2_Pos 10 /*!< GPDMA0 MASKTFR: WE_CH2 Position */
\r
3378 #define GPDMA0_MASKTFR_WE_CH2_Msk (0x01UL << GPDMA0_MASKTFR_WE_CH2_Pos) /*!< GPDMA0 MASKTFR: WE_CH2 Mask */
\r
3379 #define GPDMA0_MASKTFR_WE_CH3_Pos 11 /*!< GPDMA0 MASKTFR: WE_CH3 Position */
\r
3380 #define GPDMA0_MASKTFR_WE_CH3_Msk (0x01UL << GPDMA0_MASKTFR_WE_CH3_Pos) /*!< GPDMA0 MASKTFR: WE_CH3 Mask */
\r
3381 #define GPDMA0_MASKTFR_WE_CH4_Pos 12 /*!< GPDMA0 MASKTFR: WE_CH4 Position */
\r
3382 #define GPDMA0_MASKTFR_WE_CH4_Msk (0x01UL << GPDMA0_MASKTFR_WE_CH4_Pos) /*!< GPDMA0 MASKTFR: WE_CH4 Mask */
\r
3383 #define GPDMA0_MASKTFR_WE_CH5_Pos 13 /*!< GPDMA0 MASKTFR: WE_CH5 Position */
\r
3384 #define GPDMA0_MASKTFR_WE_CH5_Msk (0x01UL << GPDMA0_MASKTFR_WE_CH5_Pos) /*!< GPDMA0 MASKTFR: WE_CH5 Mask */
\r
3385 #define GPDMA0_MASKTFR_WE_CH6_Pos 14 /*!< GPDMA0 MASKTFR: WE_CH6 Position */
\r
3386 #define GPDMA0_MASKTFR_WE_CH6_Msk (0x01UL << GPDMA0_MASKTFR_WE_CH6_Pos) /*!< GPDMA0 MASKTFR: WE_CH6 Mask */
\r
3387 #define GPDMA0_MASKTFR_WE_CH7_Pos 15 /*!< GPDMA0 MASKTFR: WE_CH7 Position */
\r
3388 #define GPDMA0_MASKTFR_WE_CH7_Msk (0x01UL << GPDMA0_MASKTFR_WE_CH7_Pos) /*!< GPDMA0 MASKTFR: WE_CH7 Mask */
\r
3390 /* ------------------------------ GPDMA0_MASKBLOCK ------------------------------ */
\r
3391 #define GPDMA0_MASKBLOCK_CH0_Pos 0 /*!< GPDMA0 MASKBLOCK: CH0 Position */
\r
3392 #define GPDMA0_MASKBLOCK_CH0_Msk (0x01UL << GPDMA0_MASKBLOCK_CH0_Pos) /*!< GPDMA0 MASKBLOCK: CH0 Mask */
\r
3393 #define GPDMA0_MASKBLOCK_CH1_Pos 1 /*!< GPDMA0 MASKBLOCK: CH1 Position */
\r
3394 #define GPDMA0_MASKBLOCK_CH1_Msk (0x01UL << GPDMA0_MASKBLOCK_CH1_Pos) /*!< GPDMA0 MASKBLOCK: CH1 Mask */
\r
3395 #define GPDMA0_MASKBLOCK_CH2_Pos 2 /*!< GPDMA0 MASKBLOCK: CH2 Position */
\r
3396 #define GPDMA0_MASKBLOCK_CH2_Msk (0x01UL << GPDMA0_MASKBLOCK_CH2_Pos) /*!< GPDMA0 MASKBLOCK: CH2 Mask */
\r
3397 #define GPDMA0_MASKBLOCK_CH3_Pos 3 /*!< GPDMA0 MASKBLOCK: CH3 Position */
\r
3398 #define GPDMA0_MASKBLOCK_CH3_Msk (0x01UL << GPDMA0_MASKBLOCK_CH3_Pos) /*!< GPDMA0 MASKBLOCK: CH3 Mask */
\r
3399 #define GPDMA0_MASKBLOCK_CH4_Pos 4 /*!< GPDMA0 MASKBLOCK: CH4 Position */
\r
3400 #define GPDMA0_MASKBLOCK_CH4_Msk (0x01UL << GPDMA0_MASKBLOCK_CH4_Pos) /*!< GPDMA0 MASKBLOCK: CH4 Mask */
\r
3401 #define GPDMA0_MASKBLOCK_CH5_Pos 5 /*!< GPDMA0 MASKBLOCK: CH5 Position */
\r
3402 #define GPDMA0_MASKBLOCK_CH5_Msk (0x01UL << GPDMA0_MASKBLOCK_CH5_Pos) /*!< GPDMA0 MASKBLOCK: CH5 Mask */
\r
3403 #define GPDMA0_MASKBLOCK_CH6_Pos 6 /*!< GPDMA0 MASKBLOCK: CH6 Position */
\r
3404 #define GPDMA0_MASKBLOCK_CH6_Msk (0x01UL << GPDMA0_MASKBLOCK_CH6_Pos) /*!< GPDMA0 MASKBLOCK: CH6 Mask */
\r
3405 #define GPDMA0_MASKBLOCK_CH7_Pos 7 /*!< GPDMA0 MASKBLOCK: CH7 Position */
\r
3406 #define GPDMA0_MASKBLOCK_CH7_Msk (0x01UL << GPDMA0_MASKBLOCK_CH7_Pos) /*!< GPDMA0 MASKBLOCK: CH7 Mask */
\r
3407 #define GPDMA0_MASKBLOCK_WE_CH0_Pos 8 /*!< GPDMA0 MASKBLOCK: WE_CH0 Position */
\r
3408 #define GPDMA0_MASKBLOCK_WE_CH0_Msk (0x01UL << GPDMA0_MASKBLOCK_WE_CH0_Pos) /*!< GPDMA0 MASKBLOCK: WE_CH0 Mask */
\r
3409 #define GPDMA0_MASKBLOCK_WE_CH1_Pos 9 /*!< GPDMA0 MASKBLOCK: WE_CH1 Position */
\r
3410 #define GPDMA0_MASKBLOCK_WE_CH1_Msk (0x01UL << GPDMA0_MASKBLOCK_WE_CH1_Pos) /*!< GPDMA0 MASKBLOCK: WE_CH1 Mask */
\r
3411 #define GPDMA0_MASKBLOCK_WE_CH2_Pos 10 /*!< GPDMA0 MASKBLOCK: WE_CH2 Position */
\r
3412 #define GPDMA0_MASKBLOCK_WE_CH2_Msk (0x01UL << GPDMA0_MASKBLOCK_WE_CH2_Pos) /*!< GPDMA0 MASKBLOCK: WE_CH2 Mask */
\r
3413 #define GPDMA0_MASKBLOCK_WE_CH3_Pos 11 /*!< GPDMA0 MASKBLOCK: WE_CH3 Position */
\r
3414 #define GPDMA0_MASKBLOCK_WE_CH3_Msk (0x01UL << GPDMA0_MASKBLOCK_WE_CH3_Pos) /*!< GPDMA0 MASKBLOCK: WE_CH3 Mask */
\r
3415 #define GPDMA0_MASKBLOCK_WE_CH4_Pos 12 /*!< GPDMA0 MASKBLOCK: WE_CH4 Position */
\r
3416 #define GPDMA0_MASKBLOCK_WE_CH4_Msk (0x01UL << GPDMA0_MASKBLOCK_WE_CH4_Pos) /*!< GPDMA0 MASKBLOCK: WE_CH4 Mask */
\r
3417 #define GPDMA0_MASKBLOCK_WE_CH5_Pos 13 /*!< GPDMA0 MASKBLOCK: WE_CH5 Position */
\r
3418 #define GPDMA0_MASKBLOCK_WE_CH5_Msk (0x01UL << GPDMA0_MASKBLOCK_WE_CH5_Pos) /*!< GPDMA0 MASKBLOCK: WE_CH5 Mask */
\r
3419 #define GPDMA0_MASKBLOCK_WE_CH6_Pos 14 /*!< GPDMA0 MASKBLOCK: WE_CH6 Position */
\r
3420 #define GPDMA0_MASKBLOCK_WE_CH6_Msk (0x01UL << GPDMA0_MASKBLOCK_WE_CH6_Pos) /*!< GPDMA0 MASKBLOCK: WE_CH6 Mask */
\r
3421 #define GPDMA0_MASKBLOCK_WE_CH7_Pos 15 /*!< GPDMA0 MASKBLOCK: WE_CH7 Position */
\r
3422 #define GPDMA0_MASKBLOCK_WE_CH7_Msk (0x01UL << GPDMA0_MASKBLOCK_WE_CH7_Pos) /*!< GPDMA0 MASKBLOCK: WE_CH7 Mask */
\r
3424 /* ----------------------------- GPDMA0_MASKSRCTRAN ----------------------------- */
\r
3425 #define GPDMA0_MASKSRCTRAN_CH0_Pos 0 /*!< GPDMA0 MASKSRCTRAN: CH0 Position */
\r
3426 #define GPDMA0_MASKSRCTRAN_CH0_Msk (0x01UL << GPDMA0_MASKSRCTRAN_CH0_Pos) /*!< GPDMA0 MASKSRCTRAN: CH0 Mask */
\r
3427 #define GPDMA0_MASKSRCTRAN_CH1_Pos 1 /*!< GPDMA0 MASKSRCTRAN: CH1 Position */
\r
3428 #define GPDMA0_MASKSRCTRAN_CH1_Msk (0x01UL << GPDMA0_MASKSRCTRAN_CH1_Pos) /*!< GPDMA0 MASKSRCTRAN: CH1 Mask */
\r
3429 #define GPDMA0_MASKSRCTRAN_CH2_Pos 2 /*!< GPDMA0 MASKSRCTRAN: CH2 Position */
\r
3430 #define GPDMA0_MASKSRCTRAN_CH2_Msk (0x01UL << GPDMA0_MASKSRCTRAN_CH2_Pos) /*!< GPDMA0 MASKSRCTRAN: CH2 Mask */
\r
3431 #define GPDMA0_MASKSRCTRAN_CH3_Pos 3 /*!< GPDMA0 MASKSRCTRAN: CH3 Position */
\r
3432 #define GPDMA0_MASKSRCTRAN_CH3_Msk (0x01UL << GPDMA0_MASKSRCTRAN_CH3_Pos) /*!< GPDMA0 MASKSRCTRAN: CH3 Mask */
\r
3433 #define GPDMA0_MASKSRCTRAN_CH4_Pos 4 /*!< GPDMA0 MASKSRCTRAN: CH4 Position */
\r
3434 #define GPDMA0_MASKSRCTRAN_CH4_Msk (0x01UL << GPDMA0_MASKSRCTRAN_CH4_Pos) /*!< GPDMA0 MASKSRCTRAN: CH4 Mask */
\r
3435 #define GPDMA0_MASKSRCTRAN_CH5_Pos 5 /*!< GPDMA0 MASKSRCTRAN: CH5 Position */
\r
3436 #define GPDMA0_MASKSRCTRAN_CH5_Msk (0x01UL << GPDMA0_MASKSRCTRAN_CH5_Pos) /*!< GPDMA0 MASKSRCTRAN: CH5 Mask */
\r
3437 #define GPDMA0_MASKSRCTRAN_CH6_Pos 6 /*!< GPDMA0 MASKSRCTRAN: CH6 Position */
\r
3438 #define GPDMA0_MASKSRCTRAN_CH6_Msk (0x01UL << GPDMA0_MASKSRCTRAN_CH6_Pos) /*!< GPDMA0 MASKSRCTRAN: CH6 Mask */
\r
3439 #define GPDMA0_MASKSRCTRAN_CH7_Pos 7 /*!< GPDMA0 MASKSRCTRAN: CH7 Position */
\r
3440 #define GPDMA0_MASKSRCTRAN_CH7_Msk (0x01UL << GPDMA0_MASKSRCTRAN_CH7_Pos) /*!< GPDMA0 MASKSRCTRAN: CH7 Mask */
\r
3441 #define GPDMA0_MASKSRCTRAN_WE_CH0_Pos 8 /*!< GPDMA0 MASKSRCTRAN: WE_CH0 Position */
\r
3442 #define GPDMA0_MASKSRCTRAN_WE_CH0_Msk (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH0_Pos) /*!< GPDMA0 MASKSRCTRAN: WE_CH0 Mask */
\r
3443 #define GPDMA0_MASKSRCTRAN_WE_CH1_Pos 9 /*!< GPDMA0 MASKSRCTRAN: WE_CH1 Position */
\r
3444 #define GPDMA0_MASKSRCTRAN_WE_CH1_Msk (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH1_Pos) /*!< GPDMA0 MASKSRCTRAN: WE_CH1 Mask */
\r
3445 #define GPDMA0_MASKSRCTRAN_WE_CH2_Pos 10 /*!< GPDMA0 MASKSRCTRAN: WE_CH2 Position */
\r
3446 #define GPDMA0_MASKSRCTRAN_WE_CH2_Msk (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH2_Pos) /*!< GPDMA0 MASKSRCTRAN: WE_CH2 Mask */
\r
3447 #define GPDMA0_MASKSRCTRAN_WE_CH3_Pos 11 /*!< GPDMA0 MASKSRCTRAN: WE_CH3 Position */
\r
3448 #define GPDMA0_MASKSRCTRAN_WE_CH3_Msk (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH3_Pos) /*!< GPDMA0 MASKSRCTRAN: WE_CH3 Mask */
\r
3449 #define GPDMA0_MASKSRCTRAN_WE_CH4_Pos 12 /*!< GPDMA0 MASKSRCTRAN: WE_CH4 Position */
\r
3450 #define GPDMA0_MASKSRCTRAN_WE_CH4_Msk (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH4_Pos) /*!< GPDMA0 MASKSRCTRAN: WE_CH4 Mask */
\r
3451 #define GPDMA0_MASKSRCTRAN_WE_CH5_Pos 13 /*!< GPDMA0 MASKSRCTRAN: WE_CH5 Position */
\r
3452 #define GPDMA0_MASKSRCTRAN_WE_CH5_Msk (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH5_Pos) /*!< GPDMA0 MASKSRCTRAN: WE_CH5 Mask */
\r
3453 #define GPDMA0_MASKSRCTRAN_WE_CH6_Pos 14 /*!< GPDMA0 MASKSRCTRAN: WE_CH6 Position */
\r
3454 #define GPDMA0_MASKSRCTRAN_WE_CH6_Msk (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH6_Pos) /*!< GPDMA0 MASKSRCTRAN: WE_CH6 Mask */
\r
3455 #define GPDMA0_MASKSRCTRAN_WE_CH7_Pos 15 /*!< GPDMA0 MASKSRCTRAN: WE_CH7 Position */
\r
3456 #define GPDMA0_MASKSRCTRAN_WE_CH7_Msk (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH7_Pos) /*!< GPDMA0 MASKSRCTRAN: WE_CH7 Mask */
\r
3458 /* ----------------------------- GPDMA0_MASKDSTTRAN ----------------------------- */
\r
3459 #define GPDMA0_MASKDSTTRAN_CH0_Pos 0 /*!< GPDMA0 MASKDSTTRAN: CH0 Position */
\r
3460 #define GPDMA0_MASKDSTTRAN_CH0_Msk (0x01UL << GPDMA0_MASKDSTTRAN_CH0_Pos) /*!< GPDMA0 MASKDSTTRAN: CH0 Mask */
\r
3461 #define GPDMA0_MASKDSTTRAN_CH1_Pos 1 /*!< GPDMA0 MASKDSTTRAN: CH1 Position */
\r
3462 #define GPDMA0_MASKDSTTRAN_CH1_Msk (0x01UL << GPDMA0_MASKDSTTRAN_CH1_Pos) /*!< GPDMA0 MASKDSTTRAN: CH1 Mask */
\r
3463 #define GPDMA0_MASKDSTTRAN_CH2_Pos 2 /*!< GPDMA0 MASKDSTTRAN: CH2 Position */
\r
3464 #define GPDMA0_MASKDSTTRAN_CH2_Msk (0x01UL << GPDMA0_MASKDSTTRAN_CH2_Pos) /*!< GPDMA0 MASKDSTTRAN: CH2 Mask */
\r
3465 #define GPDMA0_MASKDSTTRAN_CH3_Pos 3 /*!< GPDMA0 MASKDSTTRAN: CH3 Position */
\r
3466 #define GPDMA0_MASKDSTTRAN_CH3_Msk (0x01UL << GPDMA0_MASKDSTTRAN_CH3_Pos) /*!< GPDMA0 MASKDSTTRAN: CH3 Mask */
\r
3467 #define GPDMA0_MASKDSTTRAN_CH4_Pos 4 /*!< GPDMA0 MASKDSTTRAN: CH4 Position */
\r
3468 #define GPDMA0_MASKDSTTRAN_CH4_Msk (0x01UL << GPDMA0_MASKDSTTRAN_CH4_Pos) /*!< GPDMA0 MASKDSTTRAN: CH4 Mask */
\r
3469 #define GPDMA0_MASKDSTTRAN_CH5_Pos 5 /*!< GPDMA0 MASKDSTTRAN: CH5 Position */
\r
3470 #define GPDMA0_MASKDSTTRAN_CH5_Msk (0x01UL << GPDMA0_MASKDSTTRAN_CH5_Pos) /*!< GPDMA0 MASKDSTTRAN: CH5 Mask */
\r
3471 #define GPDMA0_MASKDSTTRAN_CH6_Pos 6 /*!< GPDMA0 MASKDSTTRAN: CH6 Position */
\r
3472 #define GPDMA0_MASKDSTTRAN_CH6_Msk (0x01UL << GPDMA0_MASKDSTTRAN_CH6_Pos) /*!< GPDMA0 MASKDSTTRAN: CH6 Mask */
\r
3473 #define GPDMA0_MASKDSTTRAN_CH7_Pos 7 /*!< GPDMA0 MASKDSTTRAN: CH7 Position */
\r
3474 #define GPDMA0_MASKDSTTRAN_CH7_Msk (0x01UL << GPDMA0_MASKDSTTRAN_CH7_Pos) /*!< GPDMA0 MASKDSTTRAN: CH7 Mask */
\r
3475 #define GPDMA0_MASKDSTTRAN_WE_CH0_Pos 8 /*!< GPDMA0 MASKDSTTRAN: WE_CH0 Position */
\r
3476 #define GPDMA0_MASKDSTTRAN_WE_CH0_Msk (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH0_Pos) /*!< GPDMA0 MASKDSTTRAN: WE_CH0 Mask */
\r
3477 #define GPDMA0_MASKDSTTRAN_WE_CH1_Pos 9 /*!< GPDMA0 MASKDSTTRAN: WE_CH1 Position */
\r
3478 #define GPDMA0_MASKDSTTRAN_WE_CH1_Msk (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH1_Pos) /*!< GPDMA0 MASKDSTTRAN: WE_CH1 Mask */
\r
3479 #define GPDMA0_MASKDSTTRAN_WE_CH2_Pos 10 /*!< GPDMA0 MASKDSTTRAN: WE_CH2 Position */
\r
3480 #define GPDMA0_MASKDSTTRAN_WE_CH2_Msk (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH2_Pos) /*!< GPDMA0 MASKDSTTRAN: WE_CH2 Mask */
\r
3481 #define GPDMA0_MASKDSTTRAN_WE_CH3_Pos 11 /*!< GPDMA0 MASKDSTTRAN: WE_CH3 Position */
\r
3482 #define GPDMA0_MASKDSTTRAN_WE_CH3_Msk (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH3_Pos) /*!< GPDMA0 MASKDSTTRAN: WE_CH3 Mask */
\r
3483 #define GPDMA0_MASKDSTTRAN_WE_CH4_Pos 12 /*!< GPDMA0 MASKDSTTRAN: WE_CH4 Position */
\r
3484 #define GPDMA0_MASKDSTTRAN_WE_CH4_Msk (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH4_Pos) /*!< GPDMA0 MASKDSTTRAN: WE_CH4 Mask */
\r
3485 #define GPDMA0_MASKDSTTRAN_WE_CH5_Pos 13 /*!< GPDMA0 MASKDSTTRAN: WE_CH5 Position */
\r
3486 #define GPDMA0_MASKDSTTRAN_WE_CH5_Msk (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH5_Pos) /*!< GPDMA0 MASKDSTTRAN: WE_CH5 Mask */
\r
3487 #define GPDMA0_MASKDSTTRAN_WE_CH6_Pos 14 /*!< GPDMA0 MASKDSTTRAN: WE_CH6 Position */
\r
3488 #define GPDMA0_MASKDSTTRAN_WE_CH6_Msk (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH6_Pos) /*!< GPDMA0 MASKDSTTRAN: WE_CH6 Mask */
\r
3489 #define GPDMA0_MASKDSTTRAN_WE_CH7_Pos 15 /*!< GPDMA0 MASKDSTTRAN: WE_CH7 Position */
\r
3490 #define GPDMA0_MASKDSTTRAN_WE_CH7_Msk (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH7_Pos) /*!< GPDMA0 MASKDSTTRAN: WE_CH7 Mask */
\r
3492 /* ------------------------------- GPDMA0_MASKERR ------------------------------- */
\r
3493 #define GPDMA0_MASKERR_CH0_Pos 0 /*!< GPDMA0 MASKERR: CH0 Position */
\r
3494 #define GPDMA0_MASKERR_CH0_Msk (0x01UL << GPDMA0_MASKERR_CH0_Pos) /*!< GPDMA0 MASKERR: CH0 Mask */
\r
3495 #define GPDMA0_MASKERR_CH1_Pos 1 /*!< GPDMA0 MASKERR: CH1 Position */
\r
3496 #define GPDMA0_MASKERR_CH1_Msk (0x01UL << GPDMA0_MASKERR_CH1_Pos) /*!< GPDMA0 MASKERR: CH1 Mask */
\r
3497 #define GPDMA0_MASKERR_CH2_Pos 2 /*!< GPDMA0 MASKERR: CH2 Position */
\r
3498 #define GPDMA0_MASKERR_CH2_Msk (0x01UL << GPDMA0_MASKERR_CH2_Pos) /*!< GPDMA0 MASKERR: CH2 Mask */
\r
3499 #define GPDMA0_MASKERR_CH3_Pos 3 /*!< GPDMA0 MASKERR: CH3 Position */
\r
3500 #define GPDMA0_MASKERR_CH3_Msk (0x01UL << GPDMA0_MASKERR_CH3_Pos) /*!< GPDMA0 MASKERR: CH3 Mask */
\r
3501 #define GPDMA0_MASKERR_CH4_Pos 4 /*!< GPDMA0 MASKERR: CH4 Position */
\r
3502 #define GPDMA0_MASKERR_CH4_Msk (0x01UL << GPDMA0_MASKERR_CH4_Pos) /*!< GPDMA0 MASKERR: CH4 Mask */
\r
3503 #define GPDMA0_MASKERR_CH5_Pos 5 /*!< GPDMA0 MASKERR: CH5 Position */
\r
3504 #define GPDMA0_MASKERR_CH5_Msk (0x01UL << GPDMA0_MASKERR_CH5_Pos) /*!< GPDMA0 MASKERR: CH5 Mask */
\r
3505 #define GPDMA0_MASKERR_CH6_Pos 6 /*!< GPDMA0 MASKERR: CH6 Position */
\r
3506 #define GPDMA0_MASKERR_CH6_Msk (0x01UL << GPDMA0_MASKERR_CH6_Pos) /*!< GPDMA0 MASKERR: CH6 Mask */
\r
3507 #define GPDMA0_MASKERR_CH7_Pos 7 /*!< GPDMA0 MASKERR: CH7 Position */
\r
3508 #define GPDMA0_MASKERR_CH7_Msk (0x01UL << GPDMA0_MASKERR_CH7_Pos) /*!< GPDMA0 MASKERR: CH7 Mask */
\r
3509 #define GPDMA0_MASKERR_WE_CH0_Pos 8 /*!< GPDMA0 MASKERR: WE_CH0 Position */
\r
3510 #define GPDMA0_MASKERR_WE_CH0_Msk (0x01UL << GPDMA0_MASKERR_WE_CH0_Pos) /*!< GPDMA0 MASKERR: WE_CH0 Mask */
\r
3511 #define GPDMA0_MASKERR_WE_CH1_Pos 9 /*!< GPDMA0 MASKERR: WE_CH1 Position */
\r
3512 #define GPDMA0_MASKERR_WE_CH1_Msk (0x01UL << GPDMA0_MASKERR_WE_CH1_Pos) /*!< GPDMA0 MASKERR: WE_CH1 Mask */
\r
3513 #define GPDMA0_MASKERR_WE_CH2_Pos 10 /*!< GPDMA0 MASKERR: WE_CH2 Position */
\r
3514 #define GPDMA0_MASKERR_WE_CH2_Msk (0x01UL << GPDMA0_MASKERR_WE_CH2_Pos) /*!< GPDMA0 MASKERR: WE_CH2 Mask */
\r
3515 #define GPDMA0_MASKERR_WE_CH3_Pos 11 /*!< GPDMA0 MASKERR: WE_CH3 Position */
\r
3516 #define GPDMA0_MASKERR_WE_CH3_Msk (0x01UL << GPDMA0_MASKERR_WE_CH3_Pos) /*!< GPDMA0 MASKERR: WE_CH3 Mask */
\r
3517 #define GPDMA0_MASKERR_WE_CH4_Pos 12 /*!< GPDMA0 MASKERR: WE_CH4 Position */
\r
3518 #define GPDMA0_MASKERR_WE_CH4_Msk (0x01UL << GPDMA0_MASKERR_WE_CH4_Pos) /*!< GPDMA0 MASKERR: WE_CH4 Mask */
\r
3519 #define GPDMA0_MASKERR_WE_CH5_Pos 13 /*!< GPDMA0 MASKERR: WE_CH5 Position */
\r
3520 #define GPDMA0_MASKERR_WE_CH5_Msk (0x01UL << GPDMA0_MASKERR_WE_CH5_Pos) /*!< GPDMA0 MASKERR: WE_CH5 Mask */
\r
3521 #define GPDMA0_MASKERR_WE_CH6_Pos 14 /*!< GPDMA0 MASKERR: WE_CH6 Position */
\r
3522 #define GPDMA0_MASKERR_WE_CH6_Msk (0x01UL << GPDMA0_MASKERR_WE_CH6_Pos) /*!< GPDMA0 MASKERR: WE_CH6 Mask */
\r
3523 #define GPDMA0_MASKERR_WE_CH7_Pos 15 /*!< GPDMA0 MASKERR: WE_CH7 Position */
\r
3524 #define GPDMA0_MASKERR_WE_CH7_Msk (0x01UL << GPDMA0_MASKERR_WE_CH7_Pos) /*!< GPDMA0 MASKERR: WE_CH7 Mask */
\r
3526 /* ------------------------------- GPDMA0_CLEARTFR ------------------------------ */
\r
3527 #define GPDMA0_CLEARTFR_CH0_Pos 0 /*!< GPDMA0 CLEARTFR: CH0 Position */
\r
3528 #define GPDMA0_CLEARTFR_CH0_Msk (0x01UL << GPDMA0_CLEARTFR_CH0_Pos) /*!< GPDMA0 CLEARTFR: CH0 Mask */
\r
3529 #define GPDMA0_CLEARTFR_CH1_Pos 1 /*!< GPDMA0 CLEARTFR: CH1 Position */
\r
3530 #define GPDMA0_CLEARTFR_CH1_Msk (0x01UL << GPDMA0_CLEARTFR_CH1_Pos) /*!< GPDMA0 CLEARTFR: CH1 Mask */
\r
3531 #define GPDMA0_CLEARTFR_CH2_Pos 2 /*!< GPDMA0 CLEARTFR: CH2 Position */
\r
3532 #define GPDMA0_CLEARTFR_CH2_Msk (0x01UL << GPDMA0_CLEARTFR_CH2_Pos) /*!< GPDMA0 CLEARTFR: CH2 Mask */
\r
3533 #define GPDMA0_CLEARTFR_CH3_Pos 3 /*!< GPDMA0 CLEARTFR: CH3 Position */
\r
3534 #define GPDMA0_CLEARTFR_CH3_Msk (0x01UL << GPDMA0_CLEARTFR_CH3_Pos) /*!< GPDMA0 CLEARTFR: CH3 Mask */
\r
3535 #define GPDMA0_CLEARTFR_CH4_Pos 4 /*!< GPDMA0 CLEARTFR: CH4 Position */
\r
3536 #define GPDMA0_CLEARTFR_CH4_Msk (0x01UL << GPDMA0_CLEARTFR_CH4_Pos) /*!< GPDMA0 CLEARTFR: CH4 Mask */
\r
3537 #define GPDMA0_CLEARTFR_CH5_Pos 5 /*!< GPDMA0 CLEARTFR: CH5 Position */
\r
3538 #define GPDMA0_CLEARTFR_CH5_Msk (0x01UL << GPDMA0_CLEARTFR_CH5_Pos) /*!< GPDMA0 CLEARTFR: CH5 Mask */
\r
3539 #define GPDMA0_CLEARTFR_CH6_Pos 6 /*!< GPDMA0 CLEARTFR: CH6 Position */
\r
3540 #define GPDMA0_CLEARTFR_CH6_Msk (0x01UL << GPDMA0_CLEARTFR_CH6_Pos) /*!< GPDMA0 CLEARTFR: CH6 Mask */
\r
3541 #define GPDMA0_CLEARTFR_CH7_Pos 7 /*!< GPDMA0 CLEARTFR: CH7 Position */
\r
3542 #define GPDMA0_CLEARTFR_CH7_Msk (0x01UL << GPDMA0_CLEARTFR_CH7_Pos) /*!< GPDMA0 CLEARTFR: CH7 Mask */
\r
3544 /* ------------------------------ GPDMA0_CLEARBLOCK ----------------------------- */
\r
3545 #define GPDMA0_CLEARBLOCK_CH0_Pos 0 /*!< GPDMA0 CLEARBLOCK: CH0 Position */
\r
3546 #define GPDMA0_CLEARBLOCK_CH0_Msk (0x01UL << GPDMA0_CLEARBLOCK_CH0_Pos) /*!< GPDMA0 CLEARBLOCK: CH0 Mask */
\r
3547 #define GPDMA0_CLEARBLOCK_CH1_Pos 1 /*!< GPDMA0 CLEARBLOCK: CH1 Position */
\r
3548 #define GPDMA0_CLEARBLOCK_CH1_Msk (0x01UL << GPDMA0_CLEARBLOCK_CH1_Pos) /*!< GPDMA0 CLEARBLOCK: CH1 Mask */
\r
3549 #define GPDMA0_CLEARBLOCK_CH2_Pos 2 /*!< GPDMA0 CLEARBLOCK: CH2 Position */
\r
3550 #define GPDMA0_CLEARBLOCK_CH2_Msk (0x01UL << GPDMA0_CLEARBLOCK_CH2_Pos) /*!< GPDMA0 CLEARBLOCK: CH2 Mask */
\r
3551 #define GPDMA0_CLEARBLOCK_CH3_Pos 3 /*!< GPDMA0 CLEARBLOCK: CH3 Position */
\r
3552 #define GPDMA0_CLEARBLOCK_CH3_Msk (0x01UL << GPDMA0_CLEARBLOCK_CH3_Pos) /*!< GPDMA0 CLEARBLOCK: CH3 Mask */
\r
3553 #define GPDMA0_CLEARBLOCK_CH4_Pos 4 /*!< GPDMA0 CLEARBLOCK: CH4 Position */
\r
3554 #define GPDMA0_CLEARBLOCK_CH4_Msk (0x01UL << GPDMA0_CLEARBLOCK_CH4_Pos) /*!< GPDMA0 CLEARBLOCK: CH4 Mask */
\r
3555 #define GPDMA0_CLEARBLOCK_CH5_Pos 5 /*!< GPDMA0 CLEARBLOCK: CH5 Position */
\r
3556 #define GPDMA0_CLEARBLOCK_CH5_Msk (0x01UL << GPDMA0_CLEARBLOCK_CH5_Pos) /*!< GPDMA0 CLEARBLOCK: CH5 Mask */
\r
3557 #define GPDMA0_CLEARBLOCK_CH6_Pos 6 /*!< GPDMA0 CLEARBLOCK: CH6 Position */
\r
3558 #define GPDMA0_CLEARBLOCK_CH6_Msk (0x01UL << GPDMA0_CLEARBLOCK_CH6_Pos) /*!< GPDMA0 CLEARBLOCK: CH6 Mask */
\r
3559 #define GPDMA0_CLEARBLOCK_CH7_Pos 7 /*!< GPDMA0 CLEARBLOCK: CH7 Position */
\r
3560 #define GPDMA0_CLEARBLOCK_CH7_Msk (0x01UL << GPDMA0_CLEARBLOCK_CH7_Pos) /*!< GPDMA0 CLEARBLOCK: CH7 Mask */
\r
3562 /* ----------------------------- GPDMA0_CLEARSRCTRAN ---------------------------- */
\r
3563 #define GPDMA0_CLEARSRCTRAN_CH0_Pos 0 /*!< GPDMA0 CLEARSRCTRAN: CH0 Position */
\r
3564 #define GPDMA0_CLEARSRCTRAN_CH0_Msk (0x01UL << GPDMA0_CLEARSRCTRAN_CH0_Pos) /*!< GPDMA0 CLEARSRCTRAN: CH0 Mask */
\r
3565 #define GPDMA0_CLEARSRCTRAN_CH1_Pos 1 /*!< GPDMA0 CLEARSRCTRAN: CH1 Position */
\r
3566 #define GPDMA0_CLEARSRCTRAN_CH1_Msk (0x01UL << GPDMA0_CLEARSRCTRAN_CH1_Pos) /*!< GPDMA0 CLEARSRCTRAN: CH1 Mask */
\r
3567 #define GPDMA0_CLEARSRCTRAN_CH2_Pos 2 /*!< GPDMA0 CLEARSRCTRAN: CH2 Position */
\r
3568 #define GPDMA0_CLEARSRCTRAN_CH2_Msk (0x01UL << GPDMA0_CLEARSRCTRAN_CH2_Pos) /*!< GPDMA0 CLEARSRCTRAN: CH2 Mask */
\r
3569 #define GPDMA0_CLEARSRCTRAN_CH3_Pos 3 /*!< GPDMA0 CLEARSRCTRAN: CH3 Position */
\r
3570 #define GPDMA0_CLEARSRCTRAN_CH3_Msk (0x01UL << GPDMA0_CLEARSRCTRAN_CH3_Pos) /*!< GPDMA0 CLEARSRCTRAN: CH3 Mask */
\r
3571 #define GPDMA0_CLEARSRCTRAN_CH4_Pos 4 /*!< GPDMA0 CLEARSRCTRAN: CH4 Position */
\r
3572 #define GPDMA0_CLEARSRCTRAN_CH4_Msk (0x01UL << GPDMA0_CLEARSRCTRAN_CH4_Pos) /*!< GPDMA0 CLEARSRCTRAN: CH4 Mask */
\r
3573 #define GPDMA0_CLEARSRCTRAN_CH5_Pos 5 /*!< GPDMA0 CLEARSRCTRAN: CH5 Position */
\r
3574 #define GPDMA0_CLEARSRCTRAN_CH5_Msk (0x01UL << GPDMA0_CLEARSRCTRAN_CH5_Pos) /*!< GPDMA0 CLEARSRCTRAN: CH5 Mask */
\r
3575 #define GPDMA0_CLEARSRCTRAN_CH6_Pos 6 /*!< GPDMA0 CLEARSRCTRAN: CH6 Position */
\r
3576 #define GPDMA0_CLEARSRCTRAN_CH6_Msk (0x01UL << GPDMA0_CLEARSRCTRAN_CH6_Pos) /*!< GPDMA0 CLEARSRCTRAN: CH6 Mask */
\r
3577 #define GPDMA0_CLEARSRCTRAN_CH7_Pos 7 /*!< GPDMA0 CLEARSRCTRAN: CH7 Position */
\r
3578 #define GPDMA0_CLEARSRCTRAN_CH7_Msk (0x01UL << GPDMA0_CLEARSRCTRAN_CH7_Pos) /*!< GPDMA0 CLEARSRCTRAN: CH7 Mask */
\r
3580 /* ----------------------------- GPDMA0_CLEARDSTTRAN ---------------------------- */
\r
3581 #define GPDMA0_CLEARDSTTRAN_CH0_Pos 0 /*!< GPDMA0 CLEARDSTTRAN: CH0 Position */
\r
3582 #define GPDMA0_CLEARDSTTRAN_CH0_Msk (0x01UL << GPDMA0_CLEARDSTTRAN_CH0_Pos) /*!< GPDMA0 CLEARDSTTRAN: CH0 Mask */
\r
3583 #define GPDMA0_CLEARDSTTRAN_CH1_Pos 1 /*!< GPDMA0 CLEARDSTTRAN: CH1 Position */
\r
3584 #define GPDMA0_CLEARDSTTRAN_CH1_Msk (0x01UL << GPDMA0_CLEARDSTTRAN_CH1_Pos) /*!< GPDMA0 CLEARDSTTRAN: CH1 Mask */
\r
3585 #define GPDMA0_CLEARDSTTRAN_CH2_Pos 2 /*!< GPDMA0 CLEARDSTTRAN: CH2 Position */
\r
3586 #define GPDMA0_CLEARDSTTRAN_CH2_Msk (0x01UL << GPDMA0_CLEARDSTTRAN_CH2_Pos) /*!< GPDMA0 CLEARDSTTRAN: CH2 Mask */
\r
3587 #define GPDMA0_CLEARDSTTRAN_CH3_Pos 3 /*!< GPDMA0 CLEARDSTTRAN: CH3 Position */
\r
3588 #define GPDMA0_CLEARDSTTRAN_CH3_Msk (0x01UL << GPDMA0_CLEARDSTTRAN_CH3_Pos) /*!< GPDMA0 CLEARDSTTRAN: CH3 Mask */
\r
3589 #define GPDMA0_CLEARDSTTRAN_CH4_Pos 4 /*!< GPDMA0 CLEARDSTTRAN: CH4 Position */
\r
3590 #define GPDMA0_CLEARDSTTRAN_CH4_Msk (0x01UL << GPDMA0_CLEARDSTTRAN_CH4_Pos) /*!< GPDMA0 CLEARDSTTRAN: CH4 Mask */
\r
3591 #define GPDMA0_CLEARDSTTRAN_CH5_Pos 5 /*!< GPDMA0 CLEARDSTTRAN: CH5 Position */
\r
3592 #define GPDMA0_CLEARDSTTRAN_CH5_Msk (0x01UL << GPDMA0_CLEARDSTTRAN_CH5_Pos) /*!< GPDMA0 CLEARDSTTRAN: CH5 Mask */
\r
3593 #define GPDMA0_CLEARDSTTRAN_CH6_Pos 6 /*!< GPDMA0 CLEARDSTTRAN: CH6 Position */
\r
3594 #define GPDMA0_CLEARDSTTRAN_CH6_Msk (0x01UL << GPDMA0_CLEARDSTTRAN_CH6_Pos) /*!< GPDMA0 CLEARDSTTRAN: CH6 Mask */
\r
3595 #define GPDMA0_CLEARDSTTRAN_CH7_Pos 7 /*!< GPDMA0 CLEARDSTTRAN: CH7 Position */
\r
3596 #define GPDMA0_CLEARDSTTRAN_CH7_Msk (0x01UL << GPDMA0_CLEARDSTTRAN_CH7_Pos) /*!< GPDMA0 CLEARDSTTRAN: CH7 Mask */
\r
3598 /* ------------------------------- GPDMA0_CLEARERR ------------------------------ */
\r
3599 #define GPDMA0_CLEARERR_CH0_Pos 0 /*!< GPDMA0 CLEARERR: CH0 Position */
\r
3600 #define GPDMA0_CLEARERR_CH0_Msk (0x01UL << GPDMA0_CLEARERR_CH0_Pos) /*!< GPDMA0 CLEARERR: CH0 Mask */
\r
3601 #define GPDMA0_CLEARERR_CH1_Pos 1 /*!< GPDMA0 CLEARERR: CH1 Position */
\r
3602 #define GPDMA0_CLEARERR_CH1_Msk (0x01UL << GPDMA0_CLEARERR_CH1_Pos) /*!< GPDMA0 CLEARERR: CH1 Mask */
\r
3603 #define GPDMA0_CLEARERR_CH2_Pos 2 /*!< GPDMA0 CLEARERR: CH2 Position */
\r
3604 #define GPDMA0_CLEARERR_CH2_Msk (0x01UL << GPDMA0_CLEARERR_CH2_Pos) /*!< GPDMA0 CLEARERR: CH2 Mask */
\r
3605 #define GPDMA0_CLEARERR_CH3_Pos 3 /*!< GPDMA0 CLEARERR: CH3 Position */
\r
3606 #define GPDMA0_CLEARERR_CH3_Msk (0x01UL << GPDMA0_CLEARERR_CH3_Pos) /*!< GPDMA0 CLEARERR: CH3 Mask */
\r
3607 #define GPDMA0_CLEARERR_CH4_Pos 4 /*!< GPDMA0 CLEARERR: CH4 Position */
\r
3608 #define GPDMA0_CLEARERR_CH4_Msk (0x01UL << GPDMA0_CLEARERR_CH4_Pos) /*!< GPDMA0 CLEARERR: CH4 Mask */
\r
3609 #define GPDMA0_CLEARERR_CH5_Pos 5 /*!< GPDMA0 CLEARERR: CH5 Position */
\r
3610 #define GPDMA0_CLEARERR_CH5_Msk (0x01UL << GPDMA0_CLEARERR_CH5_Pos) /*!< GPDMA0 CLEARERR: CH5 Mask */
\r
3611 #define GPDMA0_CLEARERR_CH6_Pos 6 /*!< GPDMA0 CLEARERR: CH6 Position */
\r
3612 #define GPDMA0_CLEARERR_CH6_Msk (0x01UL << GPDMA0_CLEARERR_CH6_Pos) /*!< GPDMA0 CLEARERR: CH6 Mask */
\r
3613 #define GPDMA0_CLEARERR_CH7_Pos 7 /*!< GPDMA0 CLEARERR: CH7 Position */
\r
3614 #define GPDMA0_CLEARERR_CH7_Msk (0x01UL << GPDMA0_CLEARERR_CH7_Pos) /*!< GPDMA0 CLEARERR: CH7 Mask */
\r
3616 /* ------------------------------ GPDMA0_STATUSINT ------------------------------ */
\r
3617 #define GPDMA0_STATUSINT_TFR_Pos 0 /*!< GPDMA0 STATUSINT: TFR Position */
\r
3618 #define GPDMA0_STATUSINT_TFR_Msk (0x01UL << GPDMA0_STATUSINT_TFR_Pos) /*!< GPDMA0 STATUSINT: TFR Mask */
\r
3619 #define GPDMA0_STATUSINT_BLOCK_Pos 1 /*!< GPDMA0 STATUSINT: BLOCK Position */
\r
3620 #define GPDMA0_STATUSINT_BLOCK_Msk (0x01UL << GPDMA0_STATUSINT_BLOCK_Pos) /*!< GPDMA0 STATUSINT: BLOCK Mask */
\r
3621 #define GPDMA0_STATUSINT_SRCT_Pos 2 /*!< GPDMA0 STATUSINT: SRCT Position */
\r
3622 #define GPDMA0_STATUSINT_SRCT_Msk (0x01UL << GPDMA0_STATUSINT_SRCT_Pos) /*!< GPDMA0 STATUSINT: SRCT Mask */
\r
3623 #define GPDMA0_STATUSINT_DSTT_Pos 3 /*!< GPDMA0 STATUSINT: DSTT Position */
\r
3624 #define GPDMA0_STATUSINT_DSTT_Msk (0x01UL << GPDMA0_STATUSINT_DSTT_Pos) /*!< GPDMA0 STATUSINT: DSTT Mask */
\r
3625 #define GPDMA0_STATUSINT_ERR_Pos 4 /*!< GPDMA0 STATUSINT: ERR Position */
\r
3626 #define GPDMA0_STATUSINT_ERR_Msk (0x01UL << GPDMA0_STATUSINT_ERR_Pos) /*!< GPDMA0 STATUSINT: ERR Mask */
\r
3628 /* ------------------------------ GPDMA0_REQSRCREG ------------------------------ */
\r
3629 #define GPDMA0_REQSRCREG_CH0_Pos 0 /*!< GPDMA0 REQSRCREG: CH0 Position */
\r
3630 #define GPDMA0_REQSRCREG_CH0_Msk (0x01UL << GPDMA0_REQSRCREG_CH0_Pos) /*!< GPDMA0 REQSRCREG: CH0 Mask */
\r
3631 #define GPDMA0_REQSRCREG_CH1_Pos 1 /*!< GPDMA0 REQSRCREG: CH1 Position */
\r
3632 #define GPDMA0_REQSRCREG_CH1_Msk (0x01UL << GPDMA0_REQSRCREG_CH1_Pos) /*!< GPDMA0 REQSRCREG: CH1 Mask */
\r
3633 #define GPDMA0_REQSRCREG_CH2_Pos 2 /*!< GPDMA0 REQSRCREG: CH2 Position */
\r
3634 #define GPDMA0_REQSRCREG_CH2_Msk (0x01UL << GPDMA0_REQSRCREG_CH2_Pos) /*!< GPDMA0 REQSRCREG: CH2 Mask */
\r
3635 #define GPDMA0_REQSRCREG_CH3_Pos 3 /*!< GPDMA0 REQSRCREG: CH3 Position */
\r
3636 #define GPDMA0_REQSRCREG_CH3_Msk (0x01UL << GPDMA0_REQSRCREG_CH3_Pos) /*!< GPDMA0 REQSRCREG: CH3 Mask */
\r
3637 #define GPDMA0_REQSRCREG_CH4_Pos 4 /*!< GPDMA0 REQSRCREG: CH4 Position */
\r
3638 #define GPDMA0_REQSRCREG_CH4_Msk (0x01UL << GPDMA0_REQSRCREG_CH4_Pos) /*!< GPDMA0 REQSRCREG: CH4 Mask */
\r
3639 #define GPDMA0_REQSRCREG_CH5_Pos 5 /*!< GPDMA0 REQSRCREG: CH5 Position */
\r
3640 #define GPDMA0_REQSRCREG_CH5_Msk (0x01UL << GPDMA0_REQSRCREG_CH5_Pos) /*!< GPDMA0 REQSRCREG: CH5 Mask */
\r
3641 #define GPDMA0_REQSRCREG_CH6_Pos 6 /*!< GPDMA0 REQSRCREG: CH6 Position */
\r
3642 #define GPDMA0_REQSRCREG_CH6_Msk (0x01UL << GPDMA0_REQSRCREG_CH6_Pos) /*!< GPDMA0 REQSRCREG: CH6 Mask */
\r
3643 #define GPDMA0_REQSRCREG_CH7_Pos 7 /*!< GPDMA0 REQSRCREG: CH7 Position */
\r
3644 #define GPDMA0_REQSRCREG_CH7_Msk (0x01UL << GPDMA0_REQSRCREG_CH7_Pos) /*!< GPDMA0 REQSRCREG: CH7 Mask */
\r
3645 #define GPDMA0_REQSRCREG_WE_CH0_Pos 8 /*!< GPDMA0 REQSRCREG: WE_CH0 Position */
\r
3646 #define GPDMA0_REQSRCREG_WE_CH0_Msk (0x01UL << GPDMA0_REQSRCREG_WE_CH0_Pos) /*!< GPDMA0 REQSRCREG: WE_CH0 Mask */
\r
3647 #define GPDMA0_REQSRCREG_WE_CH1_Pos 9 /*!< GPDMA0 REQSRCREG: WE_CH1 Position */
\r
3648 #define GPDMA0_REQSRCREG_WE_CH1_Msk (0x01UL << GPDMA0_REQSRCREG_WE_CH1_Pos) /*!< GPDMA0 REQSRCREG: WE_CH1 Mask */
\r
3649 #define GPDMA0_REQSRCREG_WE_CH2_Pos 10 /*!< GPDMA0 REQSRCREG: WE_CH2 Position */
\r
3650 #define GPDMA0_REQSRCREG_WE_CH2_Msk (0x01UL << GPDMA0_REQSRCREG_WE_CH2_Pos) /*!< GPDMA0 REQSRCREG: WE_CH2 Mask */
\r
3651 #define GPDMA0_REQSRCREG_WE_CH3_Pos 11 /*!< GPDMA0 REQSRCREG: WE_CH3 Position */
\r
3652 #define GPDMA0_REQSRCREG_WE_CH3_Msk (0x01UL << GPDMA0_REQSRCREG_WE_CH3_Pos) /*!< GPDMA0 REQSRCREG: WE_CH3 Mask */
\r
3653 #define GPDMA0_REQSRCREG_WE_CH4_Pos 12 /*!< GPDMA0 REQSRCREG: WE_CH4 Position */
\r
3654 #define GPDMA0_REQSRCREG_WE_CH4_Msk (0x01UL << GPDMA0_REQSRCREG_WE_CH4_Pos) /*!< GPDMA0 REQSRCREG: WE_CH4 Mask */
\r
3655 #define GPDMA0_REQSRCREG_WE_CH5_Pos 13 /*!< GPDMA0 REQSRCREG: WE_CH5 Position */
\r
3656 #define GPDMA0_REQSRCREG_WE_CH5_Msk (0x01UL << GPDMA0_REQSRCREG_WE_CH5_Pos) /*!< GPDMA0 REQSRCREG: WE_CH5 Mask */
\r
3657 #define GPDMA0_REQSRCREG_WE_CH6_Pos 14 /*!< GPDMA0 REQSRCREG: WE_CH6 Position */
\r
3658 #define GPDMA0_REQSRCREG_WE_CH6_Msk (0x01UL << GPDMA0_REQSRCREG_WE_CH6_Pos) /*!< GPDMA0 REQSRCREG: WE_CH6 Mask */
\r
3659 #define GPDMA0_REQSRCREG_WE_CH7_Pos 15 /*!< GPDMA0 REQSRCREG: WE_CH7 Position */
\r
3660 #define GPDMA0_REQSRCREG_WE_CH7_Msk (0x01UL << GPDMA0_REQSRCREG_WE_CH7_Pos) /*!< GPDMA0 REQSRCREG: WE_CH7 Mask */
\r
3662 /* ------------------------------ GPDMA0_REQDSTREG ------------------------------ */
\r
3663 #define GPDMA0_REQDSTREG_CH0_Pos 0 /*!< GPDMA0 REQDSTREG: CH0 Position */
\r
3664 #define GPDMA0_REQDSTREG_CH0_Msk (0x01UL << GPDMA0_REQDSTREG_CH0_Pos) /*!< GPDMA0 REQDSTREG: CH0 Mask */
\r
3665 #define GPDMA0_REQDSTREG_CH1_Pos 1 /*!< GPDMA0 REQDSTREG: CH1 Position */
\r
3666 #define GPDMA0_REQDSTREG_CH1_Msk (0x01UL << GPDMA0_REQDSTREG_CH1_Pos) /*!< GPDMA0 REQDSTREG: CH1 Mask */
\r
3667 #define GPDMA0_REQDSTREG_CH2_Pos 2 /*!< GPDMA0 REQDSTREG: CH2 Position */
\r
3668 #define GPDMA0_REQDSTREG_CH2_Msk (0x01UL << GPDMA0_REQDSTREG_CH2_Pos) /*!< GPDMA0 REQDSTREG: CH2 Mask */
\r
3669 #define GPDMA0_REQDSTREG_CH3_Pos 3 /*!< GPDMA0 REQDSTREG: CH3 Position */
\r
3670 #define GPDMA0_REQDSTREG_CH3_Msk (0x01UL << GPDMA0_REQDSTREG_CH3_Pos) /*!< GPDMA0 REQDSTREG: CH3 Mask */
\r
3671 #define GPDMA0_REQDSTREG_CH4_Pos 4 /*!< GPDMA0 REQDSTREG: CH4 Position */
\r
3672 #define GPDMA0_REQDSTREG_CH4_Msk (0x01UL << GPDMA0_REQDSTREG_CH4_Pos) /*!< GPDMA0 REQDSTREG: CH4 Mask */
\r
3673 #define GPDMA0_REQDSTREG_CH5_Pos 5 /*!< GPDMA0 REQDSTREG: CH5 Position */
\r
3674 #define GPDMA0_REQDSTREG_CH5_Msk (0x01UL << GPDMA0_REQDSTREG_CH5_Pos) /*!< GPDMA0 REQDSTREG: CH5 Mask */
\r
3675 #define GPDMA0_REQDSTREG_CH6_Pos 6 /*!< GPDMA0 REQDSTREG: CH6 Position */
\r
3676 #define GPDMA0_REQDSTREG_CH6_Msk (0x01UL << GPDMA0_REQDSTREG_CH6_Pos) /*!< GPDMA0 REQDSTREG: CH6 Mask */
\r
3677 #define GPDMA0_REQDSTREG_CH7_Pos 7 /*!< GPDMA0 REQDSTREG: CH7 Position */
\r
3678 #define GPDMA0_REQDSTREG_CH7_Msk (0x01UL << GPDMA0_REQDSTREG_CH7_Pos) /*!< GPDMA0 REQDSTREG: CH7 Mask */
\r
3679 #define GPDMA0_REQDSTREG_WE_CH0_Pos 8 /*!< GPDMA0 REQDSTREG: WE_CH0 Position */
\r
3680 #define GPDMA0_REQDSTREG_WE_CH0_Msk (0x01UL << GPDMA0_REQDSTREG_WE_CH0_Pos) /*!< GPDMA0 REQDSTREG: WE_CH0 Mask */
\r
3681 #define GPDMA0_REQDSTREG_WE_CH1_Pos 9 /*!< GPDMA0 REQDSTREG: WE_CH1 Position */
\r
3682 #define GPDMA0_REQDSTREG_WE_CH1_Msk (0x01UL << GPDMA0_REQDSTREG_WE_CH1_Pos) /*!< GPDMA0 REQDSTREG: WE_CH1 Mask */
\r
3683 #define GPDMA0_REQDSTREG_WE_CH2_Pos 10 /*!< GPDMA0 REQDSTREG: WE_CH2 Position */
\r
3684 #define GPDMA0_REQDSTREG_WE_CH2_Msk (0x01UL << GPDMA0_REQDSTREG_WE_CH2_Pos) /*!< GPDMA0 REQDSTREG: WE_CH2 Mask */
\r
3685 #define GPDMA0_REQDSTREG_WE_CH3_Pos 11 /*!< GPDMA0 REQDSTREG: WE_CH3 Position */
\r
3686 #define GPDMA0_REQDSTREG_WE_CH3_Msk (0x01UL << GPDMA0_REQDSTREG_WE_CH3_Pos) /*!< GPDMA0 REQDSTREG: WE_CH3 Mask */
\r
3687 #define GPDMA0_REQDSTREG_WE_CH4_Pos 12 /*!< GPDMA0 REQDSTREG: WE_CH4 Position */
\r
3688 #define GPDMA0_REQDSTREG_WE_CH4_Msk (0x01UL << GPDMA0_REQDSTREG_WE_CH4_Pos) /*!< GPDMA0 REQDSTREG: WE_CH4 Mask */
\r
3689 #define GPDMA0_REQDSTREG_WE_CH5_Pos 13 /*!< GPDMA0 REQDSTREG: WE_CH5 Position */
\r
3690 #define GPDMA0_REQDSTREG_WE_CH5_Msk (0x01UL << GPDMA0_REQDSTREG_WE_CH5_Pos) /*!< GPDMA0 REQDSTREG: WE_CH5 Mask */
\r
3691 #define GPDMA0_REQDSTREG_WE_CH6_Pos 14 /*!< GPDMA0 REQDSTREG: WE_CH6 Position */
\r
3692 #define GPDMA0_REQDSTREG_WE_CH6_Msk (0x01UL << GPDMA0_REQDSTREG_WE_CH6_Pos) /*!< GPDMA0 REQDSTREG: WE_CH6 Mask */
\r
3693 #define GPDMA0_REQDSTREG_WE_CH7_Pos 15 /*!< GPDMA0 REQDSTREG: WE_CH7 Position */
\r
3694 #define GPDMA0_REQDSTREG_WE_CH7_Msk (0x01UL << GPDMA0_REQDSTREG_WE_CH7_Pos) /*!< GPDMA0 REQDSTREG: WE_CH7 Mask */
\r
3696 /* ----------------------------- GPDMA0_SGLREQSRCREG ---------------------------- */
\r
3697 #define GPDMA0_SGLREQSRCREG_CH0_Pos 0 /*!< GPDMA0 SGLREQSRCREG: CH0 Position */
\r
3698 #define GPDMA0_SGLREQSRCREG_CH0_Msk (0x01UL << GPDMA0_SGLREQSRCREG_CH0_Pos) /*!< GPDMA0 SGLREQSRCREG: CH0 Mask */
\r
3699 #define GPDMA0_SGLREQSRCREG_CH1_Pos 1 /*!< GPDMA0 SGLREQSRCREG: CH1 Position */
\r
3700 #define GPDMA0_SGLREQSRCREG_CH1_Msk (0x01UL << GPDMA0_SGLREQSRCREG_CH1_Pos) /*!< GPDMA0 SGLREQSRCREG: CH1 Mask */
\r
3701 #define GPDMA0_SGLREQSRCREG_CH2_Pos 2 /*!< GPDMA0 SGLREQSRCREG: CH2 Position */
\r
3702 #define GPDMA0_SGLREQSRCREG_CH2_Msk (0x01UL << GPDMA0_SGLREQSRCREG_CH2_Pos) /*!< GPDMA0 SGLREQSRCREG: CH2 Mask */
\r
3703 #define GPDMA0_SGLREQSRCREG_CH3_Pos 3 /*!< GPDMA0 SGLREQSRCREG: CH3 Position */
\r
3704 #define GPDMA0_SGLREQSRCREG_CH3_Msk (0x01UL << GPDMA0_SGLREQSRCREG_CH3_Pos) /*!< GPDMA0 SGLREQSRCREG: CH3 Mask */
\r
3705 #define GPDMA0_SGLREQSRCREG_CH4_Pos 4 /*!< GPDMA0 SGLREQSRCREG: CH4 Position */
\r
3706 #define GPDMA0_SGLREQSRCREG_CH4_Msk (0x01UL << GPDMA0_SGLREQSRCREG_CH4_Pos) /*!< GPDMA0 SGLREQSRCREG: CH4 Mask */
\r
3707 #define GPDMA0_SGLREQSRCREG_CH5_Pos 5 /*!< GPDMA0 SGLREQSRCREG: CH5 Position */
\r
3708 #define GPDMA0_SGLREQSRCREG_CH5_Msk (0x01UL << GPDMA0_SGLREQSRCREG_CH5_Pos) /*!< GPDMA0 SGLREQSRCREG: CH5 Mask */
\r
3709 #define GPDMA0_SGLREQSRCREG_CH6_Pos 6 /*!< GPDMA0 SGLREQSRCREG: CH6 Position */
\r
3710 #define GPDMA0_SGLREQSRCREG_CH6_Msk (0x01UL << GPDMA0_SGLREQSRCREG_CH6_Pos) /*!< GPDMA0 SGLREQSRCREG: CH6 Mask */
\r
3711 #define GPDMA0_SGLREQSRCREG_CH7_Pos 7 /*!< GPDMA0 SGLREQSRCREG: CH7 Position */
\r
3712 #define GPDMA0_SGLREQSRCREG_CH7_Msk (0x01UL << GPDMA0_SGLREQSRCREG_CH7_Pos) /*!< GPDMA0 SGLREQSRCREG: CH7 Mask */
\r
3713 #define GPDMA0_SGLREQSRCREG_WE_CH0_Pos 8 /*!< GPDMA0 SGLREQSRCREG: WE_CH0 Position */
\r
3714 #define GPDMA0_SGLREQSRCREG_WE_CH0_Msk (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH0_Pos) /*!< GPDMA0 SGLREQSRCREG: WE_CH0 Mask */
\r
3715 #define GPDMA0_SGLREQSRCREG_WE_CH1_Pos 9 /*!< GPDMA0 SGLREQSRCREG: WE_CH1 Position */
\r
3716 #define GPDMA0_SGLREQSRCREG_WE_CH1_Msk (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH1_Pos) /*!< GPDMA0 SGLREQSRCREG: WE_CH1 Mask */
\r
3717 #define GPDMA0_SGLREQSRCREG_WE_CH2_Pos 10 /*!< GPDMA0 SGLREQSRCREG: WE_CH2 Position */
\r
3718 #define GPDMA0_SGLREQSRCREG_WE_CH2_Msk (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH2_Pos) /*!< GPDMA0 SGLREQSRCREG: WE_CH2 Mask */
\r
3719 #define GPDMA0_SGLREQSRCREG_WE_CH3_Pos 11 /*!< GPDMA0 SGLREQSRCREG: WE_CH3 Position */
\r
3720 #define GPDMA0_SGLREQSRCREG_WE_CH3_Msk (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH3_Pos) /*!< GPDMA0 SGLREQSRCREG: WE_CH3 Mask */
\r
3721 #define GPDMA0_SGLREQSRCREG_WE_CH4_Pos 12 /*!< GPDMA0 SGLREQSRCREG: WE_CH4 Position */
\r
3722 #define GPDMA0_SGLREQSRCREG_WE_CH4_Msk (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH4_Pos) /*!< GPDMA0 SGLREQSRCREG: WE_CH4 Mask */
\r
3723 #define GPDMA0_SGLREQSRCREG_WE_CH5_Pos 13 /*!< GPDMA0 SGLREQSRCREG: WE_CH5 Position */
\r
3724 #define GPDMA0_SGLREQSRCREG_WE_CH5_Msk (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH5_Pos) /*!< GPDMA0 SGLREQSRCREG: WE_CH5 Mask */
\r
3725 #define GPDMA0_SGLREQSRCREG_WE_CH6_Pos 14 /*!< GPDMA0 SGLREQSRCREG: WE_CH6 Position */
\r
3726 #define GPDMA0_SGLREQSRCREG_WE_CH6_Msk (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH6_Pos) /*!< GPDMA0 SGLREQSRCREG: WE_CH6 Mask */
\r
3727 #define GPDMA0_SGLREQSRCREG_WE_CH7_Pos 15 /*!< GPDMA0 SGLREQSRCREG: WE_CH7 Position */
\r
3728 #define GPDMA0_SGLREQSRCREG_WE_CH7_Msk (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH7_Pos) /*!< GPDMA0 SGLREQSRCREG: WE_CH7 Mask */
\r
3730 /* ----------------------------- GPDMA0_SGLREQDSTREG ---------------------------- */
\r
3731 #define GPDMA0_SGLREQDSTREG_CH0_Pos 0 /*!< GPDMA0 SGLREQDSTREG: CH0 Position */
\r
3732 #define GPDMA0_SGLREQDSTREG_CH0_Msk (0x01UL << GPDMA0_SGLREQDSTREG_CH0_Pos) /*!< GPDMA0 SGLREQDSTREG: CH0 Mask */
\r
3733 #define GPDMA0_SGLREQDSTREG_CH1_Pos 1 /*!< GPDMA0 SGLREQDSTREG: CH1 Position */
\r
3734 #define GPDMA0_SGLREQDSTREG_CH1_Msk (0x01UL << GPDMA0_SGLREQDSTREG_CH1_Pos) /*!< GPDMA0 SGLREQDSTREG: CH1 Mask */
\r
3735 #define GPDMA0_SGLREQDSTREG_CH2_Pos 2 /*!< GPDMA0 SGLREQDSTREG: CH2 Position */
\r
3736 #define GPDMA0_SGLREQDSTREG_CH2_Msk (0x01UL << GPDMA0_SGLREQDSTREG_CH2_Pos) /*!< GPDMA0 SGLREQDSTREG: CH2 Mask */
\r
3737 #define GPDMA0_SGLREQDSTREG_CH3_Pos 3 /*!< GPDMA0 SGLREQDSTREG: CH3 Position */
\r
3738 #define GPDMA0_SGLREQDSTREG_CH3_Msk (0x01UL << GPDMA0_SGLREQDSTREG_CH3_Pos) /*!< GPDMA0 SGLREQDSTREG: CH3 Mask */
\r
3739 #define GPDMA0_SGLREQDSTREG_CH4_Pos 4 /*!< GPDMA0 SGLREQDSTREG: CH4 Position */
\r
3740 #define GPDMA0_SGLREQDSTREG_CH4_Msk (0x01UL << GPDMA0_SGLREQDSTREG_CH4_Pos) /*!< GPDMA0 SGLREQDSTREG: CH4 Mask */
\r
3741 #define GPDMA0_SGLREQDSTREG_CH5_Pos 5 /*!< GPDMA0 SGLREQDSTREG: CH5 Position */
\r
3742 #define GPDMA0_SGLREQDSTREG_CH5_Msk (0x01UL << GPDMA0_SGLREQDSTREG_CH5_Pos) /*!< GPDMA0 SGLREQDSTREG: CH5 Mask */
\r
3743 #define GPDMA0_SGLREQDSTREG_CH6_Pos 6 /*!< GPDMA0 SGLREQDSTREG: CH6 Position */
\r
3744 #define GPDMA0_SGLREQDSTREG_CH6_Msk (0x01UL << GPDMA0_SGLREQDSTREG_CH6_Pos) /*!< GPDMA0 SGLREQDSTREG: CH6 Mask */
\r
3745 #define GPDMA0_SGLREQDSTREG_CH7_Pos 7 /*!< GPDMA0 SGLREQDSTREG: CH7 Position */
\r
3746 #define GPDMA0_SGLREQDSTREG_CH7_Msk (0x01UL << GPDMA0_SGLREQDSTREG_CH7_Pos) /*!< GPDMA0 SGLREQDSTREG: CH7 Mask */
\r
3747 #define GPDMA0_SGLREQDSTREG_WE_CH0_Pos 8 /*!< GPDMA0 SGLREQDSTREG: WE_CH0 Position */
\r
3748 #define GPDMA0_SGLREQDSTREG_WE_CH0_Msk (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH0_Pos) /*!< GPDMA0 SGLREQDSTREG: WE_CH0 Mask */
\r
3749 #define GPDMA0_SGLREQDSTREG_WE_CH1_Pos 9 /*!< GPDMA0 SGLREQDSTREG: WE_CH1 Position */
\r
3750 #define GPDMA0_SGLREQDSTREG_WE_CH1_Msk (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH1_Pos) /*!< GPDMA0 SGLREQDSTREG: WE_CH1 Mask */
\r
3751 #define GPDMA0_SGLREQDSTREG_WE_CH2_Pos 10 /*!< GPDMA0 SGLREQDSTREG: WE_CH2 Position */
\r
3752 #define GPDMA0_SGLREQDSTREG_WE_CH2_Msk (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH2_Pos) /*!< GPDMA0 SGLREQDSTREG: WE_CH2 Mask */
\r
3753 #define GPDMA0_SGLREQDSTREG_WE_CH3_Pos 11 /*!< GPDMA0 SGLREQDSTREG: WE_CH3 Position */
\r
3754 #define GPDMA0_SGLREQDSTREG_WE_CH3_Msk (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH3_Pos) /*!< GPDMA0 SGLREQDSTREG: WE_CH3 Mask */
\r
3755 #define GPDMA0_SGLREQDSTREG_WE_CH4_Pos 12 /*!< GPDMA0 SGLREQDSTREG: WE_CH4 Position */
\r
3756 #define GPDMA0_SGLREQDSTREG_WE_CH4_Msk (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH4_Pos) /*!< GPDMA0 SGLREQDSTREG: WE_CH4 Mask */
\r
3757 #define GPDMA0_SGLREQDSTREG_WE_CH5_Pos 13 /*!< GPDMA0 SGLREQDSTREG: WE_CH5 Position */
\r
3758 #define GPDMA0_SGLREQDSTREG_WE_CH5_Msk (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH5_Pos) /*!< GPDMA0 SGLREQDSTREG: WE_CH5 Mask */
\r
3759 #define GPDMA0_SGLREQDSTREG_WE_CH6_Pos 14 /*!< GPDMA0 SGLREQDSTREG: WE_CH6 Position */
\r
3760 #define GPDMA0_SGLREQDSTREG_WE_CH6_Msk (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH6_Pos) /*!< GPDMA0 SGLREQDSTREG: WE_CH6 Mask */
\r
3761 #define GPDMA0_SGLREQDSTREG_WE_CH7_Pos 15 /*!< GPDMA0 SGLREQDSTREG: WE_CH7 Position */
\r
3762 #define GPDMA0_SGLREQDSTREG_WE_CH7_Msk (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH7_Pos) /*!< GPDMA0 SGLREQDSTREG: WE_CH7 Mask */
\r
3764 /* ------------------------------ GPDMA0_LSTSRCREG ------------------------------ */
\r
3765 #define GPDMA0_LSTSRCREG_CH0_Pos 0 /*!< GPDMA0 LSTSRCREG: CH0 Position */
\r
3766 #define GPDMA0_LSTSRCREG_CH0_Msk (0x01UL << GPDMA0_LSTSRCREG_CH0_Pos) /*!< GPDMA0 LSTSRCREG: CH0 Mask */
\r
3767 #define GPDMA0_LSTSRCREG_CH1_Pos 1 /*!< GPDMA0 LSTSRCREG: CH1 Position */
\r
3768 #define GPDMA0_LSTSRCREG_CH1_Msk (0x01UL << GPDMA0_LSTSRCREG_CH1_Pos) /*!< GPDMA0 LSTSRCREG: CH1 Mask */
\r
3769 #define GPDMA0_LSTSRCREG_CH2_Pos 2 /*!< GPDMA0 LSTSRCREG: CH2 Position */
\r
3770 #define GPDMA0_LSTSRCREG_CH2_Msk (0x01UL << GPDMA0_LSTSRCREG_CH2_Pos) /*!< GPDMA0 LSTSRCREG: CH2 Mask */
\r
3771 #define GPDMA0_LSTSRCREG_CH3_Pos 3 /*!< GPDMA0 LSTSRCREG: CH3 Position */
\r
3772 #define GPDMA0_LSTSRCREG_CH3_Msk (0x01UL << GPDMA0_LSTSRCREG_CH3_Pos) /*!< GPDMA0 LSTSRCREG: CH3 Mask */
\r
3773 #define GPDMA0_LSTSRCREG_CH4_Pos 4 /*!< GPDMA0 LSTSRCREG: CH4 Position */
\r
3774 #define GPDMA0_LSTSRCREG_CH4_Msk (0x01UL << GPDMA0_LSTSRCREG_CH4_Pos) /*!< GPDMA0 LSTSRCREG: CH4 Mask */
\r
3775 #define GPDMA0_LSTSRCREG_CH5_Pos 5 /*!< GPDMA0 LSTSRCREG: CH5 Position */
\r
3776 #define GPDMA0_LSTSRCREG_CH5_Msk (0x01UL << GPDMA0_LSTSRCREG_CH5_Pos) /*!< GPDMA0 LSTSRCREG: CH5 Mask */
\r
3777 #define GPDMA0_LSTSRCREG_CH6_Pos 6 /*!< GPDMA0 LSTSRCREG: CH6 Position */
\r
3778 #define GPDMA0_LSTSRCREG_CH6_Msk (0x01UL << GPDMA0_LSTSRCREG_CH6_Pos) /*!< GPDMA0 LSTSRCREG: CH6 Mask */
\r
3779 #define GPDMA0_LSTSRCREG_CH7_Pos 7 /*!< GPDMA0 LSTSRCREG: CH7 Position */
\r
3780 #define GPDMA0_LSTSRCREG_CH7_Msk (0x01UL << GPDMA0_LSTSRCREG_CH7_Pos) /*!< GPDMA0 LSTSRCREG: CH7 Mask */
\r
3781 #define GPDMA0_LSTSRCREG_WE_CH0_Pos 8 /*!< GPDMA0 LSTSRCREG: WE_CH0 Position */
\r
3782 #define GPDMA0_LSTSRCREG_WE_CH0_Msk (0x01UL << GPDMA0_LSTSRCREG_WE_CH0_Pos) /*!< GPDMA0 LSTSRCREG: WE_CH0 Mask */
\r
3783 #define GPDMA0_LSTSRCREG_WE_CH1_Pos 9 /*!< GPDMA0 LSTSRCREG: WE_CH1 Position */
\r
3784 #define GPDMA0_LSTSRCREG_WE_CH1_Msk (0x01UL << GPDMA0_LSTSRCREG_WE_CH1_Pos) /*!< GPDMA0 LSTSRCREG: WE_CH1 Mask */
\r
3785 #define GPDMA0_LSTSRCREG_WE_CH2_Pos 10 /*!< GPDMA0 LSTSRCREG: WE_CH2 Position */
\r
3786 #define GPDMA0_LSTSRCREG_WE_CH2_Msk (0x01UL << GPDMA0_LSTSRCREG_WE_CH2_Pos) /*!< GPDMA0 LSTSRCREG: WE_CH2 Mask */
\r
3787 #define GPDMA0_LSTSRCREG_WE_CH3_Pos 11 /*!< GPDMA0 LSTSRCREG: WE_CH3 Position */
\r
3788 #define GPDMA0_LSTSRCREG_WE_CH3_Msk (0x01UL << GPDMA0_LSTSRCREG_WE_CH3_Pos) /*!< GPDMA0 LSTSRCREG: WE_CH3 Mask */
\r
3789 #define GPDMA0_LSTSRCREG_WE_CH4_Pos 12 /*!< GPDMA0 LSTSRCREG: WE_CH4 Position */
\r
3790 #define GPDMA0_LSTSRCREG_WE_CH4_Msk (0x01UL << GPDMA0_LSTSRCREG_WE_CH4_Pos) /*!< GPDMA0 LSTSRCREG: WE_CH4 Mask */
\r
3791 #define GPDMA0_LSTSRCREG_WE_CH5_Pos 13 /*!< GPDMA0 LSTSRCREG: WE_CH5 Position */
\r
3792 #define GPDMA0_LSTSRCREG_WE_CH5_Msk (0x01UL << GPDMA0_LSTSRCREG_WE_CH5_Pos) /*!< GPDMA0 LSTSRCREG: WE_CH5 Mask */
\r
3793 #define GPDMA0_LSTSRCREG_WE_CH6_Pos 14 /*!< GPDMA0 LSTSRCREG: WE_CH6 Position */
\r
3794 #define GPDMA0_LSTSRCREG_WE_CH6_Msk (0x01UL << GPDMA0_LSTSRCREG_WE_CH6_Pos) /*!< GPDMA0 LSTSRCREG: WE_CH6 Mask */
\r
3795 #define GPDMA0_LSTSRCREG_WE_CH7_Pos 15 /*!< GPDMA0 LSTSRCREG: WE_CH7 Position */
\r
3796 #define GPDMA0_LSTSRCREG_WE_CH7_Msk (0x01UL << GPDMA0_LSTSRCREG_WE_CH7_Pos) /*!< GPDMA0 LSTSRCREG: WE_CH7 Mask */
\r
3798 /* ------------------------------ GPDMA0_LSTDSTREG ------------------------------ */
\r
3799 #define GPDMA0_LSTDSTREG_CH0_Pos 0 /*!< GPDMA0 LSTDSTREG: CH0 Position */
\r
3800 #define GPDMA0_LSTDSTREG_CH0_Msk (0x01UL << GPDMA0_LSTDSTREG_CH0_Pos) /*!< GPDMA0 LSTDSTREG: CH0 Mask */
\r
3801 #define GPDMA0_LSTDSTREG_CH1_Pos 1 /*!< GPDMA0 LSTDSTREG: CH1 Position */
\r
3802 #define GPDMA0_LSTDSTREG_CH1_Msk (0x01UL << GPDMA0_LSTDSTREG_CH1_Pos) /*!< GPDMA0 LSTDSTREG: CH1 Mask */
\r
3803 #define GPDMA0_LSTDSTREG_CH2_Pos 2 /*!< GPDMA0 LSTDSTREG: CH2 Position */
\r
3804 #define GPDMA0_LSTDSTREG_CH2_Msk (0x01UL << GPDMA0_LSTDSTREG_CH2_Pos) /*!< GPDMA0 LSTDSTREG: CH2 Mask */
\r
3805 #define GPDMA0_LSTDSTREG_CH3_Pos 3 /*!< GPDMA0 LSTDSTREG: CH3 Position */
\r
3806 #define GPDMA0_LSTDSTREG_CH3_Msk (0x01UL << GPDMA0_LSTDSTREG_CH3_Pos) /*!< GPDMA0 LSTDSTREG: CH3 Mask */
\r
3807 #define GPDMA0_LSTDSTREG_CH4_Pos 4 /*!< GPDMA0 LSTDSTREG: CH4 Position */
\r
3808 #define GPDMA0_LSTDSTREG_CH4_Msk (0x01UL << GPDMA0_LSTDSTREG_CH4_Pos) /*!< GPDMA0 LSTDSTREG: CH4 Mask */
\r
3809 #define GPDMA0_LSTDSTREG_CH5_Pos 5 /*!< GPDMA0 LSTDSTREG: CH5 Position */
\r
3810 #define GPDMA0_LSTDSTREG_CH5_Msk (0x01UL << GPDMA0_LSTDSTREG_CH5_Pos) /*!< GPDMA0 LSTDSTREG: CH5 Mask */
\r
3811 #define GPDMA0_LSTDSTREG_CH6_Pos 6 /*!< GPDMA0 LSTDSTREG: CH6 Position */
\r
3812 #define GPDMA0_LSTDSTREG_CH6_Msk (0x01UL << GPDMA0_LSTDSTREG_CH6_Pos) /*!< GPDMA0 LSTDSTREG: CH6 Mask */
\r
3813 #define GPDMA0_LSTDSTREG_CH7_Pos 7 /*!< GPDMA0 LSTDSTREG: CH7 Position */
\r
3814 #define GPDMA0_LSTDSTREG_CH7_Msk (0x01UL << GPDMA0_LSTDSTREG_CH7_Pos) /*!< GPDMA0 LSTDSTREG: CH7 Mask */
\r
3815 #define GPDMA0_LSTDSTREG_WE_CH0_Pos 8 /*!< GPDMA0 LSTDSTREG: WE_CH0 Position */
\r
3816 #define GPDMA0_LSTDSTREG_WE_CH0_Msk (0x01UL << GPDMA0_LSTDSTREG_WE_CH0_Pos) /*!< GPDMA0 LSTDSTREG: WE_CH0 Mask */
\r
3817 #define GPDMA0_LSTDSTREG_WE_CH1_Pos 9 /*!< GPDMA0 LSTDSTREG: WE_CH1 Position */
\r
3818 #define GPDMA0_LSTDSTREG_WE_CH1_Msk (0x01UL << GPDMA0_LSTDSTREG_WE_CH1_Pos) /*!< GPDMA0 LSTDSTREG: WE_CH1 Mask */
\r
3819 #define GPDMA0_LSTDSTREG_WE_CH2_Pos 10 /*!< GPDMA0 LSTDSTREG: WE_CH2 Position */
\r
3820 #define GPDMA0_LSTDSTREG_WE_CH2_Msk (0x01UL << GPDMA0_LSTDSTREG_WE_CH2_Pos) /*!< GPDMA0 LSTDSTREG: WE_CH2 Mask */
\r
3821 #define GPDMA0_LSTDSTREG_WE_CH3_Pos 11 /*!< GPDMA0 LSTDSTREG: WE_CH3 Position */
\r
3822 #define GPDMA0_LSTDSTREG_WE_CH3_Msk (0x01UL << GPDMA0_LSTDSTREG_WE_CH3_Pos) /*!< GPDMA0 LSTDSTREG: WE_CH3 Mask */
\r
3823 #define GPDMA0_LSTDSTREG_WE_CH4_Pos 12 /*!< GPDMA0 LSTDSTREG: WE_CH4 Position */
\r
3824 #define GPDMA0_LSTDSTREG_WE_CH4_Msk (0x01UL << GPDMA0_LSTDSTREG_WE_CH4_Pos) /*!< GPDMA0 LSTDSTREG: WE_CH4 Mask */
\r
3825 #define GPDMA0_LSTDSTREG_WE_CH5_Pos 13 /*!< GPDMA0 LSTDSTREG: WE_CH5 Position */
\r
3826 #define GPDMA0_LSTDSTREG_WE_CH5_Msk (0x01UL << GPDMA0_LSTDSTREG_WE_CH5_Pos) /*!< GPDMA0 LSTDSTREG: WE_CH5 Mask */
\r
3827 #define GPDMA0_LSTDSTREG_WE_CH6_Pos 14 /*!< GPDMA0 LSTDSTREG: WE_CH6 Position */
\r
3828 #define GPDMA0_LSTDSTREG_WE_CH6_Msk (0x01UL << GPDMA0_LSTDSTREG_WE_CH6_Pos) /*!< GPDMA0 LSTDSTREG: WE_CH6 Mask */
\r
3829 #define GPDMA0_LSTDSTREG_WE_CH7_Pos 15 /*!< GPDMA0 LSTDSTREG: WE_CH7 Position */
\r
3830 #define GPDMA0_LSTDSTREG_WE_CH7_Msk (0x01UL << GPDMA0_LSTDSTREG_WE_CH7_Pos) /*!< GPDMA0 LSTDSTREG: WE_CH7 Mask */
\r
3832 /* ------------------------------ GPDMA0_DMACFGREG ------------------------------ */
\r
3833 #define GPDMA0_DMACFGREG_DMA_EN_Pos 0 /*!< GPDMA0 DMACFGREG: DMA_EN Position */
\r
3834 #define GPDMA0_DMACFGREG_DMA_EN_Msk (0x01UL << GPDMA0_DMACFGREG_DMA_EN_Pos) /*!< GPDMA0 DMACFGREG: DMA_EN Mask */
\r
3836 /* ------------------------------- GPDMA0_CHENREG ------------------------------- */
\r
3837 #define GPDMA0_CHENREG_CH_Pos 0 /*!< GPDMA0 CHENREG: CH Position */
\r
3838 #define GPDMA0_CHENREG_CH_Msk (0x000000ffUL << GPDMA0_CHENREG_CH_Pos) /*!< GPDMA0 CHENREG: CH Mask */
\r
3839 #define GPDMA0_CHENREG_WE_CH_Pos 8 /*!< GPDMA0 CHENREG: WE_CH Position */
\r
3840 #define GPDMA0_CHENREG_WE_CH_Msk (0x000000ffUL << GPDMA0_CHENREG_WE_CH_Pos) /*!< GPDMA0 CHENREG: WE_CH Mask */
\r
3842 /* ---------------------------------- GPDMA0_ID --------------------------------- */
\r
3843 #define GPDMA0_ID_VALUE_Pos 0 /*!< GPDMA0 ID: VALUE Position */
\r
3844 #define GPDMA0_ID_VALUE_Msk (0xffffffffUL << GPDMA0_ID_VALUE_Pos) /*!< GPDMA0 ID: VALUE Mask */
\r
3846 /* --------------------------------- GPDMA0_TYPE -------------------------------- */
\r
3847 #define GPDMA0_TYPE_VALUE_Pos 0 /*!< GPDMA0 TYPE: VALUE Position */
\r
3848 #define GPDMA0_TYPE_VALUE_Msk (0xffffffffUL << GPDMA0_TYPE_VALUE_Pos) /*!< GPDMA0 TYPE: VALUE Mask */
\r
3850 /* ------------------------------- GPDMA0_VERSION ------------------------------- */
\r
3851 #define GPDMA0_VERSION_VALUE_Pos 0 /*!< GPDMA0 VERSION: VALUE Position */
\r
3852 #define GPDMA0_VERSION_VALUE_Msk (0xffffffffUL << GPDMA0_VERSION_VALUE_Pos) /*!< GPDMA0 VERSION: VALUE Mask */
\r
3855 /* ================================================================================ */
\r
3856 /* ================ Group 'GPDMA0_CH0_1' Position & Mask ================ */
\r
3857 /* ================================================================================ */
\r
3860 /* ------------------------------ GPDMA0_CH_SAR ------------------------------ */
\r
3861 #define GPDMA0_CH_SAR_SAR_Pos 0 /*!< GPDMA0_CH0_1 SAR: SAR Position */
\r
3862 #define GPDMA0_CH_SAR_SAR_Msk (0xffffffffUL << GPDMA0_CH_SAR_SAR_Pos) /*!< GPDMA0_CH0_1 SAR: SAR Mask */
\r
3864 /* ------------------------------ GPDMA0_CH_DAR ------------------------------ */
\r
3865 #define GPDMA0_CH_DAR_DAR_Pos 0 /*!< GPDMA0_CH0_1 DAR: DAR Position */
\r
3866 #define GPDMA0_CH_DAR_DAR_Msk (0xffffffffUL << GPDMA0_CH_DAR_DAR_Pos) /*!< GPDMA0_CH0_1 DAR: DAR Mask */
\r
3868 /* ------------------------------ GPDMA0_CH_LLP ------------------------------ */
\r
3869 #define GPDMA0_CH_LLP_LOC_Pos 2 /*!< GPDMA0_CH0_1 LLP: LOC Position */
\r
3870 #define GPDMA0_CH_LLP_LOC_Msk (0x3fffffffUL << GPDMA0_CH_LLP_LOC_Pos) /*!< GPDMA0_CH0_1 LLP: LOC Mask */
\r
3872 /* ------------------------------ GPDMA0_CH_CTLL ----------------------------- */
\r
3873 #define GPDMA0_CH_CTLL_INT_EN_Pos 0 /*!< GPDMA0_CH0_1 CTLL: INT_EN Position */
\r
3874 #define GPDMA0_CH_CTLL_INT_EN_Msk (0x01UL << GPDMA0_CH_CTLL_INT_EN_Pos) /*!< GPDMA0_CH0_1 CTLL: INT_EN Mask */
\r
3875 #define GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos 1 /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH Position */
\r
3876 #define GPDMA0_CH_CTLL_DST_TR_WIDTH_Msk (0x07UL << GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos) /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH Mask */
\r
3877 #define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos 4 /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH Position */
\r
3878 #define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Msk (0x07UL << GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos) /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH Mask */
\r
3879 #define GPDMA0_CH_CTLL_DINC_Pos 7 /*!< GPDMA0_CH0_1 CTLL: DINC Position */
\r
3880 #define GPDMA0_CH_CTLL_DINC_Msk (0x03UL << GPDMA0_CH_CTLL_DINC_Pos) /*!< GPDMA0_CH0_1 CTLL: DINC Mask */
\r
3881 #define GPDMA0_CH_CTLL_SINC_Pos 9 /*!< GPDMA0_CH0_1 CTLL: SINC Position */
\r
3882 #define GPDMA0_CH_CTLL_SINC_Msk (0x03UL << GPDMA0_CH_CTLL_SINC_Pos) /*!< GPDMA0_CH0_1 CTLL: SINC Mask */
\r
3883 #define GPDMA0_CH_CTLL_DEST_MSIZE_Pos 11 /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE Position */
\r
3884 #define GPDMA0_CH_CTLL_DEST_MSIZE_Msk (0x07UL << GPDMA0_CH_CTLL_DEST_MSIZE_Pos) /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE Mask */
\r
3885 #define GPDMA0_CH_CTLL_SRC_MSIZE_Pos 14 /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE Position */
\r
3886 #define GPDMA0_CH_CTLL_SRC_MSIZE_Msk (0x07UL << GPDMA0_CH_CTLL_SRC_MSIZE_Pos) /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE Mask */
\r
3887 #define GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos 17 /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN Position */
\r
3888 #define GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk (0x01UL << GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos) /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN Mask */
\r
3889 #define GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos 18 /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN Position */
\r
3890 #define GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk (0x01UL << GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos) /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN Mask */
\r
3891 #define GPDMA0_CH_CTLL_TT_FC_Pos 20 /*!< GPDMA0_CH0_1 CTLL: TT_FC Position */
\r
3892 #define GPDMA0_CH_CTLL_TT_FC_Msk (0x07UL << GPDMA0_CH_CTLL_TT_FC_Pos) /*!< GPDMA0_CH0_1 CTLL: TT_FC Mask */
\r
3893 #define GPDMA0_CH_CTLL_LLP_DST_EN_Pos 27 /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN Position */
\r
3894 #define GPDMA0_CH_CTLL_LLP_DST_EN_Msk (0x01UL << GPDMA0_CH_CTLL_LLP_DST_EN_Pos) /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN Mask */
\r
3895 #define GPDMA0_CH_CTLL_LLP_SRC_EN_Pos 28 /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN Position */
\r
3896 #define GPDMA0_CH_CTLL_LLP_SRC_EN_Msk (0x01UL << GPDMA0_CH_CTLL_LLP_SRC_EN_Pos) /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN Mask */
\r
3898 /* ------------------------------ GPDMA0_CH_CTLH ----------------------------- */
\r
3899 #define GPDMA0_CH_CTLH_BLOCK_TS_Pos 0 /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS Position */
\r
3900 #define GPDMA0_CH_CTLH_BLOCK_TS_Msk (0x00000fffUL << GPDMA0_CH_CTLH_BLOCK_TS_Pos) /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS Mask */
\r
3901 #define GPDMA0_CH_CTLH_DONE_Pos 12 /*!< GPDMA0_CH0_1 CTLH: DONE Position */
\r
3902 #define GPDMA0_CH_CTLH_DONE_Msk (0x01UL << GPDMA0_CH_CTLH_DONE_Pos) /*!< GPDMA0_CH0_1 CTLH: DONE Mask */
\r
3904 /* ----------------------------- GPDMA0_CH_SSTAT ----------------------------- */
\r
3905 #define GPDMA0_CH_SSTAT_SSTAT_Pos 0 /*!< GPDMA0_CH0_1 SSTAT: SSTAT Position */
\r
3906 #define GPDMA0_CH_SSTAT_SSTAT_Msk (0xffffffffUL << GPDMA0_CH_SSTAT_SSTAT_Pos) /*!< GPDMA0_CH0_1 SSTAT: SSTAT Mask */
\r
3908 /* ----------------------------- GPDMA0_CH_DSTAT ----------------------------- */
\r
3909 #define GPDMA0_CH_DSTAT_DSTAT_Pos 0 /*!< GPDMA0_CH0_1 DSTAT: DSTAT Position */
\r
3910 #define GPDMA0_CH_DSTAT_DSTAT_Msk (0xffffffffUL << GPDMA0_CH_DSTAT_DSTAT_Pos) /*!< GPDMA0_CH0_1 DSTAT: DSTAT Mask */
\r
3912 /* ---------------------------- GPDMA0_CH_SSTATAR ---------------------------- */
\r
3913 #define GPDMA0_CH_SSTATAR_SSTATAR_Pos 0 /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR Position */
\r
3914 #define GPDMA0_CH_SSTATAR_SSTATAR_Msk (0xffffffffUL << GPDMA0_CH_SSTATAR_SSTATAR_Pos) /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR Mask */
\r
3916 /* ---------------------------- GPDMA0_CH_DSTATAR ---------------------------- */
\r
3917 #define GPDMA0_CH_DSTATAR_DSTATAR_Pos 0 /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR Position */
\r
3918 #define GPDMA0_CH_DSTATAR_DSTATAR_Msk (0xffffffffUL << GPDMA0_CH_DSTATAR_DSTATAR_Pos) /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR Mask */
\r
3920 /* ------------------------------ GPDMA0_CH_CFGL ----------------------------- */
\r
3921 #define GPDMA0_CH_CFGL_CH_PRIOR_Pos 5 /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR Position */
\r
3922 #define GPDMA0_CH_CFGL_CH_PRIOR_Msk (0x07UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos) /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR Mask */
\r
3923 #define GPDMA0_CH_CFGL_CH_SUSP_Pos 8 /*!< GPDMA0_CH0_1 CFGL: CH_SUSP Position */
\r
3924 #define GPDMA0_CH_CFGL_CH_SUSP_Msk (0x01UL << GPDMA0_CH_CFGL_CH_SUSP_Pos) /*!< GPDMA0_CH0_1 CFGL: CH_SUSP Mask */
\r
3925 #define GPDMA0_CH_CFGL_FIFO_EMPTY_Pos 9 /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY Position */
\r
3926 #define GPDMA0_CH_CFGL_FIFO_EMPTY_Msk (0x01UL << GPDMA0_CH_CFGL_FIFO_EMPTY_Pos) /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY Mask */
\r
3927 #define GPDMA0_CH_CFGL_HS_SEL_DST_Pos 10 /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST Position */
\r
3928 #define GPDMA0_CH_CFGL_HS_SEL_DST_Msk (0x01UL << GPDMA0_CH_CFGL_HS_SEL_DST_Pos) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST Mask */
\r
3929 #define GPDMA0_CH_CFGL_HS_SEL_SRC_Pos 11 /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC Position */
\r
3930 #define GPDMA0_CH_CFGL_HS_SEL_SRC_Msk (0x01UL << GPDMA0_CH_CFGL_HS_SEL_SRC_Pos) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC Mask */
\r
3931 #define GPDMA0_CH_CFGL_LOCK_CH_L_Pos 12 /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L Position */
\r
3932 #define GPDMA0_CH_CFGL_LOCK_CH_L_Msk (0x03UL << GPDMA0_CH_CFGL_LOCK_CH_L_Pos) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L Mask */
\r
3933 #define GPDMA0_CH_CFGL_LOCK_B_L_Pos 14 /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L Position */
\r
3934 #define GPDMA0_CH_CFGL_LOCK_B_L_Msk (0x03UL << GPDMA0_CH_CFGL_LOCK_B_L_Pos) /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L Mask */
\r
3935 #define GPDMA0_CH_CFGL_LOCK_CH_Pos 16 /*!< GPDMA0_CH0_1 CFGL: LOCK_CH Position */
\r
3936 #define GPDMA0_CH_CFGL_LOCK_CH_Msk (0x01UL << GPDMA0_CH_CFGL_LOCK_CH_Pos) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH Mask */
\r
3937 #define GPDMA0_CH_CFGL_LOCK_B_Pos 17 /*!< GPDMA0_CH0_1 CFGL: LOCK_B Position */
\r
3938 #define GPDMA0_CH_CFGL_LOCK_B_Msk (0x01UL << GPDMA0_CH_CFGL_LOCK_B_Pos) /*!< GPDMA0_CH0_1 CFGL: LOCK_B Mask */
\r
3939 #define GPDMA0_CH_CFGL_DST_HS_POL_Pos 18 /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL Position */
\r
3940 #define GPDMA0_CH_CFGL_DST_HS_POL_Msk (0x01UL << GPDMA0_CH_CFGL_DST_HS_POL_Pos) /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL Mask */
\r
3941 #define GPDMA0_CH_CFGL_SRC_HS_POL_Pos 19 /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL Position */
\r
3942 #define GPDMA0_CH_CFGL_SRC_HS_POL_Msk (0x01UL << GPDMA0_CH_CFGL_SRC_HS_POL_Pos) /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL Mask */
\r
3943 #define GPDMA0_CH_CFGL_MAX_ABRST_Pos 20 /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST Position */
\r
3944 #define GPDMA0_CH_CFGL_MAX_ABRST_Msk (0x000003ffUL << GPDMA0_CH_CFGL_MAX_ABRST_Pos) /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST Mask */
\r
3945 #define GPDMA0_CH_CFGL_RELOAD_SRC_Pos 30 /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC Position */
\r
3946 #define GPDMA0_CH_CFGL_RELOAD_SRC_Msk (0x01UL << GPDMA0_CH_CFGL_RELOAD_SRC_Pos) /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC Mask */
\r
3947 #define GPDMA0_CH_CFGL_RELOAD_DST_Pos 31 /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST Position */
\r
3948 #define GPDMA0_CH_CFGL_RELOAD_DST_Msk (0x01UL << GPDMA0_CH_CFGL_RELOAD_DST_Pos) /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST Mask */
\r
3950 /* ------------------------------ GPDMA0_CH_CFGH ----------------------------- */
\r
3951 #define GPDMA0_CH_CFGH_FCMODE_Pos 0 /*!< GPDMA0_CH0_1 CFGH: FCMODE Position */
\r
3952 #define GPDMA0_CH_CFGH_FCMODE_Msk (0x01UL << GPDMA0_CH_CFGH_FCMODE_Pos) /*!< GPDMA0_CH0_1 CFGH: FCMODE Mask */
\r
3953 #define GPDMA0_CH_CFGH_FIFO_MODE_Pos 1 /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE Position */
\r
3954 #define GPDMA0_CH_CFGH_FIFO_MODE_Msk (0x01UL << GPDMA0_CH_CFGH_FIFO_MODE_Pos) /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE Mask */
\r
3955 #define GPDMA0_CH_CFGH_PROTCTL_Pos 2 /*!< GPDMA0_CH0_1 CFGH: PROTCTL Position */
\r
3956 #define GPDMA0_CH_CFGH_PROTCTL_Msk (0x07UL << GPDMA0_CH_CFGH_PROTCTL_Pos) /*!< GPDMA0_CH0_1 CFGH: PROTCTL Mask */
\r
3957 #define GPDMA0_CH_CFGH_DS_UPD_EN_Pos 5 /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN Position */
\r
3958 #define GPDMA0_CH_CFGH_DS_UPD_EN_Msk (0x01UL << GPDMA0_CH_CFGH_DS_UPD_EN_Pos) /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN Mask */
\r
3959 #define GPDMA0_CH_CFGH_SS_UPD_EN_Pos 6 /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN Position */
\r
3960 #define GPDMA0_CH_CFGH_SS_UPD_EN_Msk (0x01UL << GPDMA0_CH_CFGH_SS_UPD_EN_Pos) /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN Mask */
\r
3961 #define GPDMA0_CH_CFGH_SRC_PER_Pos 7 /*!< GPDMA0_CH0_1 CFGH: SRC_PER Position */
\r
3962 #define GPDMA0_CH_CFGH_SRC_PER_Msk (0x0fUL << GPDMA0_CH_CFGH_SRC_PER_Pos) /*!< GPDMA0_CH0_1 CFGH: SRC_PER Mask */
\r
3963 #define GPDMA0_CH_CFGH_DEST_PER_Pos 11 /*!< GPDMA0_CH0_1 CFGH: DEST_PER Position */
\r
3964 #define GPDMA0_CH_CFGH_DEST_PER_Msk (0x0fUL << GPDMA0_CH_CFGH_DEST_PER_Pos) /*!< GPDMA0_CH0_1 CFGH: DEST_PER Mask */
\r
3966 /* ------------------------------ GPDMA0_CH_SGR ------------------------------ */
\r
3967 #define GPDMA0_CH_SGR_SGI_Pos 0 /*!< GPDMA0_CH0_1 SGR: SGI Position */
\r
3968 #define GPDMA0_CH_SGR_SGI_Msk (0x000fffffUL << GPDMA0_CH_SGR_SGI_Pos) /*!< GPDMA0_CH0_1 SGR: SGI Mask */
\r
3969 #define GPDMA0_CH_SGR_SGC_Pos 20 /*!< GPDMA0_CH0_1 SGR: SGC Position */
\r
3970 #define GPDMA0_CH_SGR_SGC_Msk (0x00000fffUL << GPDMA0_CH_SGR_SGC_Pos) /*!< GPDMA0_CH0_1 SGR: SGC Mask */
\r
3972 /* ------------------------------ GPDMA0_CH_DSR ------------------------------ */
\r
3973 #define GPDMA0_CH_DSR_DSI_Pos 0 /*!< GPDMA0_CH0_1 DSR: DSI Position */
\r
3974 #define GPDMA0_CH_DSR_DSI_Msk (0x000fffffUL << GPDMA0_CH_DSR_DSI_Pos) /*!< GPDMA0_CH0_1 DSR: DSI Mask */
\r
3975 #define GPDMA0_CH_DSR_DSC_Pos 20 /*!< GPDMA0_CH0_1 DSR: DSC Position */
\r
3976 #define GPDMA0_CH_DSR_DSC_Msk (0x00000fffUL << GPDMA0_CH_DSR_DSC_Pos) /*!< GPDMA0_CH0_1 DSR: DSC Mask */
\r
3979 /* ================================================================================ */
\r
3980 /* ================ struct 'FCE' Position & Mask ================ */
\r
3981 /* ================================================================================ */
\r
3984 /* ----------------------------------- FCE_CLC ---------------------------------- */
\r
3985 #define FCE_CLC_DISR_Pos 0 /*!< FCE CLC: DISR Position */
\r
3986 #define FCE_CLC_DISR_Msk (0x01UL << FCE_CLC_DISR_Pos) /*!< FCE CLC: DISR Mask */
\r
3987 #define FCE_CLC_DISS_Pos 1 /*!< FCE CLC: DISS Position */
\r
3988 #define FCE_CLC_DISS_Msk (0x01UL << FCE_CLC_DISS_Pos) /*!< FCE CLC: DISS Mask */
\r
3990 /* ----------------------------------- FCE_ID ----------------------------------- */
\r
3991 #define FCE_ID_MOD_REV_Pos 0 /*!< FCE ID: MOD_REV Position */
\r
3992 #define FCE_ID_MOD_REV_Msk (0x000000ffUL << FCE_ID_MOD_REV_Pos) /*!< FCE ID: MOD_REV Mask */
\r
3993 #define FCE_ID_MOD_TYPE_Pos 8 /*!< FCE ID: MOD_TYPE Position */
\r
3994 #define FCE_ID_MOD_TYPE_Msk (0x000000ffUL << FCE_ID_MOD_TYPE_Pos) /*!< FCE ID: MOD_TYPE Mask */
\r
3995 #define FCE_ID_MOD_NUMBER_Pos 16 /*!< FCE ID: MOD_NUMBER Position */
\r
3996 #define FCE_ID_MOD_NUMBER_Msk (0x0000ffffUL << FCE_ID_MOD_NUMBER_Pos) /*!< FCE ID: MOD_NUMBER Mask */
\r
3999 /* ================================================================================ */
\r
4000 /* ================ Group 'FCE_KE' Position & Mask ================ */
\r
4001 /* ================================================================================ */
\r
4004 /* ---------------------------------- FCE_KE_IR --------------------------------- */
\r
4005 #define FCE_KE_IR_IR_Pos 0 /*!< FCE_KE IR: IR Position */
\r
4006 #define FCE_KE_IR_IR_Msk (0xffffffffUL << FCE_KE_IR_IR_Pos) /*!< FCE_KE IR: IR Mask */
\r
4008 /* --------------------------------- FCE_KE_RES --------------------------------- */
\r
4009 #define FCE_KE_RES_RES_Pos 0 /*!< FCE_KE RES: RES Position */
\r
4010 #define FCE_KE_RES_RES_Msk (0xffffffffUL << FCE_KE_RES_RES_Pos) /*!< FCE_KE RES: RES Mask */
\r
4012 /* --------------------------------- FCE_KE_CFG --------------------------------- */
\r
4013 #define FCE_KE_CFG_CMI_Pos 0 /*!< FCE_KE CFG: CMI Position */
\r
4014 #define FCE_KE_CFG_CMI_Msk (0x01UL << FCE_KE_CFG_CMI_Pos) /*!< FCE_KE CFG: CMI Mask */
\r
4015 #define FCE_KE_CFG_CEI_Pos 1 /*!< FCE_KE CFG: CEI Position */
\r
4016 #define FCE_KE_CFG_CEI_Msk (0x01UL << FCE_KE_CFG_CEI_Pos) /*!< FCE_KE CFG: CEI Mask */
\r
4017 #define FCE_KE_CFG_LEI_Pos 2 /*!< FCE_KE CFG: LEI Position */
\r
4018 #define FCE_KE_CFG_LEI_Msk (0x01UL << FCE_KE_CFG_LEI_Pos) /*!< FCE_KE CFG: LEI Mask */
\r
4019 #define FCE_KE_CFG_BEI_Pos 3 /*!< FCE_KE CFG: BEI Position */
\r
4020 #define FCE_KE_CFG_BEI_Msk (0x01UL << FCE_KE_CFG_BEI_Pos) /*!< FCE_KE CFG: BEI Mask */
\r
4021 #define FCE_KE_CFG_CCE_Pos 4 /*!< FCE_KE CFG: CCE Position */
\r
4022 #define FCE_KE_CFG_CCE_Msk (0x01UL << FCE_KE_CFG_CCE_Pos) /*!< FCE_KE CFG: CCE Mask */
\r
4023 #define FCE_KE_CFG_ALR_Pos 5 /*!< FCE_KE CFG: ALR Position */
\r
4024 #define FCE_KE_CFG_ALR_Msk (0x01UL << FCE_KE_CFG_ALR_Pos) /*!< FCE_KE CFG: ALR Mask */
\r
4025 #define FCE_KE_CFG_REFIN_Pos 8 /*!< FCE_KE CFG: REFIN Position */
\r
4026 #define FCE_KE_CFG_REFIN_Msk (0x01UL << FCE_KE_CFG_REFIN_Pos) /*!< FCE_KE CFG: REFIN Mask */
\r
4027 #define FCE_KE_CFG_REFOUT_Pos 9 /*!< FCE_KE CFG: REFOUT Position */
\r
4028 #define FCE_KE_CFG_REFOUT_Msk (0x01UL << FCE_KE_CFG_REFOUT_Pos) /*!< FCE_KE CFG: REFOUT Mask */
\r
4029 #define FCE_KE_CFG_XSEL_Pos 10 /*!< FCE_KE CFG: XSEL Position */
\r
4030 #define FCE_KE_CFG_XSEL_Msk (0x01UL << FCE_KE_CFG_XSEL_Pos) /*!< FCE_KE CFG: XSEL Mask */
\r
4032 /* --------------------------------- FCE_KE_STS --------------------------------- */
\r
4033 #define FCE_KE_STS_CMF_Pos 0 /*!< FCE_KE STS: CMF Position */
\r
4034 #define FCE_KE_STS_CMF_Msk (0x01UL << FCE_KE_STS_CMF_Pos) /*!< FCE_KE STS: CMF Mask */
\r
4035 #define FCE_KE_STS_CEF_Pos 1 /*!< FCE_KE STS: CEF Position */
\r
4036 #define FCE_KE_STS_CEF_Msk (0x01UL << FCE_KE_STS_CEF_Pos) /*!< FCE_KE STS: CEF Mask */
\r
4037 #define FCE_KE_STS_LEF_Pos 2 /*!< FCE_KE STS: LEF Position */
\r
4038 #define FCE_KE_STS_LEF_Msk (0x01UL << FCE_KE_STS_LEF_Pos) /*!< FCE_KE STS: LEF Mask */
\r
4039 #define FCE_KE_STS_BEF_Pos 3 /*!< FCE_KE STS: BEF Position */
\r
4040 #define FCE_KE_STS_BEF_Msk (0x01UL << FCE_KE_STS_BEF_Pos) /*!< FCE_KE STS: BEF Mask */
\r
4042 /* -------------------------------- FCE_KE_LENGTH ------------------------------- */
\r
4043 #define FCE_KE_LENGTH_LENGTH_Pos 0 /*!< FCE_KE LENGTH: LENGTH Position */
\r
4044 #define FCE_KE_LENGTH_LENGTH_Msk (0x0000ffffUL << FCE_KE_LENGTH_LENGTH_Pos) /*!< FCE_KE LENGTH: LENGTH Mask */
\r
4046 /* -------------------------------- FCE_KE_CHECK -------------------------------- */
\r
4047 #define FCE_KE_CHECK_CHECK_Pos 0 /*!< FCE_KE CHECK: CHECK Position */
\r
4048 #define FCE_KE_CHECK_CHECK_Msk (0xffffffffUL << FCE_KE_CHECK_CHECK_Pos) /*!< FCE_KE CHECK: CHECK Mask */
\r
4050 /* --------------------------------- FCE_KE_CRC --------------------------------- */
\r
4051 #define FCE_KE_CRC_CRC_Pos 0 /*!< FCE_KE CRC: CRC Position */
\r
4052 #define FCE_KE_CRC_CRC_Msk (0xffffffffUL << FCE_KE_CRC_CRC_Pos) /*!< FCE_KE CRC: CRC Mask */
\r
4054 /* --------------------------------- FCE_KE_CTR --------------------------------- */
\r
4055 #define FCE_KE_CTR_FCM_Pos 0 /*!< FCE_KE CTR: FCM Position */
\r
4056 #define FCE_KE_CTR_FCM_Msk (0x01UL << FCE_KE_CTR_FCM_Pos) /*!< FCE_KE CTR: FCM Mask */
\r
4057 #define FCE_KE_CTR_FRM_CFG_Pos 1 /*!< FCE_KE CTR: FRM_CFG Position */
\r
4058 #define FCE_KE_CTR_FRM_CFG_Msk (0x01UL << FCE_KE_CTR_FRM_CFG_Pos) /*!< FCE_KE CTR: FRM_CFG Mask */
\r
4059 #define FCE_KE_CTR_FRM_CHECK_Pos 2 /*!< FCE_KE CTR: FRM_CHECK Position */
\r
4060 #define FCE_KE_CTR_FRM_CHECK_Msk (0x01UL << FCE_KE_CTR_FRM_CHECK_Pos) /*!< FCE_KE CTR: FRM_CHECK Mask */
\r
4063 /* ================================================================================ */
\r
4064 /* ================ Group 'PBA' Position & Mask ================ */
\r
4065 /* ================================================================================ */
\r
4068 /* ----------------------------------- PBA_STS ---------------------------------- */
\r
4069 #define PBA_STS_WERR_Pos 0 /*!< PBA STS: WERR Position */
\r
4070 #define PBA_STS_WERR_Msk (0x01UL << PBA_STS_WERR_Pos) /*!< PBA STS: WERR Mask */
\r
4072 /* ---------------------------------- PBA_WADDR --------------------------------- */
\r
4073 #define PBA_WADDR_WADDR_Pos 0 /*!< PBA WADDR: WADDR Position */
\r
4074 #define PBA_WADDR_WADDR_Msk (0xffffffffUL << PBA_WADDR_WADDR_Pos) /*!< PBA WADDR: WADDR Mask */
\r
4077 /* ================================================================================ */
\r
4078 /* ================ Group 'FLASH' Position & Mask ================ */
\r
4079 /* ================================================================================ */
\r
4082 /* ---------------------------------- FLASH_ID ---------------------------------- */
\r
4083 #define FLASH_ID_MOD_REV_Pos 0 /*!< FLASH ID: MOD_REV Position */
\r
4084 #define FLASH_ID_MOD_REV_Msk (0x000000ffUL << FLASH_ID_MOD_REV_Pos) /*!< FLASH ID: MOD_REV Mask */
\r
4085 #define FLASH_ID_MOD_TYPE_Pos 8 /*!< FLASH ID: MOD_TYPE Position */
\r
4086 #define FLASH_ID_MOD_TYPE_Msk (0x000000ffUL << FLASH_ID_MOD_TYPE_Pos) /*!< FLASH ID: MOD_TYPE Mask */
\r
4087 #define FLASH_ID_MOD_NUMBER_Pos 16 /*!< FLASH ID: MOD_NUMBER Position */
\r
4088 #define FLASH_ID_MOD_NUMBER_Msk (0x0000ffffUL << FLASH_ID_MOD_NUMBER_Pos) /*!< FLASH ID: MOD_NUMBER Mask */
\r
4090 /* ---------------------------------- FLASH_FSR --------------------------------- */
\r
4091 #define FLASH_FSR_PBUSY_Pos 0 /*!< FLASH FSR: PBUSY Position */
\r
4092 #define FLASH_FSR_PBUSY_Msk (0x01UL << FLASH_FSR_PBUSY_Pos) /*!< FLASH FSR: PBUSY Mask */
\r
4093 #define FLASH_FSR_FABUSY_Pos 1 /*!< FLASH FSR: FABUSY Position */
\r
4094 #define FLASH_FSR_FABUSY_Msk (0x01UL << FLASH_FSR_FABUSY_Pos) /*!< FLASH FSR: FABUSY Mask */
\r
4095 #define FLASH_FSR_PROG_Pos 4 /*!< FLASH FSR: PROG Position */
\r
4096 #define FLASH_FSR_PROG_Msk (0x01UL << FLASH_FSR_PROG_Pos) /*!< FLASH FSR: PROG Mask */
\r
4097 #define FLASH_FSR_ERASE_Pos 5 /*!< FLASH FSR: ERASE Position */
\r
4098 #define FLASH_FSR_ERASE_Msk (0x01UL << FLASH_FSR_ERASE_Pos) /*!< FLASH FSR: ERASE Mask */
\r
4099 #define FLASH_FSR_PFPAGE_Pos 6 /*!< FLASH FSR: PFPAGE Position */
\r
4100 #define FLASH_FSR_PFPAGE_Msk (0x01UL << FLASH_FSR_PFPAGE_Pos) /*!< FLASH FSR: PFPAGE Mask */
\r
4101 #define FLASH_FSR_PFOPER_Pos 8 /*!< FLASH FSR: PFOPER Position */
\r
4102 #define FLASH_FSR_PFOPER_Msk (0x01UL << FLASH_FSR_PFOPER_Pos) /*!< FLASH FSR: PFOPER Mask */
\r
4103 #define FLASH_FSR_SQER_Pos 10 /*!< FLASH FSR: SQER Position */
\r
4104 #define FLASH_FSR_SQER_Msk (0x01UL << FLASH_FSR_SQER_Pos) /*!< FLASH FSR: SQER Mask */
\r
4105 #define FLASH_FSR_PROER_Pos 11 /*!< FLASH FSR: PROER Position */
\r
4106 #define FLASH_FSR_PROER_Msk (0x01UL << FLASH_FSR_PROER_Pos) /*!< FLASH FSR: PROER Mask */
\r
4107 #define FLASH_FSR_PFSBER_Pos 12 /*!< FLASH FSR: PFSBER Position */
\r
4108 #define FLASH_FSR_PFSBER_Msk (0x01UL << FLASH_FSR_PFSBER_Pos) /*!< FLASH FSR: PFSBER Mask */
\r
4109 #define FLASH_FSR_PFDBER_Pos 14 /*!< FLASH FSR: PFDBER Position */
\r
4110 #define FLASH_FSR_PFDBER_Msk (0x01UL << FLASH_FSR_PFDBER_Pos) /*!< FLASH FSR: PFDBER Mask */
\r
4111 #define FLASH_FSR_PROIN_Pos 16 /*!< FLASH FSR: PROIN Position */
\r
4112 #define FLASH_FSR_PROIN_Msk (0x01UL << FLASH_FSR_PROIN_Pos) /*!< FLASH FSR: PROIN Mask */
\r
4113 #define FLASH_FSR_RPROIN_Pos 18 /*!< FLASH FSR: RPROIN Position */
\r
4114 #define FLASH_FSR_RPROIN_Msk (0x01UL << FLASH_FSR_RPROIN_Pos) /*!< FLASH FSR: RPROIN Mask */
\r
4115 #define FLASH_FSR_RPRODIS_Pos 19 /*!< FLASH FSR: RPRODIS Position */
\r
4116 #define FLASH_FSR_RPRODIS_Msk (0x01UL << FLASH_FSR_RPRODIS_Pos) /*!< FLASH FSR: RPRODIS Mask */
\r
4117 #define FLASH_FSR_WPROIN0_Pos 21 /*!< FLASH FSR: WPROIN0 Position */
\r
4118 #define FLASH_FSR_WPROIN0_Msk (0x01UL << FLASH_FSR_WPROIN0_Pos) /*!< FLASH FSR: WPROIN0 Mask */
\r
4119 #define FLASH_FSR_WPROIN1_Pos 22 /*!< FLASH FSR: WPROIN1 Position */
\r
4120 #define FLASH_FSR_WPROIN1_Msk (0x01UL << FLASH_FSR_WPROIN1_Pos) /*!< FLASH FSR: WPROIN1 Mask */
\r
4121 #define FLASH_FSR_WPROIN2_Pos 23 /*!< FLASH FSR: WPROIN2 Position */
\r
4122 #define FLASH_FSR_WPROIN2_Msk (0x01UL << FLASH_FSR_WPROIN2_Pos) /*!< FLASH FSR: WPROIN2 Mask */
\r
4123 #define FLASH_FSR_WPRODIS0_Pos 25 /*!< FLASH FSR: WPRODIS0 Position */
\r
4124 #define FLASH_FSR_WPRODIS0_Msk (0x01UL << FLASH_FSR_WPRODIS0_Pos) /*!< FLASH FSR: WPRODIS0 Mask */
\r
4125 #define FLASH_FSR_WPRODIS1_Pos 26 /*!< FLASH FSR: WPRODIS1 Position */
\r
4126 #define FLASH_FSR_WPRODIS1_Msk (0x01UL << FLASH_FSR_WPRODIS1_Pos) /*!< FLASH FSR: WPRODIS1 Mask */
\r
4127 #define FLASH_FSR_SLM_Pos 28 /*!< FLASH FSR: SLM Position */
\r
4128 #define FLASH_FSR_SLM_Msk (0x01UL << FLASH_FSR_SLM_Pos) /*!< FLASH FSR: SLM Mask */
\r
4129 #define FLASH_FSR_X_Pos 30 /*!< FLASH FSR: X Position */
\r
4130 #define FLASH_FSR_X_Msk (0x01UL << FLASH_FSR_X_Pos) /*!< FLASH FSR: X Mask */
\r
4131 #define FLASH_FSR_VER_Pos 31 /*!< FLASH FSR: VER Position */
\r
4132 #define FLASH_FSR_VER_Msk (0x01UL << FLASH_FSR_VER_Pos) /*!< FLASH FSR: VER Mask */
\r
4134 /* --------------------------------- FLASH_FCON --------------------------------- */
\r
4135 #define FLASH_FCON_WSPFLASH_Pos 0 /*!< FLASH FCON: WSPFLASH Position */
\r
4136 #define FLASH_FCON_WSPFLASH_Msk (0x0fUL << FLASH_FCON_WSPFLASH_Pos) /*!< FLASH FCON: WSPFLASH Mask */
\r
4137 #define FLASH_FCON_WSECPF_Pos 4 /*!< FLASH FCON: WSECPF Position */
\r
4138 #define FLASH_FCON_WSECPF_Msk (0x01UL << FLASH_FCON_WSECPF_Pos) /*!< FLASH FCON: WSECPF Mask */
\r
4139 #define FLASH_FCON_IDLE_Pos 13 /*!< FLASH FCON: IDLE Position */
\r
4140 #define FLASH_FCON_IDLE_Msk (0x01UL << FLASH_FCON_IDLE_Pos) /*!< FLASH FCON: IDLE Mask */
\r
4141 #define FLASH_FCON_ESLDIS_Pos 14 /*!< FLASH FCON: ESLDIS Position */
\r
4142 #define FLASH_FCON_ESLDIS_Msk (0x01UL << FLASH_FCON_ESLDIS_Pos) /*!< FLASH FCON: ESLDIS Mask */
\r
4143 #define FLASH_FCON_SLEEP_Pos 15 /*!< FLASH FCON: SLEEP Position */
\r
4144 #define FLASH_FCON_SLEEP_Msk (0x01UL << FLASH_FCON_SLEEP_Pos) /*!< FLASH FCON: SLEEP Mask */
\r
4145 #define FLASH_FCON_RPA_Pos 16 /*!< FLASH FCON: RPA Position */
\r
4146 #define FLASH_FCON_RPA_Msk (0x01UL << FLASH_FCON_RPA_Pos) /*!< FLASH FCON: RPA Mask */
\r
4147 #define FLASH_FCON_DCF_Pos 17 /*!< FLASH FCON: DCF Position */
\r
4148 #define FLASH_FCON_DCF_Msk (0x01UL << FLASH_FCON_DCF_Pos) /*!< FLASH FCON: DCF Mask */
\r
4149 #define FLASH_FCON_DDF_Pos 18 /*!< FLASH FCON: DDF Position */
\r
4150 #define FLASH_FCON_DDF_Msk (0x01UL << FLASH_FCON_DDF_Pos) /*!< FLASH FCON: DDF Mask */
\r
4151 #define FLASH_FCON_VOPERM_Pos 24 /*!< FLASH FCON: VOPERM Position */
\r
4152 #define FLASH_FCON_VOPERM_Msk (0x01UL << FLASH_FCON_VOPERM_Pos) /*!< FLASH FCON: VOPERM Mask */
\r
4153 #define FLASH_FCON_SQERM_Pos 25 /*!< FLASH FCON: SQERM Position */
\r
4154 #define FLASH_FCON_SQERM_Msk (0x01UL << FLASH_FCON_SQERM_Pos) /*!< FLASH FCON: SQERM Mask */
\r
4155 #define FLASH_FCON_PROERM_Pos 26 /*!< FLASH FCON: PROERM Position */
\r
4156 #define FLASH_FCON_PROERM_Msk (0x01UL << FLASH_FCON_PROERM_Pos) /*!< FLASH FCON: PROERM Mask */
\r
4157 #define FLASH_FCON_PFSBERM_Pos 27 /*!< FLASH FCON: PFSBERM Position */
\r
4158 #define FLASH_FCON_PFSBERM_Msk (0x01UL << FLASH_FCON_PFSBERM_Pos) /*!< FLASH FCON: PFSBERM Mask */
\r
4159 #define FLASH_FCON_PFDBERM_Pos 29 /*!< FLASH FCON: PFDBERM Position */
\r
4160 #define FLASH_FCON_PFDBERM_Msk (0x01UL << FLASH_FCON_PFDBERM_Pos) /*!< FLASH FCON: PFDBERM Mask */
\r
4161 #define FLASH_FCON_EOBM_Pos 31 /*!< FLASH FCON: EOBM Position */
\r
4162 #define FLASH_FCON_EOBM_Msk (0x01UL << FLASH_FCON_EOBM_Pos) /*!< FLASH FCON: EOBM Mask */
\r
4164 /* --------------------------------- FLASH_MARP --------------------------------- */
\r
4165 #define FLASH_MARP_MARGIN_Pos 0 /*!< FLASH MARP: MARGIN Position */
\r
4166 #define FLASH_MARP_MARGIN_Msk (0x0fUL << FLASH_MARP_MARGIN_Pos) /*!< FLASH MARP: MARGIN Mask */
\r
4167 #define FLASH_MARP_TRAPDIS_Pos 15 /*!< FLASH MARP: TRAPDIS Position */
\r
4168 #define FLASH_MARP_TRAPDIS_Msk (0x01UL << FLASH_MARP_TRAPDIS_Pos) /*!< FLASH MARP: TRAPDIS Mask */
\r
4170 /* -------------------------------- FLASH_PROCON0 ------------------------------- */
\r
4171 #define FLASH_PROCON0_S0L_Pos 0 /*!< FLASH PROCON0: S0L Position */
\r
4172 #define FLASH_PROCON0_S0L_Msk (0x01UL << FLASH_PROCON0_S0L_Pos) /*!< FLASH PROCON0: S0L Mask */
\r
4173 #define FLASH_PROCON0_S1L_Pos 1 /*!< FLASH PROCON0: S1L Position */
\r
4174 #define FLASH_PROCON0_S1L_Msk (0x01UL << FLASH_PROCON0_S1L_Pos) /*!< FLASH PROCON0: S1L Mask */
\r
4175 #define FLASH_PROCON0_S2L_Pos 2 /*!< FLASH PROCON0: S2L Position */
\r
4176 #define FLASH_PROCON0_S2L_Msk (0x01UL << FLASH_PROCON0_S2L_Pos) /*!< FLASH PROCON0: S2L Mask */
\r
4177 #define FLASH_PROCON0_S3L_Pos 3 /*!< FLASH PROCON0: S3L Position */
\r
4178 #define FLASH_PROCON0_S3L_Msk (0x01UL << FLASH_PROCON0_S3L_Pos) /*!< FLASH PROCON0: S3L Mask */
\r
4179 #define FLASH_PROCON0_S4L_Pos 4 /*!< FLASH PROCON0: S4L Position */
\r
4180 #define FLASH_PROCON0_S4L_Msk (0x01UL << FLASH_PROCON0_S4L_Pos) /*!< FLASH PROCON0: S4L Mask */
\r
4181 #define FLASH_PROCON0_S5L_Pos 5 /*!< FLASH PROCON0: S5L Position */
\r
4182 #define FLASH_PROCON0_S5L_Msk (0x01UL << FLASH_PROCON0_S5L_Pos) /*!< FLASH PROCON0: S5L Mask */
\r
4183 #define FLASH_PROCON0_S6L_Pos 6 /*!< FLASH PROCON0: S6L Position */
\r
4184 #define FLASH_PROCON0_S6L_Msk (0x01UL << FLASH_PROCON0_S6L_Pos) /*!< FLASH PROCON0: S6L Mask */
\r
4185 #define FLASH_PROCON0_S7L_Pos 7 /*!< FLASH PROCON0: S7L Position */
\r
4186 #define FLASH_PROCON0_S7L_Msk (0x01UL << FLASH_PROCON0_S7L_Pos) /*!< FLASH PROCON0: S7L Mask */
\r
4187 #define FLASH_PROCON0_S8L_Pos 8 /*!< FLASH PROCON0: S8L Position */
\r
4188 #define FLASH_PROCON0_S8L_Msk (0x01UL << FLASH_PROCON0_S8L_Pos) /*!< FLASH PROCON0: S8L Mask */
\r
4189 #define FLASH_PROCON0_S9L_Pos 9 /*!< FLASH PROCON0: S9L Position */
\r
4190 #define FLASH_PROCON0_S9L_Msk (0x01UL << FLASH_PROCON0_S9L_Pos) /*!< FLASH PROCON0: S9L Mask */
\r
4191 #define FLASH_PROCON0_RPRO_Pos 15 /*!< FLASH PROCON0: RPRO Position */
\r
4192 #define FLASH_PROCON0_RPRO_Msk (0x01UL << FLASH_PROCON0_RPRO_Pos) /*!< FLASH PROCON0: RPRO Mask */
\r
4194 /* -------------------------------- FLASH_PROCON1 ------------------------------- */
\r
4195 #define FLASH_PROCON1_S0L_Pos 0 /*!< FLASH PROCON1: S0L Position */
\r
4196 #define FLASH_PROCON1_S0L_Msk (0x01UL << FLASH_PROCON1_S0L_Pos) /*!< FLASH PROCON1: S0L Mask */
\r
4197 #define FLASH_PROCON1_S1L_Pos 1 /*!< FLASH PROCON1: S1L Position */
\r
4198 #define FLASH_PROCON1_S1L_Msk (0x01UL << FLASH_PROCON1_S1L_Pos) /*!< FLASH PROCON1: S1L Mask */
\r
4199 #define FLASH_PROCON1_S2L_Pos 2 /*!< FLASH PROCON1: S2L Position */
\r
4200 #define FLASH_PROCON1_S2L_Msk (0x01UL << FLASH_PROCON1_S2L_Pos) /*!< FLASH PROCON1: S2L Mask */
\r
4201 #define FLASH_PROCON1_S3L_Pos 3 /*!< FLASH PROCON1: S3L Position */
\r
4202 #define FLASH_PROCON1_S3L_Msk (0x01UL << FLASH_PROCON1_S3L_Pos) /*!< FLASH PROCON1: S3L Mask */
\r
4203 #define FLASH_PROCON1_S4L_Pos 4 /*!< FLASH PROCON1: S4L Position */
\r
4204 #define FLASH_PROCON1_S4L_Msk (0x01UL << FLASH_PROCON1_S4L_Pos) /*!< FLASH PROCON1: S4L Mask */
\r
4205 #define FLASH_PROCON1_S5L_Pos 5 /*!< FLASH PROCON1: S5L Position */
\r
4206 #define FLASH_PROCON1_S5L_Msk (0x01UL << FLASH_PROCON1_S5L_Pos) /*!< FLASH PROCON1: S5L Mask */
\r
4207 #define FLASH_PROCON1_S6L_Pos 6 /*!< FLASH PROCON1: S6L Position */
\r
4208 #define FLASH_PROCON1_S6L_Msk (0x01UL << FLASH_PROCON1_S6L_Pos) /*!< FLASH PROCON1: S6L Mask */
\r
4209 #define FLASH_PROCON1_S7L_Pos 7 /*!< FLASH PROCON1: S7L Position */
\r
4210 #define FLASH_PROCON1_S7L_Msk (0x01UL << FLASH_PROCON1_S7L_Pos) /*!< FLASH PROCON1: S7L Mask */
\r
4211 #define FLASH_PROCON1_S8L_Pos 8 /*!< FLASH PROCON1: S8L Position */
\r
4212 #define FLASH_PROCON1_S8L_Msk (0x01UL << FLASH_PROCON1_S8L_Pos) /*!< FLASH PROCON1: S8L Mask */
\r
4213 #define FLASH_PROCON1_S9L_Pos 9 /*!< FLASH PROCON1: S9L Position */
\r
4214 #define FLASH_PROCON1_S9L_Msk (0x01UL << FLASH_PROCON1_S9L_Pos) /*!< FLASH PROCON1: S9L Mask */
\r
4216 /* -------------------------------- FLASH_PROCON2 ------------------------------- */
\r
4217 #define FLASH_PROCON2_S0ROM_Pos 0 /*!< FLASH PROCON2: S0ROM Position */
\r
4218 #define FLASH_PROCON2_S0ROM_Msk (0x01UL << FLASH_PROCON2_S0ROM_Pos) /*!< FLASH PROCON2: S0ROM Mask */
\r
4219 #define FLASH_PROCON2_S1ROM_Pos 1 /*!< FLASH PROCON2: S1ROM Position */
\r
4220 #define FLASH_PROCON2_S1ROM_Msk (0x01UL << FLASH_PROCON2_S1ROM_Pos) /*!< FLASH PROCON2: S1ROM Mask */
\r
4221 #define FLASH_PROCON2_S2ROM_Pos 2 /*!< FLASH PROCON2: S2ROM Position */
\r
4222 #define FLASH_PROCON2_S2ROM_Msk (0x01UL << FLASH_PROCON2_S2ROM_Pos) /*!< FLASH PROCON2: S2ROM Mask */
\r
4223 #define FLASH_PROCON2_S3ROM_Pos 3 /*!< FLASH PROCON2: S3ROM Position */
\r
4224 #define FLASH_PROCON2_S3ROM_Msk (0x01UL << FLASH_PROCON2_S3ROM_Pos) /*!< FLASH PROCON2: S3ROM Mask */
\r
4225 #define FLASH_PROCON2_S4ROM_Pos 4 /*!< FLASH PROCON2: S4ROM Position */
\r
4226 #define FLASH_PROCON2_S4ROM_Msk (0x01UL << FLASH_PROCON2_S4ROM_Pos) /*!< FLASH PROCON2: S4ROM Mask */
\r
4227 #define FLASH_PROCON2_S5ROM_Pos 5 /*!< FLASH PROCON2: S5ROM Position */
\r
4228 #define FLASH_PROCON2_S5ROM_Msk (0x01UL << FLASH_PROCON2_S5ROM_Pos) /*!< FLASH PROCON2: S5ROM Mask */
\r
4229 #define FLASH_PROCON2_S6ROM_Pos 6 /*!< FLASH PROCON2: S6ROM Position */
\r
4230 #define FLASH_PROCON2_S6ROM_Msk (0x01UL << FLASH_PROCON2_S6ROM_Pos) /*!< FLASH PROCON2: S6ROM Mask */
\r
4231 #define FLASH_PROCON2_S7ROM_Pos 7 /*!< FLASH PROCON2: S7ROM Position */
\r
4232 #define FLASH_PROCON2_S7ROM_Msk (0x01UL << FLASH_PROCON2_S7ROM_Pos) /*!< FLASH PROCON2: S7ROM Mask */
\r
4233 #define FLASH_PROCON2_S8ROM_Pos 8 /*!< FLASH PROCON2: S8ROM Position */
\r
4234 #define FLASH_PROCON2_S8ROM_Msk (0x01UL << FLASH_PROCON2_S8ROM_Pos) /*!< FLASH PROCON2: S8ROM Mask */
\r
4235 #define FLASH_PROCON2_S9ROM_Pos 9 /*!< FLASH PROCON2: S9ROM Position */
\r
4236 #define FLASH_PROCON2_S9ROM_Msk (0x01UL << FLASH_PROCON2_S9ROM_Pos) /*!< FLASH PROCON2: S9ROM Mask */
\r
4239 /* ================================================================================ */
\r
4240 /* ================ struct 'PREF' Position & Mask ================ */
\r
4241 /* ================================================================================ */
\r
4244 /* ---------------------------------- PREF_PCON --------------------------------- */
\r
4245 #define PREF_PCON_IBYP_Pos 0 /*!< PREF PCON: IBYP Position */
\r
4246 #define PREF_PCON_IBYP_Msk (0x01UL << PREF_PCON_IBYP_Pos) /*!< PREF PCON: IBYP Mask */
\r
4247 #define PREF_PCON_IINV_Pos 1 /*!< PREF PCON: IINV Position */
\r
4248 #define PREF_PCON_IINV_Msk (0x01UL << PREF_PCON_IINV_Pos) /*!< PREF PCON: IINV Mask */
\r
4251 /* ================================================================================ */
\r
4252 /* ================ Group 'PMU' Position & Mask ================ */
\r
4253 /* ================================================================================ */
\r
4256 /* ----------------------------------- PMU_ID ----------------------------------- */
\r
4257 #define PMU_ID_MOD_REV_Pos 0 /*!< PMU ID: MOD_REV Position */
\r
4258 #define PMU_ID_MOD_REV_Msk (0x000000ffUL << PMU_ID_MOD_REV_Pos) /*!< PMU ID: MOD_REV Mask */
\r
4259 #define PMU_ID_MOD_TYPE_Pos 8 /*!< PMU ID: MOD_TYPE Position */
\r
4260 #define PMU_ID_MOD_TYPE_Msk (0x000000ffUL << PMU_ID_MOD_TYPE_Pos) /*!< PMU ID: MOD_TYPE Mask */
\r
4261 #define PMU_ID_MOD_NUMBER_Pos 16 /*!< PMU ID: MOD_NUMBER Position */
\r
4262 #define PMU_ID_MOD_NUMBER_Msk (0x0000ffffUL << PMU_ID_MOD_NUMBER_Pos) /*!< PMU ID: MOD_NUMBER Mask */
\r
4265 /* ================================================================================ */
\r
4266 /* ================ struct 'WDT' Position & Mask ================ */
\r
4267 /* ================================================================================ */
\r
4270 /* ----------------------------------- WDT_ID ----------------------------------- */
\r
4271 #define WDT_ID_MOD_REV_Pos 0 /*!< WDT ID: MOD_REV Position */
\r
4272 #define WDT_ID_MOD_REV_Msk (0x000000ffUL << WDT_ID_MOD_REV_Pos) /*!< WDT ID: MOD_REV Mask */
\r
4273 #define WDT_ID_MOD_TYPE_Pos 8 /*!< WDT ID: MOD_TYPE Position */
\r
4274 #define WDT_ID_MOD_TYPE_Msk (0x000000ffUL << WDT_ID_MOD_TYPE_Pos) /*!< WDT ID: MOD_TYPE Mask */
\r
4275 #define WDT_ID_MOD_NUMBER_Pos 16 /*!< WDT ID: MOD_NUMBER Position */
\r
4276 #define WDT_ID_MOD_NUMBER_Msk (0x0000ffffUL << WDT_ID_MOD_NUMBER_Pos) /*!< WDT ID: MOD_NUMBER Mask */
\r
4278 /* ----------------------------------- WDT_CTR ---------------------------------- */
\r
4279 #define WDT_CTR_ENB_Pos 0 /*!< WDT CTR: ENB Position */
\r
4280 #define WDT_CTR_ENB_Msk (0x01UL << WDT_CTR_ENB_Pos) /*!< WDT CTR: ENB Mask */
\r
4281 #define WDT_CTR_PRE_Pos 1 /*!< WDT CTR: PRE Position */
\r
4282 #define WDT_CTR_PRE_Msk (0x01UL << WDT_CTR_PRE_Pos) /*!< WDT CTR: PRE Mask */
\r
4283 #define WDT_CTR_DSP_Pos 4 /*!< WDT CTR: DSP Position */
\r
4284 #define WDT_CTR_DSP_Msk (0x01UL << WDT_CTR_DSP_Pos) /*!< WDT CTR: DSP Mask */
\r
4285 #define WDT_CTR_SPW_Pos 8 /*!< WDT CTR: SPW Position */
\r
4286 #define WDT_CTR_SPW_Msk (0x000000ffUL << WDT_CTR_SPW_Pos) /*!< WDT CTR: SPW Mask */
\r
4288 /* ----------------------------------- WDT_SRV ---------------------------------- */
\r
4289 #define WDT_SRV_SRV_Pos 0 /*!< WDT SRV: SRV Position */
\r
4290 #define WDT_SRV_SRV_Msk (0xffffffffUL << WDT_SRV_SRV_Pos) /*!< WDT SRV: SRV Mask */
\r
4292 /* ----------------------------------- WDT_TIM ---------------------------------- */
\r
4293 #define WDT_TIM_TIM_Pos 0 /*!< WDT TIM: TIM Position */
\r
4294 #define WDT_TIM_TIM_Msk (0xffffffffUL << WDT_TIM_TIM_Pos) /*!< WDT TIM: TIM Mask */
\r
4296 /* ----------------------------------- WDT_WLB ---------------------------------- */
\r
4297 #define WDT_WLB_WLB_Pos 0 /*!< WDT WLB: WLB Position */
\r
4298 #define WDT_WLB_WLB_Msk (0xffffffffUL << WDT_WLB_WLB_Pos) /*!< WDT WLB: WLB Mask */
\r
4300 /* ----------------------------------- WDT_WUB ---------------------------------- */
\r
4301 #define WDT_WUB_WUB_Pos 0 /*!< WDT WUB: WUB Position */
\r
4302 #define WDT_WUB_WUB_Msk (0xffffffffUL << WDT_WUB_WUB_Pos) /*!< WDT WUB: WUB Mask */
\r
4304 /* --------------------------------- WDT_WDTSTS --------------------------------- */
\r
4305 #define WDT_WDTSTS_ALMS_Pos 0 /*!< WDT WDTSTS: ALMS Position */
\r
4306 #define WDT_WDTSTS_ALMS_Msk (0x01UL << WDT_WDTSTS_ALMS_Pos) /*!< WDT WDTSTS: ALMS Mask */
\r
4308 /* --------------------------------- WDT_WDTCLR --------------------------------- */
\r
4309 #define WDT_WDTCLR_ALMC_Pos 0 /*!< WDT WDTCLR: ALMC Position */
\r
4310 #define WDT_WDTCLR_ALMC_Msk (0x01UL << WDT_WDTCLR_ALMC_Pos) /*!< WDT WDTCLR: ALMC Mask */
\r
4313 /* ================================================================================ */
\r
4314 /* ================ struct 'RTC' Position & Mask ================ */
\r
4315 /* ================================================================================ */
\r
4318 /* ----------------------------------- RTC_ID ----------------------------------- */
\r
4319 #define RTC_ID_MOD_REV_Pos 0 /*!< RTC ID: MOD_REV Position */
\r
4320 #define RTC_ID_MOD_REV_Msk (0x000000ffUL << RTC_ID_MOD_REV_Pos) /*!< RTC ID: MOD_REV Mask */
\r
4321 #define RTC_ID_MOD_TYPE_Pos 8 /*!< RTC ID: MOD_TYPE Position */
\r
4322 #define RTC_ID_MOD_TYPE_Msk (0x000000ffUL << RTC_ID_MOD_TYPE_Pos) /*!< RTC ID: MOD_TYPE Mask */
\r
4323 #define RTC_ID_MOD_NUMBER_Pos 16 /*!< RTC ID: MOD_NUMBER Position */
\r
4324 #define RTC_ID_MOD_NUMBER_Msk (0x0000ffffUL << RTC_ID_MOD_NUMBER_Pos) /*!< RTC ID: MOD_NUMBER Mask */
\r
4326 /* ----------------------------------- RTC_CTR ---------------------------------- */
\r
4327 #define RTC_CTR_ENB_Pos 0 /*!< RTC CTR: ENB Position */
\r
4328 #define RTC_CTR_ENB_Msk (0x01UL << RTC_CTR_ENB_Pos) /*!< RTC CTR: ENB Mask */
\r
4329 #define RTC_CTR_TAE_Pos 2 /*!< RTC CTR: TAE Position */
\r
4330 #define RTC_CTR_TAE_Msk (0x01UL << RTC_CTR_TAE_Pos) /*!< RTC CTR: TAE Mask */
\r
4331 #define RTC_CTR_ESEC_Pos 8 /*!< RTC CTR: ESEC Position */
\r
4332 #define RTC_CTR_ESEC_Msk (0x01UL << RTC_CTR_ESEC_Pos) /*!< RTC CTR: ESEC Mask */
\r
4333 #define RTC_CTR_EMIC_Pos 9 /*!< RTC CTR: EMIC Position */
\r
4334 #define RTC_CTR_EMIC_Msk (0x01UL << RTC_CTR_EMIC_Pos) /*!< RTC CTR: EMIC Mask */
\r
4335 #define RTC_CTR_EHOC_Pos 10 /*!< RTC CTR: EHOC Position */
\r
4336 #define RTC_CTR_EHOC_Msk (0x01UL << RTC_CTR_EHOC_Pos) /*!< RTC CTR: EHOC Mask */
\r
4337 #define RTC_CTR_EDAC_Pos 11 /*!< RTC CTR: EDAC Position */
\r
4338 #define RTC_CTR_EDAC_Msk (0x01UL << RTC_CTR_EDAC_Pos) /*!< RTC CTR: EDAC Mask */
\r
4339 #define RTC_CTR_EMOC_Pos 13 /*!< RTC CTR: EMOC Position */
\r
4340 #define RTC_CTR_EMOC_Msk (0x01UL << RTC_CTR_EMOC_Pos) /*!< RTC CTR: EMOC Mask */
\r
4341 #define RTC_CTR_EYEC_Pos 14 /*!< RTC CTR: EYEC Position */
\r
4342 #define RTC_CTR_EYEC_Msk (0x01UL << RTC_CTR_EYEC_Pos) /*!< RTC CTR: EYEC Mask */
\r
4343 #define RTC_CTR_DIV_Pos 16 /*!< RTC CTR: DIV Position */
\r
4344 #define RTC_CTR_DIV_Msk (0x0000ffffUL << RTC_CTR_DIV_Pos) /*!< RTC CTR: DIV Mask */
\r
4346 /* --------------------------------- RTC_RAWSTAT -------------------------------- */
\r
4347 #define RTC_RAWSTAT_RPSE_Pos 0 /*!< RTC RAWSTAT: RPSE Position */
\r
4348 #define RTC_RAWSTAT_RPSE_Msk (0x01UL << RTC_RAWSTAT_RPSE_Pos) /*!< RTC RAWSTAT: RPSE Mask */
\r
4349 #define RTC_RAWSTAT_RPMI_Pos 1 /*!< RTC RAWSTAT: RPMI Position */
\r
4350 #define RTC_RAWSTAT_RPMI_Msk (0x01UL << RTC_RAWSTAT_RPMI_Pos) /*!< RTC RAWSTAT: RPMI Mask */
\r
4351 #define RTC_RAWSTAT_RPHO_Pos 2 /*!< RTC RAWSTAT: RPHO Position */
\r
4352 #define RTC_RAWSTAT_RPHO_Msk (0x01UL << RTC_RAWSTAT_RPHO_Pos) /*!< RTC RAWSTAT: RPHO Mask */
\r
4353 #define RTC_RAWSTAT_RPDA_Pos 3 /*!< RTC RAWSTAT: RPDA Position */
\r
4354 #define RTC_RAWSTAT_RPDA_Msk (0x01UL << RTC_RAWSTAT_RPDA_Pos) /*!< RTC RAWSTAT: RPDA Mask */
\r
4355 #define RTC_RAWSTAT_RPMO_Pos 5 /*!< RTC RAWSTAT: RPMO Position */
\r
4356 #define RTC_RAWSTAT_RPMO_Msk (0x01UL << RTC_RAWSTAT_RPMO_Pos) /*!< RTC RAWSTAT: RPMO Mask */
\r
4357 #define RTC_RAWSTAT_RPYE_Pos 6 /*!< RTC RAWSTAT: RPYE Position */
\r
4358 #define RTC_RAWSTAT_RPYE_Msk (0x01UL << RTC_RAWSTAT_RPYE_Pos) /*!< RTC RAWSTAT: RPYE Mask */
\r
4359 #define RTC_RAWSTAT_RAI_Pos 8 /*!< RTC RAWSTAT: RAI Position */
\r
4360 #define RTC_RAWSTAT_RAI_Msk (0x01UL << RTC_RAWSTAT_RAI_Pos) /*!< RTC RAWSTAT: RAI Mask */
\r
4362 /* ---------------------------------- RTC_STSSR --------------------------------- */
\r
4363 #define RTC_STSSR_SPSE_Pos 0 /*!< RTC STSSR: SPSE Position */
\r
4364 #define RTC_STSSR_SPSE_Msk (0x01UL << RTC_STSSR_SPSE_Pos) /*!< RTC STSSR: SPSE Mask */
\r
4365 #define RTC_STSSR_SPMI_Pos 1 /*!< RTC STSSR: SPMI Position */
\r
4366 #define RTC_STSSR_SPMI_Msk (0x01UL << RTC_STSSR_SPMI_Pos) /*!< RTC STSSR: SPMI Mask */
\r
4367 #define RTC_STSSR_SPHO_Pos 2 /*!< RTC STSSR: SPHO Position */
\r
4368 #define RTC_STSSR_SPHO_Msk (0x01UL << RTC_STSSR_SPHO_Pos) /*!< RTC STSSR: SPHO Mask */
\r
4369 #define RTC_STSSR_SPDA_Pos 3 /*!< RTC STSSR: SPDA Position */
\r
4370 #define RTC_STSSR_SPDA_Msk (0x01UL << RTC_STSSR_SPDA_Pos) /*!< RTC STSSR: SPDA Mask */
\r
4371 #define RTC_STSSR_SPMO_Pos 5 /*!< RTC STSSR: SPMO Position */
\r
4372 #define RTC_STSSR_SPMO_Msk (0x01UL << RTC_STSSR_SPMO_Pos) /*!< RTC STSSR: SPMO Mask */
\r
4373 #define RTC_STSSR_SPYE_Pos 6 /*!< RTC STSSR: SPYE Position */
\r
4374 #define RTC_STSSR_SPYE_Msk (0x01UL << RTC_STSSR_SPYE_Pos) /*!< RTC STSSR: SPYE Mask */
\r
4375 #define RTC_STSSR_SAI_Pos 8 /*!< RTC STSSR: SAI Position */
\r
4376 #define RTC_STSSR_SAI_Msk (0x01UL << RTC_STSSR_SAI_Pos) /*!< RTC STSSR: SAI Mask */
\r
4378 /* ---------------------------------- RTC_MSKSR --------------------------------- */
\r
4379 #define RTC_MSKSR_MPSE_Pos 0 /*!< RTC MSKSR: MPSE Position */
\r
4380 #define RTC_MSKSR_MPSE_Msk (0x01UL << RTC_MSKSR_MPSE_Pos) /*!< RTC MSKSR: MPSE Mask */
\r
4381 #define RTC_MSKSR_MPMI_Pos 1 /*!< RTC MSKSR: MPMI Position */
\r
4382 #define RTC_MSKSR_MPMI_Msk (0x01UL << RTC_MSKSR_MPMI_Pos) /*!< RTC MSKSR: MPMI Mask */
\r
4383 #define RTC_MSKSR_MPHO_Pos 2 /*!< RTC MSKSR: MPHO Position */
\r
4384 #define RTC_MSKSR_MPHO_Msk (0x01UL << RTC_MSKSR_MPHO_Pos) /*!< RTC MSKSR: MPHO Mask */
\r
4385 #define RTC_MSKSR_MPDA_Pos 3 /*!< RTC MSKSR: MPDA Position */
\r
4386 #define RTC_MSKSR_MPDA_Msk (0x01UL << RTC_MSKSR_MPDA_Pos) /*!< RTC MSKSR: MPDA Mask */
\r
4387 #define RTC_MSKSR_MPMO_Pos 5 /*!< RTC MSKSR: MPMO Position */
\r
4388 #define RTC_MSKSR_MPMO_Msk (0x01UL << RTC_MSKSR_MPMO_Pos) /*!< RTC MSKSR: MPMO Mask */
\r
4389 #define RTC_MSKSR_MPYE_Pos 6 /*!< RTC MSKSR: MPYE Position */
\r
4390 #define RTC_MSKSR_MPYE_Msk (0x01UL << RTC_MSKSR_MPYE_Pos) /*!< RTC MSKSR: MPYE Mask */
\r
4391 #define RTC_MSKSR_MAI_Pos 8 /*!< RTC MSKSR: MAI Position */
\r
4392 #define RTC_MSKSR_MAI_Msk (0x01UL << RTC_MSKSR_MAI_Pos) /*!< RTC MSKSR: MAI Mask */
\r
4394 /* ---------------------------------- RTC_CLRSR --------------------------------- */
\r
4395 #define RTC_CLRSR_RPSE_Pos 0 /*!< RTC CLRSR: RPSE Position */
\r
4396 #define RTC_CLRSR_RPSE_Msk (0x01UL << RTC_CLRSR_RPSE_Pos) /*!< RTC CLRSR: RPSE Mask */
\r
4397 #define RTC_CLRSR_RPMI_Pos 1 /*!< RTC CLRSR: RPMI Position */
\r
4398 #define RTC_CLRSR_RPMI_Msk (0x01UL << RTC_CLRSR_RPMI_Pos) /*!< RTC CLRSR: RPMI Mask */
\r
4399 #define RTC_CLRSR_RPHO_Pos 2 /*!< RTC CLRSR: RPHO Position */
\r
4400 #define RTC_CLRSR_RPHO_Msk (0x01UL << RTC_CLRSR_RPHO_Pos) /*!< RTC CLRSR: RPHO Mask */
\r
4401 #define RTC_CLRSR_RPDA_Pos 3 /*!< RTC CLRSR: RPDA Position */
\r
4402 #define RTC_CLRSR_RPDA_Msk (0x01UL << RTC_CLRSR_RPDA_Pos) /*!< RTC CLRSR: RPDA Mask */
\r
4403 #define RTC_CLRSR_RPMO_Pos 5 /*!< RTC CLRSR: RPMO Position */
\r
4404 #define RTC_CLRSR_RPMO_Msk (0x01UL << RTC_CLRSR_RPMO_Pos) /*!< RTC CLRSR: RPMO Mask */
\r
4405 #define RTC_CLRSR_RPYE_Pos 6 /*!< RTC CLRSR: RPYE Position */
\r
4406 #define RTC_CLRSR_RPYE_Msk (0x01UL << RTC_CLRSR_RPYE_Pos) /*!< RTC CLRSR: RPYE Mask */
\r
4407 #define RTC_CLRSR_RAI_Pos 8 /*!< RTC CLRSR: RAI Position */
\r
4408 #define RTC_CLRSR_RAI_Msk (0x01UL << RTC_CLRSR_RAI_Pos) /*!< RTC CLRSR: RAI Mask */
\r
4410 /* ---------------------------------- RTC_ATIM0 --------------------------------- */
\r
4411 #define RTC_ATIM0_ASE_Pos 0 /*!< RTC ATIM0: ASE Position */
\r
4412 #define RTC_ATIM0_ASE_Msk (0x3fUL << RTC_ATIM0_ASE_Pos) /*!< RTC ATIM0: ASE Mask */
\r
4413 #define RTC_ATIM0_AMI_Pos 8 /*!< RTC ATIM0: AMI Position */
\r
4414 #define RTC_ATIM0_AMI_Msk (0x3fUL << RTC_ATIM0_AMI_Pos) /*!< RTC ATIM0: AMI Mask */
\r
4415 #define RTC_ATIM0_AHO_Pos 16 /*!< RTC ATIM0: AHO Position */
\r
4416 #define RTC_ATIM0_AHO_Msk (0x1fUL << RTC_ATIM0_AHO_Pos) /*!< RTC ATIM0: AHO Mask */
\r
4417 #define RTC_ATIM0_ADA_Pos 24 /*!< RTC ATIM0: ADA Position */
\r
4418 #define RTC_ATIM0_ADA_Msk (0x1fUL << RTC_ATIM0_ADA_Pos) /*!< RTC ATIM0: ADA Mask */
\r
4420 /* ---------------------------------- RTC_ATIM1 --------------------------------- */
\r
4421 #define RTC_ATIM1_AMO_Pos 8 /*!< RTC ATIM1: AMO Position */
\r
4422 #define RTC_ATIM1_AMO_Msk (0x0fUL << RTC_ATIM1_AMO_Pos) /*!< RTC ATIM1: AMO Mask */
\r
4423 #define RTC_ATIM1_AYE_Pos 16 /*!< RTC ATIM1: AYE Position */
\r
4424 #define RTC_ATIM1_AYE_Msk (0x0000ffffUL << RTC_ATIM1_AYE_Pos) /*!< RTC ATIM1: AYE Mask */
\r
4426 /* ---------------------------------- RTC_TIM0 ---------------------------------- */
\r
4427 #define RTC_TIM0_SE_Pos 0 /*!< RTC TIM0: SE Position */
\r
4428 #define RTC_TIM0_SE_Msk (0x3fUL << RTC_TIM0_SE_Pos) /*!< RTC TIM0: SE Mask */
\r
4429 #define RTC_TIM0_MI_Pos 8 /*!< RTC TIM0: MI Position */
\r
4430 #define RTC_TIM0_MI_Msk (0x3fUL << RTC_TIM0_MI_Pos) /*!< RTC TIM0: MI Mask */
\r
4431 #define RTC_TIM0_HO_Pos 16 /*!< RTC TIM0: HO Position */
\r
4432 #define RTC_TIM0_HO_Msk (0x1fUL << RTC_TIM0_HO_Pos) /*!< RTC TIM0: HO Mask */
\r
4433 #define RTC_TIM0_DA_Pos 24 /*!< RTC TIM0: DA Position */
\r
4434 #define RTC_TIM0_DA_Msk (0x1fUL << RTC_TIM0_DA_Pos) /*!< RTC TIM0: DA Mask */
\r
4436 /* ---------------------------------- RTC_TIM1 ---------------------------------- */
\r
4437 #define RTC_TIM1_DAWE_Pos 0 /*!< RTC TIM1: DAWE Position */
\r
4438 #define RTC_TIM1_DAWE_Msk (0x07UL << RTC_TIM1_DAWE_Pos) /*!< RTC TIM1: DAWE Mask */
\r
4439 #define RTC_TIM1_MO_Pos 8 /*!< RTC TIM1: MO Position */
\r
4440 #define RTC_TIM1_MO_Msk (0x0fUL << RTC_TIM1_MO_Pos) /*!< RTC TIM1: MO Mask */
\r
4441 #define RTC_TIM1_YE_Pos 16 /*!< RTC TIM1: YE Position */
\r
4442 #define RTC_TIM1_YE_Msk (0x0000ffffUL << RTC_TIM1_YE_Pos) /*!< RTC TIM1: YE Mask */
\r
4445 /* ================================================================================ */
\r
4446 /* ================ struct 'SCU_CLK' Position & Mask ================ */
\r
4447 /* ================================================================================ */
\r
4450 /* ------------------------------- SCU_CLK_CLKSTAT ------------------------------ */
\r
4451 #define SCU_CLK_CLKSTAT_USBCST_Pos 0 /*!< SCU_CLK CLKSTAT: USBCST Position */
\r
4452 #define SCU_CLK_CLKSTAT_USBCST_Msk (0x01UL << SCU_CLK_CLKSTAT_USBCST_Pos) /*!< SCU_CLK CLKSTAT: USBCST Mask */
\r
4453 #define SCU_CLK_CLKSTAT_ETH0CST_Pos 2 /*!< SCU_CLK CLKSTAT: ETH0CST Position */
\r
4454 #define SCU_CLK_CLKSTAT_ETH0CST_Msk (0x01UL << SCU_CLK_CLKSTAT_ETH0CST_Pos) /*!< SCU_CLK CLKSTAT: ETH0CST Mask */
\r
4455 #define SCU_CLK_CLKSTAT_CCUCST_Pos 4 /*!< SCU_CLK CLKSTAT: CCUCST Position */
\r
4456 #define SCU_CLK_CLKSTAT_CCUCST_Msk (0x01UL << SCU_CLK_CLKSTAT_CCUCST_Pos) /*!< SCU_CLK CLKSTAT: CCUCST Mask */
\r
4457 #define SCU_CLK_CLKSTAT_WDTCST_Pos 5 /*!< SCU_CLK CLKSTAT: WDTCST Position */
\r
4458 #define SCU_CLK_CLKSTAT_WDTCST_Msk (0x01UL << SCU_CLK_CLKSTAT_WDTCST_Pos) /*!< SCU_CLK CLKSTAT: WDTCST Mask */
\r
4460 /* ------------------------------- SCU_CLK_CLKSET ------------------------------- */
\r
4461 #define SCU_CLK_CLKSET_USBCEN_Pos 0 /*!< SCU_CLK CLKSET: USBCEN Position */
\r
4462 #define SCU_CLK_CLKSET_USBCEN_Msk (0x01UL << SCU_CLK_CLKSET_USBCEN_Pos) /*!< SCU_CLK CLKSET: USBCEN Mask */
\r
4463 #define SCU_CLK_CLKSET_ETH0CEN_Pos 2 /*!< SCU_CLK CLKSET: ETH0CEN Position */
\r
4464 #define SCU_CLK_CLKSET_ETH0CEN_Msk (0x01UL << SCU_CLK_CLKSET_ETH0CEN_Pos) /*!< SCU_CLK CLKSET: ETH0CEN Mask */
\r
4465 #define SCU_CLK_CLKSET_CCUCEN_Pos 4 /*!< SCU_CLK CLKSET: CCUCEN Position */
\r
4466 #define SCU_CLK_CLKSET_CCUCEN_Msk (0x01UL << SCU_CLK_CLKSET_CCUCEN_Pos) /*!< SCU_CLK CLKSET: CCUCEN Mask */
\r
4467 #define SCU_CLK_CLKSET_WDTCEN_Pos 5 /*!< SCU_CLK CLKSET: WDTCEN Position */
\r
4468 #define SCU_CLK_CLKSET_WDTCEN_Msk (0x01UL << SCU_CLK_CLKSET_WDTCEN_Pos) /*!< SCU_CLK CLKSET: WDTCEN Mask */
\r
4470 /* ------------------------------- SCU_CLK_CLKCLR ------------------------------- */
\r
4471 #define SCU_CLK_CLKCLR_USBCDI_Pos 0 /*!< SCU_CLK CLKCLR: USBCDI Position */
\r
4472 #define SCU_CLK_CLKCLR_USBCDI_Msk (0x01UL << SCU_CLK_CLKCLR_USBCDI_Pos) /*!< SCU_CLK CLKCLR: USBCDI Mask */
\r
4473 #define SCU_CLK_CLKCLR_ETH0CDI_Pos 2 /*!< SCU_CLK CLKCLR: ETH0CDI Position */
\r
4474 #define SCU_CLK_CLKCLR_ETH0CDI_Msk (0x01UL << SCU_CLK_CLKCLR_ETH0CDI_Pos) /*!< SCU_CLK CLKCLR: ETH0CDI Mask */
\r
4475 #define SCU_CLK_CLKCLR_CCUCDI_Pos 4 /*!< SCU_CLK CLKCLR: CCUCDI Position */
\r
4476 #define SCU_CLK_CLKCLR_CCUCDI_Msk (0x01UL << SCU_CLK_CLKCLR_CCUCDI_Pos) /*!< SCU_CLK CLKCLR: CCUCDI Mask */
\r
4477 #define SCU_CLK_CLKCLR_WDTCDI_Pos 5 /*!< SCU_CLK CLKCLR: WDTCDI Position */
\r
4478 #define SCU_CLK_CLKCLR_WDTCDI_Msk (0x01UL << SCU_CLK_CLKCLR_WDTCDI_Pos) /*!< SCU_CLK CLKCLR: WDTCDI Mask */
\r
4480 /* ------------------------------ SCU_CLK_SYSCLKCR ------------------------------ */
\r
4481 #define SCU_CLK_SYSCLKCR_SYSDIV_Pos 0 /*!< SCU_CLK SYSCLKCR: SYSDIV Position */
\r
4482 #define SCU_CLK_SYSCLKCR_SYSDIV_Msk (0x000000ffUL << SCU_CLK_SYSCLKCR_SYSDIV_Pos) /*!< SCU_CLK SYSCLKCR: SYSDIV Mask */
\r
4483 #define SCU_CLK_SYSCLKCR_SYSSEL_Pos 16 /*!< SCU_CLK SYSCLKCR: SYSSEL Position */
\r
4484 #define SCU_CLK_SYSCLKCR_SYSSEL_Msk (0x01UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos) /*!< SCU_CLK SYSCLKCR: SYSSEL Mask */
\r
4486 /* ------------------------------ SCU_CLK_CPUCLKCR ------------------------------ */
\r
4487 #define SCU_CLK_CPUCLKCR_CPUDIV_Pos 0 /*!< SCU_CLK CPUCLKCR: CPUDIV Position */
\r
4488 #define SCU_CLK_CPUCLKCR_CPUDIV_Msk (0x01UL << SCU_CLK_CPUCLKCR_CPUDIV_Pos) /*!< SCU_CLK CPUCLKCR: CPUDIV Mask */
\r
4490 /* ------------------------------- SCU_CLK_PBCLKCR ------------------------------ */
\r
4491 #define SCU_CLK_PBCLKCR_PBDIV_Pos 0 /*!< SCU_CLK PBCLKCR: PBDIV Position */
\r
4492 #define SCU_CLK_PBCLKCR_PBDIV_Msk (0x01UL << SCU_CLK_PBCLKCR_PBDIV_Pos) /*!< SCU_CLK PBCLKCR: PBDIV Mask */
\r
4494 /* ------------------------------ SCU_CLK_USBCLKCR ------------------------------ */
\r
4495 #define SCU_CLK_USBCLKCR_USBDIV_Pos 0 /*!< SCU_CLK USBCLKCR: USBDIV Position */
\r
4496 #define SCU_CLK_USBCLKCR_USBDIV_Msk (0x07UL << SCU_CLK_USBCLKCR_USBDIV_Pos) /*!< SCU_CLK USBCLKCR: USBDIV Mask */
\r
4497 #define SCU_CLK_USBCLKCR_USBSEL_Pos 16 /*!< SCU_CLK USBCLKCR: USBSEL Position */
\r
4498 #define SCU_CLK_USBCLKCR_USBSEL_Msk (0x01UL << SCU_CLK_USBCLKCR_USBSEL_Pos) /*!< SCU_CLK USBCLKCR: USBSEL Mask */
\r
4500 /* ------------------------------ SCU_CLK_CCUCLKCR ------------------------------ */
\r
4501 #define SCU_CLK_CCUCLKCR_CCUDIV_Pos 0 /*!< SCU_CLK CCUCLKCR: CCUDIV Position */
\r
4502 #define SCU_CLK_CCUCLKCR_CCUDIV_Msk (0x01UL << SCU_CLK_CCUCLKCR_CCUDIV_Pos) /*!< SCU_CLK CCUCLKCR: CCUDIV Mask */
\r
4504 /* ------------------------------ SCU_CLK_WDTCLKCR ------------------------------ */
\r
4505 #define SCU_CLK_WDTCLKCR_WDTDIV_Pos 0 /*!< SCU_CLK WDTCLKCR: WDTDIV Position */
\r
4506 #define SCU_CLK_WDTCLKCR_WDTDIV_Msk (0x000000ffUL << SCU_CLK_WDTCLKCR_WDTDIV_Pos) /*!< SCU_CLK WDTCLKCR: WDTDIV Mask */
\r
4507 #define SCU_CLK_WDTCLKCR_WDTSEL_Pos 16 /*!< SCU_CLK WDTCLKCR: WDTSEL Position */
\r
4508 #define SCU_CLK_WDTCLKCR_WDTSEL_Msk (0x03UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos) /*!< SCU_CLK WDTCLKCR: WDTSEL Mask */
\r
4510 /* ------------------------------ SCU_CLK_EXTCLKCR ------------------------------ */
\r
4511 #define SCU_CLK_EXTCLKCR_ECKSEL_Pos 0 /*!< SCU_CLK EXTCLKCR: ECKSEL Position */
\r
4512 #define SCU_CLK_EXTCLKCR_ECKSEL_Msk (0x07UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos) /*!< SCU_CLK EXTCLKCR: ECKSEL Mask */
\r
4513 #define SCU_CLK_EXTCLKCR_ECKDIV_Pos 16 /*!< SCU_CLK EXTCLKCR: ECKDIV Position */
\r
4514 #define SCU_CLK_EXTCLKCR_ECKDIV_Msk (0x000001ffUL << SCU_CLK_EXTCLKCR_ECKDIV_Pos) /*!< SCU_CLK EXTCLKCR: ECKDIV Mask */
\r
4516 /* ----------------------------- SCU_CLK_MLINKCLKCR ----------------------------- */
\r
4517 #define SCU_CLK_MLINKCLKCR_SYSDIV_Pos 0 /*!< SCU_CLK MLINKCLKCR: SYSDIV Position */
\r
4518 #define SCU_CLK_MLINKCLKCR_SYSDIV_Msk (0x000000ffUL << SCU_CLK_MLINKCLKCR_SYSDIV_Pos) /*!< SCU_CLK MLINKCLKCR: SYSDIV Mask */
\r
4519 #define SCU_CLK_MLINKCLKCR_SYSSEL_Pos 8 /*!< SCU_CLK MLINKCLKCR: SYSSEL Position */
\r
4520 #define SCU_CLK_MLINKCLKCR_SYSSEL_Msk (0x01UL << SCU_CLK_MLINKCLKCR_SYSSEL_Pos) /*!< SCU_CLK MLINKCLKCR: SYSSEL Mask */
\r
4521 #define SCU_CLK_MLINKCLKCR_CPUDIV_Pos 10 /*!< SCU_CLK MLINKCLKCR: CPUDIV Position */
\r
4522 #define SCU_CLK_MLINKCLKCR_CPUDIV_Msk (0x01UL << SCU_CLK_MLINKCLKCR_CPUDIV_Pos) /*!< SCU_CLK MLINKCLKCR: CPUDIV Mask */
\r
4523 #define SCU_CLK_MLINKCLKCR_PBDIV_Pos 12 /*!< SCU_CLK MLINKCLKCR: PBDIV Position */
\r
4524 #define SCU_CLK_MLINKCLKCR_PBDIV_Msk (0x01UL << SCU_CLK_MLINKCLKCR_PBDIV_Pos) /*!< SCU_CLK MLINKCLKCR: PBDIV Mask */
\r
4525 #define SCU_CLK_MLINKCLKCR_CCUDIV_Pos 14 /*!< SCU_CLK MLINKCLKCR: CCUDIV Position */
\r
4526 #define SCU_CLK_MLINKCLKCR_CCUDIV_Msk (0x01UL << SCU_CLK_MLINKCLKCR_CCUDIV_Pos) /*!< SCU_CLK MLINKCLKCR: CCUDIV Mask */
\r
4527 #define SCU_CLK_MLINKCLKCR_WDTDIV_Pos 16 /*!< SCU_CLK MLINKCLKCR: WDTDIV Position */
\r
4528 #define SCU_CLK_MLINKCLKCR_WDTDIV_Msk (0x000000ffUL << SCU_CLK_MLINKCLKCR_WDTDIV_Pos) /*!< SCU_CLK MLINKCLKCR: WDTDIV Mask */
\r
4529 #define SCU_CLK_MLINKCLKCR_WDTSEL_Pos 24 /*!< SCU_CLK MLINKCLKCR: WDTSEL Position */
\r
4530 #define SCU_CLK_MLINKCLKCR_WDTSEL_Msk (0x03UL << SCU_CLK_MLINKCLKCR_WDTSEL_Pos) /*!< SCU_CLK MLINKCLKCR: WDTSEL Mask */
\r
4532 /* ------------------------------- SCU_CLK_SLEEPCR ------------------------------ */
\r
4533 #define SCU_CLK_SLEEPCR_SYSSEL_Pos 0 /*!< SCU_CLK SLEEPCR: SYSSEL Position */
\r
4534 #define SCU_CLK_SLEEPCR_SYSSEL_Msk (0x01UL << SCU_CLK_SLEEPCR_SYSSEL_Pos) /*!< SCU_CLK SLEEPCR: SYSSEL Mask */
\r
4535 #define SCU_CLK_SLEEPCR_USBCR_Pos 16 /*!< SCU_CLK SLEEPCR: USBCR Position */
\r
4536 #define SCU_CLK_SLEEPCR_USBCR_Msk (0x01UL << SCU_CLK_SLEEPCR_USBCR_Pos) /*!< SCU_CLK SLEEPCR: USBCR Mask */
\r
4537 #define SCU_CLK_SLEEPCR_ETH0CR_Pos 18 /*!< SCU_CLK SLEEPCR: ETH0CR Position */
\r
4538 #define SCU_CLK_SLEEPCR_ETH0CR_Msk (0x01UL << SCU_CLK_SLEEPCR_ETH0CR_Pos) /*!< SCU_CLK SLEEPCR: ETH0CR Mask */
\r
4539 #define SCU_CLK_SLEEPCR_CCUCR_Pos 20 /*!< SCU_CLK SLEEPCR: CCUCR Position */
\r
4540 #define SCU_CLK_SLEEPCR_CCUCR_Msk (0x01UL << SCU_CLK_SLEEPCR_CCUCR_Pos) /*!< SCU_CLK SLEEPCR: CCUCR Mask */
\r
4541 #define SCU_CLK_SLEEPCR_WDTCR_Pos 21 /*!< SCU_CLK SLEEPCR: WDTCR Position */
\r
4542 #define SCU_CLK_SLEEPCR_WDTCR_Msk (0x01UL << SCU_CLK_SLEEPCR_WDTCR_Pos) /*!< SCU_CLK SLEEPCR: WDTCR Mask */
\r
4544 /* ------------------------------ SCU_CLK_DSLEEPCR ------------------------------ */
\r
4545 #define SCU_CLK_DSLEEPCR_SYSSEL_Pos 0 /*!< SCU_CLK DSLEEPCR: SYSSEL Position */
\r
4546 #define SCU_CLK_DSLEEPCR_SYSSEL_Msk (0x01UL << SCU_CLK_DSLEEPCR_SYSSEL_Pos) /*!< SCU_CLK DSLEEPCR: SYSSEL Mask */
\r
4547 #define SCU_CLK_DSLEEPCR_FPDN_Pos 11 /*!< SCU_CLK DSLEEPCR: FPDN Position */
\r
4548 #define SCU_CLK_DSLEEPCR_FPDN_Msk (0x01UL << SCU_CLK_DSLEEPCR_FPDN_Pos) /*!< SCU_CLK DSLEEPCR: FPDN Mask */
\r
4549 #define SCU_CLK_DSLEEPCR_PLLPDN_Pos 12 /*!< SCU_CLK DSLEEPCR: PLLPDN Position */
\r
4550 #define SCU_CLK_DSLEEPCR_PLLPDN_Msk (0x01UL << SCU_CLK_DSLEEPCR_PLLPDN_Pos) /*!< SCU_CLK DSLEEPCR: PLLPDN Mask */
\r
4551 #define SCU_CLK_DSLEEPCR_VCOPDN_Pos 13 /*!< SCU_CLK DSLEEPCR: VCOPDN Position */
\r
4552 #define SCU_CLK_DSLEEPCR_VCOPDN_Msk (0x01UL << SCU_CLK_DSLEEPCR_VCOPDN_Pos) /*!< SCU_CLK DSLEEPCR: VCOPDN Mask */
\r
4553 #define SCU_CLK_DSLEEPCR_USBCR_Pos 16 /*!< SCU_CLK DSLEEPCR: USBCR Position */
\r
4554 #define SCU_CLK_DSLEEPCR_USBCR_Msk (0x01UL << SCU_CLK_DSLEEPCR_USBCR_Pos) /*!< SCU_CLK DSLEEPCR: USBCR Mask */
\r
4555 #define SCU_CLK_DSLEEPCR_ETH0CR_Pos 18 /*!< SCU_CLK DSLEEPCR: ETH0CR Position */
\r
4556 #define SCU_CLK_DSLEEPCR_ETH0CR_Msk (0x01UL << SCU_CLK_DSLEEPCR_ETH0CR_Pos) /*!< SCU_CLK DSLEEPCR: ETH0CR Mask */
\r
4557 #define SCU_CLK_DSLEEPCR_CCUCR_Pos 20 /*!< SCU_CLK DSLEEPCR: CCUCR Position */
\r
4558 #define SCU_CLK_DSLEEPCR_CCUCR_Msk (0x01UL << SCU_CLK_DSLEEPCR_CCUCR_Pos) /*!< SCU_CLK DSLEEPCR: CCUCR Mask */
\r
4559 #define SCU_CLK_DSLEEPCR_WDTCR_Pos 21 /*!< SCU_CLK DSLEEPCR: WDTCR Position */
\r
4560 #define SCU_CLK_DSLEEPCR_WDTCR_Msk (0x01UL << SCU_CLK_DSLEEPCR_WDTCR_Pos) /*!< SCU_CLK DSLEEPCR: WDTCR Mask */
\r
4562 /* ------------------------------ SCU_CLK_CGATSTAT0 ----------------------------- */
\r
4563 #define SCU_CLK_CGATSTAT0_VADC_Pos 0 /*!< SCU_CLK CGATSTAT0: VADC Position */
\r
4564 #define SCU_CLK_CGATSTAT0_VADC_Msk (0x01UL << SCU_CLK_CGATSTAT0_VADC_Pos) /*!< SCU_CLK CGATSTAT0: VADC Mask */
\r
4565 #define SCU_CLK_CGATSTAT0_DSD_Pos 1 /*!< SCU_CLK CGATSTAT0: DSD Position */
\r
4566 #define SCU_CLK_CGATSTAT0_DSD_Msk (0x01UL << SCU_CLK_CGATSTAT0_DSD_Pos) /*!< SCU_CLK CGATSTAT0: DSD Mask */
\r
4567 #define SCU_CLK_CGATSTAT0_CCU40_Pos 2 /*!< SCU_CLK CGATSTAT0: CCU40 Position */
\r
4568 #define SCU_CLK_CGATSTAT0_CCU40_Msk (0x01UL << SCU_CLK_CGATSTAT0_CCU40_Pos) /*!< SCU_CLK CGATSTAT0: CCU40 Mask */
\r
4569 #define SCU_CLK_CGATSTAT0_CCU41_Pos 3 /*!< SCU_CLK CGATSTAT0: CCU41 Position */
\r
4570 #define SCU_CLK_CGATSTAT0_CCU41_Msk (0x01UL << SCU_CLK_CGATSTAT0_CCU41_Pos) /*!< SCU_CLK CGATSTAT0: CCU41 Mask */
\r
4571 #define SCU_CLK_CGATSTAT0_CCU42_Pos 4 /*!< SCU_CLK CGATSTAT0: CCU42 Position */
\r
4572 #define SCU_CLK_CGATSTAT0_CCU42_Msk (0x01UL << SCU_CLK_CGATSTAT0_CCU42_Pos) /*!< SCU_CLK CGATSTAT0: CCU42 Mask */
\r
4573 #define SCU_CLK_CGATSTAT0_CCU80_Pos 7 /*!< SCU_CLK CGATSTAT0: CCU80 Position */
\r
4574 #define SCU_CLK_CGATSTAT0_CCU80_Msk (0x01UL << SCU_CLK_CGATSTAT0_CCU80_Pos) /*!< SCU_CLK CGATSTAT0: CCU80 Mask */
\r
4575 #define SCU_CLK_CGATSTAT0_CCU81_Pos 8 /*!< SCU_CLK CGATSTAT0: CCU81 Position */
\r
4576 #define SCU_CLK_CGATSTAT0_CCU81_Msk (0x01UL << SCU_CLK_CGATSTAT0_CCU81_Pos) /*!< SCU_CLK CGATSTAT0: CCU81 Mask */
\r
4577 #define SCU_CLK_CGATSTAT0_POSIF0_Pos 9 /*!< SCU_CLK CGATSTAT0: POSIF0 Position */
\r
4578 #define SCU_CLK_CGATSTAT0_POSIF0_Msk (0x01UL << SCU_CLK_CGATSTAT0_POSIF0_Pos) /*!< SCU_CLK CGATSTAT0: POSIF0 Mask */
\r
4579 #define SCU_CLK_CGATSTAT0_POSIF1_Pos 10 /*!< SCU_CLK CGATSTAT0: POSIF1 Position */
\r
4580 #define SCU_CLK_CGATSTAT0_POSIF1_Msk (0x01UL << SCU_CLK_CGATSTAT0_POSIF1_Pos) /*!< SCU_CLK CGATSTAT0: POSIF1 Mask */
\r
4581 #define SCU_CLK_CGATSTAT0_USIC0_Pos 11 /*!< SCU_CLK CGATSTAT0: USIC0 Position */
\r
4582 #define SCU_CLK_CGATSTAT0_USIC0_Msk (0x01UL << SCU_CLK_CGATSTAT0_USIC0_Pos) /*!< SCU_CLK CGATSTAT0: USIC0 Mask */
\r
4583 #define SCU_CLK_CGATSTAT0_ERU1_Pos 16 /*!< SCU_CLK CGATSTAT0: ERU1 Position */
\r
4584 #define SCU_CLK_CGATSTAT0_ERU1_Msk (0x01UL << SCU_CLK_CGATSTAT0_ERU1_Pos) /*!< SCU_CLK CGATSTAT0: ERU1 Mask */
\r
4585 #define SCU_CLK_CGATSTAT0_HRPWM0_Pos 23 /*!< SCU_CLK CGATSTAT0: HRPWM0 Position */
\r
4586 #define SCU_CLK_CGATSTAT0_HRPWM0_Msk (0x01UL << SCU_CLK_CGATSTAT0_HRPWM0_Pos) /*!< SCU_CLK CGATSTAT0: HRPWM0 Mask */
\r
4588 /* ------------------------------ SCU_CLK_CGATSET0 ------------------------------ */
\r
4589 #define SCU_CLK_CGATSET0_VADC_Pos 0 /*!< SCU_CLK CGATSET0: VADC Position */
\r
4590 #define SCU_CLK_CGATSET0_VADC_Msk (0x01UL << SCU_CLK_CGATSET0_VADC_Pos) /*!< SCU_CLK CGATSET0: VADC Mask */
\r
4591 #define SCU_CLK_CGATSET0_DSD_Pos 1 /*!< SCU_CLK CGATSET0: DSD Position */
\r
4592 #define SCU_CLK_CGATSET0_DSD_Msk (0x01UL << SCU_CLK_CGATSET0_DSD_Pos) /*!< SCU_CLK CGATSET0: DSD Mask */
\r
4593 #define SCU_CLK_CGATSET0_CCU40_Pos 2 /*!< SCU_CLK CGATSET0: CCU40 Position */
\r
4594 #define SCU_CLK_CGATSET0_CCU40_Msk (0x01UL << SCU_CLK_CGATSET0_CCU40_Pos) /*!< SCU_CLK CGATSET0: CCU40 Mask */
\r
4595 #define SCU_CLK_CGATSET0_CCU41_Pos 3 /*!< SCU_CLK CGATSET0: CCU41 Position */
\r
4596 #define SCU_CLK_CGATSET0_CCU41_Msk (0x01UL << SCU_CLK_CGATSET0_CCU41_Pos) /*!< SCU_CLK CGATSET0: CCU41 Mask */
\r
4597 #define SCU_CLK_CGATSET0_CCU42_Pos 4 /*!< SCU_CLK CGATSET0: CCU42 Position */
\r
4598 #define SCU_CLK_CGATSET0_CCU42_Msk (0x01UL << SCU_CLK_CGATSET0_CCU42_Pos) /*!< SCU_CLK CGATSET0: CCU42 Mask */
\r
4599 #define SCU_CLK_CGATSET0_CCU80_Pos 7 /*!< SCU_CLK CGATSET0: CCU80 Position */
\r
4600 #define SCU_CLK_CGATSET0_CCU80_Msk (0x01UL << SCU_CLK_CGATSET0_CCU80_Pos) /*!< SCU_CLK CGATSET0: CCU80 Mask */
\r
4601 #define SCU_CLK_CGATSET0_CCU81_Pos 8 /*!< SCU_CLK CGATSET0: CCU81 Position */
\r
4602 #define SCU_CLK_CGATSET0_CCU81_Msk (0x01UL << SCU_CLK_CGATSET0_CCU81_Pos) /*!< SCU_CLK CGATSET0: CCU81 Mask */
\r
4603 #define SCU_CLK_CGATSET0_POSIF0_Pos 9 /*!< SCU_CLK CGATSET0: POSIF0 Position */
\r
4604 #define SCU_CLK_CGATSET0_POSIF0_Msk (0x01UL << SCU_CLK_CGATSET0_POSIF0_Pos) /*!< SCU_CLK CGATSET0: POSIF0 Mask */
\r
4605 #define SCU_CLK_CGATSET0_POSIF1_Pos 10 /*!< SCU_CLK CGATSET0: POSIF1 Position */
\r
4606 #define SCU_CLK_CGATSET0_POSIF1_Msk (0x01UL << SCU_CLK_CGATSET0_POSIF1_Pos) /*!< SCU_CLK CGATSET0: POSIF1 Mask */
\r
4607 #define SCU_CLK_CGATSET0_USIC0_Pos 11 /*!< SCU_CLK CGATSET0: USIC0 Position */
\r
4608 #define SCU_CLK_CGATSET0_USIC0_Msk (0x01UL << SCU_CLK_CGATSET0_USIC0_Pos) /*!< SCU_CLK CGATSET0: USIC0 Mask */
\r
4609 #define SCU_CLK_CGATSET0_ERU1_Pos 16 /*!< SCU_CLK CGATSET0: ERU1 Position */
\r
4610 #define SCU_CLK_CGATSET0_ERU1_Msk (0x01UL << SCU_CLK_CGATSET0_ERU1_Pos) /*!< SCU_CLK CGATSET0: ERU1 Mask */
\r
4611 #define SCU_CLK_CGATSET0_HRPWM0_Pos 23 /*!< SCU_CLK CGATSET0: HRPWM0 Position */
\r
4612 #define SCU_CLK_CGATSET0_HRPWM0_Msk (0x01UL << SCU_CLK_CGATSET0_HRPWM0_Pos) /*!< SCU_CLK CGATSET0: HRPWM0 Mask */
\r
4614 /* ------------------------------ SCU_CLK_CGATCLR0 ------------------------------ */
\r
4615 #define SCU_CLK_CGATCLR0_VADC_Pos 0 /*!< SCU_CLK CGATCLR0: VADC Position */
\r
4616 #define SCU_CLK_CGATCLR0_VADC_Msk (0x01UL << SCU_CLK_CGATCLR0_VADC_Pos) /*!< SCU_CLK CGATCLR0: VADC Mask */
\r
4617 #define SCU_CLK_CGATCLR0_DSD_Pos 1 /*!< SCU_CLK CGATCLR0: DSD Position */
\r
4618 #define SCU_CLK_CGATCLR0_DSD_Msk (0x01UL << SCU_CLK_CGATCLR0_DSD_Pos) /*!< SCU_CLK CGATCLR0: DSD Mask */
\r
4619 #define SCU_CLK_CGATCLR0_CCU40_Pos 2 /*!< SCU_CLK CGATCLR0: CCU40 Position */
\r
4620 #define SCU_CLK_CGATCLR0_CCU40_Msk (0x01UL << SCU_CLK_CGATCLR0_CCU40_Pos) /*!< SCU_CLK CGATCLR0: CCU40 Mask */
\r
4621 #define SCU_CLK_CGATCLR0_CCU41_Pos 3 /*!< SCU_CLK CGATCLR0: CCU41 Position */
\r
4622 #define SCU_CLK_CGATCLR0_CCU41_Msk (0x01UL << SCU_CLK_CGATCLR0_CCU41_Pos) /*!< SCU_CLK CGATCLR0: CCU41 Mask */
\r
4623 #define SCU_CLK_CGATCLR0_CCU42_Pos 4 /*!< SCU_CLK CGATCLR0: CCU42 Position */
\r
4624 #define SCU_CLK_CGATCLR0_CCU42_Msk (0x01UL << SCU_CLK_CGATCLR0_CCU42_Pos) /*!< SCU_CLK CGATCLR0: CCU42 Mask */
\r
4625 #define SCU_CLK_CGATCLR0_CCU80_Pos 7 /*!< SCU_CLK CGATCLR0: CCU80 Position */
\r
4626 #define SCU_CLK_CGATCLR0_CCU80_Msk (0x01UL << SCU_CLK_CGATCLR0_CCU80_Pos) /*!< SCU_CLK CGATCLR0: CCU80 Mask */
\r
4627 #define SCU_CLK_CGATCLR0_CCU81_Pos 8 /*!< SCU_CLK CGATCLR0: CCU81 Position */
\r
4628 #define SCU_CLK_CGATCLR0_CCU81_Msk (0x01UL << SCU_CLK_CGATCLR0_CCU81_Pos) /*!< SCU_CLK CGATCLR0: CCU81 Mask */
\r
4629 #define SCU_CLK_CGATCLR0_POSIF0_Pos 9 /*!< SCU_CLK CGATCLR0: POSIF0 Position */
\r
4630 #define SCU_CLK_CGATCLR0_POSIF0_Msk (0x01UL << SCU_CLK_CGATCLR0_POSIF0_Pos) /*!< SCU_CLK CGATCLR0: POSIF0 Mask */
\r
4631 #define SCU_CLK_CGATCLR0_POSIF1_Pos 10 /*!< SCU_CLK CGATCLR0: POSIF1 Position */
\r
4632 #define SCU_CLK_CGATCLR0_POSIF1_Msk (0x01UL << SCU_CLK_CGATCLR0_POSIF1_Pos) /*!< SCU_CLK CGATCLR0: POSIF1 Mask */
\r
4633 #define SCU_CLK_CGATCLR0_USIC0_Pos 11 /*!< SCU_CLK CGATCLR0: USIC0 Position */
\r
4634 #define SCU_CLK_CGATCLR0_USIC0_Msk (0x01UL << SCU_CLK_CGATCLR0_USIC0_Pos) /*!< SCU_CLK CGATCLR0: USIC0 Mask */
\r
4635 #define SCU_CLK_CGATCLR0_ERU1_Pos 16 /*!< SCU_CLK CGATCLR0: ERU1 Position */
\r
4636 #define SCU_CLK_CGATCLR0_ERU1_Msk (0x01UL << SCU_CLK_CGATCLR0_ERU1_Pos) /*!< SCU_CLK CGATCLR0: ERU1 Mask */
\r
4637 #define SCU_CLK_CGATCLR0_HRPWM0_Pos 23 /*!< SCU_CLK CGATCLR0: HRPWM0 Position */
\r
4638 #define SCU_CLK_CGATCLR0_HRPWM0_Msk (0x01UL << SCU_CLK_CGATCLR0_HRPWM0_Pos) /*!< SCU_CLK CGATCLR0: HRPWM0 Mask */
\r
4640 /* ------------------------------ SCU_CLK_CGATSTAT1 ----------------------------- */
\r
4641 #define SCU_CLK_CGATSTAT1_CCU43_Pos 0 /*!< SCU_CLK CGATSTAT1: CCU43 Position */
\r
4642 #define SCU_CLK_CGATSTAT1_CCU43_Msk (0x01UL << SCU_CLK_CGATSTAT1_CCU43_Pos) /*!< SCU_CLK CGATSTAT1: CCU43 Mask */
\r
4643 #define SCU_CLK_CGATSTAT1_LEDTSCU0_Pos 3 /*!< SCU_CLK CGATSTAT1: LEDTSCU0 Position */
\r
4644 #define SCU_CLK_CGATSTAT1_LEDTSCU0_Msk (0x01UL << SCU_CLK_CGATSTAT1_LEDTSCU0_Pos) /*!< SCU_CLK CGATSTAT1: LEDTSCU0 Mask */
\r
4645 #define SCU_CLK_CGATSTAT1_MCAN0_Pos 4 /*!< SCU_CLK CGATSTAT1: MCAN0 Position */
\r
4646 #define SCU_CLK_CGATSTAT1_MCAN0_Msk (0x01UL << SCU_CLK_CGATSTAT1_MCAN0_Pos) /*!< SCU_CLK CGATSTAT1: MCAN0 Mask */
\r
4647 #define SCU_CLK_CGATSTAT1_DAC_Pos 5 /*!< SCU_CLK CGATSTAT1: DAC Position */
\r
4648 #define SCU_CLK_CGATSTAT1_DAC_Msk (0x01UL << SCU_CLK_CGATSTAT1_DAC_Pos) /*!< SCU_CLK CGATSTAT1: DAC Mask */
\r
4649 #define SCU_CLK_CGATSTAT1_USIC1_Pos 7 /*!< SCU_CLK CGATSTAT1: USIC1 Position */
\r
4650 #define SCU_CLK_CGATSTAT1_USIC1_Msk (0x01UL << SCU_CLK_CGATSTAT1_USIC1_Pos) /*!< SCU_CLK CGATSTAT1: USIC1 Mask */
\r
4651 #define SCU_CLK_CGATSTAT1_PPORTS_Pos 9 /*!< SCU_CLK CGATSTAT1: PPORTS Position */
\r
4652 #define SCU_CLK_CGATSTAT1_PPORTS_Msk (0x01UL << SCU_CLK_CGATSTAT1_PPORTS_Pos) /*!< SCU_CLK CGATSTAT1: PPORTS Mask */
\r
4654 /* ------------------------------ SCU_CLK_CGATSET1 ------------------------------ */
\r
4655 #define SCU_CLK_CGATSET1_CCU43_Pos 0 /*!< SCU_CLK CGATSET1: CCU43 Position */
\r
4656 #define SCU_CLK_CGATSET1_CCU43_Msk (0x01UL << SCU_CLK_CGATSET1_CCU43_Pos) /*!< SCU_CLK CGATSET1: CCU43 Mask */
\r
4657 #define SCU_CLK_CGATSET1_LEDTSCU0_Pos 3 /*!< SCU_CLK CGATSET1: LEDTSCU0 Position */
\r
4658 #define SCU_CLK_CGATSET1_LEDTSCU0_Msk (0x01UL << SCU_CLK_CGATSET1_LEDTSCU0_Pos) /*!< SCU_CLK CGATSET1: LEDTSCU0 Mask */
\r
4659 #define SCU_CLK_CGATSET1_MCAN0_Pos 4 /*!< SCU_CLK CGATSET1: MCAN0 Position */
\r
4660 #define SCU_CLK_CGATSET1_MCAN0_Msk (0x01UL << SCU_CLK_CGATSET1_MCAN0_Pos) /*!< SCU_CLK CGATSET1: MCAN0 Mask */
\r
4661 #define SCU_CLK_CGATSET1_DAC_Pos 5 /*!< SCU_CLK CGATSET1: DAC Position */
\r
4662 #define SCU_CLK_CGATSET1_DAC_Msk (0x01UL << SCU_CLK_CGATSET1_DAC_Pos) /*!< SCU_CLK CGATSET1: DAC Mask */
\r
4663 #define SCU_CLK_CGATSET1_USIC1_Pos 7 /*!< SCU_CLK CGATSET1: USIC1 Position */
\r
4664 #define SCU_CLK_CGATSET1_USIC1_Msk (0x01UL << SCU_CLK_CGATSET1_USIC1_Pos) /*!< SCU_CLK CGATSET1: USIC1 Mask */
\r
4665 #define SCU_CLK_CGATSET1_PPORTS_Pos 9 /*!< SCU_CLK CGATSET1: PPORTS Position */
\r
4666 #define SCU_CLK_CGATSET1_PPORTS_Msk (0x01UL << SCU_CLK_CGATSET1_PPORTS_Pos) /*!< SCU_CLK CGATSET1: PPORTS Mask */
\r
4668 /* ------------------------------ SCU_CLK_CGATCLR1 ------------------------------ */
\r
4669 #define SCU_CLK_CGATCLR1_CCU43_Pos 0 /*!< SCU_CLK CGATCLR1: CCU43 Position */
\r
4670 #define SCU_CLK_CGATCLR1_CCU43_Msk (0x01UL << SCU_CLK_CGATCLR1_CCU43_Pos) /*!< SCU_CLK CGATCLR1: CCU43 Mask */
\r
4671 #define SCU_CLK_CGATCLR1_LEDTSCU0_Pos 3 /*!< SCU_CLK CGATCLR1: LEDTSCU0 Position */
\r
4672 #define SCU_CLK_CGATCLR1_LEDTSCU0_Msk (0x01UL << SCU_CLK_CGATCLR1_LEDTSCU0_Pos) /*!< SCU_CLK CGATCLR1: LEDTSCU0 Mask */
\r
4673 #define SCU_CLK_CGATCLR1_MCAN0_Pos 4 /*!< SCU_CLK CGATCLR1: MCAN0 Position */
\r
4674 #define SCU_CLK_CGATCLR1_MCAN0_Msk (0x01UL << SCU_CLK_CGATCLR1_MCAN0_Pos) /*!< SCU_CLK CGATCLR1: MCAN0 Mask */
\r
4675 #define SCU_CLK_CGATCLR1_DAC_Pos 5 /*!< SCU_CLK CGATCLR1: DAC Position */
\r
4676 #define SCU_CLK_CGATCLR1_DAC_Msk (0x01UL << SCU_CLK_CGATCLR1_DAC_Pos) /*!< SCU_CLK CGATCLR1: DAC Mask */
\r
4677 #define SCU_CLK_CGATCLR1_USIC1_Pos 7 /*!< SCU_CLK CGATCLR1: USIC1 Position */
\r
4678 #define SCU_CLK_CGATCLR1_USIC1_Msk (0x01UL << SCU_CLK_CGATCLR1_USIC1_Pos) /*!< SCU_CLK CGATCLR1: USIC1 Mask */
\r
4679 #define SCU_CLK_CGATCLR1_PPORTS_Pos 9 /*!< SCU_CLK CGATCLR1: PPORTS Position */
\r
4680 #define SCU_CLK_CGATCLR1_PPORTS_Msk (0x01UL << SCU_CLK_CGATCLR1_PPORTS_Pos) /*!< SCU_CLK CGATCLR1: PPORTS Mask */
\r
4682 /* ------------------------------ SCU_CLK_CGATSTAT2 ----------------------------- */
\r
4683 #define SCU_CLK_CGATSTAT2_WDT_Pos 1 /*!< SCU_CLK CGATSTAT2: WDT Position */
\r
4684 #define SCU_CLK_CGATSTAT2_WDT_Msk (0x01UL << SCU_CLK_CGATSTAT2_WDT_Pos) /*!< SCU_CLK CGATSTAT2: WDT Mask */
\r
4685 #define SCU_CLK_CGATSTAT2_ETH0_Pos 2 /*!< SCU_CLK CGATSTAT2: ETH0 Position */
\r
4686 #define SCU_CLK_CGATSTAT2_ETH0_Msk (0x01UL << SCU_CLK_CGATSTAT2_ETH0_Pos) /*!< SCU_CLK CGATSTAT2: ETH0 Mask */
\r
4687 #define SCU_CLK_CGATSTAT2_DMA0_Pos 4 /*!< SCU_CLK CGATSTAT2: DMA0 Position */
\r
4688 #define SCU_CLK_CGATSTAT2_DMA0_Msk (0x01UL << SCU_CLK_CGATSTAT2_DMA0_Pos) /*!< SCU_CLK CGATSTAT2: DMA0 Mask */
\r
4689 #define SCU_CLK_CGATSTAT2_FCE_Pos 6 /*!< SCU_CLK CGATSTAT2: FCE Position */
\r
4690 #define SCU_CLK_CGATSTAT2_FCE_Msk (0x01UL << SCU_CLK_CGATSTAT2_FCE_Pos) /*!< SCU_CLK CGATSTAT2: FCE Mask */
\r
4691 #define SCU_CLK_CGATSTAT2_USB_Pos 7 /*!< SCU_CLK CGATSTAT2: USB Position */
\r
4692 #define SCU_CLK_CGATSTAT2_USB_Msk (0x01UL << SCU_CLK_CGATSTAT2_USB_Pos) /*!< SCU_CLK CGATSTAT2: USB Mask */
\r
4694 /* ------------------------------ SCU_CLK_CGATSET2 ------------------------------ */
\r
4695 #define SCU_CLK_CGATSET2_WDT_Pos 1 /*!< SCU_CLK CGATSET2: WDT Position */
\r
4696 #define SCU_CLK_CGATSET2_WDT_Msk (0x01UL << SCU_CLK_CGATSET2_WDT_Pos) /*!< SCU_CLK CGATSET2: WDT Mask */
\r
4697 #define SCU_CLK_CGATSET2_ETH0_Pos 2 /*!< SCU_CLK CGATSET2: ETH0 Position */
\r
4698 #define SCU_CLK_CGATSET2_ETH0_Msk (0x01UL << SCU_CLK_CGATSET2_ETH0_Pos) /*!< SCU_CLK CGATSET2: ETH0 Mask */
\r
4699 #define SCU_CLK_CGATSET2_DMA0_Pos 4 /*!< SCU_CLK CGATSET2: DMA0 Position */
\r
4700 #define SCU_CLK_CGATSET2_DMA0_Msk (0x01UL << SCU_CLK_CGATSET2_DMA0_Pos) /*!< SCU_CLK CGATSET2: DMA0 Mask */
\r
4701 #define SCU_CLK_CGATSET2_FCE_Pos 6 /*!< SCU_CLK CGATSET2: FCE Position */
\r
4702 #define SCU_CLK_CGATSET2_FCE_Msk (0x01UL << SCU_CLK_CGATSET2_FCE_Pos) /*!< SCU_CLK CGATSET2: FCE Mask */
\r
4703 #define SCU_CLK_CGATSET2_USB_Pos 7 /*!< SCU_CLK CGATSET2: USB Position */
\r
4704 #define SCU_CLK_CGATSET2_USB_Msk (0x01UL << SCU_CLK_CGATSET2_USB_Pos) /*!< SCU_CLK CGATSET2: USB Mask */
\r
4706 /* ------------------------------ SCU_CLK_CGATCLR2 ------------------------------ */
\r
4707 #define SCU_CLK_CGATCLR2_WDT_Pos 1 /*!< SCU_CLK CGATCLR2: WDT Position */
\r
4708 #define SCU_CLK_CGATCLR2_WDT_Msk (0x01UL << SCU_CLK_CGATCLR2_WDT_Pos) /*!< SCU_CLK CGATCLR2: WDT Mask */
\r
4709 #define SCU_CLK_CGATCLR2_ETH0_Pos 2 /*!< SCU_CLK CGATCLR2: ETH0 Position */
\r
4710 #define SCU_CLK_CGATCLR2_ETH0_Msk (0x01UL << SCU_CLK_CGATCLR2_ETH0_Pos) /*!< SCU_CLK CGATCLR2: ETH0 Mask */
\r
4711 #define SCU_CLK_CGATCLR2_DMA0_Pos 4 /*!< SCU_CLK CGATCLR2: DMA0 Position */
\r
4712 #define SCU_CLK_CGATCLR2_DMA0_Msk (0x01UL << SCU_CLK_CGATCLR2_DMA0_Pos) /*!< SCU_CLK CGATCLR2: DMA0 Mask */
\r
4713 #define SCU_CLK_CGATCLR2_FCE_Pos 6 /*!< SCU_CLK CGATCLR2: FCE Position */
\r
4714 #define SCU_CLK_CGATCLR2_FCE_Msk (0x01UL << SCU_CLK_CGATCLR2_FCE_Pos) /*!< SCU_CLK CGATCLR2: FCE Mask */
\r
4715 #define SCU_CLK_CGATCLR2_USB_Pos 7 /*!< SCU_CLK CGATCLR2: USB Position */
\r
4716 #define SCU_CLK_CGATCLR2_USB_Msk (0x01UL << SCU_CLK_CGATCLR2_USB_Pos) /*!< SCU_CLK CGATCLR2: USB Mask */
\r
4719 /* ================================================================================ */
\r
4720 /* ================ struct 'SCU_OSC' Position & Mask ================ */
\r
4721 /* ================================================================================ */
\r
4724 /* ------------------------------ SCU_OSC_OSCHPSTAT ----------------------------- */
\r
4725 #define SCU_OSC_OSCHPSTAT_X1D_Pos 0 /*!< SCU_OSC OSCHPSTAT: X1D Position */
\r
4726 #define SCU_OSC_OSCHPSTAT_X1D_Msk (0x01UL << SCU_OSC_OSCHPSTAT_X1D_Pos) /*!< SCU_OSC OSCHPSTAT: X1D Mask */
\r
4728 /* ------------------------------ SCU_OSC_OSCHPCTRL ----------------------------- */
\r
4729 #define SCU_OSC_OSCHPCTRL_X1DEN_Pos 0 /*!< SCU_OSC OSCHPCTRL: X1DEN Position */
\r
4730 #define SCU_OSC_OSCHPCTRL_X1DEN_Msk (0x01UL << SCU_OSC_OSCHPCTRL_X1DEN_Pos) /*!< SCU_OSC OSCHPCTRL: X1DEN Mask */
\r
4731 #define SCU_OSC_OSCHPCTRL_SHBY_Pos 1 /*!< SCU_OSC OSCHPCTRL: SHBY Position */
\r
4732 #define SCU_OSC_OSCHPCTRL_SHBY_Msk (0x01UL << SCU_OSC_OSCHPCTRL_SHBY_Pos) /*!< SCU_OSC OSCHPCTRL: SHBY Mask */
\r
4733 #define SCU_OSC_OSCHPCTRL_MODE_Pos 4 /*!< SCU_OSC OSCHPCTRL: MODE Position */
\r
4734 #define SCU_OSC_OSCHPCTRL_MODE_Msk (0x03UL << SCU_OSC_OSCHPCTRL_MODE_Pos) /*!< SCU_OSC OSCHPCTRL: MODE Mask */
\r
4735 #define SCU_OSC_OSCHPCTRL_OSCVAL_Pos 16 /*!< SCU_OSC OSCHPCTRL: OSCVAL Position */
\r
4736 #define SCU_OSC_OSCHPCTRL_OSCVAL_Msk (0x1fUL << SCU_OSC_OSCHPCTRL_OSCVAL_Pos) /*!< SCU_OSC OSCHPCTRL: OSCVAL Mask */
\r
4738 /* ----------------------------- SCU_OSC_CLKCALCONST ---------------------------- */
\r
4739 #define SCU_OSC_CLKCALCONST_CALIBCONST_Pos 0 /*!< SCU_OSC CLKCALCONST: CALIBCONST Position */
\r
4740 #define SCU_OSC_CLKCALCONST_CALIBCONST_Msk (0x0fUL << SCU_OSC_CLKCALCONST_CALIBCONST_Pos) /*!< SCU_OSC CLKCALCONST: CALIBCONST Mask */
\r
4743 /* ================================================================================ */
\r
4744 /* ================ struct 'SCU_PLL' Position & Mask ================ */
\r
4745 /* ================================================================================ */
\r
4748 /* ------------------------------- SCU_PLL_PLLSTAT ------------------------------ */
\r
4749 #define SCU_PLL_PLLSTAT_VCOBYST_Pos 0 /*!< SCU_PLL PLLSTAT: VCOBYST Position */
\r
4750 #define SCU_PLL_PLLSTAT_VCOBYST_Msk (0x01UL << SCU_PLL_PLLSTAT_VCOBYST_Pos) /*!< SCU_PLL PLLSTAT: VCOBYST Mask */
\r
4751 #define SCU_PLL_PLLSTAT_PWDSTAT_Pos 1 /*!< SCU_PLL PLLSTAT: PWDSTAT Position */
\r
4752 #define SCU_PLL_PLLSTAT_PWDSTAT_Msk (0x01UL << SCU_PLL_PLLSTAT_PWDSTAT_Pos) /*!< SCU_PLL PLLSTAT: PWDSTAT Mask */
\r
4753 #define SCU_PLL_PLLSTAT_VCOLOCK_Pos 2 /*!< SCU_PLL PLLSTAT: VCOLOCK Position */
\r
4754 #define SCU_PLL_PLLSTAT_VCOLOCK_Msk (0x01UL << SCU_PLL_PLLSTAT_VCOLOCK_Pos) /*!< SCU_PLL PLLSTAT: VCOLOCK Mask */
\r
4755 #define SCU_PLL_PLLSTAT_K1RDY_Pos 4 /*!< SCU_PLL PLLSTAT: K1RDY Position */
\r
4756 #define SCU_PLL_PLLSTAT_K1RDY_Msk (0x01UL << SCU_PLL_PLLSTAT_K1RDY_Pos) /*!< SCU_PLL PLLSTAT: K1RDY Mask */
\r
4757 #define SCU_PLL_PLLSTAT_K2RDY_Pos 5 /*!< SCU_PLL PLLSTAT: K2RDY Position */
\r
4758 #define SCU_PLL_PLLSTAT_K2RDY_Msk (0x01UL << SCU_PLL_PLLSTAT_K2RDY_Pos) /*!< SCU_PLL PLLSTAT: K2RDY Mask */
\r
4759 #define SCU_PLL_PLLSTAT_BY_Pos 6 /*!< SCU_PLL PLLSTAT: BY Position */
\r
4760 #define SCU_PLL_PLLSTAT_BY_Msk (0x01UL << SCU_PLL_PLLSTAT_BY_Pos) /*!< SCU_PLL PLLSTAT: BY Mask */
\r
4761 #define SCU_PLL_PLLSTAT_PLLLV_Pos 7 /*!< SCU_PLL PLLSTAT: PLLLV Position */
\r
4762 #define SCU_PLL_PLLSTAT_PLLLV_Msk (0x01UL << SCU_PLL_PLLSTAT_PLLLV_Pos) /*!< SCU_PLL PLLSTAT: PLLLV Mask */
\r
4763 #define SCU_PLL_PLLSTAT_PLLHV_Pos 8 /*!< SCU_PLL PLLSTAT: PLLHV Position */
\r
4764 #define SCU_PLL_PLLSTAT_PLLHV_Msk (0x01UL << SCU_PLL_PLLSTAT_PLLHV_Pos) /*!< SCU_PLL PLLSTAT: PLLHV Mask */
\r
4765 #define SCU_PLL_PLLSTAT_PLLSP_Pos 9 /*!< SCU_PLL PLLSTAT: PLLSP Position */
\r
4766 #define SCU_PLL_PLLSTAT_PLLSP_Msk (0x01UL << SCU_PLL_PLLSTAT_PLLSP_Pos) /*!< SCU_PLL PLLSTAT: PLLSP Mask */
\r
4768 /* ------------------------------- SCU_PLL_PLLCON0 ------------------------------ */
\r
4769 #define SCU_PLL_PLLCON0_VCOBYP_Pos 0 /*!< SCU_PLL PLLCON0: VCOBYP Position */
\r
4770 #define SCU_PLL_PLLCON0_VCOBYP_Msk (0x01UL << SCU_PLL_PLLCON0_VCOBYP_Pos) /*!< SCU_PLL PLLCON0: VCOBYP Mask */
\r
4771 #define SCU_PLL_PLLCON0_VCOPWD_Pos 1 /*!< SCU_PLL PLLCON0: VCOPWD Position */
\r
4772 #define SCU_PLL_PLLCON0_VCOPWD_Msk (0x01UL << SCU_PLL_PLLCON0_VCOPWD_Pos) /*!< SCU_PLL PLLCON0: VCOPWD Mask */
\r
4773 #define SCU_PLL_PLLCON0_VCOTR_Pos 2 /*!< SCU_PLL PLLCON0: VCOTR Position */
\r
4774 #define SCU_PLL_PLLCON0_VCOTR_Msk (0x01UL << SCU_PLL_PLLCON0_VCOTR_Pos) /*!< SCU_PLL PLLCON0: VCOTR Mask */
\r
4775 #define SCU_PLL_PLLCON0_FINDIS_Pos 4 /*!< SCU_PLL PLLCON0: FINDIS Position */
\r
4776 #define SCU_PLL_PLLCON0_FINDIS_Msk (0x01UL << SCU_PLL_PLLCON0_FINDIS_Pos) /*!< SCU_PLL PLLCON0: FINDIS Mask */
\r
4777 #define SCU_PLL_PLLCON0_OSCDISCDIS_Pos 6 /*!< SCU_PLL PLLCON0: OSCDISCDIS Position */
\r
4778 #define SCU_PLL_PLLCON0_OSCDISCDIS_Msk (0x01UL << SCU_PLL_PLLCON0_OSCDISCDIS_Pos) /*!< SCU_PLL PLLCON0: OSCDISCDIS Mask */
\r
4779 #define SCU_PLL_PLLCON0_PLLPWD_Pos 16 /*!< SCU_PLL PLLCON0: PLLPWD Position */
\r
4780 #define SCU_PLL_PLLCON0_PLLPWD_Msk (0x01UL << SCU_PLL_PLLCON0_PLLPWD_Pos) /*!< SCU_PLL PLLCON0: PLLPWD Mask */
\r
4781 #define SCU_PLL_PLLCON0_OSCRES_Pos 17 /*!< SCU_PLL PLLCON0: OSCRES Position */
\r
4782 #define SCU_PLL_PLLCON0_OSCRES_Msk (0x01UL << SCU_PLL_PLLCON0_OSCRES_Pos) /*!< SCU_PLL PLLCON0: OSCRES Mask */
\r
4783 #define SCU_PLL_PLLCON0_RESLD_Pos 18 /*!< SCU_PLL PLLCON0: RESLD Position */
\r
4784 #define SCU_PLL_PLLCON0_RESLD_Msk (0x01UL << SCU_PLL_PLLCON0_RESLD_Pos) /*!< SCU_PLL PLLCON0: RESLD Mask */
\r
4785 #define SCU_PLL_PLLCON0_AOTREN_Pos 19 /*!< SCU_PLL PLLCON0: AOTREN Position */
\r
4786 #define SCU_PLL_PLLCON0_AOTREN_Msk (0x01UL << SCU_PLL_PLLCON0_AOTREN_Pos) /*!< SCU_PLL PLLCON0: AOTREN Mask */
\r
4787 #define SCU_PLL_PLLCON0_FOTR_Pos 20 /*!< SCU_PLL PLLCON0: FOTR Position */
\r
4788 #define SCU_PLL_PLLCON0_FOTR_Msk (0x01UL << SCU_PLL_PLLCON0_FOTR_Pos) /*!< SCU_PLL PLLCON0: FOTR Mask */
\r
4790 /* ------------------------------- SCU_PLL_PLLCON1 ------------------------------ */
\r
4791 #define SCU_PLL_PLLCON1_K1DIV_Pos 0 /*!< SCU_PLL PLLCON1: K1DIV Position */
\r
4792 #define SCU_PLL_PLLCON1_K1DIV_Msk (0x7fUL << SCU_PLL_PLLCON1_K1DIV_Pos) /*!< SCU_PLL PLLCON1: K1DIV Mask */
\r
4793 #define SCU_PLL_PLLCON1_NDIV_Pos 8 /*!< SCU_PLL PLLCON1: NDIV Position */
\r
4794 #define SCU_PLL_PLLCON1_NDIV_Msk (0x7fUL << SCU_PLL_PLLCON1_NDIV_Pos) /*!< SCU_PLL PLLCON1: NDIV Mask */
\r
4795 #define SCU_PLL_PLLCON1_K2DIV_Pos 16 /*!< SCU_PLL PLLCON1: K2DIV Position */
\r
4796 #define SCU_PLL_PLLCON1_K2DIV_Msk (0x7fUL << SCU_PLL_PLLCON1_K2DIV_Pos) /*!< SCU_PLL PLLCON1: K2DIV Mask */
\r
4797 #define SCU_PLL_PLLCON1_PDIV_Pos 24 /*!< SCU_PLL PLLCON1: PDIV Position */
\r
4798 #define SCU_PLL_PLLCON1_PDIV_Msk (0x0fUL << SCU_PLL_PLLCON1_PDIV_Pos) /*!< SCU_PLL PLLCON1: PDIV Mask */
\r
4800 /* ------------------------------- SCU_PLL_PLLCON2 ------------------------------ */
\r
4801 #define SCU_PLL_PLLCON2_PINSEL_Pos 0 /*!< SCU_PLL PLLCON2: PINSEL Position */
\r
4802 #define SCU_PLL_PLLCON2_PINSEL_Msk (0x01UL << SCU_PLL_PLLCON2_PINSEL_Pos) /*!< SCU_PLL PLLCON2: PINSEL Mask */
\r
4803 #define SCU_PLL_PLLCON2_K1INSEL_Pos 8 /*!< SCU_PLL PLLCON2: K1INSEL Position */
\r
4804 #define SCU_PLL_PLLCON2_K1INSEL_Msk (0x01UL << SCU_PLL_PLLCON2_K1INSEL_Pos) /*!< SCU_PLL PLLCON2: K1INSEL Mask */
\r
4806 /* ----------------------------- SCU_PLL_USBPLLSTAT ----------------------------- */
\r
4807 #define SCU_PLL_USBPLLSTAT_VCOBYST_Pos 0 /*!< SCU_PLL USBPLLSTAT: VCOBYST Position */
\r
4808 #define SCU_PLL_USBPLLSTAT_VCOBYST_Msk (0x01UL << SCU_PLL_USBPLLSTAT_VCOBYST_Pos) /*!< SCU_PLL USBPLLSTAT: VCOBYST Mask */
\r
4809 #define SCU_PLL_USBPLLSTAT_PWDSTAT_Pos 1 /*!< SCU_PLL USBPLLSTAT: PWDSTAT Position */
\r
4810 #define SCU_PLL_USBPLLSTAT_PWDSTAT_Msk (0x01UL << SCU_PLL_USBPLLSTAT_PWDSTAT_Pos) /*!< SCU_PLL USBPLLSTAT: PWDSTAT Mask */
\r
4811 #define SCU_PLL_USBPLLSTAT_VCOLOCK_Pos 2 /*!< SCU_PLL USBPLLSTAT: VCOLOCK Position */
\r
4812 #define SCU_PLL_USBPLLSTAT_VCOLOCK_Msk (0x01UL << SCU_PLL_USBPLLSTAT_VCOLOCK_Pos) /*!< SCU_PLL USBPLLSTAT: VCOLOCK Mask */
\r
4813 #define SCU_PLL_USBPLLSTAT_BY_Pos 6 /*!< SCU_PLL USBPLLSTAT: BY Position */
\r
4814 #define SCU_PLL_USBPLLSTAT_BY_Msk (0x01UL << SCU_PLL_USBPLLSTAT_BY_Pos) /*!< SCU_PLL USBPLLSTAT: BY Mask */
\r
4815 #define SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos 7 /*!< SCU_PLL USBPLLSTAT: VCOLOCKED Position */
\r
4816 #define SCU_PLL_USBPLLSTAT_VCOLOCKED_Msk (0x01UL << SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos) /*!< SCU_PLL USBPLLSTAT: VCOLOCKED Mask */
\r
4818 /* ------------------------------ SCU_PLL_USBPLLCON ----------------------------- */
\r
4819 #define SCU_PLL_USBPLLCON_VCOBYP_Pos 0 /*!< SCU_PLL USBPLLCON: VCOBYP Position */
\r
4820 #define SCU_PLL_USBPLLCON_VCOBYP_Msk (0x01UL << SCU_PLL_USBPLLCON_VCOBYP_Pos) /*!< SCU_PLL USBPLLCON: VCOBYP Mask */
\r
4821 #define SCU_PLL_USBPLLCON_VCOPWD_Pos 1 /*!< SCU_PLL USBPLLCON: VCOPWD Position */
\r
4822 #define SCU_PLL_USBPLLCON_VCOPWD_Msk (0x01UL << SCU_PLL_USBPLLCON_VCOPWD_Pos) /*!< SCU_PLL USBPLLCON: VCOPWD Mask */
\r
4823 #define SCU_PLL_USBPLLCON_VCOTR_Pos 2 /*!< SCU_PLL USBPLLCON: VCOTR Position */
\r
4824 #define SCU_PLL_USBPLLCON_VCOTR_Msk (0x01UL << SCU_PLL_USBPLLCON_VCOTR_Pos) /*!< SCU_PLL USBPLLCON: VCOTR Mask */
\r
4825 #define SCU_PLL_USBPLLCON_FINDIS_Pos 4 /*!< SCU_PLL USBPLLCON: FINDIS Position */
\r
4826 #define SCU_PLL_USBPLLCON_FINDIS_Msk (0x01UL << SCU_PLL_USBPLLCON_FINDIS_Pos) /*!< SCU_PLL USBPLLCON: FINDIS Mask */
\r
4827 #define SCU_PLL_USBPLLCON_OSCDISCDIS_Pos 6 /*!< SCU_PLL USBPLLCON: OSCDISCDIS Position */
\r
4828 #define SCU_PLL_USBPLLCON_OSCDISCDIS_Msk (0x01UL << SCU_PLL_USBPLLCON_OSCDISCDIS_Pos) /*!< SCU_PLL USBPLLCON: OSCDISCDIS Mask */
\r
4829 #define SCU_PLL_USBPLLCON_NDIV_Pos 8 /*!< SCU_PLL USBPLLCON: NDIV Position */
\r
4830 #define SCU_PLL_USBPLLCON_NDIV_Msk (0x7fUL << SCU_PLL_USBPLLCON_NDIV_Pos) /*!< SCU_PLL USBPLLCON: NDIV Mask */
\r
4831 #define SCU_PLL_USBPLLCON_PLLPWD_Pos 16 /*!< SCU_PLL USBPLLCON: PLLPWD Position */
\r
4832 #define SCU_PLL_USBPLLCON_PLLPWD_Msk (0x01UL << SCU_PLL_USBPLLCON_PLLPWD_Pos) /*!< SCU_PLL USBPLLCON: PLLPWD Mask */
\r
4833 #define SCU_PLL_USBPLLCON_RESLD_Pos 18 /*!< SCU_PLL USBPLLCON: RESLD Position */
\r
4834 #define SCU_PLL_USBPLLCON_RESLD_Msk (0x01UL << SCU_PLL_USBPLLCON_RESLD_Pos) /*!< SCU_PLL USBPLLCON: RESLD Mask */
\r
4835 #define SCU_PLL_USBPLLCON_PDIV_Pos 24 /*!< SCU_PLL USBPLLCON: PDIV Position */
\r
4836 #define SCU_PLL_USBPLLCON_PDIV_Msk (0x0fUL << SCU_PLL_USBPLLCON_PDIV_Pos) /*!< SCU_PLL USBPLLCON: PDIV Mask */
\r
4838 /* ------------------------------ SCU_PLL_CLKMXSTAT ----------------------------- */
\r
4839 #define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos 0 /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX Position */
\r
4840 #define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Msk (0x03UL << SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos) /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX Mask */
\r
4843 /* ================================================================================ */
\r
4844 /* ================ struct 'SCU_GENERAL' Position & Mask ================ */
\r
4845 /* ================================================================================ */
\r
4848 /* ------------------------------- SCU_GENERAL_ID ------------------------------- */
\r
4849 #define SCU_GENERAL_ID_MOD_REV_Pos 0 /*!< SCU_GENERAL ID: MOD_REV Position */
\r
4850 #define SCU_GENERAL_ID_MOD_REV_Msk (0x000000ffUL << SCU_GENERAL_ID_MOD_REV_Pos) /*!< SCU_GENERAL ID: MOD_REV Mask */
\r
4851 #define SCU_GENERAL_ID_MOD_TYPE_Pos 8 /*!< SCU_GENERAL ID: MOD_TYPE Position */
\r
4852 #define SCU_GENERAL_ID_MOD_TYPE_Msk (0x000000ffUL << SCU_GENERAL_ID_MOD_TYPE_Pos) /*!< SCU_GENERAL ID: MOD_TYPE Mask */
\r
4853 #define SCU_GENERAL_ID_MOD_NUMBER_Pos 16 /*!< SCU_GENERAL ID: MOD_NUMBER Position */
\r
4854 #define SCU_GENERAL_ID_MOD_NUMBER_Msk (0x0000ffffUL << SCU_GENERAL_ID_MOD_NUMBER_Pos) /*!< SCU_GENERAL ID: MOD_NUMBER Mask */
\r
4856 /* ----------------------------- SCU_GENERAL_IDCHIP ----------------------------- */
\r
4857 #define SCU_GENERAL_IDCHIP_IDCHIP_Pos 0 /*!< SCU_GENERAL IDCHIP: IDCHIP Position */
\r
4858 #define SCU_GENERAL_IDCHIP_IDCHIP_Msk (0xffffffffUL << SCU_GENERAL_IDCHIP_IDCHIP_Pos) /*!< SCU_GENERAL IDCHIP: IDCHIP Mask */
\r
4860 /* ----------------------------- SCU_GENERAL_IDMANUF ---------------------------- */
\r
4861 #define SCU_GENERAL_IDMANUF_DEPT_Pos 0 /*!< SCU_GENERAL IDMANUF: DEPT Position */
\r
4862 #define SCU_GENERAL_IDMANUF_DEPT_Msk (0x1fUL << SCU_GENERAL_IDMANUF_DEPT_Pos) /*!< SCU_GENERAL IDMANUF: DEPT Mask */
\r
4863 #define SCU_GENERAL_IDMANUF_MANUF_Pos 5 /*!< SCU_GENERAL IDMANUF: MANUF Position */
\r
4864 #define SCU_GENERAL_IDMANUF_MANUF_Msk (0x000007ffUL << SCU_GENERAL_IDMANUF_MANUF_Pos) /*!< SCU_GENERAL IDMANUF: MANUF Mask */
\r
4866 /* ------------------------------ SCU_GENERAL_STCON ----------------------------- */
\r
4867 #define SCU_GENERAL_STCON_HWCON_Pos 0 /*!< SCU_GENERAL STCON: HWCON Position */
\r
4868 #define SCU_GENERAL_STCON_HWCON_Msk (0x03UL << SCU_GENERAL_STCON_HWCON_Pos) /*!< SCU_GENERAL STCON: HWCON Mask */
\r
4869 #define SCU_GENERAL_STCON_SWCON_Pos 8 /*!< SCU_GENERAL STCON: SWCON Position */
\r
4870 #define SCU_GENERAL_STCON_SWCON_Msk (0x0fUL << SCU_GENERAL_STCON_SWCON_Pos) /*!< SCU_GENERAL STCON: SWCON Mask */
\r
4872 /* ------------------------------- SCU_GENERAL_GPR ------------------------------ */
\r
4873 #define SCU_GENERAL_GPR_DAT_Pos 0 /*!< SCU_GENERAL GPR: DAT Position */
\r
4874 #define SCU_GENERAL_GPR_DAT_Msk (0xffffffffUL << SCU_GENERAL_GPR_DAT_Pos) /*!< SCU_GENERAL GPR: DAT Mask */
\r
4876 /* ----------------------------- SCU_GENERAL_CCUCON ----------------------------- */
\r
4877 #define SCU_GENERAL_CCUCON_GSC40_Pos 0 /*!< SCU_GENERAL CCUCON: GSC40 Position */
\r
4878 #define SCU_GENERAL_CCUCON_GSC40_Msk (0x01UL << SCU_GENERAL_CCUCON_GSC40_Pos) /*!< SCU_GENERAL CCUCON: GSC40 Mask */
\r
4879 #define SCU_GENERAL_CCUCON_GSC41_Pos 1 /*!< SCU_GENERAL CCUCON: GSC41 Position */
\r
4880 #define SCU_GENERAL_CCUCON_GSC41_Msk (0x01UL << SCU_GENERAL_CCUCON_GSC41_Pos) /*!< SCU_GENERAL CCUCON: GSC41 Mask */
\r
4881 #define SCU_GENERAL_CCUCON_GSC42_Pos 2 /*!< SCU_GENERAL CCUCON: GSC42 Position */
\r
4882 #define SCU_GENERAL_CCUCON_GSC42_Msk (0x01UL << SCU_GENERAL_CCUCON_GSC42_Pos) /*!< SCU_GENERAL CCUCON: GSC42 Mask */
\r
4883 #define SCU_GENERAL_CCUCON_GSC43_Pos 3 /*!< SCU_GENERAL CCUCON: GSC43 Position */
\r
4884 #define SCU_GENERAL_CCUCON_GSC43_Msk (0x01UL << SCU_GENERAL_CCUCON_GSC43_Pos) /*!< SCU_GENERAL CCUCON: GSC43 Mask */
\r
4885 #define SCU_GENERAL_CCUCON_GSC80_Pos 8 /*!< SCU_GENERAL CCUCON: GSC80 Position */
\r
4886 #define SCU_GENERAL_CCUCON_GSC80_Msk (0x01UL << SCU_GENERAL_CCUCON_GSC80_Pos) /*!< SCU_GENERAL CCUCON: GSC80 Mask */
\r
4887 #define SCU_GENERAL_CCUCON_GSC81_Pos 9 /*!< SCU_GENERAL CCUCON: GSC81 Position */
\r
4888 #define SCU_GENERAL_CCUCON_GSC81_Msk (0x01UL << SCU_GENERAL_CCUCON_GSC81_Pos) /*!< SCU_GENERAL CCUCON: GSC81 Mask */
\r
4889 #define SCU_GENERAL_CCUCON_GSHR0_Pos 24 /*!< SCU_GENERAL CCUCON: GSHR0 Position */
\r
4890 #define SCU_GENERAL_CCUCON_GSHR0_Msk (0x01UL << SCU_GENERAL_CCUCON_GSHR0_Pos) /*!< SCU_GENERAL CCUCON: GSHR0 Mask */
\r
4892 /* ----------------------------- SCU_GENERAL_DTSCON ----------------------------- */
\r
4893 #define SCU_GENERAL_DTSCON_PWD_Pos 0 /*!< SCU_GENERAL DTSCON: PWD Position */
\r
4894 #define SCU_GENERAL_DTSCON_PWD_Msk (0x01UL << SCU_GENERAL_DTSCON_PWD_Pos) /*!< SCU_GENERAL DTSCON: PWD Mask */
\r
4895 #define SCU_GENERAL_DTSCON_START_Pos 1 /*!< SCU_GENERAL DTSCON: START Position */
\r
4896 #define SCU_GENERAL_DTSCON_START_Msk (0x01UL << SCU_GENERAL_DTSCON_START_Pos) /*!< SCU_GENERAL DTSCON: START Mask */
\r
4897 #define SCU_GENERAL_DTSCON_OFFSET_Pos 4 /*!< SCU_GENERAL DTSCON: OFFSET Position */
\r
4898 #define SCU_GENERAL_DTSCON_OFFSET_Msk (0x7fUL << SCU_GENERAL_DTSCON_OFFSET_Pos) /*!< SCU_GENERAL DTSCON: OFFSET Mask */
\r
4899 #define SCU_GENERAL_DTSCON_GAIN_Pos 11 /*!< SCU_GENERAL DTSCON: GAIN Position */
\r
4900 #define SCU_GENERAL_DTSCON_GAIN_Msk (0x3fUL << SCU_GENERAL_DTSCON_GAIN_Pos) /*!< SCU_GENERAL DTSCON: GAIN Mask */
\r
4901 #define SCU_GENERAL_DTSCON_REFTRIM_Pos 17 /*!< SCU_GENERAL DTSCON: REFTRIM Position */
\r
4902 #define SCU_GENERAL_DTSCON_REFTRIM_Msk (0x07UL << SCU_GENERAL_DTSCON_REFTRIM_Pos) /*!< SCU_GENERAL DTSCON: REFTRIM Mask */
\r
4903 #define SCU_GENERAL_DTSCON_BGTRIM_Pos 20 /*!< SCU_GENERAL DTSCON: BGTRIM Position */
\r
4904 #define SCU_GENERAL_DTSCON_BGTRIM_Msk (0x0fUL << SCU_GENERAL_DTSCON_BGTRIM_Pos) /*!< SCU_GENERAL DTSCON: BGTRIM Mask */
\r
4906 /* ----------------------------- SCU_GENERAL_DTSSTAT ---------------------------- */
\r
4907 #define SCU_GENERAL_DTSSTAT_RESULT_Pos 0 /*!< SCU_GENERAL DTSSTAT: RESULT Position */
\r
4908 #define SCU_GENERAL_DTSSTAT_RESULT_Msk (0x000003ffUL << SCU_GENERAL_DTSSTAT_RESULT_Pos) /*!< SCU_GENERAL DTSSTAT: RESULT Mask */
\r
4909 #define SCU_GENERAL_DTSSTAT_RDY_Pos 14 /*!< SCU_GENERAL DTSSTAT: RDY Position */
\r
4910 #define SCU_GENERAL_DTSSTAT_RDY_Msk (0x01UL << SCU_GENERAL_DTSSTAT_RDY_Pos) /*!< SCU_GENERAL DTSSTAT: RDY Mask */
\r
4911 #define SCU_GENERAL_DTSSTAT_BUSY_Pos 15 /*!< SCU_GENERAL DTSSTAT: BUSY Position */
\r
4912 #define SCU_GENERAL_DTSSTAT_BUSY_Msk (0x01UL << SCU_GENERAL_DTSSTAT_BUSY_Pos) /*!< SCU_GENERAL DTSSTAT: BUSY Mask */
\r
4914 /* ----------------------------- SCU_GENERAL_GORCEN ----------------------------- */
\r
4915 #define SCU_GENERAL_GORCEN_ENORC6_Pos 6 /*!< SCU_GENERAL GORCEN: ENORC6 Position */
\r
4916 #define SCU_GENERAL_GORCEN_ENORC6_Msk (0x01UL << SCU_GENERAL_GORCEN_ENORC6_Pos) /*!< SCU_GENERAL GORCEN: ENORC6 Mask */
\r
4917 #define SCU_GENERAL_GORCEN_ENORC7_Pos 7 /*!< SCU_GENERAL GORCEN: ENORC7 Position */
\r
4918 #define SCU_GENERAL_GORCEN_ENORC7_Msk (0x01UL << SCU_GENERAL_GORCEN_ENORC7_Pos) /*!< SCU_GENERAL GORCEN: ENORC7 Mask */
\r
4920 /* ---------------------------- SCU_GENERAL_DTEMPLIM ---------------------------- */
\r
4921 #define SCU_GENERAL_DTEMPLIM_LOWER_Pos 0 /*!< SCU_GENERAL DTEMPLIM: LOWER Position */
\r
4922 #define SCU_GENERAL_DTEMPLIM_LOWER_Msk (0x000003ffUL << SCU_GENERAL_DTEMPLIM_LOWER_Pos) /*!< SCU_GENERAL DTEMPLIM: LOWER Mask */
\r
4923 #define SCU_GENERAL_DTEMPLIM_UPPER_Pos 16 /*!< SCU_GENERAL DTEMPLIM: UPPER Position */
\r
4924 #define SCU_GENERAL_DTEMPLIM_UPPER_Msk (0x000003ffUL << SCU_GENERAL_DTEMPLIM_UPPER_Pos) /*!< SCU_GENERAL DTEMPLIM: UPPER Mask */
\r
4926 /* --------------------------- SCU_GENERAL_DTEMPALARM --------------------------- */
\r
4927 #define SCU_GENERAL_DTEMPALARM_UNDERFL_Pos 0 /*!< SCU_GENERAL DTEMPALARM: UNDERFL Position */
\r
4928 #define SCU_GENERAL_DTEMPALARM_UNDERFL_Msk (0x01UL << SCU_GENERAL_DTEMPALARM_UNDERFL_Pos) /*!< SCU_GENERAL DTEMPALARM: UNDERFL Mask */
\r
4929 #define SCU_GENERAL_DTEMPALARM_OVERFL_Pos 16 /*!< SCU_GENERAL DTEMPALARM: OVERFL Position */
\r
4930 #define SCU_GENERAL_DTEMPALARM_OVERFL_Msk (0x01UL << SCU_GENERAL_DTEMPALARM_OVERFL_Pos) /*!< SCU_GENERAL DTEMPALARM: OVERFL Mask */
\r
4932 /* ----------------------------- SCU_GENERAL_MIRRSTS ---------------------------- */
\r
4933 #define SCU_GENERAL_MIRRSTS_HDCLR_Pos 1 /*!< SCU_GENERAL MIRRSTS: HDCLR Position */
\r
4934 #define SCU_GENERAL_MIRRSTS_HDCLR_Msk (0x01UL << SCU_GENERAL_MIRRSTS_HDCLR_Pos) /*!< SCU_GENERAL MIRRSTS: HDCLR Mask */
\r
4935 #define SCU_GENERAL_MIRRSTS_HDSET_Pos 2 /*!< SCU_GENERAL MIRRSTS: HDSET Position */
\r
4936 #define SCU_GENERAL_MIRRSTS_HDSET_Msk (0x01UL << SCU_GENERAL_MIRRSTS_HDSET_Pos) /*!< SCU_GENERAL MIRRSTS: HDSET Mask */
\r
4937 #define SCU_GENERAL_MIRRSTS_HDCR_Pos 3 /*!< SCU_GENERAL MIRRSTS: HDCR Position */
\r
4938 #define SCU_GENERAL_MIRRSTS_HDCR_Msk (0x01UL << SCU_GENERAL_MIRRSTS_HDCR_Pos) /*!< SCU_GENERAL MIRRSTS: HDCR Mask */
\r
4939 #define SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos 5 /*!< SCU_GENERAL MIRRSTS: OSCSICTRL Position */
\r
4940 #define SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk (0x01UL << SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos) /*!< SCU_GENERAL MIRRSTS: OSCSICTRL Mask */
\r
4941 #define SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos 6 /*!< SCU_GENERAL MIRRSTS: OSCULSTAT Position */
\r
4942 #define SCU_GENERAL_MIRRSTS_OSCULSTAT_Msk (0x01UL << SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos) /*!< SCU_GENERAL MIRRSTS: OSCULSTAT Mask */
\r
4943 #define SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos 7 /*!< SCU_GENERAL MIRRSTS: OSCULCTRL Position */
\r
4944 #define SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk (0x01UL << SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos) /*!< SCU_GENERAL MIRRSTS: OSCULCTRL Mask */
\r
4945 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos 8 /*!< SCU_GENERAL MIRRSTS: RTC_CTR Position */
\r
4946 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_CTR_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_CTR Mask */
\r
4947 #define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos 9 /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Position */
\r
4948 #define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Mask */
\r
4949 #define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos 10 /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Position */
\r
4950 #define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Mask */
\r
4951 #define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos 11 /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Position */
\r
4952 #define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Mask */
\r
4953 #define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos 12 /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Position */
\r
4954 #define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Mask */
\r
4955 #define SCU_GENERAL_MIRRSTS_RMX_Pos 13 /*!< SCU_GENERAL MIRRSTS: RMX Position */
\r
4956 #define SCU_GENERAL_MIRRSTS_RMX_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RMX_Pos) /*!< SCU_GENERAL MIRRSTS: RMX Mask */
\r
4957 #define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos 14 /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR Position */
\r
4958 #define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR Mask */
\r
4959 #define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos 15 /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR Position */
\r
4960 #define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR Mask */
\r
4961 #define SCU_GENERAL_MIRRSTS_LPACCONF_Pos 16 /*!< SCU_GENERAL MIRRSTS: LPACCONF Position */
\r
4962 #define SCU_GENERAL_MIRRSTS_LPACCONF_Msk (0x01UL << SCU_GENERAL_MIRRSTS_LPACCONF_Pos) /*!< SCU_GENERAL MIRRSTS: LPACCONF Mask */
\r
4963 #define SCU_GENERAL_MIRRSTS_LPACTH0_Pos 17 /*!< SCU_GENERAL MIRRSTS: LPACTH0 Position */
\r
4964 #define SCU_GENERAL_MIRRSTS_LPACTH0_Msk (0x01UL << SCU_GENERAL_MIRRSTS_LPACTH0_Pos) /*!< SCU_GENERAL MIRRSTS: LPACTH0 Mask */
\r
4965 #define SCU_GENERAL_MIRRSTS_LPACTH1_Pos 18 /*!< SCU_GENERAL MIRRSTS: LPACTH1 Position */
\r
4966 #define SCU_GENERAL_MIRRSTS_LPACTH1_Msk (0x01UL << SCU_GENERAL_MIRRSTS_LPACTH1_Pos) /*!< SCU_GENERAL MIRRSTS: LPACTH1 Mask */
\r
4967 #define SCU_GENERAL_MIRRSTS_LPACCLR_Pos 20 /*!< SCU_GENERAL MIRRSTS: LPACCLR Position */
\r
4968 #define SCU_GENERAL_MIRRSTS_LPACCLR_Msk (0x01UL << SCU_GENERAL_MIRRSTS_LPACCLR_Pos) /*!< SCU_GENERAL MIRRSTS: LPACCLR Mask */
\r
4969 #define SCU_GENERAL_MIRRSTS_LPACSET_Pos 21 /*!< SCU_GENERAL MIRRSTS: LPACSET Position */
\r
4970 #define SCU_GENERAL_MIRRSTS_LPACSET_Msk (0x01UL << SCU_GENERAL_MIRRSTS_LPACSET_Pos) /*!< SCU_GENERAL MIRRSTS: LPACSET Mask */
\r
4971 #define SCU_GENERAL_MIRRSTS_HINTCLR_Pos 23 /*!< SCU_GENERAL MIRRSTS: HINTCLR Position */
\r
4972 #define SCU_GENERAL_MIRRSTS_HINTCLR_Msk (0x01UL << SCU_GENERAL_MIRRSTS_HINTCLR_Pos) /*!< SCU_GENERAL MIRRSTS: HINTCLR Mask */
\r
4973 #define SCU_GENERAL_MIRRSTS_HINTSET_Pos 24 /*!< SCU_GENERAL MIRRSTS: HINTSET Position */
\r
4974 #define SCU_GENERAL_MIRRSTS_HINTSET_Msk (0x01UL << SCU_GENERAL_MIRRSTS_HINTSET_Pos) /*!< SCU_GENERAL MIRRSTS: HINTSET Mask */
\r
4976 /* ------------------------------ SCU_GENERAL_RMACR ----------------------------- */
\r
4977 #define SCU_GENERAL_RMACR_RDWR_Pos 0 /*!< SCU_GENERAL RMACR: RDWR Position */
\r
4978 #define SCU_GENERAL_RMACR_RDWR_Msk (0x01UL << SCU_GENERAL_RMACR_RDWR_Pos) /*!< SCU_GENERAL RMACR: RDWR Mask */
\r
4979 #define SCU_GENERAL_RMACR_ADDR_Pos 16 /*!< SCU_GENERAL RMACR: ADDR Position */
\r
4980 #define SCU_GENERAL_RMACR_ADDR_Msk (0x0fUL << SCU_GENERAL_RMACR_ADDR_Pos) /*!< SCU_GENERAL RMACR: ADDR Mask */
\r
4982 /* ----------------------------- SCU_GENERAL_RMDATA ----------------------------- */
\r
4983 #define SCU_GENERAL_RMDATA_DATA_Pos 0 /*!< SCU_GENERAL RMDATA: DATA Position */
\r
4984 #define SCU_GENERAL_RMDATA_DATA_Msk (0xffffffffUL << SCU_GENERAL_RMDATA_DATA_Pos) /*!< SCU_GENERAL RMDATA: DATA Mask */
\r
4986 /* --------------------------- SCU_GENERAL_MIRRALLSTAT -------------------------- */
\r
4987 #define SCU_GENERAL_MIRRALLSTAT_BUSY_Pos 0 /*!< SCU_GENERAL MIRRALLSTAT: BUSY Position */
\r
4988 #define SCU_GENERAL_MIRRALLSTAT_BUSY_Msk (0x01UL << SCU_GENERAL_MIRRALLSTAT_BUSY_Pos) /*!< SCU_GENERAL MIRRALLSTAT: BUSY Mask */
\r
4990 /* --------------------------- SCU_GENERAL_MIRRALLREQ --------------------------- */
\r
4991 #define SCU_GENERAL_MIRRALLREQ_REQ_Pos 0 /*!< SCU_GENERAL MIRRALLREQ: REQ Position */
\r
4992 #define SCU_GENERAL_MIRRALLREQ_REQ_Msk (0x01UL << SCU_GENERAL_MIRRALLREQ_REQ_Pos) /*!< SCU_GENERAL MIRRALLREQ: REQ Mask */
\r
4995 /* ================================================================================ */
\r
4996 /* ================ struct 'SCU_INTERRUPT' Position & Mask ================ */
\r
4997 /* ================================================================================ */
\r
5000 /* ---------------------------- SCU_INTERRUPT_SRSTAT ---------------------------- */
\r
5001 #define SCU_INTERRUPT_SRSTAT_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRSTAT: PRWARN Position */
\r
5002 #define SCU_INTERRUPT_SRSTAT_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_PRWARN_Pos) /*!< SCU_INTERRUPT SRSTAT: PRWARN Mask */
\r
5003 #define SCU_INTERRUPT_SRSTAT_PI_Pos 1 /*!< SCU_INTERRUPT SRSTAT: PI Position */
\r
5004 #define SCU_INTERRUPT_SRSTAT_PI_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_PI_Pos) /*!< SCU_INTERRUPT SRSTAT: PI Mask */
\r
5005 #define SCU_INTERRUPT_SRSTAT_AI_Pos 2 /*!< SCU_INTERRUPT SRSTAT: AI Position */
\r
5006 #define SCU_INTERRUPT_SRSTAT_AI_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_AI_Pos) /*!< SCU_INTERRUPT SRSTAT: AI Mask */
\r
5007 #define SCU_INTERRUPT_SRSTAT_DLROVR_Pos 3 /*!< SCU_INTERRUPT SRSTAT: DLROVR Position */
\r
5008 #define SCU_INTERRUPT_SRSTAT_DLROVR_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_DLROVR_Pos) /*!< SCU_INTERRUPT SRSTAT: DLROVR Mask */
\r
5009 #define SCU_INTERRUPT_SRSTAT_LPACCR_Pos 6 /*!< SCU_INTERRUPT SRSTAT: LPACCR Position */
\r
5010 #define SCU_INTERRUPT_SRSTAT_LPACCR_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_LPACCR_Pos) /*!< SCU_INTERRUPT SRSTAT: LPACCR Mask */
\r
5011 #define SCU_INTERRUPT_SRSTAT_LPACTH0_Pos 7 /*!< SCU_INTERRUPT SRSTAT: LPACTH0 Position */
\r
5012 #define SCU_INTERRUPT_SRSTAT_LPACTH0_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_LPACTH0_Pos) /*!< SCU_INTERRUPT SRSTAT: LPACTH0 Mask */
\r
5013 #define SCU_INTERRUPT_SRSTAT_LPACTH1_Pos 8 /*!< SCU_INTERRUPT SRSTAT: LPACTH1 Position */
\r
5014 #define SCU_INTERRUPT_SRSTAT_LPACTH1_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_LPACTH1_Pos) /*!< SCU_INTERRUPT SRSTAT: LPACTH1 Mask */
\r
5015 #define SCU_INTERRUPT_SRSTAT_LPACST_Pos 9 /*!< SCU_INTERRUPT SRSTAT: LPACST Position */
\r
5016 #define SCU_INTERRUPT_SRSTAT_LPACST_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_LPACST_Pos) /*!< SCU_INTERRUPT SRSTAT: LPACST Mask */
\r
5017 #define SCU_INTERRUPT_SRSTAT_LPACCLR_Pos 10 /*!< SCU_INTERRUPT SRSTAT: LPACCLR Position */
\r
5018 #define SCU_INTERRUPT_SRSTAT_LPACCLR_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_LPACCLR_Pos) /*!< SCU_INTERRUPT SRSTAT: LPACCLR Mask */
\r
5019 #define SCU_INTERRUPT_SRSTAT_LPACSET_Pos 11 /*!< SCU_INTERRUPT SRSTAT: LPACSET Position */
\r
5020 #define SCU_INTERRUPT_SRSTAT_LPACSET_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_LPACSET_Pos) /*!< SCU_INTERRUPT SRSTAT: LPACSET Mask */
\r
5021 #define SCU_INTERRUPT_SRSTAT_HINTST_Pos 12 /*!< SCU_INTERRUPT SRSTAT: HINTST Position */
\r
5022 #define SCU_INTERRUPT_SRSTAT_HINTST_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_HINTST_Pos) /*!< SCU_INTERRUPT SRSTAT: HINTST Mask */
\r
5023 #define SCU_INTERRUPT_SRSTAT_HINTCLR_Pos 13 /*!< SCU_INTERRUPT SRSTAT: HINTCLR Position */
\r
5024 #define SCU_INTERRUPT_SRSTAT_HINTCLR_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_HINTCLR_Pos) /*!< SCU_INTERRUPT SRSTAT: HINTCLR Mask */
\r
5025 #define SCU_INTERRUPT_SRSTAT_HINTSET_Pos 14 /*!< SCU_INTERRUPT SRSTAT: HINTSET Position */
\r
5026 #define SCU_INTERRUPT_SRSTAT_HINTSET_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_HINTSET_Pos) /*!< SCU_INTERRUPT SRSTAT: HINTSET Mask */
\r
5027 #define SCU_INTERRUPT_SRSTAT_HDSTAT_Pos 16 /*!< SCU_INTERRUPT SRSTAT: HDSTAT Position */
\r
5028 #define SCU_INTERRUPT_SRSTAT_HDSTAT_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_HDSTAT_Pos) /*!< SCU_INTERRUPT SRSTAT: HDSTAT Mask */
\r
5029 #define SCU_INTERRUPT_SRSTAT_HDCLR_Pos 17 /*!< SCU_INTERRUPT SRSTAT: HDCLR Position */
\r
5030 #define SCU_INTERRUPT_SRSTAT_HDCLR_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_HDCLR_Pos) /*!< SCU_INTERRUPT SRSTAT: HDCLR Mask */
\r
5031 #define SCU_INTERRUPT_SRSTAT_HDSET_Pos 18 /*!< SCU_INTERRUPT SRSTAT: HDSET Position */
\r
5032 #define SCU_INTERRUPT_SRSTAT_HDSET_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_HDSET_Pos) /*!< SCU_INTERRUPT SRSTAT: HDSET Mask */
\r
5033 #define SCU_INTERRUPT_SRSTAT_HDCR_Pos 19 /*!< SCU_INTERRUPT SRSTAT: HDCR Position */
\r
5034 #define SCU_INTERRUPT_SRSTAT_HDCR_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_HDCR_Pos) /*!< SCU_INTERRUPT SRSTAT: HDCR Mask */
\r
5035 #define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos 21 /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL Position */
\r
5036 #define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos) /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL Mask */
\r
5037 #define SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos 22 /*!< SCU_INTERRUPT SRSTAT: OSCULSTAT Position */
\r
5038 #define SCU_INTERRUPT_SRSTAT_OSCULSTAT_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos) /*!< SCU_INTERRUPT SRSTAT: OSCULSTAT Mask */
\r
5039 #define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos 23 /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL Position */
\r
5040 #define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos) /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL Mask */
\r
5041 #define SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRSTAT: RTC_CTR Position */
\r
5042 #define SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRSTAT: RTC_CTR Mask */
\r
5043 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 Position */
\r
5044 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 Mask */
\r
5045 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 Position */
\r
5046 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 Mask */
\r
5047 #define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 Position */
\r
5048 #define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 Mask */
\r
5049 #define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 Position */
\r
5050 #define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 Mask */
\r
5051 #define SCU_INTERRUPT_SRSTAT_RMX_Pos 29 /*!< SCU_INTERRUPT SRSTAT: RMX Position */
\r
5052 #define SCU_INTERRUPT_SRSTAT_RMX_Msk (0x01UL << SCU_INTERRUPT_SRSTAT_RMX_Pos) /*!< SCU_INTERRUPT SRSTAT: RMX Mask */
\r
5054 /* ----------------------------- SCU_INTERRUPT_SRRAW ---------------------------- */
\r
5055 #define SCU_INTERRUPT_SRRAW_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRRAW: PRWARN Position */
\r
5056 #define SCU_INTERRUPT_SRRAW_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PRWARN_Pos) /*!< SCU_INTERRUPT SRRAW: PRWARN Mask */
\r
5057 #define SCU_INTERRUPT_SRRAW_PI_Pos 1 /*!< SCU_INTERRUPT SRRAW: PI Position */
\r
5058 #define SCU_INTERRUPT_SRRAW_PI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PI_Pos) /*!< SCU_INTERRUPT SRRAW: PI Mask */
\r
5059 #define SCU_INTERRUPT_SRRAW_AI_Pos 2 /*!< SCU_INTERRUPT SRRAW: AI Position */
\r
5060 #define SCU_INTERRUPT_SRRAW_AI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_AI_Pos) /*!< SCU_INTERRUPT SRRAW: AI Mask */
\r
5061 #define SCU_INTERRUPT_SRRAW_DLROVR_Pos 3 /*!< SCU_INTERRUPT SRRAW: DLROVR Position */
\r
5062 #define SCU_INTERRUPT_SRRAW_DLROVR_Msk (0x01UL << SCU_INTERRUPT_SRRAW_DLROVR_Pos) /*!< SCU_INTERRUPT SRRAW: DLROVR Mask */
\r
5063 #define SCU_INTERRUPT_SRRAW_LPACCR_Pos 6 /*!< SCU_INTERRUPT SRRAW: LPACCR Position */
\r
5064 #define SCU_INTERRUPT_SRRAW_LPACCR_Msk (0x01UL << SCU_INTERRUPT_SRRAW_LPACCR_Pos) /*!< SCU_INTERRUPT SRRAW: LPACCR Mask */
\r
5065 #define SCU_INTERRUPT_SRRAW_LPACTH0_Pos 7 /*!< SCU_INTERRUPT SRRAW: LPACTH0 Position */
\r
5066 #define SCU_INTERRUPT_SRRAW_LPACTH0_Msk (0x01UL << SCU_INTERRUPT_SRRAW_LPACTH0_Pos) /*!< SCU_INTERRUPT SRRAW: LPACTH0 Mask */
\r
5067 #define SCU_INTERRUPT_SRRAW_LPACTH1_Pos 8 /*!< SCU_INTERRUPT SRRAW: LPACTH1 Position */
\r
5068 #define SCU_INTERRUPT_SRRAW_LPACTH1_Msk (0x01UL << SCU_INTERRUPT_SRRAW_LPACTH1_Pos) /*!< SCU_INTERRUPT SRRAW: LPACTH1 Mask */
\r
5069 #define SCU_INTERRUPT_SRRAW_LPACST_Pos 9 /*!< SCU_INTERRUPT SRRAW: LPACST Position */
\r
5070 #define SCU_INTERRUPT_SRRAW_LPACST_Msk (0x01UL << SCU_INTERRUPT_SRRAW_LPACST_Pos) /*!< SCU_INTERRUPT SRRAW: LPACST Mask */
\r
5071 #define SCU_INTERRUPT_SRRAW_LPACCLR_Pos 10 /*!< SCU_INTERRUPT SRRAW: LPACCLR Position */
\r
5072 #define SCU_INTERRUPT_SRRAW_LPACCLR_Msk (0x01UL << SCU_INTERRUPT_SRRAW_LPACCLR_Pos) /*!< SCU_INTERRUPT SRRAW: LPACCLR Mask */
\r
5073 #define SCU_INTERRUPT_SRRAW_LPACSET_Pos 11 /*!< SCU_INTERRUPT SRRAW: LPACSET Position */
\r
5074 #define SCU_INTERRUPT_SRRAW_LPACSET_Msk (0x01UL << SCU_INTERRUPT_SRRAW_LPACSET_Pos) /*!< SCU_INTERRUPT SRRAW: LPACSET Mask */
\r
5075 #define SCU_INTERRUPT_SRRAW_HINTST_Pos 12 /*!< SCU_INTERRUPT SRRAW: HINTST Position */
\r
5076 #define SCU_INTERRUPT_SRRAW_HINTST_Msk (0x01UL << SCU_INTERRUPT_SRRAW_HINTST_Pos) /*!< SCU_INTERRUPT SRRAW: HINTST Mask */
\r
5077 #define SCU_INTERRUPT_SRRAW_HINTCLR_Pos 13 /*!< SCU_INTERRUPT SRRAW: HINTCLR Position */
\r
5078 #define SCU_INTERRUPT_SRRAW_HINTCLR_Msk (0x01UL << SCU_INTERRUPT_SRRAW_HINTCLR_Pos) /*!< SCU_INTERRUPT SRRAW: HINTCLR Mask */
\r
5079 #define SCU_INTERRUPT_SRRAW_HINTSET_Pos 14 /*!< SCU_INTERRUPT SRRAW: HINTSET Position */
\r
5080 #define SCU_INTERRUPT_SRRAW_HINTSET_Msk (0x01UL << SCU_INTERRUPT_SRRAW_HINTSET_Pos) /*!< SCU_INTERRUPT SRRAW: HINTSET Mask */
\r
5081 #define SCU_INTERRUPT_SRRAW_HDSTAT_Pos 16 /*!< SCU_INTERRUPT SRRAW: HDSTAT Position */
\r
5082 #define SCU_INTERRUPT_SRRAW_HDSTAT_Msk (0x01UL << SCU_INTERRUPT_SRRAW_HDSTAT_Pos) /*!< SCU_INTERRUPT SRRAW: HDSTAT Mask */
\r
5083 #define SCU_INTERRUPT_SRRAW_HDCLR_Pos 17 /*!< SCU_INTERRUPT SRRAW: HDCLR Position */
\r
5084 #define SCU_INTERRUPT_SRRAW_HDCLR_Msk (0x01UL << SCU_INTERRUPT_SRRAW_HDCLR_Pos) /*!< SCU_INTERRUPT SRRAW: HDCLR Mask */
\r
5085 #define SCU_INTERRUPT_SRRAW_HDSET_Pos 18 /*!< SCU_INTERRUPT SRRAW: HDSET Position */
\r
5086 #define SCU_INTERRUPT_SRRAW_HDSET_Msk (0x01UL << SCU_INTERRUPT_SRRAW_HDSET_Pos) /*!< SCU_INTERRUPT SRRAW: HDSET Mask */
\r
5087 #define SCU_INTERRUPT_SRRAW_HDCR_Pos 19 /*!< SCU_INTERRUPT SRRAW: HDCR Position */
\r
5088 #define SCU_INTERRUPT_SRRAW_HDCR_Msk (0x01UL << SCU_INTERRUPT_SRRAW_HDCR_Pos) /*!< SCU_INTERRUPT SRRAW: HDCR Mask */
\r
5089 #define SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos 21 /*!< SCU_INTERRUPT SRRAW: OSCSICTRL Position */
\r
5090 #define SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk (0x01UL << SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos) /*!< SCU_INTERRUPT SRRAW: OSCSICTRL Mask */
\r
5091 #define SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos 22 /*!< SCU_INTERRUPT SRRAW: OSCULSTAT Position */
\r
5092 #define SCU_INTERRUPT_SRRAW_OSCULSTAT_Msk (0x01UL << SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos) /*!< SCU_INTERRUPT SRRAW: OSCULSTAT Mask */
\r
5093 #define SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos 23 /*!< SCU_INTERRUPT SRRAW: OSCULCTRL Position */
\r
5094 #define SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk (0x01UL << SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos) /*!< SCU_INTERRUPT SRRAW: OSCULCTRL Mask */
\r
5095 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRRAW: RTC_CTR Position */
\r
5096 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_CTR Mask */
\r
5097 #define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Position */
\r
5098 #define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Mask */
\r
5099 #define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Position */
\r
5100 #define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Mask */
\r
5101 #define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Position */
\r
5102 #define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Mask */
\r
5103 #define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Position */
\r
5104 #define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Mask */
\r
5105 #define SCU_INTERRUPT_SRRAW_RMX_Pos 29 /*!< SCU_INTERRUPT SRRAW: RMX Position */
\r
5106 #define SCU_INTERRUPT_SRRAW_RMX_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RMX_Pos) /*!< SCU_INTERRUPT SRRAW: RMX Mask */
\r
5108 /* ----------------------------- SCU_INTERRUPT_SRMSK ---------------------------- */
\r
5109 #define SCU_INTERRUPT_SRMSK_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRMSK: PRWARN Position */
\r
5110 #define SCU_INTERRUPT_SRMSK_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PRWARN_Pos) /*!< SCU_INTERRUPT SRMSK: PRWARN Mask */
\r
5111 #define SCU_INTERRUPT_SRMSK_PI_Pos 1 /*!< SCU_INTERRUPT SRMSK: PI Position */
\r
5112 #define SCU_INTERRUPT_SRMSK_PI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PI_Pos) /*!< SCU_INTERRUPT SRMSK: PI Mask */
\r
5113 #define SCU_INTERRUPT_SRMSK_AI_Pos 2 /*!< SCU_INTERRUPT SRMSK: AI Position */
\r
5114 #define SCU_INTERRUPT_SRMSK_AI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_AI_Pos) /*!< SCU_INTERRUPT SRMSK: AI Mask */
\r
5115 #define SCU_INTERRUPT_SRMSK_DLROVR_Pos 3 /*!< SCU_INTERRUPT SRMSK: DLROVR Position */
\r
5116 #define SCU_INTERRUPT_SRMSK_DLROVR_Msk (0x01UL << SCU_INTERRUPT_SRMSK_DLROVR_Pos) /*!< SCU_INTERRUPT SRMSK: DLROVR Mask */
\r
5117 #define SCU_INTERRUPT_SRMSK_LPACCR_Pos 6 /*!< SCU_INTERRUPT SRMSK: LPACCR Position */
\r
5118 #define SCU_INTERRUPT_SRMSK_LPACCR_Msk (0x01UL << SCU_INTERRUPT_SRMSK_LPACCR_Pos) /*!< SCU_INTERRUPT SRMSK: LPACCR Mask */
\r
5119 #define SCU_INTERRUPT_SRMSK_LPACTH0_Pos 7 /*!< SCU_INTERRUPT SRMSK: LPACTH0 Position */
\r
5120 #define SCU_INTERRUPT_SRMSK_LPACTH0_Msk (0x01UL << SCU_INTERRUPT_SRMSK_LPACTH0_Pos) /*!< SCU_INTERRUPT SRMSK: LPACTH0 Mask */
\r
5121 #define SCU_INTERRUPT_SRMSK_LPACTH1_Pos 8 /*!< SCU_INTERRUPT SRMSK: LPACTH1 Position */
\r
5122 #define SCU_INTERRUPT_SRMSK_LPACTH1_Msk (0x01UL << SCU_INTERRUPT_SRMSK_LPACTH1_Pos) /*!< SCU_INTERRUPT SRMSK: LPACTH1 Mask */
\r
5123 #define SCU_INTERRUPT_SRMSK_LPACST_Pos 9 /*!< SCU_INTERRUPT SRMSK: LPACST Position */
\r
5124 #define SCU_INTERRUPT_SRMSK_LPACST_Msk (0x01UL << SCU_INTERRUPT_SRMSK_LPACST_Pos) /*!< SCU_INTERRUPT SRMSK: LPACST Mask */
\r
5125 #define SCU_INTERRUPT_SRMSK_LPACCLR_Pos 10 /*!< SCU_INTERRUPT SRMSK: LPACCLR Position */
\r
5126 #define SCU_INTERRUPT_SRMSK_LPACCLR_Msk (0x01UL << SCU_INTERRUPT_SRMSK_LPACCLR_Pos) /*!< SCU_INTERRUPT SRMSK: LPACCLR Mask */
\r
5127 #define SCU_INTERRUPT_SRMSK_LPACSET_Pos 11 /*!< SCU_INTERRUPT SRMSK: LPACSET Position */
\r
5128 #define SCU_INTERRUPT_SRMSK_LPACSET_Msk (0x01UL << SCU_INTERRUPT_SRMSK_LPACSET_Pos) /*!< SCU_INTERRUPT SRMSK: LPACSET Mask */
\r
5129 #define SCU_INTERRUPT_SRMSK_HINTST_Pos 12 /*!< SCU_INTERRUPT SRMSK: HINTST Position */
\r
5130 #define SCU_INTERRUPT_SRMSK_HINTST_Msk (0x01UL << SCU_INTERRUPT_SRMSK_HINTST_Pos) /*!< SCU_INTERRUPT SRMSK: HINTST Mask */
\r
5131 #define SCU_INTERRUPT_SRMSK_HINTCLR_Pos 13 /*!< SCU_INTERRUPT SRMSK: HINTCLR Position */
\r
5132 #define SCU_INTERRUPT_SRMSK_HINTCLR_Msk (0x01UL << SCU_INTERRUPT_SRMSK_HINTCLR_Pos) /*!< SCU_INTERRUPT SRMSK: HINTCLR Mask */
\r
5133 #define SCU_INTERRUPT_SRMSK_HINTSET_Pos 14 /*!< SCU_INTERRUPT SRMSK: HINTSET Position */
\r
5134 #define SCU_INTERRUPT_SRMSK_HINTSET_Msk (0x01UL << SCU_INTERRUPT_SRMSK_HINTSET_Pos) /*!< SCU_INTERRUPT SRMSK: HINTSET Mask */
\r
5135 #define SCU_INTERRUPT_SRMSK_HDSTAT_Pos 16 /*!< SCU_INTERRUPT SRMSK: HDSTAT Position */
\r
5136 #define SCU_INTERRUPT_SRMSK_HDSTAT_Msk (0x01UL << SCU_INTERRUPT_SRMSK_HDSTAT_Pos) /*!< SCU_INTERRUPT SRMSK: HDSTAT Mask */
\r
5137 #define SCU_INTERRUPT_SRMSK_HDCLR_Pos 17 /*!< SCU_INTERRUPT SRMSK: HDCLR Position */
\r
5138 #define SCU_INTERRUPT_SRMSK_HDCLR_Msk (0x01UL << SCU_INTERRUPT_SRMSK_HDCLR_Pos) /*!< SCU_INTERRUPT SRMSK: HDCLR Mask */
\r
5139 #define SCU_INTERRUPT_SRMSK_HDSET_Pos 18 /*!< SCU_INTERRUPT SRMSK: HDSET Position */
\r
5140 #define SCU_INTERRUPT_SRMSK_HDSET_Msk (0x01UL << SCU_INTERRUPT_SRMSK_HDSET_Pos) /*!< SCU_INTERRUPT SRMSK: HDSET Mask */
\r
5141 #define SCU_INTERRUPT_SRMSK_HDCR_Pos 19 /*!< SCU_INTERRUPT SRMSK: HDCR Position */
\r
5142 #define SCU_INTERRUPT_SRMSK_HDCR_Msk (0x01UL << SCU_INTERRUPT_SRMSK_HDCR_Pos) /*!< SCU_INTERRUPT SRMSK: HDCR Mask */
\r
5143 #define SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos 21 /*!< SCU_INTERRUPT SRMSK: OSCSICTRL Position */
\r
5144 #define SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk (0x01UL << SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos) /*!< SCU_INTERRUPT SRMSK: OSCSICTRL Mask */
\r
5145 #define SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos 22 /*!< SCU_INTERRUPT SRMSK: OSCULSTAT Position */
\r
5146 #define SCU_INTERRUPT_SRMSK_OSCULSTAT_Msk (0x01UL << SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos) /*!< SCU_INTERRUPT SRMSK: OSCULSTAT Mask */
\r
5147 #define SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos 23 /*!< SCU_INTERRUPT SRMSK: OSCULCTRL Position */
\r
5148 #define SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk (0x01UL << SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos) /*!< SCU_INTERRUPT SRMSK: OSCULCTRL Mask */
\r
5149 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRMSK: RTC_CTR Position */
\r
5150 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_CTR Mask */
\r
5151 #define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Position */
\r
5152 #define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Mask */
\r
5153 #define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Position */
\r
5154 #define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Mask */
\r
5155 #define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Position */
\r
5156 #define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Mask */
\r
5157 #define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Position */
\r
5158 #define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Mask */
\r
5159 #define SCU_INTERRUPT_SRMSK_RMX_Pos 29 /*!< SCU_INTERRUPT SRMSK: RMX Position */
\r
5160 #define SCU_INTERRUPT_SRMSK_RMX_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RMX_Pos) /*!< SCU_INTERRUPT SRMSK: RMX Mask */
\r
5162 /* ----------------------------- SCU_INTERRUPT_SRCLR ---------------------------- */
\r
5163 #define SCU_INTERRUPT_SRCLR_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRCLR: PRWARN Position */
\r
5164 #define SCU_INTERRUPT_SRCLR_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PRWARN_Pos) /*!< SCU_INTERRUPT SRCLR: PRWARN Mask */
\r
5165 #define SCU_INTERRUPT_SRCLR_PI_Pos 1 /*!< SCU_INTERRUPT SRCLR: PI Position */
\r
5166 #define SCU_INTERRUPT_SRCLR_PI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PI_Pos) /*!< SCU_INTERRUPT SRCLR: PI Mask */
\r
5167 #define SCU_INTERRUPT_SRCLR_AI_Pos 2 /*!< SCU_INTERRUPT SRCLR: AI Position */
\r
5168 #define SCU_INTERRUPT_SRCLR_AI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_AI_Pos) /*!< SCU_INTERRUPT SRCLR: AI Mask */
\r
5169 #define SCU_INTERRUPT_SRCLR_DLROVR_Pos 3 /*!< SCU_INTERRUPT SRCLR: DLROVR Position */
\r
5170 #define SCU_INTERRUPT_SRCLR_DLROVR_Msk (0x01UL << SCU_INTERRUPT_SRCLR_DLROVR_Pos) /*!< SCU_INTERRUPT SRCLR: DLROVR Mask */
\r
5171 #define SCU_INTERRUPT_SRCLR_LPACCR_Pos 6 /*!< SCU_INTERRUPT SRCLR: LPACCR Position */
\r
5172 #define SCU_INTERRUPT_SRCLR_LPACCR_Msk (0x01UL << SCU_INTERRUPT_SRCLR_LPACCR_Pos) /*!< SCU_INTERRUPT SRCLR: LPACCR Mask */
\r
5173 #define SCU_INTERRUPT_SRCLR_LPACTH0_Pos 7 /*!< SCU_INTERRUPT SRCLR: LPACTH0 Position */
\r
5174 #define SCU_INTERRUPT_SRCLR_LPACTH0_Msk (0x01UL << SCU_INTERRUPT_SRCLR_LPACTH0_Pos) /*!< SCU_INTERRUPT SRCLR: LPACTH0 Mask */
\r
5175 #define SCU_INTERRUPT_SRCLR_LPACTH1_Pos 8 /*!< SCU_INTERRUPT SRCLR: LPACTH1 Position */
\r
5176 #define SCU_INTERRUPT_SRCLR_LPACTH1_Msk (0x01UL << SCU_INTERRUPT_SRCLR_LPACTH1_Pos) /*!< SCU_INTERRUPT SRCLR: LPACTH1 Mask */
\r
5177 #define SCU_INTERRUPT_SRCLR_LPACST_Pos 9 /*!< SCU_INTERRUPT SRCLR: LPACST Position */
\r
5178 #define SCU_INTERRUPT_SRCLR_LPACST_Msk (0x01UL << SCU_INTERRUPT_SRCLR_LPACST_Pos) /*!< SCU_INTERRUPT SRCLR: LPACST Mask */
\r
5179 #define SCU_INTERRUPT_SRCLR_LPACCLR_Pos 10 /*!< SCU_INTERRUPT SRCLR: LPACCLR Position */
\r
5180 #define SCU_INTERRUPT_SRCLR_LPACCLR_Msk (0x01UL << SCU_INTERRUPT_SRCLR_LPACCLR_Pos) /*!< SCU_INTERRUPT SRCLR: LPACCLR Mask */
\r
5181 #define SCU_INTERRUPT_SRCLR_LPACSET_Pos 11 /*!< SCU_INTERRUPT SRCLR: LPACSET Position */
\r
5182 #define SCU_INTERRUPT_SRCLR_LPACSET_Msk (0x01UL << SCU_INTERRUPT_SRCLR_LPACSET_Pos) /*!< SCU_INTERRUPT SRCLR: LPACSET Mask */
\r
5183 #define SCU_INTERRUPT_SRCLR_HINTST_Pos 12 /*!< SCU_INTERRUPT SRCLR: HINTST Position */
\r
5184 #define SCU_INTERRUPT_SRCLR_HINTST_Msk (0x01UL << SCU_INTERRUPT_SRCLR_HINTST_Pos) /*!< SCU_INTERRUPT SRCLR: HINTST Mask */
\r
5185 #define SCU_INTERRUPT_SRCLR_HINTCLR_Pos 13 /*!< SCU_INTERRUPT SRCLR: HINTCLR Position */
\r
5186 #define SCU_INTERRUPT_SRCLR_HINTCLR_Msk (0x01UL << SCU_INTERRUPT_SRCLR_HINTCLR_Pos) /*!< SCU_INTERRUPT SRCLR: HINTCLR Mask */
\r
5187 #define SCU_INTERRUPT_SRCLR_HINTSET_Pos 14 /*!< SCU_INTERRUPT SRCLR: HINTSET Position */
\r
5188 #define SCU_INTERRUPT_SRCLR_HINTSET_Msk (0x01UL << SCU_INTERRUPT_SRCLR_HINTSET_Pos) /*!< SCU_INTERRUPT SRCLR: HINTSET Mask */
\r
5189 #define SCU_INTERRUPT_SRCLR_HDSTAT_Pos 16 /*!< SCU_INTERRUPT SRCLR: HDSTAT Position */
\r
5190 #define SCU_INTERRUPT_SRCLR_HDSTAT_Msk (0x01UL << SCU_INTERRUPT_SRCLR_HDSTAT_Pos) /*!< SCU_INTERRUPT SRCLR: HDSTAT Mask */
\r
5191 #define SCU_INTERRUPT_SRCLR_HDCLR_Pos 17 /*!< SCU_INTERRUPT SRCLR: HDCLR Position */
\r
5192 #define SCU_INTERRUPT_SRCLR_HDCLR_Msk (0x01UL << SCU_INTERRUPT_SRCLR_HDCLR_Pos) /*!< SCU_INTERRUPT SRCLR: HDCLR Mask */
\r
5193 #define SCU_INTERRUPT_SRCLR_HDSET_Pos 18 /*!< SCU_INTERRUPT SRCLR: HDSET Position */
\r
5194 #define SCU_INTERRUPT_SRCLR_HDSET_Msk (0x01UL << SCU_INTERRUPT_SRCLR_HDSET_Pos) /*!< SCU_INTERRUPT SRCLR: HDSET Mask */
\r
5195 #define SCU_INTERRUPT_SRCLR_HDCR_Pos 19 /*!< SCU_INTERRUPT SRCLR: HDCR Position */
\r
5196 #define SCU_INTERRUPT_SRCLR_HDCR_Msk (0x01UL << SCU_INTERRUPT_SRCLR_HDCR_Pos) /*!< SCU_INTERRUPT SRCLR: HDCR Mask */
\r
5197 #define SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos 21 /*!< SCU_INTERRUPT SRCLR: OSCSICTRL Position */
\r
5198 #define SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk (0x01UL << SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos) /*!< SCU_INTERRUPT SRCLR: OSCSICTRL Mask */
\r
5199 #define SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos 22 /*!< SCU_INTERRUPT SRCLR: OSCULSTAT Position */
\r
5200 #define SCU_INTERRUPT_SRCLR_OSCULSTAT_Msk (0x01UL << SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos) /*!< SCU_INTERRUPT SRCLR: OSCULSTAT Mask */
\r
5201 #define SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos 23 /*!< SCU_INTERRUPT SRCLR: OSCULCTRL Position */
\r
5202 #define SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk (0x01UL << SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos) /*!< SCU_INTERRUPT SRCLR: OSCULCTRL Mask */
\r
5203 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRCLR: RTC_CTR Position */
\r
5204 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_CTR Mask */
\r
5205 #define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Position */
\r
5206 #define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Mask */
\r
5207 #define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Position */
\r
5208 #define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Mask */
\r
5209 #define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Position */
\r
5210 #define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Mask */
\r
5211 #define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Position */
\r
5212 #define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Mask */
\r
5213 #define SCU_INTERRUPT_SRCLR_RMX_Pos 29 /*!< SCU_INTERRUPT SRCLR: RMX Position */
\r
5214 #define SCU_INTERRUPT_SRCLR_RMX_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RMX_Pos) /*!< SCU_INTERRUPT SRCLR: RMX Mask */
\r
5216 /* ----------------------------- SCU_INTERRUPT_SRSET ---------------------------- */
\r
5217 #define SCU_INTERRUPT_SRSET_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRSET: PRWARN Position */
\r
5218 #define SCU_INTERRUPT_SRSET_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRSET_PRWARN_Pos) /*!< SCU_INTERRUPT SRSET: PRWARN Mask */
\r
5219 #define SCU_INTERRUPT_SRSET_PI_Pos 1 /*!< SCU_INTERRUPT SRSET: PI Position */
\r
5220 #define SCU_INTERRUPT_SRSET_PI_Msk (0x01UL << SCU_INTERRUPT_SRSET_PI_Pos) /*!< SCU_INTERRUPT SRSET: PI Mask */
\r
5221 #define SCU_INTERRUPT_SRSET_AI_Pos 2 /*!< SCU_INTERRUPT SRSET: AI Position */
\r
5222 #define SCU_INTERRUPT_SRSET_AI_Msk (0x01UL << SCU_INTERRUPT_SRSET_AI_Pos) /*!< SCU_INTERRUPT SRSET: AI Mask */
\r
5223 #define SCU_INTERRUPT_SRSET_DLROVR_Pos 3 /*!< SCU_INTERRUPT SRSET: DLROVR Position */
\r
5224 #define SCU_INTERRUPT_SRSET_DLROVR_Msk (0x01UL << SCU_INTERRUPT_SRSET_DLROVR_Pos) /*!< SCU_INTERRUPT SRSET: DLROVR Mask */
\r
5225 #define SCU_INTERRUPT_SRSET_LPACCR_Pos 6 /*!< SCU_INTERRUPT SRSET: LPACCR Position */
\r
5226 #define SCU_INTERRUPT_SRSET_LPACCR_Msk (0x01UL << SCU_INTERRUPT_SRSET_LPACCR_Pos) /*!< SCU_INTERRUPT SRSET: LPACCR Mask */
\r
5227 #define SCU_INTERRUPT_SRSET_LPACTH0_Pos 7 /*!< SCU_INTERRUPT SRSET: LPACTH0 Position */
\r
5228 #define SCU_INTERRUPT_SRSET_LPACTH0_Msk (0x01UL << SCU_INTERRUPT_SRSET_LPACTH0_Pos) /*!< SCU_INTERRUPT SRSET: LPACTH0 Mask */
\r
5229 #define SCU_INTERRUPT_SRSET_LPACTH1_Pos 8 /*!< SCU_INTERRUPT SRSET: LPACTH1 Position */
\r
5230 #define SCU_INTERRUPT_SRSET_LPACTH1_Msk (0x01UL << SCU_INTERRUPT_SRSET_LPACTH1_Pos) /*!< SCU_INTERRUPT SRSET: LPACTH1 Mask */
\r
5231 #define SCU_INTERRUPT_SRSET_LPACST_Pos 9 /*!< SCU_INTERRUPT SRSET: LPACST Position */
\r
5232 #define SCU_INTERRUPT_SRSET_LPACST_Msk (0x01UL << SCU_INTERRUPT_SRSET_LPACST_Pos) /*!< SCU_INTERRUPT SRSET: LPACST Mask */
\r
5233 #define SCU_INTERRUPT_SRSET_LPACCLR_Pos 10 /*!< SCU_INTERRUPT SRSET: LPACCLR Position */
\r
5234 #define SCU_INTERRUPT_SRSET_LPACCLR_Msk (0x01UL << SCU_INTERRUPT_SRSET_LPACCLR_Pos) /*!< SCU_INTERRUPT SRSET: LPACCLR Mask */
\r
5235 #define SCU_INTERRUPT_SRSET_LPACSET_Pos 11 /*!< SCU_INTERRUPT SRSET: LPACSET Position */
\r
5236 #define SCU_INTERRUPT_SRSET_LPACSET_Msk (0x01UL << SCU_INTERRUPT_SRSET_LPACSET_Pos) /*!< SCU_INTERRUPT SRSET: LPACSET Mask */
\r
5237 #define SCU_INTERRUPT_SRSET_HINTST_Pos 12 /*!< SCU_INTERRUPT SRSET: HINTST Position */
\r
5238 #define SCU_INTERRUPT_SRSET_HINTST_Msk (0x01UL << SCU_INTERRUPT_SRSET_HINTST_Pos) /*!< SCU_INTERRUPT SRSET: HINTST Mask */
\r
5239 #define SCU_INTERRUPT_SRSET_HINTCLR_Pos 13 /*!< SCU_INTERRUPT SRSET: HINTCLR Position */
\r
5240 #define SCU_INTERRUPT_SRSET_HINTCLR_Msk (0x01UL << SCU_INTERRUPT_SRSET_HINTCLR_Pos) /*!< SCU_INTERRUPT SRSET: HINTCLR Mask */
\r
5241 #define SCU_INTERRUPT_SRSET_HINTSET_Pos 14 /*!< SCU_INTERRUPT SRSET: HINTSET Position */
\r
5242 #define SCU_INTERRUPT_SRSET_HINTSET_Msk (0x01UL << SCU_INTERRUPT_SRSET_HINTSET_Pos) /*!< SCU_INTERRUPT SRSET: HINTSET Mask */
\r
5243 #define SCU_INTERRUPT_SRSET_HDSTAT_Pos 16 /*!< SCU_INTERRUPT SRSET: HDSTAT Position */
\r
5244 #define SCU_INTERRUPT_SRSET_HDSTAT_Msk (0x01UL << SCU_INTERRUPT_SRSET_HDSTAT_Pos) /*!< SCU_INTERRUPT SRSET: HDSTAT Mask */
\r
5245 #define SCU_INTERRUPT_SRSET_HDCRCLR_Pos 17 /*!< SCU_INTERRUPT SRSET: HDCRCLR Position */
\r
5246 #define SCU_INTERRUPT_SRSET_HDCRCLR_Msk (0x01UL << SCU_INTERRUPT_SRSET_HDCRCLR_Pos) /*!< SCU_INTERRUPT SRSET: HDCRCLR Mask */
\r
5247 #define SCU_INTERRUPT_SRSET_HDCRSET_Pos 18 /*!< SCU_INTERRUPT SRSET: HDCRSET Position */
\r
5248 #define SCU_INTERRUPT_SRSET_HDCRSET_Msk (0x01UL << SCU_INTERRUPT_SRSET_HDCRSET_Pos) /*!< SCU_INTERRUPT SRSET: HDCRSET Mask */
\r
5249 #define SCU_INTERRUPT_SRSET_HDCR_Pos 19 /*!< SCU_INTERRUPT SRSET: HDCR Position */
\r
5250 #define SCU_INTERRUPT_SRSET_HDCR_Msk (0x01UL << SCU_INTERRUPT_SRSET_HDCR_Pos) /*!< SCU_INTERRUPT SRSET: HDCR Mask */
\r
5251 #define SCU_INTERRUPT_SRSET_OSCSICTRL_Pos 21 /*!< SCU_INTERRUPT SRSET: OSCSICTRL Position */
\r
5252 #define SCU_INTERRUPT_SRSET_OSCSICTRL_Msk (0x01UL << SCU_INTERRUPT_SRSET_OSCSICTRL_Pos) /*!< SCU_INTERRUPT SRSET: OSCSICTRL Mask */
\r
5253 #define SCU_INTERRUPT_SRSET_OSCULSTAT_Pos 22 /*!< SCU_INTERRUPT SRSET: OSCULSTAT Position */
\r
5254 #define SCU_INTERRUPT_SRSET_OSCULSTAT_Msk (0x01UL << SCU_INTERRUPT_SRSET_OSCULSTAT_Pos) /*!< SCU_INTERRUPT SRSET: OSCULSTAT Mask */
\r
5255 #define SCU_INTERRUPT_SRSET_OSCULCTRL_Pos 23 /*!< SCU_INTERRUPT SRSET: OSCULCTRL Position */
\r
5256 #define SCU_INTERRUPT_SRSET_OSCULCTRL_Msk (0x01UL << SCU_INTERRUPT_SRSET_OSCULCTRL_Pos) /*!< SCU_INTERRUPT SRSET: OSCULCTRL Mask */
\r
5257 #define SCU_INTERRUPT_SRSET_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRSET: RTC_CTR Position */
\r
5258 #define SCU_INTERRUPT_SRSET_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRSET: RTC_CTR Mask */
\r
5259 #define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Position */
\r
5260 #define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Mask */
\r
5261 #define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Position */
\r
5262 #define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Mask */
\r
5263 #define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Position */
\r
5264 #define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Mask */
\r
5265 #define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Position */
\r
5266 #define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Mask */
\r
5267 #define SCU_INTERRUPT_SRSET_RMX_Pos 29 /*!< SCU_INTERRUPT SRSET: RMX Position */
\r
5268 #define SCU_INTERRUPT_SRSET_RMX_Msk (0x01UL << SCU_INTERRUPT_SRSET_RMX_Pos) /*!< SCU_INTERRUPT SRSET: RMX Mask */
\r
5270 /* --------------------------- SCU_INTERRUPT_NMIREQEN --------------------------- */
\r
5271 #define SCU_INTERRUPT_NMIREQEN_PRWARN_Pos 0 /*!< SCU_INTERRUPT NMIREQEN: PRWARN Position */
\r
5272 #define SCU_INTERRUPT_NMIREQEN_PRWARN_Msk (0x01UL << SCU_INTERRUPT_NMIREQEN_PRWARN_Pos) /*!< SCU_INTERRUPT NMIREQEN: PRWARN Mask */
\r
5273 #define SCU_INTERRUPT_NMIREQEN_PI_Pos 1 /*!< SCU_INTERRUPT NMIREQEN: PI Position */
\r
5274 #define SCU_INTERRUPT_NMIREQEN_PI_Msk (0x01UL << SCU_INTERRUPT_NMIREQEN_PI_Pos) /*!< SCU_INTERRUPT NMIREQEN: PI Mask */
\r
5275 #define SCU_INTERRUPT_NMIREQEN_AI_Pos 2 /*!< SCU_INTERRUPT NMIREQEN: AI Position */
\r
5276 #define SCU_INTERRUPT_NMIREQEN_AI_Msk (0x01UL << SCU_INTERRUPT_NMIREQEN_AI_Pos) /*!< SCU_INTERRUPT NMIREQEN: AI Mask */
\r
5277 #define SCU_INTERRUPT_NMIREQEN_ERU00_Pos 16 /*!< SCU_INTERRUPT NMIREQEN: ERU00 Position */
\r
5278 #define SCU_INTERRUPT_NMIREQEN_ERU00_Msk (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU00_Pos) /*!< SCU_INTERRUPT NMIREQEN: ERU00 Mask */
\r
5279 #define SCU_INTERRUPT_NMIREQEN_ERU01_Pos 17 /*!< SCU_INTERRUPT NMIREQEN: ERU01 Position */
\r
5280 #define SCU_INTERRUPT_NMIREQEN_ERU01_Msk (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU01_Pos) /*!< SCU_INTERRUPT NMIREQEN: ERU01 Mask */
\r
5281 #define SCU_INTERRUPT_NMIREQEN_ERU02_Pos 18 /*!< SCU_INTERRUPT NMIREQEN: ERU02 Position */
\r
5282 #define SCU_INTERRUPT_NMIREQEN_ERU02_Msk (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU02_Pos) /*!< SCU_INTERRUPT NMIREQEN: ERU02 Mask */
\r
5283 #define SCU_INTERRUPT_NMIREQEN_ERU03_Pos 19 /*!< SCU_INTERRUPT NMIREQEN: ERU03 Position */
\r
5284 #define SCU_INTERRUPT_NMIREQEN_ERU03_Msk (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU03_Pos) /*!< SCU_INTERRUPT NMIREQEN: ERU03 Mask */
\r
5287 /* ================================================================================ */
\r
5288 /* ================ struct 'SCU_PARITY' Position & Mask ================ */
\r
5289 /* ================================================================================ */
\r
5292 /* ------------------------------- SCU_PARITY_PEEN ------------------------------ */
\r
5293 #define SCU_PARITY_PEEN_PEENPS_Pos 0 /*!< SCU_PARITY PEEN: PEENPS Position */
\r
5294 #define SCU_PARITY_PEEN_PEENPS_Msk (0x01UL << SCU_PARITY_PEEN_PEENPS_Pos) /*!< SCU_PARITY PEEN: PEENPS Mask */
\r
5295 #define SCU_PARITY_PEEN_PEENDS1_Pos 1 /*!< SCU_PARITY PEEN: PEENDS1 Position */
\r
5296 #define SCU_PARITY_PEEN_PEENDS1_Msk (0x01UL << SCU_PARITY_PEEN_PEENDS1_Pos) /*!< SCU_PARITY PEEN: PEENDS1 Mask */
\r
5297 #define SCU_PARITY_PEEN_PEENDS2_Pos 2 /*!< SCU_PARITY PEEN: PEENDS2 Position */
\r
5298 #define SCU_PARITY_PEEN_PEENDS2_Msk (0x01UL << SCU_PARITY_PEEN_PEENDS2_Pos) /*!< SCU_PARITY PEEN: PEENDS2 Mask */
\r
5299 #define SCU_PARITY_PEEN_PEENU0_Pos 8 /*!< SCU_PARITY PEEN: PEENU0 Position */
\r
5300 #define SCU_PARITY_PEEN_PEENU0_Msk (0x01UL << SCU_PARITY_PEEN_PEENU0_Pos) /*!< SCU_PARITY PEEN: PEENU0 Mask */
\r
5301 #define SCU_PARITY_PEEN_PEENU1_Pos 9 /*!< SCU_PARITY PEEN: PEENU1 Position */
\r
5302 #define SCU_PARITY_PEEN_PEENU1_Msk (0x01UL << SCU_PARITY_PEEN_PEENU1_Pos) /*!< SCU_PARITY PEEN: PEENU1 Mask */
\r
5303 #define SCU_PARITY_PEEN_PEENMC_Pos 12 /*!< SCU_PARITY PEEN: PEENMC Position */
\r
5304 #define SCU_PARITY_PEEN_PEENMC_Msk (0x01UL << SCU_PARITY_PEEN_PEENMC_Pos) /*!< SCU_PARITY PEEN: PEENMC Mask */
\r
5305 #define SCU_PARITY_PEEN_PEENPPRF_Pos 13 /*!< SCU_PARITY PEEN: PEENPPRF Position */
\r
5306 #define SCU_PARITY_PEEN_PEENPPRF_Msk (0x01UL << SCU_PARITY_PEEN_PEENPPRF_Pos) /*!< SCU_PARITY PEEN: PEENPPRF Mask */
\r
5307 #define SCU_PARITY_PEEN_PEENUSB_Pos 16 /*!< SCU_PARITY PEEN: PEENUSB Position */
\r
5308 #define SCU_PARITY_PEEN_PEENUSB_Msk (0x01UL << SCU_PARITY_PEEN_PEENUSB_Pos) /*!< SCU_PARITY PEEN: PEENUSB Mask */
\r
5309 #define SCU_PARITY_PEEN_PEENETH0TX_Pos 17 /*!< SCU_PARITY PEEN: PEENETH0TX Position */
\r
5310 #define SCU_PARITY_PEEN_PEENETH0TX_Msk (0x01UL << SCU_PARITY_PEEN_PEENETH0TX_Pos) /*!< SCU_PARITY PEEN: PEENETH0TX Mask */
\r
5311 #define SCU_PARITY_PEEN_PEENETH0RX_Pos 18 /*!< SCU_PARITY PEEN: PEENETH0RX Position */
\r
5312 #define SCU_PARITY_PEEN_PEENETH0RX_Msk (0x01UL << SCU_PARITY_PEEN_PEENETH0RX_Pos) /*!< SCU_PARITY PEEN: PEENETH0RX Mask */
\r
5314 /* ----------------------------- SCU_PARITY_MCHKCON ----------------------------- */
\r
5315 #define SCU_PARITY_MCHKCON_SELPS_Pos 0 /*!< SCU_PARITY MCHKCON: SELPS Position */
\r
5316 #define SCU_PARITY_MCHKCON_SELPS_Msk (0x01UL << SCU_PARITY_MCHKCON_SELPS_Pos) /*!< SCU_PARITY MCHKCON: SELPS Mask */
\r
5317 #define SCU_PARITY_MCHKCON_SELDS1_Pos 1 /*!< SCU_PARITY MCHKCON: SELDS1 Position */
\r
5318 #define SCU_PARITY_MCHKCON_SELDS1_Msk (0x01UL << SCU_PARITY_MCHKCON_SELDS1_Pos) /*!< SCU_PARITY MCHKCON: SELDS1 Mask */
\r
5319 #define SCU_PARITY_MCHKCON_SELDS2_Pos 2 /*!< SCU_PARITY MCHKCON: SELDS2 Position */
\r
5320 #define SCU_PARITY_MCHKCON_SELDS2_Msk (0x01UL << SCU_PARITY_MCHKCON_SELDS2_Pos) /*!< SCU_PARITY MCHKCON: SELDS2 Mask */
\r
5321 #define SCU_PARITY_MCHKCON_USIC0DRA_Pos 8 /*!< SCU_PARITY MCHKCON: USIC0DRA Position */
\r
5322 #define SCU_PARITY_MCHKCON_USIC0DRA_Msk (0x01UL << SCU_PARITY_MCHKCON_USIC0DRA_Pos) /*!< SCU_PARITY MCHKCON: USIC0DRA Mask */
\r
5323 #define SCU_PARITY_MCHKCON_USIC1DRA_Pos 9 /*!< SCU_PARITY MCHKCON: USIC1DRA Position */
\r
5324 #define SCU_PARITY_MCHKCON_USIC1DRA_Msk (0x01UL << SCU_PARITY_MCHKCON_USIC1DRA_Pos) /*!< SCU_PARITY MCHKCON: USIC1DRA Mask */
\r
5325 #define SCU_PARITY_MCHKCON_MCANDRA_Pos 12 /*!< SCU_PARITY MCHKCON: MCANDRA Position */
\r
5326 #define SCU_PARITY_MCHKCON_MCANDRA_Msk (0x01UL << SCU_PARITY_MCHKCON_MCANDRA_Pos) /*!< SCU_PARITY MCHKCON: MCANDRA Mask */
\r
5327 #define SCU_PARITY_MCHKCON_PPRFDRA_Pos 13 /*!< SCU_PARITY MCHKCON: PPRFDRA Position */
\r
5328 #define SCU_PARITY_MCHKCON_PPRFDRA_Msk (0x01UL << SCU_PARITY_MCHKCON_PPRFDRA_Pos) /*!< SCU_PARITY MCHKCON: PPRFDRA Mask */
\r
5329 #define SCU_PARITY_MCHKCON_SELUSB_Pos 16 /*!< SCU_PARITY MCHKCON: SELUSB Position */
\r
5330 #define SCU_PARITY_MCHKCON_SELUSB_Msk (0x01UL << SCU_PARITY_MCHKCON_SELUSB_Pos) /*!< SCU_PARITY MCHKCON: SELUSB Mask */
\r
5331 #define SCU_PARITY_MCHKCON_SELETH0TX_Pos 17 /*!< SCU_PARITY MCHKCON: SELETH0TX Position */
\r
5332 #define SCU_PARITY_MCHKCON_SELETH0TX_Msk (0x01UL << SCU_PARITY_MCHKCON_SELETH0TX_Pos) /*!< SCU_PARITY MCHKCON: SELETH0TX Mask */
\r
5333 #define SCU_PARITY_MCHKCON_SELETH0RX_Pos 18 /*!< SCU_PARITY MCHKCON: SELETH0RX Position */
\r
5334 #define SCU_PARITY_MCHKCON_SELETH0RX_Msk (0x01UL << SCU_PARITY_MCHKCON_SELETH0RX_Pos) /*!< SCU_PARITY MCHKCON: SELETH0RX Mask */
\r
5336 /* ------------------------------- SCU_PARITY_PETE ------------------------------ */
\r
5337 #define SCU_PARITY_PETE_PETEPS_Pos 0 /*!< SCU_PARITY PETE: PETEPS Position */
\r
5338 #define SCU_PARITY_PETE_PETEPS_Msk (0x01UL << SCU_PARITY_PETE_PETEPS_Pos) /*!< SCU_PARITY PETE: PETEPS Mask */
\r
5339 #define SCU_PARITY_PETE_PETEDS1_Pos 1 /*!< SCU_PARITY PETE: PETEDS1 Position */
\r
5340 #define SCU_PARITY_PETE_PETEDS1_Msk (0x01UL << SCU_PARITY_PETE_PETEDS1_Pos) /*!< SCU_PARITY PETE: PETEDS1 Mask */
\r
5341 #define SCU_PARITY_PETE_PETEDS2_Pos 2 /*!< SCU_PARITY PETE: PETEDS2 Position */
\r
5342 #define SCU_PARITY_PETE_PETEDS2_Msk (0x01UL << SCU_PARITY_PETE_PETEDS2_Pos) /*!< SCU_PARITY PETE: PETEDS2 Mask */
\r
5343 #define SCU_PARITY_PETE_PETEU0_Pos 8 /*!< SCU_PARITY PETE: PETEU0 Position */
\r
5344 #define SCU_PARITY_PETE_PETEU0_Msk (0x01UL << SCU_PARITY_PETE_PETEU0_Pos) /*!< SCU_PARITY PETE: PETEU0 Mask */
\r
5345 #define SCU_PARITY_PETE_PETEU1_Pos 9 /*!< SCU_PARITY PETE: PETEU1 Position */
\r
5346 #define SCU_PARITY_PETE_PETEU1_Msk (0x01UL << SCU_PARITY_PETE_PETEU1_Pos) /*!< SCU_PARITY PETE: PETEU1 Mask */
\r
5347 #define SCU_PARITY_PETE_PETEMC_Pos 12 /*!< SCU_PARITY PETE: PETEMC Position */
\r
5348 #define SCU_PARITY_PETE_PETEMC_Msk (0x01UL << SCU_PARITY_PETE_PETEMC_Pos) /*!< SCU_PARITY PETE: PETEMC Mask */
\r
5349 #define SCU_PARITY_PETE_PETEPPRF_Pos 13 /*!< SCU_PARITY PETE: PETEPPRF Position */
\r
5350 #define SCU_PARITY_PETE_PETEPPRF_Msk (0x01UL << SCU_PARITY_PETE_PETEPPRF_Pos) /*!< SCU_PARITY PETE: PETEPPRF Mask */
\r
5351 #define SCU_PARITY_PETE_PETEUSB_Pos 16 /*!< SCU_PARITY PETE: PETEUSB Position */
\r
5352 #define SCU_PARITY_PETE_PETEUSB_Msk (0x01UL << SCU_PARITY_PETE_PETEUSB_Pos) /*!< SCU_PARITY PETE: PETEUSB Mask */
\r
5353 #define SCU_PARITY_PETE_PETEETH0TX_Pos 17 /*!< SCU_PARITY PETE: PETEETH0TX Position */
\r
5354 #define SCU_PARITY_PETE_PETEETH0TX_Msk (0x01UL << SCU_PARITY_PETE_PETEETH0TX_Pos) /*!< SCU_PARITY PETE: PETEETH0TX Mask */
\r
5355 #define SCU_PARITY_PETE_PETEETH0RX_Pos 18 /*!< SCU_PARITY PETE: PETEETH0RX Position */
\r
5356 #define SCU_PARITY_PETE_PETEETH0RX_Msk (0x01UL << SCU_PARITY_PETE_PETEETH0RX_Pos) /*!< SCU_PARITY PETE: PETEETH0RX Mask */
\r
5358 /* ----------------------------- SCU_PARITY_PERSTEN ----------------------------- */
\r
5359 #define SCU_PARITY_PERSTEN_RSEN_Pos 0 /*!< SCU_PARITY PERSTEN: RSEN Position */
\r
5360 #define SCU_PARITY_PERSTEN_RSEN_Msk (0x01UL << SCU_PARITY_PERSTEN_RSEN_Pos) /*!< SCU_PARITY PERSTEN: RSEN Mask */
\r
5362 /* ------------------------------ SCU_PARITY_PEFLAG ----------------------------- */
\r
5363 #define SCU_PARITY_PEFLAG_PEFPS_Pos 0 /*!< SCU_PARITY PEFLAG: PEFPS Position */
\r
5364 #define SCU_PARITY_PEFLAG_PEFPS_Msk (0x01UL << SCU_PARITY_PEFLAG_PEFPS_Pos) /*!< SCU_PARITY PEFLAG: PEFPS Mask */
\r
5365 #define SCU_PARITY_PEFLAG_PEFDS1_Pos 1 /*!< SCU_PARITY PEFLAG: PEFDS1 Position */
\r
5366 #define SCU_PARITY_PEFLAG_PEFDS1_Msk (0x01UL << SCU_PARITY_PEFLAG_PEFDS1_Pos) /*!< SCU_PARITY PEFLAG: PEFDS1 Mask */
\r
5367 #define SCU_PARITY_PEFLAG_PEFDS2_Pos 2 /*!< SCU_PARITY PEFLAG: PEFDS2 Position */
\r
5368 #define SCU_PARITY_PEFLAG_PEFDS2_Msk (0x01UL << SCU_PARITY_PEFLAG_PEFDS2_Pos) /*!< SCU_PARITY PEFLAG: PEFDS2 Mask */
\r
5369 #define SCU_PARITY_PEFLAG_PEFU0_Pos 8 /*!< SCU_PARITY PEFLAG: PEFU0 Position */
\r
5370 #define SCU_PARITY_PEFLAG_PEFU0_Msk (0x01UL << SCU_PARITY_PEFLAG_PEFU0_Pos) /*!< SCU_PARITY PEFLAG: PEFU0 Mask */
\r
5371 #define SCU_PARITY_PEFLAG_PEFU1_Pos 9 /*!< SCU_PARITY PEFLAG: PEFU1 Position */
\r
5372 #define SCU_PARITY_PEFLAG_PEFU1_Msk (0x01UL << SCU_PARITY_PEFLAG_PEFU1_Pos) /*!< SCU_PARITY PEFLAG: PEFU1 Mask */
\r
5373 #define SCU_PARITY_PEFLAG_PEFMC_Pos 12 /*!< SCU_PARITY PEFLAG: PEFMC Position */
\r
5374 #define SCU_PARITY_PEFLAG_PEFMC_Msk (0x01UL << SCU_PARITY_PEFLAG_PEFMC_Pos) /*!< SCU_PARITY PEFLAG: PEFMC Mask */
\r
5375 #define SCU_PARITY_PEFLAG_PEFPPRF_Pos 13 /*!< SCU_PARITY PEFLAG: PEFPPRF Position */
\r
5376 #define SCU_PARITY_PEFLAG_PEFPPRF_Msk (0x01UL << SCU_PARITY_PEFLAG_PEFPPRF_Pos) /*!< SCU_PARITY PEFLAG: PEFPPRF Mask */
\r
5377 #define SCU_PARITY_PEFLAG_PEUSB_Pos 16 /*!< SCU_PARITY PEFLAG: PEUSB Position */
\r
5378 #define SCU_PARITY_PEFLAG_PEUSB_Msk (0x01UL << SCU_PARITY_PEFLAG_PEUSB_Pos) /*!< SCU_PARITY PEFLAG: PEUSB Mask */
\r
5379 #define SCU_PARITY_PEFLAG_PEETH0TX_Pos 17 /*!< SCU_PARITY PEFLAG: PEETH0TX Position */
\r
5380 #define SCU_PARITY_PEFLAG_PEETH0TX_Msk (0x01UL << SCU_PARITY_PEFLAG_PEETH0TX_Pos) /*!< SCU_PARITY PEFLAG: PEETH0TX Mask */
\r
5381 #define SCU_PARITY_PEFLAG_PEETH0RX_Pos 18 /*!< SCU_PARITY PEFLAG: PEETH0RX Position */
\r
5382 #define SCU_PARITY_PEFLAG_PEETH0RX_Msk (0x01UL << SCU_PARITY_PEFLAG_PEETH0RX_Pos) /*!< SCU_PARITY PEFLAG: PEETH0RX Mask */
\r
5384 /* ------------------------------ SCU_PARITY_PMTPR ------------------------------ */
\r
5385 #define SCU_PARITY_PMTPR_PWR_Pos 0 /*!< SCU_PARITY PMTPR: PWR Position */
\r
5386 #define SCU_PARITY_PMTPR_PWR_Msk (0x000000ffUL << SCU_PARITY_PMTPR_PWR_Pos) /*!< SCU_PARITY PMTPR: PWR Mask */
\r
5387 #define SCU_PARITY_PMTPR_PRD_Pos 8 /*!< SCU_PARITY PMTPR: PRD Position */
\r
5388 #define SCU_PARITY_PMTPR_PRD_Msk (0x000000ffUL << SCU_PARITY_PMTPR_PRD_Pos) /*!< SCU_PARITY PMTPR: PRD Mask */
\r
5390 /* ------------------------------ SCU_PARITY_PMTSR ------------------------------ */
\r
5391 #define SCU_PARITY_PMTSR_MTENPS_Pos 0 /*!< SCU_PARITY PMTSR: MTENPS Position */
\r
5392 #define SCU_PARITY_PMTSR_MTENPS_Msk (0x01UL << SCU_PARITY_PMTSR_MTENPS_Pos) /*!< SCU_PARITY PMTSR: MTENPS Mask */
\r
5393 #define SCU_PARITY_PMTSR_MTENDS1_Pos 1 /*!< SCU_PARITY PMTSR: MTENDS1 Position */
\r
5394 #define SCU_PARITY_PMTSR_MTENDS1_Msk (0x01UL << SCU_PARITY_PMTSR_MTENDS1_Pos) /*!< SCU_PARITY PMTSR: MTENDS1 Mask */
\r
5395 #define SCU_PARITY_PMTSR_MTENDS2_Pos 2 /*!< SCU_PARITY PMTSR: MTENDS2 Position */
\r
5396 #define SCU_PARITY_PMTSR_MTENDS2_Msk (0x01UL << SCU_PARITY_PMTSR_MTENDS2_Pos) /*!< SCU_PARITY PMTSR: MTENDS2 Mask */
\r
5397 #define SCU_PARITY_PMTSR_MTEU0_Pos 8 /*!< SCU_PARITY PMTSR: MTEU0 Position */
\r
5398 #define SCU_PARITY_PMTSR_MTEU0_Msk (0x01UL << SCU_PARITY_PMTSR_MTEU0_Pos) /*!< SCU_PARITY PMTSR: MTEU0 Mask */
\r
5399 #define SCU_PARITY_PMTSR_MTEU1_Pos 9 /*!< SCU_PARITY PMTSR: MTEU1 Position */
\r
5400 #define SCU_PARITY_PMTSR_MTEU1_Msk (0x01UL << SCU_PARITY_PMTSR_MTEU1_Pos) /*!< SCU_PARITY PMTSR: MTEU1 Mask */
\r
5401 #define SCU_PARITY_PMTSR_MTEMC_Pos 12 /*!< SCU_PARITY PMTSR: MTEMC Position */
\r
5402 #define SCU_PARITY_PMTSR_MTEMC_Msk (0x01UL << SCU_PARITY_PMTSR_MTEMC_Pos) /*!< SCU_PARITY PMTSR: MTEMC Mask */
\r
5403 #define SCU_PARITY_PMTSR_MTEPPRF_Pos 13 /*!< SCU_PARITY PMTSR: MTEPPRF Position */
\r
5404 #define SCU_PARITY_PMTSR_MTEPPRF_Msk (0x01UL << SCU_PARITY_PMTSR_MTEPPRF_Pos) /*!< SCU_PARITY PMTSR: MTEPPRF Mask */
\r
5405 #define SCU_PARITY_PMTSR_MTUSB_Pos 16 /*!< SCU_PARITY PMTSR: MTUSB Position */
\r
5406 #define SCU_PARITY_PMTSR_MTUSB_Msk (0x01UL << SCU_PARITY_PMTSR_MTUSB_Pos) /*!< SCU_PARITY PMTSR: MTUSB Mask */
\r
5407 #define SCU_PARITY_PMTSR_MTETH0TX_Pos 17 /*!< SCU_PARITY PMTSR: MTETH0TX Position */
\r
5408 #define SCU_PARITY_PMTSR_MTETH0TX_Msk (0x01UL << SCU_PARITY_PMTSR_MTETH0TX_Pos) /*!< SCU_PARITY PMTSR: MTETH0TX Mask */
\r
5409 #define SCU_PARITY_PMTSR_MTETH0RX_Pos 18 /*!< SCU_PARITY PMTSR: MTETH0RX Position */
\r
5410 #define SCU_PARITY_PMTSR_MTETH0RX_Msk (0x01UL << SCU_PARITY_PMTSR_MTETH0RX_Pos) /*!< SCU_PARITY PMTSR: MTETH0RX Mask */
\r
5413 /* ================================================================================ */
\r
5414 /* ================ struct 'SCU_TRAP' Position & Mask ================ */
\r
5415 /* ================================================================================ */
\r
5418 /* ------------------------------ SCU_TRAP_TRAPSTAT ----------------------------- */
\r
5419 #define SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos 0 /*!< SCU_TRAP TRAPSTAT: SOSCWDGT Position */
\r
5420 #define SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk (0x01UL << SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos) /*!< SCU_TRAP TRAPSTAT: SOSCWDGT Mask */
\r
5421 #define SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos 2 /*!< SCU_TRAP TRAPSTAT: SVCOLCKT Position */
\r
5422 #define SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk (0x01UL << SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos) /*!< SCU_TRAP TRAPSTAT: SVCOLCKT Mask */
\r
5423 #define SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos 3 /*!< SCU_TRAP TRAPSTAT: UVCOLCKT Position */
\r
5424 #define SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk (0x01UL << SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos) /*!< SCU_TRAP TRAPSTAT: UVCOLCKT Mask */
\r
5425 #define SCU_TRAP_TRAPSTAT_PET_Pos 4 /*!< SCU_TRAP TRAPSTAT: PET Position */
\r
5426 #define SCU_TRAP_TRAPSTAT_PET_Msk (0x01UL << SCU_TRAP_TRAPSTAT_PET_Pos) /*!< SCU_TRAP TRAPSTAT: PET Mask */
\r
5427 #define SCU_TRAP_TRAPSTAT_BRWNT_Pos 5 /*!< SCU_TRAP TRAPSTAT: BRWNT Position */
\r
5428 #define SCU_TRAP_TRAPSTAT_BRWNT_Msk (0x01UL << SCU_TRAP_TRAPSTAT_BRWNT_Pos) /*!< SCU_TRAP TRAPSTAT: BRWNT Mask */
\r
5429 #define SCU_TRAP_TRAPSTAT_ULPWDGT_Pos 6 /*!< SCU_TRAP TRAPSTAT: ULPWDGT Position */
\r
5430 #define SCU_TRAP_TRAPSTAT_ULPWDGT_Msk (0x01UL << SCU_TRAP_TRAPSTAT_ULPWDGT_Pos) /*!< SCU_TRAP TRAPSTAT: ULPWDGT Mask */
\r
5431 #define SCU_TRAP_TRAPSTAT_BWERR0T_Pos 7 /*!< SCU_TRAP TRAPSTAT: BWERR0T Position */
\r
5432 #define SCU_TRAP_TRAPSTAT_BWERR0T_Msk (0x01UL << SCU_TRAP_TRAPSTAT_BWERR0T_Pos) /*!< SCU_TRAP TRAPSTAT: BWERR0T Mask */
\r
5433 #define SCU_TRAP_TRAPSTAT_BWERR1T_Pos 8 /*!< SCU_TRAP TRAPSTAT: BWERR1T Position */
\r
5434 #define SCU_TRAP_TRAPSTAT_BWERR1T_Msk (0x01UL << SCU_TRAP_TRAPSTAT_BWERR1T_Pos) /*!< SCU_TRAP TRAPSTAT: BWERR1T Mask */
\r
5435 #define SCU_TRAP_TRAPSTAT_TEMPHIT_Pos 12 /*!< SCU_TRAP TRAPSTAT: TEMPHIT Position */
\r
5436 #define SCU_TRAP_TRAPSTAT_TEMPHIT_Msk (0x01UL << SCU_TRAP_TRAPSTAT_TEMPHIT_Pos) /*!< SCU_TRAP TRAPSTAT: TEMPHIT Mask */
\r
5437 #define SCU_TRAP_TRAPSTAT_TEMPLOT_Pos 13 /*!< SCU_TRAP TRAPSTAT: TEMPLOT Position */
\r
5438 #define SCU_TRAP_TRAPSTAT_TEMPLOT_Msk (0x01UL << SCU_TRAP_TRAPSTAT_TEMPLOT_Pos) /*!< SCU_TRAP TRAPSTAT: TEMPLOT Mask */
\r
5440 /* ------------------------------ SCU_TRAP_TRAPRAW ------------------------------ */
\r
5441 #define SCU_TRAP_TRAPRAW_SOSCWDGT_Pos 0 /*!< SCU_TRAP TRAPRAW: SOSCWDGT Position */
\r
5442 #define SCU_TRAP_TRAPRAW_SOSCWDGT_Msk (0x01UL << SCU_TRAP_TRAPRAW_SOSCWDGT_Pos) /*!< SCU_TRAP TRAPRAW: SOSCWDGT Mask */
\r
5443 #define SCU_TRAP_TRAPRAW_SVCOLCKT_Pos 2 /*!< SCU_TRAP TRAPRAW: SVCOLCKT Position */
\r
5444 #define SCU_TRAP_TRAPRAW_SVCOLCKT_Msk (0x01UL << SCU_TRAP_TRAPRAW_SVCOLCKT_Pos) /*!< SCU_TRAP TRAPRAW: SVCOLCKT Mask */
\r
5445 #define SCU_TRAP_TRAPRAW_UVCOLCKT_Pos 3 /*!< SCU_TRAP TRAPRAW: UVCOLCKT Position */
\r
5446 #define SCU_TRAP_TRAPRAW_UVCOLCKT_Msk (0x01UL << SCU_TRAP_TRAPRAW_UVCOLCKT_Pos) /*!< SCU_TRAP TRAPRAW: UVCOLCKT Mask */
\r
5447 #define SCU_TRAP_TRAPRAW_PET_Pos 4 /*!< SCU_TRAP TRAPRAW: PET Position */
\r
5448 #define SCU_TRAP_TRAPRAW_PET_Msk (0x01UL << SCU_TRAP_TRAPRAW_PET_Pos) /*!< SCU_TRAP TRAPRAW: PET Mask */
\r
5449 #define SCU_TRAP_TRAPRAW_BRWNT_Pos 5 /*!< SCU_TRAP TRAPRAW: BRWNT Position */
\r
5450 #define SCU_TRAP_TRAPRAW_BRWNT_Msk (0x01UL << SCU_TRAP_TRAPRAW_BRWNT_Pos) /*!< SCU_TRAP TRAPRAW: BRWNT Mask */
\r
5451 #define SCU_TRAP_TRAPRAW_ULPWDGT_Pos 6 /*!< SCU_TRAP TRAPRAW: ULPWDGT Position */
\r
5452 #define SCU_TRAP_TRAPRAW_ULPWDGT_Msk (0x01UL << SCU_TRAP_TRAPRAW_ULPWDGT_Pos) /*!< SCU_TRAP TRAPRAW: ULPWDGT Mask */
\r
5453 #define SCU_TRAP_TRAPRAW_BWERR0T_Pos 7 /*!< SCU_TRAP TRAPRAW: BWERR0T Position */
\r
5454 #define SCU_TRAP_TRAPRAW_BWERR0T_Msk (0x01UL << SCU_TRAP_TRAPRAW_BWERR0T_Pos) /*!< SCU_TRAP TRAPRAW: BWERR0T Mask */
\r
5455 #define SCU_TRAP_TRAPRAW_BWERR1T_Pos 8 /*!< SCU_TRAP TRAPRAW: BWERR1T Position */
\r
5456 #define SCU_TRAP_TRAPRAW_BWERR1T_Msk (0x01UL << SCU_TRAP_TRAPRAW_BWERR1T_Pos) /*!< SCU_TRAP TRAPRAW: BWERR1T Mask */
\r
5457 #define SCU_TRAP_TRAPRAW_TEMPHIT_Pos 12 /*!< SCU_TRAP TRAPRAW: TEMPHIT Position */
\r
5458 #define SCU_TRAP_TRAPRAW_TEMPHIT_Msk (0x01UL << SCU_TRAP_TRAPRAW_TEMPHIT_Pos) /*!< SCU_TRAP TRAPRAW: TEMPHIT Mask */
\r
5459 #define SCU_TRAP_TRAPRAW_TEMPLOT_Pos 13 /*!< SCU_TRAP TRAPRAW: TEMPLOT Position */
\r
5460 #define SCU_TRAP_TRAPRAW_TEMPLOT_Msk (0x01UL << SCU_TRAP_TRAPRAW_TEMPLOT_Pos) /*!< SCU_TRAP TRAPRAW: TEMPLOT Mask */
\r
5462 /* ------------------------------ SCU_TRAP_TRAPDIS ------------------------------ */
\r
5463 #define SCU_TRAP_TRAPDIS_SOSCWDGT_Pos 0 /*!< SCU_TRAP TRAPDIS: SOSCWDGT Position */
\r
5464 #define SCU_TRAP_TRAPDIS_SOSCWDGT_Msk (0x01UL << SCU_TRAP_TRAPDIS_SOSCWDGT_Pos) /*!< SCU_TRAP TRAPDIS: SOSCWDGT Mask */
\r
5465 #define SCU_TRAP_TRAPDIS_SVCOLCKT_Pos 2 /*!< SCU_TRAP TRAPDIS: SVCOLCKT Position */
\r
5466 #define SCU_TRAP_TRAPDIS_SVCOLCKT_Msk (0x01UL << SCU_TRAP_TRAPDIS_SVCOLCKT_Pos) /*!< SCU_TRAP TRAPDIS: SVCOLCKT Mask */
\r
5467 #define SCU_TRAP_TRAPDIS_UVCOLCKT_Pos 3 /*!< SCU_TRAP TRAPDIS: UVCOLCKT Position */
\r
5468 #define SCU_TRAP_TRAPDIS_UVCOLCKT_Msk (0x01UL << SCU_TRAP_TRAPDIS_UVCOLCKT_Pos) /*!< SCU_TRAP TRAPDIS: UVCOLCKT Mask */
\r
5469 #define SCU_TRAP_TRAPDIS_PET_Pos 4 /*!< SCU_TRAP TRAPDIS: PET Position */
\r
5470 #define SCU_TRAP_TRAPDIS_PET_Msk (0x01UL << SCU_TRAP_TRAPDIS_PET_Pos) /*!< SCU_TRAP TRAPDIS: PET Mask */
\r
5471 #define SCU_TRAP_TRAPDIS_BRWNT_Pos 5 /*!< SCU_TRAP TRAPDIS: BRWNT Position */
\r
5472 #define SCU_TRAP_TRAPDIS_BRWNT_Msk (0x01UL << SCU_TRAP_TRAPDIS_BRWNT_Pos) /*!< SCU_TRAP TRAPDIS: BRWNT Mask */
\r
5473 #define SCU_TRAP_TRAPDIS_ULPWDGT_Pos 6 /*!< SCU_TRAP TRAPDIS: ULPWDGT Position */
\r
5474 #define SCU_TRAP_TRAPDIS_ULPWDGT_Msk (0x01UL << SCU_TRAP_TRAPDIS_ULPWDGT_Pos) /*!< SCU_TRAP TRAPDIS: ULPWDGT Mask */
\r
5475 #define SCU_TRAP_TRAPDIS_BWERR0T_Pos 7 /*!< SCU_TRAP TRAPDIS: BWERR0T Position */
\r
5476 #define SCU_TRAP_TRAPDIS_BWERR0T_Msk (0x01UL << SCU_TRAP_TRAPDIS_BWERR0T_Pos) /*!< SCU_TRAP TRAPDIS: BWERR0T Mask */
\r
5477 #define SCU_TRAP_TRAPDIS_BWERR1T_Pos 8 /*!< SCU_TRAP TRAPDIS: BWERR1T Position */
\r
5478 #define SCU_TRAP_TRAPDIS_BWERR1T_Msk (0x01UL << SCU_TRAP_TRAPDIS_BWERR1T_Pos) /*!< SCU_TRAP TRAPDIS: BWERR1T Mask */
\r
5479 #define SCU_TRAP_TRAPDIS_TEMPHIT_Pos 12 /*!< SCU_TRAP TRAPDIS: TEMPHIT Position */
\r
5480 #define SCU_TRAP_TRAPDIS_TEMPHIT_Msk (0x01UL << SCU_TRAP_TRAPDIS_TEMPHIT_Pos) /*!< SCU_TRAP TRAPDIS: TEMPHIT Mask */
\r
5481 #define SCU_TRAP_TRAPDIS_TEMPLOT_Pos 13 /*!< SCU_TRAP TRAPDIS: TEMPLOT Position */
\r
5482 #define SCU_TRAP_TRAPDIS_TEMPLOT_Msk (0x01UL << SCU_TRAP_TRAPDIS_TEMPLOT_Pos) /*!< SCU_TRAP TRAPDIS: TEMPLOT Mask */
\r
5484 /* ------------------------------ SCU_TRAP_TRAPCLR ------------------------------ */
\r
5485 #define SCU_TRAP_TRAPCLR_SOSCWDGT_Pos 0 /*!< SCU_TRAP TRAPCLR: SOSCWDGT Position */
\r
5486 #define SCU_TRAP_TRAPCLR_SOSCWDGT_Msk (0x01UL << SCU_TRAP_TRAPCLR_SOSCWDGT_Pos) /*!< SCU_TRAP TRAPCLR: SOSCWDGT Mask */
\r
5487 #define SCU_TRAP_TRAPCLR_SVCOLCKT_Pos 2 /*!< SCU_TRAP TRAPCLR: SVCOLCKT Position */
\r
5488 #define SCU_TRAP_TRAPCLR_SVCOLCKT_Msk (0x01UL << SCU_TRAP_TRAPCLR_SVCOLCKT_Pos) /*!< SCU_TRAP TRAPCLR: SVCOLCKT Mask */
\r
5489 #define SCU_TRAP_TRAPCLR_UVCOLCKT_Pos 3 /*!< SCU_TRAP TRAPCLR: UVCOLCKT Position */
\r
5490 #define SCU_TRAP_TRAPCLR_UVCOLCKT_Msk (0x01UL << SCU_TRAP_TRAPCLR_UVCOLCKT_Pos) /*!< SCU_TRAP TRAPCLR: UVCOLCKT Mask */
\r
5491 #define SCU_TRAP_TRAPCLR_PET_Pos 4 /*!< SCU_TRAP TRAPCLR: PET Position */
\r
5492 #define SCU_TRAP_TRAPCLR_PET_Msk (0x01UL << SCU_TRAP_TRAPCLR_PET_Pos) /*!< SCU_TRAP TRAPCLR: PET Mask */
\r
5493 #define SCU_TRAP_TRAPCLR_BRWNT_Pos 5 /*!< SCU_TRAP TRAPCLR: BRWNT Position */
\r
5494 #define SCU_TRAP_TRAPCLR_BRWNT_Msk (0x01UL << SCU_TRAP_TRAPCLR_BRWNT_Pos) /*!< SCU_TRAP TRAPCLR: BRWNT Mask */
\r
5495 #define SCU_TRAP_TRAPCLR_ULPWDGT_Pos 6 /*!< SCU_TRAP TRAPCLR: ULPWDGT Position */
\r
5496 #define SCU_TRAP_TRAPCLR_ULPWDGT_Msk (0x01UL << SCU_TRAP_TRAPCLR_ULPWDGT_Pos) /*!< SCU_TRAP TRAPCLR: ULPWDGT Mask */
\r
5497 #define SCU_TRAP_TRAPCLR_BWERR0T_Pos 7 /*!< SCU_TRAP TRAPCLR: BWERR0T Position */
\r
5498 #define SCU_TRAP_TRAPCLR_BWERR0T_Msk (0x01UL << SCU_TRAP_TRAPCLR_BWERR0T_Pos) /*!< SCU_TRAP TRAPCLR: BWERR0T Mask */
\r
5499 #define SCU_TRAP_TRAPCLR_BWERR1T_Pos 8 /*!< SCU_TRAP TRAPCLR: BWERR1T Position */
\r
5500 #define SCU_TRAP_TRAPCLR_BWERR1T_Msk (0x01UL << SCU_TRAP_TRAPCLR_BWERR1T_Pos) /*!< SCU_TRAP TRAPCLR: BWERR1T Mask */
\r
5501 #define SCU_TRAP_TRAPCLR_TEMPHIT_Pos 12 /*!< SCU_TRAP TRAPCLR: TEMPHIT Position */
\r
5502 #define SCU_TRAP_TRAPCLR_TEMPHIT_Msk (0x01UL << SCU_TRAP_TRAPCLR_TEMPHIT_Pos) /*!< SCU_TRAP TRAPCLR: TEMPHIT Mask */
\r
5503 #define SCU_TRAP_TRAPCLR_TEMPLOT_Pos 13 /*!< SCU_TRAP TRAPCLR: TEMPLOT Position */
\r
5504 #define SCU_TRAP_TRAPCLR_TEMPLOT_Msk (0x01UL << SCU_TRAP_TRAPCLR_TEMPLOT_Pos) /*!< SCU_TRAP TRAPCLR: TEMPLOT Mask */
\r
5506 /* ------------------------------ SCU_TRAP_TRAPSET ------------------------------ */
\r
5507 #define SCU_TRAP_TRAPSET_SOSCWDGT_Pos 0 /*!< SCU_TRAP TRAPSET: SOSCWDGT Position */
\r
5508 #define SCU_TRAP_TRAPSET_SOSCWDGT_Msk (0x01UL << SCU_TRAP_TRAPSET_SOSCWDGT_Pos) /*!< SCU_TRAP TRAPSET: SOSCWDGT Mask */
\r
5509 #define SCU_TRAP_TRAPSET_SVCOLCKT_Pos 2 /*!< SCU_TRAP TRAPSET: SVCOLCKT Position */
\r
5510 #define SCU_TRAP_TRAPSET_SVCOLCKT_Msk (0x01UL << SCU_TRAP_TRAPSET_SVCOLCKT_Pos) /*!< SCU_TRAP TRAPSET: SVCOLCKT Mask */
\r
5511 #define SCU_TRAP_TRAPSET_UVCOLCKT_Pos 3 /*!< SCU_TRAP TRAPSET: UVCOLCKT Position */
\r
5512 #define SCU_TRAP_TRAPSET_UVCOLCKT_Msk (0x01UL << SCU_TRAP_TRAPSET_UVCOLCKT_Pos) /*!< SCU_TRAP TRAPSET: UVCOLCKT Mask */
\r
5513 #define SCU_TRAP_TRAPSET_PET_Pos 4 /*!< SCU_TRAP TRAPSET: PET Position */
\r
5514 #define SCU_TRAP_TRAPSET_PET_Msk (0x01UL << SCU_TRAP_TRAPSET_PET_Pos) /*!< SCU_TRAP TRAPSET: PET Mask */
\r
5515 #define SCU_TRAP_TRAPSET_BRWNT_Pos 5 /*!< SCU_TRAP TRAPSET: BRWNT Position */
\r
5516 #define SCU_TRAP_TRAPSET_BRWNT_Msk (0x01UL << SCU_TRAP_TRAPSET_BRWNT_Pos) /*!< SCU_TRAP TRAPSET: BRWNT Mask */
\r
5517 #define SCU_TRAP_TRAPSET_ULPWDT_Pos 6 /*!< SCU_TRAP TRAPSET: ULPWDT Position */
\r
5518 #define SCU_TRAP_TRAPSET_ULPWDT_Msk (0x01UL << SCU_TRAP_TRAPSET_ULPWDT_Pos) /*!< SCU_TRAP TRAPSET: ULPWDT Mask */
\r
5519 #define SCU_TRAP_TRAPSET_BWERR0T_Pos 7 /*!< SCU_TRAP TRAPSET: BWERR0T Position */
\r
5520 #define SCU_TRAP_TRAPSET_BWERR0T_Msk (0x01UL << SCU_TRAP_TRAPSET_BWERR0T_Pos) /*!< SCU_TRAP TRAPSET: BWERR0T Mask */
\r
5521 #define SCU_TRAP_TRAPSET_BWERR1T_Pos 8 /*!< SCU_TRAP TRAPSET: BWERR1T Position */
\r
5522 #define SCU_TRAP_TRAPSET_BWERR1T_Msk (0x01UL << SCU_TRAP_TRAPSET_BWERR1T_Pos) /*!< SCU_TRAP TRAPSET: BWERR1T Mask */
\r
5523 #define SCU_TRAP_TRAPSET_TEMPHIT_Pos 12 /*!< SCU_TRAP TRAPSET: TEMPHIT Position */
\r
5524 #define SCU_TRAP_TRAPSET_TEMPHIT_Msk (0x01UL << SCU_TRAP_TRAPSET_TEMPHIT_Pos) /*!< SCU_TRAP TRAPSET: TEMPHIT Mask */
\r
5525 #define SCU_TRAP_TRAPSET_TEMPLOT_Pos 13 /*!< SCU_TRAP TRAPSET: TEMPLOT Position */
\r
5526 #define SCU_TRAP_TRAPSET_TEMPLOT_Msk (0x01UL << SCU_TRAP_TRAPSET_TEMPLOT_Pos) /*!< SCU_TRAP TRAPSET: TEMPLOT Mask */
\r
5529 /* ================================================================================ */
\r
5530 /* ================ struct 'SCU_HIBERNATE' Position & Mask ================ */
\r
5531 /* ================================================================================ */
\r
5534 /* ---------------------------- SCU_HIBERNATE_HDSTAT ---------------------------- */
\r
5535 #define SCU_HIBERNATE_HDSTAT_EPEV_Pos 0 /*!< SCU_HIBERNATE HDSTAT: EPEV Position */
\r
5536 #define SCU_HIBERNATE_HDSTAT_EPEV_Msk (0x01UL << SCU_HIBERNATE_HDSTAT_EPEV_Pos) /*!< SCU_HIBERNATE HDSTAT: EPEV Mask */
\r
5537 #define SCU_HIBERNATE_HDSTAT_ENEV_Pos 1 /*!< SCU_HIBERNATE HDSTAT: ENEV Position */
\r
5538 #define SCU_HIBERNATE_HDSTAT_ENEV_Msk (0x01UL << SCU_HIBERNATE_HDSTAT_ENEV_Pos) /*!< SCU_HIBERNATE HDSTAT: ENEV Mask */
\r
5539 #define SCU_HIBERNATE_HDSTAT_RTCEV_Pos 2 /*!< SCU_HIBERNATE HDSTAT: RTCEV Position */
\r
5540 #define SCU_HIBERNATE_HDSTAT_RTCEV_Msk (0x01UL << SCU_HIBERNATE_HDSTAT_RTCEV_Pos) /*!< SCU_HIBERNATE HDSTAT: RTCEV Mask */
\r
5541 #define SCU_HIBERNATE_HDSTAT_ULPWDG_Pos 3 /*!< SCU_HIBERNATE HDSTAT: ULPWDG Position */
\r
5542 #define SCU_HIBERNATE_HDSTAT_ULPWDG_Msk (0x01UL << SCU_HIBERNATE_HDSTAT_ULPWDG_Pos) /*!< SCU_HIBERNATE HDSTAT: ULPWDG Mask */
\r
5543 #define SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos 4 /*!< SCU_HIBERNATE HDSTAT: HIBNOUT Position */
\r
5544 #define SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk (0x01UL << SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos) /*!< SCU_HIBERNATE HDSTAT: HIBNOUT Mask */
\r
5545 #define SCU_HIBERNATE_HDSTAT_VBATPEV_Pos 8 /*!< SCU_HIBERNATE HDSTAT: VBATPEV Position */
\r
5546 #define SCU_HIBERNATE_HDSTAT_VBATPEV_Msk (0x01UL << SCU_HIBERNATE_HDSTAT_VBATPEV_Pos) /*!< SCU_HIBERNATE HDSTAT: VBATPEV Mask */
\r
5547 #define SCU_HIBERNATE_HDSTAT_VBATNEV_Pos 9 /*!< SCU_HIBERNATE HDSTAT: VBATNEV Position */
\r
5548 #define SCU_HIBERNATE_HDSTAT_VBATNEV_Msk (0x01UL << SCU_HIBERNATE_HDSTAT_VBATNEV_Pos) /*!< SCU_HIBERNATE HDSTAT: VBATNEV Mask */
\r
5549 #define SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos 10 /*!< SCU_HIBERNATE HDSTAT: AHIBIO0PEV Position */
\r
5550 #define SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Msk (0x01UL << SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0PEV Mask */
\r
5551 #define SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos 11 /*!< SCU_HIBERNATE HDSTAT: AHIBIO0NEV Position */
\r
5552 #define SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Msk (0x01UL << SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0NEV Mask */
\r
5553 #define SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Pos 12 /*!< SCU_HIBERNATE HDSTAT: AHIBIO1PEV Position */
\r
5554 #define SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Msk (0x01UL << SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Pos) /*!< SCU_HIBERNATE HDSTAT: AHIBIO1PEV Mask */
\r
5555 #define SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Pos 13 /*!< SCU_HIBERNATE HDSTAT: AHIBIO1NEV Position */
\r
5556 #define SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Msk (0x01UL << SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Pos) /*!< SCU_HIBERNATE HDSTAT: AHIBIO1NEV Mask */
\r
5558 /* ----------------------------- SCU_HIBERNATE_HDCLR ---------------------------- */
\r
5559 #define SCU_HIBERNATE_HDCLR_EPEV_Pos 0 /*!< SCU_HIBERNATE HDCLR: EPEV Position */
\r
5560 #define SCU_HIBERNATE_HDCLR_EPEV_Msk (0x01UL << SCU_HIBERNATE_HDCLR_EPEV_Pos) /*!< SCU_HIBERNATE HDCLR: EPEV Mask */
\r
5561 #define SCU_HIBERNATE_HDCLR_ENEV_Pos 1 /*!< SCU_HIBERNATE HDCLR: ENEV Position */
\r
5562 #define SCU_HIBERNATE_HDCLR_ENEV_Msk (0x01UL << SCU_HIBERNATE_HDCLR_ENEV_Pos) /*!< SCU_HIBERNATE HDCLR: ENEV Mask */
\r
5563 #define SCU_HIBERNATE_HDCLR_RTCEV_Pos 2 /*!< SCU_HIBERNATE HDCLR: RTCEV Position */
\r
5564 #define SCU_HIBERNATE_HDCLR_RTCEV_Msk (0x01UL << SCU_HIBERNATE_HDCLR_RTCEV_Pos) /*!< SCU_HIBERNATE HDCLR: RTCEV Mask */
\r
5565 #define SCU_HIBERNATE_HDCLR_ULPWDG_Pos 3 /*!< SCU_HIBERNATE HDCLR: ULPWDG Position */
\r
5566 #define SCU_HIBERNATE_HDCLR_ULPWDG_Msk (0x01UL << SCU_HIBERNATE_HDCLR_ULPWDG_Pos) /*!< SCU_HIBERNATE HDCLR: ULPWDG Mask */
\r
5567 #define SCU_HIBERNATE_HDCLR_VBATPEV_Pos 8 /*!< SCU_HIBERNATE HDCLR: VBATPEV Position */
\r
5568 #define SCU_HIBERNATE_HDCLR_VBATPEV_Msk (0x01UL << SCU_HIBERNATE_HDCLR_VBATPEV_Pos) /*!< SCU_HIBERNATE HDCLR: VBATPEV Mask */
\r
5569 #define SCU_HIBERNATE_HDCLR_VBATNEV_Pos 9 /*!< SCU_HIBERNATE HDCLR: VBATNEV Position */
\r
5570 #define SCU_HIBERNATE_HDCLR_VBATNEV_Msk (0x01UL << SCU_HIBERNATE_HDCLR_VBATNEV_Pos) /*!< SCU_HIBERNATE HDCLR: VBATNEV Mask */
\r
5571 #define SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Pos 10 /*!< SCU_HIBERNATE HDCLR: AHIBIO0PEV Position */
\r
5572 #define SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Msk (0x01UL << SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Pos) /*!< SCU_HIBERNATE HDCLR: AHIBIO0PEV Mask */
\r
5573 #define SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Pos 11 /*!< SCU_HIBERNATE HDCLR: AHIBIO0NEV Position */
\r
5574 #define SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Msk (0x01UL << SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Pos) /*!< SCU_HIBERNATE HDCLR: AHIBIO0NEV Mask */
\r
5575 #define SCU_HIBERNATE_HDCLR_AHIBIO1PEV_Pos 12 /*!< SCU_HIBERNATE HDCLR: AHIBIO1PEV Position */
\r
5576 #define SCU_HIBERNATE_HDCLR_AHIBIO1PEV_Msk (0x01UL << SCU_HIBERNATE_HDCLR_AHIBIO1PEV_Pos) /*!< SCU_HIBERNATE HDCLR: AHIBIO1PEV Mask */
\r
5577 #define SCU_HIBERNATE_HDCLR_AHIBIO1NEV_Pos 13 /*!< SCU_HIBERNATE HDCLR: AHIBIO1NEV Position */
\r
5578 #define SCU_HIBERNATE_HDCLR_AHIBIO1NEV_Msk (0x01UL << SCU_HIBERNATE_HDCLR_AHIBIO1NEV_Pos) /*!< SCU_HIBERNATE HDCLR: AHIBIO1NEV Mask */
\r
5580 /* ----------------------------- SCU_HIBERNATE_HDSET ---------------------------- */
\r
5581 #define SCU_HIBERNATE_HDSET_EPEV_Pos 0 /*!< SCU_HIBERNATE HDSET: EPEV Position */
\r
5582 #define SCU_HIBERNATE_HDSET_EPEV_Msk (0x01UL << SCU_HIBERNATE_HDSET_EPEV_Pos) /*!< SCU_HIBERNATE HDSET: EPEV Mask */
\r
5583 #define SCU_HIBERNATE_HDSET_ENEV_Pos 1 /*!< SCU_HIBERNATE HDSET: ENEV Position */
\r
5584 #define SCU_HIBERNATE_HDSET_ENEV_Msk (0x01UL << SCU_HIBERNATE_HDSET_ENEV_Pos) /*!< SCU_HIBERNATE HDSET: ENEV Mask */
\r
5585 #define SCU_HIBERNATE_HDSET_RTCEV_Pos 2 /*!< SCU_HIBERNATE HDSET: RTCEV Position */
\r
5586 #define SCU_HIBERNATE_HDSET_RTCEV_Msk (0x01UL << SCU_HIBERNATE_HDSET_RTCEV_Pos) /*!< SCU_HIBERNATE HDSET: RTCEV Mask */
\r
5587 #define SCU_HIBERNATE_HDSET_ULPWDG_Pos 3 /*!< SCU_HIBERNATE HDSET: ULPWDG Position */
\r
5588 #define SCU_HIBERNATE_HDSET_ULPWDG_Msk (0x01UL << SCU_HIBERNATE_HDSET_ULPWDG_Pos) /*!< SCU_HIBERNATE HDSET: ULPWDG Mask */
\r
5589 #define SCU_HIBERNATE_HDSET_VBATPEV_Pos 8 /*!< SCU_HIBERNATE HDSET: VBATPEV Position */
\r
5590 #define SCU_HIBERNATE_HDSET_VBATPEV_Msk (0x01UL << SCU_HIBERNATE_HDSET_VBATPEV_Pos) /*!< SCU_HIBERNATE HDSET: VBATPEV Mask */
\r
5591 #define SCU_HIBERNATE_HDSET_VBATNEV_Pos 9 /*!< SCU_HIBERNATE HDSET: VBATNEV Position */
\r
5592 #define SCU_HIBERNATE_HDSET_VBATNEV_Msk (0x01UL << SCU_HIBERNATE_HDSET_VBATNEV_Pos) /*!< SCU_HIBERNATE HDSET: VBATNEV Mask */
\r
5593 #define SCU_HIBERNATE_HDSET_AHIBIO0PEV_Pos 10 /*!< SCU_HIBERNATE HDSET: AHIBIO0PEV Position */
\r
5594 #define SCU_HIBERNATE_HDSET_AHIBIO0PEV_Msk (0x01UL << SCU_HIBERNATE_HDSET_AHIBIO0PEV_Pos) /*!< SCU_HIBERNATE HDSET: AHIBIO0PEV Mask */
\r
5595 #define SCU_HIBERNATE_HDSET_AHIBIO0NEV_Pos 11 /*!< SCU_HIBERNATE HDSET: AHIBIO0NEV Position */
\r
5596 #define SCU_HIBERNATE_HDSET_AHIBIO0NEV_Msk (0x01UL << SCU_HIBERNATE_HDSET_AHIBIO0NEV_Pos) /*!< SCU_HIBERNATE HDSET: AHIBIO0NEV Mask */
\r
5597 #define SCU_HIBERNATE_HDSET_AHIBIO1PEV_Pos 12 /*!< SCU_HIBERNATE HDSET: AHIBIO1PEV Position */
\r
5598 #define SCU_HIBERNATE_HDSET_AHIBIO1PEV_Msk (0x01UL << SCU_HIBERNATE_HDSET_AHIBIO1PEV_Pos) /*!< SCU_HIBERNATE HDSET: AHIBIO1PEV Mask */
\r
5599 #define SCU_HIBERNATE_HDSET_AHIBIO1NEV_Pos 13 /*!< SCU_HIBERNATE HDSET: AHIBIO1NEV Position */
\r
5600 #define SCU_HIBERNATE_HDSET_AHIBIO1NEV_Msk (0x01UL << SCU_HIBERNATE_HDSET_AHIBIO1NEV_Pos) /*!< SCU_HIBERNATE HDSET: AHIBIO1NEV Mask */
\r
5602 /* ----------------------------- SCU_HIBERNATE_HDCR ----------------------------- */
\r
5603 #define SCU_HIBERNATE_HDCR_WKPEP_Pos 0 /*!< SCU_HIBERNATE HDCR: WKPEP Position */
\r
5604 #define SCU_HIBERNATE_HDCR_WKPEP_Msk (0x01UL << SCU_HIBERNATE_HDCR_WKPEP_Pos) /*!< SCU_HIBERNATE HDCR: WKPEP Mask */
\r
5605 #define SCU_HIBERNATE_HDCR_WKPEN_Pos 1 /*!< SCU_HIBERNATE HDCR: WKPEN Position */
\r
5606 #define SCU_HIBERNATE_HDCR_WKPEN_Msk (0x01UL << SCU_HIBERNATE_HDCR_WKPEN_Pos) /*!< SCU_HIBERNATE HDCR: WKPEN Mask */
\r
5607 #define SCU_HIBERNATE_HDCR_RTCE_Pos 2 /*!< SCU_HIBERNATE HDCR: RTCE Position */
\r
5608 #define SCU_HIBERNATE_HDCR_RTCE_Msk (0x01UL << SCU_HIBERNATE_HDCR_RTCE_Pos) /*!< SCU_HIBERNATE HDCR: RTCE Mask */
\r
5609 #define SCU_HIBERNATE_HDCR_ULPWDGEN_Pos 3 /*!< SCU_HIBERNATE HDCR: ULPWDGEN Position */
\r
5610 #define SCU_HIBERNATE_HDCR_ULPWDGEN_Msk (0x01UL << SCU_HIBERNATE_HDCR_ULPWDGEN_Pos) /*!< SCU_HIBERNATE HDCR: ULPWDGEN Mask */
\r
5611 #define SCU_HIBERNATE_HDCR_HIB_Pos 4 /*!< SCU_HIBERNATE HDCR: HIB Position */
\r
5612 #define SCU_HIBERNATE_HDCR_HIB_Msk (0x01UL << SCU_HIBERNATE_HDCR_HIB_Pos) /*!< SCU_HIBERNATE HDCR: HIB Mask */
\r
5613 #define SCU_HIBERNATE_HDCR_XTALGPI1SEL_Pos 5 /*!< SCU_HIBERNATE HDCR: XTALGPI1SEL Position */
\r
5614 #define SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk (0x01UL << SCU_HIBERNATE_HDCR_XTALGPI1SEL_Pos) /*!< SCU_HIBERNATE HDCR: XTALGPI1SEL Mask */
\r
5615 #define SCU_HIBERNATE_HDCR_RCS_Pos 6 /*!< SCU_HIBERNATE HDCR: RCS Position */
\r
5616 #define SCU_HIBERNATE_HDCR_RCS_Msk (0x01UL << SCU_HIBERNATE_HDCR_RCS_Pos) /*!< SCU_HIBERNATE HDCR: RCS Mask */
\r
5617 #define SCU_HIBERNATE_HDCR_STDBYSEL_Pos 7 /*!< SCU_HIBERNATE HDCR: STDBYSEL Position */
\r
5618 #define SCU_HIBERNATE_HDCR_STDBYSEL_Msk (0x01UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos) /*!< SCU_HIBERNATE HDCR: STDBYSEL Mask */
\r
5619 #define SCU_HIBERNATE_HDCR_WKUPSEL_Pos 8 /*!< SCU_HIBERNATE HDCR: WKUPSEL Position */
\r
5620 #define SCU_HIBERNATE_HDCR_WKUPSEL_Msk (0x01UL << SCU_HIBERNATE_HDCR_WKUPSEL_Pos) /*!< SCU_HIBERNATE HDCR: WKUPSEL Mask */
\r
5621 #define SCU_HIBERNATE_HDCR_GPI0SEL_Pos 10 /*!< SCU_HIBERNATE HDCR: GPI0SEL Position */
\r
5622 #define SCU_HIBERNATE_HDCR_GPI0SEL_Msk (0x01UL << SCU_HIBERNATE_HDCR_GPI0SEL_Pos) /*!< SCU_HIBERNATE HDCR: GPI0SEL Mask */
\r
5623 #define SCU_HIBERNATE_HDCR_GPI1SEL_Pos 11 /*!< SCU_HIBERNATE HDCR: GPI1SEL Position */
\r
5624 #define SCU_HIBERNATE_HDCR_GPI1SEL_Msk (0x01UL << SCU_HIBERNATE_HDCR_GPI1SEL_Pos) /*!< SCU_HIBERNATE HDCR: GPI1SEL Mask */
\r
5625 #define SCU_HIBERNATE_HDCR_HIBIO0POL_Pos 12 /*!< SCU_HIBERNATE HDCR: HIBIO0POL Position */
\r
5626 #define SCU_HIBERNATE_HDCR_HIBIO0POL_Msk (0x01UL << SCU_HIBERNATE_HDCR_HIBIO0POL_Pos) /*!< SCU_HIBERNATE HDCR: HIBIO0POL Mask */
\r
5627 #define SCU_HIBERNATE_HDCR_HIBIO1POL_Pos 13 /*!< SCU_HIBERNATE HDCR: HIBIO1POL Position */
\r
5628 #define SCU_HIBERNATE_HDCR_HIBIO1POL_Msk (0x01UL << SCU_HIBERNATE_HDCR_HIBIO1POL_Pos) /*!< SCU_HIBERNATE HDCR: HIBIO1POL Mask */
\r
5629 #define SCU_HIBERNATE_HDCR_ADIG0SEL_Pos 14 /*!< SCU_HIBERNATE HDCR: ADIG0SEL Position */
\r
5630 #define SCU_HIBERNATE_HDCR_ADIG0SEL_Msk (0x01UL << SCU_HIBERNATE_HDCR_ADIG0SEL_Pos) /*!< SCU_HIBERNATE HDCR: ADIG0SEL Mask */
\r
5631 #define SCU_HIBERNATE_HDCR_ADIG1SEL_Pos 15 /*!< SCU_HIBERNATE HDCR: ADIG1SEL Position */
\r
5632 #define SCU_HIBERNATE_HDCR_ADIG1SEL_Msk (0x01UL << SCU_HIBERNATE_HDCR_ADIG1SEL_Pos) /*!< SCU_HIBERNATE HDCR: ADIG1SEL Mask */
\r
5633 #define SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos 16 /*!< SCU_HIBERNATE HDCR: HIBIO0SEL Position */
\r
5634 #define SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk (0x0fUL << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos) /*!< SCU_HIBERNATE HDCR: HIBIO0SEL Mask */
\r
5635 #define SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos 20 /*!< SCU_HIBERNATE HDCR: HIBIO1SEL Position */
\r
5636 #define SCU_HIBERNATE_HDCR_HIBIO1SEL_Msk (0x0fUL << SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos) /*!< SCU_HIBERNATE HDCR: HIBIO1SEL Mask */
\r
5637 #define SCU_HIBERNATE_HDCR_VBATLO_Pos 24 /*!< SCU_HIBERNATE HDCR: VBATLO Position */
\r
5638 #define SCU_HIBERNATE_HDCR_VBATLO_Msk (0x01UL << SCU_HIBERNATE_HDCR_VBATLO_Pos) /*!< SCU_HIBERNATE HDCR: VBATLO Mask */
\r
5639 #define SCU_HIBERNATE_HDCR_VBATHI_Pos 25 /*!< SCU_HIBERNATE HDCR: VBATHI Position */
\r
5640 #define SCU_HIBERNATE_HDCR_VBATHI_Msk (0x01UL << SCU_HIBERNATE_HDCR_VBATHI_Pos) /*!< SCU_HIBERNATE HDCR: VBATHI Mask */
\r
5641 #define SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos 26 /*!< SCU_HIBERNATE HDCR: AHIBIO0LO Position */
\r
5642 #define SCU_HIBERNATE_HDCR_AHIBIO0LO_Msk (0x01UL << SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos) /*!< SCU_HIBERNATE HDCR: AHIBIO0LO Mask */
\r
5643 #define SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos 27 /*!< SCU_HIBERNATE HDCR: AHIBIO0HI Position */
\r
5644 #define SCU_HIBERNATE_HDCR_AHIBIO0HI_Msk (0x01UL << SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos) /*!< SCU_HIBERNATE HDCR: AHIBIO0HI Mask */
\r
5645 #define SCU_HIBERNATE_HDCR_AHIBIO1LO_Pos 28 /*!< SCU_HIBERNATE HDCR: AHIBIO1LO Position */
\r
5646 #define SCU_HIBERNATE_HDCR_AHIBIO1LO_Msk (0x01UL << SCU_HIBERNATE_HDCR_AHIBIO1LO_Pos) /*!< SCU_HIBERNATE HDCR: AHIBIO1LO Mask */
\r
5647 #define SCU_HIBERNATE_HDCR_AHIBIO1HI_Pos 29 /*!< SCU_HIBERNATE HDCR: AHIBIO1HI Position */
\r
5648 #define SCU_HIBERNATE_HDCR_AHIBIO1HI_Msk (0x01UL << SCU_HIBERNATE_HDCR_AHIBIO1HI_Pos) /*!< SCU_HIBERNATE HDCR: AHIBIO1HI Mask */
\r
5650 /* --------------------------- SCU_HIBERNATE_OSCSICTRL -------------------------- */
\r
5651 #define SCU_HIBERNATE_OSCSICTRL_PWD_Pos 0 /*!< SCU_HIBERNATE OSCSICTRL: PWD Position */
\r
5652 #define SCU_HIBERNATE_OSCSICTRL_PWD_Msk (0x01UL << SCU_HIBERNATE_OSCSICTRL_PWD_Pos) /*!< SCU_HIBERNATE OSCSICTRL: PWD Mask */
\r
5654 /* --------------------------- SCU_HIBERNATE_OSCULSTAT -------------------------- */
\r
5655 #define SCU_HIBERNATE_OSCULSTAT_X1D_Pos 0 /*!< SCU_HIBERNATE OSCULSTAT: X1D Position */
\r
5656 #define SCU_HIBERNATE_OSCULSTAT_X1D_Msk (0x01UL << SCU_HIBERNATE_OSCULSTAT_X1D_Pos) /*!< SCU_HIBERNATE OSCULSTAT: X1D Mask */
\r
5658 /* --------------------------- SCU_HIBERNATE_OSCULCTRL -------------------------- */
\r
5659 #define SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos 0 /*!< SCU_HIBERNATE OSCULCTRL: X1DEN Position */
\r
5660 #define SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk (0x01UL << SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos) /*!< SCU_HIBERNATE OSCULCTRL: X1DEN Mask */
\r
5661 #define SCU_HIBERNATE_OSCULCTRL_MODE_Pos 4 /*!< SCU_HIBERNATE OSCULCTRL: MODE Position */
\r
5662 #define SCU_HIBERNATE_OSCULCTRL_MODE_Msk (0x03UL << SCU_HIBERNATE_OSCULCTRL_MODE_Pos) /*!< SCU_HIBERNATE OSCULCTRL: MODE Mask */
\r
5664 /* --------------------------- SCU_HIBERNATE_LPACCONF --------------------------- */
\r
5665 #define SCU_HIBERNATE_LPACCONF_CMPEN_Pos 0 /*!< SCU_HIBERNATE LPACCONF: CMPEN Position */
\r
5666 #define SCU_HIBERNATE_LPACCONF_CMPEN_Msk (0x07UL << SCU_HIBERNATE_LPACCONF_CMPEN_Pos) /*!< SCU_HIBERNATE LPACCONF: CMPEN Mask */
\r
5667 #define SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos 4 /*!< SCU_HIBERNATE LPACCONF: TRIGSEL Position */
\r
5668 #define SCU_HIBERNATE_LPACCONF_TRIGSEL_Msk (0x07UL << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos) /*!< SCU_HIBERNATE LPACCONF: TRIGSEL Mask */
\r
5669 #define SCU_HIBERNATE_LPACCONF_CONVDEL_Pos 12 /*!< SCU_HIBERNATE LPACCONF: CONVDEL Position */
\r
5670 #define SCU_HIBERNATE_LPACCONF_CONVDEL_Msk (0x01UL << SCU_HIBERNATE_LPACCONF_CONVDEL_Pos) /*!< SCU_HIBERNATE LPACCONF: CONVDEL Mask */
\r
5671 #define SCU_HIBERNATE_LPACCONF_INTERVCNT_Pos 16 /*!< SCU_HIBERNATE LPACCONF: INTERVCNT Position */
\r
5672 #define SCU_HIBERNATE_LPACCONF_INTERVCNT_Msk (0x00000fffUL << SCU_HIBERNATE_LPACCONF_INTERVCNT_Pos) /*!< SCU_HIBERNATE LPACCONF: INTERVCNT Mask */
\r
5673 #define SCU_HIBERNATE_LPACCONF_SETTLECNT_Pos 28 /*!< SCU_HIBERNATE LPACCONF: SETTLECNT Position */
\r
5674 #define SCU_HIBERNATE_LPACCONF_SETTLECNT_Msk (0x0fUL << SCU_HIBERNATE_LPACCONF_SETTLECNT_Pos) /*!< SCU_HIBERNATE LPACCONF: SETTLECNT Mask */
\r
5676 /* ---------------------------- SCU_HIBERNATE_LPACTH0 --------------------------- */
\r
5677 #define SCU_HIBERNATE_LPACTH0_VBATLO_Pos 0 /*!< SCU_HIBERNATE LPACTH0: VBATLO Position */
\r
5678 #define SCU_HIBERNATE_LPACTH0_VBATLO_Msk (0x3fUL << SCU_HIBERNATE_LPACTH0_VBATLO_Pos) /*!< SCU_HIBERNATE LPACTH0: VBATLO Mask */
\r
5679 #define SCU_HIBERNATE_LPACTH0_VBATHI_Pos 8 /*!< SCU_HIBERNATE LPACTH0: VBATHI Position */
\r
5680 #define SCU_HIBERNATE_LPACTH0_VBATHI_Msk (0x3fUL << SCU_HIBERNATE_LPACTH0_VBATHI_Pos) /*!< SCU_HIBERNATE LPACTH0: VBATHI Mask */
\r
5682 /* ---------------------------- SCU_HIBERNATE_LPACTH1 --------------------------- */
\r
5683 #define SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Pos 0 /*!< SCU_HIBERNATE LPACTH1: AHIBIO0LO Position */
\r
5684 #define SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Msk (0x3fUL << SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Pos) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0LO Mask */
\r
5685 #define SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Pos 8 /*!< SCU_HIBERNATE LPACTH1: AHIBIO0HI Position */
\r
5686 #define SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Msk (0x3fUL << SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Pos) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0HI Mask */
\r
5687 #define SCU_HIBERNATE_LPACTH1_AHIBIO1LO_Pos 16 /*!< SCU_HIBERNATE LPACTH1: AHIBIO1LO Position */
\r
5688 #define SCU_HIBERNATE_LPACTH1_AHIBIO1LO_Msk (0x3fUL << SCU_HIBERNATE_LPACTH1_AHIBIO1LO_Pos) /*!< SCU_HIBERNATE LPACTH1: AHIBIO1LO Mask */
\r
5689 #define SCU_HIBERNATE_LPACTH1_AHIBIO1HI_Pos 24 /*!< SCU_HIBERNATE LPACTH1: AHIBIO1HI Position */
\r
5690 #define SCU_HIBERNATE_LPACTH1_AHIBIO1HI_Msk (0x3fUL << SCU_HIBERNATE_LPACTH1_AHIBIO1HI_Pos) /*!< SCU_HIBERNATE LPACTH1: AHIBIO1HI Mask */
\r
5692 /* ---------------------------- SCU_HIBERNATE_LPACST ---------------------------- */
\r
5693 #define SCU_HIBERNATE_LPACST_VBATSCMP_Pos 0 /*!< SCU_HIBERNATE LPACST: VBATSCMP Position */
\r
5694 #define SCU_HIBERNATE_LPACST_VBATSCMP_Msk (0x01UL << SCU_HIBERNATE_LPACST_VBATSCMP_Pos) /*!< SCU_HIBERNATE LPACST: VBATSCMP Mask */
\r
5695 #define SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Pos 1 /*!< SCU_HIBERNATE LPACST: AHIBIO0SCMP Position */
\r
5696 #define SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Msk (0x01UL << SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Pos) /*!< SCU_HIBERNATE LPACST: AHIBIO0SCMP Mask */
\r
5697 #define SCU_HIBERNATE_LPACST_AHIBIO1SCMP_Pos 2 /*!< SCU_HIBERNATE LPACST: AHIBIO1SCMP Position */
\r
5698 #define SCU_HIBERNATE_LPACST_AHIBIO1SCMP_Msk (0x01UL << SCU_HIBERNATE_LPACST_AHIBIO1SCMP_Pos) /*!< SCU_HIBERNATE LPACST: AHIBIO1SCMP Mask */
\r
5699 #define SCU_HIBERNATE_LPACST_VBATVAL_Pos 16 /*!< SCU_HIBERNATE LPACST: VBATVAL Position */
\r
5700 #define SCU_HIBERNATE_LPACST_VBATVAL_Msk (0x01UL << SCU_HIBERNATE_LPACST_VBATVAL_Pos) /*!< SCU_HIBERNATE LPACST: VBATVAL Mask */
\r
5701 #define SCU_HIBERNATE_LPACST_AHIBIO0VAL_Pos 17 /*!< SCU_HIBERNATE LPACST: AHIBIO0VAL Position */
\r
5702 #define SCU_HIBERNATE_LPACST_AHIBIO0VAL_Msk (0x01UL << SCU_HIBERNATE_LPACST_AHIBIO0VAL_Pos) /*!< SCU_HIBERNATE LPACST: AHIBIO0VAL Mask */
\r
5703 #define SCU_HIBERNATE_LPACST_AHIBIO1VAL_Pos 18 /*!< SCU_HIBERNATE LPACST: AHIBIO1VAL Position */
\r
5704 #define SCU_HIBERNATE_LPACST_AHIBIO1VAL_Msk (0x01UL << SCU_HIBERNATE_LPACST_AHIBIO1VAL_Pos) /*!< SCU_HIBERNATE LPACST: AHIBIO1VAL Mask */
\r
5706 /* ---------------------------- SCU_HIBERNATE_LPACCLR --------------------------- */
\r
5707 #define SCU_HIBERNATE_LPACCLR_VBATSCMP_Pos 0 /*!< SCU_HIBERNATE LPACCLR: VBATSCMP Position */
\r
5708 #define SCU_HIBERNATE_LPACCLR_VBATSCMP_Msk (0x01UL << SCU_HIBERNATE_LPACCLR_VBATSCMP_Pos) /*!< SCU_HIBERNATE LPACCLR: VBATSCMP Mask */
\r
5709 #define SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Pos 1 /*!< SCU_HIBERNATE LPACCLR: AHIBIO0SCMP Position */
\r
5710 #define SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Msk (0x01UL << SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Pos) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0SCMP Mask */
\r
5711 #define SCU_HIBERNATE_LPACCLR_AHIBIO1SCMP_Pos 2 /*!< SCU_HIBERNATE LPACCLR: AHIBIO1SCMP Position */
\r
5712 #define SCU_HIBERNATE_LPACCLR_AHIBIO1SCMP_Msk (0x01UL << SCU_HIBERNATE_LPACCLR_AHIBIO1SCMP_Pos) /*!< SCU_HIBERNATE LPACCLR: AHIBIO1SCMP Mask */
\r
5713 #define SCU_HIBERNATE_LPACCLR_VBATVAL_Pos 16 /*!< SCU_HIBERNATE LPACCLR: VBATVAL Position */
\r
5714 #define SCU_HIBERNATE_LPACCLR_VBATVAL_Msk (0x01UL << SCU_HIBERNATE_LPACCLR_VBATVAL_Pos) /*!< SCU_HIBERNATE LPACCLR: VBATVAL Mask */
\r
5715 #define SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Pos 17 /*!< SCU_HIBERNATE LPACCLR: AHIBIO0VAL Position */
\r
5716 #define SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Msk (0x01UL << SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Pos) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0VAL Mask */
\r
5717 #define SCU_HIBERNATE_LPACCLR_AHIBIO1VAL_Pos 18 /*!< SCU_HIBERNATE LPACCLR: AHIBIO1VAL Position */
\r
5718 #define SCU_HIBERNATE_LPACCLR_AHIBIO1VAL_Msk (0x01UL << SCU_HIBERNATE_LPACCLR_AHIBIO1VAL_Pos) /*!< SCU_HIBERNATE LPACCLR: AHIBIO1VAL Mask */
\r
5720 /* ---------------------------- SCU_HIBERNATE_LPACSET --------------------------- */
\r
5721 #define SCU_HIBERNATE_LPACSET_VBATSCMP_Pos 0 /*!< SCU_HIBERNATE LPACSET: VBATSCMP Position */
\r
5722 #define SCU_HIBERNATE_LPACSET_VBATSCMP_Msk (0x01UL << SCU_HIBERNATE_LPACSET_VBATSCMP_Pos) /*!< SCU_HIBERNATE LPACSET: VBATSCMP Mask */
\r
5723 #define SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Pos 1 /*!< SCU_HIBERNATE LPACSET: AHIBIO0SCMP Position */
\r
5724 #define SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Msk (0x01UL << SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Pos) /*!< SCU_HIBERNATE LPACSET: AHIBIO0SCMP Mask */
\r
5725 #define SCU_HIBERNATE_LPACSET_AHIBIO1SCMP_Pos 2 /*!< SCU_HIBERNATE LPACSET: AHIBIO1SCMP Position */
\r
5726 #define SCU_HIBERNATE_LPACSET_AHIBIO1SCMP_Msk (0x01UL << SCU_HIBERNATE_LPACSET_AHIBIO1SCMP_Pos) /*!< SCU_HIBERNATE LPACSET: AHIBIO1SCMP Mask */
\r
5727 #define SCU_HIBERNATE_LPACSET_VBATVAL_Pos 16 /*!< SCU_HIBERNATE LPACSET: VBATVAL Position */
\r
5728 #define SCU_HIBERNATE_LPACSET_VBATVAL_Msk (0x01UL << SCU_HIBERNATE_LPACSET_VBATVAL_Pos) /*!< SCU_HIBERNATE LPACSET: VBATVAL Mask */
\r
5729 #define SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Pos 17 /*!< SCU_HIBERNATE LPACSET: AHIBIO0VAL Position */
\r
5730 #define SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Msk (0x01UL << SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Pos) /*!< SCU_HIBERNATE LPACSET: AHIBIO0VAL Mask */
\r
5731 #define SCU_HIBERNATE_LPACSET_AHIBIO1VAL_Pos 18 /*!< SCU_HIBERNATE LPACSET: AHIBIO1VAL Position */
\r
5732 #define SCU_HIBERNATE_LPACSET_AHIBIO1VAL_Msk (0x01UL << SCU_HIBERNATE_LPACSET_AHIBIO1VAL_Pos) /*!< SCU_HIBERNATE LPACSET: AHIBIO1VAL Mask */
\r
5734 /* ---------------------------- SCU_HIBERNATE_HINTST ---------------------------- */
\r
5735 #define SCU_HIBERNATE_HINTST_HIBNINT_Pos 0 /*!< SCU_HIBERNATE HINTST: HIBNINT Position */
\r
5736 #define SCU_HIBERNATE_HINTST_HIBNINT_Msk (0x01UL << SCU_HIBERNATE_HINTST_HIBNINT_Pos) /*!< SCU_HIBERNATE HINTST: HIBNINT Mask */
\r
5737 #define SCU_HIBERNATE_HINTST_FLASHOFF_Pos 2 /*!< SCU_HIBERNATE HINTST: FLASHOFF Position */
\r
5738 #define SCU_HIBERNATE_HINTST_FLASHOFF_Msk (0x01UL << SCU_HIBERNATE_HINTST_FLASHOFF_Pos) /*!< SCU_HIBERNATE HINTST: FLASHOFF Mask */
\r
5739 #define SCU_HIBERNATE_HINTST_FLASHPD_Pos 3 /*!< SCU_HIBERNATE HINTST: FLASHPD Position */
\r
5740 #define SCU_HIBERNATE_HINTST_FLASHPD_Msk (0x01UL << SCU_HIBERNATE_HINTST_FLASHPD_Pos) /*!< SCU_HIBERNATE HINTST: FLASHPD Mask */
\r
5741 #define SCU_HIBERNATE_HINTST_POFFD_Pos 4 /*!< SCU_HIBERNATE HINTST: POFFD Position */
\r
5742 #define SCU_HIBERNATE_HINTST_POFFD_Msk (0x01UL << SCU_HIBERNATE_HINTST_POFFD_Pos) /*!< SCU_HIBERNATE HINTST: POFFD Mask */
\r
5743 #define SCU_HIBERNATE_HINTST_PPODEL_Pos 16 /*!< SCU_HIBERNATE HINTST: PPODEL Position */
\r
5744 #define SCU_HIBERNATE_HINTST_PPODEL_Msk (0x03UL << SCU_HIBERNATE_HINTST_PPODEL_Pos) /*!< SCU_HIBERNATE HINTST: PPODEL Mask */
\r
5745 #define SCU_HIBERNATE_HINTST_POFFH_Pos 20 /*!< SCU_HIBERNATE HINTST: POFFH Position */
\r
5746 #define SCU_HIBERNATE_HINTST_POFFH_Msk (0x01UL << SCU_HIBERNATE_HINTST_POFFH_Pos) /*!< SCU_HIBERNATE HINTST: POFFH Mask */
\r
5748 /* ---------------------------- SCU_HIBERNATE_HINTCLR --------------------------- */
\r
5749 #define SCU_HIBERNATE_HINTCLR_HIBNINT_Pos 0 /*!< SCU_HIBERNATE HINTCLR: HIBNINT Position */
\r
5750 #define SCU_HIBERNATE_HINTCLR_HIBNINT_Msk (0x01UL << SCU_HIBERNATE_HINTCLR_HIBNINT_Pos) /*!< SCU_HIBERNATE HINTCLR: HIBNINT Mask */
\r
5751 #define SCU_HIBERNATE_HINTCLR_FLASHOFF_Pos 2 /*!< SCU_HIBERNATE HINTCLR: FLASHOFF Position */
\r
5752 #define SCU_HIBERNATE_HINTCLR_FLASHOFF_Msk (0x01UL << SCU_HIBERNATE_HINTCLR_FLASHOFF_Pos) /*!< SCU_HIBERNATE HINTCLR: FLASHOFF Mask */
\r
5753 #define SCU_HIBERNATE_HINTCLR_FLASHPD_Pos 3 /*!< SCU_HIBERNATE HINTCLR: FLASHPD Position */
\r
5754 #define SCU_HIBERNATE_HINTCLR_FLASHPD_Msk (0x01UL << SCU_HIBERNATE_HINTCLR_FLASHPD_Pos) /*!< SCU_HIBERNATE HINTCLR: FLASHPD Mask */
\r
5755 #define SCU_HIBERNATE_HINTCLR_POFFD_Pos 4 /*!< SCU_HIBERNATE HINTCLR: POFFD Position */
\r
5756 #define SCU_HIBERNATE_HINTCLR_POFFD_Msk (0x01UL << SCU_HIBERNATE_HINTCLR_POFFD_Pos) /*!< SCU_HIBERNATE HINTCLR: POFFD Mask */
\r
5757 #define SCU_HIBERNATE_HINTCLR_PPODEL_Pos 16 /*!< SCU_HIBERNATE HINTCLR: PPODEL Position */
\r
5758 #define SCU_HIBERNATE_HINTCLR_PPODEL_Msk (0x03UL << SCU_HIBERNATE_HINTCLR_PPODEL_Pos) /*!< SCU_HIBERNATE HINTCLR: PPODEL Mask */
\r
5759 #define SCU_HIBERNATE_HINTCLR_POFFH_Pos 20 /*!< SCU_HIBERNATE HINTCLR: POFFH Position */
\r
5760 #define SCU_HIBERNATE_HINTCLR_POFFH_Msk (0x01UL << SCU_HIBERNATE_HINTCLR_POFFH_Pos) /*!< SCU_HIBERNATE HINTCLR: POFFH Mask */
\r
5762 /* ---------------------------- SCU_HIBERNATE_HINTSET --------------------------- */
\r
5763 #define SCU_HIBERNATE_HINTSET_HIBNINT_Pos 0 /*!< SCU_HIBERNATE HINTSET: HIBNINT Position */
\r
5764 #define SCU_HIBERNATE_HINTSET_HIBNINT_Msk (0x01UL << SCU_HIBERNATE_HINTSET_HIBNINT_Pos) /*!< SCU_HIBERNATE HINTSET: HIBNINT Mask */
\r
5765 #define SCU_HIBERNATE_HINTSET_VCOREOFF_Pos 1 /*!< SCU_HIBERNATE HINTSET: VCOREOFF Position */
\r
5766 #define SCU_HIBERNATE_HINTSET_VCOREOFF_Msk (0x01UL << SCU_HIBERNATE_HINTSET_VCOREOFF_Pos) /*!< SCU_HIBERNATE HINTSET: VCOREOFF Mask */
\r
5767 #define SCU_HIBERNATE_HINTSET_FLASHOFF_Pos 2 /*!< SCU_HIBERNATE HINTSET: FLASHOFF Position */
\r
5768 #define SCU_HIBERNATE_HINTSET_FLASHOFF_Msk (0x01UL << SCU_HIBERNATE_HINTSET_FLASHOFF_Pos) /*!< SCU_HIBERNATE HINTSET: FLASHOFF Mask */
\r
5769 #define SCU_HIBERNATE_HINTSET_FLASHPD_Pos 3 /*!< SCU_HIBERNATE HINTSET: FLASHPD Position */
\r
5770 #define SCU_HIBERNATE_HINTSET_FLASHPD_Msk (0x01UL << SCU_HIBERNATE_HINTSET_FLASHPD_Pos) /*!< SCU_HIBERNATE HINTSET: FLASHPD Mask */
\r
5771 #define SCU_HIBERNATE_HINTSET_POFFD_Pos 4 /*!< SCU_HIBERNATE HINTSET: POFFD Position */
\r
5772 #define SCU_HIBERNATE_HINTSET_POFFD_Msk (0x01UL << SCU_HIBERNATE_HINTSET_POFFD_Pos) /*!< SCU_HIBERNATE HINTSET: POFFD Mask */
\r
5773 #define SCU_HIBERNATE_HINTSET_PPODEL_Pos 16 /*!< SCU_HIBERNATE HINTSET: PPODEL Position */
\r
5774 #define SCU_HIBERNATE_HINTSET_PPODEL_Msk (0x03UL << SCU_HIBERNATE_HINTSET_PPODEL_Pos) /*!< SCU_HIBERNATE HINTSET: PPODEL Mask */
\r
5775 #define SCU_HIBERNATE_HINTSET_POFFH_Pos 20 /*!< SCU_HIBERNATE HINTSET: POFFH Position */
\r
5776 #define SCU_HIBERNATE_HINTSET_POFFH_Msk (0x01UL << SCU_HIBERNATE_HINTSET_POFFH_Pos) /*!< SCU_HIBERNATE HINTSET: POFFH Mask */
\r
5779 /* ================================================================================ */
\r
5780 /* ================ struct 'SCU_POWER' Position & Mask ================ */
\r
5781 /* ================================================================================ */
\r
5784 /* ------------------------------ SCU_POWER_PWRSTAT ----------------------------- */
\r
5785 #define SCU_POWER_PWRSTAT_HIBEN_Pos 0 /*!< SCU_POWER PWRSTAT: HIBEN Position */
\r
5786 #define SCU_POWER_PWRSTAT_HIBEN_Msk (0x01UL << SCU_POWER_PWRSTAT_HIBEN_Pos) /*!< SCU_POWER PWRSTAT: HIBEN Mask */
\r
5787 #define SCU_POWER_PWRSTAT_USBPHYPDQ_Pos 16 /*!< SCU_POWER PWRSTAT: USBPHYPDQ Position */
\r
5788 #define SCU_POWER_PWRSTAT_USBPHYPDQ_Msk (0x01UL << SCU_POWER_PWRSTAT_USBPHYPDQ_Pos) /*!< SCU_POWER PWRSTAT: USBPHYPDQ Mask */
\r
5789 #define SCU_POWER_PWRSTAT_USBOTGEN_Pos 17 /*!< SCU_POWER PWRSTAT: USBOTGEN Position */
\r
5790 #define SCU_POWER_PWRSTAT_USBOTGEN_Msk (0x01UL << SCU_POWER_PWRSTAT_USBOTGEN_Pos) /*!< SCU_POWER PWRSTAT: USBOTGEN Mask */
\r
5791 #define SCU_POWER_PWRSTAT_USBPUWQ_Pos 18 /*!< SCU_POWER PWRSTAT: USBPUWQ Position */
\r
5792 #define SCU_POWER_PWRSTAT_USBPUWQ_Msk (0x01UL << SCU_POWER_PWRSTAT_USBPUWQ_Pos) /*!< SCU_POWER PWRSTAT: USBPUWQ Mask */
\r
5794 /* ------------------------------ SCU_POWER_PWRSET ------------------------------ */
\r
5795 #define SCU_POWER_PWRSET_HIB_Pos 0 /*!< SCU_POWER PWRSET: HIB Position */
\r
5796 #define SCU_POWER_PWRSET_HIB_Msk (0x01UL << SCU_POWER_PWRSET_HIB_Pos) /*!< SCU_POWER PWRSET: HIB Mask */
\r
5797 #define SCU_POWER_PWRSET_USBPHYPDQ_Pos 16 /*!< SCU_POWER PWRSET: USBPHYPDQ Position */
\r
5798 #define SCU_POWER_PWRSET_USBPHYPDQ_Msk (0x01UL << SCU_POWER_PWRSET_USBPHYPDQ_Pos) /*!< SCU_POWER PWRSET: USBPHYPDQ Mask */
\r
5799 #define SCU_POWER_PWRSET_USBOTGEN_Pos 17 /*!< SCU_POWER PWRSET: USBOTGEN Position */
\r
5800 #define SCU_POWER_PWRSET_USBOTGEN_Msk (0x01UL << SCU_POWER_PWRSET_USBOTGEN_Pos) /*!< SCU_POWER PWRSET: USBOTGEN Mask */
\r
5801 #define SCU_POWER_PWRSET_USBPUWQ_Pos 18 /*!< SCU_POWER PWRSET: USBPUWQ Position */
\r
5802 #define SCU_POWER_PWRSET_USBPUWQ_Msk (0x01UL << SCU_POWER_PWRSET_USBPUWQ_Pos) /*!< SCU_POWER PWRSET: USBPUWQ Mask */
\r
5804 /* ------------------------------ SCU_POWER_PWRCLR ------------------------------ */
\r
5805 #define SCU_POWER_PWRCLR_HIB_Pos 0 /*!< SCU_POWER PWRCLR: HIB Position */
\r
5806 #define SCU_POWER_PWRCLR_HIB_Msk (0x01UL << SCU_POWER_PWRCLR_HIB_Pos) /*!< SCU_POWER PWRCLR: HIB Mask */
\r
5807 #define SCU_POWER_PWRCLR_USBPHYPDQ_Pos 16 /*!< SCU_POWER PWRCLR: USBPHYPDQ Position */
\r
5808 #define SCU_POWER_PWRCLR_USBPHYPDQ_Msk (0x01UL << SCU_POWER_PWRCLR_USBPHYPDQ_Pos) /*!< SCU_POWER PWRCLR: USBPHYPDQ Mask */
\r
5809 #define SCU_POWER_PWRCLR_USBOTGEN_Pos 17 /*!< SCU_POWER PWRCLR: USBOTGEN Position */
\r
5810 #define SCU_POWER_PWRCLR_USBOTGEN_Msk (0x01UL << SCU_POWER_PWRCLR_USBOTGEN_Pos) /*!< SCU_POWER PWRCLR: USBOTGEN Mask */
\r
5811 #define SCU_POWER_PWRCLR_USBPUWQ_Pos 18 /*!< SCU_POWER PWRCLR: USBPUWQ Position */
\r
5812 #define SCU_POWER_PWRCLR_USBPUWQ_Msk (0x01UL << SCU_POWER_PWRCLR_USBPUWQ_Pos) /*!< SCU_POWER PWRCLR: USBPUWQ Mask */
\r
5814 /* ------------------------------ SCU_POWER_EVRSTAT ----------------------------- */
\r
5815 #define SCU_POWER_EVRSTAT_OV13_Pos 1 /*!< SCU_POWER EVRSTAT: OV13 Position */
\r
5816 #define SCU_POWER_EVRSTAT_OV13_Msk (0x01UL << SCU_POWER_EVRSTAT_OV13_Pos) /*!< SCU_POWER EVRSTAT: OV13 Mask */
\r
5818 /* ---------------------------- SCU_POWER_EVRVADCSTAT --------------------------- */
\r
5819 #define SCU_POWER_EVRVADCSTAT_VADC13V_Pos 0 /*!< SCU_POWER EVRVADCSTAT: VADC13V Position */
\r
5820 #define SCU_POWER_EVRVADCSTAT_VADC13V_Msk (0x000000ffUL << SCU_POWER_EVRVADCSTAT_VADC13V_Pos) /*!< SCU_POWER EVRVADCSTAT: VADC13V Mask */
\r
5821 #define SCU_POWER_EVRVADCSTAT_VADC33V_Pos 8 /*!< SCU_POWER EVRVADCSTAT: VADC33V Position */
\r
5822 #define SCU_POWER_EVRVADCSTAT_VADC33V_Msk (0x000000ffUL << SCU_POWER_EVRVADCSTAT_VADC33V_Pos) /*!< SCU_POWER EVRVADCSTAT: VADC33V Mask */
\r
5824 /* ------------------------------ SCU_POWER_PWRMON ------------------------------ */
\r
5825 #define SCU_POWER_PWRMON_THRS_Pos 0 /*!< SCU_POWER PWRMON: THRS Position */
\r
5826 #define SCU_POWER_PWRMON_THRS_Msk (0x000000ffUL << SCU_POWER_PWRMON_THRS_Pos) /*!< SCU_POWER PWRMON: THRS Mask */
\r
5827 #define SCU_POWER_PWRMON_INTV_Pos 8 /*!< SCU_POWER PWRMON: INTV Position */
\r
5828 #define SCU_POWER_PWRMON_INTV_Msk (0x000000ffUL << SCU_POWER_PWRMON_INTV_Pos) /*!< SCU_POWER PWRMON: INTV Mask */
\r
5829 #define SCU_POWER_PWRMON_ENB_Pos 16 /*!< SCU_POWER PWRMON: ENB Position */
\r
5830 #define SCU_POWER_PWRMON_ENB_Msk (0x01UL << SCU_POWER_PWRMON_ENB_Pos) /*!< SCU_POWER PWRMON: ENB Mask */
\r
5833 /* ================================================================================ */
\r
5834 /* ================ struct 'SCU_RESET' Position & Mask ================ */
\r
5835 /* ================================================================================ */
\r
5838 /* ------------------------------ SCU_RESET_RSTSTAT ----------------------------- */
\r
5839 #define SCU_RESET_RSTSTAT_RSTSTAT_Pos 0 /*!< SCU_RESET RSTSTAT: RSTSTAT Position */
\r
5840 #define SCU_RESET_RSTSTAT_RSTSTAT_Msk (0x000000ffUL << SCU_RESET_RSTSTAT_RSTSTAT_Pos) /*!< SCU_RESET RSTSTAT: RSTSTAT Mask */
\r
5841 #define SCU_RESET_RSTSTAT_HIBWK_Pos 8 /*!< SCU_RESET RSTSTAT: HIBWK Position */
\r
5842 #define SCU_RESET_RSTSTAT_HIBWK_Msk (0x01UL << SCU_RESET_RSTSTAT_HIBWK_Pos) /*!< SCU_RESET RSTSTAT: HIBWK Mask */
\r
5843 #define SCU_RESET_RSTSTAT_HIBRS_Pos 9 /*!< SCU_RESET RSTSTAT: HIBRS Position */
\r
5844 #define SCU_RESET_RSTSTAT_HIBRS_Msk (0x01UL << SCU_RESET_RSTSTAT_HIBRS_Pos) /*!< SCU_RESET RSTSTAT: HIBRS Mask */
\r
5845 #define SCU_RESET_RSTSTAT_LCKEN_Pos 10 /*!< SCU_RESET RSTSTAT: LCKEN Position */
\r
5846 #define SCU_RESET_RSTSTAT_LCKEN_Msk (0x01UL << SCU_RESET_RSTSTAT_LCKEN_Pos) /*!< SCU_RESET RSTSTAT: LCKEN Mask */
\r
5848 /* ------------------------------ SCU_RESET_RSTSET ------------------------------ */
\r
5849 #define SCU_RESET_RSTSET_HIBWK_Pos 8 /*!< SCU_RESET RSTSET: HIBWK Position */
\r
5850 #define SCU_RESET_RSTSET_HIBWK_Msk (0x01UL << SCU_RESET_RSTSET_HIBWK_Pos) /*!< SCU_RESET RSTSET: HIBWK Mask */
\r
5851 #define SCU_RESET_RSTSET_HIBRS_Pos 9 /*!< SCU_RESET RSTSET: HIBRS Position */
\r
5852 #define SCU_RESET_RSTSET_HIBRS_Msk (0x01UL << SCU_RESET_RSTSET_HIBRS_Pos) /*!< SCU_RESET RSTSET: HIBRS Mask */
\r
5853 #define SCU_RESET_RSTSET_LCKEN_Pos 10 /*!< SCU_RESET RSTSET: LCKEN Position */
\r
5854 #define SCU_RESET_RSTSET_LCKEN_Msk (0x01UL << SCU_RESET_RSTSET_LCKEN_Pos) /*!< SCU_RESET RSTSET: LCKEN Mask */
\r
5856 /* ------------------------------ SCU_RESET_RSTCLR ------------------------------ */
\r
5857 #define SCU_RESET_RSTCLR_RSCLR_Pos 0 /*!< SCU_RESET RSTCLR: RSCLR Position */
\r
5858 #define SCU_RESET_RSTCLR_RSCLR_Msk (0x01UL << SCU_RESET_RSTCLR_RSCLR_Pos) /*!< SCU_RESET RSTCLR: RSCLR Mask */
\r
5859 #define SCU_RESET_RSTCLR_HIBWK_Pos 8 /*!< SCU_RESET RSTCLR: HIBWK Position */
\r
5860 #define SCU_RESET_RSTCLR_HIBWK_Msk (0x01UL << SCU_RESET_RSTCLR_HIBWK_Pos) /*!< SCU_RESET RSTCLR: HIBWK Mask */
\r
5861 #define SCU_RESET_RSTCLR_HIBRS_Pos 9 /*!< SCU_RESET RSTCLR: HIBRS Position */
\r
5862 #define SCU_RESET_RSTCLR_HIBRS_Msk (0x01UL << SCU_RESET_RSTCLR_HIBRS_Pos) /*!< SCU_RESET RSTCLR: HIBRS Mask */
\r
5863 #define SCU_RESET_RSTCLR_LCKEN_Pos 10 /*!< SCU_RESET RSTCLR: LCKEN Position */
\r
5864 #define SCU_RESET_RSTCLR_LCKEN_Msk (0x01UL << SCU_RESET_RSTCLR_LCKEN_Pos) /*!< SCU_RESET RSTCLR: LCKEN Mask */
\r
5866 /* ------------------------------ SCU_RESET_PRSTAT0 ----------------------------- */
\r
5867 #define SCU_RESET_PRSTAT0_VADCRS_Pos 0 /*!< SCU_RESET PRSTAT0: VADCRS Position */
\r
5868 #define SCU_RESET_PRSTAT0_VADCRS_Msk (0x01UL << SCU_RESET_PRSTAT0_VADCRS_Pos) /*!< SCU_RESET PRSTAT0: VADCRS Mask */
\r
5869 #define SCU_RESET_PRSTAT0_DSDRS_Pos 1 /*!< SCU_RESET PRSTAT0: DSDRS Position */
\r
5870 #define SCU_RESET_PRSTAT0_DSDRS_Msk (0x01UL << SCU_RESET_PRSTAT0_DSDRS_Pos) /*!< SCU_RESET PRSTAT0: DSDRS Mask */
\r
5871 #define SCU_RESET_PRSTAT0_CCU40RS_Pos 2 /*!< SCU_RESET PRSTAT0: CCU40RS Position */
\r
5872 #define SCU_RESET_PRSTAT0_CCU40RS_Msk (0x01UL << SCU_RESET_PRSTAT0_CCU40RS_Pos) /*!< SCU_RESET PRSTAT0: CCU40RS Mask */
\r
5873 #define SCU_RESET_PRSTAT0_CCU41RS_Pos 3 /*!< SCU_RESET PRSTAT0: CCU41RS Position */
\r
5874 #define SCU_RESET_PRSTAT0_CCU41RS_Msk (0x01UL << SCU_RESET_PRSTAT0_CCU41RS_Pos) /*!< SCU_RESET PRSTAT0: CCU41RS Mask */
\r
5875 #define SCU_RESET_PRSTAT0_CCU42RS_Pos 4 /*!< SCU_RESET PRSTAT0: CCU42RS Position */
\r
5876 #define SCU_RESET_PRSTAT0_CCU42RS_Msk (0x01UL << SCU_RESET_PRSTAT0_CCU42RS_Pos) /*!< SCU_RESET PRSTAT0: CCU42RS Mask */
\r
5877 #define SCU_RESET_PRSTAT0_CCU80RS_Pos 7 /*!< SCU_RESET PRSTAT0: CCU80RS Position */
\r
5878 #define SCU_RESET_PRSTAT0_CCU80RS_Msk (0x01UL << SCU_RESET_PRSTAT0_CCU80RS_Pos) /*!< SCU_RESET PRSTAT0: CCU80RS Mask */
\r
5879 #define SCU_RESET_PRSTAT0_CCU81RS_Pos 8 /*!< SCU_RESET PRSTAT0: CCU81RS Position */
\r
5880 #define SCU_RESET_PRSTAT0_CCU81RS_Msk (0x01UL << SCU_RESET_PRSTAT0_CCU81RS_Pos) /*!< SCU_RESET PRSTAT0: CCU81RS Mask */
\r
5881 #define SCU_RESET_PRSTAT0_POSIF0RS_Pos 9 /*!< SCU_RESET PRSTAT0: POSIF0RS Position */
\r
5882 #define SCU_RESET_PRSTAT0_POSIF0RS_Msk (0x01UL << SCU_RESET_PRSTAT0_POSIF0RS_Pos) /*!< SCU_RESET PRSTAT0: POSIF0RS Mask */
\r
5883 #define SCU_RESET_PRSTAT0_POSIF1RS_Pos 10 /*!< SCU_RESET PRSTAT0: POSIF1RS Position */
\r
5884 #define SCU_RESET_PRSTAT0_POSIF1RS_Msk (0x01UL << SCU_RESET_PRSTAT0_POSIF1RS_Pos) /*!< SCU_RESET PRSTAT0: POSIF1RS Mask */
\r
5885 #define SCU_RESET_PRSTAT0_USIC0RS_Pos 11 /*!< SCU_RESET PRSTAT0: USIC0RS Position */
\r
5886 #define SCU_RESET_PRSTAT0_USIC0RS_Msk (0x01UL << SCU_RESET_PRSTAT0_USIC0RS_Pos) /*!< SCU_RESET PRSTAT0: USIC0RS Mask */
\r
5887 #define SCU_RESET_PRSTAT0_ERU1RS_Pos 16 /*!< SCU_RESET PRSTAT0: ERU1RS Position */
\r
5888 #define SCU_RESET_PRSTAT0_ERU1RS_Msk (0x01UL << SCU_RESET_PRSTAT0_ERU1RS_Pos) /*!< SCU_RESET PRSTAT0: ERU1RS Mask */
\r
5889 #define SCU_RESET_PRSTAT0_HRPWM0RS_Pos 23 /*!< SCU_RESET PRSTAT0: HRPWM0RS Position */
\r
5890 #define SCU_RESET_PRSTAT0_HRPWM0RS_Msk (0x01UL << SCU_RESET_PRSTAT0_HRPWM0RS_Pos) /*!< SCU_RESET PRSTAT0: HRPWM0RS Mask */
\r
5892 /* ------------------------------ SCU_RESET_PRSET0 ------------------------------ */
\r
5893 #define SCU_RESET_PRSET0_VADCRS_Pos 0 /*!< SCU_RESET PRSET0: VADCRS Position */
\r
5894 #define SCU_RESET_PRSET0_VADCRS_Msk (0x01UL << SCU_RESET_PRSET0_VADCRS_Pos) /*!< SCU_RESET PRSET0: VADCRS Mask */
\r
5895 #define SCU_RESET_PRSET0_DSDRS_Pos 1 /*!< SCU_RESET PRSET0: DSDRS Position */
\r
5896 #define SCU_RESET_PRSET0_DSDRS_Msk (0x01UL << SCU_RESET_PRSET0_DSDRS_Pos) /*!< SCU_RESET PRSET0: DSDRS Mask */
\r
5897 #define SCU_RESET_PRSET0_CCU40RS_Pos 2 /*!< SCU_RESET PRSET0: CCU40RS Position */
\r
5898 #define SCU_RESET_PRSET0_CCU40RS_Msk (0x01UL << SCU_RESET_PRSET0_CCU40RS_Pos) /*!< SCU_RESET PRSET0: CCU40RS Mask */
\r
5899 #define SCU_RESET_PRSET0_CCU41RS_Pos 3 /*!< SCU_RESET PRSET0: CCU41RS Position */
\r
5900 #define SCU_RESET_PRSET0_CCU41RS_Msk (0x01UL << SCU_RESET_PRSET0_CCU41RS_Pos) /*!< SCU_RESET PRSET0: CCU41RS Mask */
\r
5901 #define SCU_RESET_PRSET0_CCU42RS_Pos 4 /*!< SCU_RESET PRSET0: CCU42RS Position */
\r
5902 #define SCU_RESET_PRSET0_CCU42RS_Msk (0x01UL << SCU_RESET_PRSET0_CCU42RS_Pos) /*!< SCU_RESET PRSET0: CCU42RS Mask */
\r
5903 #define SCU_RESET_PRSET0_CCU80RS_Pos 7 /*!< SCU_RESET PRSET0: CCU80RS Position */
\r
5904 #define SCU_RESET_PRSET0_CCU80RS_Msk (0x01UL << SCU_RESET_PRSET0_CCU80RS_Pos) /*!< SCU_RESET PRSET0: CCU80RS Mask */
\r
5905 #define SCU_RESET_PRSET0_CCU81RS_Pos 8 /*!< SCU_RESET PRSET0: CCU81RS Position */
\r
5906 #define SCU_RESET_PRSET0_CCU81RS_Msk (0x01UL << SCU_RESET_PRSET0_CCU81RS_Pos) /*!< SCU_RESET PRSET0: CCU81RS Mask */
\r
5907 #define SCU_RESET_PRSET0_POSIF0RS_Pos 9 /*!< SCU_RESET PRSET0: POSIF0RS Position */
\r
5908 #define SCU_RESET_PRSET0_POSIF0RS_Msk (0x01UL << SCU_RESET_PRSET0_POSIF0RS_Pos) /*!< SCU_RESET PRSET0: POSIF0RS Mask */
\r
5909 #define SCU_RESET_PRSET0_POSIF1RS_Pos 10 /*!< SCU_RESET PRSET0: POSIF1RS Position */
\r
5910 #define SCU_RESET_PRSET0_POSIF1RS_Msk (0x01UL << SCU_RESET_PRSET0_POSIF1RS_Pos) /*!< SCU_RESET PRSET0: POSIF1RS Mask */
\r
5911 #define SCU_RESET_PRSET0_USIC0RS_Pos 11 /*!< SCU_RESET PRSET0: USIC0RS Position */
\r
5912 #define SCU_RESET_PRSET0_USIC0RS_Msk (0x01UL << SCU_RESET_PRSET0_USIC0RS_Pos) /*!< SCU_RESET PRSET0: USIC0RS Mask */
\r
5913 #define SCU_RESET_PRSET0_ERU1RS_Pos 16 /*!< SCU_RESET PRSET0: ERU1RS Position */
\r
5914 #define SCU_RESET_PRSET0_ERU1RS_Msk (0x01UL << SCU_RESET_PRSET0_ERU1RS_Pos) /*!< SCU_RESET PRSET0: ERU1RS Mask */
\r
5915 #define SCU_RESET_PRSET0_HRPWM0RS_Pos 23 /*!< SCU_RESET PRSET0: HRPWM0RS Position */
\r
5916 #define SCU_RESET_PRSET0_HRPWM0RS_Msk (0x01UL << SCU_RESET_PRSET0_HRPWM0RS_Pos) /*!< SCU_RESET PRSET0: HRPWM0RS Mask */
\r
5918 /* ------------------------------ SCU_RESET_PRCLR0 ------------------------------ */
\r
5919 #define SCU_RESET_PRCLR0_VADCRS_Pos 0 /*!< SCU_RESET PRCLR0: VADCRS Position */
\r
5920 #define SCU_RESET_PRCLR0_VADCRS_Msk (0x01UL << SCU_RESET_PRCLR0_VADCRS_Pos) /*!< SCU_RESET PRCLR0: VADCRS Mask */
\r
5921 #define SCU_RESET_PRCLR0_DSDRS_Pos 1 /*!< SCU_RESET PRCLR0: DSDRS Position */
\r
5922 #define SCU_RESET_PRCLR0_DSDRS_Msk (0x01UL << SCU_RESET_PRCLR0_DSDRS_Pos) /*!< SCU_RESET PRCLR0: DSDRS Mask */
\r
5923 #define SCU_RESET_PRCLR0_CCU40RS_Pos 2 /*!< SCU_RESET PRCLR0: CCU40RS Position */
\r
5924 #define SCU_RESET_PRCLR0_CCU40RS_Msk (0x01UL << SCU_RESET_PRCLR0_CCU40RS_Pos) /*!< SCU_RESET PRCLR0: CCU40RS Mask */
\r
5925 #define SCU_RESET_PRCLR0_CCU41RS_Pos 3 /*!< SCU_RESET PRCLR0: CCU41RS Position */
\r
5926 #define SCU_RESET_PRCLR0_CCU41RS_Msk (0x01UL << SCU_RESET_PRCLR0_CCU41RS_Pos) /*!< SCU_RESET PRCLR0: CCU41RS Mask */
\r
5927 #define SCU_RESET_PRCLR0_CCU42RS_Pos 4 /*!< SCU_RESET PRCLR0: CCU42RS Position */
\r
5928 #define SCU_RESET_PRCLR0_CCU42RS_Msk (0x01UL << SCU_RESET_PRCLR0_CCU42RS_Pos) /*!< SCU_RESET PRCLR0: CCU42RS Mask */
\r
5929 #define SCU_RESET_PRCLR0_CCU80RS_Pos 7 /*!< SCU_RESET PRCLR0: CCU80RS Position */
\r
5930 #define SCU_RESET_PRCLR0_CCU80RS_Msk (0x01UL << SCU_RESET_PRCLR0_CCU80RS_Pos) /*!< SCU_RESET PRCLR0: CCU80RS Mask */
\r
5931 #define SCU_RESET_PRCLR0_CCU81RS_Pos 8 /*!< SCU_RESET PRCLR0: CCU81RS Position */
\r
5932 #define SCU_RESET_PRCLR0_CCU81RS_Msk (0x01UL << SCU_RESET_PRCLR0_CCU81RS_Pos) /*!< SCU_RESET PRCLR0: CCU81RS Mask */
\r
5933 #define SCU_RESET_PRCLR0_POSIF0RS_Pos 9 /*!< SCU_RESET PRCLR0: POSIF0RS Position */
\r
5934 #define SCU_RESET_PRCLR0_POSIF0RS_Msk (0x01UL << SCU_RESET_PRCLR0_POSIF0RS_Pos) /*!< SCU_RESET PRCLR0: POSIF0RS Mask */
\r
5935 #define SCU_RESET_PRCLR0_POSIF1RS_Pos 10 /*!< SCU_RESET PRCLR0: POSIF1RS Position */
\r
5936 #define SCU_RESET_PRCLR0_POSIF1RS_Msk (0x01UL << SCU_RESET_PRCLR0_POSIF1RS_Pos) /*!< SCU_RESET PRCLR0: POSIF1RS Mask */
\r
5937 #define SCU_RESET_PRCLR0_USIC0RS_Pos 11 /*!< SCU_RESET PRCLR0: USIC0RS Position */
\r
5938 #define SCU_RESET_PRCLR0_USIC0RS_Msk (0x01UL << SCU_RESET_PRCLR0_USIC0RS_Pos) /*!< SCU_RESET PRCLR0: USIC0RS Mask */
\r
5939 #define SCU_RESET_PRCLR0_ERU1RS_Pos 16 /*!< SCU_RESET PRCLR0: ERU1RS Position */
\r
5940 #define SCU_RESET_PRCLR0_ERU1RS_Msk (0x01UL << SCU_RESET_PRCLR0_ERU1RS_Pos) /*!< SCU_RESET PRCLR0: ERU1RS Mask */
\r
5941 #define SCU_RESET_PRCLR0_HRPWM0RS_Pos 23 /*!< SCU_RESET PRCLR0: HRPWM0RS Position */
\r
5942 #define SCU_RESET_PRCLR0_HRPWM0RS_Msk (0x01UL << SCU_RESET_PRCLR0_HRPWM0RS_Pos) /*!< SCU_RESET PRCLR0: HRPWM0RS Mask */
\r
5944 /* ------------------------------ SCU_RESET_PRSTAT1 ----------------------------- */
\r
5945 #define SCU_RESET_PRSTAT1_CCU43RS_Pos 0 /*!< SCU_RESET PRSTAT1: CCU43RS Position */
\r
5946 #define SCU_RESET_PRSTAT1_CCU43RS_Msk (0x01UL << SCU_RESET_PRSTAT1_CCU43RS_Pos) /*!< SCU_RESET PRSTAT1: CCU43RS Mask */
\r
5947 #define SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos 3 /*!< SCU_RESET PRSTAT1: LEDTSCU0RS Position */
\r
5948 #define SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk (0x01UL << SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos) /*!< SCU_RESET PRSTAT1: LEDTSCU0RS Mask */
\r
5949 #define SCU_RESET_PRSTAT1_MCAN0RS_Pos 4 /*!< SCU_RESET PRSTAT1: MCAN0RS Position */
\r
5950 #define SCU_RESET_PRSTAT1_MCAN0RS_Msk (0x01UL << SCU_RESET_PRSTAT1_MCAN0RS_Pos) /*!< SCU_RESET PRSTAT1: MCAN0RS Mask */
\r
5951 #define SCU_RESET_PRSTAT1_DACRS_Pos 5 /*!< SCU_RESET PRSTAT1: DACRS Position */
\r
5952 #define SCU_RESET_PRSTAT1_DACRS_Msk (0x01UL << SCU_RESET_PRSTAT1_DACRS_Pos) /*!< SCU_RESET PRSTAT1: DACRS Mask */
\r
5953 #define SCU_RESET_PRSTAT1_USIC1RS_Pos 7 /*!< SCU_RESET PRSTAT1: USIC1RS Position */
\r
5954 #define SCU_RESET_PRSTAT1_USIC1RS_Msk (0x01UL << SCU_RESET_PRSTAT1_USIC1RS_Pos) /*!< SCU_RESET PRSTAT1: USIC1RS Mask */
\r
5955 #define SCU_RESET_PRSTAT1_PPORTSRS_Pos 9 /*!< SCU_RESET PRSTAT1: PPORTSRS Position */
\r
5956 #define SCU_RESET_PRSTAT1_PPORTSRS_Msk (0x01UL << SCU_RESET_PRSTAT1_PPORTSRS_Pos) /*!< SCU_RESET PRSTAT1: PPORTSRS Mask */
\r
5958 /* ------------------------------ SCU_RESET_PRSET1 ------------------------------ */
\r
5959 #define SCU_RESET_PRSET1_CCU43RS_Pos 0 /*!< SCU_RESET PRSET1: CCU43RS Position */
\r
5960 #define SCU_RESET_PRSET1_CCU43RS_Msk (0x01UL << SCU_RESET_PRSET1_CCU43RS_Pos) /*!< SCU_RESET PRSET1: CCU43RS Mask */
\r
5961 #define SCU_RESET_PRSET1_LEDTSCU0RS_Pos 3 /*!< SCU_RESET PRSET1: LEDTSCU0RS Position */
\r
5962 #define SCU_RESET_PRSET1_LEDTSCU0RS_Msk (0x01UL << SCU_RESET_PRSET1_LEDTSCU0RS_Pos) /*!< SCU_RESET PRSET1: LEDTSCU0RS Mask */
\r
5963 #define SCU_RESET_PRSET1_MCAN0RS_Pos 4 /*!< SCU_RESET PRSET1: MCAN0RS Position */
\r
5964 #define SCU_RESET_PRSET1_MCAN0RS_Msk (0x01UL << SCU_RESET_PRSET1_MCAN0RS_Pos) /*!< SCU_RESET PRSET1: MCAN0RS Mask */
\r
5965 #define SCU_RESET_PRSET1_DACRS_Pos 5 /*!< SCU_RESET PRSET1: DACRS Position */
\r
5966 #define SCU_RESET_PRSET1_DACRS_Msk (0x01UL << SCU_RESET_PRSET1_DACRS_Pos) /*!< SCU_RESET PRSET1: DACRS Mask */
\r
5967 #define SCU_RESET_PRSET1_USIC1RS_Pos 7 /*!< SCU_RESET PRSET1: USIC1RS Position */
\r
5968 #define SCU_RESET_PRSET1_USIC1RS_Msk (0x01UL << SCU_RESET_PRSET1_USIC1RS_Pos) /*!< SCU_RESET PRSET1: USIC1RS Mask */
\r
5969 #define SCU_RESET_PRSET1_PPORTSRS_Pos 9 /*!< SCU_RESET PRSET1: PPORTSRS Position */
\r
5970 #define SCU_RESET_PRSET1_PPORTSRS_Msk (0x01UL << SCU_RESET_PRSET1_PPORTSRS_Pos) /*!< SCU_RESET PRSET1: PPORTSRS Mask */
\r
5972 /* ------------------------------ SCU_RESET_PRCLR1 ------------------------------ */
\r
5973 #define SCU_RESET_PRCLR1_CCU43RS_Pos 0 /*!< SCU_RESET PRCLR1: CCU43RS Position */
\r
5974 #define SCU_RESET_PRCLR1_CCU43RS_Msk (0x01UL << SCU_RESET_PRCLR1_CCU43RS_Pos) /*!< SCU_RESET PRCLR1: CCU43RS Mask */
\r
5975 #define SCU_RESET_PRCLR1_LEDTSCU0RS_Pos 3 /*!< SCU_RESET PRCLR1: LEDTSCU0RS Position */
\r
5976 #define SCU_RESET_PRCLR1_LEDTSCU0RS_Msk (0x01UL << SCU_RESET_PRCLR1_LEDTSCU0RS_Pos) /*!< SCU_RESET PRCLR1: LEDTSCU0RS Mask */
\r
5977 #define SCU_RESET_PRCLR1_MCAN0RS_Pos 4 /*!< SCU_RESET PRCLR1: MCAN0RS Position */
\r
5978 #define SCU_RESET_PRCLR1_MCAN0RS_Msk (0x01UL << SCU_RESET_PRCLR1_MCAN0RS_Pos) /*!< SCU_RESET PRCLR1: MCAN0RS Mask */
\r
5979 #define SCU_RESET_PRCLR1_DACRS_Pos 5 /*!< SCU_RESET PRCLR1: DACRS Position */
\r
5980 #define SCU_RESET_PRCLR1_DACRS_Msk (0x01UL << SCU_RESET_PRCLR1_DACRS_Pos) /*!< SCU_RESET PRCLR1: DACRS Mask */
\r
5981 #define SCU_RESET_PRCLR1_USIC1RS_Pos 7 /*!< SCU_RESET PRCLR1: USIC1RS Position */
\r
5982 #define SCU_RESET_PRCLR1_USIC1RS_Msk (0x01UL << SCU_RESET_PRCLR1_USIC1RS_Pos) /*!< SCU_RESET PRCLR1: USIC1RS Mask */
\r
5983 #define SCU_RESET_PRCLR1_PPORTSRS_Pos 9 /*!< SCU_RESET PRCLR1: PPORTSRS Position */
\r
5984 #define SCU_RESET_PRCLR1_PPORTSRS_Msk (0x01UL << SCU_RESET_PRCLR1_PPORTSRS_Pos) /*!< SCU_RESET PRCLR1: PPORTSRS Mask */
\r
5986 /* ------------------------------ SCU_RESET_PRSTAT2 ----------------------------- */
\r
5987 #define SCU_RESET_PRSTAT2_WDTRS_Pos 1 /*!< SCU_RESET PRSTAT2: WDTRS Position */
\r
5988 #define SCU_RESET_PRSTAT2_WDTRS_Msk (0x01UL << SCU_RESET_PRSTAT2_WDTRS_Pos) /*!< SCU_RESET PRSTAT2: WDTRS Mask */
\r
5989 #define SCU_RESET_PRSTAT2_ETH0RS_Pos 2 /*!< SCU_RESET PRSTAT2: ETH0RS Position */
\r
5990 #define SCU_RESET_PRSTAT2_ETH0RS_Msk (0x01UL << SCU_RESET_PRSTAT2_ETH0RS_Pos) /*!< SCU_RESET PRSTAT2: ETH0RS Mask */
\r
5991 #define SCU_RESET_PRSTAT2_DMA0RS_Pos 4 /*!< SCU_RESET PRSTAT2: DMA0RS Position */
\r
5992 #define SCU_RESET_PRSTAT2_DMA0RS_Msk (0x01UL << SCU_RESET_PRSTAT2_DMA0RS_Pos) /*!< SCU_RESET PRSTAT2: DMA0RS Mask */
\r
5993 #define SCU_RESET_PRSTAT2_FCERS_Pos 6 /*!< SCU_RESET PRSTAT2: FCERS Position */
\r
5994 #define SCU_RESET_PRSTAT2_FCERS_Msk (0x01UL << SCU_RESET_PRSTAT2_FCERS_Pos) /*!< SCU_RESET PRSTAT2: FCERS Mask */
\r
5995 #define SCU_RESET_PRSTAT2_USBRS_Pos 7 /*!< SCU_RESET PRSTAT2: USBRS Position */
\r
5996 #define SCU_RESET_PRSTAT2_USBRS_Msk (0x01UL << SCU_RESET_PRSTAT2_USBRS_Pos) /*!< SCU_RESET PRSTAT2: USBRS Mask */
\r
5998 /* ------------------------------ SCU_RESET_PRSET2 ------------------------------ */
\r
5999 #define SCU_RESET_PRSET2_WDTRS_Pos 1 /*!< SCU_RESET PRSET2: WDTRS Position */
\r
6000 #define SCU_RESET_PRSET2_WDTRS_Msk (0x01UL << SCU_RESET_PRSET2_WDTRS_Pos) /*!< SCU_RESET PRSET2: WDTRS Mask */
\r
6001 #define SCU_RESET_PRSET2_ETH0RS_Pos 2 /*!< SCU_RESET PRSET2: ETH0RS Position */
\r
6002 #define SCU_RESET_PRSET2_ETH0RS_Msk (0x01UL << SCU_RESET_PRSET2_ETH0RS_Pos) /*!< SCU_RESET PRSET2: ETH0RS Mask */
\r
6003 #define SCU_RESET_PRSET2_DMA0RS_Pos 4 /*!< SCU_RESET PRSET2: DMA0RS Position */
\r
6004 #define SCU_RESET_PRSET2_DMA0RS_Msk (0x01UL << SCU_RESET_PRSET2_DMA0RS_Pos) /*!< SCU_RESET PRSET2: DMA0RS Mask */
\r
6005 #define SCU_RESET_PRSET2_FCERS_Pos 6 /*!< SCU_RESET PRSET2: FCERS Position */
\r
6006 #define SCU_RESET_PRSET2_FCERS_Msk (0x01UL << SCU_RESET_PRSET2_FCERS_Pos) /*!< SCU_RESET PRSET2: FCERS Mask */
\r
6007 #define SCU_RESET_PRSET2_USBRS_Pos 7 /*!< SCU_RESET PRSET2: USBRS Position */
\r
6008 #define SCU_RESET_PRSET2_USBRS_Msk (0x01UL << SCU_RESET_PRSET2_USBRS_Pos) /*!< SCU_RESET PRSET2: USBRS Mask */
\r
6010 /* ------------------------------ SCU_RESET_PRCLR2 ------------------------------ */
\r
6011 #define SCU_RESET_PRCLR2_WDTRS_Pos 1 /*!< SCU_RESET PRCLR2: WDTRS Position */
\r
6012 #define SCU_RESET_PRCLR2_WDTRS_Msk (0x01UL << SCU_RESET_PRCLR2_WDTRS_Pos) /*!< SCU_RESET PRCLR2: WDTRS Mask */
\r
6013 #define SCU_RESET_PRCLR2_ETH0RS_Pos 2 /*!< SCU_RESET PRCLR2: ETH0RS Position */
\r
6014 #define SCU_RESET_PRCLR2_ETH0RS_Msk (0x01UL << SCU_RESET_PRCLR2_ETH0RS_Pos) /*!< SCU_RESET PRCLR2: ETH0RS Mask */
\r
6015 #define SCU_RESET_PRCLR2_DMA0RS_Pos 4 /*!< SCU_RESET PRCLR2: DMA0RS Position */
\r
6016 #define SCU_RESET_PRCLR2_DMA0RS_Msk (0x01UL << SCU_RESET_PRCLR2_DMA0RS_Pos) /*!< SCU_RESET PRCLR2: DMA0RS Mask */
\r
6017 #define SCU_RESET_PRCLR2_FCERS_Pos 6 /*!< SCU_RESET PRCLR2: FCERS Position */
\r
6018 #define SCU_RESET_PRCLR2_FCERS_Msk (0x01UL << SCU_RESET_PRCLR2_FCERS_Pos) /*!< SCU_RESET PRCLR2: FCERS Mask */
\r
6019 #define SCU_RESET_PRCLR2_USBRS_Pos 7 /*!< SCU_RESET PRCLR2: USBRS Position */
\r
6020 #define SCU_RESET_PRCLR2_USBRS_Msk (0x01UL << SCU_RESET_PRCLR2_USBRS_Pos) /*!< SCU_RESET PRCLR2: USBRS Mask */
\r
6023 /* ================================================================================ */
\r
6024 /* ================ Group 'LEDTS' Position & Mask ================ */
\r
6025 /* ================================================================================ */
\r
6028 /* ---------------------------------- LEDTS_ID ---------------------------------- */
\r
6029 #define LEDTS_ID_MOD_REV_Pos 0 /*!< LEDTS ID: MOD_REV Position */
\r
6030 #define LEDTS_ID_MOD_REV_Msk (0x000000ffUL << LEDTS_ID_MOD_REV_Pos) /*!< LEDTS ID: MOD_REV Mask */
\r
6031 #define LEDTS_ID_MOD_TYPE_Pos 8 /*!< LEDTS ID: MOD_TYPE Position */
\r
6032 #define LEDTS_ID_MOD_TYPE_Msk (0x000000ffUL << LEDTS_ID_MOD_TYPE_Pos) /*!< LEDTS ID: MOD_TYPE Mask */
\r
6033 #define LEDTS_ID_MOD_NUMBER_Pos 16 /*!< LEDTS ID: MOD_NUMBER Position */
\r
6034 #define LEDTS_ID_MOD_NUMBER_Msk (0x0000ffffUL << LEDTS_ID_MOD_NUMBER_Pos) /*!< LEDTS ID: MOD_NUMBER Mask */
\r
6036 /* -------------------------------- LEDTS_GLOBCTL ------------------------------- */
\r
6037 #define LEDTS_GLOBCTL_TS_EN_Pos 0 /*!< LEDTS GLOBCTL: TS_EN Position */
\r
6038 #define LEDTS_GLOBCTL_TS_EN_Msk (0x01UL << LEDTS_GLOBCTL_TS_EN_Pos) /*!< LEDTS GLOBCTL: TS_EN Mask */
\r
6039 #define LEDTS_GLOBCTL_LD_EN_Pos 1 /*!< LEDTS GLOBCTL: LD_EN Position */
\r
6040 #define LEDTS_GLOBCTL_LD_EN_Msk (0x01UL << LEDTS_GLOBCTL_LD_EN_Pos) /*!< LEDTS GLOBCTL: LD_EN Mask */
\r
6041 #define LEDTS_GLOBCTL_CMTR_Pos 2 /*!< LEDTS GLOBCTL: CMTR Position */
\r
6042 #define LEDTS_GLOBCTL_CMTR_Msk (0x01UL << LEDTS_GLOBCTL_CMTR_Pos) /*!< LEDTS GLOBCTL: CMTR Mask */
\r
6043 #define LEDTS_GLOBCTL_ENSYNC_Pos 3 /*!< LEDTS GLOBCTL: ENSYNC Position */
\r
6044 #define LEDTS_GLOBCTL_ENSYNC_Msk (0x01UL << LEDTS_GLOBCTL_ENSYNC_Pos) /*!< LEDTS GLOBCTL: ENSYNC Mask */
\r
6045 #define LEDTS_GLOBCTL_SUSCFG_Pos 8 /*!< LEDTS GLOBCTL: SUSCFG Position */
\r
6046 #define LEDTS_GLOBCTL_SUSCFG_Msk (0x01UL << LEDTS_GLOBCTL_SUSCFG_Pos) /*!< LEDTS GLOBCTL: SUSCFG Mask */
\r
6047 #define LEDTS_GLOBCTL_MASKVAL_Pos 9 /*!< LEDTS GLOBCTL: MASKVAL Position */
\r
6048 #define LEDTS_GLOBCTL_MASKVAL_Msk (0x07UL << LEDTS_GLOBCTL_MASKVAL_Pos) /*!< LEDTS GLOBCTL: MASKVAL Mask */
\r
6049 #define LEDTS_GLOBCTL_FENVAL_Pos 12 /*!< LEDTS GLOBCTL: FENVAL Position */
\r
6050 #define LEDTS_GLOBCTL_FENVAL_Msk (0x01UL << LEDTS_GLOBCTL_FENVAL_Pos) /*!< LEDTS GLOBCTL: FENVAL Mask */
\r
6051 #define LEDTS_GLOBCTL_ITS_EN_Pos 13 /*!< LEDTS GLOBCTL: ITS_EN Position */
\r
6052 #define LEDTS_GLOBCTL_ITS_EN_Msk (0x01UL << LEDTS_GLOBCTL_ITS_EN_Pos) /*!< LEDTS GLOBCTL: ITS_EN Mask */
\r
6053 #define LEDTS_GLOBCTL_ITF_EN_Pos 14 /*!< LEDTS GLOBCTL: ITF_EN Position */
\r
6054 #define LEDTS_GLOBCTL_ITF_EN_Msk (0x01UL << LEDTS_GLOBCTL_ITF_EN_Pos) /*!< LEDTS GLOBCTL: ITF_EN Mask */
\r
6055 #define LEDTS_GLOBCTL_ITP_EN_Pos 15 /*!< LEDTS GLOBCTL: ITP_EN Position */
\r
6056 #define LEDTS_GLOBCTL_ITP_EN_Msk (0x01UL << LEDTS_GLOBCTL_ITP_EN_Pos) /*!< LEDTS GLOBCTL: ITP_EN Mask */
\r
6057 #define LEDTS_GLOBCTL_CLK_PS_Pos 16 /*!< LEDTS GLOBCTL: CLK_PS Position */
\r
6058 #define LEDTS_GLOBCTL_CLK_PS_Msk (0x0000ffffUL << LEDTS_GLOBCTL_CLK_PS_Pos) /*!< LEDTS GLOBCTL: CLK_PS Mask */
\r
6060 /* --------------------------------- LEDTS_FNCTL -------------------------------- */
\r
6061 #define LEDTS_FNCTL_PADT_Pos 0 /*!< LEDTS FNCTL: PADT Position */
\r
6062 #define LEDTS_FNCTL_PADT_Msk (0x07UL << LEDTS_FNCTL_PADT_Pos) /*!< LEDTS FNCTL: PADT Mask */
\r
6063 #define LEDTS_FNCTL_PADTSW_Pos 3 /*!< LEDTS FNCTL: PADTSW Position */
\r
6064 #define LEDTS_FNCTL_PADTSW_Msk (0x01UL << LEDTS_FNCTL_PADTSW_Pos) /*!< LEDTS FNCTL: PADTSW Mask */
\r
6065 #define LEDTS_FNCTL_EPULL_Pos 4 /*!< LEDTS FNCTL: EPULL Position */
\r
6066 #define LEDTS_FNCTL_EPULL_Msk (0x01UL << LEDTS_FNCTL_EPULL_Pos) /*!< LEDTS FNCTL: EPULL Mask */
\r
6067 #define LEDTS_FNCTL_FNCOL_Pos 5 /*!< LEDTS FNCTL: FNCOL Position */
\r
6068 #define LEDTS_FNCTL_FNCOL_Msk (0x07UL << LEDTS_FNCTL_FNCOL_Pos) /*!< LEDTS FNCTL: FNCOL Mask */
\r
6069 #define LEDTS_FNCTL_ACCCNT_Pos 16 /*!< LEDTS FNCTL: ACCCNT Position */
\r
6070 #define LEDTS_FNCTL_ACCCNT_Msk (0x0fUL << LEDTS_FNCTL_ACCCNT_Pos) /*!< LEDTS FNCTL: ACCCNT Mask */
\r
6071 #define LEDTS_FNCTL_TSCCMP_Pos 20 /*!< LEDTS FNCTL: TSCCMP Position */
\r
6072 #define LEDTS_FNCTL_TSCCMP_Msk (0x01UL << LEDTS_FNCTL_TSCCMP_Pos) /*!< LEDTS FNCTL: TSCCMP Mask */
\r
6073 #define LEDTS_FNCTL_TSOEXT_Pos 21 /*!< LEDTS FNCTL: TSOEXT Position */
\r
6074 #define LEDTS_FNCTL_TSOEXT_Msk (0x03UL << LEDTS_FNCTL_TSOEXT_Pos) /*!< LEDTS FNCTL: TSOEXT Mask */
\r
6075 #define LEDTS_FNCTL_TSCTRR_Pos 23 /*!< LEDTS FNCTL: TSCTRR Position */
\r
6076 #define LEDTS_FNCTL_TSCTRR_Msk (0x01UL << LEDTS_FNCTL_TSCTRR_Pos) /*!< LEDTS FNCTL: TSCTRR Mask */
\r
6077 #define LEDTS_FNCTL_TSCTRSAT_Pos 24 /*!< LEDTS FNCTL: TSCTRSAT Position */
\r
6078 #define LEDTS_FNCTL_TSCTRSAT_Msk (0x01UL << LEDTS_FNCTL_TSCTRSAT_Pos) /*!< LEDTS FNCTL: TSCTRSAT Mask */
\r
6079 #define LEDTS_FNCTL_NR_TSIN_Pos 25 /*!< LEDTS FNCTL: NR_TSIN Position */
\r
6080 #define LEDTS_FNCTL_NR_TSIN_Msk (0x07UL << LEDTS_FNCTL_NR_TSIN_Pos) /*!< LEDTS FNCTL: NR_TSIN Mask */
\r
6081 #define LEDTS_FNCTL_COLLEV_Pos 28 /*!< LEDTS FNCTL: COLLEV Position */
\r
6082 #define LEDTS_FNCTL_COLLEV_Msk (0x01UL << LEDTS_FNCTL_COLLEV_Pos) /*!< LEDTS FNCTL: COLLEV Mask */
\r
6083 #define LEDTS_FNCTL_NR_LEDCOL_Pos 29 /*!< LEDTS FNCTL: NR_LEDCOL Position */
\r
6084 #define LEDTS_FNCTL_NR_LEDCOL_Msk (0x07UL << LEDTS_FNCTL_NR_LEDCOL_Pos) /*!< LEDTS FNCTL: NR_LEDCOL Mask */
\r
6086 /* --------------------------------- LEDTS_EVFR --------------------------------- */
\r
6087 #define LEDTS_EVFR_TSF_Pos 0 /*!< LEDTS EVFR: TSF Position */
\r
6088 #define LEDTS_EVFR_TSF_Msk (0x01UL << LEDTS_EVFR_TSF_Pos) /*!< LEDTS EVFR: TSF Mask */
\r
6089 #define LEDTS_EVFR_TFF_Pos 1 /*!< LEDTS EVFR: TFF Position */
\r
6090 #define LEDTS_EVFR_TFF_Msk (0x01UL << LEDTS_EVFR_TFF_Pos) /*!< LEDTS EVFR: TFF Mask */
\r
6091 #define LEDTS_EVFR_TPF_Pos 2 /*!< LEDTS EVFR: TPF Position */
\r
6092 #define LEDTS_EVFR_TPF_Msk (0x01UL << LEDTS_EVFR_TPF_Pos) /*!< LEDTS EVFR: TPF Mask */
\r
6093 #define LEDTS_EVFR_TSCTROVF_Pos 3 /*!< LEDTS EVFR: TSCTROVF Position */
\r
6094 #define LEDTS_EVFR_TSCTROVF_Msk (0x01UL << LEDTS_EVFR_TSCTROVF_Pos) /*!< LEDTS EVFR: TSCTROVF Mask */
\r
6095 #define LEDTS_EVFR_CTSF_Pos 16 /*!< LEDTS EVFR: CTSF Position */
\r
6096 #define LEDTS_EVFR_CTSF_Msk (0x01UL << LEDTS_EVFR_CTSF_Pos) /*!< LEDTS EVFR: CTSF Mask */
\r
6097 #define LEDTS_EVFR_CTFF_Pos 17 /*!< LEDTS EVFR: CTFF Position */
\r
6098 #define LEDTS_EVFR_CTFF_Msk (0x01UL << LEDTS_EVFR_CTFF_Pos) /*!< LEDTS EVFR: CTFF Mask */
\r
6099 #define LEDTS_EVFR_CTPF_Pos 18 /*!< LEDTS EVFR: CTPF Position */
\r
6100 #define LEDTS_EVFR_CTPF_Msk (0x01UL << LEDTS_EVFR_CTPF_Pos) /*!< LEDTS EVFR: CTPF Mask */
\r
6102 /* --------------------------------- LEDTS_TSVAL -------------------------------- */
\r
6103 #define LEDTS_TSVAL_TSCTRVALR_Pos 0 /*!< LEDTS TSVAL: TSCTRVALR Position */
\r
6104 #define LEDTS_TSVAL_TSCTRVALR_Msk (0x0000ffffUL << LEDTS_TSVAL_TSCTRVALR_Pos) /*!< LEDTS TSVAL: TSCTRVALR Mask */
\r
6105 #define LEDTS_TSVAL_TSCTRVAL_Pos 16 /*!< LEDTS TSVAL: TSCTRVAL Position */
\r
6106 #define LEDTS_TSVAL_TSCTRVAL_Msk (0x0000ffffUL << LEDTS_TSVAL_TSCTRVAL_Pos) /*!< LEDTS TSVAL: TSCTRVAL Mask */
\r
6108 /* --------------------------------- LEDTS_LINE0 -------------------------------- */
\r
6109 #define LEDTS_LINE0_LINE_0_Pos 0 /*!< LEDTS LINE0: LINE_0 Position */
\r
6110 #define LEDTS_LINE0_LINE_0_Msk (0x000000ffUL << LEDTS_LINE0_LINE_0_Pos) /*!< LEDTS LINE0: LINE_0 Mask */
\r
6111 #define LEDTS_LINE0_LINE_1_Pos 8 /*!< LEDTS LINE0: LINE_1 Position */
\r
6112 #define LEDTS_LINE0_LINE_1_Msk (0x000000ffUL << LEDTS_LINE0_LINE_1_Pos) /*!< LEDTS LINE0: LINE_1 Mask */
\r
6113 #define LEDTS_LINE0_LINE_2_Pos 16 /*!< LEDTS LINE0: LINE_2 Position */
\r
6114 #define LEDTS_LINE0_LINE_2_Msk (0x000000ffUL << LEDTS_LINE0_LINE_2_Pos) /*!< LEDTS LINE0: LINE_2 Mask */
\r
6115 #define LEDTS_LINE0_LINE_3_Pos 24 /*!< LEDTS LINE0: LINE_3 Position */
\r
6116 #define LEDTS_LINE0_LINE_3_Msk (0x000000ffUL << LEDTS_LINE0_LINE_3_Pos) /*!< LEDTS LINE0: LINE_3 Mask */
\r
6118 /* --------------------------------- LEDTS_LINE1 -------------------------------- */
\r
6119 #define LEDTS_LINE1_LINE_4_Pos 0 /*!< LEDTS LINE1: LINE_4 Position */
\r
6120 #define LEDTS_LINE1_LINE_4_Msk (0x000000ffUL << LEDTS_LINE1_LINE_4_Pos) /*!< LEDTS LINE1: LINE_4 Mask */
\r
6121 #define LEDTS_LINE1_LINE_5_Pos 8 /*!< LEDTS LINE1: LINE_5 Position */
\r
6122 #define LEDTS_LINE1_LINE_5_Msk (0x000000ffUL << LEDTS_LINE1_LINE_5_Pos) /*!< LEDTS LINE1: LINE_5 Mask */
\r
6123 #define LEDTS_LINE1_LINE_6_Pos 16 /*!< LEDTS LINE1: LINE_6 Position */
\r
6124 #define LEDTS_LINE1_LINE_6_Msk (0x000000ffUL << LEDTS_LINE1_LINE_6_Pos) /*!< LEDTS LINE1: LINE_6 Mask */
\r
6125 #define LEDTS_LINE1_LINE_A_Pos 24 /*!< LEDTS LINE1: LINE_A Position */
\r
6126 #define LEDTS_LINE1_LINE_A_Msk (0x000000ffUL << LEDTS_LINE1_LINE_A_Pos) /*!< LEDTS LINE1: LINE_A Mask */
\r
6128 /* -------------------------------- LEDTS_LDCMP0 -------------------------------- */
\r
6129 #define LEDTS_LDCMP0_CMP_LD0_Pos 0 /*!< LEDTS LDCMP0: CMP_LD0 Position */
\r
6130 #define LEDTS_LDCMP0_CMP_LD0_Msk (0x000000ffUL << LEDTS_LDCMP0_CMP_LD0_Pos) /*!< LEDTS LDCMP0: CMP_LD0 Mask */
\r
6131 #define LEDTS_LDCMP0_CMP_LD1_Pos 8 /*!< LEDTS LDCMP0: CMP_LD1 Position */
\r
6132 #define LEDTS_LDCMP0_CMP_LD1_Msk (0x000000ffUL << LEDTS_LDCMP0_CMP_LD1_Pos) /*!< LEDTS LDCMP0: CMP_LD1 Mask */
\r
6133 #define LEDTS_LDCMP0_CMP_LD2_Pos 16 /*!< LEDTS LDCMP0: CMP_LD2 Position */
\r
6134 #define LEDTS_LDCMP0_CMP_LD2_Msk (0x000000ffUL << LEDTS_LDCMP0_CMP_LD2_Pos) /*!< LEDTS LDCMP0: CMP_LD2 Mask */
\r
6135 #define LEDTS_LDCMP0_CMP_LD3_Pos 24 /*!< LEDTS LDCMP0: CMP_LD3 Position */
\r
6136 #define LEDTS_LDCMP0_CMP_LD3_Msk (0x000000ffUL << LEDTS_LDCMP0_CMP_LD3_Pos) /*!< LEDTS LDCMP0: CMP_LD3 Mask */
\r
6138 /* -------------------------------- LEDTS_LDCMP1 -------------------------------- */
\r
6139 #define LEDTS_LDCMP1_CMP_LD4_Pos 0 /*!< LEDTS LDCMP1: CMP_LD4 Position */
\r
6140 #define LEDTS_LDCMP1_CMP_LD4_Msk (0x000000ffUL << LEDTS_LDCMP1_CMP_LD4_Pos) /*!< LEDTS LDCMP1: CMP_LD4 Mask */
\r
6141 #define LEDTS_LDCMP1_CMP_LD5_Pos 8 /*!< LEDTS LDCMP1: CMP_LD5 Position */
\r
6142 #define LEDTS_LDCMP1_CMP_LD5_Msk (0x000000ffUL << LEDTS_LDCMP1_CMP_LD5_Pos) /*!< LEDTS LDCMP1: CMP_LD5 Mask */
\r
6143 #define LEDTS_LDCMP1_CMP_LD6_Pos 16 /*!< LEDTS LDCMP1: CMP_LD6 Position */
\r
6144 #define LEDTS_LDCMP1_CMP_LD6_Msk (0x000000ffUL << LEDTS_LDCMP1_CMP_LD6_Pos) /*!< LEDTS LDCMP1: CMP_LD6 Mask */
\r
6145 #define LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos 24 /*!< LEDTS LDCMP1: CMP_LDA_TSCOM Position */
\r
6146 #define LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk (0x000000ffUL << LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos) /*!< LEDTS LDCMP1: CMP_LDA_TSCOM Mask */
\r
6148 /* -------------------------------- LEDTS_TSCMP0 -------------------------------- */
\r
6149 #define LEDTS_TSCMP0_CMP_TS0_Pos 0 /*!< LEDTS TSCMP0: CMP_TS0 Position */
\r
6150 #define LEDTS_TSCMP0_CMP_TS0_Msk (0x000000ffUL << LEDTS_TSCMP0_CMP_TS0_Pos) /*!< LEDTS TSCMP0: CMP_TS0 Mask */
\r
6151 #define LEDTS_TSCMP0_CMP_TS1_Pos 8 /*!< LEDTS TSCMP0: CMP_TS1 Position */
\r
6152 #define LEDTS_TSCMP0_CMP_TS1_Msk (0x000000ffUL << LEDTS_TSCMP0_CMP_TS1_Pos) /*!< LEDTS TSCMP0: CMP_TS1 Mask */
\r
6153 #define LEDTS_TSCMP0_CMP_TS2_Pos 16 /*!< LEDTS TSCMP0: CMP_TS2 Position */
\r
6154 #define LEDTS_TSCMP0_CMP_TS2_Msk (0x000000ffUL << LEDTS_TSCMP0_CMP_TS2_Pos) /*!< LEDTS TSCMP0: CMP_TS2 Mask */
\r
6155 #define LEDTS_TSCMP0_CMP_TS3_Pos 24 /*!< LEDTS TSCMP0: CMP_TS3 Position */
\r
6156 #define LEDTS_TSCMP0_CMP_TS3_Msk (0x000000ffUL << LEDTS_TSCMP0_CMP_TS3_Pos) /*!< LEDTS TSCMP0: CMP_TS3 Mask */
\r
6158 /* -------------------------------- LEDTS_TSCMP1 -------------------------------- */
\r
6159 #define LEDTS_TSCMP1_CMP_TS4_Pos 0 /*!< LEDTS TSCMP1: CMP_TS4 Position */
\r
6160 #define LEDTS_TSCMP1_CMP_TS4_Msk (0x000000ffUL << LEDTS_TSCMP1_CMP_TS4_Pos) /*!< LEDTS TSCMP1: CMP_TS4 Mask */
\r
6161 #define LEDTS_TSCMP1_CMP_TS5_Pos 8 /*!< LEDTS TSCMP1: CMP_TS5 Position */
\r
6162 #define LEDTS_TSCMP1_CMP_TS5_Msk (0x000000ffUL << LEDTS_TSCMP1_CMP_TS5_Pos) /*!< LEDTS TSCMP1: CMP_TS5 Mask */
\r
6163 #define LEDTS_TSCMP1_CMP_TS6_Pos 16 /*!< LEDTS TSCMP1: CMP_TS6 Position */
\r
6164 #define LEDTS_TSCMP1_CMP_TS6_Msk (0x000000ffUL << LEDTS_TSCMP1_CMP_TS6_Pos) /*!< LEDTS TSCMP1: CMP_TS6 Mask */
\r
6165 #define LEDTS_TSCMP1_CMP_TS7_Pos 24 /*!< LEDTS TSCMP1: CMP_TS7 Position */
\r
6166 #define LEDTS_TSCMP1_CMP_TS7_Msk (0x000000ffUL << LEDTS_TSCMP1_CMP_TS7_Pos) /*!< LEDTS TSCMP1: CMP_TS7 Mask */
\r
6169 /* ================================================================================ */
\r
6170 /* ================ struct 'ETH0_CON' Position & Mask ================ */
\r
6171 /* ================================================================================ */
\r
6174 /* ------------------------------ ETH0_CON_ETH0_CON ----------------------------- */
\r
6175 #define ETH_CON_RXD0_Pos 0 /*!< ETH0_CON ETH0_CON: RXD0 Position */
\r
6176 #define ETH_CON_RXD0_Msk (0x03UL << ETH_CON_RXD0_Pos) /*!< ETH0_CON ETH0_CON: RXD0 Mask */
\r
6177 #define ETH_CON_RXD1_Pos 2 /*!< ETH0_CON ETH0_CON: RXD1 Position */
\r
6178 #define ETH_CON_RXD1_Msk (0x03UL << ETH_CON_RXD1_Pos) /*!< ETH0_CON ETH0_CON: RXD1 Mask */
\r
6179 #define ETH_CON_RXD2_Pos 4 /*!< ETH0_CON ETH0_CON: RXD2 Position */
\r
6180 #define ETH_CON_RXD2_Msk (0x03UL << ETH_CON_RXD2_Pos) /*!< ETH0_CON ETH0_CON: RXD2 Mask */
\r
6181 #define ETH_CON_RXD3_Pos 6 /*!< ETH0_CON ETH0_CON: RXD3 Position */
\r
6182 #define ETH_CON_RXD3_Msk (0x03UL << ETH_CON_RXD3_Pos) /*!< ETH0_CON ETH0_CON: RXD3 Mask */
\r
6183 #define ETH_CON_CLK_RMII_Pos 8 /*!< ETH0_CON ETH0_CON: CLK_RMII Position */
\r
6184 #define ETH_CON_CLK_RMII_Msk (0x03UL << ETH_CON_CLK_RMII_Pos) /*!< ETH0_CON ETH0_CON: CLK_RMII Mask */
\r
6185 #define ETH_CON_CRS_DV_Pos 10 /*!< ETH0_CON ETH0_CON: CRS_DV Position */
\r
6186 #define ETH_CON_CRS_DV_Msk (0x03UL << ETH_CON_CRS_DV_Pos) /*!< ETH0_CON ETH0_CON: CRS_DV Mask */
\r
6187 #define ETH_CON_CRS_Pos 12 /*!< ETH0_CON ETH0_CON: CRS Position */
\r
6188 #define ETH_CON_CRS_Msk (0x03UL << ETH_CON_CRS_Pos) /*!< ETH0_CON ETH0_CON: CRS Mask */
\r
6189 #define ETH_CON_RXER_Pos 14 /*!< ETH0_CON ETH0_CON: RXER Position */
\r
6190 #define ETH_CON_RXER_Msk (0x03UL << ETH_CON_RXER_Pos) /*!< ETH0_CON ETH0_CON: RXER Mask */
\r
6191 #define ETH_CON_COL_Pos 16 /*!< ETH0_CON ETH0_CON: COL Position */
\r
6192 #define ETH_CON_COL_Msk (0x03UL << ETH_CON_COL_Pos) /*!< ETH0_CON ETH0_CON: COL Mask */
\r
6193 #define ETH_CON_CLK_TX_Pos 18 /*!< ETH0_CON ETH0_CON: CLK_TX Position */
\r
6194 #define ETH_CON_CLK_TX_Msk (0x03UL << ETH_CON_CLK_TX_Pos) /*!< ETH0_CON ETH0_CON: CLK_TX Mask */
\r
6195 #define ETH_CON_MDIO_Pos 22 /*!< ETH0_CON ETH0_CON: MDIO Position */
\r
6196 #define ETH_CON_MDIO_Msk (0x03UL << ETH_CON_MDIO_Pos) /*!< ETH0_CON ETH0_CON: MDIO Mask */
\r
6197 #define ETH_CON_INFSEL_Pos 26 /*!< ETH0_CON ETH0_CON: INFSEL Position */
\r
6198 #define ETH_CON_INFSEL_Msk (0x01UL << ETH_CON_INFSEL_Pos) /*!< ETH0_CON ETH0_CON: INFSEL Mask */
\r
6201 /* ================================================================================ */
\r
6202 /* ================ Group 'ETH' Position & Mask ================ */
\r
6203 /* ================================================================================ */
\r
6206 /* ---------------------------- ETH_MAC_CONFIGURATION --------------------------- */
\r
6207 #define ETH_MAC_CONFIGURATION_PRELEN_Pos 0 /*!< ETH MAC_CONFIGURATION: PRELEN Position */
\r
6208 #define ETH_MAC_CONFIGURATION_PRELEN_Msk (0x03UL << ETH_MAC_CONFIGURATION_PRELEN_Pos) /*!< ETH MAC_CONFIGURATION: PRELEN Mask */
\r
6209 #define ETH_MAC_CONFIGURATION_RE_Pos 2 /*!< ETH MAC_CONFIGURATION: RE Position */
\r
6210 #define ETH_MAC_CONFIGURATION_RE_Msk (0x01UL << ETH_MAC_CONFIGURATION_RE_Pos) /*!< ETH MAC_CONFIGURATION: RE Mask */
\r
6211 #define ETH_MAC_CONFIGURATION_TE_Pos 3 /*!< ETH MAC_CONFIGURATION: TE Position */
\r
6212 #define ETH_MAC_CONFIGURATION_TE_Msk (0x01UL << ETH_MAC_CONFIGURATION_TE_Pos) /*!< ETH MAC_CONFIGURATION: TE Mask */
\r
6213 #define ETH_MAC_CONFIGURATION_DC_Pos 4 /*!< ETH MAC_CONFIGURATION: DC Position */
\r
6214 #define ETH_MAC_CONFIGURATION_DC_Msk (0x01UL << ETH_MAC_CONFIGURATION_DC_Pos) /*!< ETH MAC_CONFIGURATION: DC Mask */
\r
6215 #define ETH_MAC_CONFIGURATION_BL_Pos 5 /*!< ETH MAC_CONFIGURATION: BL Position */
\r
6216 #define ETH_MAC_CONFIGURATION_BL_Msk (0x03UL << ETH_MAC_CONFIGURATION_BL_Pos) /*!< ETH MAC_CONFIGURATION: BL Mask */
\r
6217 #define ETH_MAC_CONFIGURATION_ACS_Pos 7 /*!< ETH MAC_CONFIGURATION: ACS Position */
\r
6218 #define ETH_MAC_CONFIGURATION_ACS_Msk (0x01UL << ETH_MAC_CONFIGURATION_ACS_Pos) /*!< ETH MAC_CONFIGURATION: ACS Mask */
\r
6219 #define ETH_MAC_CONFIGURATION_Reserved_8_Pos 8 /*!< ETH MAC_CONFIGURATION: Reserved_8 Position */
\r
6220 #define ETH_MAC_CONFIGURATION_Reserved_8_Msk (0x01UL << ETH_MAC_CONFIGURATION_Reserved_8_Pos) /*!< ETH MAC_CONFIGURATION: Reserved_8 Mask */
\r
6221 #define ETH_MAC_CONFIGURATION_DR_Pos 9 /*!< ETH MAC_CONFIGURATION: DR Position */
\r
6222 #define ETH_MAC_CONFIGURATION_DR_Msk (0x01UL << ETH_MAC_CONFIGURATION_DR_Pos) /*!< ETH MAC_CONFIGURATION: DR Mask */
\r
6223 #define ETH_MAC_CONFIGURATION_IPC_Pos 10 /*!< ETH MAC_CONFIGURATION: IPC Position */
\r
6224 #define ETH_MAC_CONFIGURATION_IPC_Msk (0x01UL << ETH_MAC_CONFIGURATION_IPC_Pos) /*!< ETH MAC_CONFIGURATION: IPC Mask */
\r
6225 #define ETH_MAC_CONFIGURATION_DM_Pos 11 /*!< ETH MAC_CONFIGURATION: DM Position */
\r
6226 #define ETH_MAC_CONFIGURATION_DM_Msk (0x01UL << ETH_MAC_CONFIGURATION_DM_Pos) /*!< ETH MAC_CONFIGURATION: DM Mask */
\r
6227 #define ETH_MAC_CONFIGURATION_LM_Pos 12 /*!< ETH MAC_CONFIGURATION: LM Position */
\r
6228 #define ETH_MAC_CONFIGURATION_LM_Msk (0x01UL << ETH_MAC_CONFIGURATION_LM_Pos) /*!< ETH MAC_CONFIGURATION: LM Mask */
\r
6229 #define ETH_MAC_CONFIGURATION_DO_Pos 13 /*!< ETH MAC_CONFIGURATION: DO Position */
\r
6230 #define ETH_MAC_CONFIGURATION_DO_Msk (0x01UL << ETH_MAC_CONFIGURATION_DO_Pos) /*!< ETH MAC_CONFIGURATION: DO Mask */
\r
6231 #define ETH_MAC_CONFIGURATION_FES_Pos 14 /*!< ETH MAC_CONFIGURATION: FES Position */
\r
6232 #define ETH_MAC_CONFIGURATION_FES_Msk (0x01UL << ETH_MAC_CONFIGURATION_FES_Pos) /*!< ETH MAC_CONFIGURATION: FES Mask */
\r
6233 #define ETH_MAC_CONFIGURATION_DCRS_Pos 16 /*!< ETH MAC_CONFIGURATION: DCRS Position */
\r
6234 #define ETH_MAC_CONFIGURATION_DCRS_Msk (0x01UL << ETH_MAC_CONFIGURATION_DCRS_Pos) /*!< ETH MAC_CONFIGURATION: DCRS Mask */
\r
6235 #define ETH_MAC_CONFIGURATION_IFG_Pos 17 /*!< ETH MAC_CONFIGURATION: IFG Position */
\r
6236 #define ETH_MAC_CONFIGURATION_IFG_Msk (0x07UL << ETH_MAC_CONFIGURATION_IFG_Pos) /*!< ETH MAC_CONFIGURATION: IFG Mask */
\r
6237 #define ETH_MAC_CONFIGURATION_JE_Pos 20 /*!< ETH MAC_CONFIGURATION: JE Position */
\r
6238 #define ETH_MAC_CONFIGURATION_JE_Msk (0x01UL << ETH_MAC_CONFIGURATION_JE_Pos) /*!< ETH MAC_CONFIGURATION: JE Mask */
\r
6239 #define ETH_MAC_CONFIGURATION_BE_Pos 21 /*!< ETH MAC_CONFIGURATION: BE Position */
\r
6240 #define ETH_MAC_CONFIGURATION_BE_Msk (0x01UL << ETH_MAC_CONFIGURATION_BE_Pos) /*!< ETH MAC_CONFIGURATION: BE Mask */
\r
6241 #define ETH_MAC_CONFIGURATION_JD_Pos 22 /*!< ETH MAC_CONFIGURATION: JD Position */
\r
6242 #define ETH_MAC_CONFIGURATION_JD_Msk (0x01UL << ETH_MAC_CONFIGURATION_JD_Pos) /*!< ETH MAC_CONFIGURATION: JD Mask */
\r
6243 #define ETH_MAC_CONFIGURATION_WD_Pos 23 /*!< ETH MAC_CONFIGURATION: WD Position */
\r
6244 #define ETH_MAC_CONFIGURATION_WD_Msk (0x01UL << ETH_MAC_CONFIGURATION_WD_Pos) /*!< ETH MAC_CONFIGURATION: WD Mask */
\r
6245 #define ETH_MAC_CONFIGURATION_TC_Pos 24 /*!< ETH MAC_CONFIGURATION: TC Position */
\r
6246 #define ETH_MAC_CONFIGURATION_TC_Msk (0x01UL << ETH_MAC_CONFIGURATION_TC_Pos) /*!< ETH MAC_CONFIGURATION: TC Mask */
\r
6247 #define ETH_MAC_CONFIGURATION_CST_Pos 25 /*!< ETH MAC_CONFIGURATION: CST Position */
\r
6248 #define ETH_MAC_CONFIGURATION_CST_Msk (0x01UL << ETH_MAC_CONFIGURATION_CST_Pos) /*!< ETH MAC_CONFIGURATION: CST Mask */
\r
6249 #define ETH_MAC_CONFIGURATION_Reserved_26_Pos 26 /*!< ETH MAC_CONFIGURATION: Reserved_26 Position */
\r
6250 #define ETH_MAC_CONFIGURATION_Reserved_26_Msk (0x01UL << ETH_MAC_CONFIGURATION_Reserved_26_Pos) /*!< ETH MAC_CONFIGURATION: Reserved_26 Mask */
\r
6251 #define ETH_MAC_CONFIGURATION_TWOKPE_Pos 27 /*!< ETH MAC_CONFIGURATION: TWOKPE Position */
\r
6252 #define ETH_MAC_CONFIGURATION_TWOKPE_Msk (0x01UL << ETH_MAC_CONFIGURATION_TWOKPE_Pos) /*!< ETH MAC_CONFIGURATION: TWOKPE Mask */
\r
6253 #define ETH_MAC_CONFIGURATION_SARC_Pos 28 /*!< ETH MAC_CONFIGURATION: SARC Position */
\r
6254 #define ETH_MAC_CONFIGURATION_SARC_Msk (0x07UL << ETH_MAC_CONFIGURATION_SARC_Pos) /*!< ETH MAC_CONFIGURATION: SARC Mask */
\r
6255 #define ETH_MAC_CONFIGURATION_Reserved_31_Pos 31 /*!< ETH MAC_CONFIGURATION: Reserved_31 Position */
\r
6256 #define ETH_MAC_CONFIGURATION_Reserved_31_Msk (0x01UL << ETH_MAC_CONFIGURATION_Reserved_31_Pos) /*!< ETH MAC_CONFIGURATION: Reserved_31 Mask */
\r
6258 /* ---------------------------- ETH_MAC_FRAME_FILTER ---------------------------- */
\r
6259 #define ETH_MAC_FRAME_FILTER_PR_Pos 0 /*!< ETH MAC_FRAME_FILTER: PR Position */
\r
6260 #define ETH_MAC_FRAME_FILTER_PR_Msk (0x01UL << ETH_MAC_FRAME_FILTER_PR_Pos) /*!< ETH MAC_FRAME_FILTER: PR Mask */
\r
6261 #define ETH_MAC_FRAME_FILTER_HUC_Pos 1 /*!< ETH MAC_FRAME_FILTER: HUC Position */
\r
6262 #define ETH_MAC_FRAME_FILTER_HUC_Msk (0x01UL << ETH_MAC_FRAME_FILTER_HUC_Pos) /*!< ETH MAC_FRAME_FILTER: HUC Mask */
\r
6263 #define ETH_MAC_FRAME_FILTER_HMC_Pos 2 /*!< ETH MAC_FRAME_FILTER: HMC Position */
\r
6264 #define ETH_MAC_FRAME_FILTER_HMC_Msk (0x01UL << ETH_MAC_FRAME_FILTER_HMC_Pos) /*!< ETH MAC_FRAME_FILTER: HMC Mask */
\r
6265 #define ETH_MAC_FRAME_FILTER_DAIF_Pos 3 /*!< ETH MAC_FRAME_FILTER: DAIF Position */
\r
6266 #define ETH_MAC_FRAME_FILTER_DAIF_Msk (0x01UL << ETH_MAC_FRAME_FILTER_DAIF_Pos) /*!< ETH MAC_FRAME_FILTER: DAIF Mask */
\r
6267 #define ETH_MAC_FRAME_FILTER_PM_Pos 4 /*!< ETH MAC_FRAME_FILTER: PM Position */
\r
6268 #define ETH_MAC_FRAME_FILTER_PM_Msk (0x01UL << ETH_MAC_FRAME_FILTER_PM_Pos) /*!< ETH MAC_FRAME_FILTER: PM Mask */
\r
6269 #define ETH_MAC_FRAME_FILTER_DBF_Pos 5 /*!< ETH MAC_FRAME_FILTER: DBF Position */
\r
6270 #define ETH_MAC_FRAME_FILTER_DBF_Msk (0x01UL << ETH_MAC_FRAME_FILTER_DBF_Pos) /*!< ETH MAC_FRAME_FILTER: DBF Mask */
\r
6271 #define ETH_MAC_FRAME_FILTER_PCF_Pos 6 /*!< ETH MAC_FRAME_FILTER: PCF Position */
\r
6272 #define ETH_MAC_FRAME_FILTER_PCF_Msk (0x03UL << ETH_MAC_FRAME_FILTER_PCF_Pos) /*!< ETH MAC_FRAME_FILTER: PCF Mask */
\r
6273 #define ETH_MAC_FRAME_FILTER_SAIF_Pos 8 /*!< ETH MAC_FRAME_FILTER: SAIF Position */
\r
6274 #define ETH_MAC_FRAME_FILTER_SAIF_Msk (0x01UL << ETH_MAC_FRAME_FILTER_SAIF_Pos) /*!< ETH MAC_FRAME_FILTER: SAIF Mask */
\r
6275 #define ETH_MAC_FRAME_FILTER_SAF_Pos 9 /*!< ETH MAC_FRAME_FILTER: SAF Position */
\r
6276 #define ETH_MAC_FRAME_FILTER_SAF_Msk (0x01UL << ETH_MAC_FRAME_FILTER_SAF_Pos) /*!< ETH MAC_FRAME_FILTER: SAF Mask */
\r
6277 #define ETH_MAC_FRAME_FILTER_HPF_Pos 10 /*!< ETH MAC_FRAME_FILTER: HPF Position */
\r
6278 #define ETH_MAC_FRAME_FILTER_HPF_Msk (0x01UL << ETH_MAC_FRAME_FILTER_HPF_Pos) /*!< ETH MAC_FRAME_FILTER: HPF Mask */
\r
6279 #define ETH_MAC_FRAME_FILTER_Reserved_15_11_Pos 11 /*!< ETH MAC_FRAME_FILTER: Reserved_15_11 Position */
\r
6280 #define ETH_MAC_FRAME_FILTER_Reserved_15_11_Msk (0x1fUL << ETH_MAC_FRAME_FILTER_Reserved_15_11_Pos) /*!< ETH MAC_FRAME_FILTER: Reserved_15_11 Mask */
\r
6281 #define ETH_MAC_FRAME_FILTER_VTFE_Pos 16 /*!< ETH MAC_FRAME_FILTER: VTFE Position */
\r
6282 #define ETH_MAC_FRAME_FILTER_VTFE_Msk (0x01UL << ETH_MAC_FRAME_FILTER_VTFE_Pos) /*!< ETH MAC_FRAME_FILTER: VTFE Mask */
\r
6283 #define ETH_MAC_FRAME_FILTER_Reserved_19_17_Pos 17 /*!< ETH MAC_FRAME_FILTER: Reserved_19_17 Position */
\r
6284 #define ETH_MAC_FRAME_FILTER_Reserved_19_17_Msk (0x07UL << ETH_MAC_FRAME_FILTER_Reserved_19_17_Pos) /*!< ETH MAC_FRAME_FILTER: Reserved_19_17 Mask */
\r
6285 #define ETH_MAC_FRAME_FILTER_IPFE_Pos 20 /*!< ETH MAC_FRAME_FILTER: IPFE Position */
\r
6286 #define ETH_MAC_FRAME_FILTER_IPFE_Msk (0x01UL << ETH_MAC_FRAME_FILTER_IPFE_Pos) /*!< ETH MAC_FRAME_FILTER: IPFE Mask */
\r
6287 #define ETH_MAC_FRAME_FILTER_DNTU_Pos 21 /*!< ETH MAC_FRAME_FILTER: DNTU Position */
\r
6288 #define ETH_MAC_FRAME_FILTER_DNTU_Msk (0x01UL << ETH_MAC_FRAME_FILTER_DNTU_Pos) /*!< ETH MAC_FRAME_FILTER: DNTU Mask */
\r
6289 #define ETH_MAC_FRAME_FILTER_Reserved_30_22_Pos 22 /*!< ETH MAC_FRAME_FILTER: Reserved_30_22 Position */
\r
6290 #define ETH_MAC_FRAME_FILTER_Reserved_30_22_Msk (0x000001ffUL << ETH_MAC_FRAME_FILTER_Reserved_30_22_Pos)/*!< ETH MAC_FRAME_FILTER: Reserved_30_22 Mask */
\r
6291 #define ETH_MAC_FRAME_FILTER_RA_Pos 31 /*!< ETH MAC_FRAME_FILTER: RA Position */
\r
6292 #define ETH_MAC_FRAME_FILTER_RA_Msk (0x01UL << ETH_MAC_FRAME_FILTER_RA_Pos) /*!< ETH MAC_FRAME_FILTER: RA Mask */
\r
6294 /* ----------------------------- ETH_HASH_TABLE_HIGH ---------------------------- */
\r
6295 #define ETH_HASH_TABLE_HIGH_HTH_Pos 0 /*!< ETH HASH_TABLE_HIGH: HTH Position */
\r
6296 #define ETH_HASH_TABLE_HIGH_HTH_Msk (0xffffffffUL << ETH_HASH_TABLE_HIGH_HTH_Pos) /*!< ETH HASH_TABLE_HIGH: HTH Mask */
\r
6298 /* ----------------------------- ETH_HASH_TABLE_LOW ----------------------------- */
\r
6299 #define ETH_HASH_TABLE_LOW_HTL_Pos 0 /*!< ETH HASH_TABLE_LOW: HTL Position */
\r
6300 #define ETH_HASH_TABLE_LOW_HTL_Msk (0xffffffffUL << ETH_HASH_TABLE_LOW_HTL_Pos) /*!< ETH HASH_TABLE_LOW: HTL Mask */
\r
6302 /* ------------------------------ ETH_GMII_ADDRESS ------------------------------ */
\r
6303 #define ETH_GMII_ADDRESS_MB_Pos 0 /*!< ETH GMII_ADDRESS: MB Position */
\r
6304 #define ETH_GMII_ADDRESS_MB_Msk (0x01UL << ETH_GMII_ADDRESS_MB_Pos) /*!< ETH GMII_ADDRESS: MB Mask */
\r
6305 #define ETH_GMII_ADDRESS_MW_Pos 1 /*!< ETH GMII_ADDRESS: MW Position */
\r
6306 #define ETH_GMII_ADDRESS_MW_Msk (0x01UL << ETH_GMII_ADDRESS_MW_Pos) /*!< ETH GMII_ADDRESS: MW Mask */
\r
6307 #define ETH_GMII_ADDRESS_CR_Pos 2 /*!< ETH GMII_ADDRESS: CR Position */
\r
6308 #define ETH_GMII_ADDRESS_CR_Msk (0x0fUL << ETH_GMII_ADDRESS_CR_Pos) /*!< ETH GMII_ADDRESS: CR Mask */
\r
6309 #define ETH_GMII_ADDRESS_MR_Pos 6 /*!< ETH GMII_ADDRESS: MR Position */
\r
6310 #define ETH_GMII_ADDRESS_MR_Msk (0x1fUL << ETH_GMII_ADDRESS_MR_Pos) /*!< ETH GMII_ADDRESS: MR Mask */
\r
6311 #define ETH_GMII_ADDRESS_PA_Pos 11 /*!< ETH GMII_ADDRESS: PA Position */
\r
6312 #define ETH_GMII_ADDRESS_PA_Msk (0x1fUL << ETH_GMII_ADDRESS_PA_Pos) /*!< ETH GMII_ADDRESS: PA Mask */
\r
6313 #define ETH_GMII_ADDRESS_Reserved_31_16_Pos 16 /*!< ETH GMII_ADDRESS: Reserved_31_16 Position */
\r
6314 #define ETH_GMII_ADDRESS_Reserved_31_16_Msk (0x0000ffffUL << ETH_GMII_ADDRESS_Reserved_31_16_Pos) /*!< ETH GMII_ADDRESS: Reserved_31_16 Mask */
\r
6316 /* -------------------------------- ETH_GMII_DATA ------------------------------- */
\r
6317 #define ETH_GMII_DATA_MD_Pos 0 /*!< ETH GMII_DATA: MD Position */
\r
6318 #define ETH_GMII_DATA_MD_Msk (0x0000ffffUL << ETH_GMII_DATA_MD_Pos) /*!< ETH GMII_DATA: MD Mask */
\r
6319 #define ETH_GMII_DATA_Reserved_31_16_Pos 16 /*!< ETH GMII_DATA: Reserved_31_16 Position */
\r
6320 #define ETH_GMII_DATA_Reserved_31_16_Msk (0x0000ffffUL << ETH_GMII_DATA_Reserved_31_16_Pos) /*!< ETH GMII_DATA: Reserved_31_16 Mask */
\r
6322 /* ------------------------------ ETH_FLOW_CONTROL ------------------------------ */
\r
6323 #define ETH_FLOW_CONTROL_FCA_BPA_Pos 0 /*!< ETH FLOW_CONTROL: FCA_BPA Position */
\r
6324 #define ETH_FLOW_CONTROL_FCA_BPA_Msk (0x01UL << ETH_FLOW_CONTROL_FCA_BPA_Pos) /*!< ETH FLOW_CONTROL: FCA_BPA Mask */
\r
6325 #define ETH_FLOW_CONTROL_TFE_Pos 1 /*!< ETH FLOW_CONTROL: TFE Position */
\r
6326 #define ETH_FLOW_CONTROL_TFE_Msk (0x01UL << ETH_FLOW_CONTROL_TFE_Pos) /*!< ETH FLOW_CONTROL: TFE Mask */
\r
6327 #define ETH_FLOW_CONTROL_RFE_Pos 2 /*!< ETH FLOW_CONTROL: RFE Position */
\r
6328 #define ETH_FLOW_CONTROL_RFE_Msk (0x01UL << ETH_FLOW_CONTROL_RFE_Pos) /*!< ETH FLOW_CONTROL: RFE Mask */
\r
6329 #define ETH_FLOW_CONTROL_UP_Pos 3 /*!< ETH FLOW_CONTROL: UP Position */
\r
6330 #define ETH_FLOW_CONTROL_UP_Msk (0x01UL << ETH_FLOW_CONTROL_UP_Pos) /*!< ETH FLOW_CONTROL: UP Mask */
\r
6331 #define ETH_FLOW_CONTROL_PLT_Pos 4 /*!< ETH FLOW_CONTROL: PLT Position */
\r
6332 #define ETH_FLOW_CONTROL_PLT_Msk (0x03UL << ETH_FLOW_CONTROL_PLT_Pos) /*!< ETH FLOW_CONTROL: PLT Mask */
\r
6333 #define ETH_FLOW_CONTROL_Reserved_6_Pos 6 /*!< ETH FLOW_CONTROL: Reserved_6 Position */
\r
6334 #define ETH_FLOW_CONTROL_Reserved_6_Msk (0x01UL << ETH_FLOW_CONTROL_Reserved_6_Pos) /*!< ETH FLOW_CONTROL: Reserved_6 Mask */
\r
6335 #define ETH_FLOW_CONTROL_DZPQ_Pos 7 /*!< ETH FLOW_CONTROL: DZPQ Position */
\r
6336 #define ETH_FLOW_CONTROL_DZPQ_Msk (0x01UL << ETH_FLOW_CONTROL_DZPQ_Pos) /*!< ETH FLOW_CONTROL: DZPQ Mask */
\r
6337 #define ETH_FLOW_CONTROL_Reserved_15_8_Pos 8 /*!< ETH FLOW_CONTROL: Reserved_15_8 Position */
\r
6338 #define ETH_FLOW_CONTROL_Reserved_15_8_Msk (0x000000ffUL << ETH_FLOW_CONTROL_Reserved_15_8_Pos) /*!< ETH FLOW_CONTROL: Reserved_15_8 Mask */
\r
6339 #define ETH_FLOW_CONTROL_PT_Pos 16 /*!< ETH FLOW_CONTROL: PT Position */
\r
6340 #define ETH_FLOW_CONTROL_PT_Msk (0x0000ffffUL << ETH_FLOW_CONTROL_PT_Pos) /*!< ETH FLOW_CONTROL: PT Mask */
\r
6342 /* -------------------------------- ETH_VLAN_TAG -------------------------------- */
\r
6343 #define ETH_VLAN_TAG_VL_Pos 0 /*!< ETH VLAN_TAG: VL Position */
\r
6344 #define ETH_VLAN_TAG_VL_Msk (0x0000ffffUL << ETH_VLAN_TAG_VL_Pos) /*!< ETH VLAN_TAG: VL Mask */
\r
6345 #define ETH_VLAN_TAG_ETV_Pos 16 /*!< ETH VLAN_TAG: ETV Position */
\r
6346 #define ETH_VLAN_TAG_ETV_Msk (0x01UL << ETH_VLAN_TAG_ETV_Pos) /*!< ETH VLAN_TAG: ETV Mask */
\r
6347 #define ETH_VLAN_TAG_VTIM_Pos 17 /*!< ETH VLAN_TAG: VTIM Position */
\r
6348 #define ETH_VLAN_TAG_VTIM_Msk (0x01UL << ETH_VLAN_TAG_VTIM_Pos) /*!< ETH VLAN_TAG: VTIM Mask */
\r
6349 #define ETH_VLAN_TAG_ESVL_Pos 18 /*!< ETH VLAN_TAG: ESVL Position */
\r
6350 #define ETH_VLAN_TAG_ESVL_Msk (0x01UL << ETH_VLAN_TAG_ESVL_Pos) /*!< ETH VLAN_TAG: ESVL Mask */
\r
6351 #define ETH_VLAN_TAG_VTHM_Pos 19 /*!< ETH VLAN_TAG: VTHM Position */
\r
6352 #define ETH_VLAN_TAG_VTHM_Msk (0x01UL << ETH_VLAN_TAG_VTHM_Pos) /*!< ETH VLAN_TAG: VTHM Mask */
\r
6353 #define ETH_VLAN_TAG_Reserved_31_20_Pos 20 /*!< ETH VLAN_TAG: Reserved_31_20 Position */
\r
6354 #define ETH_VLAN_TAG_Reserved_31_20_Msk (0x00000fffUL << ETH_VLAN_TAG_Reserved_31_20_Pos) /*!< ETH VLAN_TAG: Reserved_31_20 Mask */
\r
6356 /* --------------------------------- ETH_VERSION -------------------------------- */
\r
6357 #define ETH_VERSION_SNPSVER_Pos 0 /*!< ETH VERSION: SNPSVER Position */
\r
6358 #define ETH_VERSION_SNPSVER_Msk (0x000000ffUL << ETH_VERSION_SNPSVER_Pos) /*!< ETH VERSION: SNPSVER Mask */
\r
6359 #define ETH_VERSION_USERVER_Pos 8 /*!< ETH VERSION: USERVER Position */
\r
6360 #define ETH_VERSION_USERVER_Msk (0x000000ffUL << ETH_VERSION_USERVER_Pos) /*!< ETH VERSION: USERVER Mask */
\r
6361 #define ETH_VERSION_Reserved_31_16_Pos 16 /*!< ETH VERSION: Reserved_31_16 Position */
\r
6362 #define ETH_VERSION_Reserved_31_16_Msk (0x0000ffffUL << ETH_VERSION_Reserved_31_16_Pos) /*!< ETH VERSION: Reserved_31_16 Mask */
\r
6364 /* ---------------------------------- ETH_DEBUG --------------------------------- */
\r
6365 #define ETH_DEBUG_RPESTS_Pos 0 /*!< ETH DEBUG: RPESTS Position */
\r
6366 #define ETH_DEBUG_RPESTS_Msk (0x01UL << ETH_DEBUG_RPESTS_Pos) /*!< ETH DEBUG: RPESTS Mask */
\r
6367 #define ETH_DEBUG_RFCFCSTS_Pos 1 /*!< ETH DEBUG: RFCFCSTS Position */
\r
6368 #define ETH_DEBUG_RFCFCSTS_Msk (0x03UL << ETH_DEBUG_RFCFCSTS_Pos) /*!< ETH DEBUG: RFCFCSTS Mask */
\r
6369 #define ETH_DEBUG_Reserved_3_Pos 3 /*!< ETH DEBUG: Reserved_3 Position */
\r
6370 #define ETH_DEBUG_Reserved_3_Msk (0x01UL << ETH_DEBUG_Reserved_3_Pos) /*!< ETH DEBUG: Reserved_3 Mask */
\r
6371 #define ETH_DEBUG_RWCSTS_Pos 4 /*!< ETH DEBUG: RWCSTS Position */
\r
6372 #define ETH_DEBUG_RWCSTS_Msk (0x01UL << ETH_DEBUG_RWCSTS_Pos) /*!< ETH DEBUG: RWCSTS Mask */
\r
6373 #define ETH_DEBUG_RRCSTS_Pos 5 /*!< ETH DEBUG: RRCSTS Position */
\r
6374 #define ETH_DEBUG_RRCSTS_Msk (0x03UL << ETH_DEBUG_RRCSTS_Pos) /*!< ETH DEBUG: RRCSTS Mask */
\r
6375 #define ETH_DEBUG_Reserved_7_Pos 7 /*!< ETH DEBUG: Reserved_7 Position */
\r
6376 #define ETH_DEBUG_Reserved_7_Msk (0x01UL << ETH_DEBUG_Reserved_7_Pos) /*!< ETH DEBUG: Reserved_7 Mask */
\r
6377 #define ETH_DEBUG_RXFSTS_Pos 8 /*!< ETH DEBUG: RXFSTS Position */
\r
6378 #define ETH_DEBUG_RXFSTS_Msk (0x03UL << ETH_DEBUG_RXFSTS_Pos) /*!< ETH DEBUG: RXFSTS Mask */
\r
6379 #define ETH_DEBUG_Reserved_15_10_Pos 10 /*!< ETH DEBUG: Reserved_15_10 Position */
\r
6380 #define ETH_DEBUG_Reserved_15_10_Msk (0x3fUL << ETH_DEBUG_Reserved_15_10_Pos) /*!< ETH DEBUG: Reserved_15_10 Mask */
\r
6381 #define ETH_DEBUG_TPESTS_Pos 16 /*!< ETH DEBUG: TPESTS Position */
\r
6382 #define ETH_DEBUG_TPESTS_Msk (0x01UL << ETH_DEBUG_TPESTS_Pos) /*!< ETH DEBUG: TPESTS Mask */
\r
6383 #define ETH_DEBUG_TFCSTS_Pos 17 /*!< ETH DEBUG: TFCSTS Position */
\r
6384 #define ETH_DEBUG_TFCSTS_Msk (0x03UL << ETH_DEBUG_TFCSTS_Pos) /*!< ETH DEBUG: TFCSTS Mask */
\r
6385 #define ETH_DEBUG_TXPAUSED_Pos 19 /*!< ETH DEBUG: TXPAUSED Position */
\r
6386 #define ETH_DEBUG_TXPAUSED_Msk (0x01UL << ETH_DEBUG_TXPAUSED_Pos) /*!< ETH DEBUG: TXPAUSED Mask */
\r
6387 #define ETH_DEBUG_TRCSTS_Pos 20 /*!< ETH DEBUG: TRCSTS Position */
\r
6388 #define ETH_DEBUG_TRCSTS_Msk (0x03UL << ETH_DEBUG_TRCSTS_Pos) /*!< ETH DEBUG: TRCSTS Mask */
\r
6389 #define ETH_DEBUG_TWCSTS_Pos 22 /*!< ETH DEBUG: TWCSTS Position */
\r
6390 #define ETH_DEBUG_TWCSTS_Msk (0x01UL << ETH_DEBUG_TWCSTS_Pos) /*!< ETH DEBUG: TWCSTS Mask */
\r
6391 #define ETH_DEBUG_Reserved_23_Pos 23 /*!< ETH DEBUG: Reserved_23 Position */
\r
6392 #define ETH_DEBUG_Reserved_23_Msk (0x01UL << ETH_DEBUG_Reserved_23_Pos) /*!< ETH DEBUG: Reserved_23 Mask */
\r
6393 #define ETH_DEBUG_TXFSTS_Pos 24 /*!< ETH DEBUG: TXFSTS Position */
\r
6394 #define ETH_DEBUG_TXFSTS_Msk (0x01UL << ETH_DEBUG_TXFSTS_Pos) /*!< ETH DEBUG: TXFSTS Mask */
\r
6395 #define ETH_DEBUG_TXSTSFSTS_Pos 25 /*!< ETH DEBUG: TXSTSFSTS Position */
\r
6396 #define ETH_DEBUG_TXSTSFSTS_Msk (0x01UL << ETH_DEBUG_TXSTSFSTS_Pos) /*!< ETH DEBUG: TXSTSFSTS Mask */
\r
6397 #define ETH_DEBUG_Reserved_31_26_Pos 26 /*!< ETH DEBUG: Reserved_31_26 Position */
\r
6398 #define ETH_DEBUG_Reserved_31_26_Msk (0x3fUL << ETH_DEBUG_Reserved_31_26_Pos) /*!< ETH DEBUG: Reserved_31_26 Mask */
\r
6400 /* ----------------------- ETH_REMOTE_WAKE_UP_FRAME_FILTER ---------------------- */
\r
6401 #define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos 0 /*!< ETH REMOTE_WAKE_UP_FRAME_FILTER: WKUPFRMFTR Position */
\r
6402 #define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Msk (0xffffffffUL << ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos)/*!< ETH REMOTE_WAKE_UP_FRAME_FILTER: WKUPFRMFTR Mask */
\r
6404 /* --------------------------- ETH_PMT_CONTROL_STATUS --------------------------- */
\r
6405 #define ETH_PMT_CONTROL_STATUS_PWRDWN_Pos 0 /*!< ETH PMT_CONTROL_STATUS: PWRDWN Position */
\r
6406 #define ETH_PMT_CONTROL_STATUS_PWRDWN_Msk (0x01UL << ETH_PMT_CONTROL_STATUS_PWRDWN_Pos) /*!< ETH PMT_CONTROL_STATUS: PWRDWN Mask */
\r
6407 #define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos 1 /*!< ETH PMT_CONTROL_STATUS: MGKPKTEN Position */
\r
6408 #define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Msk (0x01UL << ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos) /*!< ETH PMT_CONTROL_STATUS: MGKPKTEN Mask */
\r
6409 #define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos 2 /*!< ETH PMT_CONTROL_STATUS: RWKPKTEN Position */
\r
6410 #define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Msk (0x01UL << ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos) /*!< ETH PMT_CONTROL_STATUS: RWKPKTEN Mask */
\r
6411 #define ETH_PMT_CONTROL_STATUS_Reserved_4_3_Pos 3 /*!< ETH PMT_CONTROL_STATUS: Reserved_4_3 Position */
\r
6412 #define ETH_PMT_CONTROL_STATUS_Reserved_4_3_Msk (0x03UL << ETH_PMT_CONTROL_STATUS_Reserved_4_3_Pos) /*!< ETH PMT_CONTROL_STATUS: Reserved_4_3 Mask */
\r
6413 #define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos 5 /*!< ETH PMT_CONTROL_STATUS: MGKPRCVD Position */
\r
6414 #define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Msk (0x01UL << ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos) /*!< ETH PMT_CONTROL_STATUS: MGKPRCVD Mask */
\r
6415 #define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos 6 /*!< ETH PMT_CONTROL_STATUS: RWKPRCVD Position */
\r
6416 #define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Msk (0x01UL << ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos) /*!< ETH PMT_CONTROL_STATUS: RWKPRCVD Mask */
\r
6417 #define ETH_PMT_CONTROL_STATUS_Reserved_8_7_Pos 7 /*!< ETH PMT_CONTROL_STATUS: Reserved_8_7 Position */
\r
6418 #define ETH_PMT_CONTROL_STATUS_Reserved_8_7_Msk (0x03UL << ETH_PMT_CONTROL_STATUS_Reserved_8_7_Pos) /*!< ETH PMT_CONTROL_STATUS: Reserved_8_7 Mask */
\r
6419 #define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos 9 /*!< ETH PMT_CONTROL_STATUS: GLBLUCAST Position */
\r
6420 #define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Msk (0x01UL << ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos) /*!< ETH PMT_CONTROL_STATUS: GLBLUCAST Mask */
\r
6421 #define ETH_PMT_CONTROL_STATUS_Reserved_30_10_Pos 10 /*!< ETH PMT_CONTROL_STATUS: Reserved_30_10 Position */
\r
6422 #define ETH_PMT_CONTROL_STATUS_Reserved_30_10_Msk (0x001fffffUL << ETH_PMT_CONTROL_STATUS_Reserved_30_10_Pos)/*!< ETH PMT_CONTROL_STATUS: Reserved_30_10 Mask */
\r
6423 #define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos 31 /*!< ETH PMT_CONTROL_STATUS: RWKFILTRST Position */
\r
6424 #define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Msk (0x01UL << ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos) /*!< ETH PMT_CONTROL_STATUS: RWKFILTRST Mask */
\r
6426 /* ---------------------------- ETH_INTERRUPT_STATUS ---------------------------- */
\r
6427 #define ETH_INTERRUPT_STATUS_Reserved_2_0_Pos 0 /*!< ETH INTERRUPT_STATUS: Reserved_2_0 Position */
\r
6428 #define ETH_INTERRUPT_STATUS_Reserved_2_0_Msk (0x07UL << ETH_INTERRUPT_STATUS_Reserved_2_0_Pos) /*!< ETH INTERRUPT_STATUS: Reserved_2_0 Mask */
\r
6429 #define ETH_INTERRUPT_STATUS_PMTIS_Pos 3 /*!< ETH INTERRUPT_STATUS: PMTIS Position */
\r
6430 #define ETH_INTERRUPT_STATUS_PMTIS_Msk (0x01UL << ETH_INTERRUPT_STATUS_PMTIS_Pos) /*!< ETH INTERRUPT_STATUS: PMTIS Mask */
\r
6431 #define ETH_INTERRUPT_STATUS_MMCIS_Pos 4 /*!< ETH INTERRUPT_STATUS: MMCIS Position */
\r
6432 #define ETH_INTERRUPT_STATUS_MMCIS_Msk (0x01UL << ETH_INTERRUPT_STATUS_MMCIS_Pos) /*!< ETH INTERRUPT_STATUS: MMCIS Mask */
\r
6433 #define ETH_INTERRUPT_STATUS_MMCRXIS_Pos 5 /*!< ETH INTERRUPT_STATUS: MMCRXIS Position */
\r
6434 #define ETH_INTERRUPT_STATUS_MMCRXIS_Msk (0x01UL << ETH_INTERRUPT_STATUS_MMCRXIS_Pos) /*!< ETH INTERRUPT_STATUS: MMCRXIS Mask */
\r
6435 #define ETH_INTERRUPT_STATUS_MMCTXIS_Pos 6 /*!< ETH INTERRUPT_STATUS: MMCTXIS Position */
\r
6436 #define ETH_INTERRUPT_STATUS_MMCTXIS_Msk (0x01UL << ETH_INTERRUPT_STATUS_MMCTXIS_Pos) /*!< ETH INTERRUPT_STATUS: MMCTXIS Mask */
\r
6437 #define ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos 7 /*!< ETH INTERRUPT_STATUS: MMCRXIPIS Position */
\r
6438 #define ETH_INTERRUPT_STATUS_MMCRXIPIS_Msk (0x01UL << ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos) /*!< ETH INTERRUPT_STATUS: MMCRXIPIS Mask */
\r
6439 #define ETH_INTERRUPT_STATUS_Reserved_8_Pos 8 /*!< ETH INTERRUPT_STATUS: Reserved_8 Position */
\r
6440 #define ETH_INTERRUPT_STATUS_Reserved_8_Msk (0x01UL << ETH_INTERRUPT_STATUS_Reserved_8_Pos) /*!< ETH INTERRUPT_STATUS: Reserved_8 Mask */
\r
6441 #define ETH_INTERRUPT_STATUS_TSIS_Pos 9 /*!< ETH INTERRUPT_STATUS: TSIS Position */
\r
6442 #define ETH_INTERRUPT_STATUS_TSIS_Msk (0x01UL << ETH_INTERRUPT_STATUS_TSIS_Pos) /*!< ETH INTERRUPT_STATUS: TSIS Mask */
\r
6443 #define ETH_INTERRUPT_STATUS_Reserved_10_Pos 10 /*!< ETH INTERRUPT_STATUS: Reserved_10 Position */
\r
6444 #define ETH_INTERRUPT_STATUS_Reserved_10_Msk (0x01UL << ETH_INTERRUPT_STATUS_Reserved_10_Pos) /*!< ETH INTERRUPT_STATUS: Reserved_10 Mask */
\r
6445 #define ETH_INTERRUPT_STATUS_Reserved_31_11_Pos 11 /*!< ETH INTERRUPT_STATUS: Reserved_31_11 Position */
\r
6446 #define ETH_INTERRUPT_STATUS_Reserved_31_11_Msk (0x001fffffUL << ETH_INTERRUPT_STATUS_Reserved_31_11_Pos)/*!< ETH INTERRUPT_STATUS: Reserved_31_11 Mask */
\r
6448 /* ----------------------------- ETH_INTERRUPT_MASK ----------------------------- */
\r
6449 #define ETH_INTERRUPT_MASK_Reserved_2_0_Pos 0 /*!< ETH INTERRUPT_MASK: Reserved_2_0 Position */
\r
6450 #define ETH_INTERRUPT_MASK_Reserved_2_0_Msk (0x07UL << ETH_INTERRUPT_MASK_Reserved_2_0_Pos) /*!< ETH INTERRUPT_MASK: Reserved_2_0 Mask */
\r
6451 #define ETH_INTERRUPT_MASK_PMTIM_Pos 3 /*!< ETH INTERRUPT_MASK: PMTIM Position */
\r
6452 #define ETH_INTERRUPT_MASK_PMTIM_Msk (0x01UL << ETH_INTERRUPT_MASK_PMTIM_Pos) /*!< ETH INTERRUPT_MASK: PMTIM Mask */
\r
6453 #define ETH_INTERRUPT_MASK_Reserved_8_4_Pos 4 /*!< ETH INTERRUPT_MASK: Reserved_8_4 Position */
\r
6454 #define ETH_INTERRUPT_MASK_Reserved_8_4_Msk (0x1fUL << ETH_INTERRUPT_MASK_Reserved_8_4_Pos) /*!< ETH INTERRUPT_MASK: Reserved_8_4 Mask */
\r
6455 #define ETH_INTERRUPT_MASK_TSIM_Pos 9 /*!< ETH INTERRUPT_MASK: TSIM Position */
\r
6456 #define ETH_INTERRUPT_MASK_TSIM_Msk (0x01UL << ETH_INTERRUPT_MASK_TSIM_Pos) /*!< ETH INTERRUPT_MASK: TSIM Mask */
\r
6457 #define ETH_INTERRUPT_MASK_Reserved_31_10_Pos 10 /*!< ETH INTERRUPT_MASK: Reserved_31_10 Position */
\r
6458 #define ETH_INTERRUPT_MASK_Reserved_31_10_Msk (0x003fffffUL << ETH_INTERRUPT_MASK_Reserved_31_10_Pos) /*!< ETH INTERRUPT_MASK: Reserved_31_10 Mask */
\r
6460 /* ---------------------------- ETH_MAC_ADDRESS0_HIGH --------------------------- */
\r
6461 #define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos 0 /*!< ETH MAC_ADDRESS0_HIGH: ADDRHI Position */
\r
6462 #define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Msk (0x0000ffffUL << ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos) /*!< ETH MAC_ADDRESS0_HIGH: ADDRHI Mask */
\r
6463 #define ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Pos 16 /*!< ETH MAC_ADDRESS0_HIGH: Reserved_30_16 Position */
\r
6464 #define ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Msk (0x00007fffUL << ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Pos)/*!< ETH MAC_ADDRESS0_HIGH: Reserved_30_16 Mask */
\r
6465 #define ETH_MAC_ADDRESS0_HIGH_AE_Pos 31 /*!< ETH MAC_ADDRESS0_HIGH: AE Position */
\r
6466 #define ETH_MAC_ADDRESS0_HIGH_AE_Msk (0x01UL << ETH_MAC_ADDRESS0_HIGH_AE_Pos) /*!< ETH MAC_ADDRESS0_HIGH: AE Mask */
\r
6468 /* ---------------------------- ETH_MAC_ADDRESS0_LOW ---------------------------- */
\r
6469 #define ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos 0 /*!< ETH MAC_ADDRESS0_LOW: ADDRLO Position */
\r
6470 #define ETH_MAC_ADDRESS0_LOW_ADDRLO_Msk (0xffffffffUL << ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos) /*!< ETH MAC_ADDRESS0_LOW: ADDRLO Mask */
\r
6472 /* ---------------------------- ETH_MAC_ADDRESS1_HIGH --------------------------- */
\r
6473 #define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos 0 /*!< ETH MAC_ADDRESS1_HIGH: ADDRHI Position */
\r
6474 #define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Msk (0x0000ffffUL << ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos) /*!< ETH MAC_ADDRESS1_HIGH: ADDRHI Mask */
\r
6475 #define ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Pos 16 /*!< ETH MAC_ADDRESS1_HIGH: Reserved_23_16 Position */
\r
6476 #define ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Msk (0x000000ffUL << ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Pos)/*!< ETH MAC_ADDRESS1_HIGH: Reserved_23_16 Mask */
\r
6477 #define ETH_MAC_ADDRESS1_HIGH_MBC_Pos 24 /*!< ETH MAC_ADDRESS1_HIGH: MBC Position */
\r
6478 #define ETH_MAC_ADDRESS1_HIGH_MBC_Msk (0x3fUL << ETH_MAC_ADDRESS1_HIGH_MBC_Pos) /*!< ETH MAC_ADDRESS1_HIGH: MBC Mask */
\r
6479 #define ETH_MAC_ADDRESS1_HIGH_SA_Pos 30 /*!< ETH MAC_ADDRESS1_HIGH: SA Position */
\r
6480 #define ETH_MAC_ADDRESS1_HIGH_SA_Msk (0x01UL << ETH_MAC_ADDRESS1_HIGH_SA_Pos) /*!< ETH MAC_ADDRESS1_HIGH: SA Mask */
\r
6481 #define ETH_MAC_ADDRESS1_HIGH_AE_Pos 31 /*!< ETH MAC_ADDRESS1_HIGH: AE Position */
\r
6482 #define ETH_MAC_ADDRESS1_HIGH_AE_Msk (0x01UL << ETH_MAC_ADDRESS1_HIGH_AE_Pos) /*!< ETH MAC_ADDRESS1_HIGH: AE Mask */
\r
6484 /* ---------------------------- ETH_MAC_ADDRESS1_LOW ---------------------------- */
\r
6485 #define ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos 0 /*!< ETH MAC_ADDRESS1_LOW: ADDRLO Position */
\r
6486 #define ETH_MAC_ADDRESS1_LOW_ADDRLO_Msk (0xffffffffUL << ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos) /*!< ETH MAC_ADDRESS1_LOW: ADDRLO Mask */
\r
6488 /* ---------------------------- ETH_MAC_ADDRESS2_HIGH --------------------------- */
\r
6489 #define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos 0 /*!< ETH MAC_ADDRESS2_HIGH: ADDRHI Position */
\r
6490 #define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Msk (0x0000ffffUL << ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos) /*!< ETH MAC_ADDRESS2_HIGH: ADDRHI Mask */
\r
6491 #define ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Pos 16 /*!< ETH MAC_ADDRESS2_HIGH: Reserved_23_16 Position */
\r
6492 #define ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Msk (0x000000ffUL << ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Pos)/*!< ETH MAC_ADDRESS2_HIGH: Reserved_23_16 Mask */
\r
6493 #define ETH_MAC_ADDRESS2_HIGH_MBC_Pos 24 /*!< ETH MAC_ADDRESS2_HIGH: MBC Position */
\r
6494 #define ETH_MAC_ADDRESS2_HIGH_MBC_Msk (0x3fUL << ETH_MAC_ADDRESS2_HIGH_MBC_Pos) /*!< ETH MAC_ADDRESS2_HIGH: MBC Mask */
\r
6495 #define ETH_MAC_ADDRESS2_HIGH_SA_Pos 30 /*!< ETH MAC_ADDRESS2_HIGH: SA Position */
\r
6496 #define ETH_MAC_ADDRESS2_HIGH_SA_Msk (0x01UL << ETH_MAC_ADDRESS2_HIGH_SA_Pos) /*!< ETH MAC_ADDRESS2_HIGH: SA Mask */
\r
6497 #define ETH_MAC_ADDRESS2_HIGH_AE_Pos 31 /*!< ETH MAC_ADDRESS2_HIGH: AE Position */
\r
6498 #define ETH_MAC_ADDRESS2_HIGH_AE_Msk (0x01UL << ETH_MAC_ADDRESS2_HIGH_AE_Pos) /*!< ETH MAC_ADDRESS2_HIGH: AE Mask */
\r
6500 /* ---------------------------- ETH_MAC_ADDRESS2_LOW ---------------------------- */
\r
6501 #define ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos 0 /*!< ETH MAC_ADDRESS2_LOW: ADDRLO Position */
\r
6502 #define ETH_MAC_ADDRESS2_LOW_ADDRLO_Msk (0xffffffffUL << ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos) /*!< ETH MAC_ADDRESS2_LOW: ADDRLO Mask */
\r
6504 /* ---------------------------- ETH_MAC_ADDRESS3_HIGH --------------------------- */
\r
6505 #define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos 0 /*!< ETH MAC_ADDRESS3_HIGH: ADDRHI Position */
\r
6506 #define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Msk (0x0000ffffUL << ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos) /*!< ETH MAC_ADDRESS3_HIGH: ADDRHI Mask */
\r
6507 #define ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Pos 16 /*!< ETH MAC_ADDRESS3_HIGH: Reserved_23_16 Position */
\r
6508 #define ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Msk (0x000000ffUL << ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Pos)/*!< ETH MAC_ADDRESS3_HIGH: Reserved_23_16 Mask */
\r
6509 #define ETH_MAC_ADDRESS3_HIGH_MBC_Pos 24 /*!< ETH MAC_ADDRESS3_HIGH: MBC Position */
\r
6510 #define ETH_MAC_ADDRESS3_HIGH_MBC_Msk (0x3fUL << ETH_MAC_ADDRESS3_HIGH_MBC_Pos) /*!< ETH MAC_ADDRESS3_HIGH: MBC Mask */
\r
6511 #define ETH_MAC_ADDRESS3_HIGH_SA_Pos 30 /*!< ETH MAC_ADDRESS3_HIGH: SA Position */
\r
6512 #define ETH_MAC_ADDRESS3_HIGH_SA_Msk (0x01UL << ETH_MAC_ADDRESS3_HIGH_SA_Pos) /*!< ETH MAC_ADDRESS3_HIGH: SA Mask */
\r
6513 #define ETH_MAC_ADDRESS3_HIGH_AE_Pos 31 /*!< ETH MAC_ADDRESS3_HIGH: AE Position */
\r
6514 #define ETH_MAC_ADDRESS3_HIGH_AE_Msk (0x01UL << ETH_MAC_ADDRESS3_HIGH_AE_Pos) /*!< ETH MAC_ADDRESS3_HIGH: AE Mask */
\r
6516 /* ---------------------------- ETH_MAC_ADDRESS3_LOW ---------------------------- */
\r
6517 #define ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos 0 /*!< ETH MAC_ADDRESS3_LOW: ADDRLO Position */
\r
6518 #define ETH_MAC_ADDRESS3_LOW_ADDRLO_Msk (0xffffffffUL << ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos) /*!< ETH MAC_ADDRESS3_LOW: ADDRLO Mask */
\r
6520 /* ------------------------------- ETH_MMC_CONTROL ------------------------------ */
\r
6521 #define ETH_MMC_CONTROL_CNTRST_Pos 0 /*!< ETH MMC_CONTROL: CNTRST Position */
\r
6522 #define ETH_MMC_CONTROL_CNTRST_Msk (0x01UL << ETH_MMC_CONTROL_CNTRST_Pos) /*!< ETH MMC_CONTROL: CNTRST Mask */
\r
6523 #define ETH_MMC_CONTROL_CNTSTOPRO_Pos 1 /*!< ETH MMC_CONTROL: CNTSTOPRO Position */
\r
6524 #define ETH_MMC_CONTROL_CNTSTOPRO_Msk (0x01UL << ETH_MMC_CONTROL_CNTSTOPRO_Pos) /*!< ETH MMC_CONTROL: CNTSTOPRO Mask */
\r
6525 #define ETH_MMC_CONTROL_RSTONRD_Pos 2 /*!< ETH MMC_CONTROL: RSTONRD Position */
\r
6526 #define ETH_MMC_CONTROL_RSTONRD_Msk (0x01UL << ETH_MMC_CONTROL_RSTONRD_Pos) /*!< ETH MMC_CONTROL: RSTONRD Mask */
\r
6527 #define ETH_MMC_CONTROL_CNTFREEZ_Pos 3 /*!< ETH MMC_CONTROL: CNTFREEZ Position */
\r
6528 #define ETH_MMC_CONTROL_CNTFREEZ_Msk (0x01UL << ETH_MMC_CONTROL_CNTFREEZ_Pos) /*!< ETH MMC_CONTROL: CNTFREEZ Mask */
\r
6529 #define ETH_MMC_CONTROL_CNTPRST_Pos 4 /*!< ETH MMC_CONTROL: CNTPRST Position */
\r
6530 #define ETH_MMC_CONTROL_CNTPRST_Msk (0x01UL << ETH_MMC_CONTROL_CNTPRST_Pos) /*!< ETH MMC_CONTROL: CNTPRST Mask */
\r
6531 #define ETH_MMC_CONTROL_CNTPRSTLVL_Pos 5 /*!< ETH MMC_CONTROL: CNTPRSTLVL Position */
\r
6532 #define ETH_MMC_CONTROL_CNTPRSTLVL_Msk (0x01UL << ETH_MMC_CONTROL_CNTPRSTLVL_Pos) /*!< ETH MMC_CONTROL: CNTPRSTLVL Mask */
\r
6533 #define ETH_MMC_CONTROL_Reserved_7_6_Pos 6 /*!< ETH MMC_CONTROL: Reserved_7_6 Position */
\r
6534 #define ETH_MMC_CONTROL_Reserved_7_6_Msk (0x03UL << ETH_MMC_CONTROL_Reserved_7_6_Pos) /*!< ETH MMC_CONTROL: Reserved_7_6 Mask */
\r
6535 #define ETH_MMC_CONTROL_UCDBC_Pos 8 /*!< ETH MMC_CONTROL: UCDBC Position */
\r
6536 #define ETH_MMC_CONTROL_UCDBC_Msk (0x01UL << ETH_MMC_CONTROL_UCDBC_Pos) /*!< ETH MMC_CONTROL: UCDBC Mask */
\r
6537 #define ETH_MMC_CONTROL_Reserved_31_9_Pos 9 /*!< ETH MMC_CONTROL: Reserved_31_9 Position */
\r
6538 #define ETH_MMC_CONTROL_Reserved_31_9_Msk (0x007fffffUL << ETH_MMC_CONTROL_Reserved_31_9_Pos) /*!< ETH MMC_CONTROL: Reserved_31_9 Mask */
\r
6540 /* -------------------------- ETH_MMC_RECEIVE_INTERRUPT ------------------------- */
\r
6541 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos 0 /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBFRMIS Position */
\r
6542 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBFRMIS Mask */
\r
6543 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos 1 /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBOCTIS Position */
\r
6544 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBOCTIS Mask */
\r
6545 #define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos 2 /*!< ETH MMC_RECEIVE_INTERRUPT: RXGOCTIS Position */
\r
6546 #define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGOCTIS Mask */
\r
6547 #define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos 3 /*!< ETH MMC_RECEIVE_INTERRUPT: RXBCGFIS Position */
\r
6548 #define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXBCGFIS Mask */
\r
6549 #define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos 4 /*!< ETH MMC_RECEIVE_INTERRUPT: RXMCGFIS Position */
\r
6550 #define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXMCGFIS Mask */
\r
6551 #define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos 5 /*!< ETH MMC_RECEIVE_INTERRUPT: RXCRCERFIS Position */
\r
6552 #define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXCRCERFIS Mask */
\r
6553 #define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos 6 /*!< ETH MMC_RECEIVE_INTERRUPT: RXALGNERFIS Position */
\r
6554 #define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXALGNERFIS Mask */
\r
6555 #define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos 7 /*!< ETH MMC_RECEIVE_INTERRUPT: RXRUNTFIS Position */
\r
6556 #define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXRUNTFIS Mask */
\r
6557 #define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos 8 /*!< ETH MMC_RECEIVE_INTERRUPT: RXJABERFIS Position */
\r
6558 #define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXJABERFIS Mask */
\r
6559 #define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos 9 /*!< ETH MMC_RECEIVE_INTERRUPT: RXUSIZEGFIS Position */
\r
6560 #define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXUSIZEGFIS Mask */
\r
6561 #define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos 10 /*!< ETH MMC_RECEIVE_INTERRUPT: RXOSIZEGFIS Position */
\r
6562 #define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXOSIZEGFIS Mask */
\r
6563 #define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos 11 /*!< ETH MMC_RECEIVE_INTERRUPT: RX64OCTGBFIS Position */
\r
6564 #define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX64OCTGBFIS Mask */
\r
6565 #define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos 12 /*!< ETH MMC_RECEIVE_INTERRUPT: RX65T127OCTGBFIS Position */
\r
6566 #define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX65T127OCTGBFIS Mask */
\r
6567 #define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos 13 /*!< ETH MMC_RECEIVE_INTERRUPT: RX128T255OCTGBFIS Position */
\r
6568 #define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX128T255OCTGBFIS Mask */
\r
6569 #define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos 14 /*!< ETH MMC_RECEIVE_INTERRUPT: RX256T511OCTGBFIS Position */
\r
6570 #define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX256T511OCTGBFIS Mask */
\r
6571 #define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos 15 /*!< ETH MMC_RECEIVE_INTERRUPT: RX512T1023OCTGBFIS Position */
\r
6572 #define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX512T1023OCTGBFIS Mask */
\r
6573 #define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos 16 /*!< ETH MMC_RECEIVE_INTERRUPT: RX1024TMAXOCTGBFIS Position */
\r
6574 #define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX1024TMAXOCTGBFIS Mask */
\r
6575 #define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos 17 /*!< ETH MMC_RECEIVE_INTERRUPT: RXUCGFIS Position */
\r
6576 #define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXUCGFIS Mask */
\r
6577 #define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos 18 /*!< ETH MMC_RECEIVE_INTERRUPT: RXLENERFIS Position */
\r
6578 #define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXLENERFIS Mask */
\r
6579 #define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos 19 /*!< ETH MMC_RECEIVE_INTERRUPT: RXORANGEFIS Position */
\r
6580 #define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXORANGEFIS Mask */
\r
6581 #define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos 20 /*!< ETH MMC_RECEIVE_INTERRUPT: RXPAUSFIS Position */
\r
6582 #define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXPAUSFIS Mask */
\r
6583 #define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos 21 /*!< ETH MMC_RECEIVE_INTERRUPT: RXFOVFIS Position */
\r
6584 #define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXFOVFIS Mask */
\r
6585 #define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos 22 /*!< ETH MMC_RECEIVE_INTERRUPT: RXVLANGBFIS Position */
\r
6586 #define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXVLANGBFIS Mask */
\r
6587 #define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos 23 /*!< ETH MMC_RECEIVE_INTERRUPT: RXWDOGFIS Position */
\r
6588 #define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXWDOGFIS Mask */
\r
6589 #define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos 24 /*!< ETH MMC_RECEIVE_INTERRUPT: RXRCVERRFIS Position */
\r
6590 #define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXRCVERRFIS Mask */
\r
6591 #define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos 25 /*!< ETH MMC_RECEIVE_INTERRUPT: RXCTRLFIS Position */
\r
6592 #define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXCTRLFIS Mask */
\r
6593 #define ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Pos 26 /*!< ETH MMC_RECEIVE_INTERRUPT: Reserved_31_26 Position */
\r
6594 #define ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Msk (0x3fUL << ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: Reserved_31_26 Mask */
\r
6596 /* ------------------------- ETH_MMC_TRANSMIT_INTERRUPT ------------------------- */
\r
6597 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos 0 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBOCTIS Position */
\r
6598 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBOCTIS Mask */
\r
6599 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos 1 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBFRMIS Position */
\r
6600 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBFRMIS Mask */
\r
6601 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos 2 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGFIS Position */
\r
6602 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGFIS Mask */
\r
6603 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos 3 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGFIS Position */
\r
6604 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGFIS Mask */
\r
6605 #define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos 4 /*!< ETH MMC_TRANSMIT_INTERRUPT: TX64OCTGBFIS Position */
\r
6606 #define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX64OCTGBFIS Mask */
\r
6607 #define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos 5 /*!< ETH MMC_TRANSMIT_INTERRUPT: TX65T127OCTGBFIS Position */
\r
6608 #define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX65T127OCTGBFIS Mask */
\r
6609 #define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos 6 /*!< ETH MMC_TRANSMIT_INTERRUPT: TX128T255OCTGBFIS Position */
\r
6610 #define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX128T255OCTGBFIS Mask */
\r
6611 #define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos 7 /*!< ETH MMC_TRANSMIT_INTERRUPT: TX256T511OCTGBFIS Position */
\r
6612 #define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX256T511OCTGBFIS Mask */
\r
6613 #define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos 8 /*!< ETH MMC_TRANSMIT_INTERRUPT: TX512T1023OCTGBFIS Position */
\r
6614 #define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX512T1023OCTGBFIS Mask */
\r
6615 #define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos 9 /*!< ETH MMC_TRANSMIT_INTERRUPT: TX1024TMAXOCTGBFIS Position */
\r
6616 #define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX1024TMAXOCTGBFIS Mask */
\r
6617 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos 10 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUCGBFIS Position */
\r
6618 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUCGBFIS Mask */
\r
6619 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos 11 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGBFIS Position */
\r
6620 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGBFIS Mask */
\r
6621 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos 12 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGBFIS Position */
\r
6622 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGBFIS Mask */
\r
6623 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos 13 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUFLOWERFIS Position */
\r
6624 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXUFLOWERFIS Mask */
\r
6625 #define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos 14 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXSCOLGFIS Position */
\r
6626 #define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXSCOLGFIS Mask */
\r
6627 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos 15 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCOLGFIS Position */
\r
6628 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCOLGFIS Mask */
\r
6629 #define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos 16 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXDEFFIS Position */
\r
6630 #define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXDEFFIS Mask */
\r
6631 #define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos 17 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXLATCOLFIS Position */
\r
6632 #define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXLATCOLFIS Mask */
\r
6633 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos 18 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXCOLFIS Position */
\r
6634 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXCOLFIS Mask */
\r
6635 #define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos 19 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXCARERFIS Position */
\r
6636 #define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXCARERFIS Mask */
\r
6637 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos 20 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGOCTIS Position */
\r
6638 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGOCTIS Mask */
\r
6639 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos 21 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGFRMIS Position */
\r
6640 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGFRMIS Mask */
\r
6641 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos 22 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXDEFFIS Position */
\r
6642 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXDEFFIS Mask */
\r
6643 #define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos 23 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXPAUSFIS Position */
\r
6644 #define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXPAUSFIS Mask */
\r
6645 #define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos 24 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXVLANGFIS Position */
\r
6646 #define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXVLANGFIS Mask */
\r
6647 #define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos 25 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXOSIZEGFIS Position */
\r
6648 #define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXOSIZEGFIS Mask */
\r
6649 #define ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Pos 26 /*!< ETH MMC_TRANSMIT_INTERRUPT: Reserved_31_26 Position */
\r
6650 #define ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Msk (0x3fUL << ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: Reserved_31_26 Mask */
\r
6652 /* ----------------------- ETH_MMC_RECEIVE_INTERRUPT_MASK ----------------------- */
\r
6653 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos 0 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBFRMIM Position */
\r
6654 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBFRMIM Mask */
\r
6655 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos 1 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBOCTIM Position */
\r
6656 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBOCTIM Mask */
\r
6657 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos 2 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGOCTIM Position */
\r
6658 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGOCTIM Mask */
\r
6659 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos 3 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXBCGFIM Position */
\r
6660 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXBCGFIM Mask */
\r
6661 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos 4 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXMCGFIM Position */
\r
6662 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXMCGFIM Mask */
\r
6663 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos 5 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCRCERFIM Position */
\r
6664 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCRCERFIM Mask */
\r
6665 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos 6 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXALGNERFIM Position */
\r
6666 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXALGNERFIM Mask */
\r
6667 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos 7 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRUNTFIM Position */
\r
6668 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRUNTFIM Mask */
\r
6669 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos 8 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXJABERFIM Position */
\r
6670 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXJABERFIM Mask */
\r
6671 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos 9 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUSIZEGFIM Position */
\r
6672 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUSIZEGFIM Mask */
\r
6673 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos 10 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXOSIZEGFIM Position */
\r
6674 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXOSIZEGFIM Mask */
\r
6675 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos 11 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX64OCTGBFIM Position */
\r
6676 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX64OCTGBFIM Mask */
\r
6677 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos 12 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX65T127OCTGBFIM Position */
\r
6678 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX65T127OCTGBFIM Mask */
\r
6679 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos 13 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX128T255OCTGBFIM Position */
\r
6680 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX128T255OCTGBFIM Mask */
\r
6681 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos 14 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX256T511OCTGBFIM Position */
\r
6682 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX256T511OCTGBFIM Mask */
\r
6683 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos 15 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX512T1023OCTGBFIM Position */
\r
6684 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX512T1023OCTGBFIM Mask */
\r
6685 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos 16 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX1024TMAXOCTGBFIM Position */
\r
6686 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX1024TMAXOCTGBFIM Mask */
\r
6687 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos 17 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUCGFIM Position */
\r
6688 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUCGFIM Mask */
\r
6689 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos 18 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXLENERFIM Position */
\r
6690 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXLENERFIM Mask */
\r
6691 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos 19 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXORANGEFIM Position */
\r
6692 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXORANGEFIM Mask */
\r
6693 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos 20 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXPAUSFIM Position */
\r
6694 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXPAUSFIM Mask */
\r
6695 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos 21 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXFOVFIM Position */
\r
6696 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXFOVFIM Mask */
\r
6697 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos 22 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXVLANGBFIM Position */
\r
6698 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXVLANGBFIM Mask */
\r
6699 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos 23 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXWDOGFIM Position */
\r
6700 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXWDOGFIM Mask */
\r
6701 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos 24 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRCVERRFIM Position */
\r
6702 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRCVERRFIM Mask */
\r
6703 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos 25 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCTRLFIM Position */
\r
6704 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCTRLFIM Mask */
\r
6705 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Pos 26 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: Reserved_31_26 Position */
\r
6706 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Msk (0x3fUL << ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: Reserved_31_26 Mask */
\r
6708 /* ----------------------- ETH_MMC_TRANSMIT_INTERRUPT_MASK ---------------------- */
\r
6709 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos 0 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBOCTIM Position */
\r
6710 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBOCTIM Mask */
\r
6711 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos 1 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBFRMIM Position */
\r
6712 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBFRMIM Mask */
\r
6713 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos 2 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGFIM Position */
\r
6714 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGFIM Mask */
\r
6715 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos 3 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGFIM Position */
\r
6716 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGFIM Mask */
\r
6717 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos 4 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX64OCTGBFIM Position */
\r
6718 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX64OCTGBFIM Mask */
\r
6719 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos 5 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX65T127OCTGBFIM Position */
\r
6720 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX65T127OCTGBFIM Mask */
\r
6721 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos 6 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX128T255OCTGBFIM Position */
\r
6722 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX128T255OCTGBFIM Mask */
\r
6723 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos 7 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX256T511OCTGBFIM Position */
\r
6724 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX256T511OCTGBFIM Mask */
\r
6725 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos 8 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX512T1023OCTGBFIM Position */
\r
6726 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX512T1023OCTGBFIM Mask */
\r
6727 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos 9 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX1024TMAXOCTGBFIM Position */
\r
6728 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX1024TMAXOCTGBFIM Mask */
\r
6729 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos 10 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUCGBFIM Position */
\r
6730 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUCGBFIM Mask */
\r
6731 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos 11 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGBFIM Position */
\r
6732 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGBFIM Mask */
\r
6733 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos 12 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGBFIM Position */
\r
6734 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGBFIM Mask */
\r
6735 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos 13 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUFLOWERFIM Position */
\r
6736 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUFLOWERFIM Mask */
\r
6737 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos 14 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXSCOLGFIM Position */
\r
6738 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXSCOLGFIM Mask */
\r
6739 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos 15 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCOLGFIM Position */
\r
6740 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCOLGFIM Mask */
\r
6741 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos 16 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXDEFFIM Position */
\r
6742 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXDEFFIM Mask */
\r
6743 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos 17 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXLATCOLFIM Position */
\r
6744 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXLATCOLFIM Mask */
\r
6745 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos 18 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXCOLFIM Position */
\r
6746 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXCOLFIM Mask */
\r
6747 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos 19 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXCARERFIM Position */
\r
6748 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXCARERFIM Mask */
\r
6749 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos 20 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGOCTIM Position */
\r
6750 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGOCTIM Mask */
\r
6751 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos 21 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGFRMIM Position */
\r
6752 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGFRMIM Mask */
\r
6753 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos 22 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXDEFFIM Position */
\r
6754 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXDEFFIM Mask */
\r
6755 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos 23 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXPAUSFIM Position */
\r
6756 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXPAUSFIM Mask */
\r
6757 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos 24 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXVLANGFIM Position */
\r
6758 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXVLANGFIM Mask */
\r
6759 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos 25 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXOSIZEGFIM Position */
\r
6760 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXOSIZEGFIM Mask */
\r
6761 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Pos 26 /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: Reserved_31_26 Position */
\r
6762 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Msk (0x3fUL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: Reserved_31_26 Mask */
\r
6764 /* ------------------------- ETH_TX_OCTET_COUNT_GOOD_BAD ------------------------ */
\r
6765 #define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos 0 /*!< ETH TX_OCTET_COUNT_GOOD_BAD: TXOCTGB Position */
\r
6766 #define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Msk (0xffffffffUL << ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos)/*!< ETH TX_OCTET_COUNT_GOOD_BAD: TXOCTGB Mask */
\r
6768 /* ------------------------- ETH_TX_FRAME_COUNT_GOOD_BAD ------------------------ */
\r
6769 #define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos 0 /*!< ETH TX_FRAME_COUNT_GOOD_BAD: TXFRMGB Position */
\r
6770 #define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Msk (0xffffffffUL << ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos)/*!< ETH TX_FRAME_COUNT_GOOD_BAD: TXFRMGB Mask */
\r
6772 /* ------------------------ ETH_TX_BROADCAST_FRAMES_GOOD ------------------------ */
\r
6773 #define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos 0 /*!< ETH TX_BROADCAST_FRAMES_GOOD: TXBCASTG Position */
\r
6774 #define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Msk (0xffffffffUL << ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos)/*!< ETH TX_BROADCAST_FRAMES_GOOD: TXBCASTG Mask */
\r
6776 /* ------------------------ ETH_TX_MULTICAST_FRAMES_GOOD ------------------------ */
\r
6777 #define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos 0 /*!< ETH TX_MULTICAST_FRAMES_GOOD: TXMCASTG Position */
\r
6778 #define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Msk (0xffffffffUL << ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos)/*!< ETH TX_MULTICAST_FRAMES_GOOD: TXMCASTG Mask */
\r
6780 /* ----------------------- ETH_TX_64OCTETS_FRAMES_GOOD_BAD ---------------------- */
\r
6781 #define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos 0 /*!< ETH TX_64OCTETS_FRAMES_GOOD_BAD: TX64OCTGB Position */
\r
6782 #define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Msk (0xffffffffUL << ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos)/*!< ETH TX_64OCTETS_FRAMES_GOOD_BAD: TX64OCTGB Mask */
\r
6784 /* -------------------- ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD -------------------- */
\r
6785 #define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos 0 /*!< ETH TX_65TO127OCTETS_FRAMES_GOOD_BAD: TX65_127OCTGB Position */
\r
6786 #define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Msk (0xffffffffUL << ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos)/*!< ETH TX_65TO127OCTETS_FRAMES_GOOD_BAD: TX65_127OCTGB Mask */
\r
6788 /* -------------------- ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD ------------------- */
\r
6789 #define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos 0 /*!< ETH TX_128TO255OCTETS_FRAMES_GOOD_BAD: TX128_255OCTGB Position */
\r
6790 #define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Msk (0xffffffffUL << ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos)/*!< ETH TX_128TO255OCTETS_FRAMES_GOOD_BAD: TX128_255OCTGB Mask */
\r
6792 /* -------------------- ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD ------------------- */
\r
6793 #define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos 0 /*!< ETH TX_256TO511OCTETS_FRAMES_GOOD_BAD: TX256_511OCTGB Position */
\r
6794 #define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Msk (0xffffffffUL << ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos)/*!< ETH TX_256TO511OCTETS_FRAMES_GOOD_BAD: TX256_511OCTGB Mask */
\r
6796 /* ------------------- ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD ------------------- */
\r
6797 #define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos 0 /*!< ETH TX_512TO1023OCTETS_FRAMES_GOOD_BAD: TX512_1023OCTGB Position */
\r
6798 #define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Msk (0xffffffffUL << ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos)/*!< ETH TX_512TO1023OCTETS_FRAMES_GOOD_BAD: TX512_1023OCTGB Mask */
\r
6800 /* ------------------- ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD ------------------- */
\r
6801 #define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos 0 /*!< ETH TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: TX1024_MAXOCTGB Position */
\r
6802 #define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Msk (0xffffffffUL << ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos)/*!< ETH TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: TX1024_MAXOCTGB Mask */
\r
6804 /* ----------------------- ETH_TX_UNICAST_FRAMES_GOOD_BAD ----------------------- */
\r
6805 #define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos 0 /*!< ETH TX_UNICAST_FRAMES_GOOD_BAD: TXUCASTGB Position */
\r
6806 #define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Msk (0xffffffffUL << ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos)/*!< ETH TX_UNICAST_FRAMES_GOOD_BAD: TXUCASTGB Mask */
\r
6808 /* ---------------------- ETH_TX_MULTICAST_FRAMES_GOOD_BAD ---------------------- */
\r
6809 #define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos 0 /*!< ETH TX_MULTICAST_FRAMES_GOOD_BAD: TXMCASTGB Position */
\r
6810 #define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Msk (0xffffffffUL << ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos)/*!< ETH TX_MULTICAST_FRAMES_GOOD_BAD: TXMCASTGB Mask */
\r
6812 /* ---------------------- ETH_TX_BROADCAST_FRAMES_GOOD_BAD ---------------------- */
\r
6813 #define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos 0 /*!< ETH TX_BROADCAST_FRAMES_GOOD_BAD: TXBCASTGB Position */
\r
6814 #define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Msk (0xffffffffUL << ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos)/*!< ETH TX_BROADCAST_FRAMES_GOOD_BAD: TXBCASTGB Mask */
\r
6816 /* ------------------------ ETH_TX_UNDERFLOW_ERROR_FRAMES ----------------------- */
\r
6817 #define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos 0 /*!< ETH TX_UNDERFLOW_ERROR_FRAMES: TXUNDRFLW Position */
\r
6818 #define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Msk (0xffffffffUL << ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos)/*!< ETH TX_UNDERFLOW_ERROR_FRAMES: TXUNDRFLW Mask */
\r
6820 /* --------------------- ETH_TX_SINGLE_COLLISION_GOOD_FRAMES -------------------- */
\r
6821 #define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos 0 /*!< ETH TX_SINGLE_COLLISION_GOOD_FRAMES: TXSNGLCOLG Position */
\r
6822 #define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Msk (0xffffffffUL << ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos)/*!< ETH TX_SINGLE_COLLISION_GOOD_FRAMES: TXSNGLCOLG Mask */
\r
6824 /* -------------------- ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES ------------------- */
\r
6825 #define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos 0 /*!< ETH TX_MULTIPLE_COLLISION_GOOD_FRAMES: TXMULTCOLG Position */
\r
6826 #define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Msk (0xffffffffUL << ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos)/*!< ETH TX_MULTIPLE_COLLISION_GOOD_FRAMES: TXMULTCOLG Mask */
\r
6828 /* --------------------------- ETH_TX_DEFERRED_FRAMES --------------------------- */
\r
6829 #define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos 0 /*!< ETH TX_DEFERRED_FRAMES: TXDEFRD Position */
\r
6830 #define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Msk (0xffffffffUL << ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos) /*!< ETH TX_DEFERRED_FRAMES: TXDEFRD Mask */
\r
6832 /* ------------------------ ETH_TX_LATE_COLLISION_FRAMES ------------------------ */
\r
6833 #define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos 0 /*!< ETH TX_LATE_COLLISION_FRAMES: TXLATECOL Position */
\r
6834 #define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Msk (0xffffffffUL << ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos)/*!< ETH TX_LATE_COLLISION_FRAMES: TXLATECOL Mask */
\r
6836 /* ---------------------- ETH_TX_EXCESSIVE_COLLISION_FRAMES --------------------- */
\r
6837 #define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos 0 /*!< ETH TX_EXCESSIVE_COLLISION_FRAMES: TXEXSCOL Position */
\r
6838 #define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Msk (0xffffffffUL << ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos)/*!< ETH TX_EXCESSIVE_COLLISION_FRAMES: TXEXSCOL Mask */
\r
6840 /* ------------------------- ETH_TX_CARRIER_ERROR_FRAMES ------------------------ */
\r
6841 #define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos 0 /*!< ETH TX_CARRIER_ERROR_FRAMES: TXCARR Position */
\r
6842 #define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Msk (0xffffffffUL << ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos)/*!< ETH TX_CARRIER_ERROR_FRAMES: TXCARR Mask */
\r
6844 /* --------------------------- ETH_TX_OCTET_COUNT_GOOD -------------------------- */
\r
6845 #define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos 0 /*!< ETH TX_OCTET_COUNT_GOOD: TXOCTG Position */
\r
6846 #define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Msk (0xffffffffUL << ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos) /*!< ETH TX_OCTET_COUNT_GOOD: TXOCTG Mask */
\r
6848 /* --------------------------- ETH_TX_FRAME_COUNT_GOOD -------------------------- */
\r
6849 #define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos 0 /*!< ETH TX_FRAME_COUNT_GOOD: TXFRMG Position */
\r
6850 #define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Msk (0xffffffffUL << ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos) /*!< ETH TX_FRAME_COUNT_GOOD: TXFRMG Mask */
\r
6852 /* ----------------------- ETH_TX_EXCESSIVE_DEFERRAL_ERROR ---------------------- */
\r
6853 #define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos 0 /*!< ETH TX_EXCESSIVE_DEFERRAL_ERROR: TXEXSDEF Position */
\r
6854 #define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Msk (0xffffffffUL << ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos)/*!< ETH TX_EXCESSIVE_DEFERRAL_ERROR: TXEXSDEF Mask */
\r
6856 /* ----------------------------- ETH_TX_PAUSE_FRAMES ---------------------------- */
\r
6857 #define ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos 0 /*!< ETH TX_PAUSE_FRAMES: TXPAUSE Position */
\r
6858 #define ETH_TX_PAUSE_FRAMES_TXPAUSE_Msk (0xffffffffUL << ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos) /*!< ETH TX_PAUSE_FRAMES: TXPAUSE Mask */
\r
6860 /* --------------------------- ETH_TX_VLAN_FRAMES_GOOD -------------------------- */
\r
6861 #define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos 0 /*!< ETH TX_VLAN_FRAMES_GOOD: TXVLANG Position */
\r
6862 #define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Msk (0xffffffffUL << ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos) /*!< ETH TX_VLAN_FRAMES_GOOD: TXVLANG Mask */
\r
6864 /* -------------------------- ETH_TX_OSIZE_FRAMES_GOOD -------------------------- */
\r
6865 #define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos 0 /*!< ETH TX_OSIZE_FRAMES_GOOD: TXOSIZG Position */
\r
6866 #define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Msk (0xffffffffUL << ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos) /*!< ETH TX_OSIZE_FRAMES_GOOD: TXOSIZG Mask */
\r
6868 /* ------------------------ ETH_RX_FRAMES_COUNT_GOOD_BAD ------------------------ */
\r
6869 #define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos 0 /*!< ETH RX_FRAMES_COUNT_GOOD_BAD: RXFRMGB Position */
\r
6870 #define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Msk (0xffffffffUL << ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos)/*!< ETH RX_FRAMES_COUNT_GOOD_BAD: RXFRMGB Mask */
\r
6872 /* ------------------------- ETH_RX_OCTET_COUNT_GOOD_BAD ------------------------ */
\r
6873 #define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos 0 /*!< ETH RX_OCTET_COUNT_GOOD_BAD: RXOCTGB Position */
\r
6874 #define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Msk (0xffffffffUL << ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos)/*!< ETH RX_OCTET_COUNT_GOOD_BAD: RXOCTGB Mask */
\r
6876 /* --------------------------- ETH_RX_OCTET_COUNT_GOOD -------------------------- */
\r
6877 #define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos 0 /*!< ETH RX_OCTET_COUNT_GOOD: RXOCTG Position */
\r
6878 #define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Msk (0xffffffffUL << ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos) /*!< ETH RX_OCTET_COUNT_GOOD: RXOCTG Mask */
\r
6880 /* ------------------------ ETH_RX_BROADCAST_FRAMES_GOOD ------------------------ */
\r
6881 #define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos 0 /*!< ETH RX_BROADCAST_FRAMES_GOOD: RXBCASTG Position */
\r
6882 #define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Msk (0xffffffffUL << ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos)/*!< ETH RX_BROADCAST_FRAMES_GOOD: RXBCASTG Mask */
\r
6884 /* ------------------------ ETH_RX_MULTICAST_FRAMES_GOOD ------------------------ */
\r
6885 #define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos 0 /*!< ETH RX_MULTICAST_FRAMES_GOOD: RXMCASTG Position */
\r
6886 #define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Msk (0xffffffffUL << ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos)/*!< ETH RX_MULTICAST_FRAMES_GOOD: RXMCASTG Mask */
\r
6888 /* --------------------------- ETH_RX_CRC_ERROR_FRAMES -------------------------- */
\r
6889 #define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos 0 /*!< ETH RX_CRC_ERROR_FRAMES: RXCRCERR Position */
\r
6890 #define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Msk (0xffffffffUL << ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos) /*!< ETH RX_CRC_ERROR_FRAMES: RXCRCERR Mask */
\r
6892 /* ------------------------ ETH_RX_ALIGNMENT_ERROR_FRAMES ----------------------- */
\r
6893 #define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos 0 /*!< ETH RX_ALIGNMENT_ERROR_FRAMES: RXALGNERR Position */
\r
6894 #define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Msk (0xffffffffUL << ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos)/*!< ETH RX_ALIGNMENT_ERROR_FRAMES: RXALGNERR Mask */
\r
6896 /* -------------------------- ETH_RX_RUNT_ERROR_FRAMES -------------------------- */
\r
6897 #define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos 0 /*!< ETH RX_RUNT_ERROR_FRAMES: RXRUNTERR Position */
\r
6898 #define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Msk (0xffffffffUL << ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos)/*!< ETH RX_RUNT_ERROR_FRAMES: RXRUNTERR Mask */
\r
6900 /* ------------------------- ETH_RX_JABBER_ERROR_FRAMES ------------------------- */
\r
6901 #define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos 0 /*!< ETH RX_JABBER_ERROR_FRAMES: RXJABERR Position */
\r
6902 #define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Msk (0xffffffffUL << ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos)/*!< ETH RX_JABBER_ERROR_FRAMES: RXJABERR Mask */
\r
6904 /* ------------------------ ETH_RX_UNDERSIZE_FRAMES_GOOD ------------------------ */
\r
6905 #define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos 0 /*!< ETH RX_UNDERSIZE_FRAMES_GOOD: RXUNDERSZG Position */
\r
6906 #define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Msk (0xffffffffUL << ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos)/*!< ETH RX_UNDERSIZE_FRAMES_GOOD: RXUNDERSZG Mask */
\r
6908 /* ------------------------- ETH_RX_OVERSIZE_FRAMES_GOOD ------------------------ */
\r
6909 #define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos 0 /*!< ETH RX_OVERSIZE_FRAMES_GOOD: RXOVERSZG Position */
\r
6910 #define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Msk (0xffffffffUL << ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos)/*!< ETH RX_OVERSIZE_FRAMES_GOOD: RXOVERSZG Mask */
\r
6912 /* ----------------------- ETH_RX_64OCTETS_FRAMES_GOOD_BAD ---------------------- */
\r
6913 #define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos 0 /*!< ETH RX_64OCTETS_FRAMES_GOOD_BAD: RX64OCTGB Position */
\r
6914 #define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Msk (0xffffffffUL << ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos)/*!< ETH RX_64OCTETS_FRAMES_GOOD_BAD: RX64OCTGB Mask */
\r
6916 /* -------------------- ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD -------------------- */
\r
6917 #define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos 0 /*!< ETH RX_65TO127OCTETS_FRAMES_GOOD_BAD: RX65_127OCTGB Position */
\r
6918 #define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Msk (0xffffffffUL << ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos)/*!< ETH RX_65TO127OCTETS_FRAMES_GOOD_BAD: RX65_127OCTGB Mask */
\r
6920 /* -------------------- ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD ------------------- */
\r
6921 #define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos 0 /*!< ETH RX_128TO255OCTETS_FRAMES_GOOD_BAD: RX128_255OCTGB Position */
\r
6922 #define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Msk (0xffffffffUL << ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos)/*!< ETH RX_128TO255OCTETS_FRAMES_GOOD_BAD: RX128_255OCTGB Mask */
\r
6924 /* -------------------- ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD ------------------- */
\r
6925 #define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos 0 /*!< ETH RX_256TO511OCTETS_FRAMES_GOOD_BAD: RX256_511OCTGB Position */
\r
6926 #define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Msk (0xffffffffUL << ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos)/*!< ETH RX_256TO511OCTETS_FRAMES_GOOD_BAD: RX256_511OCTGB Mask */
\r
6928 /* ------------------- ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD ------------------- */
\r
6929 #define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos 0 /*!< ETH RX_512TO1023OCTETS_FRAMES_GOOD_BAD: RX512_1023OCTGB Position */
\r
6930 #define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Msk (0xffffffffUL << ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos)/*!< ETH RX_512TO1023OCTETS_FRAMES_GOOD_BAD: RX512_1023OCTGB Mask */
\r
6932 /* ------------------- ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD ------------------- */
\r
6933 #define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos 0 /*!< ETH RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: RX1024_MAXOCTGB Position */
\r
6934 #define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Msk (0xffffffffUL << ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos)/*!< ETH RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: RX1024_MAXOCTGB Mask */
\r
6936 /* ------------------------- ETH_RX_UNICAST_FRAMES_GOOD ------------------------- */
\r
6937 #define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos 0 /*!< ETH RX_UNICAST_FRAMES_GOOD: RXUCASTG Position */
\r
6938 #define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Msk (0xffffffffUL << ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos)/*!< ETH RX_UNICAST_FRAMES_GOOD: RXUCASTG Mask */
\r
6940 /* ------------------------- ETH_RX_LENGTH_ERROR_FRAMES ------------------------- */
\r
6941 #define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos 0 /*!< ETH RX_LENGTH_ERROR_FRAMES: RXLENERR Position */
\r
6942 #define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Msk (0xffffffffUL << ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos)/*!< ETH RX_LENGTH_ERROR_FRAMES: RXLENERR Mask */
\r
6944 /* ----------------------- ETH_RX_OUT_OF_RANGE_TYPE_FRAMES ---------------------- */
\r
6945 #define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos 0 /*!< ETH RX_OUT_OF_RANGE_TYPE_FRAMES: RXOUTOFRNG Position */
\r
6946 #define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Msk (0xffffffffUL << ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos)/*!< ETH RX_OUT_OF_RANGE_TYPE_FRAMES: RXOUTOFRNG Mask */
\r
6948 /* ----------------------------- ETH_RX_PAUSE_FRAMES ---------------------------- */
\r
6949 #define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos 0 /*!< ETH RX_PAUSE_FRAMES: RXPAUSEFRM Position */
\r
6950 #define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Msk (0xffffffffUL << ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos) /*!< ETH RX_PAUSE_FRAMES: RXPAUSEFRM Mask */
\r
6952 /* ------------------------- ETH_RX_FIFO_OVERFLOW_FRAMES ------------------------ */
\r
6953 #define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos 0 /*!< ETH RX_FIFO_OVERFLOW_FRAMES: RXFIFOOVFL Position */
\r
6954 #define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Msk (0xffffffffUL << ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos)/*!< ETH RX_FIFO_OVERFLOW_FRAMES: RXFIFOOVFL Mask */
\r
6956 /* ------------------------- ETH_RX_VLAN_FRAMES_GOOD_BAD ------------------------ */
\r
6957 #define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos 0 /*!< ETH RX_VLAN_FRAMES_GOOD_BAD: RXVLANFRGB Position */
\r
6958 #define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Msk (0xffffffffUL << ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos)/*!< ETH RX_VLAN_FRAMES_GOOD_BAD: RXVLANFRGB Mask */
\r
6960 /* ------------------------ ETH_RX_WATCHDOG_ERROR_FRAMES ------------------------ */
\r
6961 #define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos 0 /*!< ETH RX_WATCHDOG_ERROR_FRAMES: RXWDGERR Position */
\r
6962 #define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Msk (0xffffffffUL << ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos)/*!< ETH RX_WATCHDOG_ERROR_FRAMES: RXWDGERR Mask */
\r
6964 /* ------------------------- ETH_RX_RECEIVE_ERROR_FRAMES ------------------------ */
\r
6965 #define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos 0 /*!< ETH RX_RECEIVE_ERROR_FRAMES: RXRCVERR Position */
\r
6966 #define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Msk (0xffffffffUL << ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos)/*!< ETH RX_RECEIVE_ERROR_FRAMES: RXRCVERR Mask */
\r
6968 /* ------------------------- ETH_RX_CONTROL_FRAMES_GOOD ------------------------- */
\r
6969 #define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos 0 /*!< ETH RX_CONTROL_FRAMES_GOOD: RXCTRLG Position */
\r
6970 #define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Msk (0xffffffffUL << ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos)/*!< ETH RX_CONTROL_FRAMES_GOOD: RXCTRLG Mask */
\r
6972 /* --------------------- ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK --------------------- */
\r
6973 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos 0 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GFIM Position */
\r
6974 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GFIM Mask */
\r
6975 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos 1 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HERFIM Position */
\r
6976 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HERFIM Mask */
\r
6977 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos 2 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYFIM Position */
\r
6978 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYFIM Mask */
\r
6979 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos 3 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGFIM Position */
\r
6980 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGFIM Mask */
\r
6981 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos 4 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLFIM Position */
\r
6982 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLFIM Mask */
\r
6983 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos 5 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GFIM Position */
\r
6984 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GFIM Mask */
\r
6985 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos 6 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HERFIM Position */
\r
6986 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HERFIM Mask */
\r
6987 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos 7 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYFIM Position */
\r
6988 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYFIM Mask */
\r
6989 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos 8 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGFIM Position */
\r
6990 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGFIM Mask */
\r
6991 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos 9 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPERFIM Position */
\r
6992 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPERFIM Mask */
\r
6993 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos 10 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGFIM Position */
\r
6994 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGFIM Mask */
\r
6995 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos 11 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPERFIM Position */
\r
6996 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPERFIM Mask */
\r
6997 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos 12 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGFIM Position */
\r
6998 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGFIM Mask */
\r
6999 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos 13 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPERFIM Position */
\r
7000 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPERFIM Mask */
\r
7001 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Pos 14 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: Reserved_15_14 Position */
\r
7002 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Msk (0x03UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: Reserved_15_14 Mask */
\r
7003 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos 16 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GOIM Position */
\r
7004 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GOIM Mask */
\r
7005 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos 17 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HEROIM Position */
\r
7006 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HEROIM Mask */
\r
7007 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos 18 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYOIM Position */
\r
7008 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYOIM Mask */
\r
7009 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos 19 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGOIM Position */
\r
7010 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGOIM Mask */
\r
7011 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos 20 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLOIM Position */
\r
7012 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLOIM Mask */
\r
7013 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos 21 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GOIM Position */
\r
7014 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GOIM Mask */
\r
7015 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos 22 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HEROIM Position */
\r
7016 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HEROIM Mask */
\r
7017 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos 23 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYOIM Position */
\r
7018 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYOIM Mask */
\r
7019 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos 24 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGOIM Position */
\r
7020 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGOIM Mask */
\r
7021 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos 25 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPEROIM Position */
\r
7022 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPEROIM Mask */
\r
7023 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos 26 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGOIM Position */
\r
7024 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGOIM Mask */
\r
7025 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos 27 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPEROIM Position */
\r
7026 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPEROIM Mask */
\r
7027 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos 28 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGOIM Position */
\r
7028 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGOIM Mask */
\r
7029 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos 29 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPEROIM Position */
\r
7030 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPEROIM Mask */
\r
7031 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Pos 30 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: Reserved_31_30 Position */
\r
7032 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Msk (0x03UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: Reserved_31_30 Mask */
\r
7034 /* ------------------------ ETH_MMC_IPC_RECEIVE_INTERRUPT ----------------------- */
\r
7035 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos 0 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GFIS Position */
\r
7036 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GFIS Mask */
\r
7037 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos 1 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HERFIS Position */
\r
7038 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HERFIS Mask */
\r
7039 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos 2 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYFIS Position */
\r
7040 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYFIS Mask */
\r
7041 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos 3 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGFIS Position */
\r
7042 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGFIS Mask */
\r
7043 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos 4 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLFIS Position */
\r
7044 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLFIS Mask */
\r
7045 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos 5 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GFIS Position */
\r
7046 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GFIS Mask */
\r
7047 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos 6 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HERFIS Position */
\r
7048 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HERFIS Mask */
\r
7049 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos 7 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYFIS Position */
\r
7050 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYFIS Mask */
\r
7051 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos 8 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGFIS Position */
\r
7052 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGFIS Mask */
\r
7053 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos 9 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPERFIS Position */
\r
7054 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPERFIS Mask */
\r
7055 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos 10 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGFIS Position */
\r
7056 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGFIS Mask */
\r
7057 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos 11 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPERFIS Position */
\r
7058 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPERFIS Mask */
\r
7059 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos 12 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGFIS Position */
\r
7060 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGFIS Mask */
\r
7061 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos 13 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPERFIS Position */
\r
7062 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPERFIS Mask */
\r
7063 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Pos 14 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: Reserved_15_14 Position */
\r
7064 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Msk (0x03UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: Reserved_15_14 Mask */
\r
7065 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos 16 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GOIS Position */
\r
7066 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GOIS Mask */
\r
7067 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos 17 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HEROIS Position */
\r
7068 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HEROIS Mask */
\r
7069 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos 18 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYOIS Position */
\r
7070 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYOIS Mask */
\r
7071 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos 19 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGOIS Position */
\r
7072 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGOIS Mask */
\r
7073 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos 20 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLOIS Position */
\r
7074 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLOIS Mask */
\r
7075 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos 21 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GOIS Position */
\r
7076 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GOIS Mask */
\r
7077 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos 22 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HEROIS Position */
\r
7078 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HEROIS Mask */
\r
7079 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos 23 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYOIS Position */
\r
7080 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYOIS Mask */
\r
7081 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos 24 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGOIS Position */
\r
7082 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGOIS Mask */
\r
7083 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos 25 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPEROIS Position */
\r
7084 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPEROIS Mask */
\r
7085 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos 26 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGOIS Position */
\r
7086 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGOIS Mask */
\r
7087 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos 27 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPEROIS Position */
\r
7088 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPEROIS Mask */
\r
7089 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos 28 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGOIS Position */
\r
7090 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGOIS Mask */
\r
7091 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos 29 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPEROIS Position */
\r
7092 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPEROIS Mask */
\r
7093 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Pos 30 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: Reserved_31_30 Position */
\r
7094 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Msk (0x03UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: Reserved_31_30 Mask */
\r
7096 /* --------------------------- ETH_RXIPV4_GOOD_FRAMES --------------------------- */
\r
7097 #define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos 0 /*!< ETH RXIPV4_GOOD_FRAMES: RXIPV4GDFRM Position */
\r
7098 #define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Msk (0xffffffffUL << ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos)/*!< ETH RXIPV4_GOOD_FRAMES: RXIPV4GDFRM Mask */
\r
7100 /* ----------------------- ETH_RXIPV4_HEADER_ERROR_FRAMES ----------------------- */
\r
7101 #define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos 0 /*!< ETH RXIPV4_HEADER_ERROR_FRAMES: RXIPV4HDRERRFRM Position */
\r
7102 #define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Msk (0xffffffffUL << ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos)/*!< ETH RXIPV4_HEADER_ERROR_FRAMES: RXIPV4HDRERRFRM Mask */
\r
7104 /* ------------------------ ETH_RXIPV4_NO_PAYLOAD_FRAMES ------------------------ */
\r
7105 #define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos 0 /*!< ETH RXIPV4_NO_PAYLOAD_FRAMES: RXIPV4NOPAYFRM Position */
\r
7106 #define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Msk (0xffffffffUL << ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos)/*!< ETH RXIPV4_NO_PAYLOAD_FRAMES: RXIPV4NOPAYFRM Mask */
\r
7108 /* ------------------------ ETH_RXIPV4_FRAGMENTED_FRAMES ------------------------ */
\r
7109 #define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos 0 /*!< ETH RXIPV4_FRAGMENTED_FRAMES: RXIPV4FRAGFRM Position */
\r
7110 #define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Msk (0xffffffffUL << ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos)/*!< ETH RXIPV4_FRAGMENTED_FRAMES: RXIPV4FRAGFRM Mask */
\r
7112 /* ------------------- ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES ------------------ */
\r
7113 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos 0 /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES: RXIPV4UDSBLFRM Position */
\r
7114 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Msk (0xffffffffUL << ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos)/*!< ETH RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES: RXIPV4UDSBLFRM Mask */
\r
7116 /* --------------------------- ETH_RXIPV6_GOOD_FRAMES --------------------------- */
\r
7117 #define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos 0 /*!< ETH RXIPV6_GOOD_FRAMES: RXIPV6GDFRM Position */
\r
7118 #define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Msk (0xffffffffUL << ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos)/*!< ETH RXIPV6_GOOD_FRAMES: RXIPV6GDFRM Mask */
\r
7120 /* ----------------------- ETH_RXIPV6_HEADER_ERROR_FRAMES ----------------------- */
\r
7121 #define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos 0 /*!< ETH RXIPV6_HEADER_ERROR_FRAMES: RXIPV6HDRERRFRM Position */
\r
7122 #define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Msk (0xffffffffUL << ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos)/*!< ETH RXIPV6_HEADER_ERROR_FRAMES: RXIPV6HDRERRFRM Mask */
\r
7124 /* ------------------------ ETH_RXIPV6_NO_PAYLOAD_FRAMES ------------------------ */
\r
7125 #define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos 0 /*!< ETH RXIPV6_NO_PAYLOAD_FRAMES: RXIPV6NOPAYFRM Position */
\r
7126 #define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Msk (0xffffffffUL << ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos)/*!< ETH RXIPV6_NO_PAYLOAD_FRAMES: RXIPV6NOPAYFRM Mask */
\r
7128 /* ---------------------------- ETH_RXUDP_GOOD_FRAMES --------------------------- */
\r
7129 #define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos 0 /*!< ETH RXUDP_GOOD_FRAMES: RXUDPGDFRM Position */
\r
7130 #define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Msk (0xffffffffUL << ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos) /*!< ETH RXUDP_GOOD_FRAMES: RXUDPGDFRM Mask */
\r
7132 /* --------------------------- ETH_RXUDP_ERROR_FRAMES --------------------------- */
\r
7133 #define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos 0 /*!< ETH RXUDP_ERROR_FRAMES: RXUDPERRFRM Position */
\r
7134 #define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Msk (0xffffffffUL << ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos)/*!< ETH RXUDP_ERROR_FRAMES: RXUDPERRFRM Mask */
\r
7136 /* ---------------------------- ETH_RXTCP_GOOD_FRAMES --------------------------- */
\r
7137 #define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos 0 /*!< ETH RXTCP_GOOD_FRAMES: RXTCPGDFRM Position */
\r
7138 #define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Msk (0xffffffffUL << ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos) /*!< ETH RXTCP_GOOD_FRAMES: RXTCPGDFRM Mask */
\r
7140 /* --------------------------- ETH_RXTCP_ERROR_FRAMES --------------------------- */
\r
7141 #define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos 0 /*!< ETH RXTCP_ERROR_FRAMES: RXTCPERRFRM Position */
\r
7142 #define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Msk (0xffffffffUL << ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos)/*!< ETH RXTCP_ERROR_FRAMES: RXTCPERRFRM Mask */
\r
7144 /* --------------------------- ETH_RXICMP_GOOD_FRAMES --------------------------- */
\r
7145 #define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos 0 /*!< ETH RXICMP_GOOD_FRAMES: RXICMPGDFRM Position */
\r
7146 #define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Msk (0xffffffffUL << ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos)/*!< ETH RXICMP_GOOD_FRAMES: RXICMPGDFRM Mask */
\r
7148 /* --------------------------- ETH_RXICMP_ERROR_FRAMES -------------------------- */
\r
7149 #define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos 0 /*!< ETH RXICMP_ERROR_FRAMES: RXICMPERRFRM Position */
\r
7150 #define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Msk (0xffffffffUL << ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos)/*!< ETH RXICMP_ERROR_FRAMES: RXICMPERRFRM Mask */
\r
7152 /* --------------------------- ETH_RXIPV4_GOOD_OCTETS --------------------------- */
\r
7153 #define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos 0 /*!< ETH RXIPV4_GOOD_OCTETS: RXIPV4GDOCT Position */
\r
7154 #define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Msk (0xffffffffUL << ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos)/*!< ETH RXIPV4_GOOD_OCTETS: RXIPV4GDOCT Mask */
\r
7156 /* ----------------------- ETH_RXIPV4_HEADER_ERROR_OCTETS ----------------------- */
\r
7157 #define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos 0 /*!< ETH RXIPV4_HEADER_ERROR_OCTETS: RXIPV4HDRERROCT Position */
\r
7158 #define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Msk (0xffffffffUL << ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos)/*!< ETH RXIPV4_HEADER_ERROR_OCTETS: RXIPV4HDRERROCT Mask */
\r
7160 /* ------------------------ ETH_RXIPV4_NO_PAYLOAD_OCTETS ------------------------ */
\r
7161 #define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos 0 /*!< ETH RXIPV4_NO_PAYLOAD_OCTETS: RXIPV4NOPAYOCT Position */
\r
7162 #define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Msk (0xffffffffUL << ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos)/*!< ETH RXIPV4_NO_PAYLOAD_OCTETS: RXIPV4NOPAYOCT Mask */
\r
7164 /* ------------------------ ETH_RXIPV4_FRAGMENTED_OCTETS ------------------------ */
\r
7165 #define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos 0 /*!< ETH RXIPV4_FRAGMENTED_OCTETS: RXIPV4FRAGOCT Position */
\r
7166 #define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Msk (0xffffffffUL << ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos)/*!< ETH RXIPV4_FRAGMENTED_OCTETS: RXIPV4FRAGOCT Mask */
\r
7168 /* ------------------- ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS ------------------- */
\r
7169 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos 0 /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS: RXIPV4UDSBLOCT Position */
\r
7170 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Msk (0xffffffffUL << ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos)/*!< ETH RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS: RXIPV4UDSBLOCT Mask */
\r
7172 /* --------------------------- ETH_RXIPV6_GOOD_OCTETS --------------------------- */
\r
7173 #define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos 0 /*!< ETH RXIPV6_GOOD_OCTETS: RXIPV6GDOCT Position */
\r
7174 #define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Msk (0xffffffffUL << ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos)/*!< ETH RXIPV6_GOOD_OCTETS: RXIPV6GDOCT Mask */
\r
7176 /* ----------------------- ETH_RXIPV6_HEADER_ERROR_OCTETS ----------------------- */
\r
7177 #define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos 0 /*!< ETH RXIPV6_HEADER_ERROR_OCTETS: RXIPV6HDRERROCT Position */
\r
7178 #define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Msk (0xffffffffUL << ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos)/*!< ETH RXIPV6_HEADER_ERROR_OCTETS: RXIPV6HDRERROCT Mask */
\r
7180 /* ------------------------ ETH_RXIPV6_NO_PAYLOAD_OCTETS ------------------------ */
\r
7181 #define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos 0 /*!< ETH RXIPV6_NO_PAYLOAD_OCTETS: RXIPV6NOPAYOCT Position */
\r
7182 #define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Msk (0xffffffffUL << ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos)/*!< ETH RXIPV6_NO_PAYLOAD_OCTETS: RXIPV6NOPAYOCT Mask */
\r
7184 /* ---------------------------- ETH_RXUDP_GOOD_OCTETS --------------------------- */
\r
7185 #define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos 0 /*!< ETH RXUDP_GOOD_OCTETS: RXUDPGDOCT Position */
\r
7186 #define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Msk (0xffffffffUL << ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos) /*!< ETH RXUDP_GOOD_OCTETS: RXUDPGDOCT Mask */
\r
7188 /* --------------------------- ETH_RXUDP_ERROR_OCTETS --------------------------- */
\r
7189 #define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos 0 /*!< ETH RXUDP_ERROR_OCTETS: RXUDPERROCT Position */
\r
7190 #define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Msk (0xffffffffUL << ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos)/*!< ETH RXUDP_ERROR_OCTETS: RXUDPERROCT Mask */
\r
7192 /* ---------------------------- ETH_RXTCP_GOOD_OCTETS --------------------------- */
\r
7193 #define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos 0 /*!< ETH RXTCP_GOOD_OCTETS: RXTCPGDOCT Position */
\r
7194 #define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Msk (0xffffffffUL << ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos) /*!< ETH RXTCP_GOOD_OCTETS: RXTCPGDOCT Mask */
\r
7196 /* --------------------------- ETH_RXTCP_ERROR_OCTETS --------------------------- */
\r
7197 #define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos 0 /*!< ETH RXTCP_ERROR_OCTETS: RXTCPERROCT Position */
\r
7198 #define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Msk (0xffffffffUL << ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos)/*!< ETH RXTCP_ERROR_OCTETS: RXTCPERROCT Mask */
\r
7200 /* --------------------------- ETH_RXICMP_GOOD_OCTETS --------------------------- */
\r
7201 #define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos 0 /*!< ETH RXICMP_GOOD_OCTETS: RXICMPGDOCT Position */
\r
7202 #define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Msk (0xffffffffUL << ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos)/*!< ETH RXICMP_GOOD_OCTETS: RXICMPGDOCT Mask */
\r
7204 /* --------------------------- ETH_RXICMP_ERROR_OCTETS -------------------------- */
\r
7205 #define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos 0 /*!< ETH RXICMP_ERROR_OCTETS: RXICMPERROCT Position */
\r
7206 #define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Msk (0xffffffffUL << ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos)/*!< ETH RXICMP_ERROR_OCTETS: RXICMPERROCT Mask */
\r
7208 /* ---------------------------- ETH_TIMESTAMP_CONTROL --------------------------- */
\r
7209 #define ETH_TIMESTAMP_CONTROL_TSENA_Pos 0 /*!< ETH TIMESTAMP_CONTROL: TSENA Position */
\r
7210 #define ETH_TIMESTAMP_CONTROL_TSENA_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSENA_Pos) /*!< ETH TIMESTAMP_CONTROL: TSENA Mask */
\r
7211 #define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos 1 /*!< ETH TIMESTAMP_CONTROL: TSCFUPDT Position */
\r
7212 #define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos) /*!< ETH TIMESTAMP_CONTROL: TSCFUPDT Mask */
\r
7213 #define ETH_TIMESTAMP_CONTROL_TSINIT_Pos 2 /*!< ETH TIMESTAMP_CONTROL: TSINIT Position */
\r
7214 #define ETH_TIMESTAMP_CONTROL_TSINIT_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSINIT_Pos) /*!< ETH TIMESTAMP_CONTROL: TSINIT Mask */
\r
7215 #define ETH_TIMESTAMP_CONTROL_TSUPDT_Pos 3 /*!< ETH TIMESTAMP_CONTROL: TSUPDT Position */
\r
7216 #define ETH_TIMESTAMP_CONTROL_TSUPDT_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSUPDT_Pos) /*!< ETH TIMESTAMP_CONTROL: TSUPDT Mask */
\r
7217 #define ETH_TIMESTAMP_CONTROL_TSTRIG_Pos 4 /*!< ETH TIMESTAMP_CONTROL: TSTRIG Position */
\r
7218 #define ETH_TIMESTAMP_CONTROL_TSTRIG_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSTRIG_Pos) /*!< ETH TIMESTAMP_CONTROL: TSTRIG Mask */
\r
7219 #define ETH_TIMESTAMP_CONTROL_TSADDREG_Pos 5 /*!< ETH TIMESTAMP_CONTROL: TSADDREG Position */
\r
7220 #define ETH_TIMESTAMP_CONTROL_TSADDREG_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSADDREG_Pos) /*!< ETH TIMESTAMP_CONTROL: TSADDREG Mask */
\r
7221 #define ETH_TIMESTAMP_CONTROL_Reserved_7_6_Pos 6 /*!< ETH TIMESTAMP_CONTROL: Reserved_7_6 Position */
\r
7222 #define ETH_TIMESTAMP_CONTROL_Reserved_7_6_Msk (0x03UL << ETH_TIMESTAMP_CONTROL_Reserved_7_6_Pos) /*!< ETH TIMESTAMP_CONTROL: Reserved_7_6 Mask */
\r
7223 #define ETH_TIMESTAMP_CONTROL_TSENALL_Pos 8 /*!< ETH TIMESTAMP_CONTROL: TSENALL Position */
\r
7224 #define ETH_TIMESTAMP_CONTROL_TSENALL_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSENALL_Pos) /*!< ETH TIMESTAMP_CONTROL: TSENALL Mask */
\r
7225 #define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos 9 /*!< ETH TIMESTAMP_CONTROL: TSCTRLSSR Position */
\r
7226 #define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos) /*!< ETH TIMESTAMP_CONTROL: TSCTRLSSR Mask */
\r
7227 #define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos 10 /*!< ETH TIMESTAMP_CONTROL: TSVER2ENA Position */
\r
7228 #define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos) /*!< ETH TIMESTAMP_CONTROL: TSVER2ENA Mask */
\r
7229 #define ETH_TIMESTAMP_CONTROL_TSIPENA_Pos 11 /*!< ETH TIMESTAMP_CONTROL: TSIPENA Position */
\r
7230 #define ETH_TIMESTAMP_CONTROL_TSIPENA_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSIPENA_Pos) /*!< ETH TIMESTAMP_CONTROL: TSIPENA Mask */
\r
7231 #define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos 12 /*!< ETH TIMESTAMP_CONTROL: TSIPV6ENA Position */
\r
7232 #define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos) /*!< ETH TIMESTAMP_CONTROL: TSIPV6ENA Mask */
\r
7233 #define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos 13 /*!< ETH TIMESTAMP_CONTROL: TSIPV4ENA Position */
\r
7234 #define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos) /*!< ETH TIMESTAMP_CONTROL: TSIPV4ENA Mask */
\r
7235 #define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos 14 /*!< ETH TIMESTAMP_CONTROL: TSEVNTENA Position */
\r
7236 #define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos) /*!< ETH TIMESTAMP_CONTROL: TSEVNTENA Mask */
\r
7237 #define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos 15 /*!< ETH TIMESTAMP_CONTROL: TSMSTRENA Position */
\r
7238 #define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos) /*!< ETH TIMESTAMP_CONTROL: TSMSTRENA Mask */
\r
7239 #define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos 16 /*!< ETH TIMESTAMP_CONTROL: SNAPTYPSEL Position */
\r
7240 #define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Msk (0x03UL << ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos) /*!< ETH TIMESTAMP_CONTROL: SNAPTYPSEL Mask */
\r
7241 #define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos 18 /*!< ETH TIMESTAMP_CONTROL: TSENMACADDR Position */
\r
7242 #define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos) /*!< ETH TIMESTAMP_CONTROL: TSENMACADDR Mask */
\r
7243 #define ETH_TIMESTAMP_CONTROL_Reserved_23_19_Pos 19 /*!< ETH TIMESTAMP_CONTROL: Reserved_23_19 Position */
\r
7244 #define ETH_TIMESTAMP_CONTROL_Reserved_23_19_Msk (0x00001fffUL << ETH_TIMESTAMP_CONTROL_Reserved_23_19_Pos)/*!< ETH TIMESTAMP_CONTROL: Reserved_23_19 Mask */
\r
7246 /* -------------------------- ETH_SUB_SECOND_INCREMENT -------------------------- */
\r
7247 #define ETH_SUB_SECOND_INCREMENT_SSINC_Pos 0 /*!< ETH SUB_SECOND_INCREMENT: SSINC Position */
\r
7248 #define ETH_SUB_SECOND_INCREMENT_SSINC_Msk (0x000000ffUL << ETH_SUB_SECOND_INCREMENT_SSINC_Pos) /*!< ETH SUB_SECOND_INCREMENT: SSINC Mask */
\r
7249 #define ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Pos 8 /*!< ETH SUB_SECOND_INCREMENT: Reserved_31_8 Position */
\r
7250 #define ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Msk (0x00ffffffUL << ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Pos)/*!< ETH SUB_SECOND_INCREMENT: Reserved_31_8 Mask */
\r
7252 /* --------------------------- ETH_SYSTEM_TIME_SECONDS -------------------------- */
\r
7253 #define ETH_SYSTEM_TIME_SECONDS_TSS_Pos 0 /*!< ETH SYSTEM_TIME_SECONDS: TSS Position */
\r
7254 #define ETH_SYSTEM_TIME_SECONDS_TSS_Msk (0xffffffffUL << ETH_SYSTEM_TIME_SECONDS_TSS_Pos) /*!< ETH SYSTEM_TIME_SECONDS: TSS Mask */
\r
7256 /* ------------------------- ETH_SYSTEM_TIME_NANOSECONDS ------------------------ */
\r
7257 #define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos 0 /*!< ETH SYSTEM_TIME_NANOSECONDS: TSSS Position */
\r
7258 #define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Msk (0x7fffffffUL << ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos) /*!< ETH SYSTEM_TIME_NANOSECONDS: TSSS Mask */
\r
7259 #define ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Pos 31 /*!< ETH SYSTEM_TIME_NANOSECONDS: Reserved_31 Position */
\r
7260 #define ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Msk (0x01UL << ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Pos)/*!< ETH SYSTEM_TIME_NANOSECONDS: Reserved_31 Mask */
\r
7262 /* ----------------------- ETH_SYSTEM_TIME_SECONDS_UPDATE ----------------------- */
\r
7263 #define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos 0 /*!< ETH SYSTEM_TIME_SECONDS_UPDATE: TSS Position */
\r
7264 #define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Msk (0xffffffffUL << ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos)/*!< ETH SYSTEM_TIME_SECONDS_UPDATE: TSS Mask */
\r
7266 /* --------------------- ETH_SYSTEM_TIME_NANOSECONDS_UPDATE --------------------- */
\r
7267 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos 0 /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: TSSS Position */
\r
7268 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Msk (0x7fffffffUL << ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos)/*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: TSSS Mask */
\r
7269 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos 31 /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: ADDSUB Position */
\r
7270 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Msk (0x01UL << ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos)/*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: ADDSUB Mask */
\r
7272 /* ---------------------------- ETH_TIMESTAMP_ADDEND ---------------------------- */
\r
7273 #define ETH_TIMESTAMP_ADDEND_TSAR_Pos 0 /*!< ETH TIMESTAMP_ADDEND: TSAR Position */
\r
7274 #define ETH_TIMESTAMP_ADDEND_TSAR_Msk (0xffffffffUL << ETH_TIMESTAMP_ADDEND_TSAR_Pos) /*!< ETH TIMESTAMP_ADDEND: TSAR Mask */
\r
7276 /* --------------------------- ETH_TARGET_TIME_SECONDS -------------------------- */
\r
7277 #define ETH_TARGET_TIME_SECONDS_TSTR_Pos 0 /*!< ETH TARGET_TIME_SECONDS: TSTR Position */
\r
7278 #define ETH_TARGET_TIME_SECONDS_TSTR_Msk (0xffffffffUL << ETH_TARGET_TIME_SECONDS_TSTR_Pos) /*!< ETH TARGET_TIME_SECONDS: TSTR Mask */
\r
7280 /* ------------------------- ETH_TARGET_TIME_NANOSECONDS ------------------------ */
\r
7281 #define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos 0 /*!< ETH TARGET_TIME_NANOSECONDS: TTSLO Position */
\r
7282 #define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Msk (0x7fffffffUL << ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos) /*!< ETH TARGET_TIME_NANOSECONDS: TTSLO Mask */
\r
7283 #define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos 31 /*!< ETH TARGET_TIME_NANOSECONDS: TRGTBUSY Position */
\r
7284 #define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Msk (0x01UL << ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos) /*!< ETH TARGET_TIME_NANOSECONDS: TRGTBUSY Mask */
\r
7286 /* --------------------- ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS -------------------- */
\r
7287 #define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos 0 /*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: TSHWR Position */
\r
7288 #define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Msk (0x0000ffffUL << ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos)/*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: TSHWR Mask */
\r
7289 #define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Pos 16 /*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: Reserved_31_16 Position */
\r
7290 #define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Msk (0x0000ffffUL << ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Pos)/*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: Reserved_31_16 Mask */
\r
7292 /* ---------------------------- ETH_TIMESTAMP_STATUS ---------------------------- */
\r
7293 #define ETH_TIMESTAMP_STATUS_TSSOVF_Pos 0 /*!< ETH TIMESTAMP_STATUS: TSSOVF Position */
\r
7294 #define ETH_TIMESTAMP_STATUS_TSSOVF_Msk (0x01UL << ETH_TIMESTAMP_STATUS_TSSOVF_Pos) /*!< ETH TIMESTAMP_STATUS: TSSOVF Mask */
\r
7295 #define ETH_TIMESTAMP_STATUS_TSTARGT_Pos 1 /*!< ETH TIMESTAMP_STATUS: TSTARGT Position */
\r
7296 #define ETH_TIMESTAMP_STATUS_TSTARGT_Msk (0x01UL << ETH_TIMESTAMP_STATUS_TSTARGT_Pos) /*!< ETH TIMESTAMP_STATUS: TSTARGT Mask */
\r
7297 #define ETH_TIMESTAMP_STATUS_Reserved_2_Pos 2 /*!< ETH TIMESTAMP_STATUS: Reserved_2 Position */
\r
7298 #define ETH_TIMESTAMP_STATUS_Reserved_2_Msk (0x01UL << ETH_TIMESTAMP_STATUS_Reserved_2_Pos) /*!< ETH TIMESTAMP_STATUS: Reserved_2 Mask */
\r
7299 #define ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos 3 /*!< ETH TIMESTAMP_STATUS: TSTRGTERR Position */
\r
7300 #define ETH_TIMESTAMP_STATUS_TSTRGTERR_Msk (0x01UL << ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR Mask */
\r
7301 #define ETH_TIMESTAMP_STATUS_TSTARGT1_Pos 4 /*!< ETH TIMESTAMP_STATUS: TSTARGT1 Position */
\r
7302 #define ETH_TIMESTAMP_STATUS_TSTARGT1_Msk (0x01UL << ETH_TIMESTAMP_STATUS_TSTARGT1_Pos) /*!< ETH TIMESTAMP_STATUS: TSTARGT1 Mask */
\r
7303 #define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos 5 /*!< ETH TIMESTAMP_STATUS: TSTRGTERR1 Position */
\r
7304 #define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Msk (0x01UL << ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR1 Mask */
\r
7305 #define ETH_TIMESTAMP_STATUS_TSTARGT2_Pos 6 /*!< ETH TIMESTAMP_STATUS: TSTARGT2 Position */
\r
7306 #define ETH_TIMESTAMP_STATUS_TSTARGT2_Msk (0x01UL << ETH_TIMESTAMP_STATUS_TSTARGT2_Pos) /*!< ETH TIMESTAMP_STATUS: TSTARGT2 Mask */
\r
7307 #define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos 7 /*!< ETH TIMESTAMP_STATUS: TSTRGTERR2 Position */
\r
7308 #define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Msk (0x01UL << ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR2 Mask */
\r
7309 #define ETH_TIMESTAMP_STATUS_TSTARGT3_Pos 8 /*!< ETH TIMESTAMP_STATUS: TSTARGT3 Position */
\r
7310 #define ETH_TIMESTAMP_STATUS_TSTARGT3_Msk (0x01UL << ETH_TIMESTAMP_STATUS_TSTARGT3_Pos) /*!< ETH TIMESTAMP_STATUS: TSTARGT3 Mask */
\r
7311 #define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos 9 /*!< ETH TIMESTAMP_STATUS: TSTRGTERR3 Position */
\r
7312 #define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Msk (0x01UL << ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR3 Mask */
\r
7313 #define ETH_TIMESTAMP_STATUS_Reserved_15_10_Pos 10 /*!< ETH TIMESTAMP_STATUS: Reserved_15_10 Position */
\r
7314 #define ETH_TIMESTAMP_STATUS_Reserved_15_10_Msk (0x3fUL << ETH_TIMESTAMP_STATUS_Reserved_15_10_Pos) /*!< ETH TIMESTAMP_STATUS: Reserved_15_10 Mask */
\r
7315 #define ETH_TIMESTAMP_STATUS_Reserved_19_16_Pos 16 /*!< ETH TIMESTAMP_STATUS: Reserved_19_16 Position */
\r
7316 #define ETH_TIMESTAMP_STATUS_Reserved_19_16_Msk (0x0fUL << ETH_TIMESTAMP_STATUS_Reserved_19_16_Pos) /*!< ETH TIMESTAMP_STATUS: Reserved_19_16 Mask */
\r
7317 #define ETH_TIMESTAMP_STATUS_Reserved_23_20_Pos 20 /*!< ETH TIMESTAMP_STATUS: Reserved_23_20 Position */
\r
7318 #define ETH_TIMESTAMP_STATUS_Reserved_23_20_Msk (0x0fUL << ETH_TIMESTAMP_STATUS_Reserved_23_20_Pos) /*!< ETH TIMESTAMP_STATUS: Reserved_23_20 Mask */
\r
7319 #define ETH_TIMESTAMP_STATUS_Reserved_24_Pos 24 /*!< ETH TIMESTAMP_STATUS: Reserved_24 Position */
\r
7320 #define ETH_TIMESTAMP_STATUS_Reserved_24_Msk (0x01UL << ETH_TIMESTAMP_STATUS_Reserved_24_Pos) /*!< ETH TIMESTAMP_STATUS: Reserved_24 Mask */
\r
7321 #define ETH_TIMESTAMP_STATUS_Reserved_29_25_Pos 25 /*!< ETH TIMESTAMP_STATUS: Reserved_29_25 Position */
\r
7322 #define ETH_TIMESTAMP_STATUS_Reserved_29_25_Msk (0x1fUL << ETH_TIMESTAMP_STATUS_Reserved_29_25_Pos) /*!< ETH TIMESTAMP_STATUS: Reserved_29_25 Mask */
\r
7323 #define ETH_TIMESTAMP_STATUS_Reserved_31_30_Pos 30 /*!< ETH TIMESTAMP_STATUS: Reserved_31_30 Position */
\r
7324 #define ETH_TIMESTAMP_STATUS_Reserved_31_30_Msk (0x03UL << ETH_TIMESTAMP_STATUS_Reserved_31_30_Pos) /*!< ETH TIMESTAMP_STATUS: Reserved_31_30 Mask */
\r
7326 /* ------------------------------- ETH_PPS_CONTROL ------------------------------ */
\r
7327 #define ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Pos 0 /*!< ETH PPS_CONTROL: PPSCTRL_PPSCMD Position */
\r
7328 #define ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Msk (0x0fUL << ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Pos) /*!< ETH PPS_CONTROL: PPSCTRL_PPSCMD Mask */
\r
7329 #define ETH_PPS_CONTROL_PPSEN0_Pos 4 /*!< ETH PPS_CONTROL: PPSEN0 Position */
\r
7330 #define ETH_PPS_CONTROL_PPSEN0_Msk (0x01UL << ETH_PPS_CONTROL_PPSEN0_Pos) /*!< ETH PPS_CONTROL: PPSEN0 Mask */
\r
7331 #define ETH_PPS_CONTROL_TRGTMODSEL0_Pos 5 /*!< ETH PPS_CONTROL: TRGTMODSEL0 Position */
\r
7332 #define ETH_PPS_CONTROL_TRGTMODSEL0_Msk (0x03UL << ETH_PPS_CONTROL_TRGTMODSEL0_Pos) /*!< ETH PPS_CONTROL: TRGTMODSEL0 Mask */
\r
7333 #define ETH_PPS_CONTROL_Reserved_7_Pos 7 /*!< ETH PPS_CONTROL: Reserved_7 Position */
\r
7334 #define ETH_PPS_CONTROL_Reserved_7_Msk (0x01UL << ETH_PPS_CONTROL_Reserved_7_Pos) /*!< ETH PPS_CONTROL: Reserved_7 Mask */
\r
7335 #define ETH_PPS_CONTROL_PPSCMD1_Pos 8 /*!< ETH PPS_CONTROL: PPSCMD1 Position */
\r
7336 #define ETH_PPS_CONTROL_PPSCMD1_Msk (0x07UL << ETH_PPS_CONTROL_PPSCMD1_Pos) /*!< ETH PPS_CONTROL: PPSCMD1 Mask */
\r
7337 #define ETH_PPS_CONTROL_Reserved_12_11_Pos 11 /*!< ETH PPS_CONTROL: Reserved_12_11 Position */
\r
7338 #define ETH_PPS_CONTROL_Reserved_12_11_Msk (0x03UL << ETH_PPS_CONTROL_Reserved_12_11_Pos) /*!< ETH PPS_CONTROL: Reserved_12_11 Mask */
\r
7339 #define ETH_PPS_CONTROL_TRGTMODSEL1_Pos 13 /*!< ETH PPS_CONTROL: TRGTMODSEL1 Position */
\r
7340 #define ETH_PPS_CONTROL_TRGTMODSEL1_Msk (0x03UL << ETH_PPS_CONTROL_TRGTMODSEL1_Pos) /*!< ETH PPS_CONTROL: TRGTMODSEL1 Mask */
\r
7341 #define ETH_PPS_CONTROL_Reserved_15_Pos 15 /*!< ETH PPS_CONTROL: Reserved_15 Position */
\r
7342 #define ETH_PPS_CONTROL_Reserved_15_Msk (0x01UL << ETH_PPS_CONTROL_Reserved_15_Pos) /*!< ETH PPS_CONTROL: Reserved_15 Mask */
\r
7343 #define ETH_PPS_CONTROL_PPSCMD2_Pos 16 /*!< ETH PPS_CONTROL: PPSCMD2 Position */
\r
7344 #define ETH_PPS_CONTROL_PPSCMD2_Msk (0x07UL << ETH_PPS_CONTROL_PPSCMD2_Pos) /*!< ETH PPS_CONTROL: PPSCMD2 Mask */
\r
7345 #define ETH_PPS_CONTROL_Reserved_20_19_Pos 19 /*!< ETH PPS_CONTROL: Reserved_20_19 Position */
\r
7346 #define ETH_PPS_CONTROL_Reserved_20_19_Msk (0x03UL << ETH_PPS_CONTROL_Reserved_20_19_Pos) /*!< ETH PPS_CONTROL: Reserved_20_19 Mask */
\r
7347 #define ETH_PPS_CONTROL_TRGTMODSEL2_Pos 21 /*!< ETH PPS_CONTROL: TRGTMODSEL2 Position */
\r
7348 #define ETH_PPS_CONTROL_TRGTMODSEL2_Msk (0x03UL << ETH_PPS_CONTROL_TRGTMODSEL2_Pos) /*!< ETH PPS_CONTROL: TRGTMODSEL2 Mask */
\r
7349 #define ETH_PPS_CONTROL_Reserved_23_Pos 23 /*!< ETH PPS_CONTROL: Reserved_23 Position */
\r
7350 #define ETH_PPS_CONTROL_Reserved_23_Msk (0x01UL << ETH_PPS_CONTROL_Reserved_23_Pos) /*!< ETH PPS_CONTROL: Reserved_23 Mask */
\r
7351 #define ETH_PPS_CONTROL_PPSCMD3_Pos 24 /*!< ETH PPS_CONTROL: PPSCMD3 Position */
\r
7352 #define ETH_PPS_CONTROL_PPSCMD3_Msk (0x07UL << ETH_PPS_CONTROL_PPSCMD3_Pos) /*!< ETH PPS_CONTROL: PPSCMD3 Mask */
\r
7353 #define ETH_PPS_CONTROL_Reserved_28_27_Pos 27 /*!< ETH PPS_CONTROL: Reserved_28_27 Position */
\r
7354 #define ETH_PPS_CONTROL_Reserved_28_27_Msk (0x03UL << ETH_PPS_CONTROL_Reserved_28_27_Pos) /*!< ETH PPS_CONTROL: Reserved_28_27 Mask */
\r
7355 #define ETH_PPS_CONTROL_TRGTMODSEL3_Pos 29 /*!< ETH PPS_CONTROL: TRGTMODSEL3 Position */
\r
7356 #define ETH_PPS_CONTROL_TRGTMODSEL3_Msk (0x03UL << ETH_PPS_CONTROL_TRGTMODSEL3_Pos) /*!< ETH PPS_CONTROL: TRGTMODSEL3 Mask */
\r
7357 #define ETH_PPS_CONTROL_Reserved_31_Pos 31 /*!< ETH PPS_CONTROL: Reserved_31 Position */
\r
7358 #define ETH_PPS_CONTROL_Reserved_31_Msk (0x01UL << ETH_PPS_CONTROL_Reserved_31_Pos) /*!< ETH PPS_CONTROL: Reserved_31 Mask */
\r
7360 /* -------------------------------- ETH_BUS_MODE -------------------------------- */
\r
7361 #define ETH_BUS_MODE_SWR_Pos 0 /*!< ETH BUS_MODE: SWR Position */
\r
7362 #define ETH_BUS_MODE_SWR_Msk (0x01UL << ETH_BUS_MODE_SWR_Pos) /*!< ETH BUS_MODE: SWR Mask */
\r
7363 #define ETH_BUS_MODE_DA_Pos 1 /*!< ETH BUS_MODE: DA Position */
\r
7364 #define ETH_BUS_MODE_DA_Msk (0x01UL << ETH_BUS_MODE_DA_Pos) /*!< ETH BUS_MODE: DA Mask */
\r
7365 #define ETH_BUS_MODE_DSL_Pos 2 /*!< ETH BUS_MODE: DSL Position */
\r
7366 #define ETH_BUS_MODE_DSL_Msk (0x1fUL << ETH_BUS_MODE_DSL_Pos) /*!< ETH BUS_MODE: DSL Mask */
\r
7367 #define ETH_BUS_MODE_Reserved_7_Pos 7 /*!< ETH BUS_MODE: Reserved_7 Position */
\r
7368 #define ETH_BUS_MODE_Reserved_7_Msk (0x01UL << ETH_BUS_MODE_Reserved_7_Pos) /*!< ETH BUS_MODE: Reserved_7 Mask */
\r
7369 #define ETH_BUS_MODE_PBL_Pos 8 /*!< ETH BUS_MODE: PBL Position */
\r
7370 #define ETH_BUS_MODE_PBL_Msk (0x3fUL << ETH_BUS_MODE_PBL_Pos) /*!< ETH BUS_MODE: PBL Mask */
\r
7371 #define ETH_BUS_MODE_PR_Pos 14 /*!< ETH BUS_MODE: PR Position */
\r
7372 #define ETH_BUS_MODE_PR_Msk (0x03UL << ETH_BUS_MODE_PR_Pos) /*!< ETH BUS_MODE: PR Mask */
\r
7373 #define ETH_BUS_MODE_FB_Pos 16 /*!< ETH BUS_MODE: FB Position */
\r
7374 #define ETH_BUS_MODE_FB_Msk (0x01UL << ETH_BUS_MODE_FB_Pos) /*!< ETH BUS_MODE: FB Mask */
\r
7375 #define ETH_BUS_MODE_RPBL_Pos 17 /*!< ETH BUS_MODE: RPBL Position */
\r
7376 #define ETH_BUS_MODE_RPBL_Msk (0x3fUL << ETH_BUS_MODE_RPBL_Pos) /*!< ETH BUS_MODE: RPBL Mask */
\r
7377 #define ETH_BUS_MODE_USP_Pos 23 /*!< ETH BUS_MODE: USP Position */
\r
7378 #define ETH_BUS_MODE_USP_Msk (0x01UL << ETH_BUS_MODE_USP_Pos) /*!< ETH BUS_MODE: USP Mask */
\r
7379 #define ETH_BUS_MODE_EIGHTxPBL_Pos 24 /*!< ETH BUS_MODE: EIGHTxPBL Position */
\r
7380 #define ETH_BUS_MODE_EIGHTxPBL_Msk (0x01UL << ETH_BUS_MODE_EIGHTxPBL_Pos) /*!< ETH BUS_MODE: EIGHTxPBL Mask */
\r
7381 #define ETH_BUS_MODE_AAL_Pos 25 /*!< ETH BUS_MODE: AAL Position */
\r
7382 #define ETH_BUS_MODE_AAL_Msk (0x01UL << ETH_BUS_MODE_AAL_Pos) /*!< ETH BUS_MODE: AAL Mask */
\r
7383 #define ETH_BUS_MODE_MB_Pos 26 /*!< ETH BUS_MODE: MB Position */
\r
7384 #define ETH_BUS_MODE_MB_Msk (0x01UL << ETH_BUS_MODE_MB_Pos) /*!< ETH BUS_MODE: MB Mask */
\r
7385 #define ETH_BUS_MODE_TXPR_Pos 27 /*!< ETH BUS_MODE: TXPR Position */
\r
7386 #define ETH_BUS_MODE_TXPR_Msk (0x01UL << ETH_BUS_MODE_TXPR_Pos) /*!< ETH BUS_MODE: TXPR Mask */
\r
7387 #define ETH_BUS_MODE_PRWG_Pos 28 /*!< ETH BUS_MODE: PRWG Position */
\r
7388 #define ETH_BUS_MODE_PRWG_Msk (0x03UL << ETH_BUS_MODE_PRWG_Pos) /*!< ETH BUS_MODE: PRWG Mask */
\r
7389 #define ETH_BUS_MODE_Reserved_31_30_Pos 30 /*!< ETH BUS_MODE: Reserved_31_30 Position */
\r
7390 #define ETH_BUS_MODE_Reserved_31_30_Msk (0x03UL << ETH_BUS_MODE_Reserved_31_30_Pos) /*!< ETH BUS_MODE: Reserved_31_30 Mask */
\r
7392 /* -------------------------- ETH_TRANSMIT_POLL_DEMAND -------------------------- */
\r
7393 #define ETH_TRANSMIT_POLL_DEMAND_TPD_Pos 0 /*!< ETH TRANSMIT_POLL_DEMAND: TPD Position */
\r
7394 #define ETH_TRANSMIT_POLL_DEMAND_TPD_Msk (0xffffffffUL << ETH_TRANSMIT_POLL_DEMAND_TPD_Pos) /*!< ETH TRANSMIT_POLL_DEMAND: TPD Mask */
\r
7396 /* --------------------------- ETH_RECEIVE_POLL_DEMAND -------------------------- */
\r
7397 #define ETH_RECEIVE_POLL_DEMAND_RPD_Pos 0 /*!< ETH RECEIVE_POLL_DEMAND: RPD Position */
\r
7398 #define ETH_RECEIVE_POLL_DEMAND_RPD_Msk (0xffffffffUL << ETH_RECEIVE_POLL_DEMAND_RPD_Pos) /*!< ETH RECEIVE_POLL_DEMAND: RPD Mask */
\r
7400 /* --------------------- ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS -------------------- */
\r
7401 #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos 0 /*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: Reserved_1_0 Position */
\r
7402 #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Msk (0x03UL << ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos)/*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: Reserved_1_0 Mask */
\r
7403 #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos 2 /*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: RDESLA_32bit Position */
\r
7404 #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Msk (0x3fffffffUL << ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos)/*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: RDESLA_32bit Mask */
\r
7406 /* -------------------- ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS -------------------- */
\r
7407 #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos 0 /*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: Reserved_1_0 Position */
\r
7408 #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Msk (0x03UL << ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos)/*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: Reserved_1_0 Mask */
\r
7409 #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos 2 /*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: TDESLA_32bit Position */
\r
7410 #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Msk (0x3fffffffUL << ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos)/*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: TDESLA_32bit Mask */
\r
7412 /* --------------------------------- ETH_STATUS --------------------------------- */
\r
7413 #define ETH_STATUS_TI_Pos 0 /*!< ETH STATUS: TI Position */
\r
7414 #define ETH_STATUS_TI_Msk (0x01UL << ETH_STATUS_TI_Pos) /*!< ETH STATUS: TI Mask */
\r
7415 #define ETH_STATUS_TPS_Pos 1 /*!< ETH STATUS: TPS Position */
\r
7416 #define ETH_STATUS_TPS_Msk (0x01UL << ETH_STATUS_TPS_Pos) /*!< ETH STATUS: TPS Mask */
\r
7417 #define ETH_STATUS_TU_Pos 2 /*!< ETH STATUS: TU Position */
\r
7418 #define ETH_STATUS_TU_Msk (0x01UL << ETH_STATUS_TU_Pos) /*!< ETH STATUS: TU Mask */
\r
7419 #define ETH_STATUS_TJT_Pos 3 /*!< ETH STATUS: TJT Position */
\r
7420 #define ETH_STATUS_TJT_Msk (0x01UL << ETH_STATUS_TJT_Pos) /*!< ETH STATUS: TJT Mask */
\r
7421 #define ETH_STATUS_OVF_Pos 4 /*!< ETH STATUS: OVF Position */
\r
7422 #define ETH_STATUS_OVF_Msk (0x01UL << ETH_STATUS_OVF_Pos) /*!< ETH STATUS: OVF Mask */
\r
7423 #define ETH_STATUS_UNF_Pos 5 /*!< ETH STATUS: UNF Position */
\r
7424 #define ETH_STATUS_UNF_Msk (0x01UL << ETH_STATUS_UNF_Pos) /*!< ETH STATUS: UNF Mask */
\r
7425 #define ETH_STATUS_RI_Pos 6 /*!< ETH STATUS: RI Position */
\r
7426 #define ETH_STATUS_RI_Msk (0x01UL << ETH_STATUS_RI_Pos) /*!< ETH STATUS: RI Mask */
\r
7427 #define ETH_STATUS_RU_Pos 7 /*!< ETH STATUS: RU Position */
\r
7428 #define ETH_STATUS_RU_Msk (0x01UL << ETH_STATUS_RU_Pos) /*!< ETH STATUS: RU Mask */
\r
7429 #define ETH_STATUS_RPS_Pos 8 /*!< ETH STATUS: RPS Position */
\r
7430 #define ETH_STATUS_RPS_Msk (0x01UL << ETH_STATUS_RPS_Pos) /*!< ETH STATUS: RPS Mask */
\r
7431 #define ETH_STATUS_RWT_Pos 9 /*!< ETH STATUS: RWT Position */
\r
7432 #define ETH_STATUS_RWT_Msk (0x01UL << ETH_STATUS_RWT_Pos) /*!< ETH STATUS: RWT Mask */
\r
7433 #define ETH_STATUS_ETI_Pos 10 /*!< ETH STATUS: ETI Position */
\r
7434 #define ETH_STATUS_ETI_Msk (0x01UL << ETH_STATUS_ETI_Pos) /*!< ETH STATUS: ETI Mask */
\r
7435 #define ETH_STATUS_Reserved_12_11_Pos 11 /*!< ETH STATUS: Reserved_12_11 Position */
\r
7436 #define ETH_STATUS_Reserved_12_11_Msk (0x03UL << ETH_STATUS_Reserved_12_11_Pos) /*!< ETH STATUS: Reserved_12_11 Mask */
\r
7437 #define ETH_STATUS_FBI_Pos 13 /*!< ETH STATUS: FBI Position */
\r
7438 #define ETH_STATUS_FBI_Msk (0x01UL << ETH_STATUS_FBI_Pos) /*!< ETH STATUS: FBI Mask */
\r
7439 #define ETH_STATUS_ERI_Pos 14 /*!< ETH STATUS: ERI Position */
\r
7440 #define ETH_STATUS_ERI_Msk (0x01UL << ETH_STATUS_ERI_Pos) /*!< ETH STATUS: ERI Mask */
\r
7441 #define ETH_STATUS_AIS_Pos 15 /*!< ETH STATUS: AIS Position */
\r
7442 #define ETH_STATUS_AIS_Msk (0x01UL << ETH_STATUS_AIS_Pos) /*!< ETH STATUS: AIS Mask */
\r
7443 #define ETH_STATUS_NIS_Pos 16 /*!< ETH STATUS: NIS Position */
\r
7444 #define ETH_STATUS_NIS_Msk (0x01UL << ETH_STATUS_NIS_Pos) /*!< ETH STATUS: NIS Mask */
\r
7445 #define ETH_STATUS_RS_Pos 17 /*!< ETH STATUS: RS Position */
\r
7446 #define ETH_STATUS_RS_Msk (0x07UL << ETH_STATUS_RS_Pos) /*!< ETH STATUS: RS Mask */
\r
7447 #define ETH_STATUS_TS_Pos 20 /*!< ETH STATUS: TS Position */
\r
7448 #define ETH_STATUS_TS_Msk (0x07UL << ETH_STATUS_TS_Pos) /*!< ETH STATUS: TS Mask */
\r
7449 #define ETH_STATUS_EB_Pos 23 /*!< ETH STATUS: EB Position */
\r
7450 #define ETH_STATUS_EB_Msk (0x07UL << ETH_STATUS_EB_Pos) /*!< ETH STATUS: EB Mask */
\r
7451 #define ETH_STATUS_Reserved_26_Pos 26 /*!< ETH STATUS: Reserved_26 Position */
\r
7452 #define ETH_STATUS_Reserved_26_Msk (0x01UL << ETH_STATUS_Reserved_26_Pos) /*!< ETH STATUS: Reserved_26 Mask */
\r
7453 #define ETH_STATUS_EMI_Pos 27 /*!< ETH STATUS: EMI Position */
\r
7454 #define ETH_STATUS_EMI_Msk (0x01UL << ETH_STATUS_EMI_Pos) /*!< ETH STATUS: EMI Mask */
\r
7455 #define ETH_STATUS_EPI_Pos 28 /*!< ETH STATUS: EPI Position */
\r
7456 #define ETH_STATUS_EPI_Msk (0x01UL << ETH_STATUS_EPI_Pos) /*!< ETH STATUS: EPI Mask */
\r
7457 #define ETH_STATUS_TTI_Pos 29 /*!< ETH STATUS: TTI Position */
\r
7458 #define ETH_STATUS_TTI_Msk (0x01UL << ETH_STATUS_TTI_Pos) /*!< ETH STATUS: TTI Mask */
\r
7459 #define ETH_STATUS_Reserved_30_Pos 30 /*!< ETH STATUS: Reserved_30 Position */
\r
7460 #define ETH_STATUS_Reserved_30_Msk (0x01UL << ETH_STATUS_Reserved_30_Pos) /*!< ETH STATUS: Reserved_30 Mask */
\r
7461 #define ETH_STATUS_Reserved_31_Pos 31 /*!< ETH STATUS: Reserved_31 Position */
\r
7462 #define ETH_STATUS_Reserved_31_Msk (0x01UL << ETH_STATUS_Reserved_31_Pos) /*!< ETH STATUS: Reserved_31 Mask */
\r
7464 /* ----------------------------- ETH_OPERATION_MODE ----------------------------- */
\r
7465 #define ETH_OPERATION_MODE_Reserved_0_Pos 0 /*!< ETH OPERATION_MODE: Reserved_0 Position */
\r
7466 #define ETH_OPERATION_MODE_Reserved_0_Msk (0x01UL << ETH_OPERATION_MODE_Reserved_0_Pos) /*!< ETH OPERATION_MODE: Reserved_0 Mask */
\r
7467 #define ETH_OPERATION_MODE_SR_Pos 1 /*!< ETH OPERATION_MODE: SR Position */
\r
7468 #define ETH_OPERATION_MODE_SR_Msk (0x01UL << ETH_OPERATION_MODE_SR_Pos) /*!< ETH OPERATION_MODE: SR Mask */
\r
7469 #define ETH_OPERATION_MODE_OSF_Pos 2 /*!< ETH OPERATION_MODE: OSF Position */
\r
7470 #define ETH_OPERATION_MODE_OSF_Msk (0x01UL << ETH_OPERATION_MODE_OSF_Pos) /*!< ETH OPERATION_MODE: OSF Mask */
\r
7471 #define ETH_OPERATION_MODE_RTC_Pos 3 /*!< ETH OPERATION_MODE: RTC Position */
\r
7472 #define ETH_OPERATION_MODE_RTC_Msk (0x03UL << ETH_OPERATION_MODE_RTC_Pos) /*!< ETH OPERATION_MODE: RTC Mask */
\r
7473 #define ETH_OPERATION_MODE_Reserved_5_Pos 5 /*!< ETH OPERATION_MODE: Reserved_5 Position */
\r
7474 #define ETH_OPERATION_MODE_Reserved_5_Msk (0x01UL << ETH_OPERATION_MODE_Reserved_5_Pos) /*!< ETH OPERATION_MODE: Reserved_5 Mask */
\r
7475 #define ETH_OPERATION_MODE_FUF_Pos 6 /*!< ETH OPERATION_MODE: FUF Position */
\r
7476 #define ETH_OPERATION_MODE_FUF_Msk (0x01UL << ETH_OPERATION_MODE_FUF_Pos) /*!< ETH OPERATION_MODE: FUF Mask */
\r
7477 #define ETH_OPERATION_MODE_FEF_Pos 7 /*!< ETH OPERATION_MODE: FEF Position */
\r
7478 #define ETH_OPERATION_MODE_FEF_Msk (0x01UL << ETH_OPERATION_MODE_FEF_Pos) /*!< ETH OPERATION_MODE: FEF Mask */
\r
7479 #define ETH_OPERATION_MODE_Reserved_12_8_Pos 8 /*!< ETH OPERATION_MODE: Reserved_12_8 Position */
\r
7480 #define ETH_OPERATION_MODE_Reserved_12_8_Msk (0x1fUL << ETH_OPERATION_MODE_Reserved_12_8_Pos) /*!< ETH OPERATION_MODE: Reserved_12_8 Mask */
\r
7481 #define ETH_OPERATION_MODE_ST_Pos 13 /*!< ETH OPERATION_MODE: ST Position */
\r
7482 #define ETH_OPERATION_MODE_ST_Msk (0x01UL << ETH_OPERATION_MODE_ST_Pos) /*!< ETH OPERATION_MODE: ST Mask */
\r
7483 #define ETH_OPERATION_MODE_TTC_Pos 14 /*!< ETH OPERATION_MODE: TTC Position */
\r
7484 #define ETH_OPERATION_MODE_TTC_Msk (0x07UL << ETH_OPERATION_MODE_TTC_Pos) /*!< ETH OPERATION_MODE: TTC Mask */
\r
7485 #define ETH_OPERATION_MODE_Reserved_19_17_Pos 17 /*!< ETH OPERATION_MODE: Reserved_19_17 Position */
\r
7486 #define ETH_OPERATION_MODE_Reserved_19_17_Msk (0x07UL << ETH_OPERATION_MODE_Reserved_19_17_Pos) /*!< ETH OPERATION_MODE: Reserved_19_17 Mask */
\r
7487 #define ETH_OPERATION_MODE_FTF_Pos 20 /*!< ETH OPERATION_MODE: FTF Position */
\r
7488 #define ETH_OPERATION_MODE_FTF_Msk (0x01UL << ETH_OPERATION_MODE_FTF_Pos) /*!< ETH OPERATION_MODE: FTF Mask */
\r
7489 #define ETH_OPERATION_MODE_TSF_Pos 21 /*!< ETH OPERATION_MODE: TSF Position */
\r
7490 #define ETH_OPERATION_MODE_TSF_Msk (0x01UL << ETH_OPERATION_MODE_TSF_Pos) /*!< ETH OPERATION_MODE: TSF Mask */
\r
7491 #define ETH_OPERATION_MODE_Reserved_23_22_Pos 22 /*!< ETH OPERATION_MODE: Reserved_23_22 Position */
\r
7492 #define ETH_OPERATION_MODE_Reserved_23_22_Msk (0x03UL << ETH_OPERATION_MODE_Reserved_23_22_Pos) /*!< ETH OPERATION_MODE: Reserved_23_22 Mask */
\r
7493 #define ETH_OPERATION_MODE_DFF_Pos 24 /*!< ETH OPERATION_MODE: DFF Position */
\r
7494 #define ETH_OPERATION_MODE_DFF_Msk (0x01UL << ETH_OPERATION_MODE_DFF_Pos) /*!< ETH OPERATION_MODE: DFF Mask */
\r
7495 #define ETH_OPERATION_MODE_RSF_Pos 25 /*!< ETH OPERATION_MODE: RSF Position */
\r
7496 #define ETH_OPERATION_MODE_RSF_Msk (0x01UL << ETH_OPERATION_MODE_RSF_Pos) /*!< ETH OPERATION_MODE: RSF Mask */
\r
7497 #define ETH_OPERATION_MODE_DT_Pos 26 /*!< ETH OPERATION_MODE: DT Position */
\r
7498 #define ETH_OPERATION_MODE_DT_Msk (0x01UL << ETH_OPERATION_MODE_DT_Pos) /*!< ETH OPERATION_MODE: DT Mask */
\r
7499 #define ETH_OPERATION_MODE_Reserved_31_27_Pos 27 /*!< ETH OPERATION_MODE: Reserved_31_27 Position */
\r
7500 #define ETH_OPERATION_MODE_Reserved_31_27_Msk (0x1fUL << ETH_OPERATION_MODE_Reserved_31_27_Pos) /*!< ETH OPERATION_MODE: Reserved_31_27 Mask */
\r
7502 /* ---------------------------- ETH_INTERRUPT_ENABLE ---------------------------- */
\r
7503 #define ETH_INTERRUPT_ENABLE_TIE_Pos 0 /*!< ETH INTERRUPT_ENABLE: TIE Position */
\r
7504 #define ETH_INTERRUPT_ENABLE_TIE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_TIE_Pos) /*!< ETH INTERRUPT_ENABLE: TIE Mask */
\r
7505 #define ETH_INTERRUPT_ENABLE_TSE_Pos 1 /*!< ETH INTERRUPT_ENABLE: TSE Position */
\r
7506 #define ETH_INTERRUPT_ENABLE_TSE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_TSE_Pos) /*!< ETH INTERRUPT_ENABLE: TSE Mask */
\r
7507 #define ETH_INTERRUPT_ENABLE_TUE_Pos 2 /*!< ETH INTERRUPT_ENABLE: TUE Position */
\r
7508 #define ETH_INTERRUPT_ENABLE_TUE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_TUE_Pos) /*!< ETH INTERRUPT_ENABLE: TUE Mask */
\r
7509 #define ETH_INTERRUPT_ENABLE_TJE_Pos 3 /*!< ETH INTERRUPT_ENABLE: TJE Position */
\r
7510 #define ETH_INTERRUPT_ENABLE_TJE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_TJE_Pos) /*!< ETH INTERRUPT_ENABLE: TJE Mask */
\r
7511 #define ETH_INTERRUPT_ENABLE_OVE_Pos 4 /*!< ETH INTERRUPT_ENABLE: OVE Position */
\r
7512 #define ETH_INTERRUPT_ENABLE_OVE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_OVE_Pos) /*!< ETH INTERRUPT_ENABLE: OVE Mask */
\r
7513 #define ETH_INTERRUPT_ENABLE_UNE_Pos 5 /*!< ETH INTERRUPT_ENABLE: UNE Position */
\r
7514 #define ETH_INTERRUPT_ENABLE_UNE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_UNE_Pos) /*!< ETH INTERRUPT_ENABLE: UNE Mask */
\r
7515 #define ETH_INTERRUPT_ENABLE_RIE_Pos 6 /*!< ETH INTERRUPT_ENABLE: RIE Position */
\r
7516 #define ETH_INTERRUPT_ENABLE_RIE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_RIE_Pos) /*!< ETH INTERRUPT_ENABLE: RIE Mask */
\r
7517 #define ETH_INTERRUPT_ENABLE_RUE_Pos 7 /*!< ETH INTERRUPT_ENABLE: RUE Position */
\r
7518 #define ETH_INTERRUPT_ENABLE_RUE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_RUE_Pos) /*!< ETH INTERRUPT_ENABLE: RUE Mask */
\r
7519 #define ETH_INTERRUPT_ENABLE_RSE_Pos 8 /*!< ETH INTERRUPT_ENABLE: RSE Position */
\r
7520 #define ETH_INTERRUPT_ENABLE_RSE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_RSE_Pos) /*!< ETH INTERRUPT_ENABLE: RSE Mask */
\r
7521 #define ETH_INTERRUPT_ENABLE_RWE_Pos 9 /*!< ETH INTERRUPT_ENABLE: RWE Position */
\r
7522 #define ETH_INTERRUPT_ENABLE_RWE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_RWE_Pos) /*!< ETH INTERRUPT_ENABLE: RWE Mask */
\r
7523 #define ETH_INTERRUPT_ENABLE_ETE_Pos 10 /*!< ETH INTERRUPT_ENABLE: ETE Position */
\r
7524 #define ETH_INTERRUPT_ENABLE_ETE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_ETE_Pos) /*!< ETH INTERRUPT_ENABLE: ETE Mask */
\r
7525 #define ETH_INTERRUPT_ENABLE_Reserved_12_11_Pos 11 /*!< ETH INTERRUPT_ENABLE: Reserved_12_11 Position */
\r
7526 #define ETH_INTERRUPT_ENABLE_Reserved_12_11_Msk (0x03UL << ETH_INTERRUPT_ENABLE_Reserved_12_11_Pos) /*!< ETH INTERRUPT_ENABLE: Reserved_12_11 Mask */
\r
7527 #define ETH_INTERRUPT_ENABLE_FBE_Pos 13 /*!< ETH INTERRUPT_ENABLE: FBE Position */
\r
7528 #define ETH_INTERRUPT_ENABLE_FBE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_FBE_Pos) /*!< ETH INTERRUPT_ENABLE: FBE Mask */
\r
7529 #define ETH_INTERRUPT_ENABLE_ERE_Pos 14 /*!< ETH INTERRUPT_ENABLE: ERE Position */
\r
7530 #define ETH_INTERRUPT_ENABLE_ERE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_ERE_Pos) /*!< ETH INTERRUPT_ENABLE: ERE Mask */
\r
7531 #define ETH_INTERRUPT_ENABLE_AIE_Pos 15 /*!< ETH INTERRUPT_ENABLE: AIE Position */
\r
7532 #define ETH_INTERRUPT_ENABLE_AIE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_AIE_Pos) /*!< ETH INTERRUPT_ENABLE: AIE Mask */
\r
7533 #define ETH_INTERRUPT_ENABLE_NIE_Pos 16 /*!< ETH INTERRUPT_ENABLE: NIE Position */
\r
7534 #define ETH_INTERRUPT_ENABLE_NIE_Msk (0x01UL << ETH_INTERRUPT_ENABLE_NIE_Pos) /*!< ETH INTERRUPT_ENABLE: NIE Mask */
\r
7535 #define ETH_INTERRUPT_ENABLE_Reserved_31_17_Pos 17 /*!< ETH INTERRUPT_ENABLE: Reserved_31_17 Position */
\r
7536 #define ETH_INTERRUPT_ENABLE_Reserved_31_17_Msk (0x00007fffUL << ETH_INTERRUPT_ENABLE_Reserved_31_17_Pos)/*!< ETH INTERRUPT_ENABLE: Reserved_31_17 Mask */
\r
7538 /* ---------------- ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER ---------------- */
\r
7539 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos 0 /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISFRMCNT Position */
\r
7540 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Msk (0x0000ffffUL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISFRMCNT Mask */
\r
7541 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos 16 /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISCNTOVF Position */
\r
7542 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Msk (0x01UL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISCNTOVF Mask */
\r
7543 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos 17 /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFFRMCNT Position */
\r
7544 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Msk (0x000007ffUL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFFRMCNT Mask */
\r
7545 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos 28 /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFCNTOVF Position */
\r
7546 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Msk (0x01UL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFCNTOVF Mask */
\r
7547 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Pos 29 /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: Reserved_31_29
\r
7549 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Msk (0x07UL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: Reserved_31_29
\r
7552 /* -------------------- ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER -------------------- */
\r
7553 #define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos 0 /*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: RIWT Position */
\r
7554 #define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Msk (0x000000ffUL << ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos)/*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: RIWT Mask */
\r
7555 #define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Pos 8 /*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: Reserved_31_8 Position */
\r
7556 #define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Msk (0x00ffffffUL << ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Pos)/*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: Reserved_31_8 Mask */
\r
7558 /* ------------------------------- ETH_AHB_STATUS ------------------------------- */
\r
7559 #define ETH_AHB_STATUS_AHBMS_Pos 0 /*!< ETH AHB_STATUS: AHBMS Position */
\r
7560 #define ETH_AHB_STATUS_AHBMS_Msk (0x01UL << ETH_AHB_STATUS_AHBMS_Pos) /*!< ETH AHB_STATUS: AHBMS Mask */
\r
7561 #define ETH_AHB_STATUS_Reserved_1_Pos 1 /*!< ETH AHB_STATUS: Reserved_1 Position */
\r
7562 #define ETH_AHB_STATUS_Reserved_1_Msk (0x01UL << ETH_AHB_STATUS_Reserved_1_Pos) /*!< ETH AHB_STATUS: Reserved_1 Mask */
\r
7563 #define ETH_AHB_STATUS_Reserved_31_2_Pos 2 /*!< ETH AHB_STATUS: Reserved_31_2 Position */
\r
7564 #define ETH_AHB_STATUS_Reserved_31_2_Msk (0x3fffffffUL << ETH_AHB_STATUS_Reserved_31_2_Pos) /*!< ETH AHB_STATUS: Reserved_31_2 Mask */
\r
7566 /* -------------------- ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR -------------------- */
\r
7567 #define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos 0 /*!< ETH CURRENT_HOST_TRANSMIT_DESCRIPTOR: CURTDESAPTR Position */
\r
7568 #define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Msk (0xffffffffUL << ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos)/*!< ETH CURRENT_HOST_TRANSMIT_DESCRIPTOR: CURTDESAPTR Mask */
\r
7570 /* --------------------- ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR -------------------- */
\r
7571 #define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos 0 /*!< ETH CURRENT_HOST_RECEIVE_DESCRIPTOR: CURRDESAPTR Position */
\r
7572 #define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Msk (0xffffffffUL << ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos)/*!< ETH CURRENT_HOST_RECEIVE_DESCRIPTOR: CURRDESAPTR Mask */
\r
7574 /* ------------------ ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS ------------------ */
\r
7575 #define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos 0 /*!< ETH CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS: CURTBUFAPTR Position */
\r
7576 #define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Msk (0xffffffffUL << ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos)/*!< ETH CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS: CURTBUFAPTR Mask */
\r
7578 /* ------------------- ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS ------------------ */
\r
7579 #define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos 0 /*!< ETH CURRENT_HOST_RECEIVE_BUFFER_ADDRESS: CURRBUFAPTR Position */
\r
7580 #define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Msk (0xffffffffUL << ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos)/*!< ETH CURRENT_HOST_RECEIVE_BUFFER_ADDRESS: CURRBUFAPTR Mask */
\r
7582 /* ------------------------------- ETH_HW_FEATURE ------------------------------- */
\r
7583 #define ETH_HW_FEATURE_MIISEL_Pos 0 /*!< ETH HW_FEATURE: MIISEL Position */
\r
7584 #define ETH_HW_FEATURE_MIISEL_Msk (0x01UL << ETH_HW_FEATURE_MIISEL_Pos) /*!< ETH HW_FEATURE: MIISEL Mask */
\r
7585 #define ETH_HW_FEATURE_GMIISEL_Pos 1 /*!< ETH HW_FEATURE: GMIISEL Position */
\r
7586 #define ETH_HW_FEATURE_GMIISEL_Msk (0x01UL << ETH_HW_FEATURE_GMIISEL_Pos) /*!< ETH HW_FEATURE: GMIISEL Mask */
\r
7587 #define ETH_HW_FEATURE_HDSEL_Pos 2 /*!< ETH HW_FEATURE: HDSEL Position */
\r
7588 #define ETH_HW_FEATURE_HDSEL_Msk (0x01UL << ETH_HW_FEATURE_HDSEL_Pos) /*!< ETH HW_FEATURE: HDSEL Mask */
\r
7589 #define ETH_HW_FEATURE_EXTHASHEN_Pos 3 /*!< ETH HW_FEATURE: EXTHASHEN Position */
\r
7590 #define ETH_HW_FEATURE_EXTHASHEN_Msk (0x01UL << ETH_HW_FEATURE_EXTHASHEN_Pos) /*!< ETH HW_FEATURE: EXTHASHEN Mask */
\r
7591 #define ETH_HW_FEATURE_HASHSEL_Pos 4 /*!< ETH HW_FEATURE: HASHSEL Position */
\r
7592 #define ETH_HW_FEATURE_HASHSEL_Msk (0x01UL << ETH_HW_FEATURE_HASHSEL_Pos) /*!< ETH HW_FEATURE: HASHSEL Mask */
\r
7593 #define ETH_HW_FEATURE_ADDMACADRSEL_Pos 5 /*!< ETH HW_FEATURE: ADDMACADRSEL Position */
\r
7594 #define ETH_HW_FEATURE_ADDMACADRSEL_Msk (0x01UL << ETH_HW_FEATURE_ADDMACADRSEL_Pos) /*!< ETH HW_FEATURE: ADDMACADRSEL Mask */
\r
7595 #define ETH_HW_FEATURE_PCSSEL_Pos 6 /*!< ETH HW_FEATURE: PCSSEL Position */
\r
7596 #define ETH_HW_FEATURE_PCSSEL_Msk (0x01UL << ETH_HW_FEATURE_PCSSEL_Pos) /*!< ETH HW_FEATURE: PCSSEL Mask */
\r
7597 #define ETH_HW_FEATURE_L3L4FLTREN_Pos 7 /*!< ETH HW_FEATURE: L3L4FLTREN Position */
\r
7598 #define ETH_HW_FEATURE_L3L4FLTREN_Msk (0x01UL << ETH_HW_FEATURE_L3L4FLTREN_Pos) /*!< ETH HW_FEATURE: L3L4FLTREN Mask */
\r
7599 #define ETH_HW_FEATURE_SMASEL_Pos 8 /*!< ETH HW_FEATURE: SMASEL Position */
\r
7600 #define ETH_HW_FEATURE_SMASEL_Msk (0x01UL << ETH_HW_FEATURE_SMASEL_Pos) /*!< ETH HW_FEATURE: SMASEL Mask */
\r
7601 #define ETH_HW_FEATURE_RWKSEL_Pos 9 /*!< ETH HW_FEATURE: RWKSEL Position */
\r
7602 #define ETH_HW_FEATURE_RWKSEL_Msk (0x01UL << ETH_HW_FEATURE_RWKSEL_Pos) /*!< ETH HW_FEATURE: RWKSEL Mask */
\r
7603 #define ETH_HW_FEATURE_MGKSEL_Pos 10 /*!< ETH HW_FEATURE: MGKSEL Position */
\r
7604 #define ETH_HW_FEATURE_MGKSEL_Msk (0x01UL << ETH_HW_FEATURE_MGKSEL_Pos) /*!< ETH HW_FEATURE: MGKSEL Mask */
\r
7605 #define ETH_HW_FEATURE_MMCSEL_Pos 11 /*!< ETH HW_FEATURE: MMCSEL Position */
\r
7606 #define ETH_HW_FEATURE_MMCSEL_Msk (0x01UL << ETH_HW_FEATURE_MMCSEL_Pos) /*!< ETH HW_FEATURE: MMCSEL Mask */
\r
7607 #define ETH_HW_FEATURE_TSVER1SEL_Pos 12 /*!< ETH HW_FEATURE: TSVER1SEL Position */
\r
7608 #define ETH_HW_FEATURE_TSVER1SEL_Msk (0x01UL << ETH_HW_FEATURE_TSVER1SEL_Pos) /*!< ETH HW_FEATURE: TSVER1SEL Mask */
\r
7609 #define ETH_HW_FEATURE_TSVER2SEL_Pos 13 /*!< ETH HW_FEATURE: TSVER2SEL Position */
\r
7610 #define ETH_HW_FEATURE_TSVER2SEL_Msk (0x01UL << ETH_HW_FEATURE_TSVER2SEL_Pos) /*!< ETH HW_FEATURE: TSVER2SEL Mask */
\r
7611 #define ETH_HW_FEATURE_EEESEL_Pos 14 /*!< ETH HW_FEATURE: EEESEL Position */
\r
7612 #define ETH_HW_FEATURE_EEESEL_Msk (0x01UL << ETH_HW_FEATURE_EEESEL_Pos) /*!< ETH HW_FEATURE: EEESEL Mask */
\r
7613 #define ETH_HW_FEATURE_AVSEL_Pos 15 /*!< ETH HW_FEATURE: AVSEL Position */
\r
7614 #define ETH_HW_FEATURE_AVSEL_Msk (0x01UL << ETH_HW_FEATURE_AVSEL_Pos) /*!< ETH HW_FEATURE: AVSEL Mask */
\r
7615 #define ETH_HW_FEATURE_TXCOESEL_Pos 16 /*!< ETH HW_FEATURE: TXCOESEL Position */
\r
7616 #define ETH_HW_FEATURE_TXCOESEL_Msk (0x01UL << ETH_HW_FEATURE_TXCOESEL_Pos) /*!< ETH HW_FEATURE: TXCOESEL Mask */
\r
7617 #define ETH_HW_FEATURE_RXTYP1COE_Pos 17 /*!< ETH HW_FEATURE: RXTYP1COE Position */
\r
7618 #define ETH_HW_FEATURE_RXTYP1COE_Msk (0x01UL << ETH_HW_FEATURE_RXTYP1COE_Pos) /*!< ETH HW_FEATURE: RXTYP1COE Mask */
\r
7619 #define ETH_HW_FEATURE_RXTYP2COE_Pos 18 /*!< ETH HW_FEATURE: RXTYP2COE Position */
\r
7620 #define ETH_HW_FEATURE_RXTYP2COE_Msk (0x01UL << ETH_HW_FEATURE_RXTYP2COE_Pos) /*!< ETH HW_FEATURE: RXTYP2COE Mask */
\r
7621 #define ETH_HW_FEATURE_RXFIFOSIZE_Pos 19 /*!< ETH HW_FEATURE: RXFIFOSIZE Position */
\r
7622 #define ETH_HW_FEATURE_RXFIFOSIZE_Msk (0x01UL << ETH_HW_FEATURE_RXFIFOSIZE_Pos) /*!< ETH HW_FEATURE: RXFIFOSIZE Mask */
\r
7623 #define ETH_HW_FEATURE_RXCHCNT_Pos 20 /*!< ETH HW_FEATURE: RXCHCNT Position */
\r
7624 #define ETH_HW_FEATURE_RXCHCNT_Msk (0x03UL << ETH_HW_FEATURE_RXCHCNT_Pos) /*!< ETH HW_FEATURE: RXCHCNT Mask */
\r
7625 #define ETH_HW_FEATURE_TXCHCNT_Pos 22 /*!< ETH HW_FEATURE: TXCHCNT Position */
\r
7626 #define ETH_HW_FEATURE_TXCHCNT_Msk (0x03UL << ETH_HW_FEATURE_TXCHCNT_Pos) /*!< ETH HW_FEATURE: TXCHCNT Mask */
\r
7627 #define ETH_HW_FEATURE_ENHDESSEL_Pos 24 /*!< ETH HW_FEATURE: ENHDESSEL Position */
\r
7628 #define ETH_HW_FEATURE_ENHDESSEL_Msk (0x01UL << ETH_HW_FEATURE_ENHDESSEL_Pos) /*!< ETH HW_FEATURE: ENHDESSEL Mask */
\r
7629 #define ETH_HW_FEATURE_INTTSEN_Pos 25 /*!< ETH HW_FEATURE: INTTSEN Position */
\r
7630 #define ETH_HW_FEATURE_INTTSEN_Msk (0x01UL << ETH_HW_FEATURE_INTTSEN_Pos) /*!< ETH HW_FEATURE: INTTSEN Mask */
\r
7631 #define ETH_HW_FEATURE_FLEXIPPSEN_Pos 26 /*!< ETH HW_FEATURE: FLEXIPPSEN Position */
\r
7632 #define ETH_HW_FEATURE_FLEXIPPSEN_Msk (0x01UL << ETH_HW_FEATURE_FLEXIPPSEN_Pos) /*!< ETH HW_FEATURE: FLEXIPPSEN Mask */
\r
7633 #define ETH_HW_FEATURE_SAVLANINS_Pos 27 /*!< ETH HW_FEATURE: SAVLANINS Position */
\r
7634 #define ETH_HW_FEATURE_SAVLANINS_Msk (0x01UL << ETH_HW_FEATURE_SAVLANINS_Pos) /*!< ETH HW_FEATURE: SAVLANINS Mask */
\r
7635 #define ETH_HW_FEATURE_ACTPHYIF_Pos 28 /*!< ETH HW_FEATURE: ACTPHYIF Position */
\r
7636 #define ETH_HW_FEATURE_ACTPHYIF_Msk (0x07UL << ETH_HW_FEATURE_ACTPHYIF_Pos) /*!< ETH HW_FEATURE: ACTPHYIF Mask */
\r
7637 #define ETH_HW_FEATURE_Reserved_31_Pos 31 /*!< ETH HW_FEATURE: Reserved_31 Position */
\r
7638 #define ETH_HW_FEATURE_Reserved_31_Msk (0x01UL << ETH_HW_FEATURE_Reserved_31_Pos) /*!< ETH HW_FEATURE: Reserved_31 Mask */
\r
7641 /* ================================================================================ */
\r
7642 /* ================ Group 'USB' Position & Mask ================ */
\r
7643 /* ================================================================================ */
\r
7646 /* --------------------------------- USB_GOTGCTL -------------------------------- */
\r
7647 #define USB_GOTGCTL_SesReqScs_Pos 0 /*!< USB GOTGCTL: SesReqScs Position */
\r
7648 #define USB_GOTGCTL_SesReqScs_Msk (0x01UL << USB_GOTGCTL_SesReqScs_Pos) /*!< USB GOTGCTL: SesReqScs Mask */
\r
7649 #define USB_GOTGCTL_SesReq_Pos 1 /*!< USB GOTGCTL: SesReq Position */
\r
7650 #define USB_GOTGCTL_SesReq_Msk (0x01UL << USB_GOTGCTL_SesReq_Pos) /*!< USB GOTGCTL: SesReq Mask */
\r
7651 #define USB_GOTGCTL_VbvalidOvEn_Pos 2 /*!< USB GOTGCTL: VbvalidOvEn Position */
\r
7652 #define USB_GOTGCTL_VbvalidOvEn_Msk (0x01UL << USB_GOTGCTL_VbvalidOvEn_Pos) /*!< USB GOTGCTL: VbvalidOvEn Mask */
\r
7653 #define USB_GOTGCTL_VbvalidOvVal_Pos 3 /*!< USB GOTGCTL: VbvalidOvVal Position */
\r
7654 #define USB_GOTGCTL_VbvalidOvVal_Msk (0x01UL << USB_GOTGCTL_VbvalidOvVal_Pos) /*!< USB GOTGCTL: VbvalidOvVal Mask */
\r
7655 #define USB_GOTGCTL_AvalidOvEn_Pos 4 /*!< USB GOTGCTL: AvalidOvEn Position */
\r
7656 #define USB_GOTGCTL_AvalidOvEn_Msk (0x01UL << USB_GOTGCTL_AvalidOvEn_Pos) /*!< USB GOTGCTL: AvalidOvEn Mask */
\r
7657 #define USB_GOTGCTL_AvalidOvVal_Pos 5 /*!< USB GOTGCTL: AvalidOvVal Position */
\r
7658 #define USB_GOTGCTL_AvalidOvVal_Msk (0x01UL << USB_GOTGCTL_AvalidOvVal_Pos) /*!< USB GOTGCTL: AvalidOvVal Mask */
\r
7659 #define USB_GOTGCTL_BvalidOvEn_Pos 6 /*!< USB GOTGCTL: BvalidOvEn Position */
\r
7660 #define USB_GOTGCTL_BvalidOvEn_Msk (0x01UL << USB_GOTGCTL_BvalidOvEn_Pos) /*!< USB GOTGCTL: BvalidOvEn Mask */
\r
7661 #define USB_GOTGCTL_BvalidOvVal_Pos 7 /*!< USB GOTGCTL: BvalidOvVal Position */
\r
7662 #define USB_GOTGCTL_BvalidOvVal_Msk (0x01UL << USB_GOTGCTL_BvalidOvVal_Pos) /*!< USB GOTGCTL: BvalidOvVal Mask */
\r
7663 #define USB_GOTGCTL_HstNegScs_Pos 8 /*!< USB GOTGCTL: HstNegScs Position */
\r
7664 #define USB_GOTGCTL_HstNegScs_Msk (0x01UL << USB_GOTGCTL_HstNegScs_Pos) /*!< USB GOTGCTL: HstNegScs Mask */
\r
7665 #define USB_GOTGCTL_HNPReq_Pos 9 /*!< USB GOTGCTL: HNPReq Position */
\r
7666 #define USB_GOTGCTL_HNPReq_Msk (0x01UL << USB_GOTGCTL_HNPReq_Pos) /*!< USB GOTGCTL: HNPReq Mask */
\r
7667 #define USB_GOTGCTL_HstSetHNPEn_Pos 10 /*!< USB GOTGCTL: HstSetHNPEn Position */
\r
7668 #define USB_GOTGCTL_HstSetHNPEn_Msk (0x01UL << USB_GOTGCTL_HstSetHNPEn_Pos) /*!< USB GOTGCTL: HstSetHNPEn Mask */
\r
7669 #define USB_GOTGCTL_DevHNPEn_Pos 11 /*!< USB GOTGCTL: DevHNPEn Position */
\r
7670 #define USB_GOTGCTL_DevHNPEn_Msk (0x01UL << USB_GOTGCTL_DevHNPEn_Pos) /*!< USB GOTGCTL: DevHNPEn Mask */
\r
7671 #define USB_GOTGCTL_ConlDSts_Pos 16 /*!< USB GOTGCTL: ConlDSts Position */
\r
7672 #define USB_GOTGCTL_ConlDSts_Msk (0x01UL << USB_GOTGCTL_ConlDSts_Pos) /*!< USB GOTGCTL: ConlDSts Mask */
\r
7673 #define USB_GOTGCTL_DbncTime_Pos 17 /*!< USB GOTGCTL: DbncTime Position */
\r
7674 #define USB_GOTGCTL_DbncTime_Msk (0x01UL << USB_GOTGCTL_DbncTime_Pos) /*!< USB GOTGCTL: DbncTime Mask */
\r
7675 #define USB_GOTGCTL_ASesVId_Pos 18 /*!< USB GOTGCTL: ASesVId Position */
\r
7676 #define USB_GOTGCTL_ASesVId_Msk (0x01UL << USB_GOTGCTL_ASesVId_Pos) /*!< USB GOTGCTL: ASesVId Mask */
\r
7677 #define USB_GOTGCTL_BSesVld_Pos 19 /*!< USB GOTGCTL: BSesVld Position */
\r
7678 #define USB_GOTGCTL_BSesVld_Msk (0x01UL << USB_GOTGCTL_BSesVld_Pos) /*!< USB GOTGCTL: BSesVld Mask */
\r
7679 #define USB_GOTGCTL_OTGVer_Pos 20 /*!< USB GOTGCTL: OTGVer Position */
\r
7680 #define USB_GOTGCTL_OTGVer_Msk (0x01UL << USB_GOTGCTL_OTGVer_Pos) /*!< USB GOTGCTL: OTGVer Mask */
\r
7682 /* --------------------------------- USB_GOTGINT -------------------------------- */
\r
7683 #define USB_GOTGINT_SesEndDet_Pos 2 /*!< USB GOTGINT: SesEndDet Position */
\r
7684 #define USB_GOTGINT_SesEndDet_Msk (0x01UL << USB_GOTGINT_SesEndDet_Pos) /*!< USB GOTGINT: SesEndDet Mask */
\r
7685 #define USB_GOTGINT_SesReqSucStsChng_Pos 8 /*!< USB GOTGINT: SesReqSucStsChng Position */
\r
7686 #define USB_GOTGINT_SesReqSucStsChng_Msk (0x01UL << USB_GOTGINT_SesReqSucStsChng_Pos) /*!< USB GOTGINT: SesReqSucStsChng Mask */
\r
7687 #define USB_GOTGINT_HstNegSucStsChng_Pos 9 /*!< USB GOTGINT: HstNegSucStsChng Position */
\r
7688 #define USB_GOTGINT_HstNegSucStsChng_Msk (0x01UL << USB_GOTGINT_HstNegSucStsChng_Pos) /*!< USB GOTGINT: HstNegSucStsChng Mask */
\r
7689 #define USB_GOTGINT_HstNegDet_Pos 17 /*!< USB GOTGINT: HstNegDet Position */
\r
7690 #define USB_GOTGINT_HstNegDet_Msk (0x01UL << USB_GOTGINT_HstNegDet_Pos) /*!< USB GOTGINT: HstNegDet Mask */
\r
7691 #define USB_GOTGINT_ADevTOUTChg_Pos 18 /*!< USB GOTGINT: ADevTOUTChg Position */
\r
7692 #define USB_GOTGINT_ADevTOUTChg_Msk (0x01UL << USB_GOTGINT_ADevTOUTChg_Pos) /*!< USB GOTGINT: ADevTOUTChg Mask */
\r
7693 #define USB_GOTGINT_DbnceDone_Pos 19 /*!< USB GOTGINT: DbnceDone Position */
\r
7694 #define USB_GOTGINT_DbnceDone_Msk (0x01UL << USB_GOTGINT_DbnceDone_Pos) /*!< USB GOTGINT: DbnceDone Mask */
\r
7696 /* --------------------------------- USB_GAHBCFG -------------------------------- */
\r
7697 #define USB_GAHBCFG_GlblIntrMsk_Pos 0 /*!< USB GAHBCFG: GlblIntrMsk Position */
\r
7698 #define USB_GAHBCFG_GlblIntrMsk_Msk (0x01UL << USB_GAHBCFG_GlblIntrMsk_Pos) /*!< USB GAHBCFG: GlblIntrMsk Mask */
\r
7699 #define USB_GAHBCFG_HBstLen_Pos 1 /*!< USB GAHBCFG: HBstLen Position */
\r
7700 #define USB_GAHBCFG_HBstLen_Msk (0x0fUL << USB_GAHBCFG_HBstLen_Pos) /*!< USB GAHBCFG: HBstLen Mask */
\r
7701 #define USB_GAHBCFG_DMAEn_Pos 5 /*!< USB GAHBCFG: DMAEn Position */
\r
7702 #define USB_GAHBCFG_DMAEn_Msk (0x01UL << USB_GAHBCFG_DMAEn_Pos) /*!< USB GAHBCFG: DMAEn Mask */
\r
7703 #define USB_GAHBCFG_NPTxFEmpLvl_Pos 7 /*!< USB GAHBCFG: NPTxFEmpLvl Position */
\r
7704 #define USB_GAHBCFG_NPTxFEmpLvl_Msk (0x01UL << USB_GAHBCFG_NPTxFEmpLvl_Pos) /*!< USB GAHBCFG: NPTxFEmpLvl Mask */
\r
7705 #define USB_GAHBCFG_PTxFEmpLvl_Pos 8 /*!< USB GAHBCFG: PTxFEmpLvl Position */
\r
7706 #define USB_GAHBCFG_PTxFEmpLvl_Msk (0x01UL << USB_GAHBCFG_PTxFEmpLvl_Pos) /*!< USB GAHBCFG: PTxFEmpLvl Mask */
\r
7707 #define USB_GAHBCFG_AHBSingle_Pos 23 /*!< USB GAHBCFG: AHBSingle Position */
\r
7708 #define USB_GAHBCFG_AHBSingle_Msk (0x01UL << USB_GAHBCFG_AHBSingle_Pos) /*!< USB GAHBCFG: AHBSingle Mask */
\r
7710 /* --------------------------------- USB_GUSBCFG -------------------------------- */
\r
7711 #define USB_GUSBCFG_TOutCal_Pos 0 /*!< USB GUSBCFG: TOutCal Position */
\r
7712 #define USB_GUSBCFG_TOutCal_Msk (0x07UL << USB_GUSBCFG_TOutCal_Pos) /*!< USB GUSBCFG: TOutCal Mask */
\r
7713 #define USB_GUSBCFG_PHYSel_Pos 6 /*!< USB GUSBCFG: PHYSel Position */
\r
7714 #define USB_GUSBCFG_PHYSel_Msk (0x01UL << USB_GUSBCFG_PHYSel_Pos) /*!< USB GUSBCFG: PHYSel Mask */
\r
7715 #define USB_GUSBCFG_SRPCap_Pos 8 /*!< USB GUSBCFG: SRPCap Position */
\r
7716 #define USB_GUSBCFG_SRPCap_Msk (0x01UL << USB_GUSBCFG_SRPCap_Pos) /*!< USB GUSBCFG: SRPCap Mask */
\r
7717 #define USB_GUSBCFG_HNPCap_Pos 9 /*!< USB GUSBCFG: HNPCap Position */
\r
7718 #define USB_GUSBCFG_HNPCap_Msk (0x01UL << USB_GUSBCFG_HNPCap_Pos) /*!< USB GUSBCFG: HNPCap Mask */
\r
7719 #define USB_GUSBCFG_USBTrdTim_Pos 10 /*!< USB GUSBCFG: USBTrdTim Position */
\r
7720 #define USB_GUSBCFG_USBTrdTim_Msk (0x0fUL << USB_GUSBCFG_USBTrdTim_Pos) /*!< USB GUSBCFG: USBTrdTim Mask */
\r
7721 #define USB_GUSBCFG_OtgI2CSel_Pos 16 /*!< USB GUSBCFG: OtgI2CSel Position */
\r
7722 #define USB_GUSBCFG_OtgI2CSel_Msk (0x01UL << USB_GUSBCFG_OtgI2CSel_Pos) /*!< USB GUSBCFG: OtgI2CSel Mask */
\r
7723 #define USB_GUSBCFG_TxEndDelay_Pos 28 /*!< USB GUSBCFG: TxEndDelay Position */
\r
7724 #define USB_GUSBCFG_TxEndDelay_Msk (0x01UL << USB_GUSBCFG_TxEndDelay_Pos) /*!< USB GUSBCFG: TxEndDelay Mask */
\r
7725 #define USB_GUSBCFG_ForceHstMode_Pos 29 /*!< USB GUSBCFG: ForceHstMode Position */
\r
7726 #define USB_GUSBCFG_ForceHstMode_Msk (0x01UL << USB_GUSBCFG_ForceHstMode_Pos) /*!< USB GUSBCFG: ForceHstMode Mask */
\r
7727 #define USB_GUSBCFG_ForceDevMode_Pos 30 /*!< USB GUSBCFG: ForceDevMode Position */
\r
7728 #define USB_GUSBCFG_ForceDevMode_Msk (0x01UL << USB_GUSBCFG_ForceDevMode_Pos) /*!< USB GUSBCFG: ForceDevMode Mask */
\r
7729 #define USB_GUSBCFG_CTP_Pos 31 /*!< USB GUSBCFG: CTP Position */
\r
7730 #define USB_GUSBCFG_CTP_Msk (0x01UL << USB_GUSBCFG_CTP_Pos) /*!< USB GUSBCFG: CTP Mask */
\r
7732 /* --------------------------------- USB_GRSTCTL -------------------------------- */
\r
7733 #define USB_GRSTCTL_CSftRst_Pos 0 /*!< USB GRSTCTL: CSftRst Position */
\r
7734 #define USB_GRSTCTL_CSftRst_Msk (0x01UL << USB_GRSTCTL_CSftRst_Pos) /*!< USB GRSTCTL: CSftRst Mask */
\r
7735 #define USB_GRSTCTL_FrmCntrRst_Pos 2 /*!< USB GRSTCTL: FrmCntrRst Position */
\r
7736 #define USB_GRSTCTL_FrmCntrRst_Msk (0x01UL << USB_GRSTCTL_FrmCntrRst_Pos) /*!< USB GRSTCTL: FrmCntrRst Mask */
\r
7737 #define USB_GRSTCTL_RxFFlsh_Pos 4 /*!< USB GRSTCTL: RxFFlsh Position */
\r
7738 #define USB_GRSTCTL_RxFFlsh_Msk (0x01UL << USB_GRSTCTL_RxFFlsh_Pos) /*!< USB GRSTCTL: RxFFlsh Mask */
\r
7739 #define USB_GRSTCTL_TxFFlsh_Pos 5 /*!< USB GRSTCTL: TxFFlsh Position */
\r
7740 #define USB_GRSTCTL_TxFFlsh_Msk (0x01UL << USB_GRSTCTL_TxFFlsh_Pos) /*!< USB GRSTCTL: TxFFlsh Mask */
\r
7741 #define USB_GRSTCTL_TxFNum_Pos 6 /*!< USB GRSTCTL: TxFNum Position */
\r
7742 #define USB_GRSTCTL_TxFNum_Msk (0x1fUL << USB_GRSTCTL_TxFNum_Pos) /*!< USB GRSTCTL: TxFNum Mask */
\r
7743 #define USB_GRSTCTL_DMAReq_Pos 30 /*!< USB GRSTCTL: DMAReq Position */
\r
7744 #define USB_GRSTCTL_DMAReq_Msk (0x01UL << USB_GRSTCTL_DMAReq_Pos) /*!< USB GRSTCTL: DMAReq Mask */
\r
7745 #define USB_GRSTCTL_AHBIdle_Pos 31 /*!< USB GRSTCTL: AHBIdle Position */
\r
7746 #define USB_GRSTCTL_AHBIdle_Msk (0x01UL << USB_GRSTCTL_AHBIdle_Pos) /*!< USB GRSTCTL: AHBIdle Mask */
\r
7748 /* ---------------------------- USB_GINTSTS_HOSTMODE ---------------------------- */
\r
7749 #define USB_GINTSTS_HOSTMODE_CurMod_Pos 0 /*!< USB GINTSTS_HOSTMODE: CurMod Position */
\r
7750 #define USB_GINTSTS_HOSTMODE_CurMod_Msk (0x01UL << USB_GINTSTS_HOSTMODE_CurMod_Pos) /*!< USB GINTSTS_HOSTMODE: CurMod Mask */
\r
7751 #define USB_GINTSTS_HOSTMODE_ModeMis_Pos 1 /*!< USB GINTSTS_HOSTMODE: ModeMis Position */
\r
7752 #define USB_GINTSTS_HOSTMODE_ModeMis_Msk (0x01UL << USB_GINTSTS_HOSTMODE_ModeMis_Pos) /*!< USB GINTSTS_HOSTMODE: ModeMis Mask */
\r
7753 #define USB_GINTSTS_HOSTMODE_OTGInt_Pos 2 /*!< USB GINTSTS_HOSTMODE: OTGInt Position */
\r
7754 #define USB_GINTSTS_HOSTMODE_OTGInt_Msk (0x01UL << USB_GINTSTS_HOSTMODE_OTGInt_Pos) /*!< USB GINTSTS_HOSTMODE: OTGInt Mask */
\r
7755 #define USB_GINTSTS_HOSTMODE_Sof_Pos 3 /*!< USB GINTSTS_HOSTMODE: Sof Position */
\r
7756 #define USB_GINTSTS_HOSTMODE_Sof_Msk (0x01UL << USB_GINTSTS_HOSTMODE_Sof_Pos) /*!< USB GINTSTS_HOSTMODE: Sof Mask */
\r
7757 #define USB_GINTSTS_HOSTMODE_RxFLvl_Pos 4 /*!< USB GINTSTS_HOSTMODE: RxFLvl Position */
\r
7758 #define USB_GINTSTS_HOSTMODE_RxFLvl_Msk (0x01UL << USB_GINTSTS_HOSTMODE_RxFLvl_Pos) /*!< USB GINTSTS_HOSTMODE: RxFLvl Mask */
\r
7759 #define USB_GINTSTS_HOSTMODE_incomplP_Pos 21 /*!< USB GINTSTS_HOSTMODE: incomplP Position */
\r
7760 #define USB_GINTSTS_HOSTMODE_incomplP_Msk (0x01UL << USB_GINTSTS_HOSTMODE_incomplP_Pos) /*!< USB GINTSTS_HOSTMODE: incomplP Mask */
\r
7761 #define USB_GINTSTS_HOSTMODE_PrtInt_Pos 24 /*!< USB GINTSTS_HOSTMODE: PrtInt Position */
\r
7762 #define USB_GINTSTS_HOSTMODE_PrtInt_Msk (0x01UL << USB_GINTSTS_HOSTMODE_PrtInt_Pos) /*!< USB GINTSTS_HOSTMODE: PrtInt Mask */
\r
7763 #define USB_GINTSTS_HOSTMODE_HChInt_Pos 25 /*!< USB GINTSTS_HOSTMODE: HChInt Position */
\r
7764 #define USB_GINTSTS_HOSTMODE_HChInt_Msk (0x01UL << USB_GINTSTS_HOSTMODE_HChInt_Pos) /*!< USB GINTSTS_HOSTMODE: HChInt Mask */
\r
7765 #define USB_GINTSTS_HOSTMODE_PTxFEmp_Pos 26 /*!< USB GINTSTS_HOSTMODE: PTxFEmp Position */
\r
7766 #define USB_GINTSTS_HOSTMODE_PTxFEmp_Msk (0x01UL << USB_GINTSTS_HOSTMODE_PTxFEmp_Pos) /*!< USB GINTSTS_HOSTMODE: PTxFEmp Mask */
\r
7767 #define USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos 28 /*!< USB GINTSTS_HOSTMODE: ConIDStsChng Position */
\r
7768 #define USB_GINTSTS_HOSTMODE_ConIDStsChng_Msk (0x01UL << USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos) /*!< USB GINTSTS_HOSTMODE: ConIDStsChng Mask */
\r
7769 #define USB_GINTSTS_HOSTMODE_DisconnInt_Pos 29 /*!< USB GINTSTS_HOSTMODE: DisconnInt Position */
\r
7770 #define USB_GINTSTS_HOSTMODE_DisconnInt_Msk (0x01UL << USB_GINTSTS_HOSTMODE_DisconnInt_Pos) /*!< USB GINTSTS_HOSTMODE: DisconnInt Mask */
\r
7771 #define USB_GINTSTS_HOSTMODE_SessReqInt_Pos 30 /*!< USB GINTSTS_HOSTMODE: SessReqInt Position */
\r
7772 #define USB_GINTSTS_HOSTMODE_SessReqInt_Msk (0x01UL << USB_GINTSTS_HOSTMODE_SessReqInt_Pos) /*!< USB GINTSTS_HOSTMODE: SessReqInt Mask */
\r
7773 #define USB_GINTSTS_HOSTMODE_WkUpInt_Pos 31 /*!< USB GINTSTS_HOSTMODE: WkUpInt Position */
\r
7774 #define USB_GINTSTS_HOSTMODE_WkUpInt_Msk (0x01UL << USB_GINTSTS_HOSTMODE_WkUpInt_Pos) /*!< USB GINTSTS_HOSTMODE: WkUpInt Mask */
\r
7776 /* --------------------------- USB_GINTSTS_DEVICEMODE --------------------------- */
\r
7777 #define USB_GINTSTS_DEVICEMODE_CurMod_Pos 0 /*!< USB GINTSTS_DEVICEMODE: CurMod Position */
\r
7778 #define USB_GINTSTS_DEVICEMODE_CurMod_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_CurMod_Pos) /*!< USB GINTSTS_DEVICEMODE: CurMod Mask */
\r
7779 #define USB_GINTSTS_DEVICEMODE_ModeMis_Pos 1 /*!< USB GINTSTS_DEVICEMODE: ModeMis Position */
\r
7780 #define USB_GINTSTS_DEVICEMODE_ModeMis_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_ModeMis_Pos) /*!< USB GINTSTS_DEVICEMODE: ModeMis Mask */
\r
7781 #define USB_GINTSTS_DEVICEMODE_OTGInt_Pos 2 /*!< USB GINTSTS_DEVICEMODE: OTGInt Position */
\r
7782 #define USB_GINTSTS_DEVICEMODE_OTGInt_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_OTGInt_Pos) /*!< USB GINTSTS_DEVICEMODE: OTGInt Mask */
\r
7783 #define USB_GINTSTS_DEVICEMODE_Sof_Pos 3 /*!< USB GINTSTS_DEVICEMODE: Sof Position */
\r
7784 #define USB_GINTSTS_DEVICEMODE_Sof_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_Sof_Pos) /*!< USB GINTSTS_DEVICEMODE: Sof Mask */
\r
7785 #define USB_GINTSTS_DEVICEMODE_RxFLvl_Pos 4 /*!< USB GINTSTS_DEVICEMODE: RxFLvl Position */
\r
7786 #define USB_GINTSTS_DEVICEMODE_RxFLvl_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_RxFLvl_Pos) /*!< USB GINTSTS_DEVICEMODE: RxFLvl Mask */
\r
7787 #define USB_GINTSTS_DEVICEMODE_GINNakEff_Pos 6 /*!< USB GINTSTS_DEVICEMODE: GINNakEff Position */
\r
7788 #define USB_GINTSTS_DEVICEMODE_GINNakEff_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_GINNakEff_Pos) /*!< USB GINTSTS_DEVICEMODE: GINNakEff Mask */
\r
7789 #define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos 7 /*!< USB GINTSTS_DEVICEMODE: GOUTNakEff Position */
\r
7790 #define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos) /*!< USB GINTSTS_DEVICEMODE: GOUTNakEff Mask */
\r
7791 #define USB_GINTSTS_DEVICEMODE_ErlySusp_Pos 10 /*!< USB GINTSTS_DEVICEMODE: ErlySusp Position */
\r
7792 #define USB_GINTSTS_DEVICEMODE_ErlySusp_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_ErlySusp_Pos) /*!< USB GINTSTS_DEVICEMODE: ErlySusp Mask */
\r
7793 #define USB_GINTSTS_DEVICEMODE_USBSusp_Pos 11 /*!< USB GINTSTS_DEVICEMODE: USBSusp Position */
\r
7794 #define USB_GINTSTS_DEVICEMODE_USBSusp_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_USBSusp_Pos) /*!< USB GINTSTS_DEVICEMODE: USBSusp Mask */
\r
7795 #define USB_GINTSTS_DEVICEMODE_USBRst_Pos 12 /*!< USB GINTSTS_DEVICEMODE: USBRst Position */
\r
7796 #define USB_GINTSTS_DEVICEMODE_USBRst_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_USBRst_Pos) /*!< USB GINTSTS_DEVICEMODE: USBRst Mask */
\r
7797 #define USB_GINTSTS_DEVICEMODE_EnumDone_Pos 13 /*!< USB GINTSTS_DEVICEMODE: EnumDone Position */
\r
7798 #define USB_GINTSTS_DEVICEMODE_EnumDone_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_EnumDone_Pos) /*!< USB GINTSTS_DEVICEMODE: EnumDone Mask */
\r
7799 #define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos 14 /*!< USB GINTSTS_DEVICEMODE: ISOOutDrop Position */
\r
7800 #define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos) /*!< USB GINTSTS_DEVICEMODE: ISOOutDrop Mask */
\r
7801 #define USB_GINTSTS_DEVICEMODE_EOPF_Pos 15 /*!< USB GINTSTS_DEVICEMODE: EOPF Position */
\r
7802 #define USB_GINTSTS_DEVICEMODE_EOPF_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_EOPF_Pos) /*!< USB GINTSTS_DEVICEMODE: EOPF Mask */
\r
7803 #define USB_GINTSTS_DEVICEMODE_IEPInt_Pos 18 /*!< USB GINTSTS_DEVICEMODE: IEPInt Position */
\r
7804 #define USB_GINTSTS_DEVICEMODE_IEPInt_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_IEPInt_Pos) /*!< USB GINTSTS_DEVICEMODE: IEPInt Mask */
\r
7805 #define USB_GINTSTS_DEVICEMODE_OEPInt_Pos 19 /*!< USB GINTSTS_DEVICEMODE: OEPInt Position */
\r
7806 #define USB_GINTSTS_DEVICEMODE_OEPInt_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_OEPInt_Pos) /*!< USB GINTSTS_DEVICEMODE: OEPInt Mask */
\r
7807 #define USB_GINTSTS_DEVICEMODE_incompISOIN_Pos 20 /*!< USB GINTSTS_DEVICEMODE: incompISOIN Position */
\r
7808 #define USB_GINTSTS_DEVICEMODE_incompISOIN_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_incompISOIN_Pos) /*!< USB GINTSTS_DEVICEMODE: incompISOIN Mask */
\r
7809 #define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos 21 /*!< USB GINTSTS_DEVICEMODE: incomplSOOUT Position */
\r
7810 #define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos) /*!< USB GINTSTS_DEVICEMODE: incomplSOOUT Mask */
\r
7811 #define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos 28 /*!< USB GINTSTS_DEVICEMODE: ConIDStsChng Position */
\r
7812 #define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos) /*!< USB GINTSTS_DEVICEMODE: ConIDStsChng Mask */
\r
7813 #define USB_GINTSTS_DEVICEMODE_SessReqInt_Pos 30 /*!< USB GINTSTS_DEVICEMODE: SessReqInt Position */
\r
7814 #define USB_GINTSTS_DEVICEMODE_SessReqInt_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_SessReqInt_Pos) /*!< USB GINTSTS_DEVICEMODE: SessReqInt Mask */
\r
7815 #define USB_GINTSTS_DEVICEMODE_WkUpInt_Pos 31 /*!< USB GINTSTS_DEVICEMODE: WkUpInt Position */
\r
7816 #define USB_GINTSTS_DEVICEMODE_WkUpInt_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_WkUpInt_Pos) /*!< USB GINTSTS_DEVICEMODE: WkUpInt Mask */
\r
7818 /* ---------------------------- USB_GINTMSK_HOSTMODE ---------------------------- */
\r
7819 #define USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos 1 /*!< USB GINTMSK_HOSTMODE: ModeMisMsk Position */
\r
7820 #define USB_GINTMSK_HOSTMODE_ModeMisMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos) /*!< USB GINTMSK_HOSTMODE: ModeMisMsk Mask */
\r
7821 #define USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos 2 /*!< USB GINTMSK_HOSTMODE: OTGIntMsk Position */
\r
7822 #define USB_GINTMSK_HOSTMODE_OTGIntMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos) /*!< USB GINTMSK_HOSTMODE: OTGIntMsk Mask */
\r
7823 #define USB_GINTMSK_HOSTMODE_SofMsk_Pos 3 /*!< USB GINTMSK_HOSTMODE: SofMsk Position */
\r
7824 #define USB_GINTMSK_HOSTMODE_SofMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_SofMsk_Pos) /*!< USB GINTMSK_HOSTMODE: SofMsk Mask */
\r
7825 #define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos 4 /*!< USB GINTMSK_HOSTMODE: RxFLvlMsk Position */
\r
7826 #define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos) /*!< USB GINTMSK_HOSTMODE: RxFLvlMsk Mask */
\r
7827 #define USB_GINTMSK_HOSTMODE_incomplPMsk_Pos 21 /*!< USB GINTMSK_HOSTMODE: incomplPMsk Position */
\r
7828 #define USB_GINTMSK_HOSTMODE_incomplPMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_incomplPMsk_Pos) /*!< USB GINTMSK_HOSTMODE: incomplPMsk Mask */
\r
7829 #define USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos 24 /*!< USB GINTMSK_HOSTMODE: PrtIntMsk Position */
\r
7830 #define USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos) /*!< USB GINTMSK_HOSTMODE: PrtIntMsk Mask */
\r
7831 #define USB_GINTMSK_HOSTMODE_HChIntMsk_Pos 25 /*!< USB GINTMSK_HOSTMODE: HChIntMsk Position */
\r
7832 #define USB_GINTMSK_HOSTMODE_HChIntMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_HChIntMsk_Pos) /*!< USB GINTMSK_HOSTMODE: HChIntMsk Mask */
\r
7833 #define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos 26 /*!< USB GINTMSK_HOSTMODE: PTxFEmpMsk Position */
\r
7834 #define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos) /*!< USB GINTMSK_HOSTMODE: PTxFEmpMsk Mask */
\r
7835 #define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos 28 /*!< USB GINTMSK_HOSTMODE: ConIDStsChngMsk Position */
\r
7836 #define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos) /*!< USB GINTMSK_HOSTMODE: ConIDStsChngMsk Mask */
\r
7837 #define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos 29 /*!< USB GINTMSK_HOSTMODE: DisconnIntMsk Position */
\r
7838 #define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos) /*!< USB GINTMSK_HOSTMODE: DisconnIntMsk Mask */
\r
7839 #define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos 30 /*!< USB GINTMSK_HOSTMODE: SessReqIntMsk Position */
\r
7840 #define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos) /*!< USB GINTMSK_HOSTMODE: SessReqIntMsk Mask */
\r
7841 #define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos 31 /*!< USB GINTMSK_HOSTMODE: WkUpIntMsk Position */
\r
7842 #define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos) /*!< USB GINTMSK_HOSTMODE: WkUpIntMsk Mask */
\r
7844 /* --------------------------- USB_GINTMSK_DEVICEMODE --------------------------- */
\r
7845 #define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos 1 /*!< USB GINTMSK_DEVICEMODE: ModeMisMsk Position */
\r
7846 #define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: ModeMisMsk Mask */
\r
7847 #define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos 2 /*!< USB GINTMSK_DEVICEMODE: OTGIntMsk Position */
\r
7848 #define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: OTGIntMsk Mask */
\r
7849 #define USB_GINTMSK_DEVICEMODE_SofMsk_Pos 3 /*!< USB GINTMSK_DEVICEMODE: SofMsk Position */
\r
7850 #define USB_GINTMSK_DEVICEMODE_SofMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_SofMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: SofMsk Mask */
\r
7851 #define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos 4 /*!< USB GINTMSK_DEVICEMODE: RxFLvlMsk Position */
\r
7852 #define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: RxFLvlMsk Mask */
\r
7853 #define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos 6 /*!< USB GINTMSK_DEVICEMODE: GINNakEffMsk Position */
\r
7854 #define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: GINNakEffMsk Mask */
\r
7855 #define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos 7 /*!< USB GINTMSK_DEVICEMODE: GOUTNakEffMsk Position */
\r
7856 #define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: GOUTNakEffMsk Mask */
\r
7857 #define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos 10 /*!< USB GINTMSK_DEVICEMODE: ErlySuspMsk Position */
\r
7858 #define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: ErlySuspMsk Mask */
\r
7859 #define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos 11 /*!< USB GINTMSK_DEVICEMODE: USBSuspMsk Position */
\r
7860 #define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: USBSuspMsk Mask */
\r
7861 #define USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos 12 /*!< USB GINTMSK_DEVICEMODE: USBRstMsk Position */
\r
7862 #define USB_GINTMSK_DEVICEMODE_USBRstMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: USBRstMsk Mask */
\r
7863 #define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos 13 /*!< USB GINTMSK_DEVICEMODE: EnumDoneMsk Position */
\r
7864 #define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: EnumDoneMsk Mask */
\r
7865 #define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos 14 /*!< USB GINTMSK_DEVICEMODE: ISOOutDropMsk Position */
\r
7866 #define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: ISOOutDropMsk Mask */
\r
7867 #define USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos 15 /*!< USB GINTMSK_DEVICEMODE: EOPFMsk Position */
\r
7868 #define USB_GINTMSK_DEVICEMODE_EOPFMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: EOPFMsk Mask */
\r
7869 #define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos 18 /*!< USB GINTMSK_DEVICEMODE: IEPIntMsk Position */
\r
7870 #define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: IEPIntMsk Mask */
\r
7871 #define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos 19 /*!< USB GINTMSK_DEVICEMODE: OEPIntMsk Position */
\r
7872 #define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: OEPIntMsk Mask */
\r
7873 #define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos 20 /*!< USB GINTMSK_DEVICEMODE: incompISOINMsk Position */
\r
7874 #define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos)/*!< USB GINTMSK_DEVICEMODE: incompISOINMsk Mask */
\r
7875 #define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos 21 /*!< USB GINTMSK_DEVICEMODE: incomplSOOUTMsk Position */
\r
7876 #define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos)/*!< USB GINTMSK_DEVICEMODE: incomplSOOUTMsk Mask */
\r
7877 #define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos 28 /*!< USB GINTMSK_DEVICEMODE: ConIDStsChngMsk Position */
\r
7878 #define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos)/*!< USB GINTMSK_DEVICEMODE: ConIDStsChngMsk Mask */
\r
7879 #define USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Pos 29 /*!< USB GINTMSK_DEVICEMODE: DisconnIntMsk Position */
\r
7880 #define USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: DisconnIntMsk Mask */
\r
7881 #define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos 30 /*!< USB GINTMSK_DEVICEMODE: SessReqIntMsk Position */
\r
7882 #define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: SessReqIntMsk Mask */
\r
7883 #define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos 31 /*!< USB GINTMSK_DEVICEMODE: WkUpIntMsk Position */
\r
7884 #define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: WkUpIntMsk Mask */
\r
7886 /* ---------------------------- USB_GRXSTSR_HOSTMODE ---------------------------- */
\r
7887 #define USB_GRXSTSR_HOSTMODE_ChNum_Pos 0 /*!< USB GRXSTSR_HOSTMODE: ChNum Position */
\r
7888 #define USB_GRXSTSR_HOSTMODE_ChNum_Msk (0x0fUL << USB_GRXSTSR_HOSTMODE_ChNum_Pos) /*!< USB GRXSTSR_HOSTMODE: ChNum Mask */
\r
7889 #define USB_GRXSTSR_HOSTMODE_BCnt_Pos 4 /*!< USB GRXSTSR_HOSTMODE: BCnt Position */
\r
7890 #define USB_GRXSTSR_HOSTMODE_BCnt_Msk (0x000007ffUL << USB_GRXSTSR_HOSTMODE_BCnt_Pos) /*!< USB GRXSTSR_HOSTMODE: BCnt Mask */
\r
7891 #define USB_GRXSTSR_HOSTMODE_DPID_Pos 15 /*!< USB GRXSTSR_HOSTMODE: DPID Position */
\r
7892 #define USB_GRXSTSR_HOSTMODE_DPID_Msk (0x03UL << USB_GRXSTSR_HOSTMODE_DPID_Pos) /*!< USB GRXSTSR_HOSTMODE: DPID Mask */
\r
7893 #define USB_GRXSTSR_HOSTMODE_PktSts_Pos 17 /*!< USB GRXSTSR_HOSTMODE: PktSts Position */
\r
7894 #define USB_GRXSTSR_HOSTMODE_PktSts_Msk (0x0fUL << USB_GRXSTSR_HOSTMODE_PktSts_Pos) /*!< USB GRXSTSR_HOSTMODE: PktSts Mask */
\r
7896 /* --------------------------- USB_GRXSTSR_DEVICEMODE --------------------------- */
\r
7897 #define USB_GRXSTSR_DEVICEMODE_EPNum_Pos 0 /*!< USB GRXSTSR_DEVICEMODE: EPNum Position */
\r
7898 #define USB_GRXSTSR_DEVICEMODE_EPNum_Msk (0x0fUL << USB_GRXSTSR_DEVICEMODE_EPNum_Pos) /*!< USB GRXSTSR_DEVICEMODE: EPNum Mask */
\r
7899 #define USB_GRXSTSR_DEVICEMODE_BCnt_Pos 4 /*!< USB GRXSTSR_DEVICEMODE: BCnt Position */
\r
7900 #define USB_GRXSTSR_DEVICEMODE_BCnt_Msk (0x000007ffUL << USB_GRXSTSR_DEVICEMODE_BCnt_Pos) /*!< USB GRXSTSR_DEVICEMODE: BCnt Mask */
\r
7901 #define USB_GRXSTSR_DEVICEMODE_DPID_Pos 15 /*!< USB GRXSTSR_DEVICEMODE: DPID Position */
\r
7902 #define USB_GRXSTSR_DEVICEMODE_DPID_Msk (0x03UL << USB_GRXSTSR_DEVICEMODE_DPID_Pos) /*!< USB GRXSTSR_DEVICEMODE: DPID Mask */
\r
7903 #define USB_GRXSTSR_DEVICEMODE_PktSts_Pos 17 /*!< USB GRXSTSR_DEVICEMODE: PktSts Position */
\r
7904 #define USB_GRXSTSR_DEVICEMODE_PktSts_Msk (0x0fUL << USB_GRXSTSR_DEVICEMODE_PktSts_Pos) /*!< USB GRXSTSR_DEVICEMODE: PktSts Mask */
\r
7905 #define USB_GRXSTSR_DEVICEMODE_FN_Pos 21 /*!< USB GRXSTSR_DEVICEMODE: FN Position */
\r
7906 #define USB_GRXSTSR_DEVICEMODE_FN_Msk (0x0fUL << USB_GRXSTSR_DEVICEMODE_FN_Pos) /*!< USB GRXSTSR_DEVICEMODE: FN Mask */
\r
7908 /* --------------------------- USB_GRXSTSP_DEVICEMODE --------------------------- */
\r
7909 #define USB_GRXSTSP_DEVICEMODE_EPNum_Pos 0 /*!< USB GRXSTSP_DEVICEMODE: EPNum Position */
\r
7910 #define USB_GRXSTSP_DEVICEMODE_EPNum_Msk (0x0fUL << USB_GRXSTSP_DEVICEMODE_EPNum_Pos) /*!< USB GRXSTSP_DEVICEMODE: EPNum Mask */
\r
7911 #define USB_GRXSTSP_DEVICEMODE_BCnt_Pos 4 /*!< USB GRXSTSP_DEVICEMODE: BCnt Position */
\r
7912 #define USB_GRXSTSP_DEVICEMODE_BCnt_Msk (0x000007ffUL << USB_GRXSTSP_DEVICEMODE_BCnt_Pos) /*!< USB GRXSTSP_DEVICEMODE: BCnt Mask */
\r
7913 #define USB_GRXSTSP_DEVICEMODE_DPID_Pos 15 /*!< USB GRXSTSP_DEVICEMODE: DPID Position */
\r
7914 #define USB_GRXSTSP_DEVICEMODE_DPID_Msk (0x03UL << USB_GRXSTSP_DEVICEMODE_DPID_Pos) /*!< USB GRXSTSP_DEVICEMODE: DPID Mask */
\r
7915 #define USB_GRXSTSP_DEVICEMODE_PktSts_Pos 17 /*!< USB GRXSTSP_DEVICEMODE: PktSts Position */
\r
7916 #define USB_GRXSTSP_DEVICEMODE_PktSts_Msk (0x0fUL << USB_GRXSTSP_DEVICEMODE_PktSts_Pos) /*!< USB GRXSTSP_DEVICEMODE: PktSts Mask */
\r
7917 #define USB_GRXSTSP_DEVICEMODE_FN_Pos 21 /*!< USB GRXSTSP_DEVICEMODE: FN Position */
\r
7918 #define USB_GRXSTSP_DEVICEMODE_FN_Msk (0x0fUL << USB_GRXSTSP_DEVICEMODE_FN_Pos) /*!< USB GRXSTSP_DEVICEMODE: FN Mask */
\r
7920 /* ---------------------------- USB_GRXSTSP_HOSTMODE ---------------------------- */
\r
7921 #define USB_GRXSTSP_HOSTMODE_ChNum_Pos 0 /*!< USB GRXSTSP_HOSTMODE: ChNum Position */
\r
7922 #define USB_GRXSTSP_HOSTMODE_ChNum_Msk (0x0fUL << USB_GRXSTSP_HOSTMODE_ChNum_Pos) /*!< USB GRXSTSP_HOSTMODE: ChNum Mask */
\r
7923 #define USB_GRXSTSP_HOSTMODE_BCnt_Pos 4 /*!< USB GRXSTSP_HOSTMODE: BCnt Position */
\r
7924 #define USB_GRXSTSP_HOSTMODE_BCnt_Msk (0x000007ffUL << USB_GRXSTSP_HOSTMODE_BCnt_Pos) /*!< USB GRXSTSP_HOSTMODE: BCnt Mask */
\r
7925 #define USB_GRXSTSP_HOSTMODE_DPID_Pos 15 /*!< USB GRXSTSP_HOSTMODE: DPID Position */
\r
7926 #define USB_GRXSTSP_HOSTMODE_DPID_Msk (0x03UL << USB_GRXSTSP_HOSTMODE_DPID_Pos) /*!< USB GRXSTSP_HOSTMODE: DPID Mask */
\r
7927 #define USB_GRXSTSP_HOSTMODE_PktSts_Pos 17 /*!< USB GRXSTSP_HOSTMODE: PktSts Position */
\r
7928 #define USB_GRXSTSP_HOSTMODE_PktSts_Msk (0x0fUL << USB_GRXSTSP_HOSTMODE_PktSts_Pos) /*!< USB GRXSTSP_HOSTMODE: PktSts Mask */
\r
7930 /* --------------------------------- USB_GRXFSIZ -------------------------------- */
\r
7931 #define USB_GRXFSIZ_RxFDep_Pos 0 /*!< USB GRXFSIZ: RxFDep Position */
\r
7932 #define USB_GRXFSIZ_RxFDep_Msk (0x0000ffffUL << USB_GRXFSIZ_RxFDep_Pos) /*!< USB GRXFSIZ: RxFDep Mask */
\r
7934 /* --------------------------- USB_GNPTXFSIZ_HOSTMODE --------------------------- */
\r
7935 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos 0 /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFStAddr Position */
\r
7936 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Msk (0x0000ffffUL << USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos)/*!< USB GNPTXFSIZ_HOSTMODE: NPTxFStAddr Mask */
\r
7937 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos 16 /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFDep Position */
\r
7938 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Msk (0x0000ffffUL << USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos) /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFDep Mask */
\r
7940 /* -------------------------- USB_GNPTXFSIZ_DEVICEMODE -------------------------- */
\r
7941 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Pos 0 /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0StAddr Position */
\r
7942 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Msk (0x0000ffffUL << USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Pos)/*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0StAddr Mask */
\r
7943 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos 16 /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0Dep Position */
\r
7944 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Msk (0x0000ffffUL << USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos)/*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0Dep Mask */
\r
7946 /* -------------------------------- USB_GNPTXSTS -------------------------------- */
\r
7947 #define USB_GNPTXSTS_NPTxFSpcAvail_Pos 0 /*!< USB GNPTXSTS: NPTxFSpcAvail Position */
\r
7948 #define USB_GNPTXSTS_NPTxFSpcAvail_Msk (0x0000ffffUL << USB_GNPTXSTS_NPTxFSpcAvail_Pos) /*!< USB GNPTXSTS: NPTxFSpcAvail Mask */
\r
7949 #define USB_GNPTXSTS_NPTxQSpcAvail_Pos 16 /*!< USB GNPTXSTS: NPTxQSpcAvail Position */
\r
7950 #define USB_GNPTXSTS_NPTxQSpcAvail_Msk (0x000000ffUL << USB_GNPTXSTS_NPTxQSpcAvail_Pos) /*!< USB GNPTXSTS: NPTxQSpcAvail Mask */
\r
7951 #define USB_GNPTXSTS_NPTxQTop_Pos 24 /*!< USB GNPTXSTS: NPTxQTop Position */
\r
7952 #define USB_GNPTXSTS_NPTxQTop_Msk (0x7fUL << USB_GNPTXSTS_NPTxQTop_Pos) /*!< USB GNPTXSTS: NPTxQTop Mask */
\r
7954 /* ---------------------------------- USB_GUID ---------------------------------- */
\r
7955 #define USB_GUID_MOD_REV_Pos 0 /*!< USB GUID: MOD_REV Position */
\r
7956 #define USB_GUID_MOD_REV_Msk (0x000000ffUL << USB_GUID_MOD_REV_Pos) /*!< USB GUID: MOD_REV Mask */
\r
7957 #define USB_GUID_MOD_TYPE_Pos 8 /*!< USB GUID: MOD_TYPE Position */
\r
7958 #define USB_GUID_MOD_TYPE_Msk (0x000000ffUL << USB_GUID_MOD_TYPE_Pos) /*!< USB GUID: MOD_TYPE Mask */
\r
7959 #define USB_GUID_MOD_NUMBER_Pos 16 /*!< USB GUID: MOD_NUMBER Position */
\r
7960 #define USB_GUID_MOD_NUMBER_Msk (0x0000ffffUL << USB_GUID_MOD_NUMBER_Pos) /*!< USB GUID: MOD_NUMBER Mask */
\r
7962 /* -------------------------------- USB_GDFIFOCFG ------------------------------- */
\r
7963 #define USB_GDFIFOCFG_GDFIFOCfg_Pos 0 /*!< USB GDFIFOCFG: GDFIFOCfg Position */
\r
7964 #define USB_GDFIFOCFG_GDFIFOCfg_Msk (0x0000ffffUL << USB_GDFIFOCFG_GDFIFOCfg_Pos) /*!< USB GDFIFOCFG: GDFIFOCfg Mask */
\r
7965 #define USB_GDFIFOCFG_EPInfoBaseAddr_Pos 16 /*!< USB GDFIFOCFG: EPInfoBaseAddr Position */
\r
7966 #define USB_GDFIFOCFG_EPInfoBaseAddr_Msk (0x0000ffffUL << USB_GDFIFOCFG_EPInfoBaseAddr_Pos) /*!< USB GDFIFOCFG: EPInfoBaseAddr Mask */
\r
7968 /* -------------------------------- USB_HPTXFSIZ -------------------------------- */
\r
7969 #define USB_HPTXFSIZ_PTxFStAddr_Pos 0 /*!< USB HPTXFSIZ: PTxFStAddr Position */
\r
7970 #define USB_HPTXFSIZ_PTxFStAddr_Msk (0x0000ffffUL << USB_HPTXFSIZ_PTxFStAddr_Pos) /*!< USB HPTXFSIZ: PTxFStAddr Mask */
\r
7971 #define USB_HPTXFSIZ_PTxFSize_Pos 16 /*!< USB HPTXFSIZ: PTxFSize Position */
\r
7972 #define USB_HPTXFSIZ_PTxFSize_Msk (0x0000ffffUL << USB_HPTXFSIZ_PTxFSize_Pos) /*!< USB HPTXFSIZ: PTxFSize Mask */
\r
7974 /* -------------------------------- USB_DIEPTXF1 -------------------------------- */
\r
7975 #define USB_DIEPTXF1_INEPnTxFStAddr_Pos 0 /*!< USB DIEPTXF1: INEPnTxFStAddr Position */
\r
7976 #define USB_DIEPTXF1_INEPnTxFStAddr_Msk (0x0000ffffUL << USB_DIEPTXF1_INEPnTxFStAddr_Pos) /*!< USB DIEPTXF1: INEPnTxFStAddr Mask */
\r
7977 #define USB_DIEPTXF1_INEPnTxFDep_Pos 16 /*!< USB DIEPTXF1: INEPnTxFDep Position */
\r
7978 #define USB_DIEPTXF1_INEPnTxFDep_Msk (0x0000ffffUL << USB_DIEPTXF1_INEPnTxFDep_Pos) /*!< USB DIEPTXF1: INEPnTxFDep Mask */
\r
7980 /* -------------------------------- USB_DIEPTXF2 -------------------------------- */
\r
7981 #define USB_DIEPTXF2_INEPnTxFStAddr_Pos 0 /*!< USB DIEPTXF2: INEPnTxFStAddr Position */
\r
7982 #define USB_DIEPTXF2_INEPnTxFStAddr_Msk (0x0000ffffUL << USB_DIEPTXF2_INEPnTxFStAddr_Pos) /*!< USB DIEPTXF2: INEPnTxFStAddr Mask */
\r
7983 #define USB_DIEPTXF2_INEPnTxFDep_Pos 16 /*!< USB DIEPTXF2: INEPnTxFDep Position */
\r
7984 #define USB_DIEPTXF2_INEPnTxFDep_Msk (0x0000ffffUL << USB_DIEPTXF2_INEPnTxFDep_Pos) /*!< USB DIEPTXF2: INEPnTxFDep Mask */
\r
7986 /* -------------------------------- USB_DIEPTXF3 -------------------------------- */
\r
7987 #define USB_DIEPTXF3_INEPnTxFStAddr_Pos 0 /*!< USB DIEPTXF3: INEPnTxFStAddr Position */
\r
7988 #define USB_DIEPTXF3_INEPnTxFStAddr_Msk (0x0000ffffUL << USB_DIEPTXF3_INEPnTxFStAddr_Pos) /*!< USB DIEPTXF3: INEPnTxFStAddr Mask */
\r
7989 #define USB_DIEPTXF3_INEPnTxFDep_Pos 16 /*!< USB DIEPTXF3: INEPnTxFDep Position */
\r
7990 #define USB_DIEPTXF3_INEPnTxFDep_Msk (0x0000ffffUL << USB_DIEPTXF3_INEPnTxFDep_Pos) /*!< USB DIEPTXF3: INEPnTxFDep Mask */
\r
7992 /* -------------------------------- USB_DIEPTXF4 -------------------------------- */
\r
7993 #define USB_DIEPTXF4_INEPnTxFStAddr_Pos 0 /*!< USB DIEPTXF4: INEPnTxFStAddr Position */
\r
7994 #define USB_DIEPTXF4_INEPnTxFStAddr_Msk (0x0000ffffUL << USB_DIEPTXF4_INEPnTxFStAddr_Pos) /*!< USB DIEPTXF4: INEPnTxFStAddr Mask */
\r
7995 #define USB_DIEPTXF4_INEPnTxFDep_Pos 16 /*!< USB DIEPTXF4: INEPnTxFDep Position */
\r
7996 #define USB_DIEPTXF4_INEPnTxFDep_Msk (0x0000ffffUL << USB_DIEPTXF4_INEPnTxFDep_Pos) /*!< USB DIEPTXF4: INEPnTxFDep Mask */
\r
7998 /* -------------------------------- USB_DIEPTXF5 -------------------------------- */
\r
7999 #define USB_DIEPTXF5_INEPnTxFStAddr_Pos 0 /*!< USB DIEPTXF5: INEPnTxFStAddr Position */
\r
8000 #define USB_DIEPTXF5_INEPnTxFStAddr_Msk (0x0000ffffUL << USB_DIEPTXF5_INEPnTxFStAddr_Pos) /*!< USB DIEPTXF5: INEPnTxFStAddr Mask */
\r
8001 #define USB_DIEPTXF5_INEPnTxFDep_Pos 16 /*!< USB DIEPTXF5: INEPnTxFDep Position */
\r
8002 #define USB_DIEPTXF5_INEPnTxFDep_Msk (0x0000ffffUL << USB_DIEPTXF5_INEPnTxFDep_Pos) /*!< USB DIEPTXF5: INEPnTxFDep Mask */
\r
8004 /* -------------------------------- USB_DIEPTXF6 -------------------------------- */
\r
8005 #define USB_DIEPTXF6_INEPnTxFStAddr_Pos 0 /*!< USB DIEPTXF6: INEPnTxFStAddr Position */
\r
8006 #define USB_DIEPTXF6_INEPnTxFStAddr_Msk (0x0000ffffUL << USB_DIEPTXF6_INEPnTxFStAddr_Pos) /*!< USB DIEPTXF6: INEPnTxFStAddr Mask */
\r
8007 #define USB_DIEPTXF6_INEPnTxFDep_Pos 16 /*!< USB DIEPTXF6: INEPnTxFDep Position */
\r
8008 #define USB_DIEPTXF6_INEPnTxFDep_Msk (0x0000ffffUL << USB_DIEPTXF6_INEPnTxFDep_Pos) /*!< USB DIEPTXF6: INEPnTxFDep Mask */
\r
8010 /* ---------------------------------- USB_HCFG ---------------------------------- */
\r
8011 #define USB_HCFG_FSLSPclkSel_Pos 0 /*!< USB HCFG: FSLSPclkSel Position */
\r
8012 #define USB_HCFG_FSLSPclkSel_Msk (0x03UL << USB_HCFG_FSLSPclkSel_Pos) /*!< USB HCFG: FSLSPclkSel Mask */
\r
8013 #define USB_HCFG_FSLSSupp_Pos 2 /*!< USB HCFG: FSLSSupp Position */
\r
8014 #define USB_HCFG_FSLSSupp_Msk (0x01UL << USB_HCFG_FSLSSupp_Pos) /*!< USB HCFG: FSLSSupp Mask */
\r
8015 #define USB_HCFG_DescDMA_Pos 23 /*!< USB HCFG: DescDMA Position */
\r
8016 #define USB_HCFG_DescDMA_Msk (0x01UL << USB_HCFG_DescDMA_Pos) /*!< USB HCFG: DescDMA Mask */
\r
8017 #define USB_HCFG_FrListEn_Pos 24 /*!< USB HCFG: FrListEn Position */
\r
8018 #define USB_HCFG_FrListEn_Msk (0x03UL << USB_HCFG_FrListEn_Pos) /*!< USB HCFG: FrListEn Mask */
\r
8019 #define USB_HCFG_PerSchedEna_Pos 26 /*!< USB HCFG: PerSchedEna Position */
\r
8020 #define USB_HCFG_PerSchedEna_Msk (0x01UL << USB_HCFG_PerSchedEna_Pos) /*!< USB HCFG: PerSchedEna Mask */
\r
8022 /* ---------------------------------- USB_HFIR ---------------------------------- */
\r
8023 #define USB_HFIR_FrInt_Pos 0 /*!< USB HFIR: FrInt Position */
\r
8024 #define USB_HFIR_FrInt_Msk (0x0000ffffUL << USB_HFIR_FrInt_Pos) /*!< USB HFIR: FrInt Mask */
\r
8025 #define USB_HFIR_HFIRRldCtrl_Pos 16 /*!< USB HFIR: HFIRRldCtrl Position */
\r
8026 #define USB_HFIR_HFIRRldCtrl_Msk (0x01UL << USB_HFIR_HFIRRldCtrl_Pos) /*!< USB HFIR: HFIRRldCtrl Mask */
\r
8028 /* ---------------------------------- USB_HFNUM --------------------------------- */
\r
8029 #define USB_HFNUM_FrNum_Pos 0 /*!< USB HFNUM: FrNum Position */
\r
8030 #define USB_HFNUM_FrNum_Msk (0x0000ffffUL << USB_HFNUM_FrNum_Pos) /*!< USB HFNUM: FrNum Mask */
\r
8031 #define USB_HFNUM_FrRem_Pos 16 /*!< USB HFNUM: FrRem Position */
\r
8032 #define USB_HFNUM_FrRem_Msk (0x0000ffffUL << USB_HFNUM_FrRem_Pos) /*!< USB HFNUM: FrRem Mask */
\r
8034 /* --------------------------------- USB_HPTXSTS -------------------------------- */
\r
8035 #define USB_HPTXSTS_PTxFSpcAvail_Pos 0 /*!< USB HPTXSTS: PTxFSpcAvail Position */
\r
8036 #define USB_HPTXSTS_PTxFSpcAvail_Msk (0x0000ffffUL << USB_HPTXSTS_PTxFSpcAvail_Pos) /*!< USB HPTXSTS: PTxFSpcAvail Mask */
\r
8037 #define USB_HPTXSTS_PTxQSpcAvail_Pos 16 /*!< USB HPTXSTS: PTxQSpcAvail Position */
\r
8038 #define USB_HPTXSTS_PTxQSpcAvail_Msk (0x000000ffUL << USB_HPTXSTS_PTxQSpcAvail_Pos) /*!< USB HPTXSTS: PTxQSpcAvail Mask */
\r
8039 #define USB_HPTXSTS_PTxQTop_Pos 24 /*!< USB HPTXSTS: PTxQTop Position */
\r
8040 #define USB_HPTXSTS_PTxQTop_Msk (0x000000ffUL << USB_HPTXSTS_PTxQTop_Pos) /*!< USB HPTXSTS: PTxQTop Mask */
\r
8042 /* ---------------------------------- USB_HAINT --------------------------------- */
\r
8043 #define USB_HAINT_HAINT_Pos 0 /*!< USB HAINT: HAINT Position */
\r
8044 #define USB_HAINT_HAINT_Msk (0x00003fffUL << USB_HAINT_HAINT_Pos) /*!< USB HAINT: HAINT Mask */
\r
8046 /* -------------------------------- USB_HAINTMSK -------------------------------- */
\r
8047 #define USB_HAINTMSK_HAINTMsk_Pos 0 /*!< USB HAINTMSK: HAINTMsk Position */
\r
8048 #define USB_HAINTMSK_HAINTMsk_Msk (0x00003fffUL << USB_HAINTMSK_HAINTMsk_Pos) /*!< USB HAINTMSK: HAINTMsk Mask */
\r
8050 /* -------------------------------- USB_HFLBADDR -------------------------------- */
\r
8051 #define USB_HFLBADDR_Starting_Address_Pos 0 /*!< USB HFLBADDR: Starting_Address Position */
\r
8052 #define USB_HFLBADDR_Starting_Address_Msk (0xffffffffUL << USB_HFLBADDR_Starting_Address_Pos) /*!< USB HFLBADDR: Starting_Address Mask */
\r
8054 /* ---------------------------------- USB_HPRT ---------------------------------- */
\r
8055 #define USB_HPRT_PrtConnSts_Pos 0 /*!< USB HPRT: PrtConnSts Position */
\r
8056 #define USB_HPRT_PrtConnSts_Msk (0x01UL << USB_HPRT_PrtConnSts_Pos) /*!< USB HPRT: PrtConnSts Mask */
\r
8057 #define USB_HPRT_PrtConnDet_Pos 1 /*!< USB HPRT: PrtConnDet Position */
\r
8058 #define USB_HPRT_PrtConnDet_Msk (0x01UL << USB_HPRT_PrtConnDet_Pos) /*!< USB HPRT: PrtConnDet Mask */
\r
8059 #define USB_HPRT_PrtEna_Pos 2 /*!< USB HPRT: PrtEna Position */
\r
8060 #define USB_HPRT_PrtEna_Msk (0x01UL << USB_HPRT_PrtEna_Pos) /*!< USB HPRT: PrtEna Mask */
\r
8061 #define USB_HPRT_PrtEnChng_Pos 3 /*!< USB HPRT: PrtEnChng Position */
\r
8062 #define USB_HPRT_PrtEnChng_Msk (0x01UL << USB_HPRT_PrtEnChng_Pos) /*!< USB HPRT: PrtEnChng Mask */
\r
8063 #define USB_HPRT_PrtOvrCurrAct_Pos 4 /*!< USB HPRT: PrtOvrCurrAct Position */
\r
8064 #define USB_HPRT_PrtOvrCurrAct_Msk (0x01UL << USB_HPRT_PrtOvrCurrAct_Pos) /*!< USB HPRT: PrtOvrCurrAct Mask */
\r
8065 #define USB_HPRT_PrtOvrCurrChng_Pos 5 /*!< USB HPRT: PrtOvrCurrChng Position */
\r
8066 #define USB_HPRT_PrtOvrCurrChng_Msk (0x01UL << USB_HPRT_PrtOvrCurrChng_Pos) /*!< USB HPRT: PrtOvrCurrChng Mask */
\r
8067 #define USB_HPRT_PrtRes_Pos 6 /*!< USB HPRT: PrtRes Position */
\r
8068 #define USB_HPRT_PrtRes_Msk (0x01UL << USB_HPRT_PrtRes_Pos) /*!< USB HPRT: PrtRes Mask */
\r
8069 #define USB_HPRT_PrtSusp_Pos 7 /*!< USB HPRT: PrtSusp Position */
\r
8070 #define USB_HPRT_PrtSusp_Msk (0x01UL << USB_HPRT_PrtSusp_Pos) /*!< USB HPRT: PrtSusp Mask */
\r
8071 #define USB_HPRT_PrtRst_Pos 8 /*!< USB HPRT: PrtRst Position */
\r
8072 #define USB_HPRT_PrtRst_Msk (0x01UL << USB_HPRT_PrtRst_Pos) /*!< USB HPRT: PrtRst Mask */
\r
8073 #define USB_HPRT_PrtLnSts_Pos 10 /*!< USB HPRT: PrtLnSts Position */
\r
8074 #define USB_HPRT_PrtLnSts_Msk (0x03UL << USB_HPRT_PrtLnSts_Pos) /*!< USB HPRT: PrtLnSts Mask */
\r
8075 #define USB_HPRT_PrtPwr_Pos 12 /*!< USB HPRT: PrtPwr Position */
\r
8076 #define USB_HPRT_PrtPwr_Msk (0x01UL << USB_HPRT_PrtPwr_Pos) /*!< USB HPRT: PrtPwr Mask */
\r
8077 #define USB_HPRT_PrtSpd_Pos 17 /*!< USB HPRT: PrtSpd Position */
\r
8078 #define USB_HPRT_PrtSpd_Msk (0x03UL << USB_HPRT_PrtSpd_Pos) /*!< USB HPRT: PrtSpd Mask */
\r
8080 /* ---------------------------------- USB_DCFG ---------------------------------- */
\r
8081 #define USB_DCFG_DevSpd_Pos 0 /*!< USB DCFG: DevSpd Position */
\r
8082 #define USB_DCFG_DevSpd_Msk (0x03UL << USB_DCFG_DevSpd_Pos) /*!< USB DCFG: DevSpd Mask */
\r
8083 #define USB_DCFG_NZStsOUTHShk_Pos 2 /*!< USB DCFG: NZStsOUTHShk Position */
\r
8084 #define USB_DCFG_NZStsOUTHShk_Msk (0x01UL << USB_DCFG_NZStsOUTHShk_Pos) /*!< USB DCFG: NZStsOUTHShk Mask */
\r
8085 #define USB_DCFG_DevAddr_Pos 4 /*!< USB DCFG: DevAddr Position */
\r
8086 #define USB_DCFG_DevAddr_Msk (0x7fUL << USB_DCFG_DevAddr_Pos) /*!< USB DCFG: DevAddr Mask */
\r
8087 #define USB_DCFG_PerFrInt_Pos 11 /*!< USB DCFG: PerFrInt Position */
\r
8088 #define USB_DCFG_PerFrInt_Msk (0x03UL << USB_DCFG_PerFrInt_Pos) /*!< USB DCFG: PerFrInt Mask */
\r
8089 #define USB_DCFG_DescDMA_Pos 23 /*!< USB DCFG: DescDMA Position */
\r
8090 #define USB_DCFG_DescDMA_Msk (0x01UL << USB_DCFG_DescDMA_Pos) /*!< USB DCFG: DescDMA Mask */
\r
8091 #define USB_DCFG_PerSchIntvl_Pos 24 /*!< USB DCFG: PerSchIntvl Position */
\r
8092 #define USB_DCFG_PerSchIntvl_Msk (0x03UL << USB_DCFG_PerSchIntvl_Pos) /*!< USB DCFG: PerSchIntvl Mask */
\r
8094 /* ---------------------------------- USB_DCTL ---------------------------------- */
\r
8095 #define USB_DCTL_RmtWkUpSig_Pos 0 /*!< USB DCTL: RmtWkUpSig Position */
\r
8096 #define USB_DCTL_RmtWkUpSig_Msk (0x01UL << USB_DCTL_RmtWkUpSig_Pos) /*!< USB DCTL: RmtWkUpSig Mask */
\r
8097 #define USB_DCTL_SftDiscon_Pos 1 /*!< USB DCTL: SftDiscon Position */
\r
8098 #define USB_DCTL_SftDiscon_Msk (0x01UL << USB_DCTL_SftDiscon_Pos) /*!< USB DCTL: SftDiscon Mask */
\r
8099 #define USB_DCTL_GNPINNakSts_Pos 2 /*!< USB DCTL: GNPINNakSts Position */
\r
8100 #define USB_DCTL_GNPINNakSts_Msk (0x01UL << USB_DCTL_GNPINNakSts_Pos) /*!< USB DCTL: GNPINNakSts Mask */
\r
8101 #define USB_DCTL_GOUTNakSts_Pos 3 /*!< USB DCTL: GOUTNakSts Position */
\r
8102 #define USB_DCTL_GOUTNakSts_Msk (0x01UL << USB_DCTL_GOUTNakSts_Pos) /*!< USB DCTL: GOUTNakSts Mask */
\r
8103 #define USB_DCTL_SGNPInNak_Pos 7 /*!< USB DCTL: SGNPInNak Position */
\r
8104 #define USB_DCTL_SGNPInNak_Msk (0x01UL << USB_DCTL_SGNPInNak_Pos) /*!< USB DCTL: SGNPInNak Mask */
\r
8105 #define USB_DCTL_CGNPInNak_Pos 8 /*!< USB DCTL: CGNPInNak Position */
\r
8106 #define USB_DCTL_CGNPInNak_Msk (0x01UL << USB_DCTL_CGNPInNak_Pos) /*!< USB DCTL: CGNPInNak Mask */
\r
8107 #define USB_DCTL_SGOUTNak_Pos 9 /*!< USB DCTL: SGOUTNak Position */
\r
8108 #define USB_DCTL_SGOUTNak_Msk (0x01UL << USB_DCTL_SGOUTNak_Pos) /*!< USB DCTL: SGOUTNak Mask */
\r
8109 #define USB_DCTL_CGOUTNak_Pos 10 /*!< USB DCTL: CGOUTNak Position */
\r
8110 #define USB_DCTL_CGOUTNak_Msk (0x01UL << USB_DCTL_CGOUTNak_Pos) /*!< USB DCTL: CGOUTNak Mask */
\r
8111 #define USB_DCTL_GMC_Pos 13 /*!< USB DCTL: GMC Position */
\r
8112 #define USB_DCTL_GMC_Msk (0x03UL << USB_DCTL_GMC_Pos) /*!< USB DCTL: GMC Mask */
\r
8113 #define USB_DCTL_IgnrFrmNum_Pos 15 /*!< USB DCTL: IgnrFrmNum Position */
\r
8114 #define USB_DCTL_IgnrFrmNum_Msk (0x01UL << USB_DCTL_IgnrFrmNum_Pos) /*!< USB DCTL: IgnrFrmNum Mask */
\r
8115 #define USB_DCTL_NakOnBble_Pos 16 /*!< USB DCTL: NakOnBble Position */
\r
8116 #define USB_DCTL_NakOnBble_Msk (0x01UL << USB_DCTL_NakOnBble_Pos) /*!< USB DCTL: NakOnBble Mask */
\r
8117 #define USB_DCTL_EnContOnBNA_Pos 17 /*!< USB DCTL: EnContOnBNA Position */
\r
8118 #define USB_DCTL_EnContOnBNA_Msk (0x01UL << USB_DCTL_EnContOnBNA_Pos) /*!< USB DCTL: EnContOnBNA Mask */
\r
8120 /* ---------------------------------- USB_DSTS ---------------------------------- */
\r
8121 #define USB_DSTS_SuspSts_Pos 0 /*!< USB DSTS: SuspSts Position */
\r
8122 #define USB_DSTS_SuspSts_Msk (0x01UL << USB_DSTS_SuspSts_Pos) /*!< USB DSTS: SuspSts Mask */
\r
8123 #define USB_DSTS_EnumSpd_Pos 1 /*!< USB DSTS: EnumSpd Position */
\r
8124 #define USB_DSTS_EnumSpd_Msk (0x03UL << USB_DSTS_EnumSpd_Pos) /*!< USB DSTS: EnumSpd Mask */
\r
8125 #define USB_DSTS_ErrticErr_Pos 3 /*!< USB DSTS: ErrticErr Position */
\r
8126 #define USB_DSTS_ErrticErr_Msk (0x01UL << USB_DSTS_ErrticErr_Pos) /*!< USB DSTS: ErrticErr Mask */
\r
8127 #define USB_DSTS_SOFFN_Pos 8 /*!< USB DSTS: SOFFN Position */
\r
8128 #define USB_DSTS_SOFFN_Msk (0x00003fffUL << USB_DSTS_SOFFN_Pos) /*!< USB DSTS: SOFFN Mask */
\r
8130 /* --------------------------------- USB_DIEPMSK -------------------------------- */
\r
8131 #define USB_DIEPMSK_XferComplMsk_Pos 0 /*!< USB DIEPMSK: XferComplMsk Position */
\r
8132 #define USB_DIEPMSK_XferComplMsk_Msk (0x01UL << USB_DIEPMSK_XferComplMsk_Pos) /*!< USB DIEPMSK: XferComplMsk Mask */
\r
8133 #define USB_DIEPMSK_EPDisbldMsk_Pos 1 /*!< USB DIEPMSK: EPDisbldMsk Position */
\r
8134 #define USB_DIEPMSK_EPDisbldMsk_Msk (0x01UL << USB_DIEPMSK_EPDisbldMsk_Pos) /*!< USB DIEPMSK: EPDisbldMsk Mask */
\r
8135 #define USB_DIEPMSK_AHBErrMsk_Pos 2 /*!< USB DIEPMSK: AHBErrMsk Position */
\r
8136 #define USB_DIEPMSK_AHBErrMsk_Msk (0x01UL << USB_DIEPMSK_AHBErrMsk_Pos) /*!< USB DIEPMSK: AHBErrMsk Mask */
\r
8137 #define USB_DIEPMSK_TimeOUTMsk_Pos 3 /*!< USB DIEPMSK: TimeOUTMsk Position */
\r
8138 #define USB_DIEPMSK_TimeOUTMsk_Msk (0x01UL << USB_DIEPMSK_TimeOUTMsk_Pos) /*!< USB DIEPMSK: TimeOUTMsk Mask */
\r
8139 #define USB_DIEPMSK_INTknTXFEmpMsk_Pos 4 /*!< USB DIEPMSK: INTknTXFEmpMsk Position */
\r
8140 #define USB_DIEPMSK_INTknTXFEmpMsk_Msk (0x01UL << USB_DIEPMSK_INTknTXFEmpMsk_Pos) /*!< USB DIEPMSK: INTknTXFEmpMsk Mask */
\r
8141 #define USB_DIEPMSK_INEPNakEffMsk_Pos 6 /*!< USB DIEPMSK: INEPNakEffMsk Position */
\r
8142 #define USB_DIEPMSK_INEPNakEffMsk_Msk (0x01UL << USB_DIEPMSK_INEPNakEffMsk_Pos) /*!< USB DIEPMSK: INEPNakEffMsk Mask */
\r
8143 #define USB_DIEPMSK_TxfifoUndrnMsk_Pos 8 /*!< USB DIEPMSK: TxfifoUndrnMsk Position */
\r
8144 #define USB_DIEPMSK_TxfifoUndrnMsk_Msk (0x01UL << USB_DIEPMSK_TxfifoUndrnMsk_Pos) /*!< USB DIEPMSK: TxfifoUndrnMsk Mask */
\r
8145 #define USB_DIEPMSK_BNAInIntrMsk_Pos 9 /*!< USB DIEPMSK: BNAInIntrMsk Position */
\r
8146 #define USB_DIEPMSK_BNAInIntrMsk_Msk (0x01UL << USB_DIEPMSK_BNAInIntrMsk_Pos) /*!< USB DIEPMSK: BNAInIntrMsk Mask */
\r
8147 #define USB_DIEPMSK_NAKMsk_Pos 13 /*!< USB DIEPMSK: NAKMsk Position */
\r
8148 #define USB_DIEPMSK_NAKMsk_Msk (0x01UL << USB_DIEPMSK_NAKMsk_Pos) /*!< USB DIEPMSK: NAKMsk Mask */
\r
8150 /* --------------------------------- USB_DOEPMSK -------------------------------- */
\r
8151 #define USB_DOEPMSK_XferComplMsk_Pos 0 /*!< USB DOEPMSK: XferComplMsk Position */
\r
8152 #define USB_DOEPMSK_XferComplMsk_Msk (0x01UL << USB_DOEPMSK_XferComplMsk_Pos) /*!< USB DOEPMSK: XferComplMsk Mask */
\r
8153 #define USB_DOEPMSK_EPDisbldMsk_Pos 1 /*!< USB DOEPMSK: EPDisbldMsk Position */
\r
8154 #define USB_DOEPMSK_EPDisbldMsk_Msk (0x01UL << USB_DOEPMSK_EPDisbldMsk_Pos) /*!< USB DOEPMSK: EPDisbldMsk Mask */
\r
8155 #define USB_DOEPMSK_AHBErrMsk_Pos 2 /*!< USB DOEPMSK: AHBErrMsk Position */
\r
8156 #define USB_DOEPMSK_AHBErrMsk_Msk (0x01UL << USB_DOEPMSK_AHBErrMsk_Pos) /*!< USB DOEPMSK: AHBErrMsk Mask */
\r
8157 #define USB_DOEPMSK_SetUPMsk_Pos 3 /*!< USB DOEPMSK: SetUPMsk Position */
\r
8158 #define USB_DOEPMSK_SetUPMsk_Msk (0x01UL << USB_DOEPMSK_SetUPMsk_Pos) /*!< USB DOEPMSK: SetUPMsk Mask */
\r
8159 #define USB_DOEPMSK_OUTTknEPdisMsk_Pos 4 /*!< USB DOEPMSK: OUTTknEPdisMsk Position */
\r
8160 #define USB_DOEPMSK_OUTTknEPdisMsk_Msk (0x01UL << USB_DOEPMSK_OUTTknEPdisMsk_Pos) /*!< USB DOEPMSK: OUTTknEPdisMsk Mask */
\r
8161 #define USB_DOEPMSK_Back2BackSETup_Pos 6 /*!< USB DOEPMSK: Back2BackSETup Position */
\r
8162 #define USB_DOEPMSK_Back2BackSETup_Msk (0x01UL << USB_DOEPMSK_Back2BackSETup_Pos) /*!< USB DOEPMSK: Back2BackSETup Mask */
\r
8163 #define USB_DOEPMSK_OutPktErrMsk_Pos 8 /*!< USB DOEPMSK: OutPktErrMsk Position */
\r
8164 #define USB_DOEPMSK_OutPktErrMsk_Msk (0x01UL << USB_DOEPMSK_OutPktErrMsk_Pos) /*!< USB DOEPMSK: OutPktErrMsk Mask */
\r
8165 #define USB_DOEPMSK_BnaOutIntrMsk_Pos 9 /*!< USB DOEPMSK: BnaOutIntrMsk Position */
\r
8166 #define USB_DOEPMSK_BnaOutIntrMsk_Msk (0x01UL << USB_DOEPMSK_BnaOutIntrMsk_Pos) /*!< USB DOEPMSK: BnaOutIntrMsk Mask */
\r
8167 #define USB_DOEPMSK_BbleErrMsk_Pos 12 /*!< USB DOEPMSK: BbleErrMsk Position */
\r
8168 #define USB_DOEPMSK_BbleErrMsk_Msk (0x01UL << USB_DOEPMSK_BbleErrMsk_Pos) /*!< USB DOEPMSK: BbleErrMsk Mask */
\r
8169 #define USB_DOEPMSK_NAKMsk_Pos 13 /*!< USB DOEPMSK: NAKMsk Position */
\r
8170 #define USB_DOEPMSK_NAKMsk_Msk (0x01UL << USB_DOEPMSK_NAKMsk_Pos) /*!< USB DOEPMSK: NAKMsk Mask */
\r
8171 #define USB_DOEPMSK_NYETMsk_Pos 14 /*!< USB DOEPMSK: NYETMsk Position */
\r
8172 #define USB_DOEPMSK_NYETMsk_Msk (0x01UL << USB_DOEPMSK_NYETMsk_Pos) /*!< USB DOEPMSK: NYETMsk Mask */
\r
8174 /* ---------------------------------- USB_DAINT --------------------------------- */
\r
8175 #define USB_DAINT_InEpInt_Pos 0 /*!< USB DAINT: InEpInt Position */
\r
8176 #define USB_DAINT_InEpInt_Msk (0x0000ffffUL << USB_DAINT_InEpInt_Pos) /*!< USB DAINT: InEpInt Mask */
\r
8177 #define USB_DAINT_OutEPInt_Pos 16 /*!< USB DAINT: OutEPInt Position */
\r
8178 #define USB_DAINT_OutEPInt_Msk (0x0000ffffUL << USB_DAINT_OutEPInt_Pos) /*!< USB DAINT: OutEPInt Mask */
\r
8180 /* -------------------------------- USB_DAINTMSK -------------------------------- */
\r
8181 #define USB_DAINTMSK_InEpMsk_Pos 0 /*!< USB DAINTMSK: InEpMsk Position */
\r
8182 #define USB_DAINTMSK_InEpMsk_Msk (0x0000ffffUL << USB_DAINTMSK_InEpMsk_Pos) /*!< USB DAINTMSK: InEpMsk Mask */
\r
8183 #define USB_DAINTMSK_OutEpMsk_Pos 16 /*!< USB DAINTMSK: OutEpMsk Position */
\r
8184 #define USB_DAINTMSK_OutEpMsk_Msk (0x0000ffffUL << USB_DAINTMSK_OutEpMsk_Pos) /*!< USB DAINTMSK: OutEpMsk Mask */
\r
8186 /* -------------------------------- USB_DVBUSDIS -------------------------------- */
\r
8187 #define USB_DVBUSDIS_DVBUSDis_Pos 0 /*!< USB DVBUSDIS: DVBUSDis Position */
\r
8188 #define USB_DVBUSDIS_DVBUSDis_Msk (0x0000ffffUL << USB_DVBUSDIS_DVBUSDis_Pos) /*!< USB DVBUSDIS: DVBUSDis Mask */
\r
8190 /* ------------------------------- USB_DVBUSPULSE ------------------------------- */
\r
8191 #define USB_DVBUSPULSE_DVBUSPulse_Pos 0 /*!< USB DVBUSPULSE: DVBUSPulse Position */
\r
8192 #define USB_DVBUSPULSE_DVBUSPulse_Msk (0x00000fffUL << USB_DVBUSPULSE_DVBUSPulse_Pos) /*!< USB DVBUSPULSE: DVBUSPulse Mask */
\r
8194 /* ------------------------------- USB_DIEPEMPMSK ------------------------------- */
\r
8195 #define USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos 0 /*!< USB DIEPEMPMSK: InEpTxfEmpMsk Position */
\r
8196 #define USB_DIEPEMPMSK_InEpTxfEmpMsk_Msk (0x0000ffffUL << USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos) /*!< USB DIEPEMPMSK: InEpTxfEmpMsk Mask */
\r
8198 /* --------------------------------- USB_PCGCCTL -------------------------------- */
\r
8199 #define USB_PCGCCTL_StopPclk_Pos 0 /*!< USB PCGCCTL: StopPclk Position */
\r
8200 #define USB_PCGCCTL_StopPclk_Msk (0x01UL << USB_PCGCCTL_StopPclk_Pos) /*!< USB PCGCCTL: StopPclk Mask */
\r
8201 #define USB_PCGCCTL_GateHclk_Pos 1 /*!< USB PCGCCTL: GateHclk Position */
\r
8202 #define USB_PCGCCTL_GateHclk_Msk (0x01UL << USB_PCGCCTL_GateHclk_Pos) /*!< USB PCGCCTL: GateHclk Mask */
\r
8205 /* ================================================================================ */
\r
8206 /* ================ struct 'USB0_EP0' Position & Mask ================ */
\r
8207 /* ================================================================================ */
\r
8210 /* ------------------------------ USB_EP_DIEPCTL0 ----------------------------- */
\r
8211 #define USB_EP_DIEPCTL0_MPS_Pos 0 /*!< USB0_EP0 DIEPCTL0: MPS Position */
\r
8212 #define USB_EP_DIEPCTL0_MPS_Msk (0x03UL << USB_EP_DIEPCTL0_MPS_Pos) /*!< USB0_EP0 DIEPCTL0: MPS Mask */
\r
8213 #define USB_EP_DIEPCTL0_USBActEP_Pos 15 /*!< USB0_EP0 DIEPCTL0: USBActEP Position */
\r
8214 #define USB_EP_DIEPCTL0_USBActEP_Msk (0x01UL << USB_EP_DIEPCTL0_USBActEP_Pos) /*!< USB0_EP0 DIEPCTL0: USBActEP Mask */
\r
8215 #define USB_EP_DIEPCTL0_NAKSts_Pos 17 /*!< USB0_EP0 DIEPCTL0: NAKSts Position */
\r
8216 #define USB_EP_DIEPCTL0_NAKSts_Msk (0x01UL << USB_EP_DIEPCTL0_NAKSts_Pos) /*!< USB0_EP0 DIEPCTL0: NAKSts Mask */
\r
8217 #define USB_EP_DIEPCTL0_EPType_Pos 18 /*!< USB0_EP0 DIEPCTL0: EPType Position */
\r
8218 #define USB_EP_DIEPCTL0_EPType_Msk (0x03UL << USB_EP_DIEPCTL0_EPType_Pos) /*!< USB0_EP0 DIEPCTL0: EPType Mask */
\r
8219 #define USB_EP_DIEPCTL0_Stall_Pos 21 /*!< USB0_EP0 DIEPCTL0: Stall Position */
\r
8220 #define USB_EP_DIEPCTL0_Stall_Msk (0x01UL << USB_EP_DIEPCTL0_Stall_Pos) /*!< USB0_EP0 DIEPCTL0: Stall Mask */
\r
8221 #define USB_EP_DIEPCTL0_TxFNum_Pos 22 /*!< USB0_EP0 DIEPCTL0: TxFNum Position */
\r
8222 #define USB_EP_DIEPCTL0_TxFNum_Msk (0x0fUL << USB_EP_DIEPCTL0_TxFNum_Pos) /*!< USB0_EP0 DIEPCTL0: TxFNum Mask */
\r
8223 #define USB_EP_DIEPCTL0_CNAK_Pos 26 /*!< USB0_EP0 DIEPCTL0: CNAK Position */
\r
8224 #define USB_EP_DIEPCTL0_CNAK_Msk (0x01UL << USB_EP_DIEPCTL0_CNAK_Pos) /*!< USB0_EP0 DIEPCTL0: CNAK Mask */
\r
8225 #define USB_EP_DIEPCTL0_SNAK_Pos 27 /*!< USB0_EP0 DIEPCTL0: SNAK Position */
\r
8226 #define USB_EP_DIEPCTL0_SNAK_Msk (0x01UL << USB_EP_DIEPCTL0_SNAK_Pos) /*!< USB0_EP0 DIEPCTL0: SNAK Mask */
\r
8227 #define USB_EP_DIEPCTL0_EPDis_Pos 30 /*!< USB0_EP0 DIEPCTL0: EPDis Position */
\r
8228 #define USB_EP_DIEPCTL0_EPDis_Msk (0x01UL << USB_EP_DIEPCTL0_EPDis_Pos) /*!< USB0_EP0 DIEPCTL0: EPDis Mask */
\r
8229 #define USB_EP_DIEPCTL0_EPEna_Pos 31 /*!< USB0_EP0 DIEPCTL0: EPEna Position */
\r
8230 #define USB_EP_DIEPCTL0_EPEna_Msk (0x01UL << USB_EP_DIEPCTL0_EPEna_Pos) /*!< USB0_EP0 DIEPCTL0: EPEna Mask */
\r
8232 /* ------------------------------ USB_EP_DIEPINT0 ----------------------------- */
\r
8233 #define USB_EP_DIEPINT0_XferCompl_Pos 0 /*!< USB0_EP0 DIEPINT0: XferCompl Position */
\r
8234 #define USB_EP_DIEPINT0_XferCompl_Msk (0x01UL << USB_EP_DIEPINT0_XferCompl_Pos) /*!< USB0_EP0 DIEPINT0: XferCompl Mask */
\r
8235 #define USB_EP_DIEPINT0_EPDisbld_Pos 1 /*!< USB0_EP0 DIEPINT0: EPDisbld Position */
\r
8236 #define USB_EP_DIEPINT0_EPDisbld_Msk (0x01UL << USB_EP_DIEPINT0_EPDisbld_Pos) /*!< USB0_EP0 DIEPINT0: EPDisbld Mask */
\r
8237 #define USB_EP_DIEPINT0_AHBErr_Pos 2 /*!< USB0_EP0 DIEPINT0: AHBErr Position */
\r
8238 #define USB_EP_DIEPINT0_AHBErr_Msk (0x01UL << USB_EP_DIEPINT0_AHBErr_Pos) /*!< USB0_EP0 DIEPINT0: AHBErr Mask */
\r
8239 #define USB_EP_DIEPINT0_TimeOUT_Pos 3 /*!< USB0_EP0 DIEPINT0: TimeOUT Position */
\r
8240 #define USB_EP_DIEPINT0_TimeOUT_Msk (0x01UL << USB_EP_DIEPINT0_TimeOUT_Pos) /*!< USB0_EP0 DIEPINT0: TimeOUT Mask */
\r
8241 #define USB_EP_DIEPINT0_INTknTXFEmp_Pos 4 /*!< USB0_EP0 DIEPINT0: INTknTXFEmp Position */
\r
8242 #define USB_EP_DIEPINT0_INTknTXFEmp_Msk (0x01UL << USB_EP_DIEPINT0_INTknTXFEmp_Pos) /*!< USB0_EP0 DIEPINT0: INTknTXFEmp Mask */
\r
8243 #define USB_EP_DIEPINT0_INEPNakEff_Pos 6 /*!< USB0_EP0 DIEPINT0: INEPNakEff Position */
\r
8244 #define USB_EP_DIEPINT0_INEPNakEff_Msk (0x01UL << USB_EP_DIEPINT0_INEPNakEff_Pos) /*!< USB0_EP0 DIEPINT0: INEPNakEff Mask */
\r
8245 #define USB_EP_DIEPINT0_TxFEmp_Pos 7 /*!< USB0_EP0 DIEPINT0: TxFEmp Position */
\r
8246 #define USB_EP_DIEPINT0_TxFEmp_Msk (0x01UL << USB_EP_DIEPINT0_TxFEmp_Pos) /*!< USB0_EP0 DIEPINT0: TxFEmp Mask */
\r
8247 #define USB_EP_DIEPINT0_BNAIntr_Pos 9 /*!< USB0_EP0 DIEPINT0: BNAIntr Position */
\r
8248 #define USB_EP_DIEPINT0_BNAIntr_Msk (0x01UL << USB_EP_DIEPINT0_BNAIntr_Pos) /*!< USB0_EP0 DIEPINT0: BNAIntr Mask */
\r
8250 /* ----------------------------- USB_EP_DIEPTSIZ0 ----------------------------- */
\r
8251 #define USB_EP_DIEPTSIZ0_XferSize_Pos 0 /*!< USB0_EP0 DIEPTSIZ0: XferSize Position */
\r
8252 #define USB_EP_DIEPTSIZ0_XferSize_Msk (0x7fUL << USB_EP_DIEPTSIZ0_XferSize_Pos) /*!< USB0_EP0 DIEPTSIZ0: XferSize Mask */
\r
8253 #define USB_EP_DIEPTSIZ0_PktCnt_Pos 19 /*!< USB0_EP0 DIEPTSIZ0: PktCnt Position */
\r
8254 #define USB_EP_DIEPTSIZ0_PktCnt_Msk (0x03UL << USB_EP_DIEPTSIZ0_PktCnt_Pos) /*!< USB0_EP0 DIEPTSIZ0: PktCnt Mask */
\r
8256 /* ------------------------------ USB_EP_DIEPDMA0 ----------------------------- */
\r
8257 #define USB_EP_DIEPDMA0_DMAAddr_Pos 0 /*!< USB0_EP0 DIEPDMA0: DMAAddr Position */
\r
8258 #define USB_EP_DIEPDMA0_DMAAddr_Msk (0xffffffffUL << USB_EP_DIEPDMA0_DMAAddr_Pos) /*!< USB0_EP0 DIEPDMA0: DMAAddr Mask */
\r
8260 /* ------------------------------ USB_EP_DTXFSTS0 ----------------------------- */
\r
8261 #define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos 0 /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail Position */
\r
8262 #define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Msk (0x0000ffffUL << USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos) /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail Mask */
\r
8264 /* ----------------------------- USB_EP_DIEPDMAB0 ----------------------------- */
\r
8265 #define USB_EP_DIEPDMAB0_DMABufferAddr_Pos 0 /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr Position */
\r
8266 #define USB_EP_DIEPDMAB0_DMABufferAddr_Msk (0xffffffffUL << USB_EP_DIEPDMAB0_DMABufferAddr_Pos) /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr Mask */
\r
8268 /* ------------------------------ USB_EP_DOEPCTL0 ----------------------------- */
\r
8269 #define USB_EP_DOEPCTL0_MPS_Pos 0 /*!< USB0_EP0 DOEPCTL0: MPS Position */
\r
8270 #define USB_EP_DOEPCTL0_MPS_Msk (0x03UL << USB_EP_DOEPCTL0_MPS_Pos) /*!< USB0_EP0 DOEPCTL0: MPS Mask */
\r
8271 #define USB_EP_DOEPCTL0_USBActEP_Pos 15 /*!< USB0_EP0 DOEPCTL0: USBActEP Position */
\r
8272 #define USB_EP_DOEPCTL0_USBActEP_Msk (0x01UL << USB_EP_DOEPCTL0_USBActEP_Pos) /*!< USB0_EP0 DOEPCTL0: USBActEP Mask */
\r
8273 #define USB_EP_DOEPCTL0_NAKSts_Pos 17 /*!< USB0_EP0 DOEPCTL0: NAKSts Position */
\r
8274 #define USB_EP_DOEPCTL0_NAKSts_Msk (0x01UL << USB_EP_DOEPCTL0_NAKSts_Pos) /*!< USB0_EP0 DOEPCTL0: NAKSts Mask */
\r
8275 #define USB_EP_DOEPCTL0_EPType_Pos 18 /*!< USB0_EP0 DOEPCTL0: EPType Position */
\r
8276 #define USB_EP_DOEPCTL0_EPType_Msk (0x03UL << USB_EP_DOEPCTL0_EPType_Pos) /*!< USB0_EP0 DOEPCTL0: EPType Mask */
\r
8277 #define USB_EP_DOEPCTL0_Snp_Pos 20 /*!< USB0_EP0 DOEPCTL0: Snp Position */
\r
8278 #define USB_EP_DOEPCTL0_Snp_Msk (0x01UL << USB_EP_DOEPCTL0_Snp_Pos) /*!< USB0_EP0 DOEPCTL0: Snp Mask */
\r
8279 #define USB_EP_DOEPCTL0_Stall_Pos 21 /*!< USB0_EP0 DOEPCTL0: Stall Position */
\r
8280 #define USB_EP_DOEPCTL0_Stall_Msk (0x01UL << USB_EP_DOEPCTL0_Stall_Pos) /*!< USB0_EP0 DOEPCTL0: Stall Mask */
\r
8281 #define USB_EP_DOEPCTL0_CNAK_Pos 26 /*!< USB0_EP0 DOEPCTL0: CNAK Position */
\r
8282 #define USB_EP_DOEPCTL0_CNAK_Msk (0x01UL << USB_EP_DOEPCTL0_CNAK_Pos) /*!< USB0_EP0 DOEPCTL0: CNAK Mask */
\r
8283 #define USB_EP_DOEPCTL0_SNAK_Pos 27 /*!< USB0_EP0 DOEPCTL0: SNAK Position */
\r
8284 #define USB_EP_DOEPCTL0_SNAK_Msk (0x01UL << USB_EP_DOEPCTL0_SNAK_Pos) /*!< USB0_EP0 DOEPCTL0: SNAK Mask */
\r
8285 #define USB_EP_DOEPCTL0_EPDis_Pos 30 /*!< USB0_EP0 DOEPCTL0: EPDis Position */
\r
8286 #define USB_EP_DOEPCTL0_EPDis_Msk (0x01UL << USB_EP_DOEPCTL0_EPDis_Pos) /*!< USB0_EP0 DOEPCTL0: EPDis Mask */
\r
8287 #define USB_EP_DOEPCTL0_EPEna_Pos 31 /*!< USB0_EP0 DOEPCTL0: EPEna Position */
\r
8288 #define USB_EP_DOEPCTL0_EPEna_Msk (0x01UL << USB_EP_DOEPCTL0_EPEna_Pos) /*!< USB0_EP0 DOEPCTL0: EPEna Mask */
\r
8290 /* ------------------------------ USB_EP_DOEPINT0 ----------------------------- */
\r
8291 #define USB_EP_DOEPINT0_XferCompl_Pos 0 /*!< USB0_EP0 DOEPINT0: XferCompl Position */
\r
8292 #define USB_EP_DOEPINT0_XferCompl_Msk (0x01UL << USB_EP_DOEPINT0_XferCompl_Pos) /*!< USB0_EP0 DOEPINT0: XferCompl Mask */
\r
8293 #define USB_EP_DOEPINT0_EPDisbld_Pos 1 /*!< USB0_EP0 DOEPINT0: EPDisbld Position */
\r
8294 #define USB_EP_DOEPINT0_EPDisbld_Msk (0x01UL << USB_EP_DOEPINT0_EPDisbld_Pos) /*!< USB0_EP0 DOEPINT0: EPDisbld Mask */
\r
8295 #define USB_EP_DOEPINT0_AHBErr_Pos 2 /*!< USB0_EP0 DOEPINT0: AHBErr Position */
\r
8296 #define USB_EP_DOEPINT0_AHBErr_Msk (0x01UL << USB_EP_DOEPINT0_AHBErr_Pos) /*!< USB0_EP0 DOEPINT0: AHBErr Mask */
\r
8297 #define USB_EP_DOEPINT0_SetUp_Pos 3 /*!< USB0_EP0 DOEPINT0: SetUp Position */
\r
8298 #define USB_EP_DOEPINT0_SetUp_Msk (0x01UL << USB_EP_DOEPINT0_SetUp_Pos) /*!< USB0_EP0 DOEPINT0: SetUp Mask */
\r
8299 #define USB_EP_DOEPINT0_OUTTknEPdis_Pos 4 /*!< USB0_EP0 DOEPINT0: OUTTknEPdis Position */
\r
8300 #define USB_EP_DOEPINT0_OUTTknEPdis_Msk (0x01UL << USB_EP_DOEPINT0_OUTTknEPdis_Pos) /*!< USB0_EP0 DOEPINT0: OUTTknEPdis Mask */
\r
8301 #define USB_EP_DOEPINT0_StsPhseRcvd_Pos 5 /*!< USB0_EP0 DOEPINT0: StsPhseRcvd Position */
\r
8302 #define USB_EP_DOEPINT0_StsPhseRcvd_Msk (0x01UL << USB_EP_DOEPINT0_StsPhseRcvd_Pos) /*!< USB0_EP0 DOEPINT0: StsPhseRcvd Mask */
\r
8303 #define USB_EP_DOEPINT0_Back2BackSETup_Pos 6 /*!< USB0_EP0 DOEPINT0: Back2BackSETup Position */
\r
8304 #define USB_EP_DOEPINT0_Back2BackSETup_Msk (0x01UL << USB_EP_DOEPINT0_Back2BackSETup_Pos) /*!< USB0_EP0 DOEPINT0: Back2BackSETup Mask */
\r
8305 #define USB_EP_DOEPINT0_BNAIntr_Pos 9 /*!< USB0_EP0 DOEPINT0: BNAIntr Position */
\r
8306 #define USB_EP_DOEPINT0_BNAIntr_Msk (0x01UL << USB_EP_DOEPINT0_BNAIntr_Pos) /*!< USB0_EP0 DOEPINT0: BNAIntr Mask */
\r
8307 #define USB_EP_DOEPINT0_PktDrpSts_Pos 11 /*!< USB0_EP0 DOEPINT0: PktDrpSts Position */
\r
8308 #define USB_EP_DOEPINT0_PktDrpSts_Msk (0x01UL << USB_EP_DOEPINT0_PktDrpSts_Pos) /*!< USB0_EP0 DOEPINT0: PktDrpSts Mask */
\r
8309 #define USB_EP_DOEPINT0_BbleErrIntrpt_Pos 12 /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt Position */
\r
8310 #define USB_EP_DOEPINT0_BbleErrIntrpt_Msk (0x01UL << USB_EP_DOEPINT0_BbleErrIntrpt_Pos) /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt Mask */
\r
8311 #define USB_EP_DOEPINT0_NAKIntrpt_Pos 13 /*!< USB0_EP0 DOEPINT0: NAKIntrpt Position */
\r
8312 #define USB_EP_DOEPINT0_NAKIntrpt_Msk (0x01UL << USB_EP_DOEPINT0_NAKIntrpt_Pos) /*!< USB0_EP0 DOEPINT0: NAKIntrpt Mask */
\r
8313 #define USB_EP_DOEPINT0_NYETIntrpt_Pos 14 /*!< USB0_EP0 DOEPINT0: NYETIntrpt Position */
\r
8314 #define USB_EP_DOEPINT0_NYETIntrpt_Msk (0x01UL << USB_EP_DOEPINT0_NYETIntrpt_Pos) /*!< USB0_EP0 DOEPINT0: NYETIntrpt Mask */
\r
8316 /* ----------------------------- USB_EP_DOEPTSIZ0 ----------------------------- */
\r
8317 #define USB_EP_DOEPTSIZ0_XferSize_Pos 0 /*!< USB0_EP0 DOEPTSIZ0: XferSize Position */
\r
8318 #define USB_EP_DOEPTSIZ0_XferSize_Msk (0x7fUL << USB_EP_DOEPTSIZ0_XferSize_Pos) /*!< USB0_EP0 DOEPTSIZ0: XferSize Mask */
\r
8319 #define USB_EP_DOEPTSIZ0_PktCnt_Pos 19 /*!< USB0_EP0 DOEPTSIZ0: PktCnt Position */
\r
8320 #define USB_EP_DOEPTSIZ0_PktCnt_Msk (0x03UL << USB_EP_DOEPTSIZ0_PktCnt_Pos) /*!< USB0_EP0 DOEPTSIZ0: PktCnt Mask */
\r
8321 #define USB_EP_DOEPTSIZ0_SUPCnt_Pos 29 /*!< USB0_EP0 DOEPTSIZ0: SUPCnt Position */
\r
8322 #define USB_EP_DOEPTSIZ0_SUPCnt_Msk (0x03UL << USB_EP_DOEPTSIZ0_SUPCnt_Pos) /*!< USB0_EP0 DOEPTSIZ0: SUPCnt Mask */
\r
8324 /* ------------------------------ USB_EP_DOEPDMA0 ----------------------------- */
\r
8325 #define USB_EP_DOEPDMA0_DMAAddr_Pos 0 /*!< USB0_EP0 DOEPDMA0: DMAAddr Position */
\r
8326 #define USB_EP_DOEPDMA0_DMAAddr_Msk (0xffffffffUL << USB_EP_DOEPDMA0_DMAAddr_Pos) /*!< USB0_EP0 DOEPDMA0: DMAAddr Mask */
\r
8328 /* ----------------------------- USB_EP_DOEPDMAB0 ----------------------------- */
\r
8329 #define USB_EP_DOEPDMAB0_DMABufferAddr_Pos 0 /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr Position */
\r
8330 #define USB_EP_DOEPDMAB0_DMABufferAddr_Msk (0xffffffffUL << USB_EP_DOEPDMAB0_DMABufferAddr_Pos) /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr Mask */
\r
8333 /* ================================================================================ */
\r
8334 /* ================ Group 'USB_EP' Position & Mask ================ */
\r
8335 /* ================================================================================ */
\r
8338 /* --------------------------- USB_EP_DIEPCTL_ISOCONT --------------------------- */
\r
8339 #define USB_EP_DIEPCTL_ISOCONT_MPS_Pos 0 /*!< USB_EP DIEPCTL_ISOCONT: MPS Position */
\r
8340 #define USB_EP_DIEPCTL_ISOCONT_MPS_Msk (0x000007ffUL << USB_EP_DIEPCTL_ISOCONT_MPS_Pos) /*!< USB_EP DIEPCTL_ISOCONT: MPS Mask */
\r
8341 #define USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos 15 /*!< USB_EP DIEPCTL_ISOCONT: USBActEP Position */
\r
8342 #define USB_EP_DIEPCTL_ISOCONT_USBActEP_Msk (0x01UL << USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos) /*!< USB_EP DIEPCTL_ISOCONT: USBActEP Mask */
\r
8343 #define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos 16 /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum Position */
\r
8344 #define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Msk (0x01UL << USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos) /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum Mask */
\r
8345 #define USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos 17 /*!< USB_EP DIEPCTL_ISOCONT: NAKSts Position */
\r
8346 #define USB_EP_DIEPCTL_ISOCONT_NAKSts_Msk (0x01UL << USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos) /*!< USB_EP DIEPCTL_ISOCONT: NAKSts Mask */
\r
8347 #define USB_EP_DIEPCTL_ISOCONT_EPType_Pos 18 /*!< USB_EP DIEPCTL_ISOCONT: EPType Position */
\r
8348 #define USB_EP_DIEPCTL_ISOCONT_EPType_Msk (0x03UL << USB_EP_DIEPCTL_ISOCONT_EPType_Pos) /*!< USB_EP DIEPCTL_ISOCONT: EPType Mask */
\r
8349 #define USB_EP_DIEPCTL_ISOCONT_Snp_Pos 20 /*!< USB_EP DIEPCTL_ISOCONT: Snp Position */
\r
8350 #define USB_EP_DIEPCTL_ISOCONT_Snp_Msk (0x01UL << USB_EP_DIEPCTL_ISOCONT_Snp_Pos) /*!< USB_EP DIEPCTL_ISOCONT: Snp Mask */
\r
8351 #define USB_EP_DIEPCTL_ISOCONT_Stall_Pos 21 /*!< USB_EP DIEPCTL_ISOCONT: Stall Position */
\r
8352 #define USB_EP_DIEPCTL_ISOCONT_Stall_Msk (0x01UL << USB_EP_DIEPCTL_ISOCONT_Stall_Pos) /*!< USB_EP DIEPCTL_ISOCONT: Stall Mask */
\r
8353 #define USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos 22 /*!< USB_EP DIEPCTL_ISOCONT: TxFNum Position */
\r
8354 #define USB_EP_DIEPCTL_ISOCONT_TxFNum_Msk (0x0fUL << USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos) /*!< USB_EP DIEPCTL_ISOCONT: TxFNum Mask */
\r
8355 #define USB_EP_DIEPCTL_ISOCONT_CNAK_Pos 26 /*!< USB_EP DIEPCTL_ISOCONT: CNAK Position */
\r
8356 #define USB_EP_DIEPCTL_ISOCONT_CNAK_Msk (0x01UL << USB_EP_DIEPCTL_ISOCONT_CNAK_Pos) /*!< USB_EP DIEPCTL_ISOCONT: CNAK Mask */
\r
8357 #define USB_EP_DIEPCTL_ISOCONT_SNAK_Pos 27 /*!< USB_EP DIEPCTL_ISOCONT: SNAK Position */
\r
8358 #define USB_EP_DIEPCTL_ISOCONT_SNAK_Msk (0x01UL << USB_EP_DIEPCTL_ISOCONT_SNAK_Pos) /*!< USB_EP DIEPCTL_ISOCONT: SNAK Mask */
\r
8359 #define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos 28 /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr Position */
\r
8360 #define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Msk (0x01UL << USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos) /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr Mask */
\r
8361 #define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos 29 /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr Position */
\r
8362 #define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Msk (0x01UL << USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos) /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr Mask */
\r
8363 #define USB_EP_DIEPCTL_ISOCONT_EPDis_Pos 30 /*!< USB_EP DIEPCTL_ISOCONT: EPDis Position */
\r
8364 #define USB_EP_DIEPCTL_ISOCONT_EPDis_Msk (0x01UL << USB_EP_DIEPCTL_ISOCONT_EPDis_Pos) /*!< USB_EP DIEPCTL_ISOCONT: EPDis Mask */
\r
8365 #define USB_EP_DIEPCTL_ISOCONT_EPEna_Pos 31 /*!< USB_EP DIEPCTL_ISOCONT: EPEna Position */
\r
8366 #define USB_EP_DIEPCTL_ISOCONT_EPEna_Msk (0x01UL << USB_EP_DIEPCTL_ISOCONT_EPEna_Pos) /*!< USB_EP DIEPCTL_ISOCONT: EPEna Mask */
\r
8368 /* --------------------------- USB_EP_DIEPCTL_INTBULK --------------------------- */
\r
8369 #define USB_EP_DIEPCTL_INTBULK_MPS_Pos 0 /*!< USB_EP DIEPCTL_INTBULK: MPS Position */
\r
8370 #define USB_EP_DIEPCTL_INTBULK_MPS_Msk (0x000007ffUL << USB_EP_DIEPCTL_INTBULK_MPS_Pos) /*!< USB_EP DIEPCTL_INTBULK: MPS Mask */
\r
8371 #define USB_EP_DIEPCTL_INTBULK_USBActEP_Pos 15 /*!< USB_EP DIEPCTL_INTBULK: USBActEP Position */
\r
8372 #define USB_EP_DIEPCTL_INTBULK_USBActEP_Msk (0x01UL << USB_EP_DIEPCTL_INTBULK_USBActEP_Pos) /*!< USB_EP DIEPCTL_INTBULK: USBActEP Mask */
\r
8373 #define USB_EP_DIEPCTL_INTBULK_DPID_Pos 16 /*!< USB_EP DIEPCTL_INTBULK: DPID Position */
\r
8374 #define USB_EP_DIEPCTL_INTBULK_DPID_Msk (0x01UL << USB_EP_DIEPCTL_INTBULK_DPID_Pos) /*!< USB_EP DIEPCTL_INTBULK: DPID Mask */
\r
8375 #define USB_EP_DIEPCTL_INTBULK_NAKSts_Pos 17 /*!< USB_EP DIEPCTL_INTBULK: NAKSts Position */
\r
8376 #define USB_EP_DIEPCTL_INTBULK_NAKSts_Msk (0x01UL << USB_EP_DIEPCTL_INTBULK_NAKSts_Pos) /*!< USB_EP DIEPCTL_INTBULK: NAKSts Mask */
\r
8377 #define USB_EP_DIEPCTL_INTBULK_EPType_Pos 18 /*!< USB_EP DIEPCTL_INTBULK: EPType Position */
\r
8378 #define USB_EP_DIEPCTL_INTBULK_EPType_Msk (0x03UL << USB_EP_DIEPCTL_INTBULK_EPType_Pos) /*!< USB_EP DIEPCTL_INTBULK: EPType Mask */
\r
8379 #define USB_EP_DIEPCTL_INTBULK_Snp_Pos 20 /*!< USB_EP DIEPCTL_INTBULK: Snp Position */
\r
8380 #define USB_EP_DIEPCTL_INTBULK_Snp_Msk (0x01UL << USB_EP_DIEPCTL_INTBULK_Snp_Pos) /*!< USB_EP DIEPCTL_INTBULK: Snp Mask */
\r
8381 #define USB_EP_DIEPCTL_INTBULK_Stall_Pos 21 /*!< USB_EP DIEPCTL_INTBULK: Stall Position */
\r
8382 #define USB_EP_DIEPCTL_INTBULK_Stall_Msk (0x01UL << USB_EP_DIEPCTL_INTBULK_Stall_Pos) /*!< USB_EP DIEPCTL_INTBULK: Stall Mask */
\r
8383 #define USB_EP_DIEPCTL_INTBULK_TxFNum_Pos 22 /*!< USB_EP DIEPCTL_INTBULK: TxFNum Position */
\r
8384 #define USB_EP_DIEPCTL_INTBULK_TxFNum_Msk (0x0fUL << USB_EP_DIEPCTL_INTBULK_TxFNum_Pos) /*!< USB_EP DIEPCTL_INTBULK: TxFNum Mask */
\r
8385 #define USB_EP_DIEPCTL_INTBULK_CNAK_Pos 26 /*!< USB_EP DIEPCTL_INTBULK: CNAK Position */
\r
8386 #define USB_EP_DIEPCTL_INTBULK_CNAK_Msk (0x01UL << USB_EP_DIEPCTL_INTBULK_CNAK_Pos) /*!< USB_EP DIEPCTL_INTBULK: CNAK Mask */
\r
8387 #define USB_EP_DIEPCTL_INTBULK_SNAK_Pos 27 /*!< USB_EP DIEPCTL_INTBULK: SNAK Position */
\r
8388 #define USB_EP_DIEPCTL_INTBULK_SNAK_Msk (0x01UL << USB_EP_DIEPCTL_INTBULK_SNAK_Pos) /*!< USB_EP DIEPCTL_INTBULK: SNAK Mask */
\r
8389 #define USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos 28 /*!< USB_EP DIEPCTL_INTBULK: SetD0PID Position */
\r
8390 #define USB_EP_DIEPCTL_INTBULK_SetD0PID_Msk (0x01UL << USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos) /*!< USB_EP DIEPCTL_INTBULK: SetD0PID Mask */
\r
8391 #define USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos 29 /*!< USB_EP DIEPCTL_INTBULK: SetD1PID Position */
\r
8392 #define USB_EP_DIEPCTL_INTBULK_SetD1PID_Msk (0x01UL << USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos) /*!< USB_EP DIEPCTL_INTBULK: SetD1PID Mask */
\r
8393 #define USB_EP_DIEPCTL_INTBULK_EPDis_Pos 30 /*!< USB_EP DIEPCTL_INTBULK: EPDis Position */
\r
8394 #define USB_EP_DIEPCTL_INTBULK_EPDis_Msk (0x01UL << USB_EP_DIEPCTL_INTBULK_EPDis_Pos) /*!< USB_EP DIEPCTL_INTBULK: EPDis Mask */
\r
8395 #define USB_EP_DIEPCTL_INTBULK_EPEna_Pos 31 /*!< USB_EP DIEPCTL_INTBULK: EPEna Position */
\r
8396 #define USB_EP_DIEPCTL_INTBULK_EPEna_Msk (0x01UL << USB_EP_DIEPCTL_INTBULK_EPEna_Pos) /*!< USB_EP DIEPCTL_INTBULK: EPEna Mask */
\r
8398 /* ------------------------------- USB_EP_DIEPINT ------------------------------- */
\r
8399 #define USB_EP_DIEPINT_XferCompl_Pos 0 /*!< USB_EP DIEPINT: XferCompl Position */
\r
8400 #define USB_EP_DIEPINT_XferCompl_Msk (0x01UL << USB_EP_DIEPINT_XferCompl_Pos) /*!< USB_EP DIEPINT: XferCompl Mask */
\r
8401 #define USB_EP_DIEPINT_EPDisbld_Pos 1 /*!< USB_EP DIEPINT: EPDisbld Position */
\r
8402 #define USB_EP_DIEPINT_EPDisbld_Msk (0x01UL << USB_EP_DIEPINT_EPDisbld_Pos) /*!< USB_EP DIEPINT: EPDisbld Mask */
\r
8403 #define USB_EP_DIEPINT_AHBErr_Pos 2 /*!< USB_EP DIEPINT: AHBErr Position */
\r
8404 #define USB_EP_DIEPINT_AHBErr_Msk (0x01UL << USB_EP_DIEPINT_AHBErr_Pos) /*!< USB_EP DIEPINT: AHBErr Mask */
\r
8405 #define USB_EP_DIEPINT_TimeOUT_Pos 3 /*!< USB_EP DIEPINT: TimeOUT Position */
\r
8406 #define USB_EP_DIEPINT_TimeOUT_Msk (0x01UL << USB_EP_DIEPINT_TimeOUT_Pos) /*!< USB_EP DIEPINT: TimeOUT Mask */
\r
8407 #define USB_EP_DIEPINT_INTknTXFEmp_Pos 4 /*!< USB_EP DIEPINT: INTknTXFEmp Position */
\r
8408 #define USB_EP_DIEPINT_INTknTXFEmp_Msk (0x01UL << USB_EP_DIEPINT_INTknTXFEmp_Pos) /*!< USB_EP DIEPINT: INTknTXFEmp Mask */
\r
8409 #define USB_EP_DIEPINT_INEPNakEff_Pos 6 /*!< USB_EP DIEPINT: INEPNakEff Position */
\r
8410 #define USB_EP_DIEPINT_INEPNakEff_Msk (0x01UL << USB_EP_DIEPINT_INEPNakEff_Pos) /*!< USB_EP DIEPINT: INEPNakEff Mask */
\r
8411 #define USB_EP_DIEPINT_TxFEmp_Pos 7 /*!< USB_EP DIEPINT: TxFEmp Position */
\r
8412 #define USB_EP_DIEPINT_TxFEmp_Msk (0x01UL << USB_EP_DIEPINT_TxFEmp_Pos) /*!< USB_EP DIEPINT: TxFEmp Mask */
\r
8413 #define USB_EP_DIEPINT_BNAIntr_Pos 9 /*!< USB_EP DIEPINT: BNAIntr Position */
\r
8414 #define USB_EP_DIEPINT_BNAIntr_Msk (0x01UL << USB_EP_DIEPINT_BNAIntr_Pos) /*!< USB_EP DIEPINT: BNAIntr Mask */
\r
8416 /* ------------------------------- USB_EP_DIEPTSIZ ------------------------------ */
\r
8417 #define USB_EP_DIEPTSIZ_XferSize_Pos 0 /*!< USB_EP DIEPTSIZ: XferSize Position */
\r
8418 #define USB_EP_DIEPTSIZ_XferSize_Msk (0x0007ffffUL << USB_EP_DIEPTSIZ_XferSize_Pos) /*!< USB_EP DIEPTSIZ: XferSize Mask */
\r
8419 #define USB_EP_DIEPTSIZ_PktCnt_Pos 19 /*!< USB_EP DIEPTSIZ: PktCnt Position */
\r
8420 #define USB_EP_DIEPTSIZ_PktCnt_Msk (0x000003ffUL << USB_EP_DIEPTSIZ_PktCnt_Pos) /*!< USB_EP DIEPTSIZ: PktCnt Mask */
\r
8422 /* ------------------------------- USB_EP_DIEPDMA ------------------------------- */
\r
8423 #define USB_EP_DIEPDMA_DMAAddr_Pos 0 /*!< USB_EP DIEPDMA: DMAAddr Position */
\r
8424 #define USB_EP_DIEPDMA_DMAAddr_Msk (0xffffffffUL << USB_EP_DIEPDMA_DMAAddr_Pos) /*!< USB_EP DIEPDMA: DMAAddr Mask */
\r
8426 /* ------------------------------- USB_EP_DTXFSTS ------------------------------- */
\r
8427 #define USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos 0 /*!< USB_EP DTXFSTS: INEPTxFSpcAvail Position */
\r
8428 #define USB_EP_DTXFSTS_INEPTxFSpcAvail_Msk (0x0000ffffUL << USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos) /*!< USB_EP DTXFSTS: INEPTxFSpcAvail Mask */
\r
8430 /* ------------------------------- USB_EP_DIEPDMAB ------------------------------ */
\r
8431 #define USB_EP_DIEPDMAB_DMABufferAddr_Pos 0 /*!< USB_EP DIEPDMAB: DMABufferAddr Position */
\r
8432 #define USB_EP_DIEPDMAB_DMABufferAddr_Msk (0xffffffffUL << USB_EP_DIEPDMAB_DMABufferAddr_Pos) /*!< USB_EP DIEPDMAB: DMABufferAddr Mask */
\r
8434 /* --------------------------- USB_EP_DOEPCTL_ISOCONT --------------------------- */
\r
8435 #define USB_EP_DOEPCTL_ISOCONT_MPS_Pos 0 /*!< USB_EP DOEPCTL_ISOCONT: MPS Position */
\r
8436 #define USB_EP_DOEPCTL_ISOCONT_MPS_Msk (0x000007ffUL << USB_EP_DOEPCTL_ISOCONT_MPS_Pos) /*!< USB_EP DOEPCTL_ISOCONT: MPS Mask */
\r
8437 #define USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos 15 /*!< USB_EP DOEPCTL_ISOCONT: USBActEP Position */
\r
8438 #define USB_EP_DOEPCTL_ISOCONT_USBActEP_Msk (0x01UL << USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos) /*!< USB_EP DOEPCTL_ISOCONT: USBActEP Mask */
\r
8439 #define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos 16 /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum Position */
\r
8440 #define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Msk (0x01UL << USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos) /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum Mask */
\r
8441 #define USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos 17 /*!< USB_EP DOEPCTL_ISOCONT: NAKSts Position */
\r
8442 #define USB_EP_DOEPCTL_ISOCONT_NAKSts_Msk (0x01UL << USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos) /*!< USB_EP DOEPCTL_ISOCONT: NAKSts Mask */
\r
8443 #define USB_EP_DOEPCTL_ISOCONT_EPType_Pos 18 /*!< USB_EP DOEPCTL_ISOCONT: EPType Position */
\r
8444 #define USB_EP_DOEPCTL_ISOCONT_EPType_Msk (0x03UL << USB_EP_DOEPCTL_ISOCONT_EPType_Pos) /*!< USB_EP DOEPCTL_ISOCONT: EPType Mask */
\r
8445 #define USB_EP_DOEPCTL_ISOCONT_Snp_Pos 20 /*!< USB_EP DOEPCTL_ISOCONT: Snp Position */
\r
8446 #define USB_EP_DOEPCTL_ISOCONT_Snp_Msk (0x01UL << USB_EP_DOEPCTL_ISOCONT_Snp_Pos) /*!< USB_EP DOEPCTL_ISOCONT: Snp Mask */
\r
8447 #define USB_EP_DOEPCTL_ISOCONT_Stall_Pos 21 /*!< USB_EP DOEPCTL_ISOCONT: Stall Position */
\r
8448 #define USB_EP_DOEPCTL_ISOCONT_Stall_Msk (0x01UL << USB_EP_DOEPCTL_ISOCONT_Stall_Pos) /*!< USB_EP DOEPCTL_ISOCONT: Stall Mask */
\r
8449 #define USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos 22 /*!< USB_EP DOEPCTL_ISOCONT: TxFNum Position */
\r
8450 #define USB_EP_DOEPCTL_ISOCONT_TxFNum_Msk (0x0fUL << USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos) /*!< USB_EP DOEPCTL_ISOCONT: TxFNum Mask */
\r
8451 #define USB_EP_DOEPCTL_ISOCONT_CNAK_Pos 26 /*!< USB_EP DOEPCTL_ISOCONT: CNAK Position */
\r
8452 #define USB_EP_DOEPCTL_ISOCONT_CNAK_Msk (0x01UL << USB_EP_DOEPCTL_ISOCONT_CNAK_Pos) /*!< USB_EP DOEPCTL_ISOCONT: CNAK Mask */
\r
8453 #define USB_EP_DOEPCTL_ISOCONT_SNAK_Pos 27 /*!< USB_EP DOEPCTL_ISOCONT: SNAK Position */
\r
8454 #define USB_EP_DOEPCTL_ISOCONT_SNAK_Msk (0x01UL << USB_EP_DOEPCTL_ISOCONT_SNAK_Pos) /*!< USB_EP DOEPCTL_ISOCONT: SNAK Mask */
\r
8455 #define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos 28 /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr Position */
\r
8456 #define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Msk (0x01UL << USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos) /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr Mask */
\r
8457 #define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos 29 /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr Position */
\r
8458 #define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Msk (0x01UL << USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos) /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr Mask */
\r
8459 #define USB_EP_DOEPCTL_ISOCONT_EPDis_Pos 30 /*!< USB_EP DOEPCTL_ISOCONT: EPDis Position */
\r
8460 #define USB_EP_DOEPCTL_ISOCONT_EPDis_Msk (0x01UL << USB_EP_DOEPCTL_ISOCONT_EPDis_Pos) /*!< USB_EP DOEPCTL_ISOCONT: EPDis Mask */
\r
8461 #define USB_EP_DOEPCTL_ISOCONT_EPEna_Pos 31 /*!< USB_EP DOEPCTL_ISOCONT: EPEna Position */
\r
8462 #define USB_EP_DOEPCTL_ISOCONT_EPEna_Msk (0x01UL << USB_EP_DOEPCTL_ISOCONT_EPEna_Pos) /*!< USB_EP DOEPCTL_ISOCONT: EPEna Mask */
\r
8464 /* --------------------------- USB_EP_DOEPCTL_INTBULK --------------------------- */
\r
8465 #define USB_EP_DOEPCTL_INTBULK_MPS_Pos 0 /*!< USB_EP DOEPCTL_INTBULK: MPS Position */
\r
8466 #define USB_EP_DOEPCTL_INTBULK_MPS_Msk (0x000007ffUL << USB_EP_DOEPCTL_INTBULK_MPS_Pos) /*!< USB_EP DOEPCTL_INTBULK: MPS Mask */
\r
8467 #define USB_EP_DOEPCTL_INTBULK_USBActEP_Pos 15 /*!< USB_EP DOEPCTL_INTBULK: USBActEP Position */
\r
8468 #define USB_EP_DOEPCTL_INTBULK_USBActEP_Msk (0x01UL << USB_EP_DOEPCTL_INTBULK_USBActEP_Pos) /*!< USB_EP DOEPCTL_INTBULK: USBActEP Mask */
\r
8469 #define USB_EP_DOEPCTL_INTBULK_DPID_Pos 16 /*!< USB_EP DOEPCTL_INTBULK: DPID Position */
\r
8470 #define USB_EP_DOEPCTL_INTBULK_DPID_Msk (0x01UL << USB_EP_DOEPCTL_INTBULK_DPID_Pos) /*!< USB_EP DOEPCTL_INTBULK: DPID Mask */
\r
8471 #define USB_EP_DOEPCTL_INTBULK_NAKSts_Pos 17 /*!< USB_EP DOEPCTL_INTBULK: NAKSts Position */
\r
8472 #define USB_EP_DOEPCTL_INTBULK_NAKSts_Msk (0x01UL << USB_EP_DOEPCTL_INTBULK_NAKSts_Pos) /*!< USB_EP DOEPCTL_INTBULK: NAKSts Mask */
\r
8473 #define USB_EP_DOEPCTL_INTBULK_EPType_Pos 18 /*!< USB_EP DOEPCTL_INTBULK: EPType Position */
\r
8474 #define USB_EP_DOEPCTL_INTBULK_EPType_Msk (0x03UL << USB_EP_DOEPCTL_INTBULK_EPType_Pos) /*!< USB_EP DOEPCTL_INTBULK: EPType Mask */
\r
8475 #define USB_EP_DOEPCTL_INTBULK_Snp_Pos 20 /*!< USB_EP DOEPCTL_INTBULK: Snp Position */
\r
8476 #define USB_EP_DOEPCTL_INTBULK_Snp_Msk (0x01UL << USB_EP_DOEPCTL_INTBULK_Snp_Pos) /*!< USB_EP DOEPCTL_INTBULK: Snp Mask */
\r
8477 #define USB_EP_DOEPCTL_INTBULK_Stall_Pos 21 /*!< USB_EP DOEPCTL_INTBULK: Stall Position */
\r
8478 #define USB_EP_DOEPCTL_INTBULK_Stall_Msk (0x01UL << USB_EP_DOEPCTL_INTBULK_Stall_Pos) /*!< USB_EP DOEPCTL_INTBULK: Stall Mask */
\r
8479 #define USB_EP_DOEPCTL_INTBULK_TxFNum_Pos 22 /*!< USB_EP DOEPCTL_INTBULK: TxFNum Position */
\r
8480 #define USB_EP_DOEPCTL_INTBULK_TxFNum_Msk (0x0fUL << USB_EP_DOEPCTL_INTBULK_TxFNum_Pos) /*!< USB_EP DOEPCTL_INTBULK: TxFNum Mask */
\r
8481 #define USB_EP_DOEPCTL_INTBULK_CNAK_Pos 26 /*!< USB_EP DOEPCTL_INTBULK: CNAK Position */
\r
8482 #define USB_EP_DOEPCTL_INTBULK_CNAK_Msk (0x01UL << USB_EP_DOEPCTL_INTBULK_CNAK_Pos) /*!< USB_EP DOEPCTL_INTBULK: CNAK Mask */
\r
8483 #define USB_EP_DOEPCTL_INTBULK_SNAK_Pos 27 /*!< USB_EP DOEPCTL_INTBULK: SNAK Position */
\r
8484 #define USB_EP_DOEPCTL_INTBULK_SNAK_Msk (0x01UL << USB_EP_DOEPCTL_INTBULK_SNAK_Pos) /*!< USB_EP DOEPCTL_INTBULK: SNAK Mask */
\r
8485 #define USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos 28 /*!< USB_EP DOEPCTL_INTBULK: SetD0PID Position */
\r
8486 #define USB_EP_DOEPCTL_INTBULK_SetD0PID_Msk (0x01UL << USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos) /*!< USB_EP DOEPCTL_INTBULK: SetD0PID Mask */
\r
8487 #define USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos 29 /*!< USB_EP DOEPCTL_INTBULK: SetD1PID Position */
\r
8488 #define USB_EP_DOEPCTL_INTBULK_SetD1PID_Msk (0x01UL << USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos) /*!< USB_EP DOEPCTL_INTBULK: SetD1PID Mask */
\r
8489 #define USB_EP_DOEPCTL_INTBULK_EPDis_Pos 30 /*!< USB_EP DOEPCTL_INTBULK: EPDis Position */
\r
8490 #define USB_EP_DOEPCTL_INTBULK_EPDis_Msk (0x01UL << USB_EP_DOEPCTL_INTBULK_EPDis_Pos) /*!< USB_EP DOEPCTL_INTBULK: EPDis Mask */
\r
8491 #define USB_EP_DOEPCTL_INTBULK_EPEna_Pos 31 /*!< USB_EP DOEPCTL_INTBULK: EPEna Position */
\r
8492 #define USB_EP_DOEPCTL_INTBULK_EPEna_Msk (0x01UL << USB_EP_DOEPCTL_INTBULK_EPEna_Pos) /*!< USB_EP DOEPCTL_INTBULK: EPEna Mask */
\r
8494 /* ------------------------------- USB_EP_DOEPINT ------------------------------- */
\r
8495 #define USB_EP_DOEPINT_XferCompl_Pos 0 /*!< USB_EP DOEPINT: XferCompl Position */
\r
8496 #define USB_EP_DOEPINT_XferCompl_Msk (0x01UL << USB_EP_DOEPINT_XferCompl_Pos) /*!< USB_EP DOEPINT: XferCompl Mask */
\r
8497 #define USB_EP_DOEPINT_EPDisbld_Pos 1 /*!< USB_EP DOEPINT: EPDisbld Position */
\r
8498 #define USB_EP_DOEPINT_EPDisbld_Msk (0x01UL << USB_EP_DOEPINT_EPDisbld_Pos) /*!< USB_EP DOEPINT: EPDisbld Mask */
\r
8499 #define USB_EP_DOEPINT_AHBErr_Pos 2 /*!< USB_EP DOEPINT: AHBErr Position */
\r
8500 #define USB_EP_DOEPINT_AHBErr_Msk (0x01UL << USB_EP_DOEPINT_AHBErr_Pos) /*!< USB_EP DOEPINT: AHBErr Mask */
\r
8501 #define USB_EP_DOEPINT_SetUp_Pos 3 /*!< USB_EP DOEPINT: SetUp Position */
\r
8502 #define USB_EP_DOEPINT_SetUp_Msk (0x01UL << USB_EP_DOEPINT_SetUp_Pos) /*!< USB_EP DOEPINT: SetUp Mask */
\r
8503 #define USB_EP_DOEPINT_OUTTknEPdis_Pos 4 /*!< USB_EP DOEPINT: OUTTknEPdis Position */
\r
8504 #define USB_EP_DOEPINT_OUTTknEPdis_Msk (0x01UL << USB_EP_DOEPINT_OUTTknEPdis_Pos) /*!< USB_EP DOEPINT: OUTTknEPdis Mask */
\r
8505 #define USB_EP_DOEPINT_StsPhseRcvd_Pos 5 /*!< USB_EP DOEPINT: StsPhseRcvd Position */
\r
8506 #define USB_EP_DOEPINT_StsPhseRcvd_Msk (0x01UL << USB_EP_DOEPINT_StsPhseRcvd_Pos) /*!< USB_EP DOEPINT: StsPhseRcvd Mask */
\r
8507 #define USB_EP_DOEPINT_Back2BackSETup_Pos 6 /*!< USB_EP DOEPINT: Back2BackSETup Position */
\r
8508 #define USB_EP_DOEPINT_Back2BackSETup_Msk (0x01UL << USB_EP_DOEPINT_Back2BackSETup_Pos) /*!< USB_EP DOEPINT: Back2BackSETup Mask */
\r
8509 #define USB_EP_DOEPINT_BNAIntr_Pos 9 /*!< USB_EP DOEPINT: BNAIntr Position */
\r
8510 #define USB_EP_DOEPINT_BNAIntr_Msk (0x01UL << USB_EP_DOEPINT_BNAIntr_Pos) /*!< USB_EP DOEPINT: BNAIntr Mask */
\r
8511 #define USB_EP_DOEPINT_PktDrpSts_Pos 11 /*!< USB_EP DOEPINT: PktDrpSts Position */
\r
8512 #define USB_EP_DOEPINT_PktDrpSts_Msk (0x01UL << USB_EP_DOEPINT_PktDrpSts_Pos) /*!< USB_EP DOEPINT: PktDrpSts Mask */
\r
8513 #define USB_EP_DOEPINT_BbleErrIntrpt_Pos 12 /*!< USB_EP DOEPINT: BbleErrIntrpt Position */
\r
8514 #define USB_EP_DOEPINT_BbleErrIntrpt_Msk (0x01UL << USB_EP_DOEPINT_BbleErrIntrpt_Pos) /*!< USB_EP DOEPINT: BbleErrIntrpt Mask */
\r
8515 #define USB_EP_DOEPINT_NAKIntrpt_Pos 13 /*!< USB_EP DOEPINT: NAKIntrpt Position */
\r
8516 #define USB_EP_DOEPINT_NAKIntrpt_Msk (0x01UL << USB_EP_DOEPINT_NAKIntrpt_Pos) /*!< USB_EP DOEPINT: NAKIntrpt Mask */
\r
8517 #define USB_EP_DOEPINT_NYETIntrpt_Pos 14 /*!< USB_EP DOEPINT: NYETIntrpt Position */
\r
8518 #define USB_EP_DOEPINT_NYETIntrpt_Msk (0x01UL << USB_EP_DOEPINT_NYETIntrpt_Pos) /*!< USB_EP DOEPINT: NYETIntrpt Mask */
\r
8520 /* ----------------------------- USB_EP_DOEPTSIZ_ISO ---------------------------- */
\r
8521 #define USB_EP_DOEPTSIZ_ISO_XferSize_Pos 0 /*!< USB_EP DOEPTSIZ_ISO: XferSize Position */
\r
8522 #define USB_EP_DOEPTSIZ_ISO_XferSize_Msk (0x0007ffffUL << USB_EP_DOEPTSIZ_ISO_XferSize_Pos) /*!< USB_EP DOEPTSIZ_ISO: XferSize Mask */
\r
8523 #define USB_EP_DOEPTSIZ_ISO_PktCnt_Pos 19 /*!< USB_EP DOEPTSIZ_ISO: PktCnt Position */
\r
8524 #define USB_EP_DOEPTSIZ_ISO_PktCnt_Msk (0x000003ffUL << USB_EP_DOEPTSIZ_ISO_PktCnt_Pos) /*!< USB_EP DOEPTSIZ_ISO: PktCnt Mask */
\r
8525 #define USB_EP_DOEPTSIZ_ISO_RxDPID_Pos 29 /*!< USB_EP DOEPTSIZ_ISO: RxDPID Position */
\r
8526 #define USB_EP_DOEPTSIZ_ISO_RxDPID_Msk (0x03UL << USB_EP_DOEPTSIZ_ISO_RxDPID_Pos) /*!< USB_EP DOEPTSIZ_ISO: RxDPID Mask */
\r
8528 /* --------------------------- USB_EP_DOEPTSIZ_CONTROL -------------------------- */
\r
8529 #define USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos 0 /*!< USB_EP DOEPTSIZ_CONTROL: XferSize Position */
\r
8530 #define USB_EP_DOEPTSIZ_CONTROL_XferSize_Msk (0x0007ffffUL << USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos) /*!< USB_EP DOEPTSIZ_CONTROL: XferSize Mask */
\r
8531 #define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos 19 /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt Position */
\r
8532 #define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Msk (0x000003ffUL << USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos) /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt Mask */
\r
8533 #define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos 29 /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt Position */
\r
8534 #define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Msk (0x03UL << USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos) /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt Mask */
\r
8536 /* ------------------------------- USB_EP_DOEPDMA ------------------------------- */
\r
8537 #define USB_EP_DOEPDMA_DMAAddr_Pos 0 /*!< USB_EP DOEPDMA: DMAAddr Position */
\r
8538 #define USB_EP_DOEPDMA_DMAAddr_Msk (0xffffffffUL << USB_EP_DOEPDMA_DMAAddr_Pos) /*!< USB_EP DOEPDMA: DMAAddr Mask */
\r
8540 /* ------------------------------- USB_EP_DOEPDMAB ------------------------------ */
\r
8541 #define USB_EP_DOEPDMAB_DMABufferAddr_Pos 0 /*!< USB_EP DOEPDMAB: DMABufferAddr Position */
\r
8542 #define USB_EP_DOEPDMAB_DMABufferAddr_Msk (0xffffffffUL << USB_EP_DOEPDMAB_DMABufferAddr_Pos) /*!< USB_EP DOEPDMAB: DMABufferAddr Mask */
\r
8545 /* ================================================================================ */
\r
8546 /* ================ Group 'USB_CH' Position & Mask ================ */
\r
8547 /* ================================================================================ */
\r
8550 /* -------------------------------- USB_CH_HCCHAR ------------------------------- */
\r
8551 #define USB_CH_HCCHAR_MPS_Pos 0 /*!< USB_CH HCCHAR: MPS Position */
\r
8552 #define USB_CH_HCCHAR_MPS_Msk (0x000007ffUL << USB_CH_HCCHAR_MPS_Pos) /*!< USB_CH HCCHAR: MPS Mask */
\r
8553 #define USB_CH_HCCHAR_EPNum_Pos 11 /*!< USB_CH HCCHAR: EPNum Position */
\r
8554 #define USB_CH_HCCHAR_EPNum_Msk (0x0fUL << USB_CH_HCCHAR_EPNum_Pos) /*!< USB_CH HCCHAR: EPNum Mask */
\r
8555 #define USB_CH_HCCHAR_EPDir_Pos 15 /*!< USB_CH HCCHAR: EPDir Position */
\r
8556 #define USB_CH_HCCHAR_EPDir_Msk (0x01UL << USB_CH_HCCHAR_EPDir_Pos) /*!< USB_CH HCCHAR: EPDir Mask */
\r
8557 #define USB_CH_HCCHAR_EPType_Pos 18 /*!< USB_CH HCCHAR: EPType Position */
\r
8558 #define USB_CH_HCCHAR_EPType_Msk (0x03UL << USB_CH_HCCHAR_EPType_Pos) /*!< USB_CH HCCHAR: EPType Mask */
\r
8559 #define USB_CH_HCCHAR_MC_EC_Pos 20 /*!< USB_CH HCCHAR: MC_EC Position */
\r
8560 #define USB_CH_HCCHAR_MC_EC_Msk (0x03UL << USB_CH_HCCHAR_MC_EC_Pos) /*!< USB_CH HCCHAR: MC_EC Mask */
\r
8561 #define USB_CH_HCCHAR_DevAddr_Pos 22 /*!< USB_CH HCCHAR: DevAddr Position */
\r
8562 #define USB_CH_HCCHAR_DevAddr_Msk (0x7fUL << USB_CH_HCCHAR_DevAddr_Pos) /*!< USB_CH HCCHAR: DevAddr Mask */
\r
8563 #define USB_CH_HCCHAR_OddFrm_Pos 29 /*!< USB_CH HCCHAR: OddFrm Position */
\r
8564 #define USB_CH_HCCHAR_OddFrm_Msk (0x01UL << USB_CH_HCCHAR_OddFrm_Pos) /*!< USB_CH HCCHAR: OddFrm Mask */
\r
8565 #define USB_CH_HCCHAR_ChDis_Pos 30 /*!< USB_CH HCCHAR: ChDis Position */
\r
8566 #define USB_CH_HCCHAR_ChDis_Msk (0x01UL << USB_CH_HCCHAR_ChDis_Pos) /*!< USB_CH HCCHAR: ChDis Mask */
\r
8567 #define USB_CH_HCCHAR_ChEna_Pos 31 /*!< USB_CH HCCHAR: ChEna Position */
\r
8568 #define USB_CH_HCCHAR_ChEna_Msk (0x01UL << USB_CH_HCCHAR_ChEna_Pos) /*!< USB_CH HCCHAR: ChEna Mask */
\r
8570 /* -------------------------------- USB_CH_HCINT -------------------------------- */
\r
8571 #define USB_CH_HCINT_XferCompl_Pos 0 /*!< USB_CH HCINT: XferCompl Position */
\r
8572 #define USB_CH_HCINT_XferCompl_Msk (0x01UL << USB_CH_HCINT_XferCompl_Pos) /*!< USB_CH HCINT: XferCompl Mask */
\r
8573 #define USB_CH_HCINT_ChHltd_Pos 1 /*!< USB_CH HCINT: ChHltd Position */
\r
8574 #define USB_CH_HCINT_ChHltd_Msk (0x01UL << USB_CH_HCINT_ChHltd_Pos) /*!< USB_CH HCINT: ChHltd Mask */
\r
8575 #define USB_CH_HCINT_AHBErr_Pos 2 /*!< USB_CH HCINT: AHBErr Position */
\r
8576 #define USB_CH_HCINT_AHBErr_Msk (0x01UL << USB_CH_HCINT_AHBErr_Pos) /*!< USB_CH HCINT: AHBErr Mask */
\r
8577 #define USB_CH_HCINT_STALL_Pos 3 /*!< USB_CH HCINT: STALL Position */
\r
8578 #define USB_CH_HCINT_STALL_Msk (0x01UL << USB_CH_HCINT_STALL_Pos) /*!< USB_CH HCINT: STALL Mask */
\r
8579 #define USB_CH_HCINT_NAK_Pos 4 /*!< USB_CH HCINT: NAK Position */
\r
8580 #define USB_CH_HCINT_NAK_Msk (0x01UL << USB_CH_HCINT_NAK_Pos) /*!< USB_CH HCINT: NAK Mask */
\r
8581 #define USB_CH_HCINT_ACK_Pos 5 /*!< USB_CH HCINT: ACK Position */
\r
8582 #define USB_CH_HCINT_ACK_Msk (0x01UL << USB_CH_HCINT_ACK_Pos) /*!< USB_CH HCINT: ACK Mask */
\r
8583 #define USB_CH_HCINT_NYET_Pos 6 /*!< USB_CH HCINT: NYET Position */
\r
8584 #define USB_CH_HCINT_NYET_Msk (0x01UL << USB_CH_HCINT_NYET_Pos) /*!< USB_CH HCINT: NYET Mask */
\r
8585 #define USB_CH_HCINT_XactErr_Pos 7 /*!< USB_CH HCINT: XactErr Position */
\r
8586 #define USB_CH_HCINT_XactErr_Msk (0x01UL << USB_CH_HCINT_XactErr_Pos) /*!< USB_CH HCINT: XactErr Mask */
\r
8587 #define USB_CH_HCINT_BblErr_Pos 8 /*!< USB_CH HCINT: BblErr Position */
\r
8588 #define USB_CH_HCINT_BblErr_Msk (0x01UL << USB_CH_HCINT_BblErr_Pos) /*!< USB_CH HCINT: BblErr Mask */
\r
8589 #define USB_CH_HCINT_FrmOvrun_Pos 9 /*!< USB_CH HCINT: FrmOvrun Position */
\r
8590 #define USB_CH_HCINT_FrmOvrun_Msk (0x01UL << USB_CH_HCINT_FrmOvrun_Pos) /*!< USB_CH HCINT: FrmOvrun Mask */
\r
8591 #define USB_CH_HCINT_DataTglErr_Pos 10 /*!< USB_CH HCINT: DataTglErr Position */
\r
8592 #define USB_CH_HCINT_DataTglErr_Msk (0x01UL << USB_CH_HCINT_DataTglErr_Pos) /*!< USB_CH HCINT: DataTglErr Mask */
\r
8593 #define USB_CH_HCINT_BNAIntr_Pos 11 /*!< USB_CH HCINT: BNAIntr Position */
\r
8594 #define USB_CH_HCINT_BNAIntr_Msk (0x01UL << USB_CH_HCINT_BNAIntr_Pos) /*!< USB_CH HCINT: BNAIntr Mask */
\r
8595 #define USB_CH_HCINT_XCS_XACT_ERR_Pos 12 /*!< USB_CH HCINT: XCS_XACT_ERR Position */
\r
8596 #define USB_CH_HCINT_XCS_XACT_ERR_Msk (0x01UL << USB_CH_HCINT_XCS_XACT_ERR_Pos) /*!< USB_CH HCINT: XCS_XACT_ERR Mask */
\r
8597 #define USB_CH_HCINT_DESC_LST_ROLLIntr_Pos 13 /*!< USB_CH HCINT: DESC_LST_ROLLIntr Position */
\r
8598 #define USB_CH_HCINT_DESC_LST_ROLLIntr_Msk (0x01UL << USB_CH_HCINT_DESC_LST_ROLLIntr_Pos) /*!< USB_CH HCINT: DESC_LST_ROLLIntr Mask */
\r
8600 /* ------------------------------- USB_CH_HCINTMSK ------------------------------ */
\r
8601 #define USB_CH_HCINTMSK_XferComplMsk_Pos 0 /*!< USB_CH HCINTMSK: XferComplMsk Position */
\r
8602 #define USB_CH_HCINTMSK_XferComplMsk_Msk (0x01UL << USB_CH_HCINTMSK_XferComplMsk_Pos) /*!< USB_CH HCINTMSK: XferComplMsk Mask */
\r
8603 #define USB_CH_HCINTMSK_ChHltdMsk_Pos 1 /*!< USB_CH HCINTMSK: ChHltdMsk Position */
\r
8604 #define USB_CH_HCINTMSK_ChHltdMsk_Msk (0x01UL << USB_CH_HCINTMSK_ChHltdMsk_Pos) /*!< USB_CH HCINTMSK: ChHltdMsk Mask */
\r
8605 #define USB_CH_HCINTMSK_AHBErrMsk_Pos 2 /*!< USB_CH HCINTMSK: AHBErrMsk Position */
\r
8606 #define USB_CH_HCINTMSK_AHBErrMsk_Msk (0x01UL << USB_CH_HCINTMSK_AHBErrMsk_Pos) /*!< USB_CH HCINTMSK: AHBErrMsk Mask */
\r
8607 #define USB_CH_HCINTMSK_StallMsk_Pos 3 /*!< USB_CH HCINTMSK: StallMsk Position */
\r
8608 #define USB_CH_HCINTMSK_StallMsk_Msk (0x01UL << USB_CH_HCINTMSK_StallMsk_Pos) /*!< USB_CH HCINTMSK: StallMsk Mask */
\r
8609 #define USB_CH_HCINTMSK_NakMsk_Pos 4 /*!< USB_CH HCINTMSK: NakMsk Position */
\r
8610 #define USB_CH_HCINTMSK_NakMsk_Msk (0x01UL << USB_CH_HCINTMSK_NakMsk_Pos) /*!< USB_CH HCINTMSK: NakMsk Mask */
\r
8611 #define USB_CH_HCINTMSK_AckMsk_Pos 5 /*!< USB_CH HCINTMSK: AckMsk Position */
\r
8612 #define USB_CH_HCINTMSK_AckMsk_Msk (0x01UL << USB_CH_HCINTMSK_AckMsk_Pos) /*!< USB_CH HCINTMSK: AckMsk Mask */
\r
8613 #define USB_CH_HCINTMSK_NyetMsk_Pos 6 /*!< USB_CH HCINTMSK: NyetMsk Position */
\r
8614 #define USB_CH_HCINTMSK_NyetMsk_Msk (0x01UL << USB_CH_HCINTMSK_NyetMsk_Pos) /*!< USB_CH HCINTMSK: NyetMsk Mask */
\r
8615 #define USB_CH_HCINTMSK_XactErrMsk_Pos 7 /*!< USB_CH HCINTMSK: XactErrMsk Position */
\r
8616 #define USB_CH_HCINTMSK_XactErrMsk_Msk (0x01UL << USB_CH_HCINTMSK_XactErrMsk_Pos) /*!< USB_CH HCINTMSK: XactErrMsk Mask */
\r
8617 #define USB_CH_HCINTMSK_BblErrMsk_Pos 8 /*!< USB_CH HCINTMSK: BblErrMsk Position */
\r
8618 #define USB_CH_HCINTMSK_BblErrMsk_Msk (0x01UL << USB_CH_HCINTMSK_BblErrMsk_Pos) /*!< USB_CH HCINTMSK: BblErrMsk Mask */
\r
8619 #define USB_CH_HCINTMSK_FrmOvrunMsk_Pos 9 /*!< USB_CH HCINTMSK: FrmOvrunMsk Position */
\r
8620 #define USB_CH_HCINTMSK_FrmOvrunMsk_Msk (0x01UL << USB_CH_HCINTMSK_FrmOvrunMsk_Pos) /*!< USB_CH HCINTMSK: FrmOvrunMsk Mask */
\r
8621 #define USB_CH_HCINTMSK_DataTglErrMsk_Pos 10 /*!< USB_CH HCINTMSK: DataTglErrMsk Position */
\r
8622 #define USB_CH_HCINTMSK_DataTglErrMsk_Msk (0x01UL << USB_CH_HCINTMSK_DataTglErrMsk_Pos) /*!< USB_CH HCINTMSK: DataTglErrMsk Mask */
\r
8623 #define USB_CH_HCINTMSK_BNAIntrMsk_Pos 11 /*!< USB_CH HCINTMSK: BNAIntrMsk Position */
\r
8624 #define USB_CH_HCINTMSK_BNAIntrMsk_Msk (0x01UL << USB_CH_HCINTMSK_BNAIntrMsk_Pos) /*!< USB_CH HCINTMSK: BNAIntrMsk Mask */
\r
8625 #define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos 13 /*!< USB_CH HCINTMSK: DESC_LST_ROLLIntrMsk Position */
\r
8626 #define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Msk (0x01UL << USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos) /*!< USB_CH HCINTMSK: DESC_LST_ROLLIntrMsk Mask */
\r
8628 /* -------------------------- USB_CH_HCTSIZ_BUFFERMODE -------------------------- */
\r
8629 #define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos 0 /*!< USB_CH HCTSIZ_BUFFERMODE: XferSize Position */
\r
8630 #define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Msk (0x0007ffffUL << USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos) /*!< USB_CH HCTSIZ_BUFFERMODE: XferSize Mask */
\r
8631 #define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos 19 /*!< USB_CH HCTSIZ_BUFFERMODE: PktCnt Position */
\r
8632 #define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk (0x000003ffUL << USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos) /*!< USB_CH HCTSIZ_BUFFERMODE: PktCnt Mask */
\r
8633 #define USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos 29 /*!< USB_CH HCTSIZ_BUFFERMODE: Pid Position */
\r
8634 #define USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk (0x03UL << USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos) /*!< USB_CH HCTSIZ_BUFFERMODE: Pid Mask */
\r
8636 /* -------------------------- USB_CH_HCTSIZ_SCATGATHER -------------------------- */
\r
8637 #define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos 0 /*!< USB_CH HCTSIZ_SCATGATHER: SCHED_INFO Position */
\r
8638 #define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Msk (0x000000ffUL << USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos)/*!< USB_CH HCTSIZ_SCATGATHER: SCHED_INFO Mask */
\r
8639 #define USB_CH_HCTSIZ_SCATGATHER_NTD_Pos 8 /*!< USB_CH HCTSIZ_SCATGATHER: NTD Position */
\r
8640 #define USB_CH_HCTSIZ_SCATGATHER_NTD_Msk (0x000000ffUL << USB_CH_HCTSIZ_SCATGATHER_NTD_Pos) /*!< USB_CH HCTSIZ_SCATGATHER: NTD Mask */
\r
8641 #define USB_CH_HCTSIZ_SCATGATHER_Pid_Pos 29 /*!< USB_CH HCTSIZ_SCATGATHER: Pid Position */
\r
8642 #define USB_CH_HCTSIZ_SCATGATHER_Pid_Msk (0x03UL << USB_CH_HCTSIZ_SCATGATHER_Pid_Pos) /*!< USB_CH HCTSIZ_SCATGATHER: Pid Mask */
\r
8644 /* --------------------------- USB_CH_HCDMA_BUFFERMODE -------------------------- */
\r
8645 #define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos 0 /*!< USB_CH HCDMA_BUFFERMODE: DMAAddr Position */
\r
8646 #define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Msk (0xffffffffUL << USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos) /*!< USB_CH HCDMA_BUFFERMODE: DMAAddr Mask */
\r
8648 /* --------------------------- USB_CH_HCDMA_SCATGATHER -------------------------- */
\r
8649 #define USB_CH_HCDMA_SCATGATHER_CTD_Pos 3 /*!< USB_CH HCDMA_SCATGATHER: CTD Position */
\r
8650 #define USB_CH_HCDMA_SCATGATHER_CTD_Msk (0x3fUL << USB_CH_HCDMA_SCATGATHER_CTD_Pos) /*!< USB_CH HCDMA_SCATGATHER: CTD Mask */
\r
8651 #define USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos 9 /*!< USB_CH HCDMA_SCATGATHER: DMAAddr Position */
\r
8652 #define USB_CH_HCDMA_SCATGATHER_DMAAddr_Msk (0x007fffffUL << USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos) /*!< USB_CH HCDMA_SCATGATHER: DMAAddr Mask */
\r
8654 /* -------------------------------- USB_CH_HCDMAB ------------------------------- */
\r
8655 #define USB_CH_HCDMAB_Buffer_Address_Pos 0 /*!< USB_CH HCDMAB: Buffer_Address Position */
\r
8656 #define USB_CH_HCDMAB_Buffer_Address_Msk (0xffffffffUL << USB_CH_HCDMAB_Buffer_Address_Pos) /*!< USB_CH HCDMAB: Buffer_Address Mask */
\r
8659 /* ================================================================================ */
\r
8660 /* ================ Group 'USIC' Position & Mask ================ */
\r
8661 /* ================================================================================ */
\r
8664 /* ----------------------------------- USIC_ID ---------------------------------- */
\r
8665 #define USIC_ID_MOD_REV_Pos 0 /*!< USIC ID: MOD_REV Position */
\r
8666 #define USIC_ID_MOD_REV_Msk (0x000000ffUL << USIC_ID_MOD_REV_Pos) /*!< USIC ID: MOD_REV Mask */
\r
8667 #define USIC_ID_MOD_TYPE_Pos 8 /*!< USIC ID: MOD_TYPE Position */
\r
8668 #define USIC_ID_MOD_TYPE_Msk (0x000000ffUL << USIC_ID_MOD_TYPE_Pos) /*!< USIC ID: MOD_TYPE Mask */
\r
8669 #define USIC_ID_MOD_NUMBER_Pos 16 /*!< USIC ID: MOD_NUMBER Position */
\r
8670 #define USIC_ID_MOD_NUMBER_Msk (0x0000ffffUL << USIC_ID_MOD_NUMBER_Pos) /*!< USIC ID: MOD_NUMBER Mask */
\r
8673 /* ================================================================================ */
\r
8674 /* ================ Group 'USIC_CH' Position & Mask ================ */
\r
8675 /* ================================================================================ */
\r
8678 /* -------------------------------- USIC_CH_CCFG -------------------------------- */
\r
8679 #define USIC_CH_CCFG_SSC_Pos 0 /*!< USIC_CH CCFG: SSC Position */
\r
8680 #define USIC_CH_CCFG_SSC_Msk (0x01UL << USIC_CH_CCFG_SSC_Pos) /*!< USIC_CH CCFG: SSC Mask */
\r
8681 #define USIC_CH_CCFG_ASC_Pos 1 /*!< USIC_CH CCFG: ASC Position */
\r
8682 #define USIC_CH_CCFG_ASC_Msk (0x01UL << USIC_CH_CCFG_ASC_Pos) /*!< USIC_CH CCFG: ASC Mask */
\r
8683 #define USIC_CH_CCFG_IIC_Pos 2 /*!< USIC_CH CCFG: IIC Position */
\r
8684 #define USIC_CH_CCFG_IIC_Msk (0x01UL << USIC_CH_CCFG_IIC_Pos) /*!< USIC_CH CCFG: IIC Mask */
\r
8685 #define USIC_CH_CCFG_IIS_Pos 3 /*!< USIC_CH CCFG: IIS Position */
\r
8686 #define USIC_CH_CCFG_IIS_Msk (0x01UL << USIC_CH_CCFG_IIS_Pos) /*!< USIC_CH CCFG: IIS Mask */
\r
8687 #define USIC_CH_CCFG_RB_Pos 6 /*!< USIC_CH CCFG: RB Position */
\r
8688 #define USIC_CH_CCFG_RB_Msk (0x01UL << USIC_CH_CCFG_RB_Pos) /*!< USIC_CH CCFG: RB Mask */
\r
8689 #define USIC_CH_CCFG_TB_Pos 7 /*!< USIC_CH CCFG: TB Position */
\r
8690 #define USIC_CH_CCFG_TB_Msk (0x01UL << USIC_CH_CCFG_TB_Pos) /*!< USIC_CH CCFG: TB Mask */
\r
8692 /* -------------------------------- USIC_CH_KSCFG ------------------------------- */
\r
8693 #define USIC_CH_KSCFG_MODEN_Pos 0 /*!< USIC_CH KSCFG: MODEN Position */
\r
8694 #define USIC_CH_KSCFG_MODEN_Msk (0x01UL << USIC_CH_KSCFG_MODEN_Pos) /*!< USIC_CH KSCFG: MODEN Mask */
\r
8695 #define USIC_CH_KSCFG_BPMODEN_Pos 1 /*!< USIC_CH KSCFG: BPMODEN Position */
\r
8696 #define USIC_CH_KSCFG_BPMODEN_Msk (0x01UL << USIC_CH_KSCFG_BPMODEN_Pos) /*!< USIC_CH KSCFG: BPMODEN Mask */
\r
8697 #define USIC_CH_KSCFG_NOMCFG_Pos 4 /*!< USIC_CH KSCFG: NOMCFG Position */
\r
8698 #define USIC_CH_KSCFG_NOMCFG_Msk (0x03UL << USIC_CH_KSCFG_NOMCFG_Pos) /*!< USIC_CH KSCFG: NOMCFG Mask */
\r
8699 #define USIC_CH_KSCFG_BPNOM_Pos 7 /*!< USIC_CH KSCFG: BPNOM Position */
\r
8700 #define USIC_CH_KSCFG_BPNOM_Msk (0x01UL << USIC_CH_KSCFG_BPNOM_Pos) /*!< USIC_CH KSCFG: BPNOM Mask */
\r
8701 #define USIC_CH_KSCFG_SUMCFG_Pos 8 /*!< USIC_CH KSCFG: SUMCFG Position */
\r
8702 #define USIC_CH_KSCFG_SUMCFG_Msk (0x03UL << USIC_CH_KSCFG_SUMCFG_Pos) /*!< USIC_CH KSCFG: SUMCFG Mask */
\r
8703 #define USIC_CH_KSCFG_BPSUM_Pos 11 /*!< USIC_CH KSCFG: BPSUM Position */
\r
8704 #define USIC_CH_KSCFG_BPSUM_Msk (0x01UL << USIC_CH_KSCFG_BPSUM_Pos) /*!< USIC_CH KSCFG: BPSUM Mask */
\r
8706 /* --------------------------------- USIC_CH_FDR -------------------------------- */
\r
8707 #define USIC_CH_FDR_STEP_Pos 0 /*!< USIC_CH FDR: STEP Position */
\r
8708 #define USIC_CH_FDR_STEP_Msk (0x000003ffUL << USIC_CH_FDR_STEP_Pos) /*!< USIC_CH FDR: STEP Mask */
\r
8709 #define USIC_CH_FDR_DM_Pos 14 /*!< USIC_CH FDR: DM Position */
\r
8710 #define USIC_CH_FDR_DM_Msk (0x03UL << USIC_CH_FDR_DM_Pos) /*!< USIC_CH FDR: DM Mask */
\r
8711 #define USIC_CH_FDR_RESULT_Pos 16 /*!< USIC_CH FDR: RESULT Position */
\r
8712 #define USIC_CH_FDR_RESULT_Msk (0x000003ffUL << USIC_CH_FDR_RESULT_Pos) /*!< USIC_CH FDR: RESULT Mask */
\r
8714 /* --------------------------------- USIC_CH_BRG -------------------------------- */
\r
8715 #define USIC_CH_BRG_CLKSEL_Pos 0 /*!< USIC_CH BRG: CLKSEL Position */
\r
8716 #define USIC_CH_BRG_CLKSEL_Msk (0x03UL << USIC_CH_BRG_CLKSEL_Pos) /*!< USIC_CH BRG: CLKSEL Mask */
\r
8717 #define USIC_CH_BRG_TMEN_Pos 3 /*!< USIC_CH BRG: TMEN Position */
\r
8718 #define USIC_CH_BRG_TMEN_Msk (0x01UL << USIC_CH_BRG_TMEN_Pos) /*!< USIC_CH BRG: TMEN Mask */
\r
8719 #define USIC_CH_BRG_PPPEN_Pos 4 /*!< USIC_CH BRG: PPPEN Position */
\r
8720 #define USIC_CH_BRG_PPPEN_Msk (0x01UL << USIC_CH_BRG_PPPEN_Pos) /*!< USIC_CH BRG: PPPEN Mask */
\r
8721 #define USIC_CH_BRG_CTQSEL_Pos 6 /*!< USIC_CH BRG: CTQSEL Position */
\r
8722 #define USIC_CH_BRG_CTQSEL_Msk (0x03UL << USIC_CH_BRG_CTQSEL_Pos) /*!< USIC_CH BRG: CTQSEL Mask */
\r
8723 #define USIC_CH_BRG_PCTQ_Pos 8 /*!< USIC_CH BRG: PCTQ Position */
\r
8724 #define USIC_CH_BRG_PCTQ_Msk (0x03UL << USIC_CH_BRG_PCTQ_Pos) /*!< USIC_CH BRG: PCTQ Mask */
\r
8725 #define USIC_CH_BRG_DCTQ_Pos 10 /*!< USIC_CH BRG: DCTQ Position */
\r
8726 #define USIC_CH_BRG_DCTQ_Msk (0x1fUL << USIC_CH_BRG_DCTQ_Pos) /*!< USIC_CH BRG: DCTQ Mask */
\r
8727 #define USIC_CH_BRG_PDIV_Pos 16 /*!< USIC_CH BRG: PDIV Position */
\r
8728 #define USIC_CH_BRG_PDIV_Msk (0x000003ffUL << USIC_CH_BRG_PDIV_Pos) /*!< USIC_CH BRG: PDIV Mask */
\r
8729 #define USIC_CH_BRG_SCLKOSEL_Pos 28 /*!< USIC_CH BRG: SCLKOSEL Position */
\r
8730 #define USIC_CH_BRG_SCLKOSEL_Msk (0x01UL << USIC_CH_BRG_SCLKOSEL_Pos) /*!< USIC_CH BRG: SCLKOSEL Mask */
\r
8731 #define USIC_CH_BRG_MCLKCFG_Pos 29 /*!< USIC_CH BRG: MCLKCFG Position */
\r
8732 #define USIC_CH_BRG_MCLKCFG_Msk (0x01UL << USIC_CH_BRG_MCLKCFG_Pos) /*!< USIC_CH BRG: MCLKCFG Mask */
\r
8733 #define USIC_CH_BRG_SCLKCFG_Pos 30 /*!< USIC_CH BRG: SCLKCFG Position */
\r
8734 #define USIC_CH_BRG_SCLKCFG_Msk (0x03UL << USIC_CH_BRG_SCLKCFG_Pos) /*!< USIC_CH BRG: SCLKCFG Mask */
\r
8736 /* -------------------------------- USIC_CH_INPR -------------------------------- */
\r
8737 #define USIC_CH_INPR_TSINP_Pos 0 /*!< USIC_CH INPR: TSINP Position */
\r
8738 #define USIC_CH_INPR_TSINP_Msk (0x07UL << USIC_CH_INPR_TSINP_Pos) /*!< USIC_CH INPR: TSINP Mask */
\r
8739 #define USIC_CH_INPR_TBINP_Pos 4 /*!< USIC_CH INPR: TBINP Position */
\r
8740 #define USIC_CH_INPR_TBINP_Msk (0x07UL << USIC_CH_INPR_TBINP_Pos) /*!< USIC_CH INPR: TBINP Mask */
\r
8741 #define USIC_CH_INPR_RINP_Pos 8 /*!< USIC_CH INPR: RINP Position */
\r
8742 #define USIC_CH_INPR_RINP_Msk (0x07UL << USIC_CH_INPR_RINP_Pos) /*!< USIC_CH INPR: RINP Mask */
\r
8743 #define USIC_CH_INPR_AINP_Pos 12 /*!< USIC_CH INPR: AINP Position */
\r
8744 #define USIC_CH_INPR_AINP_Msk (0x07UL << USIC_CH_INPR_AINP_Pos) /*!< USIC_CH INPR: AINP Mask */
\r
8745 #define USIC_CH_INPR_PINP_Pos 16 /*!< USIC_CH INPR: PINP Position */
\r
8746 #define USIC_CH_INPR_PINP_Msk (0x07UL << USIC_CH_INPR_PINP_Pos) /*!< USIC_CH INPR: PINP Mask */
\r
8748 /* -------------------------------- USIC_CH_DX0CR ------------------------------- */
\r
8749 #define USIC_CH_DX0CR_DSEL_Pos 0 /*!< USIC_CH DX0CR: DSEL Position */
\r
8750 #define USIC_CH_DX0CR_DSEL_Msk (0x07UL << USIC_CH_DX0CR_DSEL_Pos) /*!< USIC_CH DX0CR: DSEL Mask */
\r
8751 #define USIC_CH_DX0CR_INSW_Pos 4 /*!< USIC_CH DX0CR: INSW Position */
\r
8752 #define USIC_CH_DX0CR_INSW_Msk (0x01UL << USIC_CH_DX0CR_INSW_Pos) /*!< USIC_CH DX0CR: INSW Mask */
\r
8753 #define USIC_CH_DX0CR_DFEN_Pos 5 /*!< USIC_CH DX0CR: DFEN Position */
\r
8754 #define USIC_CH_DX0CR_DFEN_Msk (0x01UL << USIC_CH_DX0CR_DFEN_Pos) /*!< USIC_CH DX0CR: DFEN Mask */
\r
8755 #define USIC_CH_DX0CR_DSEN_Pos 6 /*!< USIC_CH DX0CR: DSEN Position */
\r
8756 #define USIC_CH_DX0CR_DSEN_Msk (0x01UL << USIC_CH_DX0CR_DSEN_Pos) /*!< USIC_CH DX0CR: DSEN Mask */
\r
8757 #define USIC_CH_DX0CR_DPOL_Pos 8 /*!< USIC_CH DX0CR: DPOL Position */
\r
8758 #define USIC_CH_DX0CR_DPOL_Msk (0x01UL << USIC_CH_DX0CR_DPOL_Pos) /*!< USIC_CH DX0CR: DPOL Mask */
\r
8759 #define USIC_CH_DX0CR_SFSEL_Pos 9 /*!< USIC_CH DX0CR: SFSEL Position */
\r
8760 #define USIC_CH_DX0CR_SFSEL_Msk (0x01UL << USIC_CH_DX0CR_SFSEL_Pos) /*!< USIC_CH DX0CR: SFSEL Mask */
\r
8761 #define USIC_CH_DX0CR_CM_Pos 10 /*!< USIC_CH DX0CR: CM Position */
\r
8762 #define USIC_CH_DX0CR_CM_Msk (0x03UL << USIC_CH_DX0CR_CM_Pos) /*!< USIC_CH DX0CR: CM Mask */
\r
8763 #define USIC_CH_DX0CR_DXS_Pos 15 /*!< USIC_CH DX0CR: DXS Position */
\r
8764 #define USIC_CH_DX0CR_DXS_Msk (0x01UL << USIC_CH_DX0CR_DXS_Pos) /*!< USIC_CH DX0CR: DXS Mask */
\r
8766 /* -------------------------------- USIC_CH_DX1CR ------------------------------- */
\r
8767 #define USIC_CH_DX1CR_DSEL_Pos 0 /*!< USIC_CH DX1CR: DSEL Position */
\r
8768 #define USIC_CH_DX1CR_DSEL_Msk (0x07UL << USIC_CH_DX1CR_DSEL_Pos) /*!< USIC_CH DX1CR: DSEL Mask */
\r
8769 #define USIC_CH_DX1CR_DCEN_Pos 3 /*!< USIC_CH DX1CR: DCEN Position */
\r
8770 #define USIC_CH_DX1CR_DCEN_Msk (0x01UL << USIC_CH_DX1CR_DCEN_Pos) /*!< USIC_CH DX1CR: DCEN Mask */
\r
8771 #define USIC_CH_DX1CR_INSW_Pos 4 /*!< USIC_CH DX1CR: INSW Position */
\r
8772 #define USIC_CH_DX1CR_INSW_Msk (0x01UL << USIC_CH_DX1CR_INSW_Pos) /*!< USIC_CH DX1CR: INSW Mask */
\r
8773 #define USIC_CH_DX1CR_DFEN_Pos 5 /*!< USIC_CH DX1CR: DFEN Position */
\r
8774 #define USIC_CH_DX1CR_DFEN_Msk (0x01UL << USIC_CH_DX1CR_DFEN_Pos) /*!< USIC_CH DX1CR: DFEN Mask */
\r
8775 #define USIC_CH_DX1CR_DSEN_Pos 6 /*!< USIC_CH DX1CR: DSEN Position */
\r
8776 #define USIC_CH_DX1CR_DSEN_Msk (0x01UL << USIC_CH_DX1CR_DSEN_Pos) /*!< USIC_CH DX1CR: DSEN Mask */
\r
8777 #define USIC_CH_DX1CR_DPOL_Pos 8 /*!< USIC_CH DX1CR: DPOL Position */
\r
8778 #define USIC_CH_DX1CR_DPOL_Msk (0x01UL << USIC_CH_DX1CR_DPOL_Pos) /*!< USIC_CH DX1CR: DPOL Mask */
\r
8779 #define USIC_CH_DX1CR_SFSEL_Pos 9 /*!< USIC_CH DX1CR: SFSEL Position */
\r
8780 #define USIC_CH_DX1CR_SFSEL_Msk (0x01UL << USIC_CH_DX1CR_SFSEL_Pos) /*!< USIC_CH DX1CR: SFSEL Mask */
\r
8781 #define USIC_CH_DX1CR_CM_Pos 10 /*!< USIC_CH DX1CR: CM Position */
\r
8782 #define USIC_CH_DX1CR_CM_Msk (0x03UL << USIC_CH_DX1CR_CM_Pos) /*!< USIC_CH DX1CR: CM Mask */
\r
8783 #define USIC_CH_DX1CR_DXS_Pos 15 /*!< USIC_CH DX1CR: DXS Position */
\r
8784 #define USIC_CH_DX1CR_DXS_Msk (0x01UL << USIC_CH_DX1CR_DXS_Pos) /*!< USIC_CH DX1CR: DXS Mask */
\r
8786 /* -------------------------------- USIC_CH_DX2CR ------------------------------- */
\r
8787 #define USIC_CH_DX2CR_DSEL_Pos 0 /*!< USIC_CH DX2CR: DSEL Position */
\r
8788 #define USIC_CH_DX2CR_DSEL_Msk (0x07UL << USIC_CH_DX2CR_DSEL_Pos) /*!< USIC_CH DX2CR: DSEL Mask */
\r
8789 #define USIC_CH_DX2CR_INSW_Pos 4 /*!< USIC_CH DX2CR: INSW Position */
\r
8790 #define USIC_CH_DX2CR_INSW_Msk (0x01UL << USIC_CH_DX2CR_INSW_Pos) /*!< USIC_CH DX2CR: INSW Mask */
\r
8791 #define USIC_CH_DX2CR_DFEN_Pos 5 /*!< USIC_CH DX2CR: DFEN Position */
\r
8792 #define USIC_CH_DX2CR_DFEN_Msk (0x01UL << USIC_CH_DX2CR_DFEN_Pos) /*!< USIC_CH DX2CR: DFEN Mask */
\r
8793 #define USIC_CH_DX2CR_DSEN_Pos 6 /*!< USIC_CH DX2CR: DSEN Position */
\r
8794 #define USIC_CH_DX2CR_DSEN_Msk (0x01UL << USIC_CH_DX2CR_DSEN_Pos) /*!< USIC_CH DX2CR: DSEN Mask */
\r
8795 #define USIC_CH_DX2CR_DPOL_Pos 8 /*!< USIC_CH DX2CR: DPOL Position */
\r
8796 #define USIC_CH_DX2CR_DPOL_Msk (0x01UL << USIC_CH_DX2CR_DPOL_Pos) /*!< USIC_CH DX2CR: DPOL Mask */
\r
8797 #define USIC_CH_DX2CR_SFSEL_Pos 9 /*!< USIC_CH DX2CR: SFSEL Position */
\r
8798 #define USIC_CH_DX2CR_SFSEL_Msk (0x01UL << USIC_CH_DX2CR_SFSEL_Pos) /*!< USIC_CH DX2CR: SFSEL Mask */
\r
8799 #define USIC_CH_DX2CR_CM_Pos 10 /*!< USIC_CH DX2CR: CM Position */
\r
8800 #define USIC_CH_DX2CR_CM_Msk (0x03UL << USIC_CH_DX2CR_CM_Pos) /*!< USIC_CH DX2CR: CM Mask */
\r
8801 #define USIC_CH_DX2CR_DXS_Pos 15 /*!< USIC_CH DX2CR: DXS Position */
\r
8802 #define USIC_CH_DX2CR_DXS_Msk (0x01UL << USIC_CH_DX2CR_DXS_Pos) /*!< USIC_CH DX2CR: DXS Mask */
\r
8804 /* -------------------------------- USIC_CH_DX3CR ------------------------------- */
\r
8805 #define USIC_CH_DX3CR_DSEL_Pos 0 /*!< USIC_CH DX3CR: DSEL Position */
\r
8806 #define USIC_CH_DX3CR_DSEL_Msk (0x07UL << USIC_CH_DX3CR_DSEL_Pos) /*!< USIC_CH DX3CR: DSEL Mask */
\r
8807 #define USIC_CH_DX3CR_INSW_Pos 4 /*!< USIC_CH DX3CR: INSW Position */
\r
8808 #define USIC_CH_DX3CR_INSW_Msk (0x01UL << USIC_CH_DX3CR_INSW_Pos) /*!< USIC_CH DX3CR: INSW Mask */
\r
8809 #define USIC_CH_DX3CR_DFEN_Pos 5 /*!< USIC_CH DX3CR: DFEN Position */
\r
8810 #define USIC_CH_DX3CR_DFEN_Msk (0x01UL << USIC_CH_DX3CR_DFEN_Pos) /*!< USIC_CH DX3CR: DFEN Mask */
\r
8811 #define USIC_CH_DX3CR_DSEN_Pos 6 /*!< USIC_CH DX3CR: DSEN Position */
\r
8812 #define USIC_CH_DX3CR_DSEN_Msk (0x01UL << USIC_CH_DX3CR_DSEN_Pos) /*!< USIC_CH DX3CR: DSEN Mask */
\r
8813 #define USIC_CH_DX3CR_DPOL_Pos 8 /*!< USIC_CH DX3CR: DPOL Position */
\r
8814 #define USIC_CH_DX3CR_DPOL_Msk (0x01UL << USIC_CH_DX3CR_DPOL_Pos) /*!< USIC_CH DX3CR: DPOL Mask */
\r
8815 #define USIC_CH_DX3CR_SFSEL_Pos 9 /*!< USIC_CH DX3CR: SFSEL Position */
\r
8816 #define USIC_CH_DX3CR_SFSEL_Msk (0x01UL << USIC_CH_DX3CR_SFSEL_Pos) /*!< USIC_CH DX3CR: SFSEL Mask */
\r
8817 #define USIC_CH_DX3CR_CM_Pos 10 /*!< USIC_CH DX3CR: CM Position */
\r
8818 #define USIC_CH_DX3CR_CM_Msk (0x03UL << USIC_CH_DX3CR_CM_Pos) /*!< USIC_CH DX3CR: CM Mask */
\r
8819 #define USIC_CH_DX3CR_DXS_Pos 15 /*!< USIC_CH DX3CR: DXS Position */
\r
8820 #define USIC_CH_DX3CR_DXS_Msk (0x01UL << USIC_CH_DX3CR_DXS_Pos) /*!< USIC_CH DX3CR: DXS Mask */
\r
8822 /* -------------------------------- USIC_CH_DX4CR ------------------------------- */
\r
8823 #define USIC_CH_DX4CR_DSEL_Pos 0 /*!< USIC_CH DX4CR: DSEL Position */
\r
8824 #define USIC_CH_DX4CR_DSEL_Msk (0x07UL << USIC_CH_DX4CR_DSEL_Pos) /*!< USIC_CH DX4CR: DSEL Mask */
\r
8825 #define USIC_CH_DX4CR_INSW_Pos 4 /*!< USIC_CH DX4CR: INSW Position */
\r
8826 #define USIC_CH_DX4CR_INSW_Msk (0x01UL << USIC_CH_DX4CR_INSW_Pos) /*!< USIC_CH DX4CR: INSW Mask */
\r
8827 #define USIC_CH_DX4CR_DFEN_Pos 5 /*!< USIC_CH DX4CR: DFEN Position */
\r
8828 #define USIC_CH_DX4CR_DFEN_Msk (0x01UL << USIC_CH_DX4CR_DFEN_Pos) /*!< USIC_CH DX4CR: DFEN Mask */
\r
8829 #define USIC_CH_DX4CR_DSEN_Pos 6 /*!< USIC_CH DX4CR: DSEN Position */
\r
8830 #define USIC_CH_DX4CR_DSEN_Msk (0x01UL << USIC_CH_DX4CR_DSEN_Pos) /*!< USIC_CH DX4CR: DSEN Mask */
\r
8831 #define USIC_CH_DX4CR_DPOL_Pos 8 /*!< USIC_CH DX4CR: DPOL Position */
\r
8832 #define USIC_CH_DX4CR_DPOL_Msk (0x01UL << USIC_CH_DX4CR_DPOL_Pos) /*!< USIC_CH DX4CR: DPOL Mask */
\r
8833 #define USIC_CH_DX4CR_SFSEL_Pos 9 /*!< USIC_CH DX4CR: SFSEL Position */
\r
8834 #define USIC_CH_DX4CR_SFSEL_Msk (0x01UL << USIC_CH_DX4CR_SFSEL_Pos) /*!< USIC_CH DX4CR: SFSEL Mask */
\r
8835 #define USIC_CH_DX4CR_CM_Pos 10 /*!< USIC_CH DX4CR: CM Position */
\r
8836 #define USIC_CH_DX4CR_CM_Msk (0x03UL << USIC_CH_DX4CR_CM_Pos) /*!< USIC_CH DX4CR: CM Mask */
\r
8837 #define USIC_CH_DX4CR_DXS_Pos 15 /*!< USIC_CH DX4CR: DXS Position */
\r
8838 #define USIC_CH_DX4CR_DXS_Msk (0x01UL << USIC_CH_DX4CR_DXS_Pos) /*!< USIC_CH DX4CR: DXS Mask */
\r
8840 /* -------------------------------- USIC_CH_DX5CR ------------------------------- */
\r
8841 #define USIC_CH_DX5CR_DSEL_Pos 0 /*!< USIC_CH DX5CR: DSEL Position */
\r
8842 #define USIC_CH_DX5CR_DSEL_Msk (0x07UL << USIC_CH_DX5CR_DSEL_Pos) /*!< USIC_CH DX5CR: DSEL Mask */
\r
8843 #define USIC_CH_DX5CR_INSW_Pos 4 /*!< USIC_CH DX5CR: INSW Position */
\r
8844 #define USIC_CH_DX5CR_INSW_Msk (0x01UL << USIC_CH_DX5CR_INSW_Pos) /*!< USIC_CH DX5CR: INSW Mask */
\r
8845 #define USIC_CH_DX5CR_DFEN_Pos 5 /*!< USIC_CH DX5CR: DFEN Position */
\r
8846 #define USIC_CH_DX5CR_DFEN_Msk (0x01UL << USIC_CH_DX5CR_DFEN_Pos) /*!< USIC_CH DX5CR: DFEN Mask */
\r
8847 #define USIC_CH_DX5CR_DSEN_Pos 6 /*!< USIC_CH DX5CR: DSEN Position */
\r
8848 #define USIC_CH_DX5CR_DSEN_Msk (0x01UL << USIC_CH_DX5CR_DSEN_Pos) /*!< USIC_CH DX5CR: DSEN Mask */
\r
8849 #define USIC_CH_DX5CR_DPOL_Pos 8 /*!< USIC_CH DX5CR: DPOL Position */
\r
8850 #define USIC_CH_DX5CR_DPOL_Msk (0x01UL << USIC_CH_DX5CR_DPOL_Pos) /*!< USIC_CH DX5CR: DPOL Mask */
\r
8851 #define USIC_CH_DX5CR_SFSEL_Pos 9 /*!< USIC_CH DX5CR: SFSEL Position */
\r
8852 #define USIC_CH_DX5CR_SFSEL_Msk (0x01UL << USIC_CH_DX5CR_SFSEL_Pos) /*!< USIC_CH DX5CR: SFSEL Mask */
\r
8853 #define USIC_CH_DX5CR_CM_Pos 10 /*!< USIC_CH DX5CR: CM Position */
\r
8854 #define USIC_CH_DX5CR_CM_Msk (0x03UL << USIC_CH_DX5CR_CM_Pos) /*!< USIC_CH DX5CR: CM Mask */
\r
8855 #define USIC_CH_DX5CR_DXS_Pos 15 /*!< USIC_CH DX5CR: DXS Position */
\r
8856 #define USIC_CH_DX5CR_DXS_Msk (0x01UL << USIC_CH_DX5CR_DXS_Pos) /*!< USIC_CH DX5CR: DXS Mask */
\r
8858 /* -------------------------------- USIC_CH_SCTR -------------------------------- */
\r
8859 #define USIC_CH_SCTR_SDIR_Pos 0 /*!< USIC_CH SCTR: SDIR Position */
\r
8860 #define USIC_CH_SCTR_SDIR_Msk (0x01UL << USIC_CH_SCTR_SDIR_Pos) /*!< USIC_CH SCTR: SDIR Mask */
\r
8861 #define USIC_CH_SCTR_PDL_Pos 1 /*!< USIC_CH SCTR: PDL Position */
\r
8862 #define USIC_CH_SCTR_PDL_Msk (0x01UL << USIC_CH_SCTR_PDL_Pos) /*!< USIC_CH SCTR: PDL Mask */
\r
8863 #define USIC_CH_SCTR_DSM_Pos 2 /*!< USIC_CH SCTR: DSM Position */
\r
8864 #define USIC_CH_SCTR_DSM_Msk (0x03UL << USIC_CH_SCTR_DSM_Pos) /*!< USIC_CH SCTR: DSM Mask */
\r
8865 #define USIC_CH_SCTR_HPCDIR_Pos 4 /*!< USIC_CH SCTR: HPCDIR Position */
\r
8866 #define USIC_CH_SCTR_HPCDIR_Msk (0x01UL << USIC_CH_SCTR_HPCDIR_Pos) /*!< USIC_CH SCTR: HPCDIR Mask */
\r
8867 #define USIC_CH_SCTR_DOCFG_Pos 6 /*!< USIC_CH SCTR: DOCFG Position */
\r
8868 #define USIC_CH_SCTR_DOCFG_Msk (0x03UL << USIC_CH_SCTR_DOCFG_Pos) /*!< USIC_CH SCTR: DOCFG Mask */
\r
8869 #define USIC_CH_SCTR_TRM_Pos 8 /*!< USIC_CH SCTR: TRM Position */
\r
8870 #define USIC_CH_SCTR_TRM_Msk (0x03UL << USIC_CH_SCTR_TRM_Pos) /*!< USIC_CH SCTR: TRM Mask */
\r
8871 #define USIC_CH_SCTR_FLE_Pos 16 /*!< USIC_CH SCTR: FLE Position */
\r
8872 #define USIC_CH_SCTR_FLE_Msk (0x3fUL << USIC_CH_SCTR_FLE_Pos) /*!< USIC_CH SCTR: FLE Mask */
\r
8873 #define USIC_CH_SCTR_WLE_Pos 24 /*!< USIC_CH SCTR: WLE Position */
\r
8874 #define USIC_CH_SCTR_WLE_Msk (0x0fUL << USIC_CH_SCTR_WLE_Pos) /*!< USIC_CH SCTR: WLE Mask */
\r
8876 /* -------------------------------- USIC_CH_TCSR -------------------------------- */
\r
8877 #define USIC_CH_TCSR_WLEMD_Pos 0 /*!< USIC_CH TCSR: WLEMD Position */
\r
8878 #define USIC_CH_TCSR_WLEMD_Msk (0x01UL << USIC_CH_TCSR_WLEMD_Pos) /*!< USIC_CH TCSR: WLEMD Mask */
\r
8879 #define USIC_CH_TCSR_SELMD_Pos 1 /*!< USIC_CH TCSR: SELMD Position */
\r
8880 #define USIC_CH_TCSR_SELMD_Msk (0x01UL << USIC_CH_TCSR_SELMD_Pos) /*!< USIC_CH TCSR: SELMD Mask */
\r
8881 #define USIC_CH_TCSR_FLEMD_Pos 2 /*!< USIC_CH TCSR: FLEMD Position */
\r
8882 #define USIC_CH_TCSR_FLEMD_Msk (0x01UL << USIC_CH_TCSR_FLEMD_Pos) /*!< USIC_CH TCSR: FLEMD Mask */
\r
8883 #define USIC_CH_TCSR_WAMD_Pos 3 /*!< USIC_CH TCSR: WAMD Position */
\r
8884 #define USIC_CH_TCSR_WAMD_Msk (0x01UL << USIC_CH_TCSR_WAMD_Pos) /*!< USIC_CH TCSR: WAMD Mask */
\r
8885 #define USIC_CH_TCSR_HPCMD_Pos 4 /*!< USIC_CH TCSR: HPCMD Position */
\r
8886 #define USIC_CH_TCSR_HPCMD_Msk (0x01UL << USIC_CH_TCSR_HPCMD_Pos) /*!< USIC_CH TCSR: HPCMD Mask */
\r
8887 #define USIC_CH_TCSR_SOF_Pos 5 /*!< USIC_CH TCSR: SOF Position */
\r
8888 #define USIC_CH_TCSR_SOF_Msk (0x01UL << USIC_CH_TCSR_SOF_Pos) /*!< USIC_CH TCSR: SOF Mask */
\r
8889 #define USIC_CH_TCSR_EOF_Pos 6 /*!< USIC_CH TCSR: EOF Position */
\r
8890 #define USIC_CH_TCSR_EOF_Msk (0x01UL << USIC_CH_TCSR_EOF_Pos) /*!< USIC_CH TCSR: EOF Mask */
\r
8891 #define USIC_CH_TCSR_TDV_Pos 7 /*!< USIC_CH TCSR: TDV Position */
\r
8892 #define USIC_CH_TCSR_TDV_Msk (0x01UL << USIC_CH_TCSR_TDV_Pos) /*!< USIC_CH TCSR: TDV Mask */
\r
8893 #define USIC_CH_TCSR_TDSSM_Pos 8 /*!< USIC_CH TCSR: TDSSM Position */
\r
8894 #define USIC_CH_TCSR_TDSSM_Msk (0x01UL << USIC_CH_TCSR_TDSSM_Pos) /*!< USIC_CH TCSR: TDSSM Mask */
\r
8895 #define USIC_CH_TCSR_TDEN_Pos 10 /*!< USIC_CH TCSR: TDEN Position */
\r
8896 #define USIC_CH_TCSR_TDEN_Msk (0x03UL << USIC_CH_TCSR_TDEN_Pos) /*!< USIC_CH TCSR: TDEN Mask */
\r
8897 #define USIC_CH_TCSR_TDVTR_Pos 12 /*!< USIC_CH TCSR: TDVTR Position */
\r
8898 #define USIC_CH_TCSR_TDVTR_Msk (0x01UL << USIC_CH_TCSR_TDVTR_Pos) /*!< USIC_CH TCSR: TDVTR Mask */
\r
8899 #define USIC_CH_TCSR_WA_Pos 13 /*!< USIC_CH TCSR: WA Position */
\r
8900 #define USIC_CH_TCSR_WA_Msk (0x01UL << USIC_CH_TCSR_WA_Pos) /*!< USIC_CH TCSR: WA Mask */
\r
8901 #define USIC_CH_TCSR_TSOF_Pos 24 /*!< USIC_CH TCSR: TSOF Position */
\r
8902 #define USIC_CH_TCSR_TSOF_Msk (0x01UL << USIC_CH_TCSR_TSOF_Pos) /*!< USIC_CH TCSR: TSOF Mask */
\r
8903 #define USIC_CH_TCSR_TV_Pos 26 /*!< USIC_CH TCSR: TV Position */
\r
8904 #define USIC_CH_TCSR_TV_Msk (0x01UL << USIC_CH_TCSR_TV_Pos) /*!< USIC_CH TCSR: TV Mask */
\r
8905 #define USIC_CH_TCSR_TVC_Pos 27 /*!< USIC_CH TCSR: TVC Position */
\r
8906 #define USIC_CH_TCSR_TVC_Msk (0x01UL << USIC_CH_TCSR_TVC_Pos) /*!< USIC_CH TCSR: TVC Mask */
\r
8907 #define USIC_CH_TCSR_TE_Pos 28 /*!< USIC_CH TCSR: TE Position */
\r
8908 #define USIC_CH_TCSR_TE_Msk (0x01UL << USIC_CH_TCSR_TE_Pos) /*!< USIC_CH TCSR: TE Mask */
\r
8910 /* --------------------------------- USIC_CH_PCR -------------------------------- */
\r
8911 #define USIC_CH_PCR_CTR0_Pos 0 /*!< USIC_CH PCR: CTR0 Position */
\r
8912 #define USIC_CH_PCR_CTR0_Msk (0x01UL << USIC_CH_PCR_CTR0_Pos) /*!< USIC_CH PCR: CTR0 Mask */
\r
8913 #define USIC_CH_PCR_CTR1_Pos 1 /*!< USIC_CH PCR: CTR1 Position */
\r
8914 #define USIC_CH_PCR_CTR1_Msk (0x01UL << USIC_CH_PCR_CTR1_Pos) /*!< USIC_CH PCR: CTR1 Mask */
\r
8915 #define USIC_CH_PCR_CTR2_Pos 2 /*!< USIC_CH PCR: CTR2 Position */
\r
8916 #define USIC_CH_PCR_CTR2_Msk (0x01UL << USIC_CH_PCR_CTR2_Pos) /*!< USIC_CH PCR: CTR2 Mask */
\r
8917 #define USIC_CH_PCR_CTR3_Pos 3 /*!< USIC_CH PCR: CTR3 Position */
\r
8918 #define USIC_CH_PCR_CTR3_Msk (0x01UL << USIC_CH_PCR_CTR3_Pos) /*!< USIC_CH PCR: CTR3 Mask */
\r
8919 #define USIC_CH_PCR_CTR4_Pos 4 /*!< USIC_CH PCR: CTR4 Position */
\r
8920 #define USIC_CH_PCR_CTR4_Msk (0x01UL << USIC_CH_PCR_CTR4_Pos) /*!< USIC_CH PCR: CTR4 Mask */
\r
8921 #define USIC_CH_PCR_CTR5_Pos 5 /*!< USIC_CH PCR: CTR5 Position */
\r
8922 #define USIC_CH_PCR_CTR5_Msk (0x01UL << USIC_CH_PCR_CTR5_Pos) /*!< USIC_CH PCR: CTR5 Mask */
\r
8923 #define USIC_CH_PCR_CTR6_Pos 6 /*!< USIC_CH PCR: CTR6 Position */
\r
8924 #define USIC_CH_PCR_CTR6_Msk (0x01UL << USIC_CH_PCR_CTR6_Pos) /*!< USIC_CH PCR: CTR6 Mask */
\r
8925 #define USIC_CH_PCR_CTR7_Pos 7 /*!< USIC_CH PCR: CTR7 Position */
\r
8926 #define USIC_CH_PCR_CTR7_Msk (0x01UL << USIC_CH_PCR_CTR7_Pos) /*!< USIC_CH PCR: CTR7 Mask */
\r
8927 #define USIC_CH_PCR_CTR8_Pos 8 /*!< USIC_CH PCR: CTR8 Position */
\r
8928 #define USIC_CH_PCR_CTR8_Msk (0x01UL << USIC_CH_PCR_CTR8_Pos) /*!< USIC_CH PCR: CTR8 Mask */
\r
8929 #define USIC_CH_PCR_CTR9_Pos 9 /*!< USIC_CH PCR: CTR9 Position */
\r
8930 #define USIC_CH_PCR_CTR9_Msk (0x01UL << USIC_CH_PCR_CTR9_Pos) /*!< USIC_CH PCR: CTR9 Mask */
\r
8931 #define USIC_CH_PCR_CTR10_Pos 10 /*!< USIC_CH PCR: CTR10 Position */
\r
8932 #define USIC_CH_PCR_CTR10_Msk (0x01UL << USIC_CH_PCR_CTR10_Pos) /*!< USIC_CH PCR: CTR10 Mask */
\r
8933 #define USIC_CH_PCR_CTR11_Pos 11 /*!< USIC_CH PCR: CTR11 Position */
\r
8934 #define USIC_CH_PCR_CTR11_Msk (0x01UL << USIC_CH_PCR_CTR11_Pos) /*!< USIC_CH PCR: CTR11 Mask */
\r
8935 #define USIC_CH_PCR_CTR12_Pos 12 /*!< USIC_CH PCR: CTR12 Position */
\r
8936 #define USIC_CH_PCR_CTR12_Msk (0x01UL << USIC_CH_PCR_CTR12_Pos) /*!< USIC_CH PCR: CTR12 Mask */
\r
8937 #define USIC_CH_PCR_CTR13_Pos 13 /*!< USIC_CH PCR: CTR13 Position */
\r
8938 #define USIC_CH_PCR_CTR13_Msk (0x01UL << USIC_CH_PCR_CTR13_Pos) /*!< USIC_CH PCR: CTR13 Mask */
\r
8939 #define USIC_CH_PCR_CTR14_Pos 14 /*!< USIC_CH PCR: CTR14 Position */
\r
8940 #define USIC_CH_PCR_CTR14_Msk (0x01UL << USIC_CH_PCR_CTR14_Pos) /*!< USIC_CH PCR: CTR14 Mask */
\r
8941 #define USIC_CH_PCR_CTR15_Pos 15 /*!< USIC_CH PCR: CTR15 Position */
\r
8942 #define USIC_CH_PCR_CTR15_Msk (0x01UL << USIC_CH_PCR_CTR15_Pos) /*!< USIC_CH PCR: CTR15 Mask */
\r
8943 #define USIC_CH_PCR_CTR16_Pos 16 /*!< USIC_CH PCR: CTR16 Position */
\r
8944 #define USIC_CH_PCR_CTR16_Msk (0x01UL << USIC_CH_PCR_CTR16_Pos) /*!< USIC_CH PCR: CTR16 Mask */
\r
8945 #define USIC_CH_PCR_CTR17_Pos 17 /*!< USIC_CH PCR: CTR17 Position */
\r
8946 #define USIC_CH_PCR_CTR17_Msk (0x01UL << USIC_CH_PCR_CTR17_Pos) /*!< USIC_CH PCR: CTR17 Mask */
\r
8947 #define USIC_CH_PCR_CTR18_Pos 18 /*!< USIC_CH PCR: CTR18 Position */
\r
8948 #define USIC_CH_PCR_CTR18_Msk (0x01UL << USIC_CH_PCR_CTR18_Pos) /*!< USIC_CH PCR: CTR18 Mask */
\r
8949 #define USIC_CH_PCR_CTR19_Pos 19 /*!< USIC_CH PCR: CTR19 Position */
\r
8950 #define USIC_CH_PCR_CTR19_Msk (0x01UL << USIC_CH_PCR_CTR19_Pos) /*!< USIC_CH PCR: CTR19 Mask */
\r
8951 #define USIC_CH_PCR_CTR20_Pos 20 /*!< USIC_CH PCR: CTR20 Position */
\r
8952 #define USIC_CH_PCR_CTR20_Msk (0x01UL << USIC_CH_PCR_CTR20_Pos) /*!< USIC_CH PCR: CTR20 Mask */
\r
8953 #define USIC_CH_PCR_CTR21_Pos 21 /*!< USIC_CH PCR: CTR21 Position */
\r
8954 #define USIC_CH_PCR_CTR21_Msk (0x01UL << USIC_CH_PCR_CTR21_Pos) /*!< USIC_CH PCR: CTR21 Mask */
\r
8955 #define USIC_CH_PCR_CTR22_Pos 22 /*!< USIC_CH PCR: CTR22 Position */
\r
8956 #define USIC_CH_PCR_CTR22_Msk (0x01UL << USIC_CH_PCR_CTR22_Pos) /*!< USIC_CH PCR: CTR22 Mask */
\r
8957 #define USIC_CH_PCR_CTR23_Pos 23 /*!< USIC_CH PCR: CTR23 Position */
\r
8958 #define USIC_CH_PCR_CTR23_Msk (0x01UL << USIC_CH_PCR_CTR23_Pos) /*!< USIC_CH PCR: CTR23 Mask */
\r
8959 #define USIC_CH_PCR_CTR24_Pos 24 /*!< USIC_CH PCR: CTR24 Position */
\r
8960 #define USIC_CH_PCR_CTR24_Msk (0x01UL << USIC_CH_PCR_CTR24_Pos) /*!< USIC_CH PCR: CTR24 Mask */
\r
8961 #define USIC_CH_PCR_CTR25_Pos 25 /*!< USIC_CH PCR: CTR25 Position */
\r
8962 #define USIC_CH_PCR_CTR25_Msk (0x01UL << USIC_CH_PCR_CTR25_Pos) /*!< USIC_CH PCR: CTR25 Mask */
\r
8963 #define USIC_CH_PCR_CTR26_Pos 26 /*!< USIC_CH PCR: CTR26 Position */
\r
8964 #define USIC_CH_PCR_CTR26_Msk (0x01UL << USIC_CH_PCR_CTR26_Pos) /*!< USIC_CH PCR: CTR26 Mask */
\r
8965 #define USIC_CH_PCR_CTR27_Pos 27 /*!< USIC_CH PCR: CTR27 Position */
\r
8966 #define USIC_CH_PCR_CTR27_Msk (0x01UL << USIC_CH_PCR_CTR27_Pos) /*!< USIC_CH PCR: CTR27 Mask */
\r
8967 #define USIC_CH_PCR_CTR28_Pos 28 /*!< USIC_CH PCR: CTR28 Position */
\r
8968 #define USIC_CH_PCR_CTR28_Msk (0x01UL << USIC_CH_PCR_CTR28_Pos) /*!< USIC_CH PCR: CTR28 Mask */
\r
8969 #define USIC_CH_PCR_CTR29_Pos 29 /*!< USIC_CH PCR: CTR29 Position */
\r
8970 #define USIC_CH_PCR_CTR29_Msk (0x01UL << USIC_CH_PCR_CTR29_Pos) /*!< USIC_CH PCR: CTR29 Mask */
\r
8971 #define USIC_CH_PCR_CTR30_Pos 30 /*!< USIC_CH PCR: CTR30 Position */
\r
8972 #define USIC_CH_PCR_CTR30_Msk (0x01UL << USIC_CH_PCR_CTR30_Pos) /*!< USIC_CH PCR: CTR30 Mask */
\r
8973 #define USIC_CH_PCR_CTR31_Pos 31 /*!< USIC_CH PCR: CTR31 Position */
\r
8974 #define USIC_CH_PCR_CTR31_Msk (0x01UL << USIC_CH_PCR_CTR31_Pos) /*!< USIC_CH PCR: CTR31 Mask */
\r
8976 /* ----------------------------- USIC_CH_PCR_ASCMode ---------------------------- */
\r
8977 #define USIC_CH_PCR_ASCMode_SMD_Pos 0 /*!< USIC_CH PCR_ASCMode: SMD Position */
\r
8978 #define USIC_CH_PCR_ASCMode_SMD_Msk (0x01UL << USIC_CH_PCR_ASCMode_SMD_Pos) /*!< USIC_CH PCR_ASCMode: SMD Mask */
\r
8979 #define USIC_CH_PCR_ASCMode_STPB_Pos 1 /*!< USIC_CH PCR_ASCMode: STPB Position */
\r
8980 #define USIC_CH_PCR_ASCMode_STPB_Msk (0x01UL << USIC_CH_PCR_ASCMode_STPB_Pos) /*!< USIC_CH PCR_ASCMode: STPB Mask */
\r
8981 #define USIC_CH_PCR_ASCMode_IDM_Pos 2 /*!< USIC_CH PCR_ASCMode: IDM Position */
\r
8982 #define USIC_CH_PCR_ASCMode_IDM_Msk (0x01UL << USIC_CH_PCR_ASCMode_IDM_Pos) /*!< USIC_CH PCR_ASCMode: IDM Mask */
\r
8983 #define USIC_CH_PCR_ASCMode_SBIEN_Pos 3 /*!< USIC_CH PCR_ASCMode: SBIEN Position */
\r
8984 #define USIC_CH_PCR_ASCMode_SBIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_SBIEN_Pos) /*!< USIC_CH PCR_ASCMode: SBIEN Mask */
\r
8985 #define USIC_CH_PCR_ASCMode_CDEN_Pos 4 /*!< USIC_CH PCR_ASCMode: CDEN Position */
\r
8986 #define USIC_CH_PCR_ASCMode_CDEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_CDEN_Pos) /*!< USIC_CH PCR_ASCMode: CDEN Mask */
\r
8987 #define USIC_CH_PCR_ASCMode_RNIEN_Pos 5 /*!< USIC_CH PCR_ASCMode: RNIEN Position */
\r
8988 #define USIC_CH_PCR_ASCMode_RNIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_RNIEN_Pos) /*!< USIC_CH PCR_ASCMode: RNIEN Mask */
\r
8989 #define USIC_CH_PCR_ASCMode_FEIEN_Pos 6 /*!< USIC_CH PCR_ASCMode: FEIEN Position */
\r
8990 #define USIC_CH_PCR_ASCMode_FEIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_FEIEN_Pos) /*!< USIC_CH PCR_ASCMode: FEIEN Mask */
\r
8991 #define USIC_CH_PCR_ASCMode_FFIEN_Pos 7 /*!< USIC_CH PCR_ASCMode: FFIEN Position */
\r
8992 #define USIC_CH_PCR_ASCMode_FFIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_FFIEN_Pos) /*!< USIC_CH PCR_ASCMode: FFIEN Mask */
\r
8993 #define USIC_CH_PCR_ASCMode_SP_Pos 8 /*!< USIC_CH PCR_ASCMode: SP Position */
\r
8994 #define USIC_CH_PCR_ASCMode_SP_Msk (0x1fUL << USIC_CH_PCR_ASCMode_SP_Pos) /*!< USIC_CH PCR_ASCMode: SP Mask */
\r
8995 #define USIC_CH_PCR_ASCMode_PL_Pos 13 /*!< USIC_CH PCR_ASCMode: PL Position */
\r
8996 #define USIC_CH_PCR_ASCMode_PL_Msk (0x07UL << USIC_CH_PCR_ASCMode_PL_Pos) /*!< USIC_CH PCR_ASCMode: PL Mask */
\r
8997 #define USIC_CH_PCR_ASCMode_RSTEN_Pos 16 /*!< USIC_CH PCR_ASCMode: RSTEN Position */
\r
8998 #define USIC_CH_PCR_ASCMode_RSTEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_RSTEN_Pos) /*!< USIC_CH PCR_ASCMode: RSTEN Mask */
\r
8999 #define USIC_CH_PCR_ASCMode_TSTEN_Pos 17 /*!< USIC_CH PCR_ASCMode: TSTEN Position */
\r
9000 #define USIC_CH_PCR_ASCMode_TSTEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_TSTEN_Pos) /*!< USIC_CH PCR_ASCMode: TSTEN Mask */
\r
9001 #define USIC_CH_PCR_ASCMode_MCLK_Pos 31 /*!< USIC_CH PCR_ASCMode: MCLK Position */
\r
9002 #define USIC_CH_PCR_ASCMode_MCLK_Msk (0x01UL << USIC_CH_PCR_ASCMode_MCLK_Pos) /*!< USIC_CH PCR_ASCMode: MCLK Mask */
\r
9004 /* ----------------------------- USIC_CH_PCR_SSCMode ---------------------------- */
\r
9005 #define USIC_CH_PCR_SSCMode_MSLSEN_Pos 0 /*!< USIC_CH PCR_SSCMode: MSLSEN Position */
\r
9006 #define USIC_CH_PCR_SSCMode_MSLSEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_MSLSEN_Pos) /*!< USIC_CH PCR_SSCMode: MSLSEN Mask */
\r
9007 #define USIC_CH_PCR_SSCMode_SELCTR_Pos 1 /*!< USIC_CH PCR_SSCMode: SELCTR Position */
\r
9008 #define USIC_CH_PCR_SSCMode_SELCTR_Msk (0x01UL << USIC_CH_PCR_SSCMode_SELCTR_Pos) /*!< USIC_CH PCR_SSCMode: SELCTR Mask */
\r
9009 #define USIC_CH_PCR_SSCMode_SELINV_Pos 2 /*!< USIC_CH PCR_SSCMode: SELINV Position */
\r
9010 #define USIC_CH_PCR_SSCMode_SELINV_Msk (0x01UL << USIC_CH_PCR_SSCMode_SELINV_Pos) /*!< USIC_CH PCR_SSCMode: SELINV Mask */
\r
9011 #define USIC_CH_PCR_SSCMode_FEM_Pos 3 /*!< USIC_CH PCR_SSCMode: FEM Position */
\r
9012 #define USIC_CH_PCR_SSCMode_FEM_Msk (0x01UL << USIC_CH_PCR_SSCMode_FEM_Pos) /*!< USIC_CH PCR_SSCMode: FEM Mask */
\r
9013 #define USIC_CH_PCR_SSCMode_CTQSEL1_Pos 4 /*!< USIC_CH PCR_SSCMode: CTQSEL1 Position */
\r
9014 #define USIC_CH_PCR_SSCMode_CTQSEL1_Msk (0x03UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos) /*!< USIC_CH PCR_SSCMode: CTQSEL1 Mask */
\r
9015 #define USIC_CH_PCR_SSCMode_PCTQ1_Pos 6 /*!< USIC_CH PCR_SSCMode: PCTQ1 Position */
\r
9016 #define USIC_CH_PCR_SSCMode_PCTQ1_Msk (0x03UL << USIC_CH_PCR_SSCMode_PCTQ1_Pos) /*!< USIC_CH PCR_SSCMode: PCTQ1 Mask */
\r
9017 #define USIC_CH_PCR_SSCMode_DCTQ1_Pos 8 /*!< USIC_CH PCR_SSCMode: DCTQ1 Position */
\r
9018 #define USIC_CH_PCR_SSCMode_DCTQ1_Msk (0x1fUL << USIC_CH_PCR_SSCMode_DCTQ1_Pos) /*!< USIC_CH PCR_SSCMode: DCTQ1 Mask */
\r
9019 #define USIC_CH_PCR_SSCMode_PARIEN_Pos 13 /*!< USIC_CH PCR_SSCMode: PARIEN Position */
\r
9020 #define USIC_CH_PCR_SSCMode_PARIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_PARIEN_Pos) /*!< USIC_CH PCR_SSCMode: PARIEN Mask */
\r
9021 #define USIC_CH_PCR_SSCMode_MSLSIEN_Pos 14 /*!< USIC_CH PCR_SSCMode: MSLSIEN Position */
\r
9022 #define USIC_CH_PCR_SSCMode_MSLSIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_MSLSIEN_Pos) /*!< USIC_CH PCR_SSCMode: MSLSIEN Mask */
\r
9023 #define USIC_CH_PCR_SSCMode_DX2TIEN_Pos 15 /*!< USIC_CH PCR_SSCMode: DX2TIEN Position */
\r
9024 #define USIC_CH_PCR_SSCMode_DX2TIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_DX2TIEN_Pos) /*!< USIC_CH PCR_SSCMode: DX2TIEN Mask */
\r
9025 #define USIC_CH_PCR_SSCMode_SELO_Pos 16 /*!< USIC_CH PCR_SSCMode: SELO Position */
\r
9026 #define USIC_CH_PCR_SSCMode_SELO_Msk (0x000000ffUL << USIC_CH_PCR_SSCMode_SELO_Pos) /*!< USIC_CH PCR_SSCMode: SELO Mask */
\r
9027 #define USIC_CH_PCR_SSCMode_TIWEN_Pos 24 /*!< USIC_CH PCR_SSCMode: TIWEN Position */
\r
9028 #define USIC_CH_PCR_SSCMode_TIWEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_TIWEN_Pos) /*!< USIC_CH PCR_SSCMode: TIWEN Mask */
\r
9029 #define USIC_CH_PCR_SSCMode_MCLK_Pos 31 /*!< USIC_CH PCR_SSCMode: MCLK Position */
\r
9030 #define USIC_CH_PCR_SSCMode_MCLK_Msk (0x01UL << USIC_CH_PCR_SSCMode_MCLK_Pos) /*!< USIC_CH PCR_SSCMode: MCLK Mask */
\r
9032 /* ----------------------------- USIC_CH_PCR_IICMode ---------------------------- */
\r
9033 #define USIC_CH_PCR_IICMode_SLAD_Pos 0 /*!< USIC_CH PCR_IICMode: SLAD Position */
\r
9034 #define USIC_CH_PCR_IICMode_SLAD_Msk (0x0000ffffUL << USIC_CH_PCR_IICMode_SLAD_Pos) /*!< USIC_CH PCR_IICMode: SLAD Mask */
\r
9035 #define USIC_CH_PCR_IICMode_ACK00_Pos 16 /*!< USIC_CH PCR_IICMode: ACK00 Position */
\r
9036 #define USIC_CH_PCR_IICMode_ACK00_Msk (0x01UL << USIC_CH_PCR_IICMode_ACK00_Pos) /*!< USIC_CH PCR_IICMode: ACK00 Mask */
\r
9037 #define USIC_CH_PCR_IICMode_STIM_Pos 17 /*!< USIC_CH PCR_IICMode: STIM Position */
\r
9038 #define USIC_CH_PCR_IICMode_STIM_Msk (0x01UL << USIC_CH_PCR_IICMode_STIM_Pos) /*!< USIC_CH PCR_IICMode: STIM Mask */
\r
9039 #define USIC_CH_PCR_IICMode_SCRIEN_Pos 18 /*!< USIC_CH PCR_IICMode: SCRIEN Position */
\r
9040 #define USIC_CH_PCR_IICMode_SCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_SCRIEN_Pos) /*!< USIC_CH PCR_IICMode: SCRIEN Mask */
\r
9041 #define USIC_CH_PCR_IICMode_RSCRIEN_Pos 19 /*!< USIC_CH PCR_IICMode: RSCRIEN Position */
\r
9042 #define USIC_CH_PCR_IICMode_RSCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_RSCRIEN_Pos) /*!< USIC_CH PCR_IICMode: RSCRIEN Mask */
\r
9043 #define USIC_CH_PCR_IICMode_PCRIEN_Pos 20 /*!< USIC_CH PCR_IICMode: PCRIEN Position */
\r
9044 #define USIC_CH_PCR_IICMode_PCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_PCRIEN_Pos) /*!< USIC_CH PCR_IICMode: PCRIEN Mask */
\r
9045 #define USIC_CH_PCR_IICMode_NACKIEN_Pos 21 /*!< USIC_CH PCR_IICMode: NACKIEN Position */
\r
9046 #define USIC_CH_PCR_IICMode_NACKIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_NACKIEN_Pos) /*!< USIC_CH PCR_IICMode: NACKIEN Mask */
\r
9047 #define USIC_CH_PCR_IICMode_ARLIEN_Pos 22 /*!< USIC_CH PCR_IICMode: ARLIEN Position */
\r
9048 #define USIC_CH_PCR_IICMode_ARLIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ARLIEN_Pos) /*!< USIC_CH PCR_IICMode: ARLIEN Mask */
\r
9049 #define USIC_CH_PCR_IICMode_SRRIEN_Pos 23 /*!< USIC_CH PCR_IICMode: SRRIEN Position */
\r
9050 #define USIC_CH_PCR_IICMode_SRRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_SRRIEN_Pos) /*!< USIC_CH PCR_IICMode: SRRIEN Mask */
\r
9051 #define USIC_CH_PCR_IICMode_ERRIEN_Pos 24 /*!< USIC_CH PCR_IICMode: ERRIEN Position */
\r
9052 #define USIC_CH_PCR_IICMode_ERRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ERRIEN_Pos) /*!< USIC_CH PCR_IICMode: ERRIEN Mask */
\r
9053 #define USIC_CH_PCR_IICMode_SACKDIS_Pos 25 /*!< USIC_CH PCR_IICMode: SACKDIS Position */
\r
9054 #define USIC_CH_PCR_IICMode_SACKDIS_Msk (0x01UL << USIC_CH_PCR_IICMode_SACKDIS_Pos) /*!< USIC_CH PCR_IICMode: SACKDIS Mask */
\r
9055 #define USIC_CH_PCR_IICMode_HDEL_Pos 26 /*!< USIC_CH PCR_IICMode: HDEL Position */
\r
9056 #define USIC_CH_PCR_IICMode_HDEL_Msk (0x0fUL << USIC_CH_PCR_IICMode_HDEL_Pos) /*!< USIC_CH PCR_IICMode: HDEL Mask */
\r
9057 #define USIC_CH_PCR_IICMode_ACKIEN_Pos 30 /*!< USIC_CH PCR_IICMode: ACKIEN Position */
\r
9058 #define USIC_CH_PCR_IICMode_ACKIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ACKIEN_Pos) /*!< USIC_CH PCR_IICMode: ACKIEN Mask */
\r
9059 #define USIC_CH_PCR_IICMode_MCLK_Pos 31 /*!< USIC_CH PCR_IICMode: MCLK Position */
\r
9060 #define USIC_CH_PCR_IICMode_MCLK_Msk (0x01UL << USIC_CH_PCR_IICMode_MCLK_Pos) /*!< USIC_CH PCR_IICMode: MCLK Mask */
\r
9062 /* ----------------------------- USIC_CH_PCR_IISMode ---------------------------- */
\r
9063 #define USIC_CH_PCR_IISMode_WAGEN_Pos 0 /*!< USIC_CH PCR_IISMode: WAGEN Position */
\r
9064 #define USIC_CH_PCR_IISMode_WAGEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAGEN_Pos) /*!< USIC_CH PCR_IISMode: WAGEN Mask */
\r
9065 #define USIC_CH_PCR_IISMode_DTEN_Pos 1 /*!< USIC_CH PCR_IISMode: DTEN Position */
\r
9066 #define USIC_CH_PCR_IISMode_DTEN_Msk (0x01UL << USIC_CH_PCR_IISMode_DTEN_Pos) /*!< USIC_CH PCR_IISMode: DTEN Mask */
\r
9067 #define USIC_CH_PCR_IISMode_SELINV_Pos 2 /*!< USIC_CH PCR_IISMode: SELINV Position */
\r
9068 #define USIC_CH_PCR_IISMode_SELINV_Msk (0x01UL << USIC_CH_PCR_IISMode_SELINV_Pos) /*!< USIC_CH PCR_IISMode: SELINV Mask */
\r
9069 #define USIC_CH_PCR_IISMode_WAFEIEN_Pos 4 /*!< USIC_CH PCR_IISMode: WAFEIEN Position */
\r
9070 #define USIC_CH_PCR_IISMode_WAFEIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAFEIEN_Pos) /*!< USIC_CH PCR_IISMode: WAFEIEN Mask */
\r
9071 #define USIC_CH_PCR_IISMode_WAREIEN_Pos 5 /*!< USIC_CH PCR_IISMode: WAREIEN Position */
\r
9072 #define USIC_CH_PCR_IISMode_WAREIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAREIEN_Pos) /*!< USIC_CH PCR_IISMode: WAREIEN Mask */
\r
9073 #define USIC_CH_PCR_IISMode_ENDIEN_Pos 6 /*!< USIC_CH PCR_IISMode: ENDIEN Position */
\r
9074 #define USIC_CH_PCR_IISMode_ENDIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_ENDIEN_Pos) /*!< USIC_CH PCR_IISMode: ENDIEN Mask */
\r
9075 #define USIC_CH_PCR_IISMode_DX2TIEN_Pos 15 /*!< USIC_CH PCR_IISMode: DX2TIEN Position */
\r
9076 #define USIC_CH_PCR_IISMode_DX2TIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_DX2TIEN_Pos) /*!< USIC_CH PCR_IISMode: DX2TIEN Mask */
\r
9077 #define USIC_CH_PCR_IISMode_TDEL_Pos 16 /*!< USIC_CH PCR_IISMode: TDEL Position */
\r
9078 #define USIC_CH_PCR_IISMode_TDEL_Msk (0x3fUL << USIC_CH_PCR_IISMode_TDEL_Pos) /*!< USIC_CH PCR_IISMode: TDEL Mask */
\r
9079 #define USIC_CH_PCR_IISMode_MCLK_Pos 31 /*!< USIC_CH PCR_IISMode: MCLK Position */
\r
9080 #define USIC_CH_PCR_IISMode_MCLK_Msk (0x01UL << USIC_CH_PCR_IISMode_MCLK_Pos) /*!< USIC_CH PCR_IISMode: MCLK Mask */
\r
9082 /* --------------------------------- USIC_CH_CCR -------------------------------- */
\r
9083 #define USIC_CH_CCR_MODE_Pos 0 /*!< USIC_CH CCR: MODE Position */
\r
9084 #define USIC_CH_CCR_MODE_Msk (0x0fUL << USIC_CH_CCR_MODE_Pos) /*!< USIC_CH CCR: MODE Mask */
\r
9085 #define USIC_CH_CCR_HPCEN_Pos 6 /*!< USIC_CH CCR: HPCEN Position */
\r
9086 #define USIC_CH_CCR_HPCEN_Msk (0x03UL << USIC_CH_CCR_HPCEN_Pos) /*!< USIC_CH CCR: HPCEN Mask */
\r
9087 #define USIC_CH_CCR_PM_Pos 8 /*!< USIC_CH CCR: PM Position */
\r
9088 #define USIC_CH_CCR_PM_Msk (0x03UL << USIC_CH_CCR_PM_Pos) /*!< USIC_CH CCR: PM Mask */
\r
9089 #define USIC_CH_CCR_RSIEN_Pos 10 /*!< USIC_CH CCR: RSIEN Position */
\r
9090 #define USIC_CH_CCR_RSIEN_Msk (0x01UL << USIC_CH_CCR_RSIEN_Pos) /*!< USIC_CH CCR: RSIEN Mask */
\r
9091 #define USIC_CH_CCR_DLIEN_Pos 11 /*!< USIC_CH CCR: DLIEN Position */
\r
9092 #define USIC_CH_CCR_DLIEN_Msk (0x01UL << USIC_CH_CCR_DLIEN_Pos) /*!< USIC_CH CCR: DLIEN Mask */
\r
9093 #define USIC_CH_CCR_TSIEN_Pos 12 /*!< USIC_CH CCR: TSIEN Position */
\r
9094 #define USIC_CH_CCR_TSIEN_Msk (0x01UL << USIC_CH_CCR_TSIEN_Pos) /*!< USIC_CH CCR: TSIEN Mask */
\r
9095 #define USIC_CH_CCR_TBIEN_Pos 13 /*!< USIC_CH CCR: TBIEN Position */
\r
9096 #define USIC_CH_CCR_TBIEN_Msk (0x01UL << USIC_CH_CCR_TBIEN_Pos) /*!< USIC_CH CCR: TBIEN Mask */
\r
9097 #define USIC_CH_CCR_RIEN_Pos 14 /*!< USIC_CH CCR: RIEN Position */
\r
9098 #define USIC_CH_CCR_RIEN_Msk (0x01UL << USIC_CH_CCR_RIEN_Pos) /*!< USIC_CH CCR: RIEN Mask */
\r
9099 #define USIC_CH_CCR_AIEN_Pos 15 /*!< USIC_CH CCR: AIEN Position */
\r
9100 #define USIC_CH_CCR_AIEN_Msk (0x01UL << USIC_CH_CCR_AIEN_Pos) /*!< USIC_CH CCR: AIEN Mask */
\r
9101 #define USIC_CH_CCR_BRGIEN_Pos 16 /*!< USIC_CH CCR: BRGIEN Position */
\r
9102 #define USIC_CH_CCR_BRGIEN_Msk (0x01UL << USIC_CH_CCR_BRGIEN_Pos) /*!< USIC_CH CCR: BRGIEN Mask */
\r
9104 /* -------------------------------- USIC_CH_CMTR -------------------------------- */
\r
9105 #define USIC_CH_CMTR_CTV_Pos 0 /*!< USIC_CH CMTR: CTV Position */
\r
9106 #define USIC_CH_CMTR_CTV_Msk (0x000003ffUL << USIC_CH_CMTR_CTV_Pos) /*!< USIC_CH CMTR: CTV Mask */
\r
9108 /* --------------------------------- USIC_CH_PSR -------------------------------- */
\r
9109 #define USIC_CH_PSR_ST0_Pos 0 /*!< USIC_CH PSR: ST0 Position */
\r
9110 #define USIC_CH_PSR_ST0_Msk (0x01UL << USIC_CH_PSR_ST0_Pos) /*!< USIC_CH PSR: ST0 Mask */
\r
9111 #define USIC_CH_PSR_ST1_Pos 1 /*!< USIC_CH PSR: ST1 Position */
\r
9112 #define USIC_CH_PSR_ST1_Msk (0x01UL << USIC_CH_PSR_ST1_Pos) /*!< USIC_CH PSR: ST1 Mask */
\r
9113 #define USIC_CH_PSR_ST2_Pos 2 /*!< USIC_CH PSR: ST2 Position */
\r
9114 #define USIC_CH_PSR_ST2_Msk (0x01UL << USIC_CH_PSR_ST2_Pos) /*!< USIC_CH PSR: ST2 Mask */
\r
9115 #define USIC_CH_PSR_ST3_Pos 3 /*!< USIC_CH PSR: ST3 Position */
\r
9116 #define USIC_CH_PSR_ST3_Msk (0x01UL << USIC_CH_PSR_ST3_Pos) /*!< USIC_CH PSR: ST3 Mask */
\r
9117 #define USIC_CH_PSR_ST4_Pos 4 /*!< USIC_CH PSR: ST4 Position */
\r
9118 #define USIC_CH_PSR_ST4_Msk (0x01UL << USIC_CH_PSR_ST4_Pos) /*!< USIC_CH PSR: ST4 Mask */
\r
9119 #define USIC_CH_PSR_ST5_Pos 5 /*!< USIC_CH PSR: ST5 Position */
\r
9120 #define USIC_CH_PSR_ST5_Msk (0x01UL << USIC_CH_PSR_ST5_Pos) /*!< USIC_CH PSR: ST5 Mask */
\r
9121 #define USIC_CH_PSR_ST6_Pos 6 /*!< USIC_CH PSR: ST6 Position */
\r
9122 #define USIC_CH_PSR_ST6_Msk (0x01UL << USIC_CH_PSR_ST6_Pos) /*!< USIC_CH PSR: ST6 Mask */
\r
9123 #define USIC_CH_PSR_ST7_Pos 7 /*!< USIC_CH PSR: ST7 Position */
\r
9124 #define USIC_CH_PSR_ST7_Msk (0x01UL << USIC_CH_PSR_ST7_Pos) /*!< USIC_CH PSR: ST7 Mask */
\r
9125 #define USIC_CH_PSR_ST8_Pos 8 /*!< USIC_CH PSR: ST8 Position */
\r
9126 #define USIC_CH_PSR_ST8_Msk (0x01UL << USIC_CH_PSR_ST8_Pos) /*!< USIC_CH PSR: ST8 Mask */
\r
9127 #define USIC_CH_PSR_ST9_Pos 9 /*!< USIC_CH PSR: ST9 Position */
\r
9128 #define USIC_CH_PSR_ST9_Msk (0x01UL << USIC_CH_PSR_ST9_Pos) /*!< USIC_CH PSR: ST9 Mask */
\r
9129 #define USIC_CH_PSR_RSIF_Pos 10 /*!< USIC_CH PSR: RSIF Position */
\r
9130 #define USIC_CH_PSR_RSIF_Msk (0x01UL << USIC_CH_PSR_RSIF_Pos) /*!< USIC_CH PSR: RSIF Mask */
\r
9131 #define USIC_CH_PSR_DLIF_Pos 11 /*!< USIC_CH PSR: DLIF Position */
\r
9132 #define USIC_CH_PSR_DLIF_Msk (0x01UL << USIC_CH_PSR_DLIF_Pos) /*!< USIC_CH PSR: DLIF Mask */
\r
9133 #define USIC_CH_PSR_TSIF_Pos 12 /*!< USIC_CH PSR: TSIF Position */
\r
9134 #define USIC_CH_PSR_TSIF_Msk (0x01UL << USIC_CH_PSR_TSIF_Pos) /*!< USIC_CH PSR: TSIF Mask */
\r
9135 #define USIC_CH_PSR_TBIF_Pos 13 /*!< USIC_CH PSR: TBIF Position */
\r
9136 #define USIC_CH_PSR_TBIF_Msk (0x01UL << USIC_CH_PSR_TBIF_Pos) /*!< USIC_CH PSR: TBIF Mask */
\r
9137 #define USIC_CH_PSR_RIF_Pos 14 /*!< USIC_CH PSR: RIF Position */
\r
9138 #define USIC_CH_PSR_RIF_Msk (0x01UL << USIC_CH_PSR_RIF_Pos) /*!< USIC_CH PSR: RIF Mask */
\r
9139 #define USIC_CH_PSR_AIF_Pos 15 /*!< USIC_CH PSR: AIF Position */
\r
9140 #define USIC_CH_PSR_AIF_Msk (0x01UL << USIC_CH_PSR_AIF_Pos) /*!< USIC_CH PSR: AIF Mask */
\r
9141 #define USIC_CH_PSR_BRGIF_Pos 16 /*!< USIC_CH PSR: BRGIF Position */
\r
9142 #define USIC_CH_PSR_BRGIF_Msk (0x01UL << USIC_CH_PSR_BRGIF_Pos) /*!< USIC_CH PSR: BRGIF Mask */
\r
9144 /* ----------------------------- USIC_CH_PSR_ASCMode ---------------------------- */
\r
9145 #define USIC_CH_PSR_ASCMode_TXIDLE_Pos 0 /*!< USIC_CH PSR_ASCMode: TXIDLE Position */
\r
9146 #define USIC_CH_PSR_ASCMode_TXIDLE_Msk (0x01UL << USIC_CH_PSR_ASCMode_TXIDLE_Pos) /*!< USIC_CH PSR_ASCMode: TXIDLE Mask */
\r
9147 #define USIC_CH_PSR_ASCMode_RXIDLE_Pos 1 /*!< USIC_CH PSR_ASCMode: RXIDLE Position */
\r
9148 #define USIC_CH_PSR_ASCMode_RXIDLE_Msk (0x01UL << USIC_CH_PSR_ASCMode_RXIDLE_Pos) /*!< USIC_CH PSR_ASCMode: RXIDLE Mask */
\r
9149 #define USIC_CH_PSR_ASCMode_SBD_Pos 2 /*!< USIC_CH PSR_ASCMode: SBD Position */
\r
9150 #define USIC_CH_PSR_ASCMode_SBD_Msk (0x01UL << USIC_CH_PSR_ASCMode_SBD_Pos) /*!< USIC_CH PSR_ASCMode: SBD Mask */
\r
9151 #define USIC_CH_PSR_ASCMode_COL_Pos 3 /*!< USIC_CH PSR_ASCMode: COL Position */
\r
9152 #define USIC_CH_PSR_ASCMode_COL_Msk (0x01UL << USIC_CH_PSR_ASCMode_COL_Pos) /*!< USIC_CH PSR_ASCMode: COL Mask */
\r
9153 #define USIC_CH_PSR_ASCMode_RNS_Pos 4 /*!< USIC_CH PSR_ASCMode: RNS Position */
\r
9154 #define USIC_CH_PSR_ASCMode_RNS_Msk (0x01UL << USIC_CH_PSR_ASCMode_RNS_Pos) /*!< USIC_CH PSR_ASCMode: RNS Mask */
\r
9155 #define USIC_CH_PSR_ASCMode_FER0_Pos 5 /*!< USIC_CH PSR_ASCMode: FER0 Position */
\r
9156 #define USIC_CH_PSR_ASCMode_FER0_Msk (0x01UL << USIC_CH_PSR_ASCMode_FER0_Pos) /*!< USIC_CH PSR_ASCMode: FER0 Mask */
\r
9157 #define USIC_CH_PSR_ASCMode_FER1_Pos 6 /*!< USIC_CH PSR_ASCMode: FER1 Position */
\r
9158 #define USIC_CH_PSR_ASCMode_FER1_Msk (0x01UL << USIC_CH_PSR_ASCMode_FER1_Pos) /*!< USIC_CH PSR_ASCMode: FER1 Mask */
\r
9159 #define USIC_CH_PSR_ASCMode_RFF_Pos 7 /*!< USIC_CH PSR_ASCMode: RFF Position */
\r
9160 #define USIC_CH_PSR_ASCMode_RFF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RFF_Pos) /*!< USIC_CH PSR_ASCMode: RFF Mask */
\r
9161 #define USIC_CH_PSR_ASCMode_TFF_Pos 8 /*!< USIC_CH PSR_ASCMode: TFF Position */
\r
9162 #define USIC_CH_PSR_ASCMode_TFF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TFF_Pos) /*!< USIC_CH PSR_ASCMode: TFF Mask */
\r
9163 #define USIC_CH_PSR_ASCMode_BUSY_Pos 9 /*!< USIC_CH PSR_ASCMode: BUSY Position */
\r
9164 #define USIC_CH_PSR_ASCMode_BUSY_Msk (0x01UL << USIC_CH_PSR_ASCMode_BUSY_Pos) /*!< USIC_CH PSR_ASCMode: BUSY Mask */
\r
9165 #define USIC_CH_PSR_ASCMode_RSIF_Pos 10 /*!< USIC_CH PSR_ASCMode: RSIF Position */
\r
9166 #define USIC_CH_PSR_ASCMode_RSIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RSIF_Pos) /*!< USIC_CH PSR_ASCMode: RSIF Mask */
\r
9167 #define USIC_CH_PSR_ASCMode_DLIF_Pos 11 /*!< USIC_CH PSR_ASCMode: DLIF Position */
\r
9168 #define USIC_CH_PSR_ASCMode_DLIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_DLIF_Pos) /*!< USIC_CH PSR_ASCMode: DLIF Mask */
\r
9169 #define USIC_CH_PSR_ASCMode_TSIF_Pos 12 /*!< USIC_CH PSR_ASCMode: TSIF Position */
\r
9170 #define USIC_CH_PSR_ASCMode_TSIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TSIF_Pos) /*!< USIC_CH PSR_ASCMode: TSIF Mask */
\r
9171 #define USIC_CH_PSR_ASCMode_TBIF_Pos 13 /*!< USIC_CH PSR_ASCMode: TBIF Position */
\r
9172 #define USIC_CH_PSR_ASCMode_TBIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TBIF_Pos) /*!< USIC_CH PSR_ASCMode: TBIF Mask */
\r
9173 #define USIC_CH_PSR_ASCMode_RIF_Pos 14 /*!< USIC_CH PSR_ASCMode: RIF Position */
\r
9174 #define USIC_CH_PSR_ASCMode_RIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RIF_Pos) /*!< USIC_CH PSR_ASCMode: RIF Mask */
\r
9175 #define USIC_CH_PSR_ASCMode_AIF_Pos 15 /*!< USIC_CH PSR_ASCMode: AIF Position */
\r
9176 #define USIC_CH_PSR_ASCMode_AIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_AIF_Pos) /*!< USIC_CH PSR_ASCMode: AIF Mask */
\r
9177 #define USIC_CH_PSR_ASCMode_BRGIF_Pos 16 /*!< USIC_CH PSR_ASCMode: BRGIF Position */
\r
9178 #define USIC_CH_PSR_ASCMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_BRGIF_Pos) /*!< USIC_CH PSR_ASCMode: BRGIF Mask */
\r
9180 /* ----------------------------- USIC_CH_PSR_SSCMode ---------------------------- */
\r
9181 #define USIC_CH_PSR_SSCMode_MSLS_Pos 0 /*!< USIC_CH PSR_SSCMode: MSLS Position */
\r
9182 #define USIC_CH_PSR_SSCMode_MSLS_Msk (0x01UL << USIC_CH_PSR_SSCMode_MSLS_Pos) /*!< USIC_CH PSR_SSCMode: MSLS Mask */
\r
9183 #define USIC_CH_PSR_SSCMode_DX2S_Pos 1 /*!< USIC_CH PSR_SSCMode: DX2S Position */
\r
9184 #define USIC_CH_PSR_SSCMode_DX2S_Msk (0x01UL << USIC_CH_PSR_SSCMode_DX2S_Pos) /*!< USIC_CH PSR_SSCMode: DX2S Mask */
\r
9185 #define USIC_CH_PSR_SSCMode_MSLSEV_Pos 2 /*!< USIC_CH PSR_SSCMode: MSLSEV Position */
\r
9186 #define USIC_CH_PSR_SSCMode_MSLSEV_Msk (0x01UL << USIC_CH_PSR_SSCMode_MSLSEV_Pos) /*!< USIC_CH PSR_SSCMode: MSLSEV Mask */
\r
9187 #define USIC_CH_PSR_SSCMode_DX2TEV_Pos 3 /*!< USIC_CH PSR_SSCMode: DX2TEV Position */
\r
9188 #define USIC_CH_PSR_SSCMode_DX2TEV_Msk (0x01UL << USIC_CH_PSR_SSCMode_DX2TEV_Pos) /*!< USIC_CH PSR_SSCMode: DX2TEV Mask */
\r
9189 #define USIC_CH_PSR_SSCMode_PARERR_Pos 4 /*!< USIC_CH PSR_SSCMode: PARERR Position */
\r
9190 #define USIC_CH_PSR_SSCMode_PARERR_Msk (0x01UL << USIC_CH_PSR_SSCMode_PARERR_Pos) /*!< USIC_CH PSR_SSCMode: PARERR Mask */
\r
9191 #define USIC_CH_PSR_SSCMode_RSIF_Pos 10 /*!< USIC_CH PSR_SSCMode: RSIF Position */
\r
9192 #define USIC_CH_PSR_SSCMode_RSIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_RSIF_Pos) /*!< USIC_CH PSR_SSCMode: RSIF Mask */
\r
9193 #define USIC_CH_PSR_SSCMode_DLIF_Pos 11 /*!< USIC_CH PSR_SSCMode: DLIF Position */
\r
9194 #define USIC_CH_PSR_SSCMode_DLIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_DLIF_Pos) /*!< USIC_CH PSR_SSCMode: DLIF Mask */
\r
9195 #define USIC_CH_PSR_SSCMode_TSIF_Pos 12 /*!< USIC_CH PSR_SSCMode: TSIF Position */
\r
9196 #define USIC_CH_PSR_SSCMode_TSIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_TSIF_Pos) /*!< USIC_CH PSR_SSCMode: TSIF Mask */
\r
9197 #define USIC_CH_PSR_SSCMode_TBIF_Pos 13 /*!< USIC_CH PSR_SSCMode: TBIF Position */
\r
9198 #define USIC_CH_PSR_SSCMode_TBIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_TBIF_Pos) /*!< USIC_CH PSR_SSCMode: TBIF Mask */
\r
9199 #define USIC_CH_PSR_SSCMode_RIF_Pos 14 /*!< USIC_CH PSR_SSCMode: RIF Position */
\r
9200 #define USIC_CH_PSR_SSCMode_RIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_RIF_Pos) /*!< USIC_CH PSR_SSCMode: RIF Mask */
\r
9201 #define USIC_CH_PSR_SSCMode_AIF_Pos 15 /*!< USIC_CH PSR_SSCMode: AIF Position */
\r
9202 #define USIC_CH_PSR_SSCMode_AIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_AIF_Pos) /*!< USIC_CH PSR_SSCMode: AIF Mask */
\r
9203 #define USIC_CH_PSR_SSCMode_BRGIF_Pos 16 /*!< USIC_CH PSR_SSCMode: BRGIF Position */
\r
9204 #define USIC_CH_PSR_SSCMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_BRGIF_Pos) /*!< USIC_CH PSR_SSCMode: BRGIF Mask */
\r
9206 /* ----------------------------- USIC_CH_PSR_IICMode ---------------------------- */
\r
9207 #define USIC_CH_PSR_IICMode_SLSEL_Pos 0 /*!< USIC_CH PSR_IICMode: SLSEL Position */
\r
9208 #define USIC_CH_PSR_IICMode_SLSEL_Msk (0x01UL << USIC_CH_PSR_IICMode_SLSEL_Pos) /*!< USIC_CH PSR_IICMode: SLSEL Mask */
\r
9209 #define USIC_CH_PSR_IICMode_WTDF_Pos 1 /*!< USIC_CH PSR_IICMode: WTDF Position */
\r
9210 #define USIC_CH_PSR_IICMode_WTDF_Msk (0x01UL << USIC_CH_PSR_IICMode_WTDF_Pos) /*!< USIC_CH PSR_IICMode: WTDF Mask */
\r
9211 #define USIC_CH_PSR_IICMode_SCR_Pos 2 /*!< USIC_CH PSR_IICMode: SCR Position */
\r
9212 #define USIC_CH_PSR_IICMode_SCR_Msk (0x01UL << USIC_CH_PSR_IICMode_SCR_Pos) /*!< USIC_CH PSR_IICMode: SCR Mask */
\r
9213 #define USIC_CH_PSR_IICMode_RSCR_Pos 3 /*!< USIC_CH PSR_IICMode: RSCR Position */
\r
9214 #define USIC_CH_PSR_IICMode_RSCR_Msk (0x01UL << USIC_CH_PSR_IICMode_RSCR_Pos) /*!< USIC_CH PSR_IICMode: RSCR Mask */
\r
9215 #define USIC_CH_PSR_IICMode_PCR_Pos 4 /*!< USIC_CH PSR_IICMode: PCR Position */
\r
9216 #define USIC_CH_PSR_IICMode_PCR_Msk (0x01UL << USIC_CH_PSR_IICMode_PCR_Pos) /*!< USIC_CH PSR_IICMode: PCR Mask */
\r
9217 #define USIC_CH_PSR_IICMode_NACK_Pos 5 /*!< USIC_CH PSR_IICMode: NACK Position */
\r
9218 #define USIC_CH_PSR_IICMode_NACK_Msk (0x01UL << USIC_CH_PSR_IICMode_NACK_Pos) /*!< USIC_CH PSR_IICMode: NACK Mask */
\r
9219 #define USIC_CH_PSR_IICMode_ARL_Pos 6 /*!< USIC_CH PSR_IICMode: ARL Position */
\r
9220 #define USIC_CH_PSR_IICMode_ARL_Msk (0x01UL << USIC_CH_PSR_IICMode_ARL_Pos) /*!< USIC_CH PSR_IICMode: ARL Mask */
\r
9221 #define USIC_CH_PSR_IICMode_SRR_Pos 7 /*!< USIC_CH PSR_IICMode: SRR Position */
\r
9222 #define USIC_CH_PSR_IICMode_SRR_Msk (0x01UL << USIC_CH_PSR_IICMode_SRR_Pos) /*!< USIC_CH PSR_IICMode: SRR Mask */
\r
9223 #define USIC_CH_PSR_IICMode_ERR_Pos 8 /*!< USIC_CH PSR_IICMode: ERR Position */
\r
9224 #define USIC_CH_PSR_IICMode_ERR_Msk (0x01UL << USIC_CH_PSR_IICMode_ERR_Pos) /*!< USIC_CH PSR_IICMode: ERR Mask */
\r
9225 #define USIC_CH_PSR_IICMode_ACK_Pos 9 /*!< USIC_CH PSR_IICMode: ACK Position */
\r
9226 #define USIC_CH_PSR_IICMode_ACK_Msk (0x01UL << USIC_CH_PSR_IICMode_ACK_Pos) /*!< USIC_CH PSR_IICMode: ACK Mask */
\r
9227 #define USIC_CH_PSR_IICMode_RSIF_Pos 10 /*!< USIC_CH PSR_IICMode: RSIF Position */
\r
9228 #define USIC_CH_PSR_IICMode_RSIF_Msk (0x01UL << USIC_CH_PSR_IICMode_RSIF_Pos) /*!< USIC_CH PSR_IICMode: RSIF Mask */
\r
9229 #define USIC_CH_PSR_IICMode_DLIF_Pos 11 /*!< USIC_CH PSR_IICMode: DLIF Position */
\r
9230 #define USIC_CH_PSR_IICMode_DLIF_Msk (0x01UL << USIC_CH_PSR_IICMode_DLIF_Pos) /*!< USIC_CH PSR_IICMode: DLIF Mask */
\r
9231 #define USIC_CH_PSR_IICMode_TSIF_Pos 12 /*!< USIC_CH PSR_IICMode: TSIF Position */
\r
9232 #define USIC_CH_PSR_IICMode_TSIF_Msk (0x01UL << USIC_CH_PSR_IICMode_TSIF_Pos) /*!< USIC_CH PSR_IICMode: TSIF Mask */
\r
9233 #define USIC_CH_PSR_IICMode_TBIF_Pos 13 /*!< USIC_CH PSR_IICMode: TBIF Position */
\r
9234 #define USIC_CH_PSR_IICMode_TBIF_Msk (0x01UL << USIC_CH_PSR_IICMode_TBIF_Pos) /*!< USIC_CH PSR_IICMode: TBIF Mask */
\r
9235 #define USIC_CH_PSR_IICMode_RIF_Pos 14 /*!< USIC_CH PSR_IICMode: RIF Position */
\r
9236 #define USIC_CH_PSR_IICMode_RIF_Msk (0x01UL << USIC_CH_PSR_IICMode_RIF_Pos) /*!< USIC_CH PSR_IICMode: RIF Mask */
\r
9237 #define USIC_CH_PSR_IICMode_AIF_Pos 15 /*!< USIC_CH PSR_IICMode: AIF Position */
\r
9238 #define USIC_CH_PSR_IICMode_AIF_Msk (0x01UL << USIC_CH_PSR_IICMode_AIF_Pos) /*!< USIC_CH PSR_IICMode: AIF Mask */
\r
9239 #define USIC_CH_PSR_IICMode_BRGIF_Pos 16 /*!< USIC_CH PSR_IICMode: BRGIF Position */
\r
9240 #define USIC_CH_PSR_IICMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_IICMode_BRGIF_Pos) /*!< USIC_CH PSR_IICMode: BRGIF Mask */
\r
9242 /* ----------------------------- USIC_CH_PSR_IISMode ---------------------------- */
\r
9243 #define USIC_CH_PSR_IISMode_WA_Pos 0 /*!< USIC_CH PSR_IISMode: WA Position */
\r
9244 #define USIC_CH_PSR_IISMode_WA_Msk (0x01UL << USIC_CH_PSR_IISMode_WA_Pos) /*!< USIC_CH PSR_IISMode: WA Mask */
\r
9245 #define USIC_CH_PSR_IISMode_DX2S_Pos 1 /*!< USIC_CH PSR_IISMode: DX2S Position */
\r
9246 #define USIC_CH_PSR_IISMode_DX2S_Msk (0x01UL << USIC_CH_PSR_IISMode_DX2S_Pos) /*!< USIC_CH PSR_IISMode: DX2S Mask */
\r
9247 #define USIC_CH_PSR_IISMode_DX2TEV_Pos 3 /*!< USIC_CH PSR_IISMode: DX2TEV Position */
\r
9248 #define USIC_CH_PSR_IISMode_DX2TEV_Msk (0x01UL << USIC_CH_PSR_IISMode_DX2TEV_Pos) /*!< USIC_CH PSR_IISMode: DX2TEV Mask */
\r
9249 #define USIC_CH_PSR_IISMode_WAFE_Pos 4 /*!< USIC_CH PSR_IISMode: WAFE Position */
\r
9250 #define USIC_CH_PSR_IISMode_WAFE_Msk (0x01UL << USIC_CH_PSR_IISMode_WAFE_Pos) /*!< USIC_CH PSR_IISMode: WAFE Mask */
\r
9251 #define USIC_CH_PSR_IISMode_WARE_Pos 5 /*!< USIC_CH PSR_IISMode: WARE Position */
\r
9252 #define USIC_CH_PSR_IISMode_WARE_Msk (0x01UL << USIC_CH_PSR_IISMode_WARE_Pos) /*!< USIC_CH PSR_IISMode: WARE Mask */
\r
9253 #define USIC_CH_PSR_IISMode_END_Pos 6 /*!< USIC_CH PSR_IISMode: END Position */
\r
9254 #define USIC_CH_PSR_IISMode_END_Msk (0x01UL << USIC_CH_PSR_IISMode_END_Pos) /*!< USIC_CH PSR_IISMode: END Mask */
\r
9255 #define USIC_CH_PSR_IISMode_RSIF_Pos 10 /*!< USIC_CH PSR_IISMode: RSIF Position */
\r
9256 #define USIC_CH_PSR_IISMode_RSIF_Msk (0x01UL << USIC_CH_PSR_IISMode_RSIF_Pos) /*!< USIC_CH PSR_IISMode: RSIF Mask */
\r
9257 #define USIC_CH_PSR_IISMode_DLIF_Pos 11 /*!< USIC_CH PSR_IISMode: DLIF Position */
\r
9258 #define USIC_CH_PSR_IISMode_DLIF_Msk (0x01UL << USIC_CH_PSR_IISMode_DLIF_Pos) /*!< USIC_CH PSR_IISMode: DLIF Mask */
\r
9259 #define USIC_CH_PSR_IISMode_TSIF_Pos 12 /*!< USIC_CH PSR_IISMode: TSIF Position */
\r
9260 #define USIC_CH_PSR_IISMode_TSIF_Msk (0x01UL << USIC_CH_PSR_IISMode_TSIF_Pos) /*!< USIC_CH PSR_IISMode: TSIF Mask */
\r
9261 #define USIC_CH_PSR_IISMode_TBIF_Pos 13 /*!< USIC_CH PSR_IISMode: TBIF Position */
\r
9262 #define USIC_CH_PSR_IISMode_TBIF_Msk (0x01UL << USIC_CH_PSR_IISMode_TBIF_Pos) /*!< USIC_CH PSR_IISMode: TBIF Mask */
\r
9263 #define USIC_CH_PSR_IISMode_RIF_Pos 14 /*!< USIC_CH PSR_IISMode: RIF Position */
\r
9264 #define USIC_CH_PSR_IISMode_RIF_Msk (0x01UL << USIC_CH_PSR_IISMode_RIF_Pos) /*!< USIC_CH PSR_IISMode: RIF Mask */
\r
9265 #define USIC_CH_PSR_IISMode_AIF_Pos 15 /*!< USIC_CH PSR_IISMode: AIF Position */
\r
9266 #define USIC_CH_PSR_IISMode_AIF_Msk (0x01UL << USIC_CH_PSR_IISMode_AIF_Pos) /*!< USIC_CH PSR_IISMode: AIF Mask */
\r
9267 #define USIC_CH_PSR_IISMode_BRGIF_Pos 16 /*!< USIC_CH PSR_IISMode: BRGIF Position */
\r
9268 #define USIC_CH_PSR_IISMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_IISMode_BRGIF_Pos) /*!< USIC_CH PSR_IISMode: BRGIF Mask */
\r
9270 /* -------------------------------- USIC_CH_PSCR -------------------------------- */
\r
9271 #define USIC_CH_PSCR_CST0_Pos 0 /*!< USIC_CH PSCR: CST0 Position */
\r
9272 #define USIC_CH_PSCR_CST0_Msk (0x01UL << USIC_CH_PSCR_CST0_Pos) /*!< USIC_CH PSCR: CST0 Mask */
\r
9273 #define USIC_CH_PSCR_CST1_Pos 1 /*!< USIC_CH PSCR: CST1 Position */
\r
9274 #define USIC_CH_PSCR_CST1_Msk (0x01UL << USIC_CH_PSCR_CST1_Pos) /*!< USIC_CH PSCR: CST1 Mask */
\r
9275 #define USIC_CH_PSCR_CST2_Pos 2 /*!< USIC_CH PSCR: CST2 Position */
\r
9276 #define USIC_CH_PSCR_CST2_Msk (0x01UL << USIC_CH_PSCR_CST2_Pos) /*!< USIC_CH PSCR: CST2 Mask */
\r
9277 #define USIC_CH_PSCR_CST3_Pos 3 /*!< USIC_CH PSCR: CST3 Position */
\r
9278 #define USIC_CH_PSCR_CST3_Msk (0x01UL << USIC_CH_PSCR_CST3_Pos) /*!< USIC_CH PSCR: CST3 Mask */
\r
9279 #define USIC_CH_PSCR_CST4_Pos 4 /*!< USIC_CH PSCR: CST4 Position */
\r
9280 #define USIC_CH_PSCR_CST4_Msk (0x01UL << USIC_CH_PSCR_CST4_Pos) /*!< USIC_CH PSCR: CST4 Mask */
\r
9281 #define USIC_CH_PSCR_CST5_Pos 5 /*!< USIC_CH PSCR: CST5 Position */
\r
9282 #define USIC_CH_PSCR_CST5_Msk (0x01UL << USIC_CH_PSCR_CST5_Pos) /*!< USIC_CH PSCR: CST5 Mask */
\r
9283 #define USIC_CH_PSCR_CST6_Pos 6 /*!< USIC_CH PSCR: CST6 Position */
\r
9284 #define USIC_CH_PSCR_CST6_Msk (0x01UL << USIC_CH_PSCR_CST6_Pos) /*!< USIC_CH PSCR: CST6 Mask */
\r
9285 #define USIC_CH_PSCR_CST7_Pos 7 /*!< USIC_CH PSCR: CST7 Position */
\r
9286 #define USIC_CH_PSCR_CST7_Msk (0x01UL << USIC_CH_PSCR_CST7_Pos) /*!< USIC_CH PSCR: CST7 Mask */
\r
9287 #define USIC_CH_PSCR_CST8_Pos 8 /*!< USIC_CH PSCR: CST8 Position */
\r
9288 #define USIC_CH_PSCR_CST8_Msk (0x01UL << USIC_CH_PSCR_CST8_Pos) /*!< USIC_CH PSCR: CST8 Mask */
\r
9289 #define USIC_CH_PSCR_CST9_Pos 9 /*!< USIC_CH PSCR: CST9 Position */
\r
9290 #define USIC_CH_PSCR_CST9_Msk (0x01UL << USIC_CH_PSCR_CST9_Pos) /*!< USIC_CH PSCR: CST9 Mask */
\r
9291 #define USIC_CH_PSCR_CRSIF_Pos 10 /*!< USIC_CH PSCR: CRSIF Position */
\r
9292 #define USIC_CH_PSCR_CRSIF_Msk (0x01UL << USIC_CH_PSCR_CRSIF_Pos) /*!< USIC_CH PSCR: CRSIF Mask */
\r
9293 #define USIC_CH_PSCR_CDLIF_Pos 11 /*!< USIC_CH PSCR: CDLIF Position */
\r
9294 #define USIC_CH_PSCR_CDLIF_Msk (0x01UL << USIC_CH_PSCR_CDLIF_Pos) /*!< USIC_CH PSCR: CDLIF Mask */
\r
9295 #define USIC_CH_PSCR_CTSIF_Pos 12 /*!< USIC_CH PSCR: CTSIF Position */
\r
9296 #define USIC_CH_PSCR_CTSIF_Msk (0x01UL << USIC_CH_PSCR_CTSIF_Pos) /*!< USIC_CH PSCR: CTSIF Mask */
\r
9297 #define USIC_CH_PSCR_CTBIF_Pos 13 /*!< USIC_CH PSCR: CTBIF Position */
\r
9298 #define USIC_CH_PSCR_CTBIF_Msk (0x01UL << USIC_CH_PSCR_CTBIF_Pos) /*!< USIC_CH PSCR: CTBIF Mask */
\r
9299 #define USIC_CH_PSCR_CRIF_Pos 14 /*!< USIC_CH PSCR: CRIF Position */
\r
9300 #define USIC_CH_PSCR_CRIF_Msk (0x01UL << USIC_CH_PSCR_CRIF_Pos) /*!< USIC_CH PSCR: CRIF Mask */
\r
9301 #define USIC_CH_PSCR_CAIF_Pos 15 /*!< USIC_CH PSCR: CAIF Position */
\r
9302 #define USIC_CH_PSCR_CAIF_Msk (0x01UL << USIC_CH_PSCR_CAIF_Pos) /*!< USIC_CH PSCR: CAIF Mask */
\r
9303 #define USIC_CH_PSCR_CBRGIF_Pos 16 /*!< USIC_CH PSCR: CBRGIF Position */
\r
9304 #define USIC_CH_PSCR_CBRGIF_Msk (0x01UL << USIC_CH_PSCR_CBRGIF_Pos) /*!< USIC_CH PSCR: CBRGIF Mask */
\r
9306 /* ------------------------------- USIC_CH_RBUFSR ------------------------------- */
\r
9307 #define USIC_CH_RBUFSR_WLEN_Pos 0 /*!< USIC_CH RBUFSR: WLEN Position */
\r
9308 #define USIC_CH_RBUFSR_WLEN_Msk (0x0fUL << USIC_CH_RBUFSR_WLEN_Pos) /*!< USIC_CH RBUFSR: WLEN Mask */
\r
9309 #define USIC_CH_RBUFSR_SOF_Pos 6 /*!< USIC_CH RBUFSR: SOF Position */
\r
9310 #define USIC_CH_RBUFSR_SOF_Msk (0x01UL << USIC_CH_RBUFSR_SOF_Pos) /*!< USIC_CH RBUFSR: SOF Mask */
\r
9311 #define USIC_CH_RBUFSR_PAR_Pos 8 /*!< USIC_CH RBUFSR: PAR Position */
\r
9312 #define USIC_CH_RBUFSR_PAR_Msk (0x01UL << USIC_CH_RBUFSR_PAR_Pos) /*!< USIC_CH RBUFSR: PAR Mask */
\r
9313 #define USIC_CH_RBUFSR_PERR_Pos 9 /*!< USIC_CH RBUFSR: PERR Position */
\r
9314 #define USIC_CH_RBUFSR_PERR_Msk (0x01UL << USIC_CH_RBUFSR_PERR_Pos) /*!< USIC_CH RBUFSR: PERR Mask */
\r
9315 #define USIC_CH_RBUFSR_RDV0_Pos 13 /*!< USIC_CH RBUFSR: RDV0 Position */
\r
9316 #define USIC_CH_RBUFSR_RDV0_Msk (0x01UL << USIC_CH_RBUFSR_RDV0_Pos) /*!< USIC_CH RBUFSR: RDV0 Mask */
\r
9317 #define USIC_CH_RBUFSR_RDV1_Pos 14 /*!< USIC_CH RBUFSR: RDV1 Position */
\r
9318 #define USIC_CH_RBUFSR_RDV1_Msk (0x01UL << USIC_CH_RBUFSR_RDV1_Pos) /*!< USIC_CH RBUFSR: RDV1 Mask */
\r
9319 #define USIC_CH_RBUFSR_DS_Pos 15 /*!< USIC_CH RBUFSR: DS Position */
\r
9320 #define USIC_CH_RBUFSR_DS_Msk (0x01UL << USIC_CH_RBUFSR_DS_Pos) /*!< USIC_CH RBUFSR: DS Mask */
\r
9322 /* -------------------------------- USIC_CH_RBUF -------------------------------- */
\r
9323 #define USIC_CH_RBUF_DSR_Pos 0 /*!< USIC_CH RBUF: DSR Position */
\r
9324 #define USIC_CH_RBUF_DSR_Msk (0x0000ffffUL << USIC_CH_RBUF_DSR_Pos) /*!< USIC_CH RBUF: DSR Mask */
\r
9326 /* -------------------------------- USIC_CH_RBUFD ------------------------------- */
\r
9327 #define USIC_CH_RBUFD_DSR_Pos 0 /*!< USIC_CH RBUFD: DSR Position */
\r
9328 #define USIC_CH_RBUFD_DSR_Msk (0x0000ffffUL << USIC_CH_RBUFD_DSR_Pos) /*!< USIC_CH RBUFD: DSR Mask */
\r
9330 /* -------------------------------- USIC_CH_RBUF0 ------------------------------- */
\r
9331 #define USIC_CH_RBUF0_DSR0_Pos 0 /*!< USIC_CH RBUF0: DSR0 Position */
\r
9332 #define USIC_CH_RBUF0_DSR0_Msk (0x0000ffffUL << USIC_CH_RBUF0_DSR0_Pos) /*!< USIC_CH RBUF0: DSR0 Mask */
\r
9334 /* -------------------------------- USIC_CH_RBUF1 ------------------------------- */
\r
9335 #define USIC_CH_RBUF1_DSR1_Pos 0 /*!< USIC_CH RBUF1: DSR1 Position */
\r
9336 #define USIC_CH_RBUF1_DSR1_Msk (0x0000ffffUL << USIC_CH_RBUF1_DSR1_Pos) /*!< USIC_CH RBUF1: DSR1 Mask */
\r
9338 /* ------------------------------ USIC_CH_RBUF01SR ------------------------------ */
\r
9339 #define USIC_CH_RBUF01SR_WLEN0_Pos 0 /*!< USIC_CH RBUF01SR: WLEN0 Position */
\r
9340 #define USIC_CH_RBUF01SR_WLEN0_Msk (0x0fUL << USIC_CH_RBUF01SR_WLEN0_Pos) /*!< USIC_CH RBUF01SR: WLEN0 Mask */
\r
9341 #define USIC_CH_RBUF01SR_SOF0_Pos 6 /*!< USIC_CH RBUF01SR: SOF0 Position */
\r
9342 #define USIC_CH_RBUF01SR_SOF0_Msk (0x01UL << USIC_CH_RBUF01SR_SOF0_Pos) /*!< USIC_CH RBUF01SR: SOF0 Mask */
\r
9343 #define USIC_CH_RBUF01SR_PAR0_Pos 8 /*!< USIC_CH RBUF01SR: PAR0 Position */
\r
9344 #define USIC_CH_RBUF01SR_PAR0_Msk (0x01UL << USIC_CH_RBUF01SR_PAR0_Pos) /*!< USIC_CH RBUF01SR: PAR0 Mask */
\r
9345 #define USIC_CH_RBUF01SR_PERR0_Pos 9 /*!< USIC_CH RBUF01SR: PERR0 Position */
\r
9346 #define USIC_CH_RBUF01SR_PERR0_Msk (0x01UL << USIC_CH_RBUF01SR_PERR0_Pos) /*!< USIC_CH RBUF01SR: PERR0 Mask */
\r
9347 #define USIC_CH_RBUF01SR_RDV00_Pos 13 /*!< USIC_CH RBUF01SR: RDV00 Position */
\r
9348 #define USIC_CH_RBUF01SR_RDV00_Msk (0x01UL << USIC_CH_RBUF01SR_RDV00_Pos) /*!< USIC_CH RBUF01SR: RDV00 Mask */
\r
9349 #define USIC_CH_RBUF01SR_RDV01_Pos 14 /*!< USIC_CH RBUF01SR: RDV01 Position */
\r
9350 #define USIC_CH_RBUF01SR_RDV01_Msk (0x01UL << USIC_CH_RBUF01SR_RDV01_Pos) /*!< USIC_CH RBUF01SR: RDV01 Mask */
\r
9351 #define USIC_CH_RBUF01SR_DS0_Pos 15 /*!< USIC_CH RBUF01SR: DS0 Position */
\r
9352 #define USIC_CH_RBUF01SR_DS0_Msk (0x01UL << USIC_CH_RBUF01SR_DS0_Pos) /*!< USIC_CH RBUF01SR: DS0 Mask */
\r
9353 #define USIC_CH_RBUF01SR_WLEN1_Pos 16 /*!< USIC_CH RBUF01SR: WLEN1 Position */
\r
9354 #define USIC_CH_RBUF01SR_WLEN1_Msk (0x0fUL << USIC_CH_RBUF01SR_WLEN1_Pos) /*!< USIC_CH RBUF01SR: WLEN1 Mask */
\r
9355 #define USIC_CH_RBUF01SR_SOF1_Pos 22 /*!< USIC_CH RBUF01SR: SOF1 Position */
\r
9356 #define USIC_CH_RBUF01SR_SOF1_Msk (0x01UL << USIC_CH_RBUF01SR_SOF1_Pos) /*!< USIC_CH RBUF01SR: SOF1 Mask */
\r
9357 #define USIC_CH_RBUF01SR_PAR1_Pos 24 /*!< USIC_CH RBUF01SR: PAR1 Position */
\r
9358 #define USIC_CH_RBUF01SR_PAR1_Msk (0x01UL << USIC_CH_RBUF01SR_PAR1_Pos) /*!< USIC_CH RBUF01SR: PAR1 Mask */
\r
9359 #define USIC_CH_RBUF01SR_PERR1_Pos 25 /*!< USIC_CH RBUF01SR: PERR1 Position */
\r
9360 #define USIC_CH_RBUF01SR_PERR1_Msk (0x01UL << USIC_CH_RBUF01SR_PERR1_Pos) /*!< USIC_CH RBUF01SR: PERR1 Mask */
\r
9361 #define USIC_CH_RBUF01SR_RDV10_Pos 29 /*!< USIC_CH RBUF01SR: RDV10 Position */
\r
9362 #define USIC_CH_RBUF01SR_RDV10_Msk (0x01UL << USIC_CH_RBUF01SR_RDV10_Pos) /*!< USIC_CH RBUF01SR: RDV10 Mask */
\r
9363 #define USIC_CH_RBUF01SR_RDV11_Pos 30 /*!< USIC_CH RBUF01SR: RDV11 Position */
\r
9364 #define USIC_CH_RBUF01SR_RDV11_Msk (0x01UL << USIC_CH_RBUF01SR_RDV11_Pos) /*!< USIC_CH RBUF01SR: RDV11 Mask */
\r
9365 #define USIC_CH_RBUF01SR_DS1_Pos 31 /*!< USIC_CH RBUF01SR: DS1 Position */
\r
9366 #define USIC_CH_RBUF01SR_DS1_Msk (0x01UL << USIC_CH_RBUF01SR_DS1_Pos) /*!< USIC_CH RBUF01SR: DS1 Mask */
\r
9368 /* --------------------------------- USIC_CH_FMR -------------------------------- */
\r
9369 #define USIC_CH_FMR_MTDV_Pos 0 /*!< USIC_CH FMR: MTDV Position */
\r
9370 #define USIC_CH_FMR_MTDV_Msk (0x03UL << USIC_CH_FMR_MTDV_Pos) /*!< USIC_CH FMR: MTDV Mask */
\r
9371 #define USIC_CH_FMR_ATVC_Pos 4 /*!< USIC_CH FMR: ATVC Position */
\r
9372 #define USIC_CH_FMR_ATVC_Msk (0x01UL << USIC_CH_FMR_ATVC_Pos) /*!< USIC_CH FMR: ATVC Mask */
\r
9373 #define USIC_CH_FMR_CRDV0_Pos 14 /*!< USIC_CH FMR: CRDV0 Position */
\r
9374 #define USIC_CH_FMR_CRDV0_Msk (0x01UL << USIC_CH_FMR_CRDV0_Pos) /*!< USIC_CH FMR: CRDV0 Mask */
\r
9375 #define USIC_CH_FMR_CRDV1_Pos 15 /*!< USIC_CH FMR: CRDV1 Position */
\r
9376 #define USIC_CH_FMR_CRDV1_Msk (0x01UL << USIC_CH_FMR_CRDV1_Pos) /*!< USIC_CH FMR: CRDV1 Mask */
\r
9377 #define USIC_CH_FMR_SIO0_Pos 16 /*!< USIC_CH FMR: SIO0 Position */
\r
9378 #define USIC_CH_FMR_SIO0_Msk (0x01UL << USIC_CH_FMR_SIO0_Pos) /*!< USIC_CH FMR: SIO0 Mask */
\r
9379 #define USIC_CH_FMR_SIO1_Pos 17 /*!< USIC_CH FMR: SIO1 Position */
\r
9380 #define USIC_CH_FMR_SIO1_Msk (0x01UL << USIC_CH_FMR_SIO1_Pos) /*!< USIC_CH FMR: SIO1 Mask */
\r
9381 #define USIC_CH_FMR_SIO2_Pos 18 /*!< USIC_CH FMR: SIO2 Position */
\r
9382 #define USIC_CH_FMR_SIO2_Msk (0x01UL << USIC_CH_FMR_SIO2_Pos) /*!< USIC_CH FMR: SIO2 Mask */
\r
9383 #define USIC_CH_FMR_SIO3_Pos 19 /*!< USIC_CH FMR: SIO3 Position */
\r
9384 #define USIC_CH_FMR_SIO3_Msk (0x01UL << USIC_CH_FMR_SIO3_Pos) /*!< USIC_CH FMR: SIO3 Mask */
\r
9385 #define USIC_CH_FMR_SIO4_Pos 20 /*!< USIC_CH FMR: SIO4 Position */
\r
9386 #define USIC_CH_FMR_SIO4_Msk (0x01UL << USIC_CH_FMR_SIO4_Pos) /*!< USIC_CH FMR: SIO4 Mask */
\r
9387 #define USIC_CH_FMR_SIO5_Pos 21 /*!< USIC_CH FMR: SIO5 Position */
\r
9388 #define USIC_CH_FMR_SIO5_Msk (0x01UL << USIC_CH_FMR_SIO5_Pos) /*!< USIC_CH FMR: SIO5 Mask */
\r
9390 /* -------------------------------- USIC_CH_TBUF -------------------------------- */
\r
9391 #define USIC_CH_TBUF_TDATA_Pos 0 /*!< USIC_CH TBUF: TDATA Position */
\r
9392 #define USIC_CH_TBUF_TDATA_Msk (0x0000ffffUL << USIC_CH_TBUF_TDATA_Pos) /*!< USIC_CH TBUF: TDATA Mask */
\r
9394 /* --------------------------------- USIC_CH_BYP -------------------------------- */
\r
9395 #define USIC_CH_BYP_BDATA_Pos 0 /*!< USIC_CH BYP: BDATA Position */
\r
9396 #define USIC_CH_BYP_BDATA_Msk (0x0000ffffUL << USIC_CH_BYP_BDATA_Pos) /*!< USIC_CH BYP: BDATA Mask */
\r
9398 /* -------------------------------- USIC_CH_BYPCR ------------------------------- */
\r
9399 #define USIC_CH_BYPCR_BWLE_Pos 0 /*!< USIC_CH BYPCR: BWLE Position */
\r
9400 #define USIC_CH_BYPCR_BWLE_Msk (0x0fUL << USIC_CH_BYPCR_BWLE_Pos) /*!< USIC_CH BYPCR: BWLE Mask */
\r
9401 #define USIC_CH_BYPCR_BDSSM_Pos 8 /*!< USIC_CH BYPCR: BDSSM Position */
\r
9402 #define USIC_CH_BYPCR_BDSSM_Msk (0x01UL << USIC_CH_BYPCR_BDSSM_Pos) /*!< USIC_CH BYPCR: BDSSM Mask */
\r
9403 #define USIC_CH_BYPCR_BDEN_Pos 10 /*!< USIC_CH BYPCR: BDEN Position */
\r
9404 #define USIC_CH_BYPCR_BDEN_Msk (0x03UL << USIC_CH_BYPCR_BDEN_Pos) /*!< USIC_CH BYPCR: BDEN Mask */
\r
9405 #define USIC_CH_BYPCR_BDVTR_Pos 12 /*!< USIC_CH BYPCR: BDVTR Position */
\r
9406 #define USIC_CH_BYPCR_BDVTR_Msk (0x01UL << USIC_CH_BYPCR_BDVTR_Pos) /*!< USIC_CH BYPCR: BDVTR Mask */
\r
9407 #define USIC_CH_BYPCR_BPRIO_Pos 13 /*!< USIC_CH BYPCR: BPRIO Position */
\r
9408 #define USIC_CH_BYPCR_BPRIO_Msk (0x01UL << USIC_CH_BYPCR_BPRIO_Pos) /*!< USIC_CH BYPCR: BPRIO Mask */
\r
9409 #define USIC_CH_BYPCR_BDV_Pos 15 /*!< USIC_CH BYPCR: BDV Position */
\r
9410 #define USIC_CH_BYPCR_BDV_Msk (0x01UL << USIC_CH_BYPCR_BDV_Pos) /*!< USIC_CH BYPCR: BDV Mask */
\r
9411 #define USIC_CH_BYPCR_BSELO_Pos 16 /*!< USIC_CH BYPCR: BSELO Position */
\r
9412 #define USIC_CH_BYPCR_BSELO_Msk (0x1fUL << USIC_CH_BYPCR_BSELO_Pos) /*!< USIC_CH BYPCR: BSELO Mask */
\r
9413 #define USIC_CH_BYPCR_BHPC_Pos 21 /*!< USIC_CH BYPCR: BHPC Position */
\r
9414 #define USIC_CH_BYPCR_BHPC_Msk (0x07UL << USIC_CH_BYPCR_BHPC_Pos) /*!< USIC_CH BYPCR: BHPC Mask */
\r
9416 /* -------------------------------- USIC_CH_TBCTR ------------------------------- */
\r
9417 #define USIC_CH_TBCTR_DPTR_Pos 0 /*!< USIC_CH TBCTR: DPTR Position */
\r
9418 #define USIC_CH_TBCTR_DPTR_Msk (0x3fUL << USIC_CH_TBCTR_DPTR_Pos) /*!< USIC_CH TBCTR: DPTR Mask */
\r
9419 #define USIC_CH_TBCTR_LIMIT_Pos 8 /*!< USIC_CH TBCTR: LIMIT Position */
\r
9420 #define USIC_CH_TBCTR_LIMIT_Msk (0x3fUL << USIC_CH_TBCTR_LIMIT_Pos) /*!< USIC_CH TBCTR: LIMIT Mask */
\r
9421 #define USIC_CH_TBCTR_STBTM_Pos 14 /*!< USIC_CH TBCTR: STBTM Position */
\r
9422 #define USIC_CH_TBCTR_STBTM_Msk (0x01UL << USIC_CH_TBCTR_STBTM_Pos) /*!< USIC_CH TBCTR: STBTM Mask */
\r
9423 #define USIC_CH_TBCTR_STBTEN_Pos 15 /*!< USIC_CH TBCTR: STBTEN Position */
\r
9424 #define USIC_CH_TBCTR_STBTEN_Msk (0x01UL << USIC_CH_TBCTR_STBTEN_Pos) /*!< USIC_CH TBCTR: STBTEN Mask */
\r
9425 #define USIC_CH_TBCTR_STBINP_Pos 16 /*!< USIC_CH TBCTR: STBINP Position */
\r
9426 #define USIC_CH_TBCTR_STBINP_Msk (0x07UL << USIC_CH_TBCTR_STBINP_Pos) /*!< USIC_CH TBCTR: STBINP Mask */
\r
9427 #define USIC_CH_TBCTR_ATBINP_Pos 19 /*!< USIC_CH TBCTR: ATBINP Position */
\r
9428 #define USIC_CH_TBCTR_ATBINP_Msk (0x07UL << USIC_CH_TBCTR_ATBINP_Pos) /*!< USIC_CH TBCTR: ATBINP Mask */
\r
9429 #define USIC_CH_TBCTR_SIZE_Pos 24 /*!< USIC_CH TBCTR: SIZE Position */
\r
9430 #define USIC_CH_TBCTR_SIZE_Msk (0x07UL << USIC_CH_TBCTR_SIZE_Pos) /*!< USIC_CH TBCTR: SIZE Mask */
\r
9431 #define USIC_CH_TBCTR_LOF_Pos 28 /*!< USIC_CH TBCTR: LOF Position */
\r
9432 #define USIC_CH_TBCTR_LOF_Msk (0x01UL << USIC_CH_TBCTR_LOF_Pos) /*!< USIC_CH TBCTR: LOF Mask */
\r
9433 #define USIC_CH_TBCTR_STBIEN_Pos 30 /*!< USIC_CH TBCTR: STBIEN Position */
\r
9434 #define USIC_CH_TBCTR_STBIEN_Msk (0x01UL << USIC_CH_TBCTR_STBIEN_Pos) /*!< USIC_CH TBCTR: STBIEN Mask */
\r
9435 #define USIC_CH_TBCTR_TBERIEN_Pos 31 /*!< USIC_CH TBCTR: TBERIEN Position */
\r
9436 #define USIC_CH_TBCTR_TBERIEN_Msk (0x01UL << USIC_CH_TBCTR_TBERIEN_Pos) /*!< USIC_CH TBCTR: TBERIEN Mask */
\r
9438 /* -------------------------------- USIC_CH_RBCTR ------------------------------- */
\r
9439 #define USIC_CH_RBCTR_DPTR_Pos 0 /*!< USIC_CH RBCTR: DPTR Position */
\r
9440 #define USIC_CH_RBCTR_DPTR_Msk (0x3fUL << USIC_CH_RBCTR_DPTR_Pos) /*!< USIC_CH RBCTR: DPTR Mask */
\r
9441 #define USIC_CH_RBCTR_LIMIT_Pos 8 /*!< USIC_CH RBCTR: LIMIT Position */
\r
9442 #define USIC_CH_RBCTR_LIMIT_Msk (0x3fUL << USIC_CH_RBCTR_LIMIT_Pos) /*!< USIC_CH RBCTR: LIMIT Mask */
\r
9443 #define USIC_CH_RBCTR_SRBTM_Pos 14 /*!< USIC_CH RBCTR: SRBTM Position */
\r
9444 #define USIC_CH_RBCTR_SRBTM_Msk (0x01UL << USIC_CH_RBCTR_SRBTM_Pos) /*!< USIC_CH RBCTR: SRBTM Mask */
\r
9445 #define USIC_CH_RBCTR_SRBTEN_Pos 15 /*!< USIC_CH RBCTR: SRBTEN Position */
\r
9446 #define USIC_CH_RBCTR_SRBTEN_Msk (0x01UL << USIC_CH_RBCTR_SRBTEN_Pos) /*!< USIC_CH RBCTR: SRBTEN Mask */
\r
9447 #define USIC_CH_RBCTR_SRBINP_Pos 16 /*!< USIC_CH RBCTR: SRBINP Position */
\r
9448 #define USIC_CH_RBCTR_SRBINP_Msk (0x07UL << USIC_CH_RBCTR_SRBINP_Pos) /*!< USIC_CH RBCTR: SRBINP Mask */
\r
9449 #define USIC_CH_RBCTR_ARBINP_Pos 19 /*!< USIC_CH RBCTR: ARBINP Position */
\r
9450 #define USIC_CH_RBCTR_ARBINP_Msk (0x07UL << USIC_CH_RBCTR_ARBINP_Pos) /*!< USIC_CH RBCTR: ARBINP Mask */
\r
9451 #define USIC_CH_RBCTR_RCIM_Pos 22 /*!< USIC_CH RBCTR: RCIM Position */
\r
9452 #define USIC_CH_RBCTR_RCIM_Msk (0x03UL << USIC_CH_RBCTR_RCIM_Pos) /*!< USIC_CH RBCTR: RCIM Mask */
\r
9453 #define USIC_CH_RBCTR_SIZE_Pos 24 /*!< USIC_CH RBCTR: SIZE Position */
\r
9454 #define USIC_CH_RBCTR_SIZE_Msk (0x07UL << USIC_CH_RBCTR_SIZE_Pos) /*!< USIC_CH RBCTR: SIZE Mask */
\r
9455 #define USIC_CH_RBCTR_RNM_Pos 27 /*!< USIC_CH RBCTR: RNM Position */
\r
9456 #define USIC_CH_RBCTR_RNM_Msk (0x01UL << USIC_CH_RBCTR_RNM_Pos) /*!< USIC_CH RBCTR: RNM Mask */
\r
9457 #define USIC_CH_RBCTR_LOF_Pos 28 /*!< USIC_CH RBCTR: LOF Position */
\r
9458 #define USIC_CH_RBCTR_LOF_Msk (0x01UL << USIC_CH_RBCTR_LOF_Pos) /*!< USIC_CH RBCTR: LOF Mask */
\r
9459 #define USIC_CH_RBCTR_ARBIEN_Pos 29 /*!< USIC_CH RBCTR: ARBIEN Position */
\r
9460 #define USIC_CH_RBCTR_ARBIEN_Msk (0x01UL << USIC_CH_RBCTR_ARBIEN_Pos) /*!< USIC_CH RBCTR: ARBIEN Mask */
\r
9461 #define USIC_CH_RBCTR_SRBIEN_Pos 30 /*!< USIC_CH RBCTR: SRBIEN Position */
\r
9462 #define USIC_CH_RBCTR_SRBIEN_Msk (0x01UL << USIC_CH_RBCTR_SRBIEN_Pos) /*!< USIC_CH RBCTR: SRBIEN Mask */
\r
9463 #define USIC_CH_RBCTR_RBERIEN_Pos 31 /*!< USIC_CH RBCTR: RBERIEN Position */
\r
9464 #define USIC_CH_RBCTR_RBERIEN_Msk (0x01UL << USIC_CH_RBCTR_RBERIEN_Pos) /*!< USIC_CH RBCTR: RBERIEN Mask */
\r
9466 /* ------------------------------- USIC_CH_TRBPTR ------------------------------- */
\r
9467 #define USIC_CH_TRBPTR_TDIPTR_Pos 0 /*!< USIC_CH TRBPTR: TDIPTR Position */
\r
9468 #define USIC_CH_TRBPTR_TDIPTR_Msk (0x3fUL << USIC_CH_TRBPTR_TDIPTR_Pos) /*!< USIC_CH TRBPTR: TDIPTR Mask */
\r
9469 #define USIC_CH_TRBPTR_TDOPTR_Pos 8 /*!< USIC_CH TRBPTR: TDOPTR Position */
\r
9470 #define USIC_CH_TRBPTR_TDOPTR_Msk (0x3fUL << USIC_CH_TRBPTR_TDOPTR_Pos) /*!< USIC_CH TRBPTR: TDOPTR Mask */
\r
9471 #define USIC_CH_TRBPTR_RDIPTR_Pos 16 /*!< USIC_CH TRBPTR: RDIPTR Position */
\r
9472 #define USIC_CH_TRBPTR_RDIPTR_Msk (0x3fUL << USIC_CH_TRBPTR_RDIPTR_Pos) /*!< USIC_CH TRBPTR: RDIPTR Mask */
\r
9473 #define USIC_CH_TRBPTR_RDOPTR_Pos 24 /*!< USIC_CH TRBPTR: RDOPTR Position */
\r
9474 #define USIC_CH_TRBPTR_RDOPTR_Msk (0x3fUL << USIC_CH_TRBPTR_RDOPTR_Pos) /*!< USIC_CH TRBPTR: RDOPTR Mask */
\r
9476 /* -------------------------------- USIC_CH_TRBSR ------------------------------- */
\r
9477 #define USIC_CH_TRBSR_SRBI_Pos 0 /*!< USIC_CH TRBSR: SRBI Position */
\r
9478 #define USIC_CH_TRBSR_SRBI_Msk (0x01UL << USIC_CH_TRBSR_SRBI_Pos) /*!< USIC_CH TRBSR: SRBI Mask */
\r
9479 #define USIC_CH_TRBSR_RBERI_Pos 1 /*!< USIC_CH TRBSR: RBERI Position */
\r
9480 #define USIC_CH_TRBSR_RBERI_Msk (0x01UL << USIC_CH_TRBSR_RBERI_Pos) /*!< USIC_CH TRBSR: RBERI Mask */
\r
9481 #define USIC_CH_TRBSR_ARBI_Pos 2 /*!< USIC_CH TRBSR: ARBI Position */
\r
9482 #define USIC_CH_TRBSR_ARBI_Msk (0x01UL << USIC_CH_TRBSR_ARBI_Pos) /*!< USIC_CH TRBSR: ARBI Mask */
\r
9483 #define USIC_CH_TRBSR_REMPTY_Pos 3 /*!< USIC_CH TRBSR: REMPTY Position */
\r
9484 #define USIC_CH_TRBSR_REMPTY_Msk (0x01UL << USIC_CH_TRBSR_REMPTY_Pos) /*!< USIC_CH TRBSR: REMPTY Mask */
\r
9485 #define USIC_CH_TRBSR_RFULL_Pos 4 /*!< USIC_CH TRBSR: RFULL Position */
\r
9486 #define USIC_CH_TRBSR_RFULL_Msk (0x01UL << USIC_CH_TRBSR_RFULL_Pos) /*!< USIC_CH TRBSR: RFULL Mask */
\r
9487 #define USIC_CH_TRBSR_RBUS_Pos 5 /*!< USIC_CH TRBSR: RBUS Position */
\r
9488 #define USIC_CH_TRBSR_RBUS_Msk (0x01UL << USIC_CH_TRBSR_RBUS_Pos) /*!< USIC_CH TRBSR: RBUS Mask */
\r
9489 #define USIC_CH_TRBSR_SRBT_Pos 6 /*!< USIC_CH TRBSR: SRBT Position */
\r
9490 #define USIC_CH_TRBSR_SRBT_Msk (0x01UL << USIC_CH_TRBSR_SRBT_Pos) /*!< USIC_CH TRBSR: SRBT Mask */
\r
9491 #define USIC_CH_TRBSR_STBI_Pos 8 /*!< USIC_CH TRBSR: STBI Position */
\r
9492 #define USIC_CH_TRBSR_STBI_Msk (0x01UL << USIC_CH_TRBSR_STBI_Pos) /*!< USIC_CH TRBSR: STBI Mask */
\r
9493 #define USIC_CH_TRBSR_TBERI_Pos 9 /*!< USIC_CH TRBSR: TBERI Position */
\r
9494 #define USIC_CH_TRBSR_TBERI_Msk (0x01UL << USIC_CH_TRBSR_TBERI_Pos) /*!< USIC_CH TRBSR: TBERI Mask */
\r
9495 #define USIC_CH_TRBSR_TEMPTY_Pos 11 /*!< USIC_CH TRBSR: TEMPTY Position */
\r
9496 #define USIC_CH_TRBSR_TEMPTY_Msk (0x01UL << USIC_CH_TRBSR_TEMPTY_Pos) /*!< USIC_CH TRBSR: TEMPTY Mask */
\r
9497 #define USIC_CH_TRBSR_TFULL_Pos 12 /*!< USIC_CH TRBSR: TFULL Position */
\r
9498 #define USIC_CH_TRBSR_TFULL_Msk (0x01UL << USIC_CH_TRBSR_TFULL_Pos) /*!< USIC_CH TRBSR: TFULL Mask */
\r
9499 #define USIC_CH_TRBSR_TBUS_Pos 13 /*!< USIC_CH TRBSR: TBUS Position */
\r
9500 #define USIC_CH_TRBSR_TBUS_Msk (0x01UL << USIC_CH_TRBSR_TBUS_Pos) /*!< USIC_CH TRBSR: TBUS Mask */
\r
9501 #define USIC_CH_TRBSR_STBT_Pos 14 /*!< USIC_CH TRBSR: STBT Position */
\r
9502 #define USIC_CH_TRBSR_STBT_Msk (0x01UL << USIC_CH_TRBSR_STBT_Pos) /*!< USIC_CH TRBSR: STBT Mask */
\r
9503 #define USIC_CH_TRBSR_RBFLVL_Pos 16 /*!< USIC_CH TRBSR: RBFLVL Position */
\r
9504 #define USIC_CH_TRBSR_RBFLVL_Msk (0x7fUL << USIC_CH_TRBSR_RBFLVL_Pos) /*!< USIC_CH TRBSR: RBFLVL Mask */
\r
9505 #define USIC_CH_TRBSR_TBFLVL_Pos 24 /*!< USIC_CH TRBSR: TBFLVL Position */
\r
9506 #define USIC_CH_TRBSR_TBFLVL_Msk (0x7fUL << USIC_CH_TRBSR_TBFLVL_Pos) /*!< USIC_CH TRBSR: TBFLVL Mask */
\r
9508 /* ------------------------------- USIC_CH_TRBSCR ------------------------------- */
\r
9509 #define USIC_CH_TRBSCR_CSRBI_Pos 0 /*!< USIC_CH TRBSCR: CSRBI Position */
\r
9510 #define USIC_CH_TRBSCR_CSRBI_Msk (0x01UL << USIC_CH_TRBSCR_CSRBI_Pos) /*!< USIC_CH TRBSCR: CSRBI Mask */
\r
9511 #define USIC_CH_TRBSCR_CRBERI_Pos 1 /*!< USIC_CH TRBSCR: CRBERI Position */
\r
9512 #define USIC_CH_TRBSCR_CRBERI_Msk (0x01UL << USIC_CH_TRBSCR_CRBERI_Pos) /*!< USIC_CH TRBSCR: CRBERI Mask */
\r
9513 #define USIC_CH_TRBSCR_CARBI_Pos 2 /*!< USIC_CH TRBSCR: CARBI Position */
\r
9514 #define USIC_CH_TRBSCR_CARBI_Msk (0x01UL << USIC_CH_TRBSCR_CARBI_Pos) /*!< USIC_CH TRBSCR: CARBI Mask */
\r
9515 #define USIC_CH_TRBSCR_CSTBI_Pos 8 /*!< USIC_CH TRBSCR: CSTBI Position */
\r
9516 #define USIC_CH_TRBSCR_CSTBI_Msk (0x01UL << USIC_CH_TRBSCR_CSTBI_Pos) /*!< USIC_CH TRBSCR: CSTBI Mask */
\r
9517 #define USIC_CH_TRBSCR_CTBERI_Pos 9 /*!< USIC_CH TRBSCR: CTBERI Position */
\r
9518 #define USIC_CH_TRBSCR_CTBERI_Msk (0x01UL << USIC_CH_TRBSCR_CTBERI_Pos) /*!< USIC_CH TRBSCR: CTBERI Mask */
\r
9519 #define USIC_CH_TRBSCR_CBDV_Pos 10 /*!< USIC_CH TRBSCR: CBDV Position */
\r
9520 #define USIC_CH_TRBSCR_CBDV_Msk (0x01UL << USIC_CH_TRBSCR_CBDV_Pos) /*!< USIC_CH TRBSCR: CBDV Mask */
\r
9521 #define USIC_CH_TRBSCR_FLUSHRB_Pos 14 /*!< USIC_CH TRBSCR: FLUSHRB Position */
\r
9522 #define USIC_CH_TRBSCR_FLUSHRB_Msk (0x01UL << USIC_CH_TRBSCR_FLUSHRB_Pos) /*!< USIC_CH TRBSCR: FLUSHRB Mask */
\r
9523 #define USIC_CH_TRBSCR_FLUSHTB_Pos 15 /*!< USIC_CH TRBSCR: FLUSHTB Position */
\r
9524 #define USIC_CH_TRBSCR_FLUSHTB_Msk (0x01UL << USIC_CH_TRBSCR_FLUSHTB_Pos) /*!< USIC_CH TRBSCR: FLUSHTB Mask */
\r
9526 /* -------------------------------- USIC_CH_OUTR -------------------------------- */
\r
9527 #define USIC_CH_OUTR_DSR_Pos 0 /*!< USIC_CH OUTR: DSR Position */
\r
9528 #define USIC_CH_OUTR_DSR_Msk (0x0000ffffUL << USIC_CH_OUTR_DSR_Pos) /*!< USIC_CH OUTR: DSR Mask */
\r
9529 #define USIC_CH_OUTR_RCI_Pos 16 /*!< USIC_CH OUTR: RCI Position */
\r
9530 #define USIC_CH_OUTR_RCI_Msk (0x1fUL << USIC_CH_OUTR_RCI_Pos) /*!< USIC_CH OUTR: RCI Mask */
\r
9532 /* -------------------------------- USIC_CH_OUTDR ------------------------------- */
\r
9533 #define USIC_CH_OUTDR_DSR_Pos 0 /*!< USIC_CH OUTDR: DSR Position */
\r
9534 #define USIC_CH_OUTDR_DSR_Msk (0x0000ffffUL << USIC_CH_OUTDR_DSR_Pos) /*!< USIC_CH OUTDR: DSR Mask */
\r
9535 #define USIC_CH_OUTDR_RCI_Pos 16 /*!< USIC_CH OUTDR: RCI Position */
\r
9536 #define USIC_CH_OUTDR_RCI_Msk (0x1fUL << USIC_CH_OUTDR_RCI_Pos) /*!< USIC_CH OUTDR: RCI Mask */
\r
9538 /* --------------------------------- USIC_CH_IN --------------------------------- */
\r
9539 #define USIC_CH_IN_TDATA_Pos 0 /*!< USIC_CH IN: TDATA Position */
\r
9540 #define USIC_CH_IN_TDATA_Msk (0x0000ffffUL << USIC_CH_IN_TDATA_Pos) /*!< USIC_CH IN: TDATA Mask */
\r
9543 /* ================================================================================ */
\r
9544 /* ================ struct 'CAN' Position & Mask ================ */
\r
9545 /* ================================================================================ */
\r
9548 /* ----------------------------------- CAN_CLC ---------------------------------- */
\r
9549 #define CAN_CLC_DISR_Pos 0 /*!< CAN CLC: DISR Position */
\r
9550 #define CAN_CLC_DISR_Msk (0x01UL << CAN_CLC_DISR_Pos) /*!< CAN CLC: DISR Mask */
\r
9551 #define CAN_CLC_DISS_Pos 1 /*!< CAN CLC: DISS Position */
\r
9552 #define CAN_CLC_DISS_Msk (0x01UL << CAN_CLC_DISS_Pos) /*!< CAN CLC: DISS Mask */
\r
9553 #define CAN_CLC_EDIS_Pos 3 /*!< CAN CLC: EDIS Position */
\r
9554 #define CAN_CLC_EDIS_Msk (0x01UL << CAN_CLC_EDIS_Pos) /*!< CAN CLC: EDIS Mask */
\r
9555 #define CAN_CLC_SBWE_Pos 4 /*!< CAN CLC: SBWE Position */
\r
9556 #define CAN_CLC_SBWE_Msk (0x01UL << CAN_CLC_SBWE_Pos) /*!< CAN CLC: SBWE Mask */
\r
9558 /* ----------------------------------- CAN_ID ----------------------------------- */
\r
9559 #define CAN_ID_MOD_REV_Pos 0 /*!< CAN ID: MOD_REV Position */
\r
9560 #define CAN_ID_MOD_REV_Msk (0x000000ffUL << CAN_ID_MOD_REV_Pos) /*!< CAN ID: MOD_REV Mask */
\r
9561 #define CAN_ID_MOD_TYPE_Pos 8 /*!< CAN ID: MOD_TYPE Position */
\r
9562 #define CAN_ID_MOD_TYPE_Msk (0x000000ffUL << CAN_ID_MOD_TYPE_Pos) /*!< CAN ID: MOD_TYPE Mask */
\r
9563 #define CAN_ID_MOD_NUMBER_Pos 16 /*!< CAN ID: MOD_NUMBER Position */
\r
9564 #define CAN_ID_MOD_NUMBER_Msk (0x0000ffffUL << CAN_ID_MOD_NUMBER_Pos) /*!< CAN ID: MOD_NUMBER Mask */
\r
9566 /* ----------------------------------- CAN_FDR ---------------------------------- */
\r
9567 #define CAN_FDR_STEP_Pos 0 /*!< CAN FDR: STEP Position */
\r
9568 #define CAN_FDR_STEP_Msk (0x000003ffUL << CAN_FDR_STEP_Pos) /*!< CAN FDR: STEP Mask */
\r
9569 #define CAN_FDR_SM_Pos 11 /*!< CAN FDR: SM Position */
\r
9570 #define CAN_FDR_SM_Msk (0x01UL << CAN_FDR_SM_Pos) /*!< CAN FDR: SM Mask */
\r
9571 #define CAN_FDR_SC_Pos 12 /*!< CAN FDR: SC Position */
\r
9572 #define CAN_FDR_SC_Msk (0x03UL << CAN_FDR_SC_Pos) /*!< CAN FDR: SC Mask */
\r
9573 #define CAN_FDR_DM_Pos 14 /*!< CAN FDR: DM Position */
\r
9574 #define CAN_FDR_DM_Msk (0x03UL << CAN_FDR_DM_Pos) /*!< CAN FDR: DM Mask */
\r
9575 #define CAN_FDR_RESULT_Pos 16 /*!< CAN FDR: RESULT Position */
\r
9576 #define CAN_FDR_RESULT_Msk (0x000003ffUL << CAN_FDR_RESULT_Pos) /*!< CAN FDR: RESULT Mask */
\r
9577 #define CAN_FDR_SUSACK_Pos 28 /*!< CAN FDR: SUSACK Position */
\r
9578 #define CAN_FDR_SUSACK_Msk (0x01UL << CAN_FDR_SUSACK_Pos) /*!< CAN FDR: SUSACK Mask */
\r
9579 #define CAN_FDR_SUSREQ_Pos 29 /*!< CAN FDR: SUSREQ Position */
\r
9580 #define CAN_FDR_SUSREQ_Msk (0x01UL << CAN_FDR_SUSREQ_Pos) /*!< CAN FDR: SUSREQ Mask */
\r
9581 #define CAN_FDR_ENHW_Pos 30 /*!< CAN FDR: ENHW Position */
\r
9582 #define CAN_FDR_ENHW_Msk (0x01UL << CAN_FDR_ENHW_Pos) /*!< CAN FDR: ENHW Mask */
\r
9583 #define CAN_FDR_DISCLK_Pos 31 /*!< CAN FDR: DISCLK Position */
\r
9584 #define CAN_FDR_DISCLK_Msk (0x01UL << CAN_FDR_DISCLK_Pos) /*!< CAN FDR: DISCLK Mask */
\r
9586 /* ---------------------------------- CAN_LIST ---------------------------------- */
\r
9587 #define CAN_LIST_BEGIN_Pos 0 /*!< CAN LIST: BEGIN Position */
\r
9588 #define CAN_LIST_BEGIN_Msk (0x000000ffUL << CAN_LIST_BEGIN_Pos) /*!< CAN LIST: BEGIN Mask */
\r
9589 #define CAN_LIST_END_Pos 8 /*!< CAN LIST: END Position */
\r
9590 #define CAN_LIST_END_Msk (0x000000ffUL << CAN_LIST_END_Pos) /*!< CAN LIST: END Mask */
\r
9591 #define CAN_LIST_SIZE_Pos 16 /*!< CAN LIST: SIZE Position */
\r
9592 #define CAN_LIST_SIZE_Msk (0x000000ffUL << CAN_LIST_SIZE_Pos) /*!< CAN LIST: SIZE Mask */
\r
9593 #define CAN_LIST_EMPTY_Pos 24 /*!< CAN LIST: EMPTY Position */
\r
9594 #define CAN_LIST_EMPTY_Msk (0x01UL << CAN_LIST_EMPTY_Pos) /*!< CAN LIST: EMPTY Mask */
\r
9596 /* ---------------------------------- CAN_MSPND --------------------------------- */
\r
9597 #define CAN_MSPND_PND_Pos 0 /*!< CAN MSPND: PND Position */
\r
9598 #define CAN_MSPND_PND_Msk (0xffffffffUL << CAN_MSPND_PND_Pos) /*!< CAN MSPND: PND Mask */
\r
9600 /* ---------------------------------- CAN_MSID ---------------------------------- */
\r
9601 #define CAN_MSID_INDEX_Pos 0 /*!< CAN MSID: INDEX Position */
\r
9602 #define CAN_MSID_INDEX_Msk (0x3fUL << CAN_MSID_INDEX_Pos) /*!< CAN MSID: INDEX Mask */
\r
9604 /* --------------------------------- CAN_MSIMASK -------------------------------- */
\r
9605 #define CAN_MSIMASK_IM_Pos 0 /*!< CAN MSIMASK: IM Position */
\r
9606 #define CAN_MSIMASK_IM_Msk (0xffffffffUL << CAN_MSIMASK_IM_Pos) /*!< CAN MSIMASK: IM Mask */
\r
9608 /* --------------------------------- CAN_PANCTR --------------------------------- */
\r
9609 #define CAN_PANCTR_PANCMD_Pos 0 /*!< CAN PANCTR: PANCMD Position */
\r
9610 #define CAN_PANCTR_PANCMD_Msk (0x000000ffUL << CAN_PANCTR_PANCMD_Pos) /*!< CAN PANCTR: PANCMD Mask */
\r
9611 #define CAN_PANCTR_BUSY_Pos 8 /*!< CAN PANCTR: BUSY Position */
\r
9612 #define CAN_PANCTR_BUSY_Msk (0x01UL << CAN_PANCTR_BUSY_Pos) /*!< CAN PANCTR: BUSY Mask */
\r
9613 #define CAN_PANCTR_RBUSY_Pos 9 /*!< CAN PANCTR: RBUSY Position */
\r
9614 #define CAN_PANCTR_RBUSY_Msk (0x01UL << CAN_PANCTR_RBUSY_Pos) /*!< CAN PANCTR: RBUSY Mask */
\r
9615 #define CAN_PANCTR_PANAR1_Pos 16 /*!< CAN PANCTR: PANAR1 Position */
\r
9616 #define CAN_PANCTR_PANAR1_Msk (0x000000ffUL << CAN_PANCTR_PANAR1_Pos) /*!< CAN PANCTR: PANAR1 Mask */
\r
9617 #define CAN_PANCTR_PANAR2_Pos 24 /*!< CAN PANCTR: PANAR2 Position */
\r
9618 #define CAN_PANCTR_PANAR2_Msk (0x000000ffUL << CAN_PANCTR_PANAR2_Pos) /*!< CAN PANCTR: PANAR2 Mask */
\r
9620 /* ----------------------------------- CAN_MCR ---------------------------------- */
\r
9621 #define CAN_MCR_MPSEL_Pos 12 /*!< CAN MCR: MPSEL Position */
\r
9622 #define CAN_MCR_MPSEL_Msk (0x0fUL << CAN_MCR_MPSEL_Pos) /*!< CAN MCR: MPSEL Mask */
\r
9624 /* ---------------------------------- CAN_MITR ---------------------------------- */
\r
9625 #define CAN_MITR_IT_Pos 0 /*!< CAN MITR: IT Position */
\r
9626 #define CAN_MITR_IT_Msk (0x000000ffUL << CAN_MITR_IT_Pos) /*!< CAN MITR: IT Mask */
\r
9629 /* ================================================================================ */
\r
9630 /* ================ Group 'CAN_NODE' Position & Mask ================ */
\r
9631 /* ================================================================================ */
\r
9634 /* -------------------------------- CAN_NODE_NCR -------------------------------- */
\r
9635 #define CAN_NODE_NCR_INIT_Pos 0 /*!< CAN_NODE NCR: INIT Position */
\r
9636 #define CAN_NODE_NCR_INIT_Msk (0x01UL << CAN_NODE_NCR_INIT_Pos) /*!< CAN_NODE NCR: INIT Mask */
\r
9637 #define CAN_NODE_NCR_TRIE_Pos 1 /*!< CAN_NODE NCR: TRIE Position */
\r
9638 #define CAN_NODE_NCR_TRIE_Msk (0x01UL << CAN_NODE_NCR_TRIE_Pos) /*!< CAN_NODE NCR: TRIE Mask */
\r
9639 #define CAN_NODE_NCR_LECIE_Pos 2 /*!< CAN_NODE NCR: LECIE Position */
\r
9640 #define CAN_NODE_NCR_LECIE_Msk (0x01UL << CAN_NODE_NCR_LECIE_Pos) /*!< CAN_NODE NCR: LECIE Mask */
\r
9641 #define CAN_NODE_NCR_ALIE_Pos 3 /*!< CAN_NODE NCR: ALIE Position */
\r
9642 #define CAN_NODE_NCR_ALIE_Msk (0x01UL << CAN_NODE_NCR_ALIE_Pos) /*!< CAN_NODE NCR: ALIE Mask */
\r
9643 #define CAN_NODE_NCR_CANDIS_Pos 4 /*!< CAN_NODE NCR: CANDIS Position */
\r
9644 #define CAN_NODE_NCR_CANDIS_Msk (0x01UL << CAN_NODE_NCR_CANDIS_Pos) /*!< CAN_NODE NCR: CANDIS Mask */
\r
9645 #define CAN_NODE_NCR_CCE_Pos 6 /*!< CAN_NODE NCR: CCE Position */
\r
9646 #define CAN_NODE_NCR_CCE_Msk (0x01UL << CAN_NODE_NCR_CCE_Pos) /*!< CAN_NODE NCR: CCE Mask */
\r
9647 #define CAN_NODE_NCR_CALM_Pos 7 /*!< CAN_NODE NCR: CALM Position */
\r
9648 #define CAN_NODE_NCR_CALM_Msk (0x01UL << CAN_NODE_NCR_CALM_Pos) /*!< CAN_NODE NCR: CALM Mask */
\r
9649 #define CAN_NODE_NCR_SUSEN_Pos 8 /*!< CAN_NODE NCR: SUSEN Position */
\r
9650 #define CAN_NODE_NCR_SUSEN_Msk (0x01UL << CAN_NODE_NCR_SUSEN_Pos) /*!< CAN_NODE NCR: SUSEN Mask */
\r
9652 /* -------------------------------- CAN_NODE_NSR -------------------------------- */
\r
9653 #define CAN_NODE_NSR_LEC_Pos 0 /*!< CAN_NODE NSR: LEC Position */
\r
9654 #define CAN_NODE_NSR_LEC_Msk (0x07UL << CAN_NODE_NSR_LEC_Pos) /*!< CAN_NODE NSR: LEC Mask */
\r
9655 #define CAN_NODE_NSR_TXOK_Pos 3 /*!< CAN_NODE NSR: TXOK Position */
\r
9656 #define CAN_NODE_NSR_TXOK_Msk (0x01UL << CAN_NODE_NSR_TXOK_Pos) /*!< CAN_NODE NSR: TXOK Mask */
\r
9657 #define CAN_NODE_NSR_RXOK_Pos 4 /*!< CAN_NODE NSR: RXOK Position */
\r
9658 #define CAN_NODE_NSR_RXOK_Msk (0x01UL << CAN_NODE_NSR_RXOK_Pos) /*!< CAN_NODE NSR: RXOK Mask */
\r
9659 #define CAN_NODE_NSR_ALERT_Pos 5 /*!< CAN_NODE NSR: ALERT Position */
\r
9660 #define CAN_NODE_NSR_ALERT_Msk (0x01UL << CAN_NODE_NSR_ALERT_Pos) /*!< CAN_NODE NSR: ALERT Mask */
\r
9661 #define CAN_NODE_NSR_EWRN_Pos 6 /*!< CAN_NODE NSR: EWRN Position */
\r
9662 #define CAN_NODE_NSR_EWRN_Msk (0x01UL << CAN_NODE_NSR_EWRN_Pos) /*!< CAN_NODE NSR: EWRN Mask */
\r
9663 #define CAN_NODE_NSR_BOFF_Pos 7 /*!< CAN_NODE NSR: BOFF Position */
\r
9664 #define CAN_NODE_NSR_BOFF_Msk (0x01UL << CAN_NODE_NSR_BOFF_Pos) /*!< CAN_NODE NSR: BOFF Mask */
\r
9665 #define CAN_NODE_NSR_LLE_Pos 8 /*!< CAN_NODE NSR: LLE Position */
\r
9666 #define CAN_NODE_NSR_LLE_Msk (0x01UL << CAN_NODE_NSR_LLE_Pos) /*!< CAN_NODE NSR: LLE Mask */
\r
9667 #define CAN_NODE_NSR_LOE_Pos 9 /*!< CAN_NODE NSR: LOE Position */
\r
9668 #define CAN_NODE_NSR_LOE_Msk (0x01UL << CAN_NODE_NSR_LOE_Pos) /*!< CAN_NODE NSR: LOE Mask */
\r
9669 #define CAN_NODE_NSR_SUSACK_Pos 10 /*!< CAN_NODE NSR: SUSACK Position */
\r
9670 #define CAN_NODE_NSR_SUSACK_Msk (0x01UL << CAN_NODE_NSR_SUSACK_Pos) /*!< CAN_NODE NSR: SUSACK Mask */
\r
9672 /* -------------------------------- CAN_NODE_NIPR ------------------------------- */
\r
9673 #define CAN_NODE_NIPR_ALINP_Pos 0 /*!< CAN_NODE NIPR: ALINP Position */
\r
9674 #define CAN_NODE_NIPR_ALINP_Msk (0x07UL << CAN_NODE_NIPR_ALINP_Pos) /*!< CAN_NODE NIPR: ALINP Mask */
\r
9675 #define CAN_NODE_NIPR_LECINP_Pos 4 /*!< CAN_NODE NIPR: LECINP Position */
\r
9676 #define CAN_NODE_NIPR_LECINP_Msk (0x07UL << CAN_NODE_NIPR_LECINP_Pos) /*!< CAN_NODE NIPR: LECINP Mask */
\r
9677 #define CAN_NODE_NIPR_TRINP_Pos 8 /*!< CAN_NODE NIPR: TRINP Position */
\r
9678 #define CAN_NODE_NIPR_TRINP_Msk (0x07UL << CAN_NODE_NIPR_TRINP_Pos) /*!< CAN_NODE NIPR: TRINP Mask */
\r
9679 #define CAN_NODE_NIPR_CFCINP_Pos 12 /*!< CAN_NODE NIPR: CFCINP Position */
\r
9680 #define CAN_NODE_NIPR_CFCINP_Msk (0x07UL << CAN_NODE_NIPR_CFCINP_Pos) /*!< CAN_NODE NIPR: CFCINP Mask */
\r
9682 /* -------------------------------- CAN_NODE_NPCR ------------------------------- */
\r
9683 #define CAN_NODE_NPCR_RXSEL_Pos 0 /*!< CAN_NODE NPCR: RXSEL Position */
\r
9684 #define CAN_NODE_NPCR_RXSEL_Msk (0x07UL << CAN_NODE_NPCR_RXSEL_Pos) /*!< CAN_NODE NPCR: RXSEL Mask */
\r
9685 #define CAN_NODE_NPCR_LBM_Pos 8 /*!< CAN_NODE NPCR: LBM Position */
\r
9686 #define CAN_NODE_NPCR_LBM_Msk (0x01UL << CAN_NODE_NPCR_LBM_Pos) /*!< CAN_NODE NPCR: LBM Mask */
\r
9688 /* -------------------------------- CAN_NODE_NBTR ------------------------------- */
\r
9689 #define CAN_NODE_NBTR_BRP_Pos 0 /*!< CAN_NODE NBTR: BRP Position */
\r
9690 #define CAN_NODE_NBTR_BRP_Msk (0x3fUL << CAN_NODE_NBTR_BRP_Pos) /*!< CAN_NODE NBTR: BRP Mask */
\r
9691 #define CAN_NODE_NBTR_SJW_Pos 6 /*!< CAN_NODE NBTR: SJW Position */
\r
9692 #define CAN_NODE_NBTR_SJW_Msk (0x03UL << CAN_NODE_NBTR_SJW_Pos) /*!< CAN_NODE NBTR: SJW Mask */
\r
9693 #define CAN_NODE_NBTR_TSEG1_Pos 8 /*!< CAN_NODE NBTR: TSEG1 Position */
\r
9694 #define CAN_NODE_NBTR_TSEG1_Msk (0x0fUL << CAN_NODE_NBTR_TSEG1_Pos) /*!< CAN_NODE NBTR: TSEG1 Mask */
\r
9695 #define CAN_NODE_NBTR_TSEG2_Pos 12 /*!< CAN_NODE NBTR: TSEG2 Position */
\r
9696 #define CAN_NODE_NBTR_TSEG2_Msk (0x07UL << CAN_NODE_NBTR_TSEG2_Pos) /*!< CAN_NODE NBTR: TSEG2 Mask */
\r
9697 #define CAN_NODE_NBTR_DIV8_Pos 15 /*!< CAN_NODE NBTR: DIV8 Position */
\r
9698 #define CAN_NODE_NBTR_DIV8_Msk (0x01UL << CAN_NODE_NBTR_DIV8_Pos) /*!< CAN_NODE NBTR: DIV8 Mask */
\r
9700 /* ------------------------------- CAN_NODE_NECNT ------------------------------- */
\r
9701 #define CAN_NODE_NECNT_REC_Pos 0 /*!< CAN_NODE NECNT: REC Position */
\r
9702 #define CAN_NODE_NECNT_REC_Msk (0x000000ffUL << CAN_NODE_NECNT_REC_Pos) /*!< CAN_NODE NECNT: REC Mask */
\r
9703 #define CAN_NODE_NECNT_TEC_Pos 8 /*!< CAN_NODE NECNT: TEC Position */
\r
9704 #define CAN_NODE_NECNT_TEC_Msk (0x000000ffUL << CAN_NODE_NECNT_TEC_Pos) /*!< CAN_NODE NECNT: TEC Mask */
\r
9705 #define CAN_NODE_NECNT_EWRNLVL_Pos 16 /*!< CAN_NODE NECNT: EWRNLVL Position */
\r
9706 #define CAN_NODE_NECNT_EWRNLVL_Msk (0x000000ffUL << CAN_NODE_NECNT_EWRNLVL_Pos) /*!< CAN_NODE NECNT: EWRNLVL Mask */
\r
9707 #define CAN_NODE_NECNT_LETD_Pos 24 /*!< CAN_NODE NECNT: LETD Position */
\r
9708 #define CAN_NODE_NECNT_LETD_Msk (0x01UL << CAN_NODE_NECNT_LETD_Pos) /*!< CAN_NODE NECNT: LETD Mask */
\r
9709 #define CAN_NODE_NECNT_LEINC_Pos 25 /*!< CAN_NODE NECNT: LEINC Position */
\r
9710 #define CAN_NODE_NECNT_LEINC_Msk (0x01UL << CAN_NODE_NECNT_LEINC_Pos) /*!< CAN_NODE NECNT: LEINC Mask */
\r
9712 /* -------------------------------- CAN_NODE_NFCR ------------------------------- */
\r
9713 #define CAN_NODE_NFCR_CFC_Pos 0 /*!< CAN_NODE NFCR: CFC Position */
\r
9714 #define CAN_NODE_NFCR_CFC_Msk (0x0000ffffUL << CAN_NODE_NFCR_CFC_Pos) /*!< CAN_NODE NFCR: CFC Mask */
\r
9715 #define CAN_NODE_NFCR_CFSEL_Pos 16 /*!< CAN_NODE NFCR: CFSEL Position */
\r
9716 #define CAN_NODE_NFCR_CFSEL_Msk (0x07UL << CAN_NODE_NFCR_CFSEL_Pos) /*!< CAN_NODE NFCR: CFSEL Mask */
\r
9717 #define CAN_NODE_NFCR_CFMOD_Pos 19 /*!< CAN_NODE NFCR: CFMOD Position */
\r
9718 #define CAN_NODE_NFCR_CFMOD_Msk (0x03UL << CAN_NODE_NFCR_CFMOD_Pos) /*!< CAN_NODE NFCR: CFMOD Mask */
\r
9719 #define CAN_NODE_NFCR_CFCIE_Pos 22 /*!< CAN_NODE NFCR: CFCIE Position */
\r
9720 #define CAN_NODE_NFCR_CFCIE_Msk (0x01UL << CAN_NODE_NFCR_CFCIE_Pos) /*!< CAN_NODE NFCR: CFCIE Mask */
\r
9721 #define CAN_NODE_NFCR_CFCOV_Pos 23 /*!< CAN_NODE NFCR: CFCOV Position */
\r
9722 #define CAN_NODE_NFCR_CFCOV_Msk (0x01UL << CAN_NODE_NFCR_CFCOV_Pos) /*!< CAN_NODE NFCR: CFCOV Mask */
\r
9725 /* ================================================================================ */
\r
9726 /* ================ Group 'CAN_MO' Position & Mask ================ */
\r
9727 /* ================================================================================ */
\r
9730 /* -------------------------------- CAN_MO_MOFCR -------------------------------- */
\r
9731 #define CAN_MO_MOFCR_MMC_Pos 0 /*!< CAN_MO MOFCR: MMC Position */
\r
9732 #define CAN_MO_MOFCR_MMC_Msk (0x0fUL << CAN_MO_MOFCR_MMC_Pos) /*!< CAN_MO MOFCR: MMC Mask */
\r
9733 #define CAN_MO_MOFCR_GDFS_Pos 8 /*!< CAN_MO MOFCR: GDFS Position */
\r
9734 #define CAN_MO_MOFCR_GDFS_Msk (0x01UL << CAN_MO_MOFCR_GDFS_Pos) /*!< CAN_MO MOFCR: GDFS Mask */
\r
9735 #define CAN_MO_MOFCR_IDC_Pos 9 /*!< CAN_MO MOFCR: IDC Position */
\r
9736 #define CAN_MO_MOFCR_IDC_Msk (0x01UL << CAN_MO_MOFCR_IDC_Pos) /*!< CAN_MO MOFCR: IDC Mask */
\r
9737 #define CAN_MO_MOFCR_DLCC_Pos 10 /*!< CAN_MO MOFCR: DLCC Position */
\r
9738 #define CAN_MO_MOFCR_DLCC_Msk (0x01UL << CAN_MO_MOFCR_DLCC_Pos) /*!< CAN_MO MOFCR: DLCC Mask */
\r
9739 #define CAN_MO_MOFCR_DATC_Pos 11 /*!< CAN_MO MOFCR: DATC Position */
\r
9740 #define CAN_MO_MOFCR_DATC_Msk (0x01UL << CAN_MO_MOFCR_DATC_Pos) /*!< CAN_MO MOFCR: DATC Mask */
\r
9741 #define CAN_MO_MOFCR_RXIE_Pos 16 /*!< CAN_MO MOFCR: RXIE Position */
\r
9742 #define CAN_MO_MOFCR_RXIE_Msk (0x01UL << CAN_MO_MOFCR_RXIE_Pos) /*!< CAN_MO MOFCR: RXIE Mask */
\r
9743 #define CAN_MO_MOFCR_TXIE_Pos 17 /*!< CAN_MO MOFCR: TXIE Position */
\r
9744 #define CAN_MO_MOFCR_TXIE_Msk (0x01UL << CAN_MO_MOFCR_TXIE_Pos) /*!< CAN_MO MOFCR: TXIE Mask */
\r
9745 #define CAN_MO_MOFCR_OVIE_Pos 18 /*!< CAN_MO MOFCR: OVIE Position */
\r
9746 #define CAN_MO_MOFCR_OVIE_Msk (0x01UL << CAN_MO_MOFCR_OVIE_Pos) /*!< CAN_MO MOFCR: OVIE Mask */
\r
9747 #define CAN_MO_MOFCR_FRREN_Pos 20 /*!< CAN_MO MOFCR: FRREN Position */
\r
9748 #define CAN_MO_MOFCR_FRREN_Msk (0x01UL << CAN_MO_MOFCR_FRREN_Pos) /*!< CAN_MO MOFCR: FRREN Mask */
\r
9749 #define CAN_MO_MOFCR_RMM_Pos 21 /*!< CAN_MO MOFCR: RMM Position */
\r
9750 #define CAN_MO_MOFCR_RMM_Msk (0x01UL << CAN_MO_MOFCR_RMM_Pos) /*!< CAN_MO MOFCR: RMM Mask */
\r
9751 #define CAN_MO_MOFCR_SDT_Pos 22 /*!< CAN_MO MOFCR: SDT Position */
\r
9752 #define CAN_MO_MOFCR_SDT_Msk (0x01UL << CAN_MO_MOFCR_SDT_Pos) /*!< CAN_MO MOFCR: SDT Mask */
\r
9753 #define CAN_MO_MOFCR_STT_Pos 23 /*!< CAN_MO MOFCR: STT Position */
\r
9754 #define CAN_MO_MOFCR_STT_Msk (0x01UL << CAN_MO_MOFCR_STT_Pos) /*!< CAN_MO MOFCR: STT Mask */
\r
9755 #define CAN_MO_MOFCR_DLC_Pos 24 /*!< CAN_MO MOFCR: DLC Position */
\r
9756 #define CAN_MO_MOFCR_DLC_Msk (0x0fUL << CAN_MO_MOFCR_DLC_Pos) /*!< CAN_MO MOFCR: DLC Mask */
\r
9758 /* -------------------------------- CAN_MO_MOFGPR ------------------------------- */
\r
9759 #define CAN_MO_MOFGPR_BOT_Pos 0 /*!< CAN_MO MOFGPR: BOT Position */
\r
9760 #define CAN_MO_MOFGPR_BOT_Msk (0x000000ffUL << CAN_MO_MOFGPR_BOT_Pos) /*!< CAN_MO MOFGPR: BOT Mask */
\r
9761 #define CAN_MO_MOFGPR_TOP_Pos 8 /*!< CAN_MO MOFGPR: TOP Position */
\r
9762 #define CAN_MO_MOFGPR_TOP_Msk (0x000000ffUL << CAN_MO_MOFGPR_TOP_Pos) /*!< CAN_MO MOFGPR: TOP Mask */
\r
9763 #define CAN_MO_MOFGPR_CUR_Pos 16 /*!< CAN_MO MOFGPR: CUR Position */
\r
9764 #define CAN_MO_MOFGPR_CUR_Msk (0x000000ffUL << CAN_MO_MOFGPR_CUR_Pos) /*!< CAN_MO MOFGPR: CUR Mask */
\r
9765 #define CAN_MO_MOFGPR_SEL_Pos 24 /*!< CAN_MO MOFGPR: SEL Position */
\r
9766 #define CAN_MO_MOFGPR_SEL_Msk (0x000000ffUL << CAN_MO_MOFGPR_SEL_Pos) /*!< CAN_MO MOFGPR: SEL Mask */
\r
9768 /* -------------------------------- CAN_MO_MOIPR -------------------------------- */
\r
9769 #define CAN_MO_MOIPR_RXINP_Pos 0 /*!< CAN_MO MOIPR: RXINP Position */
\r
9770 #define CAN_MO_MOIPR_RXINP_Msk (0x07UL << CAN_MO_MOIPR_RXINP_Pos) /*!< CAN_MO MOIPR: RXINP Mask */
\r
9771 #define CAN_MO_MOIPR_TXINP_Pos 4 /*!< CAN_MO MOIPR: TXINP Position */
\r
9772 #define CAN_MO_MOIPR_TXINP_Msk (0x07UL << CAN_MO_MOIPR_TXINP_Pos) /*!< CAN_MO MOIPR: TXINP Mask */
\r
9773 #define CAN_MO_MOIPR_MPN_Pos 8 /*!< CAN_MO MOIPR: MPN Position */
\r
9774 #define CAN_MO_MOIPR_MPN_Msk (0x000000ffUL << CAN_MO_MOIPR_MPN_Pos) /*!< CAN_MO MOIPR: MPN Mask */
\r
9775 #define CAN_MO_MOIPR_CFCVAL_Pos 16 /*!< CAN_MO MOIPR: CFCVAL Position */
\r
9776 #define CAN_MO_MOIPR_CFCVAL_Msk (0x0000ffffUL << CAN_MO_MOIPR_CFCVAL_Pos) /*!< CAN_MO MOIPR: CFCVAL Mask */
\r
9778 /* -------------------------------- CAN_MO_MOAMR -------------------------------- */
\r
9779 #define CAN_MO_MOAMR_AM_Pos 0 /*!< CAN_MO MOAMR: AM Position */
\r
9780 #define CAN_MO_MOAMR_AM_Msk (0x1fffffffUL << CAN_MO_MOAMR_AM_Pos) /*!< CAN_MO MOAMR: AM Mask */
\r
9781 #define CAN_MO_MOAMR_MIDE_Pos 29 /*!< CAN_MO MOAMR: MIDE Position */
\r
9782 #define CAN_MO_MOAMR_MIDE_Msk (0x01UL << CAN_MO_MOAMR_MIDE_Pos) /*!< CAN_MO MOAMR: MIDE Mask */
\r
9784 /* ------------------------------- CAN_MO_MODATAL ------------------------------- */
\r
9785 #define CAN_MO_MODATAL_DB0_Pos 0 /*!< CAN_MO MODATAL: DB0 Position */
\r
9786 #define CAN_MO_MODATAL_DB0_Msk (0x000000ffUL << CAN_MO_MODATAL_DB0_Pos) /*!< CAN_MO MODATAL: DB0 Mask */
\r
9787 #define CAN_MO_MODATAL_DB1_Pos 8 /*!< CAN_MO MODATAL: DB1 Position */
\r
9788 #define CAN_MO_MODATAL_DB1_Msk (0x000000ffUL << CAN_MO_MODATAL_DB1_Pos) /*!< CAN_MO MODATAL: DB1 Mask */
\r
9789 #define CAN_MO_MODATAL_DB2_Pos 16 /*!< CAN_MO MODATAL: DB2 Position */
\r
9790 #define CAN_MO_MODATAL_DB2_Msk (0x000000ffUL << CAN_MO_MODATAL_DB2_Pos) /*!< CAN_MO MODATAL: DB2 Mask */
\r
9791 #define CAN_MO_MODATAL_DB3_Pos 24 /*!< CAN_MO MODATAL: DB3 Position */
\r
9792 #define CAN_MO_MODATAL_DB3_Msk (0x000000ffUL << CAN_MO_MODATAL_DB3_Pos) /*!< CAN_MO MODATAL: DB3 Mask */
\r
9794 /* ------------------------------- CAN_MO_MODATAH ------------------------------- */
\r
9795 #define CAN_MO_MODATAH_DB4_Pos 0 /*!< CAN_MO MODATAH: DB4 Position */
\r
9796 #define CAN_MO_MODATAH_DB4_Msk (0x000000ffUL << CAN_MO_MODATAH_DB4_Pos) /*!< CAN_MO MODATAH: DB4 Mask */
\r
9797 #define CAN_MO_MODATAH_DB5_Pos 8 /*!< CAN_MO MODATAH: DB5 Position */
\r
9798 #define CAN_MO_MODATAH_DB5_Msk (0x000000ffUL << CAN_MO_MODATAH_DB5_Pos) /*!< CAN_MO MODATAH: DB5 Mask */
\r
9799 #define CAN_MO_MODATAH_DB6_Pos 16 /*!< CAN_MO MODATAH: DB6 Position */
\r
9800 #define CAN_MO_MODATAH_DB6_Msk (0x000000ffUL << CAN_MO_MODATAH_DB6_Pos) /*!< CAN_MO MODATAH: DB6 Mask */
\r
9801 #define CAN_MO_MODATAH_DB7_Pos 24 /*!< CAN_MO MODATAH: DB7 Position */
\r
9802 #define CAN_MO_MODATAH_DB7_Msk (0x000000ffUL << CAN_MO_MODATAH_DB7_Pos) /*!< CAN_MO MODATAH: DB7 Mask */
\r
9804 /* --------------------------------- CAN_MO_MOAR -------------------------------- */
\r
9805 #define CAN_MO_MOAR_ID_Pos 0 /*!< CAN_MO MOAR: ID Position */
\r
9806 #define CAN_MO_MOAR_ID_Msk (0x1fffffffUL << CAN_MO_MOAR_ID_Pos) /*!< CAN_MO MOAR: ID Mask */
\r
9807 #define CAN_MO_MOAR_IDE_Pos 29 /*!< CAN_MO MOAR: IDE Position */
\r
9808 #define CAN_MO_MOAR_IDE_Msk (0x01UL << CAN_MO_MOAR_IDE_Pos) /*!< CAN_MO MOAR: IDE Mask */
\r
9809 #define CAN_MO_MOAR_PRI_Pos 30 /*!< CAN_MO MOAR: PRI Position */
\r
9810 #define CAN_MO_MOAR_PRI_Msk (0x03UL << CAN_MO_MOAR_PRI_Pos) /*!< CAN_MO MOAR: PRI Mask */
\r
9812 /* -------------------------------- CAN_MO_MOCTR -------------------------------- */
\r
9813 #define CAN_MO_MOCTR_RESRXPND_Pos 0 /*!< CAN_MO MOCTR: RESRXPND Position */
\r
9814 #define CAN_MO_MOCTR_RESRXPND_Msk (0x01UL << CAN_MO_MOCTR_RESRXPND_Pos) /*!< CAN_MO MOCTR: RESRXPND Mask */
\r
9815 #define CAN_MO_MOCTR_RESTXPND_Pos 1 /*!< CAN_MO MOCTR: RESTXPND Position */
\r
9816 #define CAN_MO_MOCTR_RESTXPND_Msk (0x01UL << CAN_MO_MOCTR_RESTXPND_Pos) /*!< CAN_MO MOCTR: RESTXPND Mask */
\r
9817 #define CAN_MO_MOCTR_RESRXUPD_Pos 2 /*!< CAN_MO MOCTR: RESRXUPD Position */
\r
9818 #define CAN_MO_MOCTR_RESRXUPD_Msk (0x01UL << CAN_MO_MOCTR_RESRXUPD_Pos) /*!< CAN_MO MOCTR: RESRXUPD Mask */
\r
9819 #define CAN_MO_MOCTR_RESNEWDAT_Pos 3 /*!< CAN_MO MOCTR: RESNEWDAT Position */
\r
9820 #define CAN_MO_MOCTR_RESNEWDAT_Msk (0x01UL << CAN_MO_MOCTR_RESNEWDAT_Pos) /*!< CAN_MO MOCTR: RESNEWDAT Mask */
\r
9821 #define CAN_MO_MOCTR_RESMSGLST_Pos 4 /*!< CAN_MO MOCTR: RESMSGLST Position */
\r
9822 #define CAN_MO_MOCTR_RESMSGLST_Msk (0x01UL << CAN_MO_MOCTR_RESMSGLST_Pos) /*!< CAN_MO MOCTR: RESMSGLST Mask */
\r
9823 #define CAN_MO_MOCTR_RESMSGVAL_Pos 5 /*!< CAN_MO MOCTR: RESMSGVAL Position */
\r
9824 #define CAN_MO_MOCTR_RESMSGVAL_Msk (0x01UL << CAN_MO_MOCTR_RESMSGVAL_Pos) /*!< CAN_MO MOCTR: RESMSGVAL Mask */
\r
9825 #define CAN_MO_MOCTR_RESRTSEL_Pos 6 /*!< CAN_MO MOCTR: RESRTSEL Position */
\r
9826 #define CAN_MO_MOCTR_RESRTSEL_Msk (0x01UL << CAN_MO_MOCTR_RESRTSEL_Pos) /*!< CAN_MO MOCTR: RESRTSEL Mask */
\r
9827 #define CAN_MO_MOCTR_RESRXEN_Pos 7 /*!< CAN_MO MOCTR: RESRXEN Position */
\r
9828 #define CAN_MO_MOCTR_RESRXEN_Msk (0x01UL << CAN_MO_MOCTR_RESRXEN_Pos) /*!< CAN_MO MOCTR: RESRXEN Mask */
\r
9829 #define CAN_MO_MOCTR_RESTXRQ_Pos 8 /*!< CAN_MO MOCTR: RESTXRQ Position */
\r
9830 #define CAN_MO_MOCTR_RESTXRQ_Msk (0x01UL << CAN_MO_MOCTR_RESTXRQ_Pos) /*!< CAN_MO MOCTR: RESTXRQ Mask */
\r
9831 #define CAN_MO_MOCTR_RESTXEN0_Pos 9 /*!< CAN_MO MOCTR: RESTXEN0 Position */
\r
9832 #define CAN_MO_MOCTR_RESTXEN0_Msk (0x01UL << CAN_MO_MOCTR_RESTXEN0_Pos) /*!< CAN_MO MOCTR: RESTXEN0 Mask */
\r
9833 #define CAN_MO_MOCTR_RESTXEN1_Pos 10 /*!< CAN_MO MOCTR: RESTXEN1 Position */
\r
9834 #define CAN_MO_MOCTR_RESTXEN1_Msk (0x01UL << CAN_MO_MOCTR_RESTXEN1_Pos) /*!< CAN_MO MOCTR: RESTXEN1 Mask */
\r
9835 #define CAN_MO_MOCTR_RESDIR_Pos 11 /*!< CAN_MO MOCTR: RESDIR Position */
\r
9836 #define CAN_MO_MOCTR_RESDIR_Msk (0x01UL << CAN_MO_MOCTR_RESDIR_Pos) /*!< CAN_MO MOCTR: RESDIR Mask */
\r
9837 #define CAN_MO_MOCTR_SETRXPND_Pos 16 /*!< CAN_MO MOCTR: SETRXPND Position */
\r
9838 #define CAN_MO_MOCTR_SETRXPND_Msk (0x01UL << CAN_MO_MOCTR_SETRXPND_Pos) /*!< CAN_MO MOCTR: SETRXPND Mask */
\r
9839 #define CAN_MO_MOCTR_SETTXPND_Pos 17 /*!< CAN_MO MOCTR: SETTXPND Position */
\r
9840 #define CAN_MO_MOCTR_SETTXPND_Msk (0x01UL << CAN_MO_MOCTR_SETTXPND_Pos) /*!< CAN_MO MOCTR: SETTXPND Mask */
\r
9841 #define CAN_MO_MOCTR_SETRXUPD_Pos 18 /*!< CAN_MO MOCTR: SETRXUPD Position */
\r
9842 #define CAN_MO_MOCTR_SETRXUPD_Msk (0x01UL << CAN_MO_MOCTR_SETRXUPD_Pos) /*!< CAN_MO MOCTR: SETRXUPD Mask */
\r
9843 #define CAN_MO_MOCTR_SETNEWDAT_Pos 19 /*!< CAN_MO MOCTR: SETNEWDAT Position */
\r
9844 #define CAN_MO_MOCTR_SETNEWDAT_Msk (0x01UL << CAN_MO_MOCTR_SETNEWDAT_Pos) /*!< CAN_MO MOCTR: SETNEWDAT Mask */
\r
9845 #define CAN_MO_MOCTR_SETMSGLST_Pos 20 /*!< CAN_MO MOCTR: SETMSGLST Position */
\r
9846 #define CAN_MO_MOCTR_SETMSGLST_Msk (0x01UL << CAN_MO_MOCTR_SETMSGLST_Pos) /*!< CAN_MO MOCTR: SETMSGLST Mask */
\r
9847 #define CAN_MO_MOCTR_SETMSGVAL_Pos 21 /*!< CAN_MO MOCTR: SETMSGVAL Position */
\r
9848 #define CAN_MO_MOCTR_SETMSGVAL_Msk (0x01UL << CAN_MO_MOCTR_SETMSGVAL_Pos) /*!< CAN_MO MOCTR: SETMSGVAL Mask */
\r
9849 #define CAN_MO_MOCTR_SETRTSEL_Pos 22 /*!< CAN_MO MOCTR: SETRTSEL Position */
\r
9850 #define CAN_MO_MOCTR_SETRTSEL_Msk (0x01UL << CAN_MO_MOCTR_SETRTSEL_Pos) /*!< CAN_MO MOCTR: SETRTSEL Mask */
\r
9851 #define CAN_MO_MOCTR_SETRXEN_Pos 23 /*!< CAN_MO MOCTR: SETRXEN Position */
\r
9852 #define CAN_MO_MOCTR_SETRXEN_Msk (0x01UL << CAN_MO_MOCTR_SETRXEN_Pos) /*!< CAN_MO MOCTR: SETRXEN Mask */
\r
9853 #define CAN_MO_MOCTR_SETTXRQ_Pos 24 /*!< CAN_MO MOCTR: SETTXRQ Position */
\r
9854 #define CAN_MO_MOCTR_SETTXRQ_Msk (0x01UL << CAN_MO_MOCTR_SETTXRQ_Pos) /*!< CAN_MO MOCTR: SETTXRQ Mask */
\r
9855 #define CAN_MO_MOCTR_SETTXEN0_Pos 25 /*!< CAN_MO MOCTR: SETTXEN0 Position */
\r
9856 #define CAN_MO_MOCTR_SETTXEN0_Msk (0x01UL << CAN_MO_MOCTR_SETTXEN0_Pos) /*!< CAN_MO MOCTR: SETTXEN0 Mask */
\r
9857 #define CAN_MO_MOCTR_SETTXEN1_Pos 26 /*!< CAN_MO MOCTR: SETTXEN1 Position */
\r
9858 #define CAN_MO_MOCTR_SETTXEN1_Msk (0x01UL << CAN_MO_MOCTR_SETTXEN1_Pos) /*!< CAN_MO MOCTR: SETTXEN1 Mask */
\r
9859 #define CAN_MO_MOCTR_SETDIR_Pos 27 /*!< CAN_MO MOCTR: SETDIR Position */
\r
9860 #define CAN_MO_MOCTR_SETDIR_Msk (0x01UL << CAN_MO_MOCTR_SETDIR_Pos) /*!< CAN_MO MOCTR: SETDIR Mask */
\r
9862 /* -------------------------------- CAN_MO_MOSTAT ------------------------------- */
\r
9863 #define CAN_MO_MOSTAT_RXPND_Pos 0 /*!< CAN_MO MOSTAT: RXPND Position */
\r
9864 #define CAN_MO_MOSTAT_RXPND_Msk (0x01UL << CAN_MO_MOSTAT_RXPND_Pos) /*!< CAN_MO MOSTAT: RXPND Mask */
\r
9865 #define CAN_MO_MOSTAT_TXPND_Pos 1 /*!< CAN_MO MOSTAT: TXPND Position */
\r
9866 #define CAN_MO_MOSTAT_TXPND_Msk (0x01UL << CAN_MO_MOSTAT_TXPND_Pos) /*!< CAN_MO MOSTAT: TXPND Mask */
\r
9867 #define CAN_MO_MOSTAT_RXUPD_Pos 2 /*!< CAN_MO MOSTAT: RXUPD Position */
\r
9868 #define CAN_MO_MOSTAT_RXUPD_Msk (0x01UL << CAN_MO_MOSTAT_RXUPD_Pos) /*!< CAN_MO MOSTAT: RXUPD Mask */
\r
9869 #define CAN_MO_MOSTAT_NEWDAT_Pos 3 /*!< CAN_MO MOSTAT: NEWDAT Position */
\r
9870 #define CAN_MO_MOSTAT_NEWDAT_Msk (0x01UL << CAN_MO_MOSTAT_NEWDAT_Pos) /*!< CAN_MO MOSTAT: NEWDAT Mask */
\r
9871 #define CAN_MO_MOSTAT_MSGLST_Pos 4 /*!< CAN_MO MOSTAT: MSGLST Position */
\r
9872 #define CAN_MO_MOSTAT_MSGLST_Msk (0x01UL << CAN_MO_MOSTAT_MSGLST_Pos) /*!< CAN_MO MOSTAT: MSGLST Mask */
\r
9873 #define CAN_MO_MOSTAT_MSGVAL_Pos 5 /*!< CAN_MO MOSTAT: MSGVAL Position */
\r
9874 #define CAN_MO_MOSTAT_MSGVAL_Msk (0x01UL << CAN_MO_MOSTAT_MSGVAL_Pos) /*!< CAN_MO MOSTAT: MSGVAL Mask */
\r
9875 #define CAN_MO_MOSTAT_RTSEL_Pos 6 /*!< CAN_MO MOSTAT: RTSEL Position */
\r
9876 #define CAN_MO_MOSTAT_RTSEL_Msk (0x01UL << CAN_MO_MOSTAT_RTSEL_Pos) /*!< CAN_MO MOSTAT: RTSEL Mask */
\r
9877 #define CAN_MO_MOSTAT_RXEN_Pos 7 /*!< CAN_MO MOSTAT: RXEN Position */
\r
9878 #define CAN_MO_MOSTAT_RXEN_Msk (0x01UL << CAN_MO_MOSTAT_RXEN_Pos) /*!< CAN_MO MOSTAT: RXEN Mask */
\r
9879 #define CAN_MO_MOSTAT_TXRQ_Pos 8 /*!< CAN_MO MOSTAT: TXRQ Position */
\r
9880 #define CAN_MO_MOSTAT_TXRQ_Msk (0x01UL << CAN_MO_MOSTAT_TXRQ_Pos) /*!< CAN_MO MOSTAT: TXRQ Mask */
\r
9881 #define CAN_MO_MOSTAT_TXEN0_Pos 9 /*!< CAN_MO MOSTAT: TXEN0 Position */
\r
9882 #define CAN_MO_MOSTAT_TXEN0_Msk (0x01UL << CAN_MO_MOSTAT_TXEN0_Pos) /*!< CAN_MO MOSTAT: TXEN0 Mask */
\r
9883 #define CAN_MO_MOSTAT_TXEN1_Pos 10 /*!< CAN_MO MOSTAT: TXEN1 Position */
\r
9884 #define CAN_MO_MOSTAT_TXEN1_Msk (0x01UL << CAN_MO_MOSTAT_TXEN1_Pos) /*!< CAN_MO MOSTAT: TXEN1 Mask */
\r
9885 #define CAN_MO_MOSTAT_DIR_Pos 11 /*!< CAN_MO MOSTAT: DIR Position */
\r
9886 #define CAN_MO_MOSTAT_DIR_Msk (0x01UL << CAN_MO_MOSTAT_DIR_Pos) /*!< CAN_MO MOSTAT: DIR Mask */
\r
9887 #define CAN_MO_MOSTAT_LIST_Pos 12 /*!< CAN_MO MOSTAT: LIST Position */
\r
9888 #define CAN_MO_MOSTAT_LIST_Msk (0x0fUL << CAN_MO_MOSTAT_LIST_Pos) /*!< CAN_MO MOSTAT: LIST Mask */
\r
9889 #define CAN_MO_MOSTAT_PPREV_Pos 16 /*!< CAN_MO MOSTAT: PPREV Position */
\r
9890 #define CAN_MO_MOSTAT_PPREV_Msk (0x000000ffUL << CAN_MO_MOSTAT_PPREV_Pos) /*!< CAN_MO MOSTAT: PPREV Mask */
\r
9891 #define CAN_MO_MOSTAT_PNEXT_Pos 24 /*!< CAN_MO MOSTAT: PNEXT Position */
\r
9892 #define CAN_MO_MOSTAT_PNEXT_Msk (0x000000ffUL << CAN_MO_MOSTAT_PNEXT_Pos) /*!< CAN_MO MOSTAT: PNEXT Mask */
\r
9895 /* ================================================================================ */
\r
9896 /* ================ struct 'VADC' Position & Mask ================ */
\r
9897 /* ================================================================================ */
\r
9900 /* ---------------------------------- VADC_CLC ---------------------------------- */
\r
9901 #define VADC_CLC_DISR_Pos 0 /*!< VADC CLC: DISR Position */
\r
9902 #define VADC_CLC_DISR_Msk (0x01UL << VADC_CLC_DISR_Pos) /*!< VADC CLC: DISR Mask */
\r
9903 #define VADC_CLC_DISS_Pos 1 /*!< VADC CLC: DISS Position */
\r
9904 #define VADC_CLC_DISS_Msk (0x01UL << VADC_CLC_DISS_Pos) /*!< VADC CLC: DISS Mask */
\r
9905 #define VADC_CLC_EDIS_Pos 3 /*!< VADC CLC: EDIS Position */
\r
9906 #define VADC_CLC_EDIS_Msk (0x01UL << VADC_CLC_EDIS_Pos) /*!< VADC CLC: EDIS Mask */
\r
9908 /* ----------------------------------- VADC_ID ---------------------------------- */
\r
9909 #define VADC_ID_MOD_REV_Pos 0 /*!< VADC ID: MOD_REV Position */
\r
9910 #define VADC_ID_MOD_REV_Msk (0x000000ffUL << VADC_ID_MOD_REV_Pos) /*!< VADC ID: MOD_REV Mask */
\r
9911 #define VADC_ID_MOD_TYPE_Pos 8 /*!< VADC ID: MOD_TYPE Position */
\r
9912 #define VADC_ID_MOD_TYPE_Msk (0x000000ffUL << VADC_ID_MOD_TYPE_Pos) /*!< VADC ID: MOD_TYPE Mask */
\r
9913 #define VADC_ID_MOD_NUMBER_Pos 16 /*!< VADC ID: MOD_NUMBER Position */
\r
9914 #define VADC_ID_MOD_NUMBER_Msk (0x0000ffffUL << VADC_ID_MOD_NUMBER_Pos) /*!< VADC ID: MOD_NUMBER Mask */
\r
9916 /* ---------------------------------- VADC_OCS ---------------------------------- */
\r
9917 #define VADC_OCS_TGS_Pos 0 /*!< VADC OCS: TGS Position */
\r
9918 #define VADC_OCS_TGS_Msk (0x03UL << VADC_OCS_TGS_Pos) /*!< VADC OCS: TGS Mask */
\r
9919 #define VADC_OCS_TGB_Pos 2 /*!< VADC OCS: TGB Position */
\r
9920 #define VADC_OCS_TGB_Msk (0x01UL << VADC_OCS_TGB_Pos) /*!< VADC OCS: TGB Mask */
\r
9921 #define VADC_OCS_TG_P_Pos 3 /*!< VADC OCS: TG_P Position */
\r
9922 #define VADC_OCS_TG_P_Msk (0x01UL << VADC_OCS_TG_P_Pos) /*!< VADC OCS: TG_P Mask */
\r
9923 #define VADC_OCS_SUS_Pos 24 /*!< VADC OCS: SUS Position */
\r
9924 #define VADC_OCS_SUS_Msk (0x0fUL << VADC_OCS_SUS_Pos) /*!< VADC OCS: SUS Mask */
\r
9925 #define VADC_OCS_SUS_P_Pos 28 /*!< VADC OCS: SUS_P Position */
\r
9926 #define VADC_OCS_SUS_P_Msk (0x01UL << VADC_OCS_SUS_P_Pos) /*!< VADC OCS: SUS_P Mask */
\r
9927 #define VADC_OCS_SUSSTA_Pos 29 /*!< VADC OCS: SUSSTA Position */
\r
9928 #define VADC_OCS_SUSSTA_Msk (0x01UL << VADC_OCS_SUSSTA_Pos) /*!< VADC OCS: SUSSTA Mask */
\r
9930 /* -------------------------------- VADC_GLOBCFG -------------------------------- */
\r
9931 #define VADC_GLOBCFG_DIVA_Pos 0 /*!< VADC GLOBCFG: DIVA Position */
\r
9932 #define VADC_GLOBCFG_DIVA_Msk (0x1fUL << VADC_GLOBCFG_DIVA_Pos) /*!< VADC GLOBCFG: DIVA Mask */
\r
9933 #define VADC_GLOBCFG_DCMSB_Pos 7 /*!< VADC GLOBCFG: DCMSB Position */
\r
9934 #define VADC_GLOBCFG_DCMSB_Msk (0x01UL << VADC_GLOBCFG_DCMSB_Pos) /*!< VADC GLOBCFG: DCMSB Mask */
\r
9935 #define VADC_GLOBCFG_DIVD_Pos 8 /*!< VADC GLOBCFG: DIVD Position */
\r
9936 #define VADC_GLOBCFG_DIVD_Msk (0x03UL << VADC_GLOBCFG_DIVD_Pos) /*!< VADC GLOBCFG: DIVD Mask */
\r
9937 #define VADC_GLOBCFG_DIVWC_Pos 15 /*!< VADC GLOBCFG: DIVWC Position */
\r
9938 #define VADC_GLOBCFG_DIVWC_Msk (0x01UL << VADC_GLOBCFG_DIVWC_Pos) /*!< VADC GLOBCFG: DIVWC Mask */
\r
9939 #define VADC_GLOBCFG_DPCAL0_Pos 16 /*!< VADC GLOBCFG: DPCAL0 Position */
\r
9940 #define VADC_GLOBCFG_DPCAL0_Msk (0x01UL << VADC_GLOBCFG_DPCAL0_Pos) /*!< VADC GLOBCFG: DPCAL0 Mask */
\r
9941 #define VADC_GLOBCFG_DPCAL1_Pos 17 /*!< VADC GLOBCFG: DPCAL1 Position */
\r
9942 #define VADC_GLOBCFG_DPCAL1_Msk (0x01UL << VADC_GLOBCFG_DPCAL1_Pos) /*!< VADC GLOBCFG: DPCAL1 Mask */
\r
9943 #define VADC_GLOBCFG_DPCAL2_Pos 18 /*!< VADC GLOBCFG: DPCAL2 Position */
\r
9944 #define VADC_GLOBCFG_DPCAL2_Msk (0x01UL << VADC_GLOBCFG_DPCAL2_Pos) /*!< VADC GLOBCFG: DPCAL2 Mask */
\r
9945 #define VADC_GLOBCFG_DPCAL3_Pos 19 /*!< VADC GLOBCFG: DPCAL3 Position */
\r
9946 #define VADC_GLOBCFG_DPCAL3_Msk (0x01UL << VADC_GLOBCFG_DPCAL3_Pos) /*!< VADC GLOBCFG: DPCAL3 Mask */
\r
9947 #define VADC_GLOBCFG_SUCAL_Pos 31 /*!< VADC GLOBCFG: SUCAL Position */
\r
9948 #define VADC_GLOBCFG_SUCAL_Msk (0x01UL << VADC_GLOBCFG_SUCAL_Pos) /*!< VADC GLOBCFG: SUCAL Mask */
\r
9950 /* ------------------------------- VADC_GLOBICLASS ------------------------------ */
\r
9951 #define VADC_GLOBICLASS_STCS_Pos 0 /*!< VADC GLOBICLASS: STCS Position */
\r
9952 #define VADC_GLOBICLASS_STCS_Msk (0x1fUL << VADC_GLOBICLASS_STCS_Pos) /*!< VADC GLOBICLASS: STCS Mask */
\r
9953 #define VADC_GLOBICLASS_CMS_Pos 8 /*!< VADC GLOBICLASS: CMS Position */
\r
9954 #define VADC_GLOBICLASS_CMS_Msk (0x07UL << VADC_GLOBICLASS_CMS_Pos) /*!< VADC GLOBICLASS: CMS Mask */
\r
9955 #define VADC_GLOBICLASS_STCE_Pos 16 /*!< VADC GLOBICLASS: STCE Position */
\r
9956 #define VADC_GLOBICLASS_STCE_Msk (0x1fUL << VADC_GLOBICLASS_STCE_Pos) /*!< VADC GLOBICLASS: STCE Mask */
\r
9957 #define VADC_GLOBICLASS_CME_Pos 24 /*!< VADC GLOBICLASS: CME Position */
\r
9958 #define VADC_GLOBICLASS_CME_Msk (0x07UL << VADC_GLOBICLASS_CME_Pos) /*!< VADC GLOBICLASS: CME Mask */
\r
9960 /* ------------------------------- VADC_GLOBBOUND ------------------------------- */
\r
9961 #define VADC_GLOBBOUND_BOUNDARY0_Pos 0 /*!< VADC GLOBBOUND: BOUNDARY0 Position */
\r
9962 #define VADC_GLOBBOUND_BOUNDARY0_Msk (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY0_Pos) /*!< VADC GLOBBOUND: BOUNDARY0 Mask */
\r
9963 #define VADC_GLOBBOUND_BOUNDARY1_Pos 16 /*!< VADC GLOBBOUND: BOUNDARY1 Position */
\r
9964 #define VADC_GLOBBOUND_BOUNDARY1_Msk (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY1_Pos) /*!< VADC GLOBBOUND: BOUNDARY1 Mask */
\r
9966 /* ------------------------------- VADC_GLOBEFLAG ------------------------------- */
\r
9967 #define VADC_GLOBEFLAG_SEVGLB_Pos 0 /*!< VADC GLOBEFLAG: SEVGLB Position */
\r
9968 #define VADC_GLOBEFLAG_SEVGLB_Msk (0x01UL << VADC_GLOBEFLAG_SEVGLB_Pos) /*!< VADC GLOBEFLAG: SEVGLB Mask */
\r
9969 #define VADC_GLOBEFLAG_REVGLB_Pos 8 /*!< VADC GLOBEFLAG: REVGLB Position */
\r
9970 #define VADC_GLOBEFLAG_REVGLB_Msk (0x01UL << VADC_GLOBEFLAG_REVGLB_Pos) /*!< VADC GLOBEFLAG: REVGLB Mask */
\r
9971 #define VADC_GLOBEFLAG_SEVGLBCLR_Pos 16 /*!< VADC GLOBEFLAG: SEVGLBCLR Position */
\r
9972 #define VADC_GLOBEFLAG_SEVGLBCLR_Msk (0x01UL << VADC_GLOBEFLAG_SEVGLBCLR_Pos) /*!< VADC GLOBEFLAG: SEVGLBCLR Mask */
\r
9973 #define VADC_GLOBEFLAG_REVGLBCLR_Pos 24 /*!< VADC GLOBEFLAG: REVGLBCLR Position */
\r
9974 #define VADC_GLOBEFLAG_REVGLBCLR_Msk (0x01UL << VADC_GLOBEFLAG_REVGLBCLR_Pos) /*!< VADC GLOBEFLAG: REVGLBCLR Mask */
\r
9976 /* -------------------------------- VADC_GLOBEVNP ------------------------------- */
\r
9977 #define VADC_GLOBEVNP_SEV0NP_Pos 0 /*!< VADC GLOBEVNP: SEV0NP Position */
\r
9978 #define VADC_GLOBEVNP_SEV0NP_Msk (0x0fUL << VADC_GLOBEVNP_SEV0NP_Pos) /*!< VADC GLOBEVNP: SEV0NP Mask */
\r
9979 #define VADC_GLOBEVNP_REV0NP_Pos 16 /*!< VADC GLOBEVNP: REV0NP Position */
\r
9980 #define VADC_GLOBEVNP_REV0NP_Msk (0x0fUL << VADC_GLOBEVNP_REV0NP_Pos) /*!< VADC GLOBEVNP: REV0NP Mask */
\r
9982 /* --------------------------------- VADC_GLOBTF -------------------------------- */
\r
9983 #define VADC_GLOBTF_CDGR_Pos 4 /*!< VADC GLOBTF: CDGR Position */
\r
9984 #define VADC_GLOBTF_CDGR_Msk (0x0fUL << VADC_GLOBTF_CDGR_Pos) /*!< VADC GLOBTF: CDGR Mask */
\r
9985 #define VADC_GLOBTF_CDEN_Pos 8 /*!< VADC GLOBTF: CDEN Position */
\r
9986 #define VADC_GLOBTF_CDEN_Msk (0x01UL << VADC_GLOBTF_CDEN_Pos) /*!< VADC GLOBTF: CDEN Mask */
\r
9987 #define VADC_GLOBTF_CDSEL_Pos 9 /*!< VADC GLOBTF: CDSEL Position */
\r
9988 #define VADC_GLOBTF_CDSEL_Msk (0x03UL << VADC_GLOBTF_CDSEL_Pos) /*!< VADC GLOBTF: CDSEL Mask */
\r
9989 #define VADC_GLOBTF_CDWC_Pos 15 /*!< VADC GLOBTF: CDWC Position */
\r
9990 #define VADC_GLOBTF_CDWC_Msk (0x01UL << VADC_GLOBTF_CDWC_Pos) /*!< VADC GLOBTF: CDWC Mask */
\r
9991 #define VADC_GLOBTF_PDD_Pos 16 /*!< VADC GLOBTF: PDD Position */
\r
9992 #define VADC_GLOBTF_PDD_Msk (0x01UL << VADC_GLOBTF_PDD_Pos) /*!< VADC GLOBTF: PDD Mask */
\r
9993 #define VADC_GLOBTF_MDWC_Pos 23 /*!< VADC GLOBTF: MDWC Position */
\r
9994 #define VADC_GLOBTF_MDWC_Msk (0x01UL << VADC_GLOBTF_MDWC_Pos) /*!< VADC GLOBTF: MDWC Mask */
\r
9996 /* --------------------------------- VADC_BRSSEL -------------------------------- */
\r
9997 #define VADC_BRSSEL_CHSELG0_Pos 0 /*!< VADC BRSSEL: CHSELG0 Position */
\r
9998 #define VADC_BRSSEL_CHSELG0_Msk (0x01UL << VADC_BRSSEL_CHSELG0_Pos) /*!< VADC BRSSEL: CHSELG0 Mask */
\r
9999 #define VADC_BRSSEL_CHSELG1_Pos 1 /*!< VADC BRSSEL: CHSELG1 Position */
\r
10000 #define VADC_BRSSEL_CHSELG1_Msk (0x01UL << VADC_BRSSEL_CHSELG1_Pos) /*!< VADC BRSSEL: CHSELG1 Mask */
\r
10001 #define VADC_BRSSEL_CHSELG2_Pos 2 /*!< VADC BRSSEL: CHSELG2 Position */
\r
10002 #define VADC_BRSSEL_CHSELG2_Msk (0x01UL << VADC_BRSSEL_CHSELG2_Pos) /*!< VADC BRSSEL: CHSELG2 Mask */
\r
10003 #define VADC_BRSSEL_CHSELG3_Pos 3 /*!< VADC BRSSEL: CHSELG3 Position */
\r
10004 #define VADC_BRSSEL_CHSELG3_Msk (0x01UL << VADC_BRSSEL_CHSELG3_Pos) /*!< VADC BRSSEL: CHSELG3 Mask */
\r
10005 #define VADC_BRSSEL_CHSELG4_Pos 4 /*!< VADC BRSSEL: CHSELG4 Position */
\r
10006 #define VADC_BRSSEL_CHSELG4_Msk (0x01UL << VADC_BRSSEL_CHSELG4_Pos) /*!< VADC BRSSEL: CHSELG4 Mask */
\r
10007 #define VADC_BRSSEL_CHSELG5_Pos 5 /*!< VADC BRSSEL: CHSELG5 Position */
\r
10008 #define VADC_BRSSEL_CHSELG5_Msk (0x01UL << VADC_BRSSEL_CHSELG5_Pos) /*!< VADC BRSSEL: CHSELG5 Mask */
\r
10009 #define VADC_BRSSEL_CHSELG6_Pos 6 /*!< VADC BRSSEL: CHSELG6 Position */
\r
10010 #define VADC_BRSSEL_CHSELG6_Msk (0x01UL << VADC_BRSSEL_CHSELG6_Pos) /*!< VADC BRSSEL: CHSELG6 Mask */
\r
10011 #define VADC_BRSSEL_CHSELG7_Pos 7 /*!< VADC BRSSEL: CHSELG7 Position */
\r
10012 #define VADC_BRSSEL_CHSELG7_Msk (0x01UL << VADC_BRSSEL_CHSELG7_Pos) /*!< VADC BRSSEL: CHSELG7 Mask */
\r
10014 /* --------------------------------- VADC_BRSPND -------------------------------- */
\r
10015 #define VADC_BRSPND_CHPNDG0_Pos 0 /*!< VADC BRSPND: CHPNDG0 Position */
\r
10016 #define VADC_BRSPND_CHPNDG0_Msk (0x01UL << VADC_BRSPND_CHPNDG0_Pos) /*!< VADC BRSPND: CHPNDG0 Mask */
\r
10017 #define VADC_BRSPND_CHPNDG1_Pos 1 /*!< VADC BRSPND: CHPNDG1 Position */
\r
10018 #define VADC_BRSPND_CHPNDG1_Msk (0x01UL << VADC_BRSPND_CHPNDG1_Pos) /*!< VADC BRSPND: CHPNDG1 Mask */
\r
10019 #define VADC_BRSPND_CHPNDG2_Pos 2 /*!< VADC BRSPND: CHPNDG2 Position */
\r
10020 #define VADC_BRSPND_CHPNDG2_Msk (0x01UL << VADC_BRSPND_CHPNDG2_Pos) /*!< VADC BRSPND: CHPNDG2 Mask */
\r
10021 #define VADC_BRSPND_CHPNDG3_Pos 3 /*!< VADC BRSPND: CHPNDG3 Position */
\r
10022 #define VADC_BRSPND_CHPNDG3_Msk (0x01UL << VADC_BRSPND_CHPNDG3_Pos) /*!< VADC BRSPND: CHPNDG3 Mask */
\r
10023 #define VADC_BRSPND_CHPNDG4_Pos 4 /*!< VADC BRSPND: CHPNDG4 Position */
\r
10024 #define VADC_BRSPND_CHPNDG4_Msk (0x01UL << VADC_BRSPND_CHPNDG4_Pos) /*!< VADC BRSPND: CHPNDG4 Mask */
\r
10025 #define VADC_BRSPND_CHPNDG5_Pos 5 /*!< VADC BRSPND: CHPNDG5 Position */
\r
10026 #define VADC_BRSPND_CHPNDG5_Msk (0x01UL << VADC_BRSPND_CHPNDG5_Pos) /*!< VADC BRSPND: CHPNDG5 Mask */
\r
10027 #define VADC_BRSPND_CHPNDG6_Pos 6 /*!< VADC BRSPND: CHPNDG6 Position */
\r
10028 #define VADC_BRSPND_CHPNDG6_Msk (0x01UL << VADC_BRSPND_CHPNDG6_Pos) /*!< VADC BRSPND: CHPNDG6 Mask */
\r
10029 #define VADC_BRSPND_CHPNDG7_Pos 7 /*!< VADC BRSPND: CHPNDG7 Position */
\r
10030 #define VADC_BRSPND_CHPNDG7_Msk (0x01UL << VADC_BRSPND_CHPNDG7_Pos) /*!< VADC BRSPND: CHPNDG7 Mask */
\r
10032 /* -------------------------------- VADC_BRSCTRL -------------------------------- */
\r
10033 #define VADC_BRSCTRL_XTSEL_Pos 8 /*!< VADC BRSCTRL: XTSEL Position */
\r
10034 #define VADC_BRSCTRL_XTSEL_Msk (0x0fUL << VADC_BRSCTRL_XTSEL_Pos) /*!< VADC BRSCTRL: XTSEL Mask */
\r
10035 #define VADC_BRSCTRL_XTLVL_Pos 12 /*!< VADC BRSCTRL: XTLVL Position */
\r
10036 #define VADC_BRSCTRL_XTLVL_Msk (0x01UL << VADC_BRSCTRL_XTLVL_Pos) /*!< VADC BRSCTRL: XTLVL Mask */
\r
10037 #define VADC_BRSCTRL_XTMODE_Pos 13 /*!< VADC BRSCTRL: XTMODE Position */
\r
10038 #define VADC_BRSCTRL_XTMODE_Msk (0x03UL << VADC_BRSCTRL_XTMODE_Pos) /*!< VADC BRSCTRL: XTMODE Mask */
\r
10039 #define VADC_BRSCTRL_XTWC_Pos 15 /*!< VADC BRSCTRL: XTWC Position */
\r
10040 #define VADC_BRSCTRL_XTWC_Msk (0x01UL << VADC_BRSCTRL_XTWC_Pos) /*!< VADC BRSCTRL: XTWC Mask */
\r
10041 #define VADC_BRSCTRL_GTSEL_Pos 16 /*!< VADC BRSCTRL: GTSEL Position */
\r
10042 #define VADC_BRSCTRL_GTSEL_Msk (0x0fUL << VADC_BRSCTRL_GTSEL_Pos) /*!< VADC BRSCTRL: GTSEL Mask */
\r
10043 #define VADC_BRSCTRL_GTLVL_Pos 20 /*!< VADC BRSCTRL: GTLVL Position */
\r
10044 #define VADC_BRSCTRL_GTLVL_Msk (0x01UL << VADC_BRSCTRL_GTLVL_Pos) /*!< VADC BRSCTRL: GTLVL Mask */
\r
10045 #define VADC_BRSCTRL_GTWC_Pos 23 /*!< VADC BRSCTRL: GTWC Position */
\r
10046 #define VADC_BRSCTRL_GTWC_Msk (0x01UL << VADC_BRSCTRL_GTWC_Pos) /*!< VADC BRSCTRL: GTWC Mask */
\r
10048 /* --------------------------------- VADC_BRSMR --------------------------------- */
\r
10049 #define VADC_BRSMR_ENGT_Pos 0 /*!< VADC BRSMR: ENGT Position */
\r
10050 #define VADC_BRSMR_ENGT_Msk (0x03UL << VADC_BRSMR_ENGT_Pos) /*!< VADC BRSMR: ENGT Mask */
\r
10051 #define VADC_BRSMR_ENTR_Pos 2 /*!< VADC BRSMR: ENTR Position */
\r
10052 #define VADC_BRSMR_ENTR_Msk (0x01UL << VADC_BRSMR_ENTR_Pos) /*!< VADC BRSMR: ENTR Mask */
\r
10053 #define VADC_BRSMR_ENSI_Pos 3 /*!< VADC BRSMR: ENSI Position */
\r
10054 #define VADC_BRSMR_ENSI_Msk (0x01UL << VADC_BRSMR_ENSI_Pos) /*!< VADC BRSMR: ENSI Mask */
\r
10055 #define VADC_BRSMR_SCAN_Pos 4 /*!< VADC BRSMR: SCAN Position */
\r
10056 #define VADC_BRSMR_SCAN_Msk (0x01UL << VADC_BRSMR_SCAN_Pos) /*!< VADC BRSMR: SCAN Mask */
\r
10057 #define VADC_BRSMR_LDM_Pos 5 /*!< VADC BRSMR: LDM Position */
\r
10058 #define VADC_BRSMR_LDM_Msk (0x01UL << VADC_BRSMR_LDM_Pos) /*!< VADC BRSMR: LDM Mask */
\r
10059 #define VADC_BRSMR_REQGT_Pos 7 /*!< VADC BRSMR: REQGT Position */
\r
10060 #define VADC_BRSMR_REQGT_Msk (0x01UL << VADC_BRSMR_REQGT_Pos) /*!< VADC BRSMR: REQGT Mask */
\r
10061 #define VADC_BRSMR_CLRPND_Pos 8 /*!< VADC BRSMR: CLRPND Position */
\r
10062 #define VADC_BRSMR_CLRPND_Msk (0x01UL << VADC_BRSMR_CLRPND_Pos) /*!< VADC BRSMR: CLRPND Mask */
\r
10063 #define VADC_BRSMR_LDEV_Pos 9 /*!< VADC BRSMR: LDEV Position */
\r
10064 #define VADC_BRSMR_LDEV_Msk (0x01UL << VADC_BRSMR_LDEV_Pos) /*!< VADC BRSMR: LDEV Mask */
\r
10065 #define VADC_BRSMR_RPTDIS_Pos 16 /*!< VADC BRSMR: RPTDIS Position */
\r
10066 #define VADC_BRSMR_RPTDIS_Msk (0x01UL << VADC_BRSMR_RPTDIS_Pos) /*!< VADC BRSMR: RPTDIS Mask */
\r
10068 /* -------------------------------- VADC_GLOBRCR -------------------------------- */
\r
10069 #define VADC_GLOBRCR_DRCTR_Pos 16 /*!< VADC GLOBRCR: DRCTR Position */
\r
10070 #define VADC_GLOBRCR_DRCTR_Msk (0x0fUL << VADC_GLOBRCR_DRCTR_Pos) /*!< VADC GLOBRCR: DRCTR Mask */
\r
10071 #define VADC_GLOBRCR_WFR_Pos 24 /*!< VADC GLOBRCR: WFR Position */
\r
10072 #define VADC_GLOBRCR_WFR_Msk (0x01UL << VADC_GLOBRCR_WFR_Pos) /*!< VADC GLOBRCR: WFR Mask */
\r
10073 #define VADC_GLOBRCR_SRGEN_Pos 31 /*!< VADC GLOBRCR: SRGEN Position */
\r
10074 #define VADC_GLOBRCR_SRGEN_Msk (0x01UL << VADC_GLOBRCR_SRGEN_Pos) /*!< VADC GLOBRCR: SRGEN Mask */
\r
10076 /* -------------------------------- VADC_GLOBRES -------------------------------- */
\r
10077 #define VADC_GLOBRES_RESULT_Pos 0 /*!< VADC GLOBRES: RESULT Position */
\r
10078 #define VADC_GLOBRES_RESULT_Msk (0x0000ffffUL << VADC_GLOBRES_RESULT_Pos) /*!< VADC GLOBRES: RESULT Mask */
\r
10079 #define VADC_GLOBRES_GNR_Pos 16 /*!< VADC GLOBRES: GNR Position */
\r
10080 #define VADC_GLOBRES_GNR_Msk (0x0fUL << VADC_GLOBRES_GNR_Pos) /*!< VADC GLOBRES: GNR Mask */
\r
10081 #define VADC_GLOBRES_CHNR_Pos 20 /*!< VADC GLOBRES: CHNR Position */
\r
10082 #define VADC_GLOBRES_CHNR_Msk (0x1fUL << VADC_GLOBRES_CHNR_Pos) /*!< VADC GLOBRES: CHNR Mask */
\r
10083 #define VADC_GLOBRES_EMUX_Pos 25 /*!< VADC GLOBRES: EMUX Position */
\r
10084 #define VADC_GLOBRES_EMUX_Msk (0x07UL << VADC_GLOBRES_EMUX_Pos) /*!< VADC GLOBRES: EMUX Mask */
\r
10085 #define VADC_GLOBRES_CRS_Pos 28 /*!< VADC GLOBRES: CRS Position */
\r
10086 #define VADC_GLOBRES_CRS_Msk (0x03UL << VADC_GLOBRES_CRS_Pos) /*!< VADC GLOBRES: CRS Mask */
\r
10087 #define VADC_GLOBRES_FCR_Pos 30 /*!< VADC GLOBRES: FCR Position */
\r
10088 #define VADC_GLOBRES_FCR_Msk (0x01UL << VADC_GLOBRES_FCR_Pos) /*!< VADC GLOBRES: FCR Mask */
\r
10089 #define VADC_GLOBRES_VF_Pos 31 /*!< VADC GLOBRES: VF Position */
\r
10090 #define VADC_GLOBRES_VF_Msk (0x01UL << VADC_GLOBRES_VF_Pos) /*!< VADC GLOBRES: VF Mask */
\r
10092 /* -------------------------------- VADC_GLOBRESD ------------------------------- */
\r
10093 #define VADC_GLOBRESD_RESULT_Pos 0 /*!< VADC GLOBRESD: RESULT Position */
\r
10094 #define VADC_GLOBRESD_RESULT_Msk (0x0000ffffUL << VADC_GLOBRESD_RESULT_Pos) /*!< VADC GLOBRESD: RESULT Mask */
\r
10095 #define VADC_GLOBRESD_GNR_Pos 16 /*!< VADC GLOBRESD: GNR Position */
\r
10096 #define VADC_GLOBRESD_GNR_Msk (0x0fUL << VADC_GLOBRESD_GNR_Pos) /*!< VADC GLOBRESD: GNR Mask */
\r
10097 #define VADC_GLOBRESD_CHNR_Pos 20 /*!< VADC GLOBRESD: CHNR Position */
\r
10098 #define VADC_GLOBRESD_CHNR_Msk (0x1fUL << VADC_GLOBRESD_CHNR_Pos) /*!< VADC GLOBRESD: CHNR Mask */
\r
10099 #define VADC_GLOBRESD_EMUX_Pos 25 /*!< VADC GLOBRESD: EMUX Position */
\r
10100 #define VADC_GLOBRESD_EMUX_Msk (0x07UL << VADC_GLOBRESD_EMUX_Pos) /*!< VADC GLOBRESD: EMUX Mask */
\r
10101 #define VADC_GLOBRESD_CRS_Pos 28 /*!< VADC GLOBRESD: CRS Position */
\r
10102 #define VADC_GLOBRESD_CRS_Msk (0x03UL << VADC_GLOBRESD_CRS_Pos) /*!< VADC GLOBRESD: CRS Mask */
\r
10103 #define VADC_GLOBRESD_FCR_Pos 30 /*!< VADC GLOBRESD: FCR Position */
\r
10104 #define VADC_GLOBRESD_FCR_Msk (0x01UL << VADC_GLOBRESD_FCR_Pos) /*!< VADC GLOBRESD: FCR Mask */
\r
10105 #define VADC_GLOBRESD_VF_Pos 31 /*!< VADC GLOBRESD: VF Position */
\r
10106 #define VADC_GLOBRESD_VF_Msk (0x01UL << VADC_GLOBRESD_VF_Pos) /*!< VADC GLOBRESD: VF Mask */
\r
10108 /* -------------------------------- VADC_EMUXSEL -------------------------------- */
\r
10109 #define VADC_EMUXSEL_EMUXGRP0_Pos 0 /*!< VADC EMUXSEL: EMUXGRP0 Position */
\r
10110 #define VADC_EMUXSEL_EMUXGRP0_Msk (0x0fUL << VADC_EMUXSEL_EMUXGRP0_Pos) /*!< VADC EMUXSEL: EMUXGRP0 Mask */
\r
10111 #define VADC_EMUXSEL_EMUXGRP1_Pos 4 /*!< VADC EMUXSEL: EMUXGRP1 Position */
\r
10112 #define VADC_EMUXSEL_EMUXGRP1_Msk (0x0fUL << VADC_EMUXSEL_EMUXGRP1_Pos) /*!< VADC EMUXSEL: EMUXGRP1 Mask */
\r
10115 /* ================================================================================ */
\r
10116 /* ================ Group 'VADC_G' Position & Mask ================ */
\r
10117 /* ================================================================================ */
\r
10120 /* -------------------------------- VADC_G_ARBCFG ------------------------------- */
\r
10121 #define VADC_G_ARBCFG_ANONC_Pos 0 /*!< VADC_G ARBCFG: ANONC Position */
\r
10122 #define VADC_G_ARBCFG_ANONC_Msk (0x03UL << VADC_G_ARBCFG_ANONC_Pos) /*!< VADC_G ARBCFG: ANONC Mask */
\r
10123 #define VADC_G_ARBCFG_ARBRND_Pos 4 /*!< VADC_G ARBCFG: ARBRND Position */
\r
10124 #define VADC_G_ARBCFG_ARBRND_Msk (0x03UL << VADC_G_ARBCFG_ARBRND_Pos) /*!< VADC_G ARBCFG: ARBRND Mask */
\r
10125 #define VADC_G_ARBCFG_ARBM_Pos 7 /*!< VADC_G ARBCFG: ARBM Position */
\r
10126 #define VADC_G_ARBCFG_ARBM_Msk (0x01UL << VADC_G_ARBCFG_ARBM_Pos) /*!< VADC_G ARBCFG: ARBM Mask */
\r
10127 #define VADC_G_ARBCFG_ANONS_Pos 16 /*!< VADC_G ARBCFG: ANONS Position */
\r
10128 #define VADC_G_ARBCFG_ANONS_Msk (0x03UL << VADC_G_ARBCFG_ANONS_Pos) /*!< VADC_G ARBCFG: ANONS Mask */
\r
10129 #define VADC_G_ARBCFG_CAL_Pos 28 /*!< VADC_G ARBCFG: CAL Position */
\r
10130 #define VADC_G_ARBCFG_CAL_Msk (0x01UL << VADC_G_ARBCFG_CAL_Pos) /*!< VADC_G ARBCFG: CAL Mask */
\r
10131 #define VADC_G_ARBCFG_BUSY_Pos 30 /*!< VADC_G ARBCFG: BUSY Position */
\r
10132 #define VADC_G_ARBCFG_BUSY_Msk (0x01UL << VADC_G_ARBCFG_BUSY_Pos) /*!< VADC_G ARBCFG: BUSY Mask */
\r
10133 #define VADC_G_ARBCFG_SAMPLE_Pos 31 /*!< VADC_G ARBCFG: SAMPLE Position */
\r
10134 #define VADC_G_ARBCFG_SAMPLE_Msk (0x01UL << VADC_G_ARBCFG_SAMPLE_Pos) /*!< VADC_G ARBCFG: SAMPLE Mask */
\r
10136 /* -------------------------------- VADC_G_ARBPR -------------------------------- */
\r
10137 #define VADC_G_ARBPR_PRIO0_Pos 0 /*!< VADC_G ARBPR: PRIO0 Position */
\r
10138 #define VADC_G_ARBPR_PRIO0_Msk (0x03UL << VADC_G_ARBPR_PRIO0_Pos) /*!< VADC_G ARBPR: PRIO0 Mask */
\r
10139 #define VADC_G_ARBPR_CSM0_Pos 3 /*!< VADC_G ARBPR: CSM0 Position */
\r
10140 #define VADC_G_ARBPR_CSM0_Msk (0x01UL << VADC_G_ARBPR_CSM0_Pos) /*!< VADC_G ARBPR: CSM0 Mask */
\r
10141 #define VADC_G_ARBPR_PRIO1_Pos 4 /*!< VADC_G ARBPR: PRIO1 Position */
\r
10142 #define VADC_G_ARBPR_PRIO1_Msk (0x03UL << VADC_G_ARBPR_PRIO1_Pos) /*!< VADC_G ARBPR: PRIO1 Mask */
\r
10143 #define VADC_G_ARBPR_CSM1_Pos 7 /*!< VADC_G ARBPR: CSM1 Position */
\r
10144 #define VADC_G_ARBPR_CSM1_Msk (0x01UL << VADC_G_ARBPR_CSM1_Pos) /*!< VADC_G ARBPR: CSM1 Mask */
\r
10145 #define VADC_G_ARBPR_PRIO2_Pos 8 /*!< VADC_G ARBPR: PRIO2 Position */
\r
10146 #define VADC_G_ARBPR_PRIO2_Msk (0x03UL << VADC_G_ARBPR_PRIO2_Pos) /*!< VADC_G ARBPR: PRIO2 Mask */
\r
10147 #define VADC_G_ARBPR_CSM2_Pos 11 /*!< VADC_G ARBPR: CSM2 Position */
\r
10148 #define VADC_G_ARBPR_CSM2_Msk (0x01UL << VADC_G_ARBPR_CSM2_Pos) /*!< VADC_G ARBPR: CSM2 Mask */
\r
10149 #define VADC_G_ARBPR_ASEN0_Pos 24 /*!< VADC_G ARBPR: ASEN0 Position */
\r
10150 #define VADC_G_ARBPR_ASEN0_Msk (0x01UL << VADC_G_ARBPR_ASEN0_Pos) /*!< VADC_G ARBPR: ASEN0 Mask */
\r
10151 #define VADC_G_ARBPR_ASEN1_Pos 25 /*!< VADC_G ARBPR: ASEN1 Position */
\r
10152 #define VADC_G_ARBPR_ASEN1_Msk (0x01UL << VADC_G_ARBPR_ASEN1_Pos) /*!< VADC_G ARBPR: ASEN1 Mask */
\r
10153 #define VADC_G_ARBPR_ASEN2_Pos 26 /*!< VADC_G ARBPR: ASEN2 Position */
\r
10154 #define VADC_G_ARBPR_ASEN2_Msk (0x01UL << VADC_G_ARBPR_ASEN2_Pos) /*!< VADC_G ARBPR: ASEN2 Mask */
\r
10156 /* -------------------------------- VADC_G_CHASS -------------------------------- */
\r
10157 #define VADC_G_CHASS_ASSCH0_Pos 0 /*!< VADC_G CHASS: ASSCH0 Position */
\r
10158 #define VADC_G_CHASS_ASSCH0_Msk (0x01UL << VADC_G_CHASS_ASSCH0_Pos) /*!< VADC_G CHASS: ASSCH0 Mask */
\r
10159 #define VADC_G_CHASS_ASSCH1_Pos 1 /*!< VADC_G CHASS: ASSCH1 Position */
\r
10160 #define VADC_G_CHASS_ASSCH1_Msk (0x01UL << VADC_G_CHASS_ASSCH1_Pos) /*!< VADC_G CHASS: ASSCH1 Mask */
\r
10161 #define VADC_G_CHASS_ASSCH2_Pos 2 /*!< VADC_G CHASS: ASSCH2 Position */
\r
10162 #define VADC_G_CHASS_ASSCH2_Msk (0x01UL << VADC_G_CHASS_ASSCH2_Pos) /*!< VADC_G CHASS: ASSCH2 Mask */
\r
10163 #define VADC_G_CHASS_ASSCH3_Pos 3 /*!< VADC_G CHASS: ASSCH3 Position */
\r
10164 #define VADC_G_CHASS_ASSCH3_Msk (0x01UL << VADC_G_CHASS_ASSCH3_Pos) /*!< VADC_G CHASS: ASSCH3 Mask */
\r
10165 #define VADC_G_CHASS_ASSCH4_Pos 4 /*!< VADC_G CHASS: ASSCH4 Position */
\r
10166 #define VADC_G_CHASS_ASSCH4_Msk (0x01UL << VADC_G_CHASS_ASSCH4_Pos) /*!< VADC_G CHASS: ASSCH4 Mask */
\r
10167 #define VADC_G_CHASS_ASSCH5_Pos 5 /*!< VADC_G CHASS: ASSCH5 Position */
\r
10168 #define VADC_G_CHASS_ASSCH5_Msk (0x01UL << VADC_G_CHASS_ASSCH5_Pos) /*!< VADC_G CHASS: ASSCH5 Mask */
\r
10169 #define VADC_G_CHASS_ASSCH6_Pos 6 /*!< VADC_G CHASS: ASSCH6 Position */
\r
10170 #define VADC_G_CHASS_ASSCH6_Msk (0x01UL << VADC_G_CHASS_ASSCH6_Pos) /*!< VADC_G CHASS: ASSCH6 Mask */
\r
10171 #define VADC_G_CHASS_ASSCH7_Pos 7 /*!< VADC_G CHASS: ASSCH7 Position */
\r
10172 #define VADC_G_CHASS_ASSCH7_Msk (0x01UL << VADC_G_CHASS_ASSCH7_Pos) /*!< VADC_G CHASS: ASSCH7 Mask */
\r
10174 /* -------------------------------- VADC_G_ICLASS ------------------------------- */
\r
10175 #define VADC_G_ICLASS_STCS_Pos 0 /*!< VADC_G ICLASS: STCS Position */
\r
10176 #define VADC_G_ICLASS_STCS_Msk (0x1fUL << VADC_G_ICLASS_STCS_Pos) /*!< VADC_G ICLASS: STCS Mask */
\r
10177 #define VADC_G_ICLASS_CMS_Pos 8 /*!< VADC_G ICLASS: CMS Position */
\r
10178 #define VADC_G_ICLASS_CMS_Msk (0x07UL << VADC_G_ICLASS_CMS_Pos) /*!< VADC_G ICLASS: CMS Mask */
\r
10179 #define VADC_G_ICLASS_STCE_Pos 16 /*!< VADC_G ICLASS: STCE Position */
\r
10180 #define VADC_G_ICLASS_STCE_Msk (0x1fUL << VADC_G_ICLASS_STCE_Pos) /*!< VADC_G ICLASS: STCE Mask */
\r
10181 #define VADC_G_ICLASS_CME_Pos 24 /*!< VADC_G ICLASS: CME Position */
\r
10182 #define VADC_G_ICLASS_CME_Msk (0x07UL << VADC_G_ICLASS_CME_Pos) /*!< VADC_G ICLASS: CME Mask */
\r
10184 /* -------------------------------- VADC_G_ALIAS -------------------------------- */
\r
10185 #define VADC_G_ALIAS_ALIAS0_Pos 0 /*!< VADC_G ALIAS: ALIAS0 Position */
\r
10186 #define VADC_G_ALIAS_ALIAS0_Msk (0x1fUL << VADC_G_ALIAS_ALIAS0_Pos) /*!< VADC_G ALIAS: ALIAS0 Mask */
\r
10187 #define VADC_G_ALIAS_ALIAS1_Pos 8 /*!< VADC_G ALIAS: ALIAS1 Position */
\r
10188 #define VADC_G_ALIAS_ALIAS1_Msk (0x1fUL << VADC_G_ALIAS_ALIAS1_Pos) /*!< VADC_G ALIAS: ALIAS1 Mask */
\r
10190 /* -------------------------------- VADC_G_BOUND -------------------------------- */
\r
10191 #define VADC_G_BOUND_BOUNDARY0_Pos 0 /*!< VADC_G BOUND: BOUNDARY0 Position */
\r
10192 #define VADC_G_BOUND_BOUNDARY0_Msk (0x00000fffUL << VADC_G_BOUND_BOUNDARY0_Pos) /*!< VADC_G BOUND: BOUNDARY0 Mask */
\r
10193 #define VADC_G_BOUND_BOUNDARY1_Pos 16 /*!< VADC_G BOUND: BOUNDARY1 Position */
\r
10194 #define VADC_G_BOUND_BOUNDARY1_Msk (0x00000fffUL << VADC_G_BOUND_BOUNDARY1_Pos) /*!< VADC_G BOUND: BOUNDARY1 Mask */
\r
10196 /* -------------------------------- VADC_G_SYNCTR ------------------------------- */
\r
10197 #define VADC_G_SYNCTR_STSEL_Pos 0 /*!< VADC_G SYNCTR: STSEL Position */
\r
10198 #define VADC_G_SYNCTR_STSEL_Msk (0x03UL << VADC_G_SYNCTR_STSEL_Pos) /*!< VADC_G SYNCTR: STSEL Mask */
\r
10199 #define VADC_G_SYNCTR_EVALR1_Pos 4 /*!< VADC_G SYNCTR: EVALR1 Position */
\r
10200 #define VADC_G_SYNCTR_EVALR1_Msk (0x01UL << VADC_G_SYNCTR_EVALR1_Pos) /*!< VADC_G SYNCTR: EVALR1 Mask */
\r
10201 #define VADC_G_SYNCTR_EVALR2_Pos 5 /*!< VADC_G SYNCTR: EVALR2 Position */
\r
10202 #define VADC_G_SYNCTR_EVALR2_Msk (0x01UL << VADC_G_SYNCTR_EVALR2_Pos) /*!< VADC_G SYNCTR: EVALR2 Mask */
\r
10203 #define VADC_G_SYNCTR_EVALR3_Pos 6 /*!< VADC_G SYNCTR: EVALR3 Position */
\r
10204 #define VADC_G_SYNCTR_EVALR3_Msk (0x01UL << VADC_G_SYNCTR_EVALR3_Pos) /*!< VADC_G SYNCTR: EVALR3 Mask */
\r
10206 /* --------------------------------- VADC_G_BFL --------------------------------- */
\r
10207 #define VADC_G_BFL_BFL0_Pos 0 /*!< VADC_G BFL: BFL0 Position */
\r
10208 #define VADC_G_BFL_BFL0_Msk (0x01UL << VADC_G_BFL_BFL0_Pos) /*!< VADC_G BFL: BFL0 Mask */
\r
10209 #define VADC_G_BFL_BFL1_Pos 1 /*!< VADC_G BFL: BFL1 Position */
\r
10210 #define VADC_G_BFL_BFL1_Msk (0x01UL << VADC_G_BFL_BFL1_Pos) /*!< VADC_G BFL: BFL1 Mask */
\r
10211 #define VADC_G_BFL_BFL2_Pos 2 /*!< VADC_G BFL: BFL2 Position */
\r
10212 #define VADC_G_BFL_BFL2_Msk (0x01UL << VADC_G_BFL_BFL2_Pos) /*!< VADC_G BFL: BFL2 Mask */
\r
10213 #define VADC_G_BFL_BFL3_Pos 3 /*!< VADC_G BFL: BFL3 Position */
\r
10214 #define VADC_G_BFL_BFL3_Msk (0x01UL << VADC_G_BFL_BFL3_Pos) /*!< VADC_G BFL: BFL3 Mask */
\r
10215 #define VADC_G_BFL_BFE0_Pos 16 /*!< VADC_G BFL: BFE0 Position */
\r
10216 #define VADC_G_BFL_BFE0_Msk (0x01UL << VADC_G_BFL_BFE0_Pos) /*!< VADC_G BFL: BFE0 Mask */
\r
10217 #define VADC_G_BFL_BFE1_Pos 17 /*!< VADC_G BFL: BFE1 Position */
\r
10218 #define VADC_G_BFL_BFE1_Msk (0x01UL << VADC_G_BFL_BFE1_Pos) /*!< VADC_G BFL: BFE1 Mask */
\r
10219 #define VADC_G_BFL_BFE2_Pos 18 /*!< VADC_G BFL: BFE2 Position */
\r
10220 #define VADC_G_BFL_BFE2_Msk (0x01UL << VADC_G_BFL_BFE2_Pos) /*!< VADC_G BFL: BFE2 Mask */
\r
10221 #define VADC_G_BFL_BFE3_Pos 19 /*!< VADC_G BFL: BFE3 Position */
\r
10222 #define VADC_G_BFL_BFE3_Msk (0x01UL << VADC_G_BFL_BFE3_Pos) /*!< VADC_G BFL: BFE3 Mask */
\r
10224 /* -------------------------------- VADC_G_QCTRL0 ------------------------------- */
\r
10225 #define VADC_G_QCTRL0_XTSEL_Pos 8 /*!< VADC_G QCTRL0: XTSEL Position */
\r
10226 #define VADC_G_QCTRL0_XTSEL_Msk (0x0fUL << VADC_G_QCTRL0_XTSEL_Pos) /*!< VADC_G QCTRL0: XTSEL Mask */
\r
10227 #define VADC_G_QCTRL0_XTLVL_Pos 12 /*!< VADC_G QCTRL0: XTLVL Position */
\r
10228 #define VADC_G_QCTRL0_XTLVL_Msk (0x01UL << VADC_G_QCTRL0_XTLVL_Pos) /*!< VADC_G QCTRL0: XTLVL Mask */
\r
10229 #define VADC_G_QCTRL0_XTMODE_Pos 13 /*!< VADC_G QCTRL0: XTMODE Position */
\r
10230 #define VADC_G_QCTRL0_XTMODE_Msk (0x03UL << VADC_G_QCTRL0_XTMODE_Pos) /*!< VADC_G QCTRL0: XTMODE Mask */
\r
10231 #define VADC_G_QCTRL0_XTWC_Pos 15 /*!< VADC_G QCTRL0: XTWC Position */
\r
10232 #define VADC_G_QCTRL0_XTWC_Msk (0x01UL << VADC_G_QCTRL0_XTWC_Pos) /*!< VADC_G QCTRL0: XTWC Mask */
\r
10233 #define VADC_G_QCTRL0_GTSEL_Pos 16 /*!< VADC_G QCTRL0: GTSEL Position */
\r
10234 #define VADC_G_QCTRL0_GTSEL_Msk (0x0fUL << VADC_G_QCTRL0_GTSEL_Pos) /*!< VADC_G QCTRL0: GTSEL Mask */
\r
10235 #define VADC_G_QCTRL0_GTLVL_Pos 20 /*!< VADC_G QCTRL0: GTLVL Position */
\r
10236 #define VADC_G_QCTRL0_GTLVL_Msk (0x01UL << VADC_G_QCTRL0_GTLVL_Pos) /*!< VADC_G QCTRL0: GTLVL Mask */
\r
10237 #define VADC_G_QCTRL0_GTWC_Pos 23 /*!< VADC_G QCTRL0: GTWC Position */
\r
10238 #define VADC_G_QCTRL0_GTWC_Msk (0x01UL << VADC_G_QCTRL0_GTWC_Pos) /*!< VADC_G QCTRL0: GTWC Mask */
\r
10239 #define VADC_G_QCTRL0_TMEN_Pos 28 /*!< VADC_G QCTRL0: TMEN Position */
\r
10240 #define VADC_G_QCTRL0_TMEN_Msk (0x01UL << VADC_G_QCTRL0_TMEN_Pos) /*!< VADC_G QCTRL0: TMEN Mask */
\r
10241 #define VADC_G_QCTRL0_TMWC_Pos 31 /*!< VADC_G QCTRL0: TMWC Position */
\r
10242 #define VADC_G_QCTRL0_TMWC_Msk (0x01UL << VADC_G_QCTRL0_TMWC_Pos) /*!< VADC_G QCTRL0: TMWC Mask */
\r
10244 /* --------------------------------- VADC_G_QMR0 -------------------------------- */
\r
10245 #define VADC_G_QMR0_ENGT_Pos 0 /*!< VADC_G QMR0: ENGT Position */
\r
10246 #define VADC_G_QMR0_ENGT_Msk (0x03UL << VADC_G_QMR0_ENGT_Pos) /*!< VADC_G QMR0: ENGT Mask */
\r
10247 #define VADC_G_QMR0_ENTR_Pos 2 /*!< VADC_G QMR0: ENTR Position */
\r
10248 #define VADC_G_QMR0_ENTR_Msk (0x01UL << VADC_G_QMR0_ENTR_Pos) /*!< VADC_G QMR0: ENTR Mask */
\r
10249 #define VADC_G_QMR0_CLRV_Pos 8 /*!< VADC_G QMR0: CLRV Position */
\r
10250 #define VADC_G_QMR0_CLRV_Msk (0x01UL << VADC_G_QMR0_CLRV_Pos) /*!< VADC_G QMR0: CLRV Mask */
\r
10251 #define VADC_G_QMR0_TREV_Pos 9 /*!< VADC_G QMR0: TREV Position */
\r
10252 #define VADC_G_QMR0_TREV_Msk (0x01UL << VADC_G_QMR0_TREV_Pos) /*!< VADC_G QMR0: TREV Mask */
\r
10253 #define VADC_G_QMR0_FLUSH_Pos 10 /*!< VADC_G QMR0: FLUSH Position */
\r
10254 #define VADC_G_QMR0_FLUSH_Msk (0x01UL << VADC_G_QMR0_FLUSH_Pos) /*!< VADC_G QMR0: FLUSH Mask */
\r
10255 #define VADC_G_QMR0_CEV_Pos 11 /*!< VADC_G QMR0: CEV Position */
\r
10256 #define VADC_G_QMR0_CEV_Msk (0x01UL << VADC_G_QMR0_CEV_Pos) /*!< VADC_G QMR0: CEV Mask */
\r
10257 #define VADC_G_QMR0_RPTDIS_Pos 16 /*!< VADC_G QMR0: RPTDIS Position */
\r
10258 #define VADC_G_QMR0_RPTDIS_Msk (0x01UL << VADC_G_QMR0_RPTDIS_Pos) /*!< VADC_G QMR0: RPTDIS Mask */
\r
10260 /* --------------------------------- VADC_G_QSR0 -------------------------------- */
\r
10261 #define VADC_G_QSR0_FILL_Pos 0 /*!< VADC_G QSR0: FILL Position */
\r
10262 #define VADC_G_QSR0_FILL_Msk (0x0fUL << VADC_G_QSR0_FILL_Pos) /*!< VADC_G QSR0: FILL Mask */
\r
10263 #define VADC_G_QSR0_EMPTY_Pos 5 /*!< VADC_G QSR0: EMPTY Position */
\r
10264 #define VADC_G_QSR0_EMPTY_Msk (0x01UL << VADC_G_QSR0_EMPTY_Pos) /*!< VADC_G QSR0: EMPTY Mask */
\r
10265 #define VADC_G_QSR0_REQGT_Pos 7 /*!< VADC_G QSR0: REQGT Position */
\r
10266 #define VADC_G_QSR0_REQGT_Msk (0x01UL << VADC_G_QSR0_REQGT_Pos) /*!< VADC_G QSR0: REQGT Mask */
\r
10267 #define VADC_G_QSR0_EV_Pos 8 /*!< VADC_G QSR0: EV Position */
\r
10268 #define VADC_G_QSR0_EV_Msk (0x01UL << VADC_G_QSR0_EV_Pos) /*!< VADC_G QSR0: EV Mask */
\r
10270 /* --------------------------------- VADC_G_Q0R0 -------------------------------- */
\r
10271 #define VADC_G_Q0R0_REQCHNR_Pos 0 /*!< VADC_G Q0R0: REQCHNR Position */
\r
10272 #define VADC_G_Q0R0_REQCHNR_Msk (0x1fUL << VADC_G_Q0R0_REQCHNR_Pos) /*!< VADC_G Q0R0: REQCHNR Mask */
\r
10273 #define VADC_G_Q0R0_RF_Pos 5 /*!< VADC_G Q0R0: RF Position */
\r
10274 #define VADC_G_Q0R0_RF_Msk (0x01UL << VADC_G_Q0R0_RF_Pos) /*!< VADC_G Q0R0: RF Mask */
\r
10275 #define VADC_G_Q0R0_ENSI_Pos 6 /*!< VADC_G Q0R0: ENSI Position */
\r
10276 #define VADC_G_Q0R0_ENSI_Msk (0x01UL << VADC_G_Q0R0_ENSI_Pos) /*!< VADC_G Q0R0: ENSI Mask */
\r
10277 #define VADC_G_Q0R0_EXTR_Pos 7 /*!< VADC_G Q0R0: EXTR Position */
\r
10278 #define VADC_G_Q0R0_EXTR_Msk (0x01UL << VADC_G_Q0R0_EXTR_Pos) /*!< VADC_G Q0R0: EXTR Mask */
\r
10279 #define VADC_G_Q0R0_V_Pos 8 /*!< VADC_G Q0R0: V Position */
\r
10280 #define VADC_G_Q0R0_V_Msk (0x01UL << VADC_G_Q0R0_V_Pos) /*!< VADC_G Q0R0: V Mask */
\r
10282 /* -------------------------------- VADC_G_QINR0 -------------------------------- */
\r
10283 #define VADC_G_QINR0_REQCHNR_Pos 0 /*!< VADC_G QINR0: REQCHNR Position */
\r
10284 #define VADC_G_QINR0_REQCHNR_Msk (0x1fUL << VADC_G_QINR0_REQCHNR_Pos) /*!< VADC_G QINR0: REQCHNR Mask */
\r
10285 #define VADC_G_QINR0_RF_Pos 5 /*!< VADC_G QINR0: RF Position */
\r
10286 #define VADC_G_QINR0_RF_Msk (0x01UL << VADC_G_QINR0_RF_Pos) /*!< VADC_G QINR0: RF Mask */
\r
10287 #define VADC_G_QINR0_ENSI_Pos 6 /*!< VADC_G QINR0: ENSI Position */
\r
10288 #define VADC_G_QINR0_ENSI_Msk (0x01UL << VADC_G_QINR0_ENSI_Pos) /*!< VADC_G QINR0: ENSI Mask */
\r
10289 #define VADC_G_QINR0_EXTR_Pos 7 /*!< VADC_G QINR0: EXTR Position */
\r
10290 #define VADC_G_QINR0_EXTR_Msk (0x01UL << VADC_G_QINR0_EXTR_Pos) /*!< VADC_G QINR0: EXTR Mask */
\r
10292 /* -------------------------------- VADC_G_QBUR0 -------------------------------- */
\r
10293 #define VADC_G_QBUR0_REQCHNR_Pos 0 /*!< VADC_G QBUR0: REQCHNR Position */
\r
10294 #define VADC_G_QBUR0_REQCHNR_Msk (0x1fUL << VADC_G_QBUR0_REQCHNR_Pos) /*!< VADC_G QBUR0: REQCHNR Mask */
\r
10295 #define VADC_G_QBUR0_RF_Pos 5 /*!< VADC_G QBUR0: RF Position */
\r
10296 #define VADC_G_QBUR0_RF_Msk (0x01UL << VADC_G_QBUR0_RF_Pos) /*!< VADC_G QBUR0: RF Mask */
\r
10297 #define VADC_G_QBUR0_ENSI_Pos 6 /*!< VADC_G QBUR0: ENSI Position */
\r
10298 #define VADC_G_QBUR0_ENSI_Msk (0x01UL << VADC_G_QBUR0_ENSI_Pos) /*!< VADC_G QBUR0: ENSI Mask */
\r
10299 #define VADC_G_QBUR0_EXTR_Pos 7 /*!< VADC_G QBUR0: EXTR Position */
\r
10300 #define VADC_G_QBUR0_EXTR_Msk (0x01UL << VADC_G_QBUR0_EXTR_Pos) /*!< VADC_G QBUR0: EXTR Mask */
\r
10301 #define VADC_G_QBUR0_V_Pos 8 /*!< VADC_G QBUR0: V Position */
\r
10302 #define VADC_G_QBUR0_V_Msk (0x01UL << VADC_G_QBUR0_V_Pos) /*!< VADC_G QBUR0: V Mask */
\r
10304 /* -------------------------------- VADC_G_ASCTRL ------------------------------- */
\r
10305 #define VADC_G_ASCTRL_XTSEL_Pos 8 /*!< VADC_G ASCTRL: XTSEL Position */
\r
10306 #define VADC_G_ASCTRL_XTSEL_Msk (0x0fUL << VADC_G_ASCTRL_XTSEL_Pos) /*!< VADC_G ASCTRL: XTSEL Mask */
\r
10307 #define VADC_G_ASCTRL_XTLVL_Pos 12 /*!< VADC_G ASCTRL: XTLVL Position */
\r
10308 #define VADC_G_ASCTRL_XTLVL_Msk (0x01UL << VADC_G_ASCTRL_XTLVL_Pos) /*!< VADC_G ASCTRL: XTLVL Mask */
\r
10309 #define VADC_G_ASCTRL_XTMODE_Pos 13 /*!< VADC_G ASCTRL: XTMODE Position */
\r
10310 #define VADC_G_ASCTRL_XTMODE_Msk (0x03UL << VADC_G_ASCTRL_XTMODE_Pos) /*!< VADC_G ASCTRL: XTMODE Mask */
\r
10311 #define VADC_G_ASCTRL_XTWC_Pos 15 /*!< VADC_G ASCTRL: XTWC Position */
\r
10312 #define VADC_G_ASCTRL_XTWC_Msk (0x01UL << VADC_G_ASCTRL_XTWC_Pos) /*!< VADC_G ASCTRL: XTWC Mask */
\r
10313 #define VADC_G_ASCTRL_GTSEL_Pos 16 /*!< VADC_G ASCTRL: GTSEL Position */
\r
10314 #define VADC_G_ASCTRL_GTSEL_Msk (0x0fUL << VADC_G_ASCTRL_GTSEL_Pos) /*!< VADC_G ASCTRL: GTSEL Mask */
\r
10315 #define VADC_G_ASCTRL_GTLVL_Pos 20 /*!< VADC_G ASCTRL: GTLVL Position */
\r
10316 #define VADC_G_ASCTRL_GTLVL_Msk (0x01UL << VADC_G_ASCTRL_GTLVL_Pos) /*!< VADC_G ASCTRL: GTLVL Mask */
\r
10317 #define VADC_G_ASCTRL_GTWC_Pos 23 /*!< VADC_G ASCTRL: GTWC Position */
\r
10318 #define VADC_G_ASCTRL_GTWC_Msk (0x01UL << VADC_G_ASCTRL_GTWC_Pos) /*!< VADC_G ASCTRL: GTWC Mask */
\r
10319 #define VADC_G_ASCTRL_TMEN_Pos 28 /*!< VADC_G ASCTRL: TMEN Position */
\r
10320 #define VADC_G_ASCTRL_TMEN_Msk (0x01UL << VADC_G_ASCTRL_TMEN_Pos) /*!< VADC_G ASCTRL: TMEN Mask */
\r
10321 #define VADC_G_ASCTRL_TMWC_Pos 31 /*!< VADC_G ASCTRL: TMWC Position */
\r
10322 #define VADC_G_ASCTRL_TMWC_Msk (0x01UL << VADC_G_ASCTRL_TMWC_Pos) /*!< VADC_G ASCTRL: TMWC Mask */
\r
10324 /* --------------------------------- VADC_G_ASMR -------------------------------- */
\r
10325 #define VADC_G_ASMR_ENGT_Pos 0 /*!< VADC_G ASMR: ENGT Position */
\r
10326 #define VADC_G_ASMR_ENGT_Msk (0x03UL << VADC_G_ASMR_ENGT_Pos) /*!< VADC_G ASMR: ENGT Mask */
\r
10327 #define VADC_G_ASMR_ENTR_Pos 2 /*!< VADC_G ASMR: ENTR Position */
\r
10328 #define VADC_G_ASMR_ENTR_Msk (0x01UL << VADC_G_ASMR_ENTR_Pos) /*!< VADC_G ASMR: ENTR Mask */
\r
10329 #define VADC_G_ASMR_ENSI_Pos 3 /*!< VADC_G ASMR: ENSI Position */
\r
10330 #define VADC_G_ASMR_ENSI_Msk (0x01UL << VADC_G_ASMR_ENSI_Pos) /*!< VADC_G ASMR: ENSI Mask */
\r
10331 #define VADC_G_ASMR_SCAN_Pos 4 /*!< VADC_G ASMR: SCAN Position */
\r
10332 #define VADC_G_ASMR_SCAN_Msk (0x01UL << VADC_G_ASMR_SCAN_Pos) /*!< VADC_G ASMR: SCAN Mask */
\r
10333 #define VADC_G_ASMR_LDM_Pos 5 /*!< VADC_G ASMR: LDM Position */
\r
10334 #define VADC_G_ASMR_LDM_Msk (0x01UL << VADC_G_ASMR_LDM_Pos) /*!< VADC_G ASMR: LDM Mask */
\r
10335 #define VADC_G_ASMR_REQGT_Pos 7 /*!< VADC_G ASMR: REQGT Position */
\r
10336 #define VADC_G_ASMR_REQGT_Msk (0x01UL << VADC_G_ASMR_REQGT_Pos) /*!< VADC_G ASMR: REQGT Mask */
\r
10337 #define VADC_G_ASMR_CLRPND_Pos 8 /*!< VADC_G ASMR: CLRPND Position */
\r
10338 #define VADC_G_ASMR_CLRPND_Msk (0x01UL << VADC_G_ASMR_CLRPND_Pos) /*!< VADC_G ASMR: CLRPND Mask */
\r
10339 #define VADC_G_ASMR_LDEV_Pos 9 /*!< VADC_G ASMR: LDEV Position */
\r
10340 #define VADC_G_ASMR_LDEV_Msk (0x01UL << VADC_G_ASMR_LDEV_Pos) /*!< VADC_G ASMR: LDEV Mask */
\r
10341 #define VADC_G_ASMR_RPTDIS_Pos 16 /*!< VADC_G ASMR: RPTDIS Position */
\r
10342 #define VADC_G_ASMR_RPTDIS_Msk (0x01UL << VADC_G_ASMR_RPTDIS_Pos) /*!< VADC_G ASMR: RPTDIS Mask */
\r
10344 /* -------------------------------- VADC_G_ASSEL -------------------------------- */
\r
10345 #define VADC_G_ASSEL_CHSEL0_Pos 0 /*!< VADC_G ASSEL: CHSEL0 Position */
\r
10346 #define VADC_G_ASSEL_CHSEL0_Msk (0x01UL << VADC_G_ASSEL_CHSEL0_Pos) /*!< VADC_G ASSEL: CHSEL0 Mask */
\r
10347 #define VADC_G_ASSEL_CHSEL1_Pos 1 /*!< VADC_G ASSEL: CHSEL1 Position */
\r
10348 #define VADC_G_ASSEL_CHSEL1_Msk (0x01UL << VADC_G_ASSEL_CHSEL1_Pos) /*!< VADC_G ASSEL: CHSEL1 Mask */
\r
10349 #define VADC_G_ASSEL_CHSEL2_Pos 2 /*!< VADC_G ASSEL: CHSEL2 Position */
\r
10350 #define VADC_G_ASSEL_CHSEL2_Msk (0x01UL << VADC_G_ASSEL_CHSEL2_Pos) /*!< VADC_G ASSEL: CHSEL2 Mask */
\r
10351 #define VADC_G_ASSEL_CHSEL3_Pos 3 /*!< VADC_G ASSEL: CHSEL3 Position */
\r
10352 #define VADC_G_ASSEL_CHSEL3_Msk (0x01UL << VADC_G_ASSEL_CHSEL3_Pos) /*!< VADC_G ASSEL: CHSEL3 Mask */
\r
10353 #define VADC_G_ASSEL_CHSEL4_Pos 4 /*!< VADC_G ASSEL: CHSEL4 Position */
\r
10354 #define VADC_G_ASSEL_CHSEL4_Msk (0x01UL << VADC_G_ASSEL_CHSEL4_Pos) /*!< VADC_G ASSEL: CHSEL4 Mask */
\r
10355 #define VADC_G_ASSEL_CHSEL5_Pos 5 /*!< VADC_G ASSEL: CHSEL5 Position */
\r
10356 #define VADC_G_ASSEL_CHSEL5_Msk (0x01UL << VADC_G_ASSEL_CHSEL5_Pos) /*!< VADC_G ASSEL: CHSEL5 Mask */
\r
10357 #define VADC_G_ASSEL_CHSEL6_Pos 6 /*!< VADC_G ASSEL: CHSEL6 Position */
\r
10358 #define VADC_G_ASSEL_CHSEL6_Msk (0x01UL << VADC_G_ASSEL_CHSEL6_Pos) /*!< VADC_G ASSEL: CHSEL6 Mask */
\r
10359 #define VADC_G_ASSEL_CHSEL7_Pos 7 /*!< VADC_G ASSEL: CHSEL7 Position */
\r
10360 #define VADC_G_ASSEL_CHSEL7_Msk (0x01UL << VADC_G_ASSEL_CHSEL7_Pos) /*!< VADC_G ASSEL: CHSEL7 Mask */
\r
10362 /* -------------------------------- VADC_G_ASPND -------------------------------- */
\r
10363 #define VADC_G_ASPND_CHPND0_Pos 0 /*!< VADC_G ASPND: CHPND0 Position */
\r
10364 #define VADC_G_ASPND_CHPND0_Msk (0x01UL << VADC_G_ASPND_CHPND0_Pos) /*!< VADC_G ASPND: CHPND0 Mask */
\r
10365 #define VADC_G_ASPND_CHPND1_Pos 1 /*!< VADC_G ASPND: CHPND1 Position */
\r
10366 #define VADC_G_ASPND_CHPND1_Msk (0x01UL << VADC_G_ASPND_CHPND1_Pos) /*!< VADC_G ASPND: CHPND1 Mask */
\r
10367 #define VADC_G_ASPND_CHPND2_Pos 2 /*!< VADC_G ASPND: CHPND2 Position */
\r
10368 #define VADC_G_ASPND_CHPND2_Msk (0x01UL << VADC_G_ASPND_CHPND2_Pos) /*!< VADC_G ASPND: CHPND2 Mask */
\r
10369 #define VADC_G_ASPND_CHPND3_Pos 3 /*!< VADC_G ASPND: CHPND3 Position */
\r
10370 #define VADC_G_ASPND_CHPND3_Msk (0x01UL << VADC_G_ASPND_CHPND3_Pos) /*!< VADC_G ASPND: CHPND3 Mask */
\r
10371 #define VADC_G_ASPND_CHPND4_Pos 4 /*!< VADC_G ASPND: CHPND4 Position */
\r
10372 #define VADC_G_ASPND_CHPND4_Msk (0x01UL << VADC_G_ASPND_CHPND4_Pos) /*!< VADC_G ASPND: CHPND4 Mask */
\r
10373 #define VADC_G_ASPND_CHPND5_Pos 5 /*!< VADC_G ASPND: CHPND5 Position */
\r
10374 #define VADC_G_ASPND_CHPND5_Msk (0x01UL << VADC_G_ASPND_CHPND5_Pos) /*!< VADC_G ASPND: CHPND5 Mask */
\r
10375 #define VADC_G_ASPND_CHPND6_Pos 6 /*!< VADC_G ASPND: CHPND6 Position */
\r
10376 #define VADC_G_ASPND_CHPND6_Msk (0x01UL << VADC_G_ASPND_CHPND6_Pos) /*!< VADC_G ASPND: CHPND6 Mask */
\r
10377 #define VADC_G_ASPND_CHPND7_Pos 7 /*!< VADC_G ASPND: CHPND7 Position */
\r
10378 #define VADC_G_ASPND_CHPND7_Msk (0x01UL << VADC_G_ASPND_CHPND7_Pos) /*!< VADC_G ASPND: CHPND7 Mask */
\r
10380 /* -------------------------------- VADC_G_CEFLAG ------------------------------- */
\r
10381 #define VADC_G_CEFLAG_CEV0_Pos 0 /*!< VADC_G CEFLAG: CEV0 Position */
\r
10382 #define VADC_G_CEFLAG_CEV0_Msk (0x01UL << VADC_G_CEFLAG_CEV0_Pos) /*!< VADC_G CEFLAG: CEV0 Mask */
\r
10383 #define VADC_G_CEFLAG_CEV1_Pos 1 /*!< VADC_G CEFLAG: CEV1 Position */
\r
10384 #define VADC_G_CEFLAG_CEV1_Msk (0x01UL << VADC_G_CEFLAG_CEV1_Pos) /*!< VADC_G CEFLAG: CEV1 Mask */
\r
10385 #define VADC_G_CEFLAG_CEV2_Pos 2 /*!< VADC_G CEFLAG: CEV2 Position */
\r
10386 #define VADC_G_CEFLAG_CEV2_Msk (0x01UL << VADC_G_CEFLAG_CEV2_Pos) /*!< VADC_G CEFLAG: CEV2 Mask */
\r
10387 #define VADC_G_CEFLAG_CEV3_Pos 3 /*!< VADC_G CEFLAG: CEV3 Position */
\r
10388 #define VADC_G_CEFLAG_CEV3_Msk (0x01UL << VADC_G_CEFLAG_CEV3_Pos) /*!< VADC_G CEFLAG: CEV3 Mask */
\r
10389 #define VADC_G_CEFLAG_CEV4_Pos 4 /*!< VADC_G CEFLAG: CEV4 Position */
\r
10390 #define VADC_G_CEFLAG_CEV4_Msk (0x01UL << VADC_G_CEFLAG_CEV4_Pos) /*!< VADC_G CEFLAG: CEV4 Mask */
\r
10391 #define VADC_G_CEFLAG_CEV5_Pos 5 /*!< VADC_G CEFLAG: CEV5 Position */
\r
10392 #define VADC_G_CEFLAG_CEV5_Msk (0x01UL << VADC_G_CEFLAG_CEV5_Pos) /*!< VADC_G CEFLAG: CEV5 Mask */
\r
10393 #define VADC_G_CEFLAG_CEV6_Pos 6 /*!< VADC_G CEFLAG: CEV6 Position */
\r
10394 #define VADC_G_CEFLAG_CEV6_Msk (0x01UL << VADC_G_CEFLAG_CEV6_Pos) /*!< VADC_G CEFLAG: CEV6 Mask */
\r
10395 #define VADC_G_CEFLAG_CEV7_Pos 7 /*!< VADC_G CEFLAG: CEV7 Position */
\r
10396 #define VADC_G_CEFLAG_CEV7_Msk (0x01UL << VADC_G_CEFLAG_CEV7_Pos) /*!< VADC_G CEFLAG: CEV7 Mask */
\r
10398 /* -------------------------------- VADC_G_REFLAG ------------------------------- */
\r
10399 #define VADC_G_REFLAG_REV0_Pos 0 /*!< VADC_G REFLAG: REV0 Position */
\r
10400 #define VADC_G_REFLAG_REV0_Msk (0x01UL << VADC_G_REFLAG_REV0_Pos) /*!< VADC_G REFLAG: REV0 Mask */
\r
10401 #define VADC_G_REFLAG_REV1_Pos 1 /*!< VADC_G REFLAG: REV1 Position */
\r
10402 #define VADC_G_REFLAG_REV1_Msk (0x01UL << VADC_G_REFLAG_REV1_Pos) /*!< VADC_G REFLAG: REV1 Mask */
\r
10403 #define VADC_G_REFLAG_REV2_Pos 2 /*!< VADC_G REFLAG: REV2 Position */
\r
10404 #define VADC_G_REFLAG_REV2_Msk (0x01UL << VADC_G_REFLAG_REV2_Pos) /*!< VADC_G REFLAG: REV2 Mask */
\r
10405 #define VADC_G_REFLAG_REV3_Pos 3 /*!< VADC_G REFLAG: REV3 Position */
\r
10406 #define VADC_G_REFLAG_REV3_Msk (0x01UL << VADC_G_REFLAG_REV3_Pos) /*!< VADC_G REFLAG: REV3 Mask */
\r
10407 #define VADC_G_REFLAG_REV4_Pos 4 /*!< VADC_G REFLAG: REV4 Position */
\r
10408 #define VADC_G_REFLAG_REV4_Msk (0x01UL << VADC_G_REFLAG_REV4_Pos) /*!< VADC_G REFLAG: REV4 Mask */
\r
10409 #define VADC_G_REFLAG_REV5_Pos 5 /*!< VADC_G REFLAG: REV5 Position */
\r
10410 #define VADC_G_REFLAG_REV5_Msk (0x01UL << VADC_G_REFLAG_REV5_Pos) /*!< VADC_G REFLAG: REV5 Mask */
\r
10411 #define VADC_G_REFLAG_REV6_Pos 6 /*!< VADC_G REFLAG: REV6 Position */
\r
10412 #define VADC_G_REFLAG_REV6_Msk (0x01UL << VADC_G_REFLAG_REV6_Pos) /*!< VADC_G REFLAG: REV6 Mask */
\r
10413 #define VADC_G_REFLAG_REV7_Pos 7 /*!< VADC_G REFLAG: REV7 Position */
\r
10414 #define VADC_G_REFLAG_REV7_Msk (0x01UL << VADC_G_REFLAG_REV7_Pos) /*!< VADC_G REFLAG: REV7 Mask */
\r
10415 #define VADC_G_REFLAG_REV8_Pos 8 /*!< VADC_G REFLAG: REV8 Position */
\r
10416 #define VADC_G_REFLAG_REV8_Msk (0x01UL << VADC_G_REFLAG_REV8_Pos) /*!< VADC_G REFLAG: REV8 Mask */
\r
10417 #define VADC_G_REFLAG_REV9_Pos 9 /*!< VADC_G REFLAG: REV9 Position */
\r
10418 #define VADC_G_REFLAG_REV9_Msk (0x01UL << VADC_G_REFLAG_REV9_Pos) /*!< VADC_G REFLAG: REV9 Mask */
\r
10419 #define VADC_G_REFLAG_REV10_Pos 10 /*!< VADC_G REFLAG: REV10 Position */
\r
10420 #define VADC_G_REFLAG_REV10_Msk (0x01UL << VADC_G_REFLAG_REV10_Pos) /*!< VADC_G REFLAG: REV10 Mask */
\r
10421 #define VADC_G_REFLAG_REV11_Pos 11 /*!< VADC_G REFLAG: REV11 Position */
\r
10422 #define VADC_G_REFLAG_REV11_Msk (0x01UL << VADC_G_REFLAG_REV11_Pos) /*!< VADC_G REFLAG: REV11 Mask */
\r
10423 #define VADC_G_REFLAG_REV12_Pos 12 /*!< VADC_G REFLAG: REV12 Position */
\r
10424 #define VADC_G_REFLAG_REV12_Msk (0x01UL << VADC_G_REFLAG_REV12_Pos) /*!< VADC_G REFLAG: REV12 Mask */
\r
10425 #define VADC_G_REFLAG_REV13_Pos 13 /*!< VADC_G REFLAG: REV13 Position */
\r
10426 #define VADC_G_REFLAG_REV13_Msk (0x01UL << VADC_G_REFLAG_REV13_Pos) /*!< VADC_G REFLAG: REV13 Mask */
\r
10427 #define VADC_G_REFLAG_REV14_Pos 14 /*!< VADC_G REFLAG: REV14 Position */
\r
10428 #define VADC_G_REFLAG_REV14_Msk (0x01UL << VADC_G_REFLAG_REV14_Pos) /*!< VADC_G REFLAG: REV14 Mask */
\r
10429 #define VADC_G_REFLAG_REV15_Pos 15 /*!< VADC_G REFLAG: REV15 Position */
\r
10430 #define VADC_G_REFLAG_REV15_Msk (0x01UL << VADC_G_REFLAG_REV15_Pos) /*!< VADC_G REFLAG: REV15 Mask */
\r
10432 /* -------------------------------- VADC_G_SEFLAG ------------------------------- */
\r
10433 #define VADC_G_SEFLAG_SEV0_Pos 0 /*!< VADC_G SEFLAG: SEV0 Position */
\r
10434 #define VADC_G_SEFLAG_SEV0_Msk (0x01UL << VADC_G_SEFLAG_SEV0_Pos) /*!< VADC_G SEFLAG: SEV0 Mask */
\r
10435 #define VADC_G_SEFLAG_SEV1_Pos 1 /*!< VADC_G SEFLAG: SEV1 Position */
\r
10436 #define VADC_G_SEFLAG_SEV1_Msk (0x01UL << VADC_G_SEFLAG_SEV1_Pos) /*!< VADC_G SEFLAG: SEV1 Mask */
\r
10438 /* -------------------------------- VADC_G_CEFCLR ------------------------------- */
\r
10439 #define VADC_G_CEFCLR_CEV0_Pos 0 /*!< VADC_G CEFCLR: CEV0 Position */
\r
10440 #define VADC_G_CEFCLR_CEV0_Msk (0x01UL << VADC_G_CEFCLR_CEV0_Pos) /*!< VADC_G CEFCLR: CEV0 Mask */
\r
10441 #define VADC_G_CEFCLR_CEV1_Pos 1 /*!< VADC_G CEFCLR: CEV1 Position */
\r
10442 #define VADC_G_CEFCLR_CEV1_Msk (0x01UL << VADC_G_CEFCLR_CEV1_Pos) /*!< VADC_G CEFCLR: CEV1 Mask */
\r
10443 #define VADC_G_CEFCLR_CEV2_Pos 2 /*!< VADC_G CEFCLR: CEV2 Position */
\r
10444 #define VADC_G_CEFCLR_CEV2_Msk (0x01UL << VADC_G_CEFCLR_CEV2_Pos) /*!< VADC_G CEFCLR: CEV2 Mask */
\r
10445 #define VADC_G_CEFCLR_CEV3_Pos 3 /*!< VADC_G CEFCLR: CEV3 Position */
\r
10446 #define VADC_G_CEFCLR_CEV3_Msk (0x01UL << VADC_G_CEFCLR_CEV3_Pos) /*!< VADC_G CEFCLR: CEV3 Mask */
\r
10447 #define VADC_G_CEFCLR_CEV4_Pos 4 /*!< VADC_G CEFCLR: CEV4 Position */
\r
10448 #define VADC_G_CEFCLR_CEV4_Msk (0x01UL << VADC_G_CEFCLR_CEV4_Pos) /*!< VADC_G CEFCLR: CEV4 Mask */
\r
10449 #define VADC_G_CEFCLR_CEV5_Pos 5 /*!< VADC_G CEFCLR: CEV5 Position */
\r
10450 #define VADC_G_CEFCLR_CEV5_Msk (0x01UL << VADC_G_CEFCLR_CEV5_Pos) /*!< VADC_G CEFCLR: CEV5 Mask */
\r
10451 #define VADC_G_CEFCLR_CEV6_Pos 6 /*!< VADC_G CEFCLR: CEV6 Position */
\r
10452 #define VADC_G_CEFCLR_CEV6_Msk (0x01UL << VADC_G_CEFCLR_CEV6_Pos) /*!< VADC_G CEFCLR: CEV6 Mask */
\r
10453 #define VADC_G_CEFCLR_CEV7_Pos 7 /*!< VADC_G CEFCLR: CEV7 Position */
\r
10454 #define VADC_G_CEFCLR_CEV7_Msk (0x01UL << VADC_G_CEFCLR_CEV7_Pos) /*!< VADC_G CEFCLR: CEV7 Mask */
\r
10456 /* -------------------------------- VADC_G_REFCLR ------------------------------- */
\r
10457 #define VADC_G_REFCLR_REV0_Pos 0 /*!< VADC_G REFCLR: REV0 Position */
\r
10458 #define VADC_G_REFCLR_REV0_Msk (0x01UL << VADC_G_REFCLR_REV0_Pos) /*!< VADC_G REFCLR: REV0 Mask */
\r
10459 #define VADC_G_REFCLR_REV1_Pos 1 /*!< VADC_G REFCLR: REV1 Position */
\r
10460 #define VADC_G_REFCLR_REV1_Msk (0x01UL << VADC_G_REFCLR_REV1_Pos) /*!< VADC_G REFCLR: REV1 Mask */
\r
10461 #define VADC_G_REFCLR_REV2_Pos 2 /*!< VADC_G REFCLR: REV2 Position */
\r
10462 #define VADC_G_REFCLR_REV2_Msk (0x01UL << VADC_G_REFCLR_REV2_Pos) /*!< VADC_G REFCLR: REV2 Mask */
\r
10463 #define VADC_G_REFCLR_REV3_Pos 3 /*!< VADC_G REFCLR: REV3 Position */
\r
10464 #define VADC_G_REFCLR_REV3_Msk (0x01UL << VADC_G_REFCLR_REV3_Pos) /*!< VADC_G REFCLR: REV3 Mask */
\r
10465 #define VADC_G_REFCLR_REV4_Pos 4 /*!< VADC_G REFCLR: REV4 Position */
\r
10466 #define VADC_G_REFCLR_REV4_Msk (0x01UL << VADC_G_REFCLR_REV4_Pos) /*!< VADC_G REFCLR: REV4 Mask */
\r
10467 #define VADC_G_REFCLR_REV5_Pos 5 /*!< VADC_G REFCLR: REV5 Position */
\r
10468 #define VADC_G_REFCLR_REV5_Msk (0x01UL << VADC_G_REFCLR_REV5_Pos) /*!< VADC_G REFCLR: REV5 Mask */
\r
10469 #define VADC_G_REFCLR_REV6_Pos 6 /*!< VADC_G REFCLR: REV6 Position */
\r
10470 #define VADC_G_REFCLR_REV6_Msk (0x01UL << VADC_G_REFCLR_REV6_Pos) /*!< VADC_G REFCLR: REV6 Mask */
\r
10471 #define VADC_G_REFCLR_REV7_Pos 7 /*!< VADC_G REFCLR: REV7 Position */
\r
10472 #define VADC_G_REFCLR_REV7_Msk (0x01UL << VADC_G_REFCLR_REV7_Pos) /*!< VADC_G REFCLR: REV7 Mask */
\r
10473 #define VADC_G_REFCLR_REV8_Pos 8 /*!< VADC_G REFCLR: REV8 Position */
\r
10474 #define VADC_G_REFCLR_REV8_Msk (0x01UL << VADC_G_REFCLR_REV8_Pos) /*!< VADC_G REFCLR: REV8 Mask */
\r
10475 #define VADC_G_REFCLR_REV9_Pos 9 /*!< VADC_G REFCLR: REV9 Position */
\r
10476 #define VADC_G_REFCLR_REV9_Msk (0x01UL << VADC_G_REFCLR_REV9_Pos) /*!< VADC_G REFCLR: REV9 Mask */
\r
10477 #define VADC_G_REFCLR_REV10_Pos 10 /*!< VADC_G REFCLR: REV10 Position */
\r
10478 #define VADC_G_REFCLR_REV10_Msk (0x01UL << VADC_G_REFCLR_REV10_Pos) /*!< VADC_G REFCLR: REV10 Mask */
\r
10479 #define VADC_G_REFCLR_REV11_Pos 11 /*!< VADC_G REFCLR: REV11 Position */
\r
10480 #define VADC_G_REFCLR_REV11_Msk (0x01UL << VADC_G_REFCLR_REV11_Pos) /*!< VADC_G REFCLR: REV11 Mask */
\r
10481 #define VADC_G_REFCLR_REV12_Pos 12 /*!< VADC_G REFCLR: REV12 Position */
\r
10482 #define VADC_G_REFCLR_REV12_Msk (0x01UL << VADC_G_REFCLR_REV12_Pos) /*!< VADC_G REFCLR: REV12 Mask */
\r
10483 #define VADC_G_REFCLR_REV13_Pos 13 /*!< VADC_G REFCLR: REV13 Position */
\r
10484 #define VADC_G_REFCLR_REV13_Msk (0x01UL << VADC_G_REFCLR_REV13_Pos) /*!< VADC_G REFCLR: REV13 Mask */
\r
10485 #define VADC_G_REFCLR_REV14_Pos 14 /*!< VADC_G REFCLR: REV14 Position */
\r
10486 #define VADC_G_REFCLR_REV14_Msk (0x01UL << VADC_G_REFCLR_REV14_Pos) /*!< VADC_G REFCLR: REV14 Mask */
\r
10487 #define VADC_G_REFCLR_REV15_Pos 15 /*!< VADC_G REFCLR: REV15 Position */
\r
10488 #define VADC_G_REFCLR_REV15_Msk (0x01UL << VADC_G_REFCLR_REV15_Pos) /*!< VADC_G REFCLR: REV15 Mask */
\r
10490 /* -------------------------------- VADC_G_SEFCLR ------------------------------- */
\r
10491 #define VADC_G_SEFCLR_SEV0_Pos 0 /*!< VADC_G SEFCLR: SEV0 Position */
\r
10492 #define VADC_G_SEFCLR_SEV0_Msk (0x01UL << VADC_G_SEFCLR_SEV0_Pos) /*!< VADC_G SEFCLR: SEV0 Mask */
\r
10493 #define VADC_G_SEFCLR_SEV1_Pos 1 /*!< VADC_G SEFCLR: SEV1 Position */
\r
10494 #define VADC_G_SEFCLR_SEV1_Msk (0x01UL << VADC_G_SEFCLR_SEV1_Pos) /*!< VADC_G SEFCLR: SEV1 Mask */
\r
10496 /* -------------------------------- VADC_G_CEVNP0 ------------------------------- */
\r
10497 #define VADC_G_CEVNP0_CEV0NP_Pos 0 /*!< VADC_G CEVNP0: CEV0NP Position */
\r
10498 #define VADC_G_CEVNP0_CEV0NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV0NP_Pos) /*!< VADC_G CEVNP0: CEV0NP Mask */
\r
10499 #define VADC_G_CEVNP0_CEV1NP_Pos 4 /*!< VADC_G CEVNP0: CEV1NP Position */
\r
10500 #define VADC_G_CEVNP0_CEV1NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV1NP_Pos) /*!< VADC_G CEVNP0: CEV1NP Mask */
\r
10501 #define VADC_G_CEVNP0_CEV2NP_Pos 8 /*!< VADC_G CEVNP0: CEV2NP Position */
\r
10502 #define VADC_G_CEVNP0_CEV2NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV2NP_Pos) /*!< VADC_G CEVNP0: CEV2NP Mask */
\r
10503 #define VADC_G_CEVNP0_CEV3NP_Pos 12 /*!< VADC_G CEVNP0: CEV3NP Position */
\r
10504 #define VADC_G_CEVNP0_CEV3NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV3NP_Pos) /*!< VADC_G CEVNP0: CEV3NP Mask */
\r
10505 #define VADC_G_CEVNP0_CEV4NP_Pos 16 /*!< VADC_G CEVNP0: CEV4NP Position */
\r
10506 #define VADC_G_CEVNP0_CEV4NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV4NP_Pos) /*!< VADC_G CEVNP0: CEV4NP Mask */
\r
10507 #define VADC_G_CEVNP0_CEV5NP_Pos 20 /*!< VADC_G CEVNP0: CEV5NP Position */
\r
10508 #define VADC_G_CEVNP0_CEV5NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV5NP_Pos) /*!< VADC_G CEVNP0: CEV5NP Mask */
\r
10509 #define VADC_G_CEVNP0_CEV6NP_Pos 24 /*!< VADC_G CEVNP0: CEV6NP Position */
\r
10510 #define VADC_G_CEVNP0_CEV6NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV6NP_Pos) /*!< VADC_G CEVNP0: CEV6NP Mask */
\r
10511 #define VADC_G_CEVNP0_CEV7NP_Pos 28 /*!< VADC_G CEVNP0: CEV7NP Position */
\r
10512 #define VADC_G_CEVNP0_CEV7NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV7NP_Pos) /*!< VADC_G CEVNP0: CEV7NP Mask */
\r
10514 /* -------------------------------- VADC_G_REVNP0 ------------------------------- */
\r
10515 #define VADC_G_REVNP0_REV0NP_Pos 0 /*!< VADC_G REVNP0: REV0NP Position */
\r
10516 #define VADC_G_REVNP0_REV0NP_Msk (0x0fUL << VADC_G_REVNP0_REV0NP_Pos) /*!< VADC_G REVNP0: REV0NP Mask */
\r
10517 #define VADC_G_REVNP0_REV1NP_Pos 4 /*!< VADC_G REVNP0: REV1NP Position */
\r
10518 #define VADC_G_REVNP0_REV1NP_Msk (0x0fUL << VADC_G_REVNP0_REV1NP_Pos) /*!< VADC_G REVNP0: REV1NP Mask */
\r
10519 #define VADC_G_REVNP0_REV2NP_Pos 8 /*!< VADC_G REVNP0: REV2NP Position */
\r
10520 #define VADC_G_REVNP0_REV2NP_Msk (0x0fUL << VADC_G_REVNP0_REV2NP_Pos) /*!< VADC_G REVNP0: REV2NP Mask */
\r
10521 #define VADC_G_REVNP0_REV3NP_Pos 12 /*!< VADC_G REVNP0: REV3NP Position */
\r
10522 #define VADC_G_REVNP0_REV3NP_Msk (0x0fUL << VADC_G_REVNP0_REV3NP_Pos) /*!< VADC_G REVNP0: REV3NP Mask */
\r
10523 #define VADC_G_REVNP0_REV4NP_Pos 16 /*!< VADC_G REVNP0: REV4NP Position */
\r
10524 #define VADC_G_REVNP0_REV4NP_Msk (0x0fUL << VADC_G_REVNP0_REV4NP_Pos) /*!< VADC_G REVNP0: REV4NP Mask */
\r
10525 #define VADC_G_REVNP0_REV5NP_Pos 20 /*!< VADC_G REVNP0: REV5NP Position */
\r
10526 #define VADC_G_REVNP0_REV5NP_Msk (0x0fUL << VADC_G_REVNP0_REV5NP_Pos) /*!< VADC_G REVNP0: REV5NP Mask */
\r
10527 #define VADC_G_REVNP0_REV6NP_Pos 24 /*!< VADC_G REVNP0: REV6NP Position */
\r
10528 #define VADC_G_REVNP0_REV6NP_Msk (0x0fUL << VADC_G_REVNP0_REV6NP_Pos) /*!< VADC_G REVNP0: REV6NP Mask */
\r
10529 #define VADC_G_REVNP0_REV7NP_Pos 28 /*!< VADC_G REVNP0: REV7NP Position */
\r
10530 #define VADC_G_REVNP0_REV7NP_Msk (0x0fUL << VADC_G_REVNP0_REV7NP_Pos) /*!< VADC_G REVNP0: REV7NP Mask */
\r
10532 /* -------------------------------- VADC_G_REVNP1 ------------------------------- */
\r
10533 #define VADC_G_REVNP1_REV8NP_Pos 0 /*!< VADC_G REVNP1: REV8NP Position */
\r
10534 #define VADC_G_REVNP1_REV8NP_Msk (0x0fUL << VADC_G_REVNP1_REV8NP_Pos) /*!< VADC_G REVNP1: REV8NP Mask */
\r
10535 #define VADC_G_REVNP1_REV9NP_Pos 4 /*!< VADC_G REVNP1: REV9NP Position */
\r
10536 #define VADC_G_REVNP1_REV9NP_Msk (0x0fUL << VADC_G_REVNP1_REV9NP_Pos) /*!< VADC_G REVNP1: REV9NP Mask */
\r
10537 #define VADC_G_REVNP1_REV10NP_Pos 8 /*!< VADC_G REVNP1: REV10NP Position */
\r
10538 #define VADC_G_REVNP1_REV10NP_Msk (0x0fUL << VADC_G_REVNP1_REV10NP_Pos) /*!< VADC_G REVNP1: REV10NP Mask */
\r
10539 #define VADC_G_REVNP1_REV11NP_Pos 12 /*!< VADC_G REVNP1: REV11NP Position */
\r
10540 #define VADC_G_REVNP1_REV11NP_Msk (0x0fUL << VADC_G_REVNP1_REV11NP_Pos) /*!< VADC_G REVNP1: REV11NP Mask */
\r
10541 #define VADC_G_REVNP1_REV12NP_Pos 16 /*!< VADC_G REVNP1: REV12NP Position */
\r
10542 #define VADC_G_REVNP1_REV12NP_Msk (0x0fUL << VADC_G_REVNP1_REV12NP_Pos) /*!< VADC_G REVNP1: REV12NP Mask */
\r
10543 #define VADC_G_REVNP1_REV13NP_Pos 20 /*!< VADC_G REVNP1: REV13NP Position */
\r
10544 #define VADC_G_REVNP1_REV13NP_Msk (0x0fUL << VADC_G_REVNP1_REV13NP_Pos) /*!< VADC_G REVNP1: REV13NP Mask */
\r
10545 #define VADC_G_REVNP1_REV14NP_Pos 24 /*!< VADC_G REVNP1: REV14NP Position */
\r
10546 #define VADC_G_REVNP1_REV14NP_Msk (0x0fUL << VADC_G_REVNP1_REV14NP_Pos) /*!< VADC_G REVNP1: REV14NP Mask */
\r
10547 #define VADC_G_REVNP1_REV15NP_Pos 28 /*!< VADC_G REVNP1: REV15NP Position */
\r
10548 #define VADC_G_REVNP1_REV15NP_Msk (0x0fUL << VADC_G_REVNP1_REV15NP_Pos) /*!< VADC_G REVNP1: REV15NP Mask */
\r
10550 /* -------------------------------- VADC_G_SEVNP -------------------------------- */
\r
10551 #define VADC_G_SEVNP_SEV0NP_Pos 0 /*!< VADC_G SEVNP: SEV0NP Position */
\r
10552 #define VADC_G_SEVNP_SEV0NP_Msk (0x0fUL << VADC_G_SEVNP_SEV0NP_Pos) /*!< VADC_G SEVNP: SEV0NP Mask */
\r
10553 #define VADC_G_SEVNP_SEV1NP_Pos 4 /*!< VADC_G SEVNP: SEV1NP Position */
\r
10554 #define VADC_G_SEVNP_SEV1NP_Msk (0x0fUL << VADC_G_SEVNP_SEV1NP_Pos) /*!< VADC_G SEVNP: SEV1NP Mask */
\r
10556 /* -------------------------------- VADC_G_SRACT -------------------------------- */
\r
10557 #define VADC_G_SRACT_AGSR0_Pos 0 /*!< VADC_G SRACT: AGSR0 Position */
\r
10558 #define VADC_G_SRACT_AGSR0_Msk (0x01UL << VADC_G_SRACT_AGSR0_Pos) /*!< VADC_G SRACT: AGSR0 Mask */
\r
10559 #define VADC_G_SRACT_AGSR1_Pos 1 /*!< VADC_G SRACT: AGSR1 Position */
\r
10560 #define VADC_G_SRACT_AGSR1_Msk (0x01UL << VADC_G_SRACT_AGSR1_Pos) /*!< VADC_G SRACT: AGSR1 Mask */
\r
10561 #define VADC_G_SRACT_AGSR2_Pos 2 /*!< VADC_G SRACT: AGSR2 Position */
\r
10562 #define VADC_G_SRACT_AGSR2_Msk (0x01UL << VADC_G_SRACT_AGSR2_Pos) /*!< VADC_G SRACT: AGSR2 Mask */
\r
10563 #define VADC_G_SRACT_AGSR3_Pos 3 /*!< VADC_G SRACT: AGSR3 Position */
\r
10564 #define VADC_G_SRACT_AGSR3_Msk (0x01UL << VADC_G_SRACT_AGSR3_Pos) /*!< VADC_G SRACT: AGSR3 Mask */
\r
10565 #define VADC_G_SRACT_ASSR0_Pos 8 /*!< VADC_G SRACT: ASSR0 Position */
\r
10566 #define VADC_G_SRACT_ASSR0_Msk (0x01UL << VADC_G_SRACT_ASSR0_Pos) /*!< VADC_G SRACT: ASSR0 Mask */
\r
10567 #define VADC_G_SRACT_ASSR1_Pos 9 /*!< VADC_G SRACT: ASSR1 Position */
\r
10568 #define VADC_G_SRACT_ASSR1_Msk (0x01UL << VADC_G_SRACT_ASSR1_Pos) /*!< VADC_G SRACT: ASSR1 Mask */
\r
10569 #define VADC_G_SRACT_ASSR2_Pos 10 /*!< VADC_G SRACT: ASSR2 Position */
\r
10570 #define VADC_G_SRACT_ASSR2_Msk (0x01UL << VADC_G_SRACT_ASSR2_Pos) /*!< VADC_G SRACT: ASSR2 Mask */
\r
10571 #define VADC_G_SRACT_ASSR3_Pos 11 /*!< VADC_G SRACT: ASSR3 Position */
\r
10572 #define VADC_G_SRACT_ASSR3_Msk (0x01UL << VADC_G_SRACT_ASSR3_Pos) /*!< VADC_G SRACT: ASSR3 Mask */
\r
10574 /* ------------------------------- VADC_G_EMUXCTR ------------------------------- */
\r
10575 #define VADC_G_EMUXCTR_EMUXSET_Pos 0 /*!< VADC_G EMUXCTR: EMUXSET Position */
\r
10576 #define VADC_G_EMUXCTR_EMUXSET_Msk (0x07UL << VADC_G_EMUXCTR_EMUXSET_Pos) /*!< VADC_G EMUXCTR: EMUXSET Mask */
\r
10577 #define VADC_G_EMUXCTR_EMUXACT_Pos 8 /*!< VADC_G EMUXCTR: EMUXACT Position */
\r
10578 #define VADC_G_EMUXCTR_EMUXACT_Msk (0x07UL << VADC_G_EMUXCTR_EMUXACT_Pos) /*!< VADC_G EMUXCTR: EMUXACT Mask */
\r
10579 #define VADC_G_EMUXCTR_EMUXCH_Pos 16 /*!< VADC_G EMUXCTR: EMUXCH Position */
\r
10580 #define VADC_G_EMUXCTR_EMUXCH_Msk (0x000003ffUL << VADC_G_EMUXCTR_EMUXCH_Pos) /*!< VADC_G EMUXCTR: EMUXCH Mask */
\r
10581 #define VADC_G_EMUXCTR_EMUXMODE_Pos 26 /*!< VADC_G EMUXCTR: EMUXMODE Position */
\r
10582 #define VADC_G_EMUXCTR_EMUXMODE_Msk (0x03UL << VADC_G_EMUXCTR_EMUXMODE_Pos) /*!< VADC_G EMUXCTR: EMUXMODE Mask */
\r
10583 #define VADC_G_EMUXCTR_EMXCOD_Pos 28 /*!< VADC_G EMUXCTR: EMXCOD Position */
\r
10584 #define VADC_G_EMUXCTR_EMXCOD_Msk (0x01UL << VADC_G_EMUXCTR_EMXCOD_Pos) /*!< VADC_G EMUXCTR: EMXCOD Mask */
\r
10585 #define VADC_G_EMUXCTR_EMXST_Pos 29 /*!< VADC_G EMUXCTR: EMXST Position */
\r
10586 #define VADC_G_EMUXCTR_EMXST_Msk (0x01UL << VADC_G_EMUXCTR_EMXST_Pos) /*!< VADC_G EMUXCTR: EMXST Mask */
\r
10587 #define VADC_G_EMUXCTR_EMXCSS_Pos 30 /*!< VADC_G EMUXCTR: EMXCSS Position */
\r
10588 #define VADC_G_EMUXCTR_EMXCSS_Msk (0x01UL << VADC_G_EMUXCTR_EMXCSS_Pos) /*!< VADC_G EMUXCTR: EMXCSS Mask */
\r
10589 #define VADC_G_EMUXCTR_EMXWC_Pos 31 /*!< VADC_G EMUXCTR: EMXWC Position */
\r
10590 #define VADC_G_EMUXCTR_EMXWC_Msk (0x01UL << VADC_G_EMUXCTR_EMXWC_Pos) /*!< VADC_G EMUXCTR: EMXWC Mask */
\r
10592 /* --------------------------------- VADC_G_VFR --------------------------------- */
\r
10593 #define VADC_G_VFR_VF0_Pos 0 /*!< VADC_G VFR: VF0 Position */
\r
10594 #define VADC_G_VFR_VF0_Msk (0x01UL << VADC_G_VFR_VF0_Pos) /*!< VADC_G VFR: VF0 Mask */
\r
10595 #define VADC_G_VFR_VF1_Pos 1 /*!< VADC_G VFR: VF1 Position */
\r
10596 #define VADC_G_VFR_VF1_Msk (0x01UL << VADC_G_VFR_VF1_Pos) /*!< VADC_G VFR: VF1 Mask */
\r
10597 #define VADC_G_VFR_VF2_Pos 2 /*!< VADC_G VFR: VF2 Position */
\r
10598 #define VADC_G_VFR_VF2_Msk (0x01UL << VADC_G_VFR_VF2_Pos) /*!< VADC_G VFR: VF2 Mask */
\r
10599 #define VADC_G_VFR_VF3_Pos 3 /*!< VADC_G VFR: VF3 Position */
\r
10600 #define VADC_G_VFR_VF3_Msk (0x01UL << VADC_G_VFR_VF3_Pos) /*!< VADC_G VFR: VF3 Mask */
\r
10601 #define VADC_G_VFR_VF4_Pos 4 /*!< VADC_G VFR: VF4 Position */
\r
10602 #define VADC_G_VFR_VF4_Msk (0x01UL << VADC_G_VFR_VF4_Pos) /*!< VADC_G VFR: VF4 Mask */
\r
10603 #define VADC_G_VFR_VF5_Pos 5 /*!< VADC_G VFR: VF5 Position */
\r
10604 #define VADC_G_VFR_VF5_Msk (0x01UL << VADC_G_VFR_VF5_Pos) /*!< VADC_G VFR: VF5 Mask */
\r
10605 #define VADC_G_VFR_VF6_Pos 6 /*!< VADC_G VFR: VF6 Position */
\r
10606 #define VADC_G_VFR_VF6_Msk (0x01UL << VADC_G_VFR_VF6_Pos) /*!< VADC_G VFR: VF6 Mask */
\r
10607 #define VADC_G_VFR_VF7_Pos 7 /*!< VADC_G VFR: VF7 Position */
\r
10608 #define VADC_G_VFR_VF7_Msk (0x01UL << VADC_G_VFR_VF7_Pos) /*!< VADC_G VFR: VF7 Mask */
\r
10609 #define VADC_G_VFR_VF8_Pos 8 /*!< VADC_G VFR: VF8 Position */
\r
10610 #define VADC_G_VFR_VF8_Msk (0x01UL << VADC_G_VFR_VF8_Pos) /*!< VADC_G VFR: VF8 Mask */
\r
10611 #define VADC_G_VFR_VF9_Pos 9 /*!< VADC_G VFR: VF9 Position */
\r
10612 #define VADC_G_VFR_VF9_Msk (0x01UL << VADC_G_VFR_VF9_Pos) /*!< VADC_G VFR: VF9 Mask */
\r
10613 #define VADC_G_VFR_VF10_Pos 10 /*!< VADC_G VFR: VF10 Position */
\r
10614 #define VADC_G_VFR_VF10_Msk (0x01UL << VADC_G_VFR_VF10_Pos) /*!< VADC_G VFR: VF10 Mask */
\r
10615 #define VADC_G_VFR_VF11_Pos 11 /*!< VADC_G VFR: VF11 Position */
\r
10616 #define VADC_G_VFR_VF11_Msk (0x01UL << VADC_G_VFR_VF11_Pos) /*!< VADC_G VFR: VF11 Mask */
\r
10617 #define VADC_G_VFR_VF12_Pos 12 /*!< VADC_G VFR: VF12 Position */
\r
10618 #define VADC_G_VFR_VF12_Msk (0x01UL << VADC_G_VFR_VF12_Pos) /*!< VADC_G VFR: VF12 Mask */
\r
10619 #define VADC_G_VFR_VF13_Pos 13 /*!< VADC_G VFR: VF13 Position */
\r
10620 #define VADC_G_VFR_VF13_Msk (0x01UL << VADC_G_VFR_VF13_Pos) /*!< VADC_G VFR: VF13 Mask */
\r
10621 #define VADC_G_VFR_VF14_Pos 14 /*!< VADC_G VFR: VF14 Position */
\r
10622 #define VADC_G_VFR_VF14_Msk (0x01UL << VADC_G_VFR_VF14_Pos) /*!< VADC_G VFR: VF14 Mask */
\r
10623 #define VADC_G_VFR_VF15_Pos 15 /*!< VADC_G VFR: VF15 Position */
\r
10624 #define VADC_G_VFR_VF15_Msk (0x01UL << VADC_G_VFR_VF15_Pos) /*!< VADC_G VFR: VF15 Mask */
\r
10626 /* -------------------------------- VADC_G_CHCTR -------------------------------- */
\r
10627 #define VADC_G_CHCTR_ICLSEL_Pos 0 /*!< VADC_G CHCTR: ICLSEL Position */
\r
10628 #define VADC_G_CHCTR_ICLSEL_Msk (0x03UL << VADC_G_CHCTR_ICLSEL_Pos) /*!< VADC_G CHCTR: ICLSEL Mask */
\r
10629 #define VADC_G_CHCTR_BNDSELL_Pos 4 /*!< VADC_G CHCTR: BNDSELL Position */
\r
10630 #define VADC_G_CHCTR_BNDSELL_Msk (0x03UL << VADC_G_CHCTR_BNDSELL_Pos) /*!< VADC_G CHCTR: BNDSELL Mask */
\r
10631 #define VADC_G_CHCTR_BNDSELU_Pos 6 /*!< VADC_G CHCTR: BNDSELU Position */
\r
10632 #define VADC_G_CHCTR_BNDSELU_Msk (0x03UL << VADC_G_CHCTR_BNDSELU_Pos) /*!< VADC_G CHCTR: BNDSELU Mask */
\r
10633 #define VADC_G_CHCTR_CHEVMODE_Pos 8 /*!< VADC_G CHCTR: CHEVMODE Position */
\r
10634 #define VADC_G_CHCTR_CHEVMODE_Msk (0x03UL << VADC_G_CHCTR_CHEVMODE_Pos) /*!< VADC_G CHCTR: CHEVMODE Mask */
\r
10635 #define VADC_G_CHCTR_SYNC_Pos 10 /*!< VADC_G CHCTR: SYNC Position */
\r
10636 #define VADC_G_CHCTR_SYNC_Msk (0x01UL << VADC_G_CHCTR_SYNC_Pos) /*!< VADC_G CHCTR: SYNC Mask */
\r
10637 #define VADC_G_CHCTR_REFSEL_Pos 11 /*!< VADC_G CHCTR: REFSEL Position */
\r
10638 #define VADC_G_CHCTR_REFSEL_Msk (0x01UL << VADC_G_CHCTR_REFSEL_Pos) /*!< VADC_G CHCTR: REFSEL Mask */
\r
10639 #define VADC_G_CHCTR_RESREG_Pos 16 /*!< VADC_G CHCTR: RESREG Position */
\r
10640 #define VADC_G_CHCTR_RESREG_Msk (0x0fUL << VADC_G_CHCTR_RESREG_Pos) /*!< VADC_G CHCTR: RESREG Mask */
\r
10641 #define VADC_G_CHCTR_RESTBS_Pos 20 /*!< VADC_G CHCTR: RESTBS Position */
\r
10642 #define VADC_G_CHCTR_RESTBS_Msk (0x01UL << VADC_G_CHCTR_RESTBS_Pos) /*!< VADC_G CHCTR: RESTBS Mask */
\r
10643 #define VADC_G_CHCTR_RESPOS_Pos 21 /*!< VADC_G CHCTR: RESPOS Position */
\r
10644 #define VADC_G_CHCTR_RESPOS_Msk (0x01UL << VADC_G_CHCTR_RESPOS_Pos) /*!< VADC_G CHCTR: RESPOS Mask */
\r
10645 #define VADC_G_CHCTR_BWDCH_Pos 28 /*!< VADC_G CHCTR: BWDCH Position */
\r
10646 #define VADC_G_CHCTR_BWDCH_Msk (0x03UL << VADC_G_CHCTR_BWDCH_Pos) /*!< VADC_G CHCTR: BWDCH Mask */
\r
10647 #define VADC_G_CHCTR_BWDEN_Pos 30 /*!< VADC_G CHCTR: BWDEN Position */
\r
10648 #define VADC_G_CHCTR_BWDEN_Msk (0x01UL << VADC_G_CHCTR_BWDEN_Pos) /*!< VADC_G CHCTR: BWDEN Mask */
\r
10650 /* --------------------------------- VADC_G_RCR --------------------------------- */
\r
10651 #define VADC_G_RCR_DRCTR_Pos 16 /*!< VADC_G RCR: DRCTR Position */
\r
10652 #define VADC_G_RCR_DRCTR_Msk (0x0fUL << VADC_G_RCR_DRCTR_Pos) /*!< VADC_G RCR: DRCTR Mask */
\r
10653 #define VADC_G_RCR_DMM_Pos 20 /*!< VADC_G RCR: DMM Position */
\r
10654 #define VADC_G_RCR_DMM_Msk (0x03UL << VADC_G_RCR_DMM_Pos) /*!< VADC_G RCR: DMM Mask */
\r
10655 #define VADC_G_RCR_WFR_Pos 24 /*!< VADC_G RCR: WFR Position */
\r
10656 #define VADC_G_RCR_WFR_Msk (0x01UL << VADC_G_RCR_WFR_Pos) /*!< VADC_G RCR: WFR Mask */
\r
10657 #define VADC_G_RCR_FEN_Pos 25 /*!< VADC_G RCR: FEN Position */
\r
10658 #define VADC_G_RCR_FEN_Msk (0x03UL << VADC_G_RCR_FEN_Pos) /*!< VADC_G RCR: FEN Mask */
\r
10659 #define VADC_G_RCR_SRGEN_Pos 31 /*!< VADC_G RCR: SRGEN Position */
\r
10660 #define VADC_G_RCR_SRGEN_Msk (0x01UL << VADC_G_RCR_SRGEN_Pos) /*!< VADC_G RCR: SRGEN Mask */
\r
10662 /* --------------------------------- VADC_G_RES --------------------------------- */
\r
10663 #define VADC_G_RES_RESULT_Pos 0 /*!< VADC_G RES: RESULT Position */
\r
10664 #define VADC_G_RES_RESULT_Msk (0x0000ffffUL << VADC_G_RES_RESULT_Pos) /*!< VADC_G RES: RESULT Mask */
\r
10665 #define VADC_G_RES_DRC_Pos 16 /*!< VADC_G RES: DRC Position */
\r
10666 #define VADC_G_RES_DRC_Msk (0x0fUL << VADC_G_RES_DRC_Pos) /*!< VADC_G RES: DRC Mask */
\r
10667 #define VADC_G_RES_CHNR_Pos 20 /*!< VADC_G RES: CHNR Position */
\r
10668 #define VADC_G_RES_CHNR_Msk (0x1fUL << VADC_G_RES_CHNR_Pos) /*!< VADC_G RES: CHNR Mask */
\r
10669 #define VADC_G_RES_EMUX_Pos 25 /*!< VADC_G RES: EMUX Position */
\r
10670 #define VADC_G_RES_EMUX_Msk (0x07UL << VADC_G_RES_EMUX_Pos) /*!< VADC_G RES: EMUX Mask */
\r
10671 #define VADC_G_RES_CRS_Pos 28 /*!< VADC_G RES: CRS Position */
\r
10672 #define VADC_G_RES_CRS_Msk (0x03UL << VADC_G_RES_CRS_Pos) /*!< VADC_G RES: CRS Mask */
\r
10673 #define VADC_G_RES_FCR_Pos 30 /*!< VADC_G RES: FCR Position */
\r
10674 #define VADC_G_RES_FCR_Msk (0x01UL << VADC_G_RES_FCR_Pos) /*!< VADC_G RES: FCR Mask */
\r
10675 #define VADC_G_RES_VF_Pos 31 /*!< VADC_G RES: VF Position */
\r
10676 #define VADC_G_RES_VF_Msk (0x01UL << VADC_G_RES_VF_Pos) /*!< VADC_G RES: VF Mask */
\r
10678 /* --------------------------------- VADC_G_RESD -------------------------------- */
\r
10679 #define VADC_G_RESD_RESULT_Pos 0 /*!< VADC_G RESD: RESULT Position */
\r
10680 #define VADC_G_RESD_RESULT_Msk (0x0000ffffUL << VADC_G_RESD_RESULT_Pos) /*!< VADC_G RESD: RESULT Mask */
\r
10681 #define VADC_G_RESD_DRC_Pos 16 /*!< VADC_G RESD: DRC Position */
\r
10682 #define VADC_G_RESD_DRC_Msk (0x0fUL << VADC_G_RESD_DRC_Pos) /*!< VADC_G RESD: DRC Mask */
\r
10683 #define VADC_G_RESD_CHNR_Pos 20 /*!< VADC_G RESD: CHNR Position */
\r
10684 #define VADC_G_RESD_CHNR_Msk (0x1fUL << VADC_G_RESD_CHNR_Pos) /*!< VADC_G RESD: CHNR Mask */
\r
10685 #define VADC_G_RESD_EMUX_Pos 25 /*!< VADC_G RESD: EMUX Position */
\r
10686 #define VADC_G_RESD_EMUX_Msk (0x07UL << VADC_G_RESD_EMUX_Pos) /*!< VADC_G RESD: EMUX Mask */
\r
10687 #define VADC_G_RESD_CRS_Pos 28 /*!< VADC_G RESD: CRS Position */
\r
10688 #define VADC_G_RESD_CRS_Msk (0x03UL << VADC_G_RESD_CRS_Pos) /*!< VADC_G RESD: CRS Mask */
\r
10689 #define VADC_G_RESD_FCR_Pos 30 /*!< VADC_G RESD: FCR Position */
\r
10690 #define VADC_G_RESD_FCR_Msk (0x01UL << VADC_G_RESD_FCR_Pos) /*!< VADC_G RESD: FCR Mask */
\r
10691 #define VADC_G_RESD_VF_Pos 31 /*!< VADC_G RESD: VF Position */
\r
10692 #define VADC_G_RESD_VF_Msk (0x01UL << VADC_G_RESD_VF_Pos) /*!< VADC_G RESD: VF Mask */
\r
10695 /* ================================================================================ */
\r
10696 /* ================ struct 'DSD' Position & Mask ================ */
\r
10697 /* ================================================================================ */
\r
10700 /* ----------------------------------- DSD_CLC ---------------------------------- */
\r
10701 #define DSD_CLC_DISR_Pos 0 /*!< DSD CLC: DISR Position */
\r
10702 #define DSD_CLC_DISR_Msk (0x01UL << DSD_CLC_DISR_Pos) /*!< DSD CLC: DISR Mask */
\r
10703 #define DSD_CLC_DISS_Pos 1 /*!< DSD CLC: DISS Position */
\r
10704 #define DSD_CLC_DISS_Msk (0x01UL << DSD_CLC_DISS_Pos) /*!< DSD CLC: DISS Mask */
\r
10705 #define DSD_CLC_EDIS_Pos 3 /*!< DSD CLC: EDIS Position */
\r
10706 #define DSD_CLC_EDIS_Msk (0x01UL << DSD_CLC_EDIS_Pos) /*!< DSD CLC: EDIS Mask */
\r
10708 /* ----------------------------------- DSD_ID ----------------------------------- */
\r
10709 #define DSD_ID_MOD_REV_Pos 0 /*!< DSD ID: MOD_REV Position */
\r
10710 #define DSD_ID_MOD_REV_Msk (0x000000ffUL << DSD_ID_MOD_REV_Pos) /*!< DSD ID: MOD_REV Mask */
\r
10711 #define DSD_ID_MOD_TYPE_Pos 8 /*!< DSD ID: MOD_TYPE Position */
\r
10712 #define DSD_ID_MOD_TYPE_Msk (0x000000ffUL << DSD_ID_MOD_TYPE_Pos) /*!< DSD ID: MOD_TYPE Mask */
\r
10713 #define DSD_ID_MOD_NUMBER_Pos 16 /*!< DSD ID: MOD_NUMBER Position */
\r
10714 #define DSD_ID_MOD_NUMBER_Msk (0x0000ffffUL << DSD_ID_MOD_NUMBER_Pos) /*!< DSD ID: MOD_NUMBER Mask */
\r
10716 /* ----------------------------------- DSD_OCS ---------------------------------- */
\r
10717 #define DSD_OCS_SUS_Pos 24 /*!< DSD OCS: SUS Position */
\r
10718 #define DSD_OCS_SUS_Msk (0x0fUL << DSD_OCS_SUS_Pos) /*!< DSD OCS: SUS Mask */
\r
10719 #define DSD_OCS_SUS_P_Pos 28 /*!< DSD OCS: SUS_P Position */
\r
10720 #define DSD_OCS_SUS_P_Msk (0x01UL << DSD_OCS_SUS_P_Pos) /*!< DSD OCS: SUS_P Mask */
\r
10721 #define DSD_OCS_SUSSTA_Pos 29 /*!< DSD OCS: SUSSTA Position */
\r
10722 #define DSD_OCS_SUSSTA_Msk (0x01UL << DSD_OCS_SUSSTA_Pos) /*!< DSD OCS: SUSSTA Mask */
\r
10724 /* --------------------------------- DSD_GLOBCFG -------------------------------- */
\r
10725 #define DSD_GLOBCFG_MCSEL_Pos 0 /*!< DSD GLOBCFG: MCSEL Position */
\r
10726 #define DSD_GLOBCFG_MCSEL_Msk (0x07UL << DSD_GLOBCFG_MCSEL_Pos) /*!< DSD GLOBCFG: MCSEL Mask */
\r
10728 /* --------------------------------- DSD_GLOBRC --------------------------------- */
\r
10729 #define DSD_GLOBRC_CH0RUN_Pos 0 /*!< DSD GLOBRC: CH0RUN Position */
\r
10730 #define DSD_GLOBRC_CH0RUN_Msk (0x01UL << DSD_GLOBRC_CH0RUN_Pos) /*!< DSD GLOBRC: CH0RUN Mask */
\r
10731 #define DSD_GLOBRC_CH1RUN_Pos 1 /*!< DSD GLOBRC: CH1RUN Position */
\r
10732 #define DSD_GLOBRC_CH1RUN_Msk (0x01UL << DSD_GLOBRC_CH1RUN_Pos) /*!< DSD GLOBRC: CH1RUN Mask */
\r
10733 #define DSD_GLOBRC_CH2RUN_Pos 2 /*!< DSD GLOBRC: CH2RUN Position */
\r
10734 #define DSD_GLOBRC_CH2RUN_Msk (0x01UL << DSD_GLOBRC_CH2RUN_Pos) /*!< DSD GLOBRC: CH2RUN Mask */
\r
10735 #define DSD_GLOBRC_CH3RUN_Pos 3 /*!< DSD GLOBRC: CH3RUN Position */
\r
10736 #define DSD_GLOBRC_CH3RUN_Msk (0x01UL << DSD_GLOBRC_CH3RUN_Pos) /*!< DSD GLOBRC: CH3RUN Mask */
\r
10738 /* ---------------------------------- DSD_CGCFG --------------------------------- */
\r
10739 #define DSD_CGCFG_CGMOD_Pos 0 /*!< DSD CGCFG: CGMOD Position */
\r
10740 #define DSD_CGCFG_CGMOD_Msk (0x03UL << DSD_CGCFG_CGMOD_Pos) /*!< DSD CGCFG: CGMOD Mask */
\r
10741 #define DSD_CGCFG_BREV_Pos 2 /*!< DSD CGCFG: BREV Position */
\r
10742 #define DSD_CGCFG_BREV_Msk (0x01UL << DSD_CGCFG_BREV_Pos) /*!< DSD CGCFG: BREV Mask */
\r
10743 #define DSD_CGCFG_SIGPOL_Pos 3 /*!< DSD CGCFG: SIGPOL Position */
\r
10744 #define DSD_CGCFG_SIGPOL_Msk (0x01UL << DSD_CGCFG_SIGPOL_Pos) /*!< DSD CGCFG: SIGPOL Mask */
\r
10745 #define DSD_CGCFG_DIVCG_Pos 4 /*!< DSD CGCFG: DIVCG Position */
\r
10746 #define DSD_CGCFG_DIVCG_Msk (0x0fUL << DSD_CGCFG_DIVCG_Pos) /*!< DSD CGCFG: DIVCG Mask */
\r
10747 #define DSD_CGCFG_RUN_Pos 15 /*!< DSD CGCFG: RUN Position */
\r
10748 #define DSD_CGCFG_RUN_Msk (0x01UL << DSD_CGCFG_RUN_Pos) /*!< DSD CGCFG: RUN Mask */
\r
10749 #define DSD_CGCFG_BITCOUNT_Pos 16 /*!< DSD CGCFG: BITCOUNT Position */
\r
10750 #define DSD_CGCFG_BITCOUNT_Msk (0x1fUL << DSD_CGCFG_BITCOUNT_Pos) /*!< DSD CGCFG: BITCOUNT Mask */
\r
10751 #define DSD_CGCFG_STEPCOUNT_Pos 24 /*!< DSD CGCFG: STEPCOUNT Position */
\r
10752 #define DSD_CGCFG_STEPCOUNT_Msk (0x0fUL << DSD_CGCFG_STEPCOUNT_Pos) /*!< DSD CGCFG: STEPCOUNT Mask */
\r
10753 #define DSD_CGCFG_STEPS_Pos 28 /*!< DSD CGCFG: STEPS Position */
\r
10754 #define DSD_CGCFG_STEPS_Msk (0x01UL << DSD_CGCFG_STEPS_Pos) /*!< DSD CGCFG: STEPS Mask */
\r
10755 #define DSD_CGCFG_STEPD_Pos 29 /*!< DSD CGCFG: STEPD Position */
\r
10756 #define DSD_CGCFG_STEPD_Msk (0x01UL << DSD_CGCFG_STEPD_Pos) /*!< DSD CGCFG: STEPD Mask */
\r
10757 #define DSD_CGCFG_SGNCG_Pos 30 /*!< DSD CGCFG: SGNCG Position */
\r
10758 #define DSD_CGCFG_SGNCG_Msk (0x01UL << DSD_CGCFG_SGNCG_Pos) /*!< DSD CGCFG: SGNCG Mask */
\r
10760 /* --------------------------------- DSD_EVFLAG --------------------------------- */
\r
10761 #define DSD_EVFLAG_RESEV0_Pos 0 /*!< DSD EVFLAG: RESEV0 Position */
\r
10762 #define DSD_EVFLAG_RESEV0_Msk (0x01UL << DSD_EVFLAG_RESEV0_Pos) /*!< DSD EVFLAG: RESEV0 Mask */
\r
10763 #define DSD_EVFLAG_RESEV1_Pos 1 /*!< DSD EVFLAG: RESEV1 Position */
\r
10764 #define DSD_EVFLAG_RESEV1_Msk (0x01UL << DSD_EVFLAG_RESEV1_Pos) /*!< DSD EVFLAG: RESEV1 Mask */
\r
10765 #define DSD_EVFLAG_RESEV2_Pos 2 /*!< DSD EVFLAG: RESEV2 Position */
\r
10766 #define DSD_EVFLAG_RESEV2_Msk (0x01UL << DSD_EVFLAG_RESEV2_Pos) /*!< DSD EVFLAG: RESEV2 Mask */
\r
10767 #define DSD_EVFLAG_RESEV3_Pos 3 /*!< DSD EVFLAG: RESEV3 Position */
\r
10768 #define DSD_EVFLAG_RESEV3_Msk (0x01UL << DSD_EVFLAG_RESEV3_Pos) /*!< DSD EVFLAG: RESEV3 Mask */
\r
10769 #define DSD_EVFLAG_ALEV0_Pos 16 /*!< DSD EVFLAG: ALEV0 Position */
\r
10770 #define DSD_EVFLAG_ALEV0_Msk (0x01UL << DSD_EVFLAG_ALEV0_Pos) /*!< DSD EVFLAG: ALEV0 Mask */
\r
10771 #define DSD_EVFLAG_ALEV1_Pos 17 /*!< DSD EVFLAG: ALEV1 Position */
\r
10772 #define DSD_EVFLAG_ALEV1_Msk (0x01UL << DSD_EVFLAG_ALEV1_Pos) /*!< DSD EVFLAG: ALEV1 Mask */
\r
10773 #define DSD_EVFLAG_ALEV2_Pos 18 /*!< DSD EVFLAG: ALEV2 Position */
\r
10774 #define DSD_EVFLAG_ALEV2_Msk (0x01UL << DSD_EVFLAG_ALEV2_Pos) /*!< DSD EVFLAG: ALEV2 Mask */
\r
10775 #define DSD_EVFLAG_ALEV3_Pos 19 /*!< DSD EVFLAG: ALEV3 Position */
\r
10776 #define DSD_EVFLAG_ALEV3_Msk (0x01UL << DSD_EVFLAG_ALEV3_Pos) /*!< DSD EVFLAG: ALEV3 Mask */
\r
10777 #define DSD_EVFLAG_ALEV4_Pos 20 /*!< DSD EVFLAG: ALEV4 Position */
\r
10778 #define DSD_EVFLAG_ALEV4_Msk (0x01UL << DSD_EVFLAG_ALEV4_Pos) /*!< DSD EVFLAG: ALEV4 Mask */
\r
10779 #define DSD_EVFLAG_ALEV5_Pos 21 /*!< DSD EVFLAG: ALEV5 Position */
\r
10780 #define DSD_EVFLAG_ALEV5_Msk (0x01UL << DSD_EVFLAG_ALEV5_Pos) /*!< DSD EVFLAG: ALEV5 Mask */
\r
10781 #define DSD_EVFLAG_ALEV6_Pos 22 /*!< DSD EVFLAG: ALEV6 Position */
\r
10782 #define DSD_EVFLAG_ALEV6_Msk (0x01UL << DSD_EVFLAG_ALEV6_Pos) /*!< DSD EVFLAG: ALEV6 Mask */
\r
10783 #define DSD_EVFLAG_ALEV7_Pos 23 /*!< DSD EVFLAG: ALEV7 Position */
\r
10784 #define DSD_EVFLAG_ALEV7_Msk (0x01UL << DSD_EVFLAG_ALEV7_Pos) /*!< DSD EVFLAG: ALEV7 Mask */
\r
10785 #define DSD_EVFLAG_ALEV8_Pos 24 /*!< DSD EVFLAG: ALEV8 Position */
\r
10786 #define DSD_EVFLAG_ALEV8_Msk (0x01UL << DSD_EVFLAG_ALEV8_Pos) /*!< DSD EVFLAG: ALEV8 Mask */
\r
10787 #define DSD_EVFLAG_ALEV9_Pos 25 /*!< DSD EVFLAG: ALEV9 Position */
\r
10788 #define DSD_EVFLAG_ALEV9_Msk (0x01UL << DSD_EVFLAG_ALEV9_Pos) /*!< DSD EVFLAG: ALEV9 Mask */
\r
10790 /* -------------------------------- DSD_EVFLAGCLR ------------------------------- */
\r
10791 #define DSD_EVFLAGCLR_RESEC0_Pos 0 /*!< DSD EVFLAGCLR: RESEC0 Position */
\r
10792 #define DSD_EVFLAGCLR_RESEC0_Msk (0x01UL << DSD_EVFLAGCLR_RESEC0_Pos) /*!< DSD EVFLAGCLR: RESEC0 Mask */
\r
10793 #define DSD_EVFLAGCLR_RESEC1_Pos 1 /*!< DSD EVFLAGCLR: RESEC1 Position */
\r
10794 #define DSD_EVFLAGCLR_RESEC1_Msk (0x01UL << DSD_EVFLAGCLR_RESEC1_Pos) /*!< DSD EVFLAGCLR: RESEC1 Mask */
\r
10795 #define DSD_EVFLAGCLR_RESEC2_Pos 2 /*!< DSD EVFLAGCLR: RESEC2 Position */
\r
10796 #define DSD_EVFLAGCLR_RESEC2_Msk (0x01UL << DSD_EVFLAGCLR_RESEC2_Pos) /*!< DSD EVFLAGCLR: RESEC2 Mask */
\r
10797 #define DSD_EVFLAGCLR_RESEC3_Pos 3 /*!< DSD EVFLAGCLR: RESEC3 Position */
\r
10798 #define DSD_EVFLAGCLR_RESEC3_Msk (0x01UL << DSD_EVFLAGCLR_RESEC3_Pos) /*!< DSD EVFLAGCLR: RESEC3 Mask */
\r
10799 #define DSD_EVFLAGCLR_ALEC0_Pos 16 /*!< DSD EVFLAGCLR: ALEC0 Position */
\r
10800 #define DSD_EVFLAGCLR_ALEC0_Msk (0x01UL << DSD_EVFLAGCLR_ALEC0_Pos) /*!< DSD EVFLAGCLR: ALEC0 Mask */
\r
10801 #define DSD_EVFLAGCLR_ALEC1_Pos 17 /*!< DSD EVFLAGCLR: ALEC1 Position */
\r
10802 #define DSD_EVFLAGCLR_ALEC1_Msk (0x01UL << DSD_EVFLAGCLR_ALEC1_Pos) /*!< DSD EVFLAGCLR: ALEC1 Mask */
\r
10803 #define DSD_EVFLAGCLR_ALEC2_Pos 18 /*!< DSD EVFLAGCLR: ALEC2 Position */
\r
10804 #define DSD_EVFLAGCLR_ALEC2_Msk (0x01UL << DSD_EVFLAGCLR_ALEC2_Pos) /*!< DSD EVFLAGCLR: ALEC2 Mask */
\r
10805 #define DSD_EVFLAGCLR_ALEC3_Pos 19 /*!< DSD EVFLAGCLR: ALEC3 Position */
\r
10806 #define DSD_EVFLAGCLR_ALEC3_Msk (0x01UL << DSD_EVFLAGCLR_ALEC3_Pos) /*!< DSD EVFLAGCLR: ALEC3 Mask */
\r
10809 /* ================================================================================ */
\r
10810 /* ================ Group 'DSD_CH' Position & Mask ================ */
\r
10811 /* ================================================================================ */
\r
10814 /* -------------------------------- DSD_CH_MODCFG ------------------------------- */
\r
10815 #define DSD_CH_MODCFG_DIVM_Pos 16 /*!< DSD_CH MODCFG: DIVM Position */
\r
10816 #define DSD_CH_MODCFG_DIVM_Msk (0x0fUL << DSD_CH_MODCFG_DIVM_Pos) /*!< DSD_CH MODCFG: DIVM Mask */
\r
10817 #define DSD_CH_MODCFG_DWC_Pos 23 /*!< DSD_CH MODCFG: DWC Position */
\r
10818 #define DSD_CH_MODCFG_DWC_Msk (0x01UL << DSD_CH_MODCFG_DWC_Pos) /*!< DSD_CH MODCFG: DWC Mask */
\r
10820 /* -------------------------------- DSD_CH_DICFG -------------------------------- */
\r
10821 #define DSD_CH_DICFG_DSRC_Pos 0 /*!< DSD_CH DICFG: DSRC Position */
\r
10822 #define DSD_CH_DICFG_DSRC_Msk (0x0fUL << DSD_CH_DICFG_DSRC_Pos) /*!< DSD_CH DICFG: DSRC Mask */
\r
10823 #define DSD_CH_DICFG_DSWC_Pos 7 /*!< DSD_CH DICFG: DSWC Position */
\r
10824 #define DSD_CH_DICFG_DSWC_Msk (0x01UL << DSD_CH_DICFG_DSWC_Pos) /*!< DSD_CH DICFG: DSWC Mask */
\r
10825 #define DSD_CH_DICFG_ITRMODE_Pos 8 /*!< DSD_CH DICFG: ITRMODE Position */
\r
10826 #define DSD_CH_DICFG_ITRMODE_Msk (0x03UL << DSD_CH_DICFG_ITRMODE_Pos) /*!< DSD_CH DICFG: ITRMODE Mask */
\r
10827 #define DSD_CH_DICFG_TSTRMODE_Pos 10 /*!< DSD_CH DICFG: TSTRMODE Position */
\r
10828 #define DSD_CH_DICFG_TSTRMODE_Msk (0x03UL << DSD_CH_DICFG_TSTRMODE_Pos) /*!< DSD_CH DICFG: TSTRMODE Mask */
\r
10829 #define DSD_CH_DICFG_TRSEL_Pos 12 /*!< DSD_CH DICFG: TRSEL Position */
\r
10830 #define DSD_CH_DICFG_TRSEL_Msk (0x07UL << DSD_CH_DICFG_TRSEL_Pos) /*!< DSD_CH DICFG: TRSEL Mask */
\r
10831 #define DSD_CH_DICFG_TRWC_Pos 15 /*!< DSD_CH DICFG: TRWC Position */
\r
10832 #define DSD_CH_DICFG_TRWC_Msk (0x01UL << DSD_CH_DICFG_TRWC_Pos) /*!< DSD_CH DICFG: TRWC Mask */
\r
10833 #define DSD_CH_DICFG_CSRC_Pos 16 /*!< DSD_CH DICFG: CSRC Position */
\r
10834 #define DSD_CH_DICFG_CSRC_Msk (0x0fUL << DSD_CH_DICFG_CSRC_Pos) /*!< DSD_CH DICFG: CSRC Mask */
\r
10835 #define DSD_CH_DICFG_STROBE_Pos 20 /*!< DSD_CH DICFG: STROBE Position */
\r
10836 #define DSD_CH_DICFG_STROBE_Msk (0x0fUL << DSD_CH_DICFG_STROBE_Pos) /*!< DSD_CH DICFG: STROBE Mask */
\r
10837 #define DSD_CH_DICFG_SCWC_Pos 31 /*!< DSD_CH DICFG: SCWC Position */
\r
10838 #define DSD_CH_DICFG_SCWC_Msk (0x01UL << DSD_CH_DICFG_SCWC_Pos) /*!< DSD_CH DICFG: SCWC Mask */
\r
10840 /* -------------------------------- DSD_CH_FCFGC -------------------------------- */
\r
10841 #define DSD_CH_FCFGC_CFMDF_Pos 0 /*!< DSD_CH FCFGC: CFMDF Position */
\r
10842 #define DSD_CH_FCFGC_CFMDF_Msk (0x000000ffUL << DSD_CH_FCFGC_CFMDF_Pos) /*!< DSD_CH FCFGC: CFMDF Mask */
\r
10843 #define DSD_CH_FCFGC_CFMC_Pos 8 /*!< DSD_CH FCFGC: CFMC Position */
\r
10844 #define DSD_CH_FCFGC_CFMC_Msk (0x03UL << DSD_CH_FCFGC_CFMC_Pos) /*!< DSD_CH FCFGC: CFMC Mask */
\r
10845 #define DSD_CH_FCFGC_CFEN_Pos 10 /*!< DSD_CH FCFGC: CFEN Position */
\r
10846 #define DSD_CH_FCFGC_CFEN_Msk (0x01UL << DSD_CH_FCFGC_CFEN_Pos) /*!< DSD_CH FCFGC: CFEN Mask */
\r
10847 #define DSD_CH_FCFGC_SRGM_Pos 14 /*!< DSD_CH FCFGC: SRGM Position */
\r
10848 #define DSD_CH_FCFGC_SRGM_Msk (0x03UL << DSD_CH_FCFGC_SRGM_Pos) /*!< DSD_CH FCFGC: SRGM Mask */
\r
10849 #define DSD_CH_FCFGC_CFMSV_Pos 16 /*!< DSD_CH FCFGC: CFMSV Position */
\r
10850 #define DSD_CH_FCFGC_CFMSV_Msk (0x000000ffUL << DSD_CH_FCFGC_CFMSV_Pos) /*!< DSD_CH FCFGC: CFMSV Mask */
\r
10851 #define DSD_CH_FCFGC_CFMDCNT_Pos 24 /*!< DSD_CH FCFGC: CFMDCNT Position */
\r
10852 #define DSD_CH_FCFGC_CFMDCNT_Msk (0x000000ffUL << DSD_CH_FCFGC_CFMDCNT_Pos) /*!< DSD_CH FCFGC: CFMDCNT Mask */
\r
10854 /* -------------------------------- DSD_CH_FCFGA -------------------------------- */
\r
10855 #define DSD_CH_FCFGA_CFADF_Pos 0 /*!< DSD_CH FCFGA: CFADF Position */
\r
10856 #define DSD_CH_FCFGA_CFADF_Msk (0x000000ffUL << DSD_CH_FCFGA_CFADF_Pos) /*!< DSD_CH FCFGA: CFADF Mask */
\r
10857 #define DSD_CH_FCFGA_CFAC_Pos 8 /*!< DSD_CH FCFGA: CFAC Position */
\r
10858 #define DSD_CH_FCFGA_CFAC_Msk (0x03UL << DSD_CH_FCFGA_CFAC_Pos) /*!< DSD_CH FCFGA: CFAC Mask */
\r
10859 #define DSD_CH_FCFGA_SRGA_Pos 10 /*!< DSD_CH FCFGA: SRGA Position */
\r
10860 #define DSD_CH_FCFGA_SRGA_Msk (0x03UL << DSD_CH_FCFGA_SRGA_Pos) /*!< DSD_CH FCFGA: SRGA Mask */
\r
10861 #define DSD_CH_FCFGA_ESEL_Pos 12 /*!< DSD_CH FCFGA: ESEL Position */
\r
10862 #define DSD_CH_FCFGA_ESEL_Msk (0x03UL << DSD_CH_FCFGA_ESEL_Pos) /*!< DSD_CH FCFGA: ESEL Mask */
\r
10863 #define DSD_CH_FCFGA_EGT_Pos 14 /*!< DSD_CH FCFGA: EGT Position */
\r
10864 #define DSD_CH_FCFGA_EGT_Msk (0x01UL << DSD_CH_FCFGA_EGT_Pos) /*!< DSD_CH FCFGA: EGT Mask */
\r
10865 #define DSD_CH_FCFGA_CFADCNT_Pos 24 /*!< DSD_CH FCFGA: CFADCNT Position */
\r
10866 #define DSD_CH_FCFGA_CFADCNT_Msk (0x000000ffUL << DSD_CH_FCFGA_CFADCNT_Pos) /*!< DSD_CH FCFGA: CFADCNT Mask */
\r
10868 /* -------------------------------- DSD_CH_IWCTR -------------------------------- */
\r
10869 #define DSD_CH_IWCTR_NVALCNT_Pos 0 /*!< DSD_CH IWCTR: NVALCNT Position */
\r
10870 #define DSD_CH_IWCTR_NVALCNT_Msk (0x3fUL << DSD_CH_IWCTR_NVALCNT_Pos) /*!< DSD_CH IWCTR: NVALCNT Mask */
\r
10871 #define DSD_CH_IWCTR_INTEN_Pos 7 /*!< DSD_CH IWCTR: INTEN Position */
\r
10872 #define DSD_CH_IWCTR_INTEN_Msk (0x01UL << DSD_CH_IWCTR_INTEN_Pos) /*!< DSD_CH IWCTR: INTEN Mask */
\r
10873 #define DSD_CH_IWCTR_REPCNT_Pos 8 /*!< DSD_CH IWCTR: REPCNT Position */
\r
10874 #define DSD_CH_IWCTR_REPCNT_Msk (0x0fUL << DSD_CH_IWCTR_REPCNT_Pos) /*!< DSD_CH IWCTR: REPCNT Mask */
\r
10875 #define DSD_CH_IWCTR_REPVAL_Pos 12 /*!< DSD_CH IWCTR: REPVAL Position */
\r
10876 #define DSD_CH_IWCTR_REPVAL_Msk (0x0fUL << DSD_CH_IWCTR_REPVAL_Pos) /*!< DSD_CH IWCTR: REPVAL Mask */
\r
10877 #define DSD_CH_IWCTR_NVALDIS_Pos 16 /*!< DSD_CH IWCTR: NVALDIS Position */
\r
10878 #define DSD_CH_IWCTR_NVALDIS_Msk (0x3fUL << DSD_CH_IWCTR_NVALDIS_Pos) /*!< DSD_CH IWCTR: NVALDIS Mask */
\r
10879 #define DSD_CH_IWCTR_IWS_Pos 23 /*!< DSD_CH IWCTR: IWS Position */
\r
10880 #define DSD_CH_IWCTR_IWS_Msk (0x01UL << DSD_CH_IWCTR_IWS_Pos) /*!< DSD_CH IWCTR: IWS Mask */
\r
10881 #define DSD_CH_IWCTR_NVALINT_Pos 24 /*!< DSD_CH IWCTR: NVALINT Position */
\r
10882 #define DSD_CH_IWCTR_NVALINT_Msk (0x3fUL << DSD_CH_IWCTR_NVALINT_Pos) /*!< DSD_CH IWCTR: NVALINT Mask */
\r
10884 /* ------------------------------- DSD_CH_BOUNDSEL ------------------------------ */
\r
10885 #define DSD_CH_BOUNDSEL_BOUNDARYL_Pos 0 /*!< DSD_CH BOUNDSEL: BOUNDARYL Position */
\r
10886 #define DSD_CH_BOUNDSEL_BOUNDARYL_Msk (0x0000ffffUL << DSD_CH_BOUNDSEL_BOUNDARYL_Pos) /*!< DSD_CH BOUNDSEL: BOUNDARYL Mask */
\r
10887 #define DSD_CH_BOUNDSEL_BOUNDARYU_Pos 16 /*!< DSD_CH BOUNDSEL: BOUNDARYU Position */
\r
10888 #define DSD_CH_BOUNDSEL_BOUNDARYU_Msk (0x0000ffffUL << DSD_CH_BOUNDSEL_BOUNDARYU_Pos) /*!< DSD_CH BOUNDSEL: BOUNDARYU Mask */
\r
10890 /* --------------------------------- DSD_CH_RESM -------------------------------- */
\r
10891 #define DSD_CH_RESM_RESULT_Pos 0 /*!< DSD_CH RESM: RESULT Position */
\r
10892 #define DSD_CH_RESM_RESULT_Msk (0x0000ffffUL << DSD_CH_RESM_RESULT_Pos) /*!< DSD_CH RESM: RESULT Mask */
\r
10894 /* --------------------------------- DSD_CH_OFFM -------------------------------- */
\r
10895 #define DSD_CH_OFFM_OFFSET_Pos 0 /*!< DSD_CH OFFM: OFFSET Position */
\r
10896 #define DSD_CH_OFFM_OFFSET_Msk (0x0000ffffUL << DSD_CH_OFFM_OFFSET_Pos) /*!< DSD_CH OFFM: OFFSET Mask */
\r
10898 /* --------------------------------- DSD_CH_RESA -------------------------------- */
\r
10899 #define DSD_CH_RESA_RESULT_Pos 0 /*!< DSD_CH RESA: RESULT Position */
\r
10900 #define DSD_CH_RESA_RESULT_Msk (0x0000ffffUL << DSD_CH_RESA_RESULT_Pos) /*!< DSD_CH RESA: RESULT Mask */
\r
10902 /* -------------------------------- DSD_CH_TSTMP -------------------------------- */
\r
10903 #define DSD_CH_TSTMP_RESULT_Pos 0 /*!< DSD_CH TSTMP: RESULT Position */
\r
10904 #define DSD_CH_TSTMP_RESULT_Msk (0x0000ffffUL << DSD_CH_TSTMP_RESULT_Pos) /*!< DSD_CH TSTMP: RESULT Mask */
\r
10905 #define DSD_CH_TSTMP_CFMDCNT_Pos 16 /*!< DSD_CH TSTMP: CFMDCNT Position */
\r
10906 #define DSD_CH_TSTMP_CFMDCNT_Msk (0x000000ffUL << DSD_CH_TSTMP_CFMDCNT_Pos) /*!< DSD_CH TSTMP: CFMDCNT Mask */
\r
10907 #define DSD_CH_TSTMP_NVALCNT_Pos 24 /*!< DSD_CH TSTMP: NVALCNT Position */
\r
10908 #define DSD_CH_TSTMP_NVALCNT_Msk (0x3fUL << DSD_CH_TSTMP_NVALCNT_Pos) /*!< DSD_CH TSTMP: NVALCNT Mask */
\r
10910 /* -------------------------------- DSD_CH_CGSYNC ------------------------------- */
\r
10911 #define DSD_CH_CGSYNC_SDCOUNT_Pos 0 /*!< DSD_CH CGSYNC: SDCOUNT Position */
\r
10912 #define DSD_CH_CGSYNC_SDCOUNT_Msk (0x000000ffUL << DSD_CH_CGSYNC_SDCOUNT_Pos) /*!< DSD_CH CGSYNC: SDCOUNT Mask */
\r
10913 #define DSD_CH_CGSYNC_SDCAP_Pos 8 /*!< DSD_CH CGSYNC: SDCAP Position */
\r
10914 #define DSD_CH_CGSYNC_SDCAP_Msk (0x000000ffUL << DSD_CH_CGSYNC_SDCAP_Pos) /*!< DSD_CH CGSYNC: SDCAP Mask */
\r
10915 #define DSD_CH_CGSYNC_SDPOS_Pos 16 /*!< DSD_CH CGSYNC: SDPOS Position */
\r
10916 #define DSD_CH_CGSYNC_SDPOS_Msk (0x000000ffUL << DSD_CH_CGSYNC_SDPOS_Pos) /*!< DSD_CH CGSYNC: SDPOS Mask */
\r
10917 #define DSD_CH_CGSYNC_SDNEG_Pos 24 /*!< DSD_CH CGSYNC: SDNEG Position */
\r
10918 #define DSD_CH_CGSYNC_SDNEG_Msk (0x000000ffUL << DSD_CH_CGSYNC_SDNEG_Pos) /*!< DSD_CH CGSYNC: SDNEG Mask */
\r
10920 /* ------------------------------- DSD_CH_RECTCFG ------------------------------- */
\r
10921 #define DSD_CH_RECTCFG_RFEN_Pos 0 /*!< DSD_CH RECTCFG: RFEN Position */
\r
10922 #define DSD_CH_RECTCFG_RFEN_Msk (0x01UL << DSD_CH_RECTCFG_RFEN_Pos) /*!< DSD_CH RECTCFG: RFEN Mask */
\r
10923 #define DSD_CH_RECTCFG_SSRC_Pos 4 /*!< DSD_CH RECTCFG: SSRC Position */
\r
10924 #define DSD_CH_RECTCFG_SSRC_Msk (0x03UL << DSD_CH_RECTCFG_SSRC_Pos) /*!< DSD_CH RECTCFG: SSRC Mask */
\r
10925 #define DSD_CH_RECTCFG_SDVAL_Pos 15 /*!< DSD_CH RECTCFG: SDVAL Position */
\r
10926 #define DSD_CH_RECTCFG_SDVAL_Msk (0x01UL << DSD_CH_RECTCFG_SDVAL_Pos) /*!< DSD_CH RECTCFG: SDVAL Mask */
\r
10927 #define DSD_CH_RECTCFG_SGNCS_Pos 30 /*!< DSD_CH RECTCFG: SGNCS Position */
\r
10928 #define DSD_CH_RECTCFG_SGNCS_Msk (0x01UL << DSD_CH_RECTCFG_SGNCS_Pos) /*!< DSD_CH RECTCFG: SGNCS Mask */
\r
10929 #define DSD_CH_RECTCFG_SGND_Pos 31 /*!< DSD_CH RECTCFG: SGND Position */
\r
10930 #define DSD_CH_RECTCFG_SGND_Msk (0x01UL << DSD_CH_RECTCFG_SGND_Pos) /*!< DSD_CH RECTCFG: SGND Mask */
\r
10933 /* ================================================================================ */
\r
10934 /* ================ struct 'DAC' Position & Mask ================ */
\r
10935 /* ================================================================================ */
\r
10938 /* ----------------------------------- DAC_ID ----------------------------------- */
\r
10939 #define DAC_ID_MODR_Pos 0 /*!< DAC ID: MODR Position */
\r
10940 #define DAC_ID_MODR_Msk (0x000000ffUL << DAC_ID_MODR_Pos) /*!< DAC ID: MODR Mask */
\r
10941 #define DAC_ID_MODT_Pos 8 /*!< DAC ID: MODT Position */
\r
10942 #define DAC_ID_MODT_Msk (0x000000ffUL << DAC_ID_MODT_Pos) /*!< DAC ID: MODT Mask */
\r
10943 #define DAC_ID_MODN_Pos 16 /*!< DAC ID: MODN Position */
\r
10944 #define DAC_ID_MODN_Msk (0x0000ffffUL << DAC_ID_MODN_Pos) /*!< DAC ID: MODN Mask */
\r
10946 /* -------------------------------- DAC_DAC0CFG0 -------------------------------- */
\r
10947 #define DAC_DAC0CFG0_FREQ_Pos 0 /*!< DAC DAC0CFG0: FREQ Position */
\r
10948 #define DAC_DAC0CFG0_FREQ_Msk (0x000fffffUL << DAC_DAC0CFG0_FREQ_Pos) /*!< DAC DAC0CFG0: FREQ Mask */
\r
10949 #define DAC_DAC0CFG0_MODE_Pos 20 /*!< DAC DAC0CFG0: MODE Position */
\r
10950 #define DAC_DAC0CFG0_MODE_Msk (0x07UL << DAC_DAC0CFG0_MODE_Pos) /*!< DAC DAC0CFG0: MODE Mask */
\r
10951 #define DAC_DAC0CFG0_SIGN_Pos 23 /*!< DAC DAC0CFG0: SIGN Position */
\r
10952 #define DAC_DAC0CFG0_SIGN_Msk (0x01UL << DAC_DAC0CFG0_SIGN_Pos) /*!< DAC DAC0CFG0: SIGN Mask */
\r
10953 #define DAC_DAC0CFG0_FIFOIND_Pos 24 /*!< DAC DAC0CFG0: FIFOIND Position */
\r
10954 #define DAC_DAC0CFG0_FIFOIND_Msk (0x03UL << DAC_DAC0CFG0_FIFOIND_Pos) /*!< DAC DAC0CFG0: FIFOIND Mask */
\r
10955 #define DAC_DAC0CFG0_FIFOEMP_Pos 26 /*!< DAC DAC0CFG0: FIFOEMP Position */
\r
10956 #define DAC_DAC0CFG0_FIFOEMP_Msk (0x01UL << DAC_DAC0CFG0_FIFOEMP_Pos) /*!< DAC DAC0CFG0: FIFOEMP Mask */
\r
10957 #define DAC_DAC0CFG0_FIFOFUL_Pos 27 /*!< DAC DAC0CFG0: FIFOFUL Position */
\r
10958 #define DAC_DAC0CFG0_FIFOFUL_Msk (0x01UL << DAC_DAC0CFG0_FIFOFUL_Pos) /*!< DAC DAC0CFG0: FIFOFUL Mask */
\r
10959 #define DAC_DAC0CFG0_SIGNEN_Pos 29 /*!< DAC DAC0CFG0: SIGNEN Position */
\r
10960 #define DAC_DAC0CFG0_SIGNEN_Msk (0x01UL << DAC_DAC0CFG0_SIGNEN_Pos) /*!< DAC DAC0CFG0: SIGNEN Mask */
\r
10961 #define DAC_DAC0CFG0_SREN_Pos 30 /*!< DAC DAC0CFG0: SREN Position */
\r
10962 #define DAC_DAC0CFG0_SREN_Msk (0x01UL << DAC_DAC0CFG0_SREN_Pos) /*!< DAC DAC0CFG0: SREN Mask */
\r
10963 #define DAC_DAC0CFG0_RUN_Pos 31 /*!< DAC DAC0CFG0: RUN Position */
\r
10964 #define DAC_DAC0CFG0_RUN_Msk (0x01UL << DAC_DAC0CFG0_RUN_Pos) /*!< DAC DAC0CFG0: RUN Mask */
\r
10966 /* -------------------------------- DAC_DAC0CFG1 -------------------------------- */
\r
10967 #define DAC_DAC0CFG1_SCALE_Pos 0 /*!< DAC DAC0CFG1: SCALE Position */
\r
10968 #define DAC_DAC0CFG1_SCALE_Msk (0x07UL << DAC_DAC0CFG1_SCALE_Pos) /*!< DAC DAC0CFG1: SCALE Mask */
\r
10969 #define DAC_DAC0CFG1_MULDIV_Pos 3 /*!< DAC DAC0CFG1: MULDIV Position */
\r
10970 #define DAC_DAC0CFG1_MULDIV_Msk (0x01UL << DAC_DAC0CFG1_MULDIV_Pos) /*!< DAC DAC0CFG1: MULDIV Mask */
\r
10971 #define DAC_DAC0CFG1_OFFS_Pos 4 /*!< DAC DAC0CFG1: OFFS Position */
\r
10972 #define DAC_DAC0CFG1_OFFS_Msk (0x000000ffUL << DAC_DAC0CFG1_OFFS_Pos) /*!< DAC DAC0CFG1: OFFS Mask */
\r
10973 #define DAC_DAC0CFG1_TRIGSEL_Pos 12 /*!< DAC DAC0CFG1: TRIGSEL Position */
\r
10974 #define DAC_DAC0CFG1_TRIGSEL_Msk (0x07UL << DAC_DAC0CFG1_TRIGSEL_Pos) /*!< DAC DAC0CFG1: TRIGSEL Mask */
\r
10975 #define DAC_DAC0CFG1_DATMOD_Pos 15 /*!< DAC DAC0CFG1: DATMOD Position */
\r
10976 #define DAC_DAC0CFG1_DATMOD_Msk (0x01UL << DAC_DAC0CFG1_DATMOD_Pos) /*!< DAC DAC0CFG1: DATMOD Mask */
\r
10977 #define DAC_DAC0CFG1_SWTRIG_Pos 16 /*!< DAC DAC0CFG1: SWTRIG Position */
\r
10978 #define DAC_DAC0CFG1_SWTRIG_Msk (0x01UL << DAC_DAC0CFG1_SWTRIG_Pos) /*!< DAC DAC0CFG1: SWTRIG Mask */
\r
10979 #define DAC_DAC0CFG1_TRIGMOD_Pos 17 /*!< DAC DAC0CFG1: TRIGMOD Position */
\r
10980 #define DAC_DAC0CFG1_TRIGMOD_Msk (0x03UL << DAC_DAC0CFG1_TRIGMOD_Pos) /*!< DAC DAC0CFG1: TRIGMOD Mask */
\r
10981 #define DAC_DAC0CFG1_ANACFG_Pos 19 /*!< DAC DAC0CFG1: ANACFG Position */
\r
10982 #define DAC_DAC0CFG1_ANACFG_Msk (0x1fUL << DAC_DAC0CFG1_ANACFG_Pos) /*!< DAC DAC0CFG1: ANACFG Mask */
\r
10983 #define DAC_DAC0CFG1_ANAEN_Pos 24 /*!< DAC DAC0CFG1: ANAEN Position */
\r
10984 #define DAC_DAC0CFG1_ANAEN_Msk (0x01UL << DAC_DAC0CFG1_ANAEN_Pos) /*!< DAC DAC0CFG1: ANAEN Mask */
\r
10985 #define DAC_DAC0CFG1_REFCFGL_Pos 28 /*!< DAC DAC0CFG1: REFCFGL Position */
\r
10986 #define DAC_DAC0CFG1_REFCFGL_Msk (0x0fUL << DAC_DAC0CFG1_REFCFGL_Pos) /*!< DAC DAC0CFG1: REFCFGL Mask */
\r
10988 /* -------------------------------- DAC_DAC1CFG0 -------------------------------- */
\r
10989 #define DAC_DAC1CFG0_FREQ_Pos 0 /*!< DAC DAC1CFG0: FREQ Position */
\r
10990 #define DAC_DAC1CFG0_FREQ_Msk (0x000fffffUL << DAC_DAC1CFG0_FREQ_Pos) /*!< DAC DAC1CFG0: FREQ Mask */
\r
10991 #define DAC_DAC1CFG0_MODE_Pos 20 /*!< DAC DAC1CFG0: MODE Position */
\r
10992 #define DAC_DAC1CFG0_MODE_Msk (0x07UL << DAC_DAC1CFG0_MODE_Pos) /*!< DAC DAC1CFG0: MODE Mask */
\r
10993 #define DAC_DAC1CFG0_SIGN_Pos 23 /*!< DAC DAC1CFG0: SIGN Position */
\r
10994 #define DAC_DAC1CFG0_SIGN_Msk (0x01UL << DAC_DAC1CFG0_SIGN_Pos) /*!< DAC DAC1CFG0: SIGN Mask */
\r
10995 #define DAC_DAC1CFG0_FIFOIND_Pos 24 /*!< DAC DAC1CFG0: FIFOIND Position */
\r
10996 #define DAC_DAC1CFG0_FIFOIND_Msk (0x03UL << DAC_DAC1CFG0_FIFOIND_Pos) /*!< DAC DAC1CFG0: FIFOIND Mask */
\r
10997 #define DAC_DAC1CFG0_FIFOEMP_Pos 26 /*!< DAC DAC1CFG0: FIFOEMP Position */
\r
10998 #define DAC_DAC1CFG0_FIFOEMP_Msk (0x01UL << DAC_DAC1CFG0_FIFOEMP_Pos) /*!< DAC DAC1CFG0: FIFOEMP Mask */
\r
10999 #define DAC_DAC1CFG0_FIFOFUL_Pos 27 /*!< DAC DAC1CFG0: FIFOFUL Position */
\r
11000 #define DAC_DAC1CFG0_FIFOFUL_Msk (0x01UL << DAC_DAC1CFG0_FIFOFUL_Pos) /*!< DAC DAC1CFG0: FIFOFUL Mask */
\r
11001 #define DAC_DAC1CFG0_SIGNEN_Pos 29 /*!< DAC DAC1CFG0: SIGNEN Position */
\r
11002 #define DAC_DAC1CFG0_SIGNEN_Msk (0x01UL << DAC_DAC1CFG0_SIGNEN_Pos) /*!< DAC DAC1CFG0: SIGNEN Mask */
\r
11003 #define DAC_DAC1CFG0_SREN_Pos 30 /*!< DAC DAC1CFG0: SREN Position */
\r
11004 #define DAC_DAC1CFG0_SREN_Msk (0x01UL << DAC_DAC1CFG0_SREN_Pos) /*!< DAC DAC1CFG0: SREN Mask */
\r
11005 #define DAC_DAC1CFG0_RUN_Pos 31 /*!< DAC DAC1CFG0: RUN Position */
\r
11006 #define DAC_DAC1CFG0_RUN_Msk (0x01UL << DAC_DAC1CFG0_RUN_Pos) /*!< DAC DAC1CFG0: RUN Mask */
\r
11008 /* -------------------------------- DAC_DAC1CFG1 -------------------------------- */
\r
11009 #define DAC_DAC1CFG1_SCALE_Pos 0 /*!< DAC DAC1CFG1: SCALE Position */
\r
11010 #define DAC_DAC1CFG1_SCALE_Msk (0x07UL << DAC_DAC1CFG1_SCALE_Pos) /*!< DAC DAC1CFG1: SCALE Mask */
\r
11011 #define DAC_DAC1CFG1_MULDIV_Pos 3 /*!< DAC DAC1CFG1: MULDIV Position */
\r
11012 #define DAC_DAC1CFG1_MULDIV_Msk (0x01UL << DAC_DAC1CFG1_MULDIV_Pos) /*!< DAC DAC1CFG1: MULDIV Mask */
\r
11013 #define DAC_DAC1CFG1_OFFS_Pos 4 /*!< DAC DAC1CFG1: OFFS Position */
\r
11014 #define DAC_DAC1CFG1_OFFS_Msk (0x000000ffUL << DAC_DAC1CFG1_OFFS_Pos) /*!< DAC DAC1CFG1: OFFS Mask */
\r
11015 #define DAC_DAC1CFG1_TRIGSEL_Pos 12 /*!< DAC DAC1CFG1: TRIGSEL Position */
\r
11016 #define DAC_DAC1CFG1_TRIGSEL_Msk (0x07UL << DAC_DAC1CFG1_TRIGSEL_Pos) /*!< DAC DAC1CFG1: TRIGSEL Mask */
\r
11017 #define DAC_DAC1CFG1_SWTRIG_Pos 16 /*!< DAC DAC1CFG1: SWTRIG Position */
\r
11018 #define DAC_DAC1CFG1_SWTRIG_Msk (0x01UL << DAC_DAC1CFG1_SWTRIG_Pos) /*!< DAC DAC1CFG1: SWTRIG Mask */
\r
11019 #define DAC_DAC1CFG1_TRIGMOD_Pos 17 /*!< DAC DAC1CFG1: TRIGMOD Position */
\r
11020 #define DAC_DAC1CFG1_TRIGMOD_Msk (0x03UL << DAC_DAC1CFG1_TRIGMOD_Pos) /*!< DAC DAC1CFG1: TRIGMOD Mask */
\r
11021 #define DAC_DAC1CFG1_ANACFG_Pos 19 /*!< DAC DAC1CFG1: ANACFG Position */
\r
11022 #define DAC_DAC1CFG1_ANACFG_Msk (0x1fUL << DAC_DAC1CFG1_ANACFG_Pos) /*!< DAC DAC1CFG1: ANACFG Mask */
\r
11023 #define DAC_DAC1CFG1_ANAEN_Pos 24 /*!< DAC DAC1CFG1: ANAEN Position */
\r
11024 #define DAC_DAC1CFG1_ANAEN_Msk (0x01UL << DAC_DAC1CFG1_ANAEN_Pos) /*!< DAC DAC1CFG1: ANAEN Mask */
\r
11025 #define DAC_DAC1CFG1_REFCFGH_Pos 28 /*!< DAC DAC1CFG1: REFCFGH Position */
\r
11026 #define DAC_DAC1CFG1_REFCFGH_Msk (0x0fUL << DAC_DAC1CFG1_REFCFGH_Pos) /*!< DAC DAC1CFG1: REFCFGH Mask */
\r
11028 /* -------------------------------- DAC_DAC0DATA -------------------------------- */
\r
11029 #define DAC_DAC0DATA_DATA0_Pos 0 /*!< DAC DAC0DATA: DATA0 Position */
\r
11030 #define DAC_DAC0DATA_DATA0_Msk (0x00000fffUL << DAC_DAC0DATA_DATA0_Pos) /*!< DAC DAC0DATA: DATA0 Mask */
\r
11032 /* -------------------------------- DAC_DAC1DATA -------------------------------- */
\r
11033 #define DAC_DAC1DATA_DATA1_Pos 0 /*!< DAC DAC1DATA: DATA1 Position */
\r
11034 #define DAC_DAC1DATA_DATA1_Msk (0x00000fffUL << DAC_DAC1DATA_DATA1_Pos) /*!< DAC DAC1DATA: DATA1 Mask */
\r
11036 /* -------------------------------- DAC_DAC01DATA ------------------------------- */
\r
11037 #define DAC_DAC01DATA_DATA0_Pos 0 /*!< DAC DAC01DATA: DATA0 Position */
\r
11038 #define DAC_DAC01DATA_DATA0_Msk (0x00000fffUL << DAC_DAC01DATA_DATA0_Pos) /*!< DAC DAC01DATA: DATA0 Mask */
\r
11039 #define DAC_DAC01DATA_DATA1_Pos 16 /*!< DAC DAC01DATA: DATA1 Position */
\r
11040 #define DAC_DAC01DATA_DATA1_Msk (0x00000fffUL << DAC_DAC01DATA_DATA1_Pos) /*!< DAC DAC01DATA: DATA1 Mask */
\r
11042 /* -------------------------------- DAC_DAC0PATL -------------------------------- */
\r
11043 #define DAC_DAC0PATL_PAT0_Pos 0 /*!< DAC DAC0PATL: PAT0 Position */
\r
11044 #define DAC_DAC0PATL_PAT0_Msk (0x1fUL << DAC_DAC0PATL_PAT0_Pos) /*!< DAC DAC0PATL: PAT0 Mask */
\r
11045 #define DAC_DAC0PATL_PAT1_Pos 5 /*!< DAC DAC0PATL: PAT1 Position */
\r
11046 #define DAC_DAC0PATL_PAT1_Msk (0x1fUL << DAC_DAC0PATL_PAT1_Pos) /*!< DAC DAC0PATL: PAT1 Mask */
\r
11047 #define DAC_DAC0PATL_PAT2_Pos 10 /*!< DAC DAC0PATL: PAT2 Position */
\r
11048 #define DAC_DAC0PATL_PAT2_Msk (0x1fUL << DAC_DAC0PATL_PAT2_Pos) /*!< DAC DAC0PATL: PAT2 Mask */
\r
11049 #define DAC_DAC0PATL_PAT3_Pos 15 /*!< DAC DAC0PATL: PAT3 Position */
\r
11050 #define DAC_DAC0PATL_PAT3_Msk (0x1fUL << DAC_DAC0PATL_PAT3_Pos) /*!< DAC DAC0PATL: PAT3 Mask */
\r
11051 #define DAC_DAC0PATL_PAT4_Pos 20 /*!< DAC DAC0PATL: PAT4 Position */
\r
11052 #define DAC_DAC0PATL_PAT4_Msk (0x1fUL << DAC_DAC0PATL_PAT4_Pos) /*!< DAC DAC0PATL: PAT4 Mask */
\r
11053 #define DAC_DAC0PATL_PAT5_Pos 25 /*!< DAC DAC0PATL: PAT5 Position */
\r
11054 #define DAC_DAC0PATL_PAT5_Msk (0x1fUL << DAC_DAC0PATL_PAT5_Pos) /*!< DAC DAC0PATL: PAT5 Mask */
\r
11056 /* -------------------------------- DAC_DAC0PATH -------------------------------- */
\r
11057 #define DAC_DAC0PATH_PAT6_Pos 0 /*!< DAC DAC0PATH: PAT6 Position */
\r
11058 #define DAC_DAC0PATH_PAT6_Msk (0x1fUL << DAC_DAC0PATH_PAT6_Pos) /*!< DAC DAC0PATH: PAT6 Mask */
\r
11059 #define DAC_DAC0PATH_PAT7_Pos 5 /*!< DAC DAC0PATH: PAT7 Position */
\r
11060 #define DAC_DAC0PATH_PAT7_Msk (0x1fUL << DAC_DAC0PATH_PAT7_Pos) /*!< DAC DAC0PATH: PAT7 Mask */
\r
11061 #define DAC_DAC0PATH_PAT8_Pos 10 /*!< DAC DAC0PATH: PAT8 Position */
\r
11062 #define DAC_DAC0PATH_PAT8_Msk (0x1fUL << DAC_DAC0PATH_PAT8_Pos) /*!< DAC DAC0PATH: PAT8 Mask */
\r
11064 /* -------------------------------- DAC_DAC1PATL -------------------------------- */
\r
11065 #define DAC_DAC1PATL_PAT0_Pos 0 /*!< DAC DAC1PATL: PAT0 Position */
\r
11066 #define DAC_DAC1PATL_PAT0_Msk (0x1fUL << DAC_DAC1PATL_PAT0_Pos) /*!< DAC DAC1PATL: PAT0 Mask */
\r
11067 #define DAC_DAC1PATL_PAT1_Pos 5 /*!< DAC DAC1PATL: PAT1 Position */
\r
11068 #define DAC_DAC1PATL_PAT1_Msk (0x1fUL << DAC_DAC1PATL_PAT1_Pos) /*!< DAC DAC1PATL: PAT1 Mask */
\r
11069 #define DAC_DAC1PATL_PAT2_Pos 10 /*!< DAC DAC1PATL: PAT2 Position */
\r
11070 #define DAC_DAC1PATL_PAT2_Msk (0x1fUL << DAC_DAC1PATL_PAT2_Pos) /*!< DAC DAC1PATL: PAT2 Mask */
\r
11071 #define DAC_DAC1PATL_PAT3_Pos 15 /*!< DAC DAC1PATL: PAT3 Position */
\r
11072 #define DAC_DAC1PATL_PAT3_Msk (0x1fUL << DAC_DAC1PATL_PAT3_Pos) /*!< DAC DAC1PATL: PAT3 Mask */
\r
11073 #define DAC_DAC1PATL_PAT4_Pos 20 /*!< DAC DAC1PATL: PAT4 Position */
\r
11074 #define DAC_DAC1PATL_PAT4_Msk (0x1fUL << DAC_DAC1PATL_PAT4_Pos) /*!< DAC DAC1PATL: PAT4 Mask */
\r
11075 #define DAC_DAC1PATL_PAT5_Pos 25 /*!< DAC DAC1PATL: PAT5 Position */
\r
11076 #define DAC_DAC1PATL_PAT5_Msk (0x1fUL << DAC_DAC1PATL_PAT5_Pos) /*!< DAC DAC1PATL: PAT5 Mask */
\r
11078 /* -------------------------------- DAC_DAC1PATH -------------------------------- */
\r
11079 #define DAC_DAC1PATH_PAT6_Pos 0 /*!< DAC DAC1PATH: PAT6 Position */
\r
11080 #define DAC_DAC1PATH_PAT6_Msk (0x1fUL << DAC_DAC1PATH_PAT6_Pos) /*!< DAC DAC1PATH: PAT6 Mask */
\r
11081 #define DAC_DAC1PATH_PAT7_Pos 5 /*!< DAC DAC1PATH: PAT7 Position */
\r
11082 #define DAC_DAC1PATH_PAT7_Msk (0x1fUL << DAC_DAC1PATH_PAT7_Pos) /*!< DAC DAC1PATH: PAT7 Mask */
\r
11083 #define DAC_DAC1PATH_PAT8_Pos 10 /*!< DAC DAC1PATH: PAT8 Position */
\r
11084 #define DAC_DAC1PATH_PAT8_Msk (0x1fUL << DAC_DAC1PATH_PAT8_Pos) /*!< DAC DAC1PATH: PAT8 Mask */
\r
11087 /* ================================================================================ */
\r
11088 /* ================ Group 'CCU4' Position & Mask ================ */
\r
11089 /* ================================================================================ */
\r
11092 /* --------------------------------- CCU4_GCTRL --------------------------------- */
\r
11093 #define CCU4_GCTRL_PRBC_Pos 0 /*!< CCU4 GCTRL: PRBC Position */
\r
11094 #define CCU4_GCTRL_PRBC_Msk (0x07UL << CCU4_GCTRL_PRBC_Pos) /*!< CCU4 GCTRL: PRBC Mask */
\r
11095 #define CCU4_GCTRL_PCIS_Pos 4 /*!< CCU4 GCTRL: PCIS Position */
\r
11096 #define CCU4_GCTRL_PCIS_Msk (0x03UL << CCU4_GCTRL_PCIS_Pos) /*!< CCU4 GCTRL: PCIS Mask */
\r
11097 #define CCU4_GCTRL_SUSCFG_Pos 8 /*!< CCU4 GCTRL: SUSCFG Position */
\r
11098 #define CCU4_GCTRL_SUSCFG_Msk (0x03UL << CCU4_GCTRL_SUSCFG_Pos) /*!< CCU4 GCTRL: SUSCFG Mask */
\r
11099 #define CCU4_GCTRL_MSE0_Pos 10 /*!< CCU4 GCTRL: MSE0 Position */
\r
11100 #define CCU4_GCTRL_MSE0_Msk (0x01UL << CCU4_GCTRL_MSE0_Pos) /*!< CCU4 GCTRL: MSE0 Mask */
\r
11101 #define CCU4_GCTRL_MSE1_Pos 11 /*!< CCU4 GCTRL: MSE1 Position */
\r
11102 #define CCU4_GCTRL_MSE1_Msk (0x01UL << CCU4_GCTRL_MSE1_Pos) /*!< CCU4 GCTRL: MSE1 Mask */
\r
11103 #define CCU4_GCTRL_MSE2_Pos 12 /*!< CCU4 GCTRL: MSE2 Position */
\r
11104 #define CCU4_GCTRL_MSE2_Msk (0x01UL << CCU4_GCTRL_MSE2_Pos) /*!< CCU4 GCTRL: MSE2 Mask */
\r
11105 #define CCU4_GCTRL_MSE3_Pos 13 /*!< CCU4 GCTRL: MSE3 Position */
\r
11106 #define CCU4_GCTRL_MSE3_Msk (0x01UL << CCU4_GCTRL_MSE3_Pos) /*!< CCU4 GCTRL: MSE3 Mask */
\r
11107 #define CCU4_GCTRL_MSDE_Pos 14 /*!< CCU4 GCTRL: MSDE Position */
\r
11108 #define CCU4_GCTRL_MSDE_Msk (0x03UL << CCU4_GCTRL_MSDE_Pos) /*!< CCU4 GCTRL: MSDE Mask */
\r
11110 /* --------------------------------- CCU4_GSTAT --------------------------------- */
\r
11111 #define CCU4_GSTAT_S0I_Pos 0 /*!< CCU4 GSTAT: S0I Position */
\r
11112 #define CCU4_GSTAT_S0I_Msk (0x01UL << CCU4_GSTAT_S0I_Pos) /*!< CCU4 GSTAT: S0I Mask */
\r
11113 #define CCU4_GSTAT_S1I_Pos 1 /*!< CCU4 GSTAT: S1I Position */
\r
11114 #define CCU4_GSTAT_S1I_Msk (0x01UL << CCU4_GSTAT_S1I_Pos) /*!< CCU4 GSTAT: S1I Mask */
\r
11115 #define CCU4_GSTAT_S2I_Pos 2 /*!< CCU4 GSTAT: S2I Position */
\r
11116 #define CCU4_GSTAT_S2I_Msk (0x01UL << CCU4_GSTAT_S2I_Pos) /*!< CCU4 GSTAT: S2I Mask */
\r
11117 #define CCU4_GSTAT_S3I_Pos 3 /*!< CCU4 GSTAT: S3I Position */
\r
11118 #define CCU4_GSTAT_S3I_Msk (0x01UL << CCU4_GSTAT_S3I_Pos) /*!< CCU4 GSTAT: S3I Mask */
\r
11119 #define CCU4_GSTAT_PRB_Pos 8 /*!< CCU4 GSTAT: PRB Position */
\r
11120 #define CCU4_GSTAT_PRB_Msk (0x01UL << CCU4_GSTAT_PRB_Pos) /*!< CCU4 GSTAT: PRB Mask */
\r
11122 /* --------------------------------- CCU4_GIDLS --------------------------------- */
\r
11123 #define CCU4_GIDLS_SS0I_Pos 0 /*!< CCU4 GIDLS: SS0I Position */
\r
11124 #define CCU4_GIDLS_SS0I_Msk (0x01UL << CCU4_GIDLS_SS0I_Pos) /*!< CCU4 GIDLS: SS0I Mask */
\r
11125 #define CCU4_GIDLS_SS1I_Pos 1 /*!< CCU4 GIDLS: SS1I Position */
\r
11126 #define CCU4_GIDLS_SS1I_Msk (0x01UL << CCU4_GIDLS_SS1I_Pos) /*!< CCU4 GIDLS: SS1I Mask */
\r
11127 #define CCU4_GIDLS_SS2I_Pos 2 /*!< CCU4 GIDLS: SS2I Position */
\r
11128 #define CCU4_GIDLS_SS2I_Msk (0x01UL << CCU4_GIDLS_SS2I_Pos) /*!< CCU4 GIDLS: SS2I Mask */
\r
11129 #define CCU4_GIDLS_SS3I_Pos 3 /*!< CCU4 GIDLS: SS3I Position */
\r
11130 #define CCU4_GIDLS_SS3I_Msk (0x01UL << CCU4_GIDLS_SS3I_Pos) /*!< CCU4 GIDLS: SS3I Mask */
\r
11131 #define CCU4_GIDLS_CPRB_Pos 8 /*!< CCU4 GIDLS: CPRB Position */
\r
11132 #define CCU4_GIDLS_CPRB_Msk (0x01UL << CCU4_GIDLS_CPRB_Pos) /*!< CCU4 GIDLS: CPRB Mask */
\r
11133 #define CCU4_GIDLS_PSIC_Pos 9 /*!< CCU4 GIDLS: PSIC Position */
\r
11134 #define CCU4_GIDLS_PSIC_Msk (0x01UL << CCU4_GIDLS_PSIC_Pos) /*!< CCU4 GIDLS: PSIC Mask */
\r
11136 /* --------------------------------- CCU4_GIDLC --------------------------------- */
\r
11137 #define CCU4_GIDLC_CS0I_Pos 0 /*!< CCU4 GIDLC: CS0I Position */
\r
11138 #define CCU4_GIDLC_CS0I_Msk (0x01UL << CCU4_GIDLC_CS0I_Pos) /*!< CCU4 GIDLC: CS0I Mask */
\r
11139 #define CCU4_GIDLC_CS1I_Pos 1 /*!< CCU4 GIDLC: CS1I Position */
\r
11140 #define CCU4_GIDLC_CS1I_Msk (0x01UL << CCU4_GIDLC_CS1I_Pos) /*!< CCU4 GIDLC: CS1I Mask */
\r
11141 #define CCU4_GIDLC_CS2I_Pos 2 /*!< CCU4 GIDLC: CS2I Position */
\r
11142 #define CCU4_GIDLC_CS2I_Msk (0x01UL << CCU4_GIDLC_CS2I_Pos) /*!< CCU4 GIDLC: CS2I Mask */
\r
11143 #define CCU4_GIDLC_CS3I_Pos 3 /*!< CCU4 GIDLC: CS3I Position */
\r
11144 #define CCU4_GIDLC_CS3I_Msk (0x01UL << CCU4_GIDLC_CS3I_Pos) /*!< CCU4 GIDLC: CS3I Mask */
\r
11145 #define CCU4_GIDLC_SPRB_Pos 8 /*!< CCU4 GIDLC: SPRB Position */
\r
11146 #define CCU4_GIDLC_SPRB_Msk (0x01UL << CCU4_GIDLC_SPRB_Pos) /*!< CCU4 GIDLC: SPRB Mask */
\r
11148 /* ---------------------------------- CCU4_GCSS --------------------------------- */
\r
11149 #define CCU4_GCSS_S0SE_Pos 0 /*!< CCU4 GCSS: S0SE Position */
\r
11150 #define CCU4_GCSS_S0SE_Msk (0x01UL << CCU4_GCSS_S0SE_Pos) /*!< CCU4 GCSS: S0SE Mask */
\r
11151 #define CCU4_GCSS_S0DSE_Pos 1 /*!< CCU4 GCSS: S0DSE Position */
\r
11152 #define CCU4_GCSS_S0DSE_Msk (0x01UL << CCU4_GCSS_S0DSE_Pos) /*!< CCU4 GCSS: S0DSE Mask */
\r
11153 #define CCU4_GCSS_S0PSE_Pos 2 /*!< CCU4 GCSS: S0PSE Position */
\r
11154 #define CCU4_GCSS_S0PSE_Msk (0x01UL << CCU4_GCSS_S0PSE_Pos) /*!< CCU4 GCSS: S0PSE Mask */
\r
11155 #define CCU4_GCSS_S1SE_Pos 4 /*!< CCU4 GCSS: S1SE Position */
\r
11156 #define CCU4_GCSS_S1SE_Msk (0x01UL << CCU4_GCSS_S1SE_Pos) /*!< CCU4 GCSS: S1SE Mask */
\r
11157 #define CCU4_GCSS_S1DSE_Pos 5 /*!< CCU4 GCSS: S1DSE Position */
\r
11158 #define CCU4_GCSS_S1DSE_Msk (0x01UL << CCU4_GCSS_S1DSE_Pos) /*!< CCU4 GCSS: S1DSE Mask */
\r
11159 #define CCU4_GCSS_S1PSE_Pos 6 /*!< CCU4 GCSS: S1PSE Position */
\r
11160 #define CCU4_GCSS_S1PSE_Msk (0x01UL << CCU4_GCSS_S1PSE_Pos) /*!< CCU4 GCSS: S1PSE Mask */
\r
11161 #define CCU4_GCSS_S2SE_Pos 8 /*!< CCU4 GCSS: S2SE Position */
\r
11162 #define CCU4_GCSS_S2SE_Msk (0x01UL << CCU4_GCSS_S2SE_Pos) /*!< CCU4 GCSS: S2SE Mask */
\r
11163 #define CCU4_GCSS_S2DSE_Pos 9 /*!< CCU4 GCSS: S2DSE Position */
\r
11164 #define CCU4_GCSS_S2DSE_Msk (0x01UL << CCU4_GCSS_S2DSE_Pos) /*!< CCU4 GCSS: S2DSE Mask */
\r
11165 #define CCU4_GCSS_S2PSE_Pos 10 /*!< CCU4 GCSS: S2PSE Position */
\r
11166 #define CCU4_GCSS_S2PSE_Msk (0x01UL << CCU4_GCSS_S2PSE_Pos) /*!< CCU4 GCSS: S2PSE Mask */
\r
11167 #define CCU4_GCSS_S3SE_Pos 12 /*!< CCU4 GCSS: S3SE Position */
\r
11168 #define CCU4_GCSS_S3SE_Msk (0x01UL << CCU4_GCSS_S3SE_Pos) /*!< CCU4 GCSS: S3SE Mask */
\r
11169 #define CCU4_GCSS_S3DSE_Pos 13 /*!< CCU4 GCSS: S3DSE Position */
\r
11170 #define CCU4_GCSS_S3DSE_Msk (0x01UL << CCU4_GCSS_S3DSE_Pos) /*!< CCU4 GCSS: S3DSE Mask */
\r
11171 #define CCU4_GCSS_S3PSE_Pos 14 /*!< CCU4 GCSS: S3PSE Position */
\r
11172 #define CCU4_GCSS_S3PSE_Msk (0x01UL << CCU4_GCSS_S3PSE_Pos) /*!< CCU4 GCSS: S3PSE Mask */
\r
11173 #define CCU4_GCSS_S0STS_Pos 16 /*!< CCU4 GCSS: S0STS Position */
\r
11174 #define CCU4_GCSS_S0STS_Msk (0x01UL << CCU4_GCSS_S0STS_Pos) /*!< CCU4 GCSS: S0STS Mask */
\r
11175 #define CCU4_GCSS_S1STS_Pos 17 /*!< CCU4 GCSS: S1STS Position */
\r
11176 #define CCU4_GCSS_S1STS_Msk (0x01UL << CCU4_GCSS_S1STS_Pos) /*!< CCU4 GCSS: S1STS Mask */
\r
11177 #define CCU4_GCSS_S2STS_Pos 18 /*!< CCU4 GCSS: S2STS Position */
\r
11178 #define CCU4_GCSS_S2STS_Msk (0x01UL << CCU4_GCSS_S2STS_Pos) /*!< CCU4 GCSS: S2STS Mask */
\r
11179 #define CCU4_GCSS_S3STS_Pos 19 /*!< CCU4 GCSS: S3STS Position */
\r
11180 #define CCU4_GCSS_S3STS_Msk (0x01UL << CCU4_GCSS_S3STS_Pos) /*!< CCU4 GCSS: S3STS Mask */
\r
11182 /* ---------------------------------- CCU4_GCSC --------------------------------- */
\r
11183 #define CCU4_GCSC_S0SC_Pos 0 /*!< CCU4 GCSC: S0SC Position */
\r
11184 #define CCU4_GCSC_S0SC_Msk (0x01UL << CCU4_GCSC_S0SC_Pos) /*!< CCU4 GCSC: S0SC Mask */
\r
11185 #define CCU4_GCSC_S0DSC_Pos 1 /*!< CCU4 GCSC: S0DSC Position */
\r
11186 #define CCU4_GCSC_S0DSC_Msk (0x01UL << CCU4_GCSC_S0DSC_Pos) /*!< CCU4 GCSC: S0DSC Mask */
\r
11187 #define CCU4_GCSC_S0PSC_Pos 2 /*!< CCU4 GCSC: S0PSC Position */
\r
11188 #define CCU4_GCSC_S0PSC_Msk (0x01UL << CCU4_GCSC_S0PSC_Pos) /*!< CCU4 GCSC: S0PSC Mask */
\r
11189 #define CCU4_GCSC_S1SC_Pos 4 /*!< CCU4 GCSC: S1SC Position */
\r
11190 #define CCU4_GCSC_S1SC_Msk (0x01UL << CCU4_GCSC_S1SC_Pos) /*!< CCU4 GCSC: S1SC Mask */
\r
11191 #define CCU4_GCSC_S1DSC_Pos 5 /*!< CCU4 GCSC: S1DSC Position */
\r
11192 #define CCU4_GCSC_S1DSC_Msk (0x01UL << CCU4_GCSC_S1DSC_Pos) /*!< CCU4 GCSC: S1DSC Mask */
\r
11193 #define CCU4_GCSC_S1PSC_Pos 6 /*!< CCU4 GCSC: S1PSC Position */
\r
11194 #define CCU4_GCSC_S1PSC_Msk (0x01UL << CCU4_GCSC_S1PSC_Pos) /*!< CCU4 GCSC: S1PSC Mask */
\r
11195 #define CCU4_GCSC_S2SC_Pos 8 /*!< CCU4 GCSC: S2SC Position */
\r
11196 #define CCU4_GCSC_S2SC_Msk (0x01UL << CCU4_GCSC_S2SC_Pos) /*!< CCU4 GCSC: S2SC Mask */
\r
11197 #define CCU4_GCSC_S2DSC_Pos 9 /*!< CCU4 GCSC: S2DSC Position */
\r
11198 #define CCU4_GCSC_S2DSC_Msk (0x01UL << CCU4_GCSC_S2DSC_Pos) /*!< CCU4 GCSC: S2DSC Mask */
\r
11199 #define CCU4_GCSC_S2PSC_Pos 10 /*!< CCU4 GCSC: S2PSC Position */
\r
11200 #define CCU4_GCSC_S2PSC_Msk (0x01UL << CCU4_GCSC_S2PSC_Pos) /*!< CCU4 GCSC: S2PSC Mask */
\r
11201 #define CCU4_GCSC_S3SC_Pos 12 /*!< CCU4 GCSC: S3SC Position */
\r
11202 #define CCU4_GCSC_S3SC_Msk (0x01UL << CCU4_GCSC_S3SC_Pos) /*!< CCU4 GCSC: S3SC Mask */
\r
11203 #define CCU4_GCSC_S3DSC_Pos 13 /*!< CCU4 GCSC: S3DSC Position */
\r
11204 #define CCU4_GCSC_S3DSC_Msk (0x01UL << CCU4_GCSC_S3DSC_Pos) /*!< CCU4 GCSC: S3DSC Mask */
\r
11205 #define CCU4_GCSC_S3PSC_Pos 14 /*!< CCU4 GCSC: S3PSC Position */
\r
11206 #define CCU4_GCSC_S3PSC_Msk (0x01UL << CCU4_GCSC_S3PSC_Pos) /*!< CCU4 GCSC: S3PSC Mask */
\r
11207 #define CCU4_GCSC_S0STC_Pos 16 /*!< CCU4 GCSC: S0STC Position */
\r
11208 #define CCU4_GCSC_S0STC_Msk (0x01UL << CCU4_GCSC_S0STC_Pos) /*!< CCU4 GCSC: S0STC Mask */
\r
11209 #define CCU4_GCSC_S1STC_Pos 17 /*!< CCU4 GCSC: S1STC Position */
\r
11210 #define CCU4_GCSC_S1STC_Msk (0x01UL << CCU4_GCSC_S1STC_Pos) /*!< CCU4 GCSC: S1STC Mask */
\r
11211 #define CCU4_GCSC_S2STC_Pos 18 /*!< CCU4 GCSC: S2STC Position */
\r
11212 #define CCU4_GCSC_S2STC_Msk (0x01UL << CCU4_GCSC_S2STC_Pos) /*!< CCU4 GCSC: S2STC Mask */
\r
11213 #define CCU4_GCSC_S3STC_Pos 19 /*!< CCU4 GCSC: S3STC Position */
\r
11214 #define CCU4_GCSC_S3STC_Msk (0x01UL << CCU4_GCSC_S3STC_Pos) /*!< CCU4 GCSC: S3STC Mask */
\r
11216 /* ---------------------------------- CCU4_GCST --------------------------------- */
\r
11217 #define CCU4_GCST_S0SS_Pos 0 /*!< CCU4 GCST: S0SS Position */
\r
11218 #define CCU4_GCST_S0SS_Msk (0x01UL << CCU4_GCST_S0SS_Pos) /*!< CCU4 GCST: S0SS Mask */
\r
11219 #define CCU4_GCST_S0DSS_Pos 1 /*!< CCU4 GCST: S0DSS Position */
\r
11220 #define CCU4_GCST_S0DSS_Msk (0x01UL << CCU4_GCST_S0DSS_Pos) /*!< CCU4 GCST: S0DSS Mask */
\r
11221 #define CCU4_GCST_S0PSS_Pos 2 /*!< CCU4 GCST: S0PSS Position */
\r
11222 #define CCU4_GCST_S0PSS_Msk (0x01UL << CCU4_GCST_S0PSS_Pos) /*!< CCU4 GCST: S0PSS Mask */
\r
11223 #define CCU4_GCST_S1SS_Pos 4 /*!< CCU4 GCST: S1SS Position */
\r
11224 #define CCU4_GCST_S1SS_Msk (0x01UL << CCU4_GCST_S1SS_Pos) /*!< CCU4 GCST: S1SS Mask */
\r
11225 #define CCU4_GCST_S1DSS_Pos 5 /*!< CCU4 GCST: S1DSS Position */
\r
11226 #define CCU4_GCST_S1DSS_Msk (0x01UL << CCU4_GCST_S1DSS_Pos) /*!< CCU4 GCST: S1DSS Mask */
\r
11227 #define CCU4_GCST_S1PSS_Pos 6 /*!< CCU4 GCST: S1PSS Position */
\r
11228 #define CCU4_GCST_S1PSS_Msk (0x01UL << CCU4_GCST_S1PSS_Pos) /*!< CCU4 GCST: S1PSS Mask */
\r
11229 #define CCU4_GCST_S2SS_Pos 8 /*!< CCU4 GCST: S2SS Position */
\r
11230 #define CCU4_GCST_S2SS_Msk (0x01UL << CCU4_GCST_S2SS_Pos) /*!< CCU4 GCST: S2SS Mask */
\r
11231 #define CCU4_GCST_S2DSS_Pos 9 /*!< CCU4 GCST: S2DSS Position */
\r
11232 #define CCU4_GCST_S2DSS_Msk (0x01UL << CCU4_GCST_S2DSS_Pos) /*!< CCU4 GCST: S2DSS Mask */
\r
11233 #define CCU4_GCST_S2PSS_Pos 10 /*!< CCU4 GCST: S2PSS Position */
\r
11234 #define CCU4_GCST_S2PSS_Msk (0x01UL << CCU4_GCST_S2PSS_Pos) /*!< CCU4 GCST: S2PSS Mask */
\r
11235 #define CCU4_GCST_S3SS_Pos 12 /*!< CCU4 GCST: S3SS Position */
\r
11236 #define CCU4_GCST_S3SS_Msk (0x01UL << CCU4_GCST_S3SS_Pos) /*!< CCU4 GCST: S3SS Mask */
\r
11237 #define CCU4_GCST_S3DSS_Pos 13 /*!< CCU4 GCST: S3DSS Position */
\r
11238 #define CCU4_GCST_S3DSS_Msk (0x01UL << CCU4_GCST_S3DSS_Pos) /*!< CCU4 GCST: S3DSS Mask */
\r
11239 #define CCU4_GCST_S3PSS_Pos 14 /*!< CCU4 GCST: S3PSS Position */
\r
11240 #define CCU4_GCST_S3PSS_Msk (0x01UL << CCU4_GCST_S3PSS_Pos) /*!< CCU4 GCST: S3PSS Mask */
\r
11241 #define CCU4_GCST_CC40ST_Pos 16 /*!< CCU4 GCST: CC40ST Position */
\r
11242 #define CCU4_GCST_CC40ST_Msk (0x01UL << CCU4_GCST_CC40ST_Pos) /*!< CCU4 GCST: CC40ST Mask */
\r
11243 #define CCU4_GCST_CC41ST_Pos 17 /*!< CCU4 GCST: CC41ST Position */
\r
11244 #define CCU4_GCST_CC41ST_Msk (0x01UL << CCU4_GCST_CC41ST_Pos) /*!< CCU4 GCST: CC41ST Mask */
\r
11245 #define CCU4_GCST_CC42ST_Pos 18 /*!< CCU4 GCST: CC42ST Position */
\r
11246 #define CCU4_GCST_CC42ST_Msk (0x01UL << CCU4_GCST_CC42ST_Pos) /*!< CCU4 GCST: CC42ST Mask */
\r
11247 #define CCU4_GCST_CC43ST_Pos 19 /*!< CCU4 GCST: CC43ST Position */
\r
11248 #define CCU4_GCST_CC43ST_Msk (0x01UL << CCU4_GCST_CC43ST_Pos) /*!< CCU4 GCST: CC43ST Mask */
\r
11250 /* ---------------------------------- CCU4_ECRD --------------------------------- */
\r
11251 #define CCU4_ECRD_CAPV_Pos 0 /*!< CCU4 ECRD: CAPV Position */
\r
11252 #define CCU4_ECRD_CAPV_Msk (0x0000ffffUL << CCU4_ECRD_CAPV_Pos) /*!< CCU4 ECRD: CAPV Mask */
\r
11253 #define CCU4_ECRD_FPCV_Pos 16 /*!< CCU4 ECRD: FPCV Position */
\r
11254 #define CCU4_ECRD_FPCV_Msk (0x0fUL << CCU4_ECRD_FPCV_Pos) /*!< CCU4 ECRD: FPCV Mask */
\r
11255 #define CCU4_ECRD_SPTR_Pos 20 /*!< CCU4 ECRD: SPTR Position */
\r
11256 #define CCU4_ECRD_SPTR_Msk (0x03UL << CCU4_ECRD_SPTR_Pos) /*!< CCU4 ECRD: SPTR Mask */
\r
11257 #define CCU4_ECRD_VPTR_Pos 22 /*!< CCU4 ECRD: VPTR Position */
\r
11258 #define CCU4_ECRD_VPTR_Msk (0x03UL << CCU4_ECRD_VPTR_Pos) /*!< CCU4 ECRD: VPTR Mask */
\r
11259 #define CCU4_ECRD_FFL_Pos 24 /*!< CCU4 ECRD: FFL Position */
\r
11260 #define CCU4_ECRD_FFL_Msk (0x01UL << CCU4_ECRD_FFL_Pos) /*!< CCU4 ECRD: FFL Mask */
\r
11262 /* ---------------------------------- CCU4_MIDR --------------------------------- */
\r
11263 #define CCU4_MIDR_MODR_Pos 0 /*!< CCU4 MIDR: MODR Position */
\r
11264 #define CCU4_MIDR_MODR_Msk (0x000000ffUL << CCU4_MIDR_MODR_Pos) /*!< CCU4 MIDR: MODR Mask */
\r
11265 #define CCU4_MIDR_MODT_Pos 8 /*!< CCU4 MIDR: MODT Position */
\r
11266 #define CCU4_MIDR_MODT_Msk (0x000000ffUL << CCU4_MIDR_MODT_Pos) /*!< CCU4 MIDR: MODT Mask */
\r
11267 #define CCU4_MIDR_MODN_Pos 16 /*!< CCU4 MIDR: MODN Position */
\r
11268 #define CCU4_MIDR_MODN_Msk (0x0000ffffUL << CCU4_MIDR_MODN_Pos) /*!< CCU4 MIDR: MODN Mask */
\r
11271 /* ================================================================================ */
\r
11272 /* ================ Group 'CCU4_CC4' Position & Mask ================ */
\r
11273 /* ================================================================================ */
\r
11276 /* -------------------------------- CCU4_CC4_INS -------------------------------- */
\r
11277 #define CCU4_CC4_INS_EV0IS_Pos 0 /*!< CCU4_CC4 INS: EV0IS Position */
\r
11278 #define CCU4_CC4_INS_EV0IS_Msk (0x0fUL << CCU4_CC4_INS_EV0IS_Pos) /*!< CCU4_CC4 INS: EV0IS Mask */
\r
11279 #define CCU4_CC4_INS_EV1IS_Pos 4 /*!< CCU4_CC4 INS: EV1IS Position */
\r
11280 #define CCU4_CC4_INS_EV1IS_Msk (0x0fUL << CCU4_CC4_INS_EV1IS_Pos) /*!< CCU4_CC4 INS: EV1IS Mask */
\r
11281 #define CCU4_CC4_INS_EV2IS_Pos 8 /*!< CCU4_CC4 INS: EV2IS Position */
\r
11282 #define CCU4_CC4_INS_EV2IS_Msk (0x0fUL << CCU4_CC4_INS_EV2IS_Pos) /*!< CCU4_CC4 INS: EV2IS Mask */
\r
11283 #define CCU4_CC4_INS_EV0EM_Pos 16 /*!< CCU4_CC4 INS: EV0EM Position */
\r
11284 #define CCU4_CC4_INS_EV0EM_Msk (0x03UL << CCU4_CC4_INS_EV0EM_Pos) /*!< CCU4_CC4 INS: EV0EM Mask */
\r
11285 #define CCU4_CC4_INS_EV1EM_Pos 18 /*!< CCU4_CC4 INS: EV1EM Position */
\r
11286 #define CCU4_CC4_INS_EV1EM_Msk (0x03UL << CCU4_CC4_INS_EV1EM_Pos) /*!< CCU4_CC4 INS: EV1EM Mask */
\r
11287 #define CCU4_CC4_INS_EV2EM_Pos 20 /*!< CCU4_CC4 INS: EV2EM Position */
\r
11288 #define CCU4_CC4_INS_EV2EM_Msk (0x03UL << CCU4_CC4_INS_EV2EM_Pos) /*!< CCU4_CC4 INS: EV2EM Mask */
\r
11289 #define CCU4_CC4_INS_EV0LM_Pos 22 /*!< CCU4_CC4 INS: EV0LM Position */
\r
11290 #define CCU4_CC4_INS_EV0LM_Msk (0x01UL << CCU4_CC4_INS_EV0LM_Pos) /*!< CCU4_CC4 INS: EV0LM Mask */
\r
11291 #define CCU4_CC4_INS_EV1LM_Pos 23 /*!< CCU4_CC4 INS: EV1LM Position */
\r
11292 #define CCU4_CC4_INS_EV1LM_Msk (0x01UL << CCU4_CC4_INS_EV1LM_Pos) /*!< CCU4_CC4 INS: EV1LM Mask */
\r
11293 #define CCU4_CC4_INS_EV2LM_Pos 24 /*!< CCU4_CC4 INS: EV2LM Position */
\r
11294 #define CCU4_CC4_INS_EV2LM_Msk (0x01UL << CCU4_CC4_INS_EV2LM_Pos) /*!< CCU4_CC4 INS: EV2LM Mask */
\r
11295 #define CCU4_CC4_INS_LPF0M_Pos 25 /*!< CCU4_CC4 INS: LPF0M Position */
\r
11296 #define CCU4_CC4_INS_LPF0M_Msk (0x03UL << CCU4_CC4_INS_LPF0M_Pos) /*!< CCU4_CC4 INS: LPF0M Mask */
\r
11297 #define CCU4_CC4_INS_LPF1M_Pos 27 /*!< CCU4_CC4 INS: LPF1M Position */
\r
11298 #define CCU4_CC4_INS_LPF1M_Msk (0x03UL << CCU4_CC4_INS_LPF1M_Pos) /*!< CCU4_CC4 INS: LPF1M Mask */
\r
11299 #define CCU4_CC4_INS_LPF2M_Pos 29 /*!< CCU4_CC4 INS: LPF2M Position */
\r
11300 #define CCU4_CC4_INS_LPF2M_Msk (0x03UL << CCU4_CC4_INS_LPF2M_Pos) /*!< CCU4_CC4 INS: LPF2M Mask */
\r
11302 /* -------------------------------- CCU4_CC4_CMC -------------------------------- */
\r
11303 #define CCU4_CC4_CMC_STRTS_Pos 0 /*!< CCU4_CC4 CMC: STRTS Position */
\r
11304 #define CCU4_CC4_CMC_STRTS_Msk (0x03UL << CCU4_CC4_CMC_STRTS_Pos) /*!< CCU4_CC4 CMC: STRTS Mask */
\r
11305 #define CCU4_CC4_CMC_ENDS_Pos 2 /*!< CCU4_CC4 CMC: ENDS Position */
\r
11306 #define CCU4_CC4_CMC_ENDS_Msk (0x03UL << CCU4_CC4_CMC_ENDS_Pos) /*!< CCU4_CC4 CMC: ENDS Mask */
\r
11307 #define CCU4_CC4_CMC_CAP0S_Pos 4 /*!< CCU4_CC4 CMC: CAP0S Position */
\r
11308 #define CCU4_CC4_CMC_CAP0S_Msk (0x03UL << CCU4_CC4_CMC_CAP0S_Pos) /*!< CCU4_CC4 CMC: CAP0S Mask */
\r
11309 #define CCU4_CC4_CMC_CAP1S_Pos 6 /*!< CCU4_CC4 CMC: CAP1S Position */
\r
11310 #define CCU4_CC4_CMC_CAP1S_Msk (0x03UL << CCU4_CC4_CMC_CAP1S_Pos) /*!< CCU4_CC4 CMC: CAP1S Mask */
\r
11311 #define CCU4_CC4_CMC_GATES_Pos 8 /*!< CCU4_CC4 CMC: GATES Position */
\r
11312 #define CCU4_CC4_CMC_GATES_Msk (0x03UL << CCU4_CC4_CMC_GATES_Pos) /*!< CCU4_CC4 CMC: GATES Mask */
\r
11313 #define CCU4_CC4_CMC_UDS_Pos 10 /*!< CCU4_CC4 CMC: UDS Position */
\r
11314 #define CCU4_CC4_CMC_UDS_Msk (0x03UL << CCU4_CC4_CMC_UDS_Pos) /*!< CCU4_CC4 CMC: UDS Mask */
\r
11315 #define CCU4_CC4_CMC_LDS_Pos 12 /*!< CCU4_CC4 CMC: LDS Position */
\r
11316 #define CCU4_CC4_CMC_LDS_Msk (0x03UL << CCU4_CC4_CMC_LDS_Pos) /*!< CCU4_CC4 CMC: LDS Mask */
\r
11317 #define CCU4_CC4_CMC_CNTS_Pos 14 /*!< CCU4_CC4 CMC: CNTS Position */
\r
11318 #define CCU4_CC4_CMC_CNTS_Msk (0x03UL << CCU4_CC4_CMC_CNTS_Pos) /*!< CCU4_CC4 CMC: CNTS Mask */
\r
11319 #define CCU4_CC4_CMC_OFS_Pos 16 /*!< CCU4_CC4 CMC: OFS Position */
\r
11320 #define CCU4_CC4_CMC_OFS_Msk (0x01UL << CCU4_CC4_CMC_OFS_Pos) /*!< CCU4_CC4 CMC: OFS Mask */
\r
11321 #define CCU4_CC4_CMC_TS_Pos 17 /*!< CCU4_CC4 CMC: TS Position */
\r
11322 #define CCU4_CC4_CMC_TS_Msk (0x01UL << CCU4_CC4_CMC_TS_Pos) /*!< CCU4_CC4 CMC: TS Mask */
\r
11323 #define CCU4_CC4_CMC_MOS_Pos 18 /*!< CCU4_CC4 CMC: MOS Position */
\r
11324 #define CCU4_CC4_CMC_MOS_Msk (0x03UL << CCU4_CC4_CMC_MOS_Pos) /*!< CCU4_CC4 CMC: MOS Mask */
\r
11325 #define CCU4_CC4_CMC_TCE_Pos 20 /*!< CCU4_CC4 CMC: TCE Position */
\r
11326 #define CCU4_CC4_CMC_TCE_Msk (0x01UL << CCU4_CC4_CMC_TCE_Pos) /*!< CCU4_CC4 CMC: TCE Mask */
\r
11328 /* -------------------------------- CCU4_CC4_TCST ------------------------------- */
\r
11329 #define CCU4_CC4_TCST_TRB_Pos 0 /*!< CCU4_CC4 TCST: TRB Position */
\r
11330 #define CCU4_CC4_TCST_TRB_Msk (0x01UL << CCU4_CC4_TCST_TRB_Pos) /*!< CCU4_CC4 TCST: TRB Mask */
\r
11331 #define CCU4_CC4_TCST_CDIR_Pos 1 /*!< CCU4_CC4 TCST: CDIR Position */
\r
11332 #define CCU4_CC4_TCST_CDIR_Msk (0x01UL << CCU4_CC4_TCST_CDIR_Pos) /*!< CCU4_CC4 TCST: CDIR Mask */
\r
11334 /* ------------------------------- CCU4_CC4_TCSET ------------------------------- */
\r
11335 #define CCU4_CC4_TCSET_TRBS_Pos 0 /*!< CCU4_CC4 TCSET: TRBS Position */
\r
11336 #define CCU4_CC4_TCSET_TRBS_Msk (0x01UL << CCU4_CC4_TCSET_TRBS_Pos) /*!< CCU4_CC4 TCSET: TRBS Mask */
\r
11338 /* ------------------------------- CCU4_CC4_TCCLR ------------------------------- */
\r
11339 #define CCU4_CC4_TCCLR_TRBC_Pos 0 /*!< CCU4_CC4 TCCLR: TRBC Position */
\r
11340 #define CCU4_CC4_TCCLR_TRBC_Msk (0x01UL << CCU4_CC4_TCCLR_TRBC_Pos) /*!< CCU4_CC4 TCCLR: TRBC Mask */
\r
11341 #define CCU4_CC4_TCCLR_TCC_Pos 1 /*!< CCU4_CC4 TCCLR: TCC Position */
\r
11342 #define CCU4_CC4_TCCLR_TCC_Msk (0x01UL << CCU4_CC4_TCCLR_TCC_Pos) /*!< CCU4_CC4 TCCLR: TCC Mask */
\r
11343 #define CCU4_CC4_TCCLR_DITC_Pos 2 /*!< CCU4_CC4 TCCLR: DITC Position */
\r
11344 #define CCU4_CC4_TCCLR_DITC_Msk (0x01UL << CCU4_CC4_TCCLR_DITC_Pos) /*!< CCU4_CC4 TCCLR: DITC Mask */
\r
11346 /* --------------------------------- CCU4_CC4_TC -------------------------------- */
\r
11347 #define CCU4_CC4_TC_TCM_Pos 0 /*!< CCU4_CC4 TC: TCM Position */
\r
11348 #define CCU4_CC4_TC_TCM_Msk (0x01UL << CCU4_CC4_TC_TCM_Pos) /*!< CCU4_CC4 TC: TCM Mask */
\r
11349 #define CCU4_CC4_TC_TSSM_Pos 1 /*!< CCU4_CC4 TC: TSSM Position */
\r
11350 #define CCU4_CC4_TC_TSSM_Msk (0x01UL << CCU4_CC4_TC_TSSM_Pos) /*!< CCU4_CC4 TC: TSSM Mask */
\r
11351 #define CCU4_CC4_TC_CLST_Pos 2 /*!< CCU4_CC4 TC: CLST Position */
\r
11352 #define CCU4_CC4_TC_CLST_Msk (0x01UL << CCU4_CC4_TC_CLST_Pos) /*!< CCU4_CC4 TC: CLST Mask */
\r
11353 #define CCU4_CC4_TC_CMOD_Pos 3 /*!< CCU4_CC4 TC: CMOD Position */
\r
11354 #define CCU4_CC4_TC_CMOD_Msk (0x01UL << CCU4_CC4_TC_CMOD_Pos) /*!< CCU4_CC4 TC: CMOD Mask */
\r
11355 #define CCU4_CC4_TC_ECM_Pos 4 /*!< CCU4_CC4 TC: ECM Position */
\r
11356 #define CCU4_CC4_TC_ECM_Msk (0x01UL << CCU4_CC4_TC_ECM_Pos) /*!< CCU4_CC4 TC: ECM Mask */
\r
11357 #define CCU4_CC4_TC_CAPC_Pos 5 /*!< CCU4_CC4 TC: CAPC Position */
\r
11358 #define CCU4_CC4_TC_CAPC_Msk (0x03UL << CCU4_CC4_TC_CAPC_Pos) /*!< CCU4_CC4 TC: CAPC Mask */
\r
11359 #define CCU4_CC4_TC_ENDM_Pos 8 /*!< CCU4_CC4 TC: ENDM Position */
\r
11360 #define CCU4_CC4_TC_ENDM_Msk (0x03UL << CCU4_CC4_TC_ENDM_Pos) /*!< CCU4_CC4 TC: ENDM Mask */
\r
11361 #define CCU4_CC4_TC_STRM_Pos 10 /*!< CCU4_CC4 TC: STRM Position */
\r
11362 #define CCU4_CC4_TC_STRM_Msk (0x01UL << CCU4_CC4_TC_STRM_Pos) /*!< CCU4_CC4 TC: STRM Mask */
\r
11363 #define CCU4_CC4_TC_SCE_Pos 11 /*!< CCU4_CC4 TC: SCE Position */
\r
11364 #define CCU4_CC4_TC_SCE_Msk (0x01UL << CCU4_CC4_TC_SCE_Pos) /*!< CCU4_CC4 TC: SCE Mask */
\r
11365 #define CCU4_CC4_TC_CCS_Pos 12 /*!< CCU4_CC4 TC: CCS Position */
\r
11366 #define CCU4_CC4_TC_CCS_Msk (0x01UL << CCU4_CC4_TC_CCS_Pos) /*!< CCU4_CC4 TC: CCS Mask */
\r
11367 #define CCU4_CC4_TC_DITHE_Pos 13 /*!< CCU4_CC4 TC: DITHE Position */
\r
11368 #define CCU4_CC4_TC_DITHE_Msk (0x03UL << CCU4_CC4_TC_DITHE_Pos) /*!< CCU4_CC4 TC: DITHE Mask */
\r
11369 #define CCU4_CC4_TC_DIM_Pos 15 /*!< CCU4_CC4 TC: DIM Position */
\r
11370 #define CCU4_CC4_TC_DIM_Msk (0x01UL << CCU4_CC4_TC_DIM_Pos) /*!< CCU4_CC4 TC: DIM Mask */
\r
11371 #define CCU4_CC4_TC_FPE_Pos 16 /*!< CCU4_CC4 TC: FPE Position */
\r
11372 #define CCU4_CC4_TC_FPE_Msk (0x01UL << CCU4_CC4_TC_FPE_Pos) /*!< CCU4_CC4 TC: FPE Mask */
\r
11373 #define CCU4_CC4_TC_TRAPE_Pos 17 /*!< CCU4_CC4 TC: TRAPE Position */
\r
11374 #define CCU4_CC4_TC_TRAPE_Msk (0x01UL << CCU4_CC4_TC_TRAPE_Pos) /*!< CCU4_CC4 TC: TRAPE Mask */
\r
11375 #define CCU4_CC4_TC_TRPSE_Pos 21 /*!< CCU4_CC4 TC: TRPSE Position */
\r
11376 #define CCU4_CC4_TC_TRPSE_Msk (0x01UL << CCU4_CC4_TC_TRPSE_Pos) /*!< CCU4_CC4 TC: TRPSE Mask */
\r
11377 #define CCU4_CC4_TC_TRPSW_Pos 22 /*!< CCU4_CC4 TC: TRPSW Position */
\r
11378 #define CCU4_CC4_TC_TRPSW_Msk (0x01UL << CCU4_CC4_TC_TRPSW_Pos) /*!< CCU4_CC4 TC: TRPSW Mask */
\r
11379 #define CCU4_CC4_TC_EMS_Pos 23 /*!< CCU4_CC4 TC: EMS Position */
\r
11380 #define CCU4_CC4_TC_EMS_Msk (0x01UL << CCU4_CC4_TC_EMS_Pos) /*!< CCU4_CC4 TC: EMS Mask */
\r
11381 #define CCU4_CC4_TC_EMT_Pos 24 /*!< CCU4_CC4 TC: EMT Position */
\r
11382 #define CCU4_CC4_TC_EMT_Msk (0x01UL << CCU4_CC4_TC_EMT_Pos) /*!< CCU4_CC4 TC: EMT Mask */
\r
11383 #define CCU4_CC4_TC_MCME_Pos 25 /*!< CCU4_CC4 TC: MCME Position */
\r
11384 #define CCU4_CC4_TC_MCME_Msk (0x01UL << CCU4_CC4_TC_MCME_Pos) /*!< CCU4_CC4 TC: MCME Mask */
\r
11386 /* -------------------------------- CCU4_CC4_PSL -------------------------------- */
\r
11387 #define CCU4_CC4_PSL_PSL_Pos 0 /*!< CCU4_CC4 PSL: PSL Position */
\r
11388 #define CCU4_CC4_PSL_PSL_Msk (0x01UL << CCU4_CC4_PSL_PSL_Pos) /*!< CCU4_CC4 PSL: PSL Mask */
\r
11390 /* -------------------------------- CCU4_CC4_DIT -------------------------------- */
\r
11391 #define CCU4_CC4_DIT_DCV_Pos 0 /*!< CCU4_CC4 DIT: DCV Position */
\r
11392 #define CCU4_CC4_DIT_DCV_Msk (0x0fUL << CCU4_CC4_DIT_DCV_Pos) /*!< CCU4_CC4 DIT: DCV Mask */
\r
11393 #define CCU4_CC4_DIT_DCNT_Pos 8 /*!< CCU4_CC4 DIT: DCNT Position */
\r
11394 #define CCU4_CC4_DIT_DCNT_Msk (0x0fUL << CCU4_CC4_DIT_DCNT_Pos) /*!< CCU4_CC4 DIT: DCNT Mask */
\r
11396 /* -------------------------------- CCU4_CC4_DITS ------------------------------- */
\r
11397 #define CCU4_CC4_DITS_DCVS_Pos 0 /*!< CCU4_CC4 DITS: DCVS Position */
\r
11398 #define CCU4_CC4_DITS_DCVS_Msk (0x0fUL << CCU4_CC4_DITS_DCVS_Pos) /*!< CCU4_CC4 DITS: DCVS Mask */
\r
11400 /* -------------------------------- CCU4_CC4_PSC -------------------------------- */
\r
11401 #define CCU4_CC4_PSC_PSIV_Pos 0 /*!< CCU4_CC4 PSC: PSIV Position */
\r
11402 #define CCU4_CC4_PSC_PSIV_Msk (0x0fUL << CCU4_CC4_PSC_PSIV_Pos) /*!< CCU4_CC4 PSC: PSIV Mask */
\r
11404 /* -------------------------------- CCU4_CC4_FPC -------------------------------- */
\r
11405 #define CCU4_CC4_FPC_PCMP_Pos 0 /*!< CCU4_CC4 FPC: PCMP Position */
\r
11406 #define CCU4_CC4_FPC_PCMP_Msk (0x0fUL << CCU4_CC4_FPC_PCMP_Pos) /*!< CCU4_CC4 FPC: PCMP Mask */
\r
11407 #define CCU4_CC4_FPC_PVAL_Pos 8 /*!< CCU4_CC4 FPC: PVAL Position */
\r
11408 #define CCU4_CC4_FPC_PVAL_Msk (0x0fUL << CCU4_CC4_FPC_PVAL_Pos) /*!< CCU4_CC4 FPC: PVAL Mask */
\r
11410 /* -------------------------------- CCU4_CC4_FPCS ------------------------------- */
\r
11411 #define CCU4_CC4_FPCS_PCMP_Pos 0 /*!< CCU4_CC4 FPCS: PCMP Position */
\r
11412 #define CCU4_CC4_FPCS_PCMP_Msk (0x0fUL << CCU4_CC4_FPCS_PCMP_Pos) /*!< CCU4_CC4 FPCS: PCMP Mask */
\r
11414 /* --------------------------------- CCU4_CC4_PR -------------------------------- */
\r
11415 #define CCU4_CC4_PR_PR_Pos 0 /*!< CCU4_CC4 PR: PR Position */
\r
11416 #define CCU4_CC4_PR_PR_Msk (0x0000ffffUL << CCU4_CC4_PR_PR_Pos) /*!< CCU4_CC4 PR: PR Mask */
\r
11418 /* -------------------------------- CCU4_CC4_PRS -------------------------------- */
\r
11419 #define CCU4_CC4_PRS_PRS_Pos 0 /*!< CCU4_CC4 PRS: PRS Position */
\r
11420 #define CCU4_CC4_PRS_PRS_Msk (0x0000ffffUL << CCU4_CC4_PRS_PRS_Pos) /*!< CCU4_CC4 PRS: PRS Mask */
\r
11422 /* --------------------------------- CCU4_CC4_CR -------------------------------- */
\r
11423 #define CCU4_CC4_CR_CR_Pos 0 /*!< CCU4_CC4 CR: CR Position */
\r
11424 #define CCU4_CC4_CR_CR_Msk (0x0000ffffUL << CCU4_CC4_CR_CR_Pos) /*!< CCU4_CC4 CR: CR Mask */
\r
11426 /* -------------------------------- CCU4_CC4_CRS -------------------------------- */
\r
11427 #define CCU4_CC4_CRS_CRS_Pos 0 /*!< CCU4_CC4 CRS: CRS Position */
\r
11428 #define CCU4_CC4_CRS_CRS_Msk (0x0000ffffUL << CCU4_CC4_CRS_CRS_Pos) /*!< CCU4_CC4 CRS: CRS Mask */
\r
11430 /* ------------------------------- CCU4_CC4_TIMER ------------------------------- */
\r
11431 #define CCU4_CC4_TIMER_TVAL_Pos 0 /*!< CCU4_CC4 TIMER: TVAL Position */
\r
11432 #define CCU4_CC4_TIMER_TVAL_Msk (0x0000ffffUL << CCU4_CC4_TIMER_TVAL_Pos) /*!< CCU4_CC4 TIMER: TVAL Mask */
\r
11434 /* --------------------------------- CCU4_CC4_CV -------------------------------- */
\r
11435 #define CCU4_CC4_CV_CAPTV_Pos 0 /*!< CCU4_CC4 CV: CAPTV Position */
\r
11436 #define CCU4_CC4_CV_CAPTV_Msk (0x0000ffffUL << CCU4_CC4_CV_CAPTV_Pos) /*!< CCU4_CC4 CV: CAPTV Mask */
\r
11437 #define CCU4_CC4_CV_FPCV_Pos 16 /*!< CCU4_CC4 CV: FPCV Position */
\r
11438 #define CCU4_CC4_CV_FPCV_Msk (0x0fUL << CCU4_CC4_CV_FPCV_Pos) /*!< CCU4_CC4 CV: FPCV Mask */
\r
11439 #define CCU4_CC4_CV_FFL_Pos 20 /*!< CCU4_CC4 CV: FFL Position */
\r
11440 #define CCU4_CC4_CV_FFL_Msk (0x01UL << CCU4_CC4_CV_FFL_Pos) /*!< CCU4_CC4 CV: FFL Mask */
\r
11442 /* -------------------------------- CCU4_CC4_INTS ------------------------------- */
\r
11443 #define CCU4_CC4_INTS_PMUS_Pos 0 /*!< CCU4_CC4 INTS: PMUS Position */
\r
11444 #define CCU4_CC4_INTS_PMUS_Msk (0x01UL << CCU4_CC4_INTS_PMUS_Pos) /*!< CCU4_CC4 INTS: PMUS Mask */
\r
11445 #define CCU4_CC4_INTS_OMDS_Pos 1 /*!< CCU4_CC4 INTS: OMDS Position */
\r
11446 #define CCU4_CC4_INTS_OMDS_Msk (0x01UL << CCU4_CC4_INTS_OMDS_Pos) /*!< CCU4_CC4 INTS: OMDS Mask */
\r
11447 #define CCU4_CC4_INTS_CMUS_Pos 2 /*!< CCU4_CC4 INTS: CMUS Position */
\r
11448 #define CCU4_CC4_INTS_CMUS_Msk (0x01UL << CCU4_CC4_INTS_CMUS_Pos) /*!< CCU4_CC4 INTS: CMUS Mask */
\r
11449 #define CCU4_CC4_INTS_CMDS_Pos 3 /*!< CCU4_CC4 INTS: CMDS Position */
\r
11450 #define CCU4_CC4_INTS_CMDS_Msk (0x01UL << CCU4_CC4_INTS_CMDS_Pos) /*!< CCU4_CC4 INTS: CMDS Mask */
\r
11451 #define CCU4_CC4_INTS_E0AS_Pos 8 /*!< CCU4_CC4 INTS: E0AS Position */
\r
11452 #define CCU4_CC4_INTS_E0AS_Msk (0x01UL << CCU4_CC4_INTS_E0AS_Pos) /*!< CCU4_CC4 INTS: E0AS Mask */
\r
11453 #define CCU4_CC4_INTS_E1AS_Pos 9 /*!< CCU4_CC4 INTS: E1AS Position */
\r
11454 #define CCU4_CC4_INTS_E1AS_Msk (0x01UL << CCU4_CC4_INTS_E1AS_Pos) /*!< CCU4_CC4 INTS: E1AS Mask */
\r
11455 #define CCU4_CC4_INTS_E2AS_Pos 10 /*!< CCU4_CC4 INTS: E2AS Position */
\r
11456 #define CCU4_CC4_INTS_E2AS_Msk (0x01UL << CCU4_CC4_INTS_E2AS_Pos) /*!< CCU4_CC4 INTS: E2AS Mask */
\r
11457 #define CCU4_CC4_INTS_TRPF_Pos 11 /*!< CCU4_CC4 INTS: TRPF Position */
\r
11458 #define CCU4_CC4_INTS_TRPF_Msk (0x01UL << CCU4_CC4_INTS_TRPF_Pos) /*!< CCU4_CC4 INTS: TRPF Mask */
\r
11460 /* -------------------------------- CCU4_CC4_INTE ------------------------------- */
\r
11461 #define CCU4_CC4_INTE_PME_Pos 0 /*!< CCU4_CC4 INTE: PME Position */
\r
11462 #define CCU4_CC4_INTE_PME_Msk (0x01UL << CCU4_CC4_INTE_PME_Pos) /*!< CCU4_CC4 INTE: PME Mask */
\r
11463 #define CCU4_CC4_INTE_OME_Pos 1 /*!< CCU4_CC4 INTE: OME Position */
\r
11464 #define CCU4_CC4_INTE_OME_Msk (0x01UL << CCU4_CC4_INTE_OME_Pos) /*!< CCU4_CC4 INTE: OME Mask */
\r
11465 #define CCU4_CC4_INTE_CMUE_Pos 2 /*!< CCU4_CC4 INTE: CMUE Position */
\r
11466 #define CCU4_CC4_INTE_CMUE_Msk (0x01UL << CCU4_CC4_INTE_CMUE_Pos) /*!< CCU4_CC4 INTE: CMUE Mask */
\r
11467 #define CCU4_CC4_INTE_CMDE_Pos 3 /*!< CCU4_CC4 INTE: CMDE Position */
\r
11468 #define CCU4_CC4_INTE_CMDE_Msk (0x01UL << CCU4_CC4_INTE_CMDE_Pos) /*!< CCU4_CC4 INTE: CMDE Mask */
\r
11469 #define CCU4_CC4_INTE_E0AE_Pos 8 /*!< CCU4_CC4 INTE: E0AE Position */
\r
11470 #define CCU4_CC4_INTE_E0AE_Msk (0x01UL << CCU4_CC4_INTE_E0AE_Pos) /*!< CCU4_CC4 INTE: E0AE Mask */
\r
11471 #define CCU4_CC4_INTE_E1AE_Pos 9 /*!< CCU4_CC4 INTE: E1AE Position */
\r
11472 #define CCU4_CC4_INTE_E1AE_Msk (0x01UL << CCU4_CC4_INTE_E1AE_Pos) /*!< CCU4_CC4 INTE: E1AE Mask */
\r
11473 #define CCU4_CC4_INTE_E2AE_Pos 10 /*!< CCU4_CC4 INTE: E2AE Position */
\r
11474 #define CCU4_CC4_INTE_E2AE_Msk (0x01UL << CCU4_CC4_INTE_E2AE_Pos) /*!< CCU4_CC4 INTE: E2AE Mask */
\r
11476 /* -------------------------------- CCU4_CC4_SRS -------------------------------- */
\r
11477 #define CCU4_CC4_SRS_POSR_Pos 0 /*!< CCU4_CC4 SRS: POSR Position */
\r
11478 #define CCU4_CC4_SRS_POSR_Msk (0x03UL << CCU4_CC4_SRS_POSR_Pos) /*!< CCU4_CC4 SRS: POSR Mask */
\r
11479 #define CCU4_CC4_SRS_CMSR_Pos 2 /*!< CCU4_CC4 SRS: CMSR Position */
\r
11480 #define CCU4_CC4_SRS_CMSR_Msk (0x03UL << CCU4_CC4_SRS_CMSR_Pos) /*!< CCU4_CC4 SRS: CMSR Mask */
\r
11481 #define CCU4_CC4_SRS_E0SR_Pos 8 /*!< CCU4_CC4 SRS: E0SR Position */
\r
11482 #define CCU4_CC4_SRS_E0SR_Msk (0x03UL << CCU4_CC4_SRS_E0SR_Pos) /*!< CCU4_CC4 SRS: E0SR Mask */
\r
11483 #define CCU4_CC4_SRS_E1SR_Pos 10 /*!< CCU4_CC4 SRS: E1SR Position */
\r
11484 #define CCU4_CC4_SRS_E1SR_Msk (0x03UL << CCU4_CC4_SRS_E1SR_Pos) /*!< CCU4_CC4 SRS: E1SR Mask */
\r
11485 #define CCU4_CC4_SRS_E2SR_Pos 12 /*!< CCU4_CC4 SRS: E2SR Position */
\r
11486 #define CCU4_CC4_SRS_E2SR_Msk (0x03UL << CCU4_CC4_SRS_E2SR_Pos) /*!< CCU4_CC4 SRS: E2SR Mask */
\r
11488 /* -------------------------------- CCU4_CC4_SWS -------------------------------- */
\r
11489 #define CCU4_CC4_SWS_SPM_Pos 0 /*!< CCU4_CC4 SWS: SPM Position */
\r
11490 #define CCU4_CC4_SWS_SPM_Msk (0x01UL << CCU4_CC4_SWS_SPM_Pos) /*!< CCU4_CC4 SWS: SPM Mask */
\r
11491 #define CCU4_CC4_SWS_SOM_Pos 1 /*!< CCU4_CC4 SWS: SOM Position */
\r
11492 #define CCU4_CC4_SWS_SOM_Msk (0x01UL << CCU4_CC4_SWS_SOM_Pos) /*!< CCU4_CC4 SWS: SOM Mask */
\r
11493 #define CCU4_CC4_SWS_SCMU_Pos 2 /*!< CCU4_CC4 SWS: SCMU Position */
\r
11494 #define CCU4_CC4_SWS_SCMU_Msk (0x01UL << CCU4_CC4_SWS_SCMU_Pos) /*!< CCU4_CC4 SWS: SCMU Mask */
\r
11495 #define CCU4_CC4_SWS_SCMD_Pos 3 /*!< CCU4_CC4 SWS: SCMD Position */
\r
11496 #define CCU4_CC4_SWS_SCMD_Msk (0x01UL << CCU4_CC4_SWS_SCMD_Pos) /*!< CCU4_CC4 SWS: SCMD Mask */
\r
11497 #define CCU4_CC4_SWS_SE0A_Pos 8 /*!< CCU4_CC4 SWS: SE0A Position */
\r
11498 #define CCU4_CC4_SWS_SE0A_Msk (0x01UL << CCU4_CC4_SWS_SE0A_Pos) /*!< CCU4_CC4 SWS: SE0A Mask */
\r
11499 #define CCU4_CC4_SWS_SE1A_Pos 9 /*!< CCU4_CC4 SWS: SE1A Position */
\r
11500 #define CCU4_CC4_SWS_SE1A_Msk (0x01UL << CCU4_CC4_SWS_SE1A_Pos) /*!< CCU4_CC4 SWS: SE1A Mask */
\r
11501 #define CCU4_CC4_SWS_SE2A_Pos 10 /*!< CCU4_CC4 SWS: SE2A Position */
\r
11502 #define CCU4_CC4_SWS_SE2A_Msk (0x01UL << CCU4_CC4_SWS_SE2A_Pos) /*!< CCU4_CC4 SWS: SE2A Mask */
\r
11503 #define CCU4_CC4_SWS_STRPF_Pos 11 /*!< CCU4_CC4 SWS: STRPF Position */
\r
11504 #define CCU4_CC4_SWS_STRPF_Msk (0x01UL << CCU4_CC4_SWS_STRPF_Pos) /*!< CCU4_CC4 SWS: STRPF Mask */
\r
11506 /* -------------------------------- CCU4_CC4_SWR -------------------------------- */
\r
11507 #define CCU4_CC4_SWR_RPM_Pos 0 /*!< CCU4_CC4 SWR: RPM Position */
\r
11508 #define CCU4_CC4_SWR_RPM_Msk (0x01UL << CCU4_CC4_SWR_RPM_Pos) /*!< CCU4_CC4 SWR: RPM Mask */
\r
11509 #define CCU4_CC4_SWR_ROM_Pos 1 /*!< CCU4_CC4 SWR: ROM Position */
\r
11510 #define CCU4_CC4_SWR_ROM_Msk (0x01UL << CCU4_CC4_SWR_ROM_Pos) /*!< CCU4_CC4 SWR: ROM Mask */
\r
11511 #define CCU4_CC4_SWR_RCMU_Pos 2 /*!< CCU4_CC4 SWR: RCMU Position */
\r
11512 #define CCU4_CC4_SWR_RCMU_Msk (0x01UL << CCU4_CC4_SWR_RCMU_Pos) /*!< CCU4_CC4 SWR: RCMU Mask */
\r
11513 #define CCU4_CC4_SWR_RCMD_Pos 3 /*!< CCU4_CC4 SWR: RCMD Position */
\r
11514 #define CCU4_CC4_SWR_RCMD_Msk (0x01UL << CCU4_CC4_SWR_RCMD_Pos) /*!< CCU4_CC4 SWR: RCMD Mask */
\r
11515 #define CCU4_CC4_SWR_RE0A_Pos 8 /*!< CCU4_CC4 SWR: RE0A Position */
\r
11516 #define CCU4_CC4_SWR_RE0A_Msk (0x01UL << CCU4_CC4_SWR_RE0A_Pos) /*!< CCU4_CC4 SWR: RE0A Mask */
\r
11517 #define CCU4_CC4_SWR_RE1A_Pos 9 /*!< CCU4_CC4 SWR: RE1A Position */
\r
11518 #define CCU4_CC4_SWR_RE1A_Msk (0x01UL << CCU4_CC4_SWR_RE1A_Pos) /*!< CCU4_CC4 SWR: RE1A Mask */
\r
11519 #define CCU4_CC4_SWR_RE2A_Pos 10 /*!< CCU4_CC4 SWR: RE2A Position */
\r
11520 #define CCU4_CC4_SWR_RE2A_Msk (0x01UL << CCU4_CC4_SWR_RE2A_Pos) /*!< CCU4_CC4 SWR: RE2A Mask */
\r
11521 #define CCU4_CC4_SWR_RTRPF_Pos 11 /*!< CCU4_CC4 SWR: RTRPF Position */
\r
11522 #define CCU4_CC4_SWR_RTRPF_Msk (0x01UL << CCU4_CC4_SWR_RTRPF_Pos) /*!< CCU4_CC4 SWR: RTRPF Mask */
\r
11525 /* ================================================================================ */
\r
11526 /* ================ Group 'CCU8' Position & Mask ================ */
\r
11527 /* ================================================================================ */
\r
11530 /* --------------------------------- CCU8_GCTRL --------------------------------- */
\r
11531 #define CCU8_GCTRL_PRBC_Pos 0 /*!< CCU8 GCTRL: PRBC Position */
\r
11532 #define CCU8_GCTRL_PRBC_Msk (0x07UL << CCU8_GCTRL_PRBC_Pos) /*!< CCU8 GCTRL: PRBC Mask */
\r
11533 #define CCU8_GCTRL_PCIS_Pos 4 /*!< CCU8 GCTRL: PCIS Position */
\r
11534 #define CCU8_GCTRL_PCIS_Msk (0x03UL << CCU8_GCTRL_PCIS_Pos) /*!< CCU8 GCTRL: PCIS Mask */
\r
11535 #define CCU8_GCTRL_SUSCFG_Pos 8 /*!< CCU8 GCTRL: SUSCFG Position */
\r
11536 #define CCU8_GCTRL_SUSCFG_Msk (0x03UL << CCU8_GCTRL_SUSCFG_Pos) /*!< CCU8 GCTRL: SUSCFG Mask */
\r
11537 #define CCU8_GCTRL_MSE0_Pos 10 /*!< CCU8 GCTRL: MSE0 Position */
\r
11538 #define CCU8_GCTRL_MSE0_Msk (0x01UL << CCU8_GCTRL_MSE0_Pos) /*!< CCU8 GCTRL: MSE0 Mask */
\r
11539 #define CCU8_GCTRL_MSE1_Pos 11 /*!< CCU8 GCTRL: MSE1 Position */
\r
11540 #define CCU8_GCTRL_MSE1_Msk (0x01UL << CCU8_GCTRL_MSE1_Pos) /*!< CCU8 GCTRL: MSE1 Mask */
\r
11541 #define CCU8_GCTRL_MSE2_Pos 12 /*!< CCU8 GCTRL: MSE2 Position */
\r
11542 #define CCU8_GCTRL_MSE2_Msk (0x01UL << CCU8_GCTRL_MSE2_Pos) /*!< CCU8 GCTRL: MSE2 Mask */
\r
11543 #define CCU8_GCTRL_MSE3_Pos 13 /*!< CCU8 GCTRL: MSE3 Position */
\r
11544 #define CCU8_GCTRL_MSE3_Msk (0x01UL << CCU8_GCTRL_MSE3_Pos) /*!< CCU8 GCTRL: MSE3 Mask */
\r
11545 #define CCU8_GCTRL_MSDE_Pos 14 /*!< CCU8 GCTRL: MSDE Position */
\r
11546 #define CCU8_GCTRL_MSDE_Msk (0x03UL << CCU8_GCTRL_MSDE_Pos) /*!< CCU8 GCTRL: MSDE Mask */
\r
11548 /* --------------------------------- CCU8_GSTAT --------------------------------- */
\r
11549 #define CCU8_GSTAT_S0I_Pos 0 /*!< CCU8 GSTAT: S0I Position */
\r
11550 #define CCU8_GSTAT_S0I_Msk (0x01UL << CCU8_GSTAT_S0I_Pos) /*!< CCU8 GSTAT: S0I Mask */
\r
11551 #define CCU8_GSTAT_S1I_Pos 1 /*!< CCU8 GSTAT: S1I Position */
\r
11552 #define CCU8_GSTAT_S1I_Msk (0x01UL << CCU8_GSTAT_S1I_Pos) /*!< CCU8 GSTAT: S1I Mask */
\r
11553 #define CCU8_GSTAT_S2I_Pos 2 /*!< CCU8 GSTAT: S2I Position */
\r
11554 #define CCU8_GSTAT_S2I_Msk (0x01UL << CCU8_GSTAT_S2I_Pos) /*!< CCU8 GSTAT: S2I Mask */
\r
11555 #define CCU8_GSTAT_S3I_Pos 3 /*!< CCU8 GSTAT: S3I Position */
\r
11556 #define CCU8_GSTAT_S3I_Msk (0x01UL << CCU8_GSTAT_S3I_Pos) /*!< CCU8 GSTAT: S3I Mask */
\r
11557 #define CCU8_GSTAT_PRB_Pos 8 /*!< CCU8 GSTAT: PRB Position */
\r
11558 #define CCU8_GSTAT_PRB_Msk (0x01UL << CCU8_GSTAT_PRB_Pos) /*!< CCU8 GSTAT: PRB Mask */
\r
11559 #define CCU8_GSTAT_PCRB_Pos 10 /*!< CCU8 GSTAT: PCRB Position */
\r
11560 #define CCU8_GSTAT_PCRB_Msk (0x01UL << CCU8_GSTAT_PCRB_Pos) /*!< CCU8 GSTAT: PCRB Mask */
\r
11562 /* --------------------------------- CCU8_GIDLS --------------------------------- */
\r
11563 #define CCU8_GIDLS_SS0I_Pos 0 /*!< CCU8 GIDLS: SS0I Position */
\r
11564 #define CCU8_GIDLS_SS0I_Msk (0x01UL << CCU8_GIDLS_SS0I_Pos) /*!< CCU8 GIDLS: SS0I Mask */
\r
11565 #define CCU8_GIDLS_SS1I_Pos 1 /*!< CCU8 GIDLS: SS1I Position */
\r
11566 #define CCU8_GIDLS_SS1I_Msk (0x01UL << CCU8_GIDLS_SS1I_Pos) /*!< CCU8 GIDLS: SS1I Mask */
\r
11567 #define CCU8_GIDLS_SS2I_Pos 2 /*!< CCU8 GIDLS: SS2I Position */
\r
11568 #define CCU8_GIDLS_SS2I_Msk (0x01UL << CCU8_GIDLS_SS2I_Pos) /*!< CCU8 GIDLS: SS2I Mask */
\r
11569 #define CCU8_GIDLS_SS3I_Pos 3 /*!< CCU8 GIDLS: SS3I Position */
\r
11570 #define CCU8_GIDLS_SS3I_Msk (0x01UL << CCU8_GIDLS_SS3I_Pos) /*!< CCU8 GIDLS: SS3I Mask */
\r
11571 #define CCU8_GIDLS_CPRB_Pos 8 /*!< CCU8 GIDLS: CPRB Position */
\r
11572 #define CCU8_GIDLS_CPRB_Msk (0x01UL << CCU8_GIDLS_CPRB_Pos) /*!< CCU8 GIDLS: CPRB Mask */
\r
11573 #define CCU8_GIDLS_PSIC_Pos 9 /*!< CCU8 GIDLS: PSIC Position */
\r
11574 #define CCU8_GIDLS_PSIC_Msk (0x01UL << CCU8_GIDLS_PSIC_Pos) /*!< CCU8 GIDLS: PSIC Mask */
\r
11575 #define CCU8_GIDLS_CPCH_Pos 10 /*!< CCU8 GIDLS: CPCH Position */
\r
11576 #define CCU8_GIDLS_CPCH_Msk (0x01UL << CCU8_GIDLS_CPCH_Pos) /*!< CCU8 GIDLS: CPCH Mask */
\r
11578 /* --------------------------------- CCU8_GIDLC --------------------------------- */
\r
11579 #define CCU8_GIDLC_CS0I_Pos 0 /*!< CCU8 GIDLC: CS0I Position */
\r
11580 #define CCU8_GIDLC_CS0I_Msk (0x01UL << CCU8_GIDLC_CS0I_Pos) /*!< CCU8 GIDLC: CS0I Mask */
\r
11581 #define CCU8_GIDLC_CS1I_Pos 1 /*!< CCU8 GIDLC: CS1I Position */
\r
11582 #define CCU8_GIDLC_CS1I_Msk (0x01UL << CCU8_GIDLC_CS1I_Pos) /*!< CCU8 GIDLC: CS1I Mask */
\r
11583 #define CCU8_GIDLC_CS2I_Pos 2 /*!< CCU8 GIDLC: CS2I Position */
\r
11584 #define CCU8_GIDLC_CS2I_Msk (0x01UL << CCU8_GIDLC_CS2I_Pos) /*!< CCU8 GIDLC: CS2I Mask */
\r
11585 #define CCU8_GIDLC_CS3I_Pos 3 /*!< CCU8 GIDLC: CS3I Position */
\r
11586 #define CCU8_GIDLC_CS3I_Msk (0x01UL << CCU8_GIDLC_CS3I_Pos) /*!< CCU8 GIDLC: CS3I Mask */
\r
11587 #define CCU8_GIDLC_SPRB_Pos 8 /*!< CCU8 GIDLC: SPRB Position */
\r
11588 #define CCU8_GIDLC_SPRB_Msk (0x01UL << CCU8_GIDLC_SPRB_Pos) /*!< CCU8 GIDLC: SPRB Mask */
\r
11589 #define CCU8_GIDLC_SPCH_Pos 10 /*!< CCU8 GIDLC: SPCH Position */
\r
11590 #define CCU8_GIDLC_SPCH_Msk (0x01UL << CCU8_GIDLC_SPCH_Pos) /*!< CCU8 GIDLC: SPCH Mask */
\r
11592 /* ---------------------------------- CCU8_GCSS --------------------------------- */
\r
11593 #define CCU8_GCSS_S0SE_Pos 0 /*!< CCU8 GCSS: S0SE Position */
\r
11594 #define CCU8_GCSS_S0SE_Msk (0x01UL << CCU8_GCSS_S0SE_Pos) /*!< CCU8 GCSS: S0SE Mask */
\r
11595 #define CCU8_GCSS_S0DSE_Pos 1 /*!< CCU8 GCSS: S0DSE Position */
\r
11596 #define CCU8_GCSS_S0DSE_Msk (0x01UL << CCU8_GCSS_S0DSE_Pos) /*!< CCU8 GCSS: S0DSE Mask */
\r
11597 #define CCU8_GCSS_S0PSE_Pos 2 /*!< CCU8 GCSS: S0PSE Position */
\r
11598 #define CCU8_GCSS_S0PSE_Msk (0x01UL << CCU8_GCSS_S0PSE_Pos) /*!< CCU8 GCSS: S0PSE Mask */
\r
11599 #define CCU8_GCSS_S1SE_Pos 4 /*!< CCU8 GCSS: S1SE Position */
\r
11600 #define CCU8_GCSS_S1SE_Msk (0x01UL << CCU8_GCSS_S1SE_Pos) /*!< CCU8 GCSS: S1SE Mask */
\r
11601 #define CCU8_GCSS_S1DSE_Pos 5 /*!< CCU8 GCSS: S1DSE Position */
\r
11602 #define CCU8_GCSS_S1DSE_Msk (0x01UL << CCU8_GCSS_S1DSE_Pos) /*!< CCU8 GCSS: S1DSE Mask */
\r
11603 #define CCU8_GCSS_S1PSE_Pos 6 /*!< CCU8 GCSS: S1PSE Position */
\r
11604 #define CCU8_GCSS_S1PSE_Msk (0x01UL << CCU8_GCSS_S1PSE_Pos) /*!< CCU8 GCSS: S1PSE Mask */
\r
11605 #define CCU8_GCSS_S2SE_Pos 8 /*!< CCU8 GCSS: S2SE Position */
\r
11606 #define CCU8_GCSS_S2SE_Msk (0x01UL << CCU8_GCSS_S2SE_Pos) /*!< CCU8 GCSS: S2SE Mask */
\r
11607 #define CCU8_GCSS_S2DSE_Pos 9 /*!< CCU8 GCSS: S2DSE Position */
\r
11608 #define CCU8_GCSS_S2DSE_Msk (0x01UL << CCU8_GCSS_S2DSE_Pos) /*!< CCU8 GCSS: S2DSE Mask */
\r
11609 #define CCU8_GCSS_S2PSE_Pos 10 /*!< CCU8 GCSS: S2PSE Position */
\r
11610 #define CCU8_GCSS_S2PSE_Msk (0x01UL << CCU8_GCSS_S2PSE_Pos) /*!< CCU8 GCSS: S2PSE Mask */
\r
11611 #define CCU8_GCSS_S3SE_Pos 12 /*!< CCU8 GCSS: S3SE Position */
\r
11612 #define CCU8_GCSS_S3SE_Msk (0x01UL << CCU8_GCSS_S3SE_Pos) /*!< CCU8 GCSS: S3SE Mask */
\r
11613 #define CCU8_GCSS_S3DSE_Pos 13 /*!< CCU8 GCSS: S3DSE Position */
\r
11614 #define CCU8_GCSS_S3DSE_Msk (0x01UL << CCU8_GCSS_S3DSE_Pos) /*!< CCU8 GCSS: S3DSE Mask */
\r
11615 #define CCU8_GCSS_S3PSE_Pos 14 /*!< CCU8 GCSS: S3PSE Position */
\r
11616 #define CCU8_GCSS_S3PSE_Msk (0x01UL << CCU8_GCSS_S3PSE_Pos) /*!< CCU8 GCSS: S3PSE Mask */
\r
11617 #define CCU8_GCSS_S0ST1S_Pos 16 /*!< CCU8 GCSS: S0ST1S Position */
\r
11618 #define CCU8_GCSS_S0ST1S_Msk (0x01UL << CCU8_GCSS_S0ST1S_Pos) /*!< CCU8 GCSS: S0ST1S Mask */
\r
11619 #define CCU8_GCSS_S1ST1S_Pos 17 /*!< CCU8 GCSS: S1ST1S Position */
\r
11620 #define CCU8_GCSS_S1ST1S_Msk (0x01UL << CCU8_GCSS_S1ST1S_Pos) /*!< CCU8 GCSS: S1ST1S Mask */
\r
11621 #define CCU8_GCSS_S2ST1S_Pos 18 /*!< CCU8 GCSS: S2ST1S Position */
\r
11622 #define CCU8_GCSS_S2ST1S_Msk (0x01UL << CCU8_GCSS_S2ST1S_Pos) /*!< CCU8 GCSS: S2ST1S Mask */
\r
11623 #define CCU8_GCSS_S3ST1S_Pos 19 /*!< CCU8 GCSS: S3ST1S Position */
\r
11624 #define CCU8_GCSS_S3ST1S_Msk (0x01UL << CCU8_GCSS_S3ST1S_Pos) /*!< CCU8 GCSS: S3ST1S Mask */
\r
11625 #define CCU8_GCSS_S0ST2S_Pos 20 /*!< CCU8 GCSS: S0ST2S Position */
\r
11626 #define CCU8_GCSS_S0ST2S_Msk (0x01UL << CCU8_GCSS_S0ST2S_Pos) /*!< CCU8 GCSS: S0ST2S Mask */
\r
11627 #define CCU8_GCSS_S1ST2S_Pos 21 /*!< CCU8 GCSS: S1ST2S Position */
\r
11628 #define CCU8_GCSS_S1ST2S_Msk (0x01UL << CCU8_GCSS_S1ST2S_Pos) /*!< CCU8 GCSS: S1ST2S Mask */
\r
11629 #define CCU8_GCSS_S2ST2S_Pos 22 /*!< CCU8 GCSS: S2ST2S Position */
\r
11630 #define CCU8_GCSS_S2ST2S_Msk (0x01UL << CCU8_GCSS_S2ST2S_Pos) /*!< CCU8 GCSS: S2ST2S Mask */
\r
11631 #define CCU8_GCSS_S3ST2S_Pos 23 /*!< CCU8 GCSS: S3ST2S Position */
\r
11632 #define CCU8_GCSS_S3ST2S_Msk (0x01UL << CCU8_GCSS_S3ST2S_Pos) /*!< CCU8 GCSS: S3ST2S Mask */
\r
11634 /* ---------------------------------- CCU8_GCSC --------------------------------- */
\r
11635 #define CCU8_GCSC_S0SC_Pos 0 /*!< CCU8 GCSC: S0SC Position */
\r
11636 #define CCU8_GCSC_S0SC_Msk (0x01UL << CCU8_GCSC_S0SC_Pos) /*!< CCU8 GCSC: S0SC Mask */
\r
11637 #define CCU8_GCSC_S0DSC_Pos 1 /*!< CCU8 GCSC: S0DSC Position */
\r
11638 #define CCU8_GCSC_S0DSC_Msk (0x01UL << CCU8_GCSC_S0DSC_Pos) /*!< CCU8 GCSC: S0DSC Mask */
\r
11639 #define CCU8_GCSC_S0PSC_Pos 2 /*!< CCU8 GCSC: S0PSC Position */
\r
11640 #define CCU8_GCSC_S0PSC_Msk (0x01UL << CCU8_GCSC_S0PSC_Pos) /*!< CCU8 GCSC: S0PSC Mask */
\r
11641 #define CCU8_GCSC_S1SC_Pos 4 /*!< CCU8 GCSC: S1SC Position */
\r
11642 #define CCU8_GCSC_S1SC_Msk (0x01UL << CCU8_GCSC_S1SC_Pos) /*!< CCU8 GCSC: S1SC Mask */
\r
11643 #define CCU8_GCSC_S1DSC_Pos 5 /*!< CCU8 GCSC: S1DSC Position */
\r
11644 #define CCU8_GCSC_S1DSC_Msk (0x01UL << CCU8_GCSC_S1DSC_Pos) /*!< CCU8 GCSC: S1DSC Mask */
\r
11645 #define CCU8_GCSC_S1PSC_Pos 6 /*!< CCU8 GCSC: S1PSC Position */
\r
11646 #define CCU8_GCSC_S1PSC_Msk (0x01UL << CCU8_GCSC_S1PSC_Pos) /*!< CCU8 GCSC: S1PSC Mask */
\r
11647 #define CCU8_GCSC_S2SC_Pos 8 /*!< CCU8 GCSC: S2SC Position */
\r
11648 #define CCU8_GCSC_S2SC_Msk (0x01UL << CCU8_GCSC_S2SC_Pos) /*!< CCU8 GCSC: S2SC Mask */
\r
11649 #define CCU8_GCSC_S2DSC_Pos 9 /*!< CCU8 GCSC: S2DSC Position */
\r
11650 #define CCU8_GCSC_S2DSC_Msk (0x01UL << CCU8_GCSC_S2DSC_Pos) /*!< CCU8 GCSC: S2DSC Mask */
\r
11651 #define CCU8_GCSC_S2PSC_Pos 10 /*!< CCU8 GCSC: S2PSC Position */
\r
11652 #define CCU8_GCSC_S2PSC_Msk (0x01UL << CCU8_GCSC_S2PSC_Pos) /*!< CCU8 GCSC: S2PSC Mask */
\r
11653 #define CCU8_GCSC_S3SC_Pos 12 /*!< CCU8 GCSC: S3SC Position */
\r
11654 #define CCU8_GCSC_S3SC_Msk (0x01UL << CCU8_GCSC_S3SC_Pos) /*!< CCU8 GCSC: S3SC Mask */
\r
11655 #define CCU8_GCSC_S3DSC_Pos 13 /*!< CCU8 GCSC: S3DSC Position */
\r
11656 #define CCU8_GCSC_S3DSC_Msk (0x01UL << CCU8_GCSC_S3DSC_Pos) /*!< CCU8 GCSC: S3DSC Mask */
\r
11657 #define CCU8_GCSC_S3PSC_Pos 14 /*!< CCU8 GCSC: S3PSC Position */
\r
11658 #define CCU8_GCSC_S3PSC_Msk (0x01UL << CCU8_GCSC_S3PSC_Pos) /*!< CCU8 GCSC: S3PSC Mask */
\r
11659 #define CCU8_GCSC_S0ST1C_Pos 16 /*!< CCU8 GCSC: S0ST1C Position */
\r
11660 #define CCU8_GCSC_S0ST1C_Msk (0x01UL << CCU8_GCSC_S0ST1C_Pos) /*!< CCU8 GCSC: S0ST1C Mask */
\r
11661 #define CCU8_GCSC_S1ST1C_Pos 17 /*!< CCU8 GCSC: S1ST1C Position */
\r
11662 #define CCU8_GCSC_S1ST1C_Msk (0x01UL << CCU8_GCSC_S1ST1C_Pos) /*!< CCU8 GCSC: S1ST1C Mask */
\r
11663 #define CCU8_GCSC_S2ST1C_Pos 18 /*!< CCU8 GCSC: S2ST1C Position */
\r
11664 #define CCU8_GCSC_S2ST1C_Msk (0x01UL << CCU8_GCSC_S2ST1C_Pos) /*!< CCU8 GCSC: S2ST1C Mask */
\r
11665 #define CCU8_GCSC_S3ST1C_Pos 19 /*!< CCU8 GCSC: S3ST1C Position */
\r
11666 #define CCU8_GCSC_S3ST1C_Msk (0x01UL << CCU8_GCSC_S3ST1C_Pos) /*!< CCU8 GCSC: S3ST1C Mask */
\r
11667 #define CCU8_GCSC_S0ST2C_Pos 20 /*!< CCU8 GCSC: S0ST2C Position */
\r
11668 #define CCU8_GCSC_S0ST2C_Msk (0x01UL << CCU8_GCSC_S0ST2C_Pos) /*!< CCU8 GCSC: S0ST2C Mask */
\r
11669 #define CCU8_GCSC_S1ST2C_Pos 21 /*!< CCU8 GCSC: S1ST2C Position */
\r
11670 #define CCU8_GCSC_S1ST2C_Msk (0x01UL << CCU8_GCSC_S1ST2C_Pos) /*!< CCU8 GCSC: S1ST2C Mask */
\r
11671 #define CCU8_GCSC_S2ST2C_Pos 22 /*!< CCU8 GCSC: S2ST2C Position */
\r
11672 #define CCU8_GCSC_S2ST2C_Msk (0x01UL << CCU8_GCSC_S2ST2C_Pos) /*!< CCU8 GCSC: S2ST2C Mask */
\r
11673 #define CCU8_GCSC_S3ST2C_Pos 23 /*!< CCU8 GCSC: S3ST2C Position */
\r
11674 #define CCU8_GCSC_S3ST2C_Msk (0x01UL << CCU8_GCSC_S3ST2C_Pos) /*!< CCU8 GCSC: S3ST2C Mask */
\r
11676 /* ---------------------------------- CCU8_GCST --------------------------------- */
\r
11677 #define CCU8_GCST_S0SS_Pos 0 /*!< CCU8 GCST: S0SS Position */
\r
11678 #define CCU8_GCST_S0SS_Msk (0x01UL << CCU8_GCST_S0SS_Pos) /*!< CCU8 GCST: S0SS Mask */
\r
11679 #define CCU8_GCST_S0DSS_Pos 1 /*!< CCU8 GCST: S0DSS Position */
\r
11680 #define CCU8_GCST_S0DSS_Msk (0x01UL << CCU8_GCST_S0DSS_Pos) /*!< CCU8 GCST: S0DSS Mask */
\r
11681 #define CCU8_GCST_S0PSS_Pos 2 /*!< CCU8 GCST: S0PSS Position */
\r
11682 #define CCU8_GCST_S0PSS_Msk (0x01UL << CCU8_GCST_S0PSS_Pos) /*!< CCU8 GCST: S0PSS Mask */
\r
11683 #define CCU8_GCST_S1SS_Pos 4 /*!< CCU8 GCST: S1SS Position */
\r
11684 #define CCU8_GCST_S1SS_Msk (0x01UL << CCU8_GCST_S1SS_Pos) /*!< CCU8 GCST: S1SS Mask */
\r
11685 #define CCU8_GCST_S1DSS_Pos 5 /*!< CCU8 GCST: S1DSS Position */
\r
11686 #define CCU8_GCST_S1DSS_Msk (0x01UL << CCU8_GCST_S1DSS_Pos) /*!< CCU8 GCST: S1DSS Mask */
\r
11687 #define CCU8_GCST_S1PSS_Pos 6 /*!< CCU8 GCST: S1PSS Position */
\r
11688 #define CCU8_GCST_S1PSS_Msk (0x01UL << CCU8_GCST_S1PSS_Pos) /*!< CCU8 GCST: S1PSS Mask */
\r
11689 #define CCU8_GCST_S2SS_Pos 8 /*!< CCU8 GCST: S2SS Position */
\r
11690 #define CCU8_GCST_S2SS_Msk (0x01UL << CCU8_GCST_S2SS_Pos) /*!< CCU8 GCST: S2SS Mask */
\r
11691 #define CCU8_GCST_S2DSS_Pos 9 /*!< CCU8 GCST: S2DSS Position */
\r
11692 #define CCU8_GCST_S2DSS_Msk (0x01UL << CCU8_GCST_S2DSS_Pos) /*!< CCU8 GCST: S2DSS Mask */
\r
11693 #define CCU8_GCST_S2PSS_Pos 10 /*!< CCU8 GCST: S2PSS Position */
\r
11694 #define CCU8_GCST_S2PSS_Msk (0x01UL << CCU8_GCST_S2PSS_Pos) /*!< CCU8 GCST: S2PSS Mask */
\r
11695 #define CCU8_GCST_S3SS_Pos 12 /*!< CCU8 GCST: S3SS Position */
\r
11696 #define CCU8_GCST_S3SS_Msk (0x01UL << CCU8_GCST_S3SS_Pos) /*!< CCU8 GCST: S3SS Mask */
\r
11697 #define CCU8_GCST_S3DSS_Pos 13 /*!< CCU8 GCST: S3DSS Position */
\r
11698 #define CCU8_GCST_S3DSS_Msk (0x01UL << CCU8_GCST_S3DSS_Pos) /*!< CCU8 GCST: S3DSS Mask */
\r
11699 #define CCU8_GCST_S3PSS_Pos 14 /*!< CCU8 GCST: S3PSS Position */
\r
11700 #define CCU8_GCST_S3PSS_Msk (0x01UL << CCU8_GCST_S3PSS_Pos) /*!< CCU8 GCST: S3PSS Mask */
\r
11701 #define CCU8_GCST_CC80ST1_Pos 16 /*!< CCU8 GCST: CC80ST1 Position */
\r
11702 #define CCU8_GCST_CC80ST1_Msk (0x01UL << CCU8_GCST_CC80ST1_Pos) /*!< CCU8 GCST: CC80ST1 Mask */
\r
11703 #define CCU8_GCST_CC81ST1_Pos 17 /*!< CCU8 GCST: CC81ST1 Position */
\r
11704 #define CCU8_GCST_CC81ST1_Msk (0x01UL << CCU8_GCST_CC81ST1_Pos) /*!< CCU8 GCST: CC81ST1 Mask */
\r
11705 #define CCU8_GCST_CC82ST1_Pos 18 /*!< CCU8 GCST: CC82ST1 Position */
\r
11706 #define CCU8_GCST_CC82ST1_Msk (0x01UL << CCU8_GCST_CC82ST1_Pos) /*!< CCU8 GCST: CC82ST1 Mask */
\r
11707 #define CCU8_GCST_CC83ST1_Pos 19 /*!< CCU8 GCST: CC83ST1 Position */
\r
11708 #define CCU8_GCST_CC83ST1_Msk (0x01UL << CCU8_GCST_CC83ST1_Pos) /*!< CCU8 GCST: CC83ST1 Mask */
\r
11709 #define CCU8_GCST_CC80ST2_Pos 20 /*!< CCU8 GCST: CC80ST2 Position */
\r
11710 #define CCU8_GCST_CC80ST2_Msk (0x01UL << CCU8_GCST_CC80ST2_Pos) /*!< CCU8 GCST: CC80ST2 Mask */
\r
11711 #define CCU8_GCST_CC81ST2_Pos 21 /*!< CCU8 GCST: CC81ST2 Position */
\r
11712 #define CCU8_GCST_CC81ST2_Msk (0x01UL << CCU8_GCST_CC81ST2_Pos) /*!< CCU8 GCST: CC81ST2 Mask */
\r
11713 #define CCU8_GCST_CC82ST2_Pos 22 /*!< CCU8 GCST: CC82ST2 Position */
\r
11714 #define CCU8_GCST_CC82ST2_Msk (0x01UL << CCU8_GCST_CC82ST2_Pos) /*!< CCU8 GCST: CC82ST2 Mask */
\r
11715 #define CCU8_GCST_CC83ST2_Pos 23 /*!< CCU8 GCST: CC83ST2 Position */
\r
11716 #define CCU8_GCST_CC83ST2_Msk (0x01UL << CCU8_GCST_CC83ST2_Pos) /*!< CCU8 GCST: CC83ST2 Mask */
\r
11718 /* --------------------------------- CCU8_GPCHK --------------------------------- */
\r
11719 #define CCU8_GPCHK_PASE_Pos 0 /*!< CCU8 GPCHK: PASE Position */
\r
11720 #define CCU8_GPCHK_PASE_Msk (0x01UL << CCU8_GPCHK_PASE_Pos) /*!< CCU8 GPCHK: PASE Mask */
\r
11721 #define CCU8_GPCHK_PACS_Pos 1 /*!< CCU8 GPCHK: PACS Position */
\r
11722 #define CCU8_GPCHK_PACS_Msk (0x03UL << CCU8_GPCHK_PACS_Pos) /*!< CCU8 GPCHK: PACS Mask */
\r
11723 #define CCU8_GPCHK_PISEL_Pos 3 /*!< CCU8 GPCHK: PISEL Position */
\r
11724 #define CCU8_GPCHK_PISEL_Msk (0x03UL << CCU8_GPCHK_PISEL_Pos) /*!< CCU8 GPCHK: PISEL Mask */
\r
11725 #define CCU8_GPCHK_PCDS_Pos 5 /*!< CCU8 GPCHK: PCDS Position */
\r
11726 #define CCU8_GPCHK_PCDS_Msk (0x03UL << CCU8_GPCHK_PCDS_Pos) /*!< CCU8 GPCHK: PCDS Mask */
\r
11727 #define CCU8_GPCHK_PCTS_Pos 7 /*!< CCU8 GPCHK: PCTS Position */
\r
11728 #define CCU8_GPCHK_PCTS_Msk (0x01UL << CCU8_GPCHK_PCTS_Pos) /*!< CCU8 GPCHK: PCTS Mask */
\r
11729 #define CCU8_GPCHK_PCST_Pos 15 /*!< CCU8 GPCHK: PCST Position */
\r
11730 #define CCU8_GPCHK_PCST_Msk (0x01UL << CCU8_GPCHK_PCST_Pos) /*!< CCU8 GPCHK: PCST Mask */
\r
11731 #define CCU8_GPCHK_PCSEL0_Pos 16 /*!< CCU8 GPCHK: PCSEL0 Position */
\r
11732 #define CCU8_GPCHK_PCSEL0_Msk (0x0fUL << CCU8_GPCHK_PCSEL0_Pos) /*!< CCU8 GPCHK: PCSEL0 Mask */
\r
11733 #define CCU8_GPCHK_PCSEL1_Pos 20 /*!< CCU8 GPCHK: PCSEL1 Position */
\r
11734 #define CCU8_GPCHK_PCSEL1_Msk (0x0fUL << CCU8_GPCHK_PCSEL1_Pos) /*!< CCU8 GPCHK: PCSEL1 Mask */
\r
11735 #define CCU8_GPCHK_PCSEL2_Pos 24 /*!< CCU8 GPCHK: PCSEL2 Position */
\r
11736 #define CCU8_GPCHK_PCSEL2_Msk (0x0fUL << CCU8_GPCHK_PCSEL2_Pos) /*!< CCU8 GPCHK: PCSEL2 Mask */
\r
11737 #define CCU8_GPCHK_PCSEL3_Pos 28 /*!< CCU8 GPCHK: PCSEL3 Position */
\r
11738 #define CCU8_GPCHK_PCSEL3_Msk (0x0fUL << CCU8_GPCHK_PCSEL3_Pos) /*!< CCU8 GPCHK: PCSEL3 Mask */
\r
11740 /* ---------------------------------- CCU8_ECRD --------------------------------- */
\r
11741 #define CCU8_ECRD_CAPV_Pos 0 /*!< CCU8 ECRD: CAPV Position */
\r
11742 #define CCU8_ECRD_CAPV_Msk (0x0000ffffUL << CCU8_ECRD_CAPV_Pos) /*!< CCU8 ECRD: CAPV Mask */
\r
11743 #define CCU8_ECRD_FPCV_Pos 16 /*!< CCU8 ECRD: FPCV Position */
\r
11744 #define CCU8_ECRD_FPCV_Msk (0x0fUL << CCU8_ECRD_FPCV_Pos) /*!< CCU8 ECRD: FPCV Mask */
\r
11745 #define CCU8_ECRD_SPTR_Pos 20 /*!< CCU8 ECRD: SPTR Position */
\r
11746 #define CCU8_ECRD_SPTR_Msk (0x03UL << CCU8_ECRD_SPTR_Pos) /*!< CCU8 ECRD: SPTR Mask */
\r
11747 #define CCU8_ECRD_VPTR_Pos 22 /*!< CCU8 ECRD: VPTR Position */
\r
11748 #define CCU8_ECRD_VPTR_Msk (0x03UL << CCU8_ECRD_VPTR_Pos) /*!< CCU8 ECRD: VPTR Mask */
\r
11749 #define CCU8_ECRD_FFL_Pos 24 /*!< CCU8 ECRD: FFL Position */
\r
11750 #define CCU8_ECRD_FFL_Msk (0x01UL << CCU8_ECRD_FFL_Pos) /*!< CCU8 ECRD: FFL Mask */
\r
11752 /* ---------------------------------- CCU8_MIDR --------------------------------- */
\r
11753 #define CCU8_MIDR_MODR_Pos 0 /*!< CCU8 MIDR: MODR Position */
\r
11754 #define CCU8_MIDR_MODR_Msk (0x000000ffUL << CCU8_MIDR_MODR_Pos) /*!< CCU8 MIDR: MODR Mask */
\r
11755 #define CCU8_MIDR_MODT_Pos 8 /*!< CCU8 MIDR: MODT Position */
\r
11756 #define CCU8_MIDR_MODT_Msk (0x000000ffUL << CCU8_MIDR_MODT_Pos) /*!< CCU8 MIDR: MODT Mask */
\r
11757 #define CCU8_MIDR_MODN_Pos 16 /*!< CCU8 MIDR: MODN Position */
\r
11758 #define CCU8_MIDR_MODN_Msk (0x0000ffffUL << CCU8_MIDR_MODN_Pos) /*!< CCU8 MIDR: MODN Mask */
\r
11761 /* ================================================================================ */
\r
11762 /* ================ Group 'CCU8_CC8' Position & Mask ================ */
\r
11763 /* ================================================================================ */
\r
11766 /* -------------------------------- CCU8_CC8_INS -------------------------------- */
\r
11767 #define CCU8_CC8_INS_EV0IS_Pos 0 /*!< CCU8_CC8 INS: EV0IS Position */
\r
11768 #define CCU8_CC8_INS_EV0IS_Msk (0x0fUL << CCU8_CC8_INS_EV0IS_Pos) /*!< CCU8_CC8 INS: EV0IS Mask */
\r
11769 #define CCU8_CC8_INS_EV1IS_Pos 4 /*!< CCU8_CC8 INS: EV1IS Position */
\r
11770 #define CCU8_CC8_INS_EV1IS_Msk (0x0fUL << CCU8_CC8_INS_EV1IS_Pos) /*!< CCU8_CC8 INS: EV1IS Mask */
\r
11771 #define CCU8_CC8_INS_EV2IS_Pos 8 /*!< CCU8_CC8 INS: EV2IS Position */
\r
11772 #define CCU8_CC8_INS_EV2IS_Msk (0x0fUL << CCU8_CC8_INS_EV2IS_Pos) /*!< CCU8_CC8 INS: EV2IS Mask */
\r
11773 #define CCU8_CC8_INS_EV0EM_Pos 16 /*!< CCU8_CC8 INS: EV0EM Position */
\r
11774 #define CCU8_CC8_INS_EV0EM_Msk (0x03UL << CCU8_CC8_INS_EV0EM_Pos) /*!< CCU8_CC8 INS: EV0EM Mask */
\r
11775 #define CCU8_CC8_INS_EV1EM_Pos 18 /*!< CCU8_CC8 INS: EV1EM Position */
\r
11776 #define CCU8_CC8_INS_EV1EM_Msk (0x03UL << CCU8_CC8_INS_EV1EM_Pos) /*!< CCU8_CC8 INS: EV1EM Mask */
\r
11777 #define CCU8_CC8_INS_EV2EM_Pos 20 /*!< CCU8_CC8 INS: EV2EM Position */
\r
11778 #define CCU8_CC8_INS_EV2EM_Msk (0x03UL << CCU8_CC8_INS_EV2EM_Pos) /*!< CCU8_CC8 INS: EV2EM Mask */
\r
11779 #define CCU8_CC8_INS_EV0LM_Pos 22 /*!< CCU8_CC8 INS: EV0LM Position */
\r
11780 #define CCU8_CC8_INS_EV0LM_Msk (0x01UL << CCU8_CC8_INS_EV0LM_Pos) /*!< CCU8_CC8 INS: EV0LM Mask */
\r
11781 #define CCU8_CC8_INS_EV1LM_Pos 23 /*!< CCU8_CC8 INS: EV1LM Position */
\r
11782 #define CCU8_CC8_INS_EV1LM_Msk (0x01UL << CCU8_CC8_INS_EV1LM_Pos) /*!< CCU8_CC8 INS: EV1LM Mask */
\r
11783 #define CCU8_CC8_INS_EV2LM_Pos 24 /*!< CCU8_CC8 INS: EV2LM Position */
\r
11784 #define CCU8_CC8_INS_EV2LM_Msk (0x01UL << CCU8_CC8_INS_EV2LM_Pos) /*!< CCU8_CC8 INS: EV2LM Mask */
\r
11785 #define CCU8_CC8_INS_LPF0M_Pos 25 /*!< CCU8_CC8 INS: LPF0M Position */
\r
11786 #define CCU8_CC8_INS_LPF0M_Msk (0x03UL << CCU8_CC8_INS_LPF0M_Pos) /*!< CCU8_CC8 INS: LPF0M Mask */
\r
11787 #define CCU8_CC8_INS_LPF1M_Pos 27 /*!< CCU8_CC8 INS: LPF1M Position */
\r
11788 #define CCU8_CC8_INS_LPF1M_Msk (0x03UL << CCU8_CC8_INS_LPF1M_Pos) /*!< CCU8_CC8 INS: LPF1M Mask */
\r
11789 #define CCU8_CC8_INS_LPF2M_Pos 29 /*!< CCU8_CC8 INS: LPF2M Position */
\r
11790 #define CCU8_CC8_INS_LPF2M_Msk (0x03UL << CCU8_CC8_INS_LPF2M_Pos) /*!< CCU8_CC8 INS: LPF2M Mask */
\r
11792 /* -------------------------------- CCU8_CC8_CMC -------------------------------- */
\r
11793 #define CCU8_CC8_CMC_STRTS_Pos 0 /*!< CCU8_CC8 CMC: STRTS Position */
\r
11794 #define CCU8_CC8_CMC_STRTS_Msk (0x03UL << CCU8_CC8_CMC_STRTS_Pos) /*!< CCU8_CC8 CMC: STRTS Mask */
\r
11795 #define CCU8_CC8_CMC_ENDS_Pos 2 /*!< CCU8_CC8 CMC: ENDS Position */
\r
11796 #define CCU8_CC8_CMC_ENDS_Msk (0x03UL << CCU8_CC8_CMC_ENDS_Pos) /*!< CCU8_CC8 CMC: ENDS Mask */
\r
11797 #define CCU8_CC8_CMC_CAP0S_Pos 4 /*!< CCU8_CC8 CMC: CAP0S Position */
\r
11798 #define CCU8_CC8_CMC_CAP0S_Msk (0x03UL << CCU8_CC8_CMC_CAP0S_Pos) /*!< CCU8_CC8 CMC: CAP0S Mask */
\r
11799 #define CCU8_CC8_CMC_CAP1S_Pos 6 /*!< CCU8_CC8 CMC: CAP1S Position */
\r
11800 #define CCU8_CC8_CMC_CAP1S_Msk (0x03UL << CCU8_CC8_CMC_CAP1S_Pos) /*!< CCU8_CC8 CMC: CAP1S Mask */
\r
11801 #define CCU8_CC8_CMC_GATES_Pos 8 /*!< CCU8_CC8 CMC: GATES Position */
\r
11802 #define CCU8_CC8_CMC_GATES_Msk (0x03UL << CCU8_CC8_CMC_GATES_Pos) /*!< CCU8_CC8 CMC: GATES Mask */
\r
11803 #define CCU8_CC8_CMC_UDS_Pos 10 /*!< CCU8_CC8 CMC: UDS Position */
\r
11804 #define CCU8_CC8_CMC_UDS_Msk (0x03UL << CCU8_CC8_CMC_UDS_Pos) /*!< CCU8_CC8 CMC: UDS Mask */
\r
11805 #define CCU8_CC8_CMC_LDS_Pos 12 /*!< CCU8_CC8 CMC: LDS Position */
\r
11806 #define CCU8_CC8_CMC_LDS_Msk (0x03UL << CCU8_CC8_CMC_LDS_Pos) /*!< CCU8_CC8 CMC: LDS Mask */
\r
11807 #define CCU8_CC8_CMC_CNTS_Pos 14 /*!< CCU8_CC8 CMC: CNTS Position */
\r
11808 #define CCU8_CC8_CMC_CNTS_Msk (0x03UL << CCU8_CC8_CMC_CNTS_Pos) /*!< CCU8_CC8 CMC: CNTS Mask */
\r
11809 #define CCU8_CC8_CMC_OFS_Pos 16 /*!< CCU8_CC8 CMC: OFS Position */
\r
11810 #define CCU8_CC8_CMC_OFS_Msk (0x01UL << CCU8_CC8_CMC_OFS_Pos) /*!< CCU8_CC8 CMC: OFS Mask */
\r
11811 #define CCU8_CC8_CMC_TS_Pos 17 /*!< CCU8_CC8 CMC: TS Position */
\r
11812 #define CCU8_CC8_CMC_TS_Msk (0x01UL << CCU8_CC8_CMC_TS_Pos) /*!< CCU8_CC8 CMC: TS Mask */
\r
11813 #define CCU8_CC8_CMC_MOS_Pos 18 /*!< CCU8_CC8 CMC: MOS Position */
\r
11814 #define CCU8_CC8_CMC_MOS_Msk (0x03UL << CCU8_CC8_CMC_MOS_Pos) /*!< CCU8_CC8 CMC: MOS Mask */
\r
11815 #define CCU8_CC8_CMC_TCE_Pos 20 /*!< CCU8_CC8 CMC: TCE Position */
\r
11816 #define CCU8_CC8_CMC_TCE_Msk (0x01UL << CCU8_CC8_CMC_TCE_Pos) /*!< CCU8_CC8 CMC: TCE Mask */
\r
11818 /* -------------------------------- CCU8_CC8_TCST ------------------------------- */
\r
11819 #define CCU8_CC8_TCST_TRB_Pos 0 /*!< CCU8_CC8 TCST: TRB Position */
\r
11820 #define CCU8_CC8_TCST_TRB_Msk (0x01UL << CCU8_CC8_TCST_TRB_Pos) /*!< CCU8_CC8 TCST: TRB Mask */
\r
11821 #define CCU8_CC8_TCST_CDIR_Pos 1 /*!< CCU8_CC8 TCST: CDIR Position */
\r
11822 #define CCU8_CC8_TCST_CDIR_Msk (0x01UL << CCU8_CC8_TCST_CDIR_Pos) /*!< CCU8_CC8 TCST: CDIR Mask */
\r
11823 #define CCU8_CC8_TCST_DTR1_Pos 3 /*!< CCU8_CC8 TCST: DTR1 Position */
\r
11824 #define CCU8_CC8_TCST_DTR1_Msk (0x01UL << CCU8_CC8_TCST_DTR1_Pos) /*!< CCU8_CC8 TCST: DTR1 Mask */
\r
11825 #define CCU8_CC8_TCST_DTR2_Pos 4 /*!< CCU8_CC8 TCST: DTR2 Position */
\r
11826 #define CCU8_CC8_TCST_DTR2_Msk (0x01UL << CCU8_CC8_TCST_DTR2_Pos) /*!< CCU8_CC8 TCST: DTR2 Mask */
\r
11828 /* ------------------------------- CCU8_CC8_TCSET ------------------------------- */
\r
11829 #define CCU8_CC8_TCSET_TRBS_Pos 0 /*!< CCU8_CC8 TCSET: TRBS Position */
\r
11830 #define CCU8_CC8_TCSET_TRBS_Msk (0x01UL << CCU8_CC8_TCSET_TRBS_Pos) /*!< CCU8_CC8 TCSET: TRBS Mask */
\r
11832 /* ------------------------------- CCU8_CC8_TCCLR ------------------------------- */
\r
11833 #define CCU8_CC8_TCCLR_TRBC_Pos 0 /*!< CCU8_CC8 TCCLR: TRBC Position */
\r
11834 #define CCU8_CC8_TCCLR_TRBC_Msk (0x01UL << CCU8_CC8_TCCLR_TRBC_Pos) /*!< CCU8_CC8 TCCLR: TRBC Mask */
\r
11835 #define CCU8_CC8_TCCLR_TCC_Pos 1 /*!< CCU8_CC8 TCCLR: TCC Position */
\r
11836 #define CCU8_CC8_TCCLR_TCC_Msk (0x01UL << CCU8_CC8_TCCLR_TCC_Pos) /*!< CCU8_CC8 TCCLR: TCC Mask */
\r
11837 #define CCU8_CC8_TCCLR_DITC_Pos 2 /*!< CCU8_CC8 TCCLR: DITC Position */
\r
11838 #define CCU8_CC8_TCCLR_DITC_Msk (0x01UL << CCU8_CC8_TCCLR_DITC_Pos) /*!< CCU8_CC8 TCCLR: DITC Mask */
\r
11839 #define CCU8_CC8_TCCLR_DTC1C_Pos 3 /*!< CCU8_CC8 TCCLR: DTC1C Position */
\r
11840 #define CCU8_CC8_TCCLR_DTC1C_Msk (0x01UL << CCU8_CC8_TCCLR_DTC1C_Pos) /*!< CCU8_CC8 TCCLR: DTC1C Mask */
\r
11841 #define CCU8_CC8_TCCLR_DTC2C_Pos 4 /*!< CCU8_CC8 TCCLR: DTC2C Position */
\r
11842 #define CCU8_CC8_TCCLR_DTC2C_Msk (0x01UL << CCU8_CC8_TCCLR_DTC2C_Pos) /*!< CCU8_CC8 TCCLR: DTC2C Mask */
\r
11844 /* --------------------------------- CCU8_CC8_TC -------------------------------- */
\r
11845 #define CCU8_CC8_TC_TCM_Pos 0 /*!< CCU8_CC8 TC: TCM Position */
\r
11846 #define CCU8_CC8_TC_TCM_Msk (0x01UL << CCU8_CC8_TC_TCM_Pos) /*!< CCU8_CC8 TC: TCM Mask */
\r
11847 #define CCU8_CC8_TC_TSSM_Pos 1 /*!< CCU8_CC8 TC: TSSM Position */
\r
11848 #define CCU8_CC8_TC_TSSM_Msk (0x01UL << CCU8_CC8_TC_TSSM_Pos) /*!< CCU8_CC8 TC: TSSM Mask */
\r
11849 #define CCU8_CC8_TC_CLST_Pos 2 /*!< CCU8_CC8 TC: CLST Position */
\r
11850 #define CCU8_CC8_TC_CLST_Msk (0x01UL << CCU8_CC8_TC_CLST_Pos) /*!< CCU8_CC8 TC: CLST Mask */
\r
11851 #define CCU8_CC8_TC_CMOD_Pos 3 /*!< CCU8_CC8 TC: CMOD Position */
\r
11852 #define CCU8_CC8_TC_CMOD_Msk (0x01UL << CCU8_CC8_TC_CMOD_Pos) /*!< CCU8_CC8 TC: CMOD Mask */
\r
11853 #define CCU8_CC8_TC_ECM_Pos 4 /*!< CCU8_CC8 TC: ECM Position */
\r
11854 #define CCU8_CC8_TC_ECM_Msk (0x01UL << CCU8_CC8_TC_ECM_Pos) /*!< CCU8_CC8 TC: ECM Mask */
\r
11855 #define CCU8_CC8_TC_CAPC_Pos 5 /*!< CCU8_CC8 TC: CAPC Position */
\r
11856 #define CCU8_CC8_TC_CAPC_Msk (0x03UL << CCU8_CC8_TC_CAPC_Pos) /*!< CCU8_CC8 TC: CAPC Mask */
\r
11857 #define CCU8_CC8_TC_TLS_Pos 7 /*!< CCU8_CC8 TC: TLS Position */
\r
11858 #define CCU8_CC8_TC_TLS_Msk (0x01UL << CCU8_CC8_TC_TLS_Pos) /*!< CCU8_CC8 TC: TLS Mask */
\r
11859 #define CCU8_CC8_TC_ENDM_Pos 8 /*!< CCU8_CC8 TC: ENDM Position */
\r
11860 #define CCU8_CC8_TC_ENDM_Msk (0x03UL << CCU8_CC8_TC_ENDM_Pos) /*!< CCU8_CC8 TC: ENDM Mask */
\r
11861 #define CCU8_CC8_TC_STRM_Pos 10 /*!< CCU8_CC8 TC: STRM Position */
\r
11862 #define CCU8_CC8_TC_STRM_Msk (0x01UL << CCU8_CC8_TC_STRM_Pos) /*!< CCU8_CC8 TC: STRM Mask */
\r
11863 #define CCU8_CC8_TC_SCE_Pos 11 /*!< CCU8_CC8 TC: SCE Position */
\r
11864 #define CCU8_CC8_TC_SCE_Msk (0x01UL << CCU8_CC8_TC_SCE_Pos) /*!< CCU8_CC8 TC: SCE Mask */
\r
11865 #define CCU8_CC8_TC_CCS_Pos 12 /*!< CCU8_CC8 TC: CCS Position */
\r
11866 #define CCU8_CC8_TC_CCS_Msk (0x01UL << CCU8_CC8_TC_CCS_Pos) /*!< CCU8_CC8 TC: CCS Mask */
\r
11867 #define CCU8_CC8_TC_DITHE_Pos 13 /*!< CCU8_CC8 TC: DITHE Position */
\r
11868 #define CCU8_CC8_TC_DITHE_Msk (0x03UL << CCU8_CC8_TC_DITHE_Pos) /*!< CCU8_CC8 TC: DITHE Mask */
\r
11869 #define CCU8_CC8_TC_DIM_Pos 15 /*!< CCU8_CC8 TC: DIM Position */
\r
11870 #define CCU8_CC8_TC_DIM_Msk (0x01UL << CCU8_CC8_TC_DIM_Pos) /*!< CCU8_CC8 TC: DIM Mask */
\r
11871 #define CCU8_CC8_TC_FPE_Pos 16 /*!< CCU8_CC8 TC: FPE Position */
\r
11872 #define CCU8_CC8_TC_FPE_Msk (0x01UL << CCU8_CC8_TC_FPE_Pos) /*!< CCU8_CC8 TC: FPE Mask */
\r
11873 #define CCU8_CC8_TC_TRAPE0_Pos 17 /*!< CCU8_CC8 TC: TRAPE0 Position */
\r
11874 #define CCU8_CC8_TC_TRAPE0_Msk (0x01UL << CCU8_CC8_TC_TRAPE0_Pos) /*!< CCU8_CC8 TC: TRAPE0 Mask */
\r
11875 #define CCU8_CC8_TC_TRAPE1_Pos 18 /*!< CCU8_CC8 TC: TRAPE1 Position */
\r
11876 #define CCU8_CC8_TC_TRAPE1_Msk (0x01UL << CCU8_CC8_TC_TRAPE1_Pos) /*!< CCU8_CC8 TC: TRAPE1 Mask */
\r
11877 #define CCU8_CC8_TC_TRAPE2_Pos 19 /*!< CCU8_CC8 TC: TRAPE2 Position */
\r
11878 #define CCU8_CC8_TC_TRAPE2_Msk (0x01UL << CCU8_CC8_TC_TRAPE2_Pos) /*!< CCU8_CC8 TC: TRAPE2 Mask */
\r
11879 #define CCU8_CC8_TC_TRAPE3_Pos 20 /*!< CCU8_CC8 TC: TRAPE3 Position */
\r
11880 #define CCU8_CC8_TC_TRAPE3_Msk (0x01UL << CCU8_CC8_TC_TRAPE3_Pos) /*!< CCU8_CC8 TC: TRAPE3 Mask */
\r
11881 #define CCU8_CC8_TC_TRPSE_Pos 21 /*!< CCU8_CC8 TC: TRPSE Position */
\r
11882 #define CCU8_CC8_TC_TRPSE_Msk (0x01UL << CCU8_CC8_TC_TRPSE_Pos) /*!< CCU8_CC8 TC: TRPSE Mask */
\r
11883 #define CCU8_CC8_TC_TRPSW_Pos 22 /*!< CCU8_CC8 TC: TRPSW Position */
\r
11884 #define CCU8_CC8_TC_TRPSW_Msk (0x01UL << CCU8_CC8_TC_TRPSW_Pos) /*!< CCU8_CC8 TC: TRPSW Mask */
\r
11885 #define CCU8_CC8_TC_EMS_Pos 23 /*!< CCU8_CC8 TC: EMS Position */
\r
11886 #define CCU8_CC8_TC_EMS_Msk (0x01UL << CCU8_CC8_TC_EMS_Pos) /*!< CCU8_CC8 TC: EMS Mask */
\r
11887 #define CCU8_CC8_TC_EMT_Pos 24 /*!< CCU8_CC8 TC: EMT Position */
\r
11888 #define CCU8_CC8_TC_EMT_Msk (0x01UL << CCU8_CC8_TC_EMT_Pos) /*!< CCU8_CC8 TC: EMT Mask */
\r
11889 #define CCU8_CC8_TC_MCME1_Pos 25 /*!< CCU8_CC8 TC: MCME1 Position */
\r
11890 #define CCU8_CC8_TC_MCME1_Msk (0x01UL << CCU8_CC8_TC_MCME1_Pos) /*!< CCU8_CC8 TC: MCME1 Mask */
\r
11891 #define CCU8_CC8_TC_MCME2_Pos 26 /*!< CCU8_CC8 TC: MCME2 Position */
\r
11892 #define CCU8_CC8_TC_MCME2_Msk (0x01UL << CCU8_CC8_TC_MCME2_Pos) /*!< CCU8_CC8 TC: MCME2 Mask */
\r
11893 #define CCU8_CC8_TC_EME_Pos 27 /*!< CCU8_CC8 TC: EME Position */
\r
11894 #define CCU8_CC8_TC_EME_Msk (0x03UL << CCU8_CC8_TC_EME_Pos) /*!< CCU8_CC8 TC: EME Mask */
\r
11895 #define CCU8_CC8_TC_STOS_Pos 29 /*!< CCU8_CC8 TC: STOS Position */
\r
11896 #define CCU8_CC8_TC_STOS_Msk (0x03UL << CCU8_CC8_TC_STOS_Pos) /*!< CCU8_CC8 TC: STOS Mask */
\r
11898 /* -------------------------------- CCU8_CC8_PSL -------------------------------- */
\r
11899 #define CCU8_CC8_PSL_PSL11_Pos 0 /*!< CCU8_CC8 PSL: PSL11 Position */
\r
11900 #define CCU8_CC8_PSL_PSL11_Msk (0x01UL << CCU8_CC8_PSL_PSL11_Pos) /*!< CCU8_CC8 PSL: PSL11 Mask */
\r
11901 #define CCU8_CC8_PSL_PSL12_Pos 1 /*!< CCU8_CC8 PSL: PSL12 Position */
\r
11902 #define CCU8_CC8_PSL_PSL12_Msk (0x01UL << CCU8_CC8_PSL_PSL12_Pos) /*!< CCU8_CC8 PSL: PSL12 Mask */
\r
11903 #define CCU8_CC8_PSL_PSL21_Pos 2 /*!< CCU8_CC8 PSL: PSL21 Position */
\r
11904 #define CCU8_CC8_PSL_PSL21_Msk (0x01UL << CCU8_CC8_PSL_PSL21_Pos) /*!< CCU8_CC8 PSL: PSL21 Mask */
\r
11905 #define CCU8_CC8_PSL_PSL22_Pos 3 /*!< CCU8_CC8 PSL: PSL22 Position */
\r
11906 #define CCU8_CC8_PSL_PSL22_Msk (0x01UL << CCU8_CC8_PSL_PSL22_Pos) /*!< CCU8_CC8 PSL: PSL22 Mask */
\r
11908 /* -------------------------------- CCU8_CC8_DIT -------------------------------- */
\r
11909 #define CCU8_CC8_DIT_DCV_Pos 0 /*!< CCU8_CC8 DIT: DCV Position */
\r
11910 #define CCU8_CC8_DIT_DCV_Msk (0x0fUL << CCU8_CC8_DIT_DCV_Pos) /*!< CCU8_CC8 DIT: DCV Mask */
\r
11911 #define CCU8_CC8_DIT_DCNT_Pos 8 /*!< CCU8_CC8 DIT: DCNT Position */
\r
11912 #define CCU8_CC8_DIT_DCNT_Msk (0x0fUL << CCU8_CC8_DIT_DCNT_Pos) /*!< CCU8_CC8 DIT: DCNT Mask */
\r
11914 /* -------------------------------- CCU8_CC8_DITS ------------------------------- */
\r
11915 #define CCU8_CC8_DITS_DCVS_Pos 0 /*!< CCU8_CC8 DITS: DCVS Position */
\r
11916 #define CCU8_CC8_DITS_DCVS_Msk (0x0fUL << CCU8_CC8_DITS_DCVS_Pos) /*!< CCU8_CC8 DITS: DCVS Mask */
\r
11918 /* -------------------------------- CCU8_CC8_PSC -------------------------------- */
\r
11919 #define CCU8_CC8_PSC_PSIV_Pos 0 /*!< CCU8_CC8 PSC: PSIV Position */
\r
11920 #define CCU8_CC8_PSC_PSIV_Msk (0x0fUL << CCU8_CC8_PSC_PSIV_Pos) /*!< CCU8_CC8 PSC: PSIV Mask */
\r
11922 /* -------------------------------- CCU8_CC8_FPC -------------------------------- */
\r
11923 #define CCU8_CC8_FPC_PCMP_Pos 0 /*!< CCU8_CC8 FPC: PCMP Position */
\r
11924 #define CCU8_CC8_FPC_PCMP_Msk (0x0fUL << CCU8_CC8_FPC_PCMP_Pos) /*!< CCU8_CC8 FPC: PCMP Mask */
\r
11925 #define CCU8_CC8_FPC_PVAL_Pos 8 /*!< CCU8_CC8 FPC: PVAL Position */
\r
11926 #define CCU8_CC8_FPC_PVAL_Msk (0x0fUL << CCU8_CC8_FPC_PVAL_Pos) /*!< CCU8_CC8 FPC: PVAL Mask */
\r
11928 /* -------------------------------- CCU8_CC8_FPCS ------------------------------- */
\r
11929 #define CCU8_CC8_FPCS_PCMP_Pos 0 /*!< CCU8_CC8 FPCS: PCMP Position */
\r
11930 #define CCU8_CC8_FPCS_PCMP_Msk (0x0fUL << CCU8_CC8_FPCS_PCMP_Pos) /*!< CCU8_CC8 FPCS: PCMP Mask */
\r
11932 /* --------------------------------- CCU8_CC8_PR -------------------------------- */
\r
11933 #define CCU8_CC8_PR_PR_Pos 0 /*!< CCU8_CC8 PR: PR Position */
\r
11934 #define CCU8_CC8_PR_PR_Msk (0x0000ffffUL << CCU8_CC8_PR_PR_Pos) /*!< CCU8_CC8 PR: PR Mask */
\r
11936 /* -------------------------------- CCU8_CC8_PRS -------------------------------- */
\r
11937 #define CCU8_CC8_PRS_PRS_Pos 0 /*!< CCU8_CC8 PRS: PRS Position */
\r
11938 #define CCU8_CC8_PRS_PRS_Msk (0x0000ffffUL << CCU8_CC8_PRS_PRS_Pos) /*!< CCU8_CC8 PRS: PRS Mask */
\r
11940 /* -------------------------------- CCU8_CC8_CR1 -------------------------------- */
\r
11941 #define CCU8_CC8_CR1_CR1_Pos 0 /*!< CCU8_CC8 CR1: CR1 Position */
\r
11942 #define CCU8_CC8_CR1_CR1_Msk (0x0000ffffUL << CCU8_CC8_CR1_CR1_Pos) /*!< CCU8_CC8 CR1: CR1 Mask */
\r
11944 /* -------------------------------- CCU8_CC8_CR1S ------------------------------- */
\r
11945 #define CCU8_CC8_CR1S_CR1S_Pos 0 /*!< CCU8_CC8 CR1S: CR1S Position */
\r
11946 #define CCU8_CC8_CR1S_CR1S_Msk (0x0000ffffUL << CCU8_CC8_CR1S_CR1S_Pos) /*!< CCU8_CC8 CR1S: CR1S Mask */
\r
11948 /* -------------------------------- CCU8_CC8_CR2 -------------------------------- */
\r
11949 #define CCU8_CC8_CR2_CR2_Pos 0 /*!< CCU8_CC8 CR2: CR2 Position */
\r
11950 #define CCU8_CC8_CR2_CR2_Msk (0x0000ffffUL << CCU8_CC8_CR2_CR2_Pos) /*!< CCU8_CC8 CR2: CR2 Mask */
\r
11952 /* -------------------------------- CCU8_CC8_CR2S ------------------------------- */
\r
11953 #define CCU8_CC8_CR2S_CR2S_Pos 0 /*!< CCU8_CC8 CR2S: CR2S Position */
\r
11954 #define CCU8_CC8_CR2S_CR2S_Msk (0x0000ffffUL << CCU8_CC8_CR2S_CR2S_Pos) /*!< CCU8_CC8 CR2S: CR2S Mask */
\r
11956 /* -------------------------------- CCU8_CC8_CHC -------------------------------- */
\r
11957 #define CCU8_CC8_CHC_ASE_Pos 0 /*!< CCU8_CC8 CHC: ASE Position */
\r
11958 #define CCU8_CC8_CHC_ASE_Msk (0x01UL << CCU8_CC8_CHC_ASE_Pos) /*!< CCU8_CC8 CHC: ASE Mask */
\r
11959 #define CCU8_CC8_CHC_OCS1_Pos 1 /*!< CCU8_CC8 CHC: OCS1 Position */
\r
11960 #define CCU8_CC8_CHC_OCS1_Msk (0x01UL << CCU8_CC8_CHC_OCS1_Pos) /*!< CCU8_CC8 CHC: OCS1 Mask */
\r
11961 #define CCU8_CC8_CHC_OCS2_Pos 2 /*!< CCU8_CC8 CHC: OCS2 Position */
\r
11962 #define CCU8_CC8_CHC_OCS2_Msk (0x01UL << CCU8_CC8_CHC_OCS2_Pos) /*!< CCU8_CC8 CHC: OCS2 Mask */
\r
11963 #define CCU8_CC8_CHC_OCS3_Pos 3 /*!< CCU8_CC8 CHC: OCS3 Position */
\r
11964 #define CCU8_CC8_CHC_OCS3_Msk (0x01UL << CCU8_CC8_CHC_OCS3_Pos) /*!< CCU8_CC8 CHC: OCS3 Mask */
\r
11965 #define CCU8_CC8_CHC_OCS4_Pos 4 /*!< CCU8_CC8 CHC: OCS4 Position */
\r
11966 #define CCU8_CC8_CHC_OCS4_Msk (0x01UL << CCU8_CC8_CHC_OCS4_Pos) /*!< CCU8_CC8 CHC: OCS4 Mask */
\r
11968 /* -------------------------------- CCU8_CC8_DTC -------------------------------- */
\r
11969 #define CCU8_CC8_DTC_DTE1_Pos 0 /*!< CCU8_CC8 DTC: DTE1 Position */
\r
11970 #define CCU8_CC8_DTC_DTE1_Msk (0x01UL << CCU8_CC8_DTC_DTE1_Pos) /*!< CCU8_CC8 DTC: DTE1 Mask */
\r
11971 #define CCU8_CC8_DTC_DTE2_Pos 1 /*!< CCU8_CC8 DTC: DTE2 Position */
\r
11972 #define CCU8_CC8_DTC_DTE2_Msk (0x01UL << CCU8_CC8_DTC_DTE2_Pos) /*!< CCU8_CC8 DTC: DTE2 Mask */
\r
11973 #define CCU8_CC8_DTC_DCEN1_Pos 2 /*!< CCU8_CC8 DTC: DCEN1 Position */
\r
11974 #define CCU8_CC8_DTC_DCEN1_Msk (0x01UL << CCU8_CC8_DTC_DCEN1_Pos) /*!< CCU8_CC8 DTC: DCEN1 Mask */
\r
11975 #define CCU8_CC8_DTC_DCEN2_Pos 3 /*!< CCU8_CC8 DTC: DCEN2 Position */
\r
11976 #define CCU8_CC8_DTC_DCEN2_Msk (0x01UL << CCU8_CC8_DTC_DCEN2_Pos) /*!< CCU8_CC8 DTC: DCEN2 Mask */
\r
11977 #define CCU8_CC8_DTC_DCEN3_Pos 4 /*!< CCU8_CC8 DTC: DCEN3 Position */
\r
11978 #define CCU8_CC8_DTC_DCEN3_Msk (0x01UL << CCU8_CC8_DTC_DCEN3_Pos) /*!< CCU8_CC8 DTC: DCEN3 Mask */
\r
11979 #define CCU8_CC8_DTC_DCEN4_Pos 5 /*!< CCU8_CC8 DTC: DCEN4 Position */
\r
11980 #define CCU8_CC8_DTC_DCEN4_Msk (0x01UL << CCU8_CC8_DTC_DCEN4_Pos) /*!< CCU8_CC8 DTC: DCEN4 Mask */
\r
11981 #define CCU8_CC8_DTC_DTCC_Pos 6 /*!< CCU8_CC8 DTC: DTCC Position */
\r
11982 #define CCU8_CC8_DTC_DTCC_Msk (0x03UL << CCU8_CC8_DTC_DTCC_Pos) /*!< CCU8_CC8 DTC: DTCC Mask */
\r
11984 /* -------------------------------- CCU8_CC8_DC1R ------------------------------- */
\r
11985 #define CCU8_CC8_DC1R_DT1R_Pos 0 /*!< CCU8_CC8 DC1R: DT1R Position */
\r
11986 #define CCU8_CC8_DC1R_DT1R_Msk (0x000000ffUL << CCU8_CC8_DC1R_DT1R_Pos) /*!< CCU8_CC8 DC1R: DT1R Mask */
\r
11987 #define CCU8_CC8_DC1R_DT1F_Pos 8 /*!< CCU8_CC8 DC1R: DT1F Position */
\r
11988 #define CCU8_CC8_DC1R_DT1F_Msk (0x000000ffUL << CCU8_CC8_DC1R_DT1F_Pos) /*!< CCU8_CC8 DC1R: DT1F Mask */
\r
11990 /* -------------------------------- CCU8_CC8_DC2R ------------------------------- */
\r
11991 #define CCU8_CC8_DC2R_DT2R_Pos 0 /*!< CCU8_CC8 DC2R: DT2R Position */
\r
11992 #define CCU8_CC8_DC2R_DT2R_Msk (0x000000ffUL << CCU8_CC8_DC2R_DT2R_Pos) /*!< CCU8_CC8 DC2R: DT2R Mask */
\r
11993 #define CCU8_CC8_DC2R_DT2F_Pos 8 /*!< CCU8_CC8 DC2R: DT2F Position */
\r
11994 #define CCU8_CC8_DC2R_DT2F_Msk (0x000000ffUL << CCU8_CC8_DC2R_DT2F_Pos) /*!< CCU8_CC8 DC2R: DT2F Mask */
\r
11996 /* ------------------------------- CCU8_CC8_TIMER ------------------------------- */
\r
11997 #define CCU8_CC8_TIMER_TVAL_Pos 0 /*!< CCU8_CC8 TIMER: TVAL Position */
\r
11998 #define CCU8_CC8_TIMER_TVAL_Msk (0x0000ffffUL << CCU8_CC8_TIMER_TVAL_Pos) /*!< CCU8_CC8 TIMER: TVAL Mask */
\r
12000 /* --------------------------------- CCU8_CC8_CV -------------------------------- */
\r
12001 #define CCU8_CC8_CV_CAPTV_Pos 0 /*!< CCU8_CC8 CV: CAPTV Position */
\r
12002 #define CCU8_CC8_CV_CAPTV_Msk (0x0000ffffUL << CCU8_CC8_CV_CAPTV_Pos) /*!< CCU8_CC8 CV: CAPTV Mask */
\r
12003 #define CCU8_CC8_CV_FPCV_Pos 16 /*!< CCU8_CC8 CV: FPCV Position */
\r
12004 #define CCU8_CC8_CV_FPCV_Msk (0x0fUL << CCU8_CC8_CV_FPCV_Pos) /*!< CCU8_CC8 CV: FPCV Mask */
\r
12005 #define CCU8_CC8_CV_FFL_Pos 20 /*!< CCU8_CC8 CV: FFL Position */
\r
12006 #define CCU8_CC8_CV_FFL_Msk (0x01UL << CCU8_CC8_CV_FFL_Pos) /*!< CCU8_CC8 CV: FFL Mask */
\r
12008 /* -------------------------------- CCU8_CC8_INTS ------------------------------- */
\r
12009 #define CCU8_CC8_INTS_PMUS_Pos 0 /*!< CCU8_CC8 INTS: PMUS Position */
\r
12010 #define CCU8_CC8_INTS_PMUS_Msk (0x01UL << CCU8_CC8_INTS_PMUS_Pos) /*!< CCU8_CC8 INTS: PMUS Mask */
\r
12011 #define CCU8_CC8_INTS_OMDS_Pos 1 /*!< CCU8_CC8 INTS: OMDS Position */
\r
12012 #define CCU8_CC8_INTS_OMDS_Msk (0x01UL << CCU8_CC8_INTS_OMDS_Pos) /*!< CCU8_CC8 INTS: OMDS Mask */
\r
12013 #define CCU8_CC8_INTS_CMU1S_Pos 2 /*!< CCU8_CC8 INTS: CMU1S Position */
\r
12014 #define CCU8_CC8_INTS_CMU1S_Msk (0x01UL << CCU8_CC8_INTS_CMU1S_Pos) /*!< CCU8_CC8 INTS: CMU1S Mask */
\r
12015 #define CCU8_CC8_INTS_CMD1S_Pos 3 /*!< CCU8_CC8 INTS: CMD1S Position */
\r
12016 #define CCU8_CC8_INTS_CMD1S_Msk (0x01UL << CCU8_CC8_INTS_CMD1S_Pos) /*!< CCU8_CC8 INTS: CMD1S Mask */
\r
12017 #define CCU8_CC8_INTS_CMU2S_Pos 4 /*!< CCU8_CC8 INTS: CMU2S Position */
\r
12018 #define CCU8_CC8_INTS_CMU2S_Msk (0x01UL << CCU8_CC8_INTS_CMU2S_Pos) /*!< CCU8_CC8 INTS: CMU2S Mask */
\r
12019 #define CCU8_CC8_INTS_CMD2S_Pos 5 /*!< CCU8_CC8 INTS: CMD2S Position */
\r
12020 #define CCU8_CC8_INTS_CMD2S_Msk (0x01UL << CCU8_CC8_INTS_CMD2S_Pos) /*!< CCU8_CC8 INTS: CMD2S Mask */
\r
12021 #define CCU8_CC8_INTS_E0AS_Pos 8 /*!< CCU8_CC8 INTS: E0AS Position */
\r
12022 #define CCU8_CC8_INTS_E0AS_Msk (0x01UL << CCU8_CC8_INTS_E0AS_Pos) /*!< CCU8_CC8 INTS: E0AS Mask */
\r
12023 #define CCU8_CC8_INTS_E1AS_Pos 9 /*!< CCU8_CC8 INTS: E1AS Position */
\r
12024 #define CCU8_CC8_INTS_E1AS_Msk (0x01UL << CCU8_CC8_INTS_E1AS_Pos) /*!< CCU8_CC8 INTS: E1AS Mask */
\r
12025 #define CCU8_CC8_INTS_E2AS_Pos 10 /*!< CCU8_CC8 INTS: E2AS Position */
\r
12026 #define CCU8_CC8_INTS_E2AS_Msk (0x01UL << CCU8_CC8_INTS_E2AS_Pos) /*!< CCU8_CC8 INTS: E2AS Mask */
\r
12027 #define CCU8_CC8_INTS_TRPF_Pos 11 /*!< CCU8_CC8 INTS: TRPF Position */
\r
12028 #define CCU8_CC8_INTS_TRPF_Msk (0x01UL << CCU8_CC8_INTS_TRPF_Pos) /*!< CCU8_CC8 INTS: TRPF Mask */
\r
12030 /* -------------------------------- CCU8_CC8_INTE ------------------------------- */
\r
12031 #define CCU8_CC8_INTE_PME_Pos 0 /*!< CCU8_CC8 INTE: PME Position */
\r
12032 #define CCU8_CC8_INTE_PME_Msk (0x01UL << CCU8_CC8_INTE_PME_Pos) /*!< CCU8_CC8 INTE: PME Mask */
\r
12033 #define CCU8_CC8_INTE_OME_Pos 1 /*!< CCU8_CC8 INTE: OME Position */
\r
12034 #define CCU8_CC8_INTE_OME_Msk (0x01UL << CCU8_CC8_INTE_OME_Pos) /*!< CCU8_CC8 INTE: OME Mask */
\r
12035 #define CCU8_CC8_INTE_CMU1E_Pos 2 /*!< CCU8_CC8 INTE: CMU1E Position */
\r
12036 #define CCU8_CC8_INTE_CMU1E_Msk (0x01UL << CCU8_CC8_INTE_CMU1E_Pos) /*!< CCU8_CC8 INTE: CMU1E Mask */
\r
12037 #define CCU8_CC8_INTE_CMD1E_Pos 3 /*!< CCU8_CC8 INTE: CMD1E Position */
\r
12038 #define CCU8_CC8_INTE_CMD1E_Msk (0x01UL << CCU8_CC8_INTE_CMD1E_Pos) /*!< CCU8_CC8 INTE: CMD1E Mask */
\r
12039 #define CCU8_CC8_INTE_CMU2E_Pos 4 /*!< CCU8_CC8 INTE: CMU2E Position */
\r
12040 #define CCU8_CC8_INTE_CMU2E_Msk (0x01UL << CCU8_CC8_INTE_CMU2E_Pos) /*!< CCU8_CC8 INTE: CMU2E Mask */
\r
12041 #define CCU8_CC8_INTE_CMD2E_Pos 5 /*!< CCU8_CC8 INTE: CMD2E Position */
\r
12042 #define CCU8_CC8_INTE_CMD2E_Msk (0x01UL << CCU8_CC8_INTE_CMD2E_Pos) /*!< CCU8_CC8 INTE: CMD2E Mask */
\r
12043 #define CCU8_CC8_INTE_E0AE_Pos 8 /*!< CCU8_CC8 INTE: E0AE Position */
\r
12044 #define CCU8_CC8_INTE_E0AE_Msk (0x01UL << CCU8_CC8_INTE_E0AE_Pos) /*!< CCU8_CC8 INTE: E0AE Mask */
\r
12045 #define CCU8_CC8_INTE_E1AE_Pos 9 /*!< CCU8_CC8 INTE: E1AE Position */
\r
12046 #define CCU8_CC8_INTE_E1AE_Msk (0x01UL << CCU8_CC8_INTE_E1AE_Pos) /*!< CCU8_CC8 INTE: E1AE Mask */
\r
12047 #define CCU8_CC8_INTE_E2AE_Pos 10 /*!< CCU8_CC8 INTE: E2AE Position */
\r
12048 #define CCU8_CC8_INTE_E2AE_Msk (0x01UL << CCU8_CC8_INTE_E2AE_Pos) /*!< CCU8_CC8 INTE: E2AE Mask */
\r
12050 /* -------------------------------- CCU8_CC8_SRS -------------------------------- */
\r
12051 #define CCU8_CC8_SRS_POSR_Pos 0 /*!< CCU8_CC8 SRS: POSR Position */
\r
12052 #define CCU8_CC8_SRS_POSR_Msk (0x03UL << CCU8_CC8_SRS_POSR_Pos) /*!< CCU8_CC8 SRS: POSR Mask */
\r
12053 #define CCU8_CC8_SRS_CM1SR_Pos 2 /*!< CCU8_CC8 SRS: CM1SR Position */
\r
12054 #define CCU8_CC8_SRS_CM1SR_Msk (0x03UL << CCU8_CC8_SRS_CM1SR_Pos) /*!< CCU8_CC8 SRS: CM1SR Mask */
\r
12055 #define CCU8_CC8_SRS_CM2SR_Pos 4 /*!< CCU8_CC8 SRS: CM2SR Position */
\r
12056 #define CCU8_CC8_SRS_CM2SR_Msk (0x03UL << CCU8_CC8_SRS_CM2SR_Pos) /*!< CCU8_CC8 SRS: CM2SR Mask */
\r
12057 #define CCU8_CC8_SRS_E0SR_Pos 8 /*!< CCU8_CC8 SRS: E0SR Position */
\r
12058 #define CCU8_CC8_SRS_E0SR_Msk (0x03UL << CCU8_CC8_SRS_E0SR_Pos) /*!< CCU8_CC8 SRS: E0SR Mask */
\r
12059 #define CCU8_CC8_SRS_E1SR_Pos 10 /*!< CCU8_CC8 SRS: E1SR Position */
\r
12060 #define CCU8_CC8_SRS_E1SR_Msk (0x03UL << CCU8_CC8_SRS_E1SR_Pos) /*!< CCU8_CC8 SRS: E1SR Mask */
\r
12061 #define CCU8_CC8_SRS_E2SR_Pos 12 /*!< CCU8_CC8 SRS: E2SR Position */
\r
12062 #define CCU8_CC8_SRS_E2SR_Msk (0x03UL << CCU8_CC8_SRS_E2SR_Pos) /*!< CCU8_CC8 SRS: E2SR Mask */
\r
12064 /* -------------------------------- CCU8_CC8_SWS -------------------------------- */
\r
12065 #define CCU8_CC8_SWS_SPM_Pos 0 /*!< CCU8_CC8 SWS: SPM Position */
\r
12066 #define CCU8_CC8_SWS_SPM_Msk (0x01UL << CCU8_CC8_SWS_SPM_Pos) /*!< CCU8_CC8 SWS: SPM Mask */
\r
12067 #define CCU8_CC8_SWS_SOM_Pos 1 /*!< CCU8_CC8 SWS: SOM Position */
\r
12068 #define CCU8_CC8_SWS_SOM_Msk (0x01UL << CCU8_CC8_SWS_SOM_Pos) /*!< CCU8_CC8 SWS: SOM Mask */
\r
12069 #define CCU8_CC8_SWS_SCM1U_Pos 2 /*!< CCU8_CC8 SWS: SCM1U Position */
\r
12070 #define CCU8_CC8_SWS_SCM1U_Msk (0x01UL << CCU8_CC8_SWS_SCM1U_Pos) /*!< CCU8_CC8 SWS: SCM1U Mask */
\r
12071 #define CCU8_CC8_SWS_SCM1D_Pos 3 /*!< CCU8_CC8 SWS: SCM1D Position */
\r
12072 #define CCU8_CC8_SWS_SCM1D_Msk (0x01UL << CCU8_CC8_SWS_SCM1D_Pos) /*!< CCU8_CC8 SWS: SCM1D Mask */
\r
12073 #define CCU8_CC8_SWS_SCM2U_Pos 4 /*!< CCU8_CC8 SWS: SCM2U Position */
\r
12074 #define CCU8_CC8_SWS_SCM2U_Msk (0x01UL << CCU8_CC8_SWS_SCM2U_Pos) /*!< CCU8_CC8 SWS: SCM2U Mask */
\r
12075 #define CCU8_CC8_SWS_SCM2D_Pos 5 /*!< CCU8_CC8 SWS: SCM2D Position */
\r
12076 #define CCU8_CC8_SWS_SCM2D_Msk (0x01UL << CCU8_CC8_SWS_SCM2D_Pos) /*!< CCU8_CC8 SWS: SCM2D Mask */
\r
12077 #define CCU8_CC8_SWS_SE0A_Pos 8 /*!< CCU8_CC8 SWS: SE0A Position */
\r
12078 #define CCU8_CC8_SWS_SE0A_Msk (0x01UL << CCU8_CC8_SWS_SE0A_Pos) /*!< CCU8_CC8 SWS: SE0A Mask */
\r
12079 #define CCU8_CC8_SWS_SE1A_Pos 9 /*!< CCU8_CC8 SWS: SE1A Position */
\r
12080 #define CCU8_CC8_SWS_SE1A_Msk (0x01UL << CCU8_CC8_SWS_SE1A_Pos) /*!< CCU8_CC8 SWS: SE1A Mask */
\r
12081 #define CCU8_CC8_SWS_SE2A_Pos 10 /*!< CCU8_CC8 SWS: SE2A Position */
\r
12082 #define CCU8_CC8_SWS_SE2A_Msk (0x01UL << CCU8_CC8_SWS_SE2A_Pos) /*!< CCU8_CC8 SWS: SE2A Mask */
\r
12083 #define CCU8_CC8_SWS_STRPF_Pos 11 /*!< CCU8_CC8 SWS: STRPF Position */
\r
12084 #define CCU8_CC8_SWS_STRPF_Msk (0x01UL << CCU8_CC8_SWS_STRPF_Pos) /*!< CCU8_CC8 SWS: STRPF Mask */
\r
12086 /* -------------------------------- CCU8_CC8_SWR -------------------------------- */
\r
12087 #define CCU8_CC8_SWR_RPM_Pos 0 /*!< CCU8_CC8 SWR: RPM Position */
\r
12088 #define CCU8_CC8_SWR_RPM_Msk (0x01UL << CCU8_CC8_SWR_RPM_Pos) /*!< CCU8_CC8 SWR: RPM Mask */
\r
12089 #define CCU8_CC8_SWR_ROM_Pos 1 /*!< CCU8_CC8 SWR: ROM Position */
\r
12090 #define CCU8_CC8_SWR_ROM_Msk (0x01UL << CCU8_CC8_SWR_ROM_Pos) /*!< CCU8_CC8 SWR: ROM Mask */
\r
12091 #define CCU8_CC8_SWR_RCM1U_Pos 2 /*!< CCU8_CC8 SWR: RCM1U Position */
\r
12092 #define CCU8_CC8_SWR_RCM1U_Msk (0x01UL << CCU8_CC8_SWR_RCM1U_Pos) /*!< CCU8_CC8 SWR: RCM1U Mask */
\r
12093 #define CCU8_CC8_SWR_RCM1D_Pos 3 /*!< CCU8_CC8 SWR: RCM1D Position */
\r
12094 #define CCU8_CC8_SWR_RCM1D_Msk (0x01UL << CCU8_CC8_SWR_RCM1D_Pos) /*!< CCU8_CC8 SWR: RCM1D Mask */
\r
12095 #define CCU8_CC8_SWR_RCM2U_Pos 4 /*!< CCU8_CC8 SWR: RCM2U Position */
\r
12096 #define CCU8_CC8_SWR_RCM2U_Msk (0x01UL << CCU8_CC8_SWR_RCM2U_Pos) /*!< CCU8_CC8 SWR: RCM2U Mask */
\r
12097 #define CCU8_CC8_SWR_RCM2D_Pos 5 /*!< CCU8_CC8 SWR: RCM2D Position */
\r
12098 #define CCU8_CC8_SWR_RCM2D_Msk (0x01UL << CCU8_CC8_SWR_RCM2D_Pos) /*!< CCU8_CC8 SWR: RCM2D Mask */
\r
12099 #define CCU8_CC8_SWR_RE0A_Pos 8 /*!< CCU8_CC8 SWR: RE0A Position */
\r
12100 #define CCU8_CC8_SWR_RE0A_Msk (0x01UL << CCU8_CC8_SWR_RE0A_Pos) /*!< CCU8_CC8 SWR: RE0A Mask */
\r
12101 #define CCU8_CC8_SWR_RE1A_Pos 9 /*!< CCU8_CC8 SWR: RE1A Position */
\r
12102 #define CCU8_CC8_SWR_RE1A_Msk (0x01UL << CCU8_CC8_SWR_RE1A_Pos) /*!< CCU8_CC8 SWR: RE1A Mask */
\r
12103 #define CCU8_CC8_SWR_RE2A_Pos 10 /*!< CCU8_CC8 SWR: RE2A Position */
\r
12104 #define CCU8_CC8_SWR_RE2A_Msk (0x01UL << CCU8_CC8_SWR_RE2A_Pos) /*!< CCU8_CC8 SWR: RE2A Mask */
\r
12105 #define CCU8_CC8_SWR_RTRPF_Pos 11 /*!< CCU8_CC8 SWR: RTRPF Position */
\r
12106 #define CCU8_CC8_SWR_RTRPF_Msk (0x01UL << CCU8_CC8_SWR_RTRPF_Pos) /*!< CCU8_CC8 SWR: RTRPF Mask */
\r
12109 /* ================================================================================ */
\r
12110 /* ================ struct 'HRPWM0' Position & Mask ================ */
\r
12111 /* ================================================================================ */
\r
12114 /* -------------------------------- HRPWM0_HRBSC -------------------------------- */
\r
12115 #define HRPWM0_HRBSC_SUSCFG_Pos 0 /*!< HRPWM0 HRBSC: SUSCFG Position */
\r
12116 #define HRPWM0_HRBSC_SUSCFG_Msk (0x07UL << HRPWM0_HRBSC_SUSCFG_Pos) /*!< HRPWM0 HRBSC: SUSCFG Mask */
\r
12117 #define HRPWM0_HRBSC_HRBE_Pos 8 /*!< HRPWM0 HRBSC: HRBE Position */
\r
12118 #define HRPWM0_HRBSC_HRBE_Msk (0x01UL << HRPWM0_HRBSC_HRBE_Pos) /*!< HRPWM0 HRBSC: HRBE Mask */
\r
12120 /* --------------------------------- HRPWM0_MIDR -------------------------------- */
\r
12121 #define HRPWM0_MIDR_MODR_Pos 0 /*!< HRPWM0 MIDR: MODR Position */
\r
12122 #define HRPWM0_MIDR_MODR_Msk (0x000000ffUL << HRPWM0_MIDR_MODR_Pos) /*!< HRPWM0 MIDR: MODR Mask */
\r
12123 #define HRPWM0_MIDR_MODT_Pos 8 /*!< HRPWM0 MIDR: MODT Position */
\r
12124 #define HRPWM0_MIDR_MODT_Msk (0x000000ffUL << HRPWM0_MIDR_MODT_Pos) /*!< HRPWM0 MIDR: MODT Mask */
\r
12125 #define HRPWM0_MIDR_MODN_Pos 16 /*!< HRPWM0 MIDR: MODN Position */
\r
12126 #define HRPWM0_MIDR_MODN_Msk (0x0000ffffUL << HRPWM0_MIDR_MODN_Pos) /*!< HRPWM0 MIDR: MODN Mask */
\r
12128 /* -------------------------------- HRPWM0_GLBANA ------------------------------- */
\r
12129 #define HRPWM0_GLBANA_SLDLY_Pos 0 /*!< HRPWM0 GLBANA: SLDLY Position */
\r
12130 #define HRPWM0_GLBANA_SLDLY_Msk (0x03UL << HRPWM0_GLBANA_SLDLY_Pos) /*!< HRPWM0 GLBANA: SLDLY Mask */
\r
12131 #define HRPWM0_GLBANA_FUP_Pos 2 /*!< HRPWM0 GLBANA: FUP Position */
\r
12132 #define HRPWM0_GLBANA_FUP_Msk (0x01UL << HRPWM0_GLBANA_FUP_Pos) /*!< HRPWM0 GLBANA: FUP Mask */
\r
12133 #define HRPWM0_GLBANA_FDN_Pos 3 /*!< HRPWM0 GLBANA: FDN Position */
\r
12134 #define HRPWM0_GLBANA_FDN_Msk (0x01UL << HRPWM0_GLBANA_FDN_Pos) /*!< HRPWM0 GLBANA: FDN Mask */
\r
12135 #define HRPWM0_GLBANA_SLCP_Pos 6 /*!< HRPWM0 GLBANA: SLCP Position */
\r
12136 #define HRPWM0_GLBANA_SLCP_Msk (0x07UL << HRPWM0_GLBANA_SLCP_Pos) /*!< HRPWM0 GLBANA: SLCP Mask */
\r
12137 #define HRPWM0_GLBANA_SLIBLDO_Pos 9 /*!< HRPWM0 GLBANA: SLIBLDO Position */
\r
12138 #define HRPWM0_GLBANA_SLIBLDO_Msk (0x03UL << HRPWM0_GLBANA_SLIBLDO_Pos) /*!< HRPWM0 GLBANA: SLIBLDO Mask */
\r
12139 #define HRPWM0_GLBANA_SLIBLF_Pos 11 /*!< HRPWM0 GLBANA: SLIBLF Position */
\r
12140 #define HRPWM0_GLBANA_SLIBLF_Msk (0x03UL << HRPWM0_GLBANA_SLIBLF_Pos) /*!< HRPWM0 GLBANA: SLIBLF Mask */
\r
12141 #define HRPWM0_GLBANA_SLVREF_Pos 13 /*!< HRPWM0 GLBANA: SLVREF Position */
\r
12142 #define HRPWM0_GLBANA_SLVREF_Msk (0x07UL << HRPWM0_GLBANA_SLVREF_Pos) /*!< HRPWM0 GLBANA: SLVREF Mask */
\r
12143 #define HRPWM0_GLBANA_TRIBIAS_Pos 16 /*!< HRPWM0 GLBANA: TRIBIAS Position */
\r
12144 #define HRPWM0_GLBANA_TRIBIAS_Msk (0x03UL << HRPWM0_GLBANA_TRIBIAS_Pos) /*!< HRPWM0 GLBANA: TRIBIAS Mask */
\r
12145 #define HRPWM0_GLBANA_GHREN_Pos 18 /*!< HRPWM0 GLBANA: GHREN Position */
\r
12146 #define HRPWM0_GLBANA_GHREN_Msk (0x01UL << HRPWM0_GLBANA_GHREN_Pos) /*!< HRPWM0 GLBANA: GHREN Mask */
\r
12148 /* -------------------------------- HRPWM0_CSGCFG ------------------------------- */
\r
12149 #define HRPWM0_CSGCFG_C0PM_Pos 0 /*!< HRPWM0 CSGCFG: C0PM Position */
\r
12150 #define HRPWM0_CSGCFG_C0PM_Msk (0x03UL << HRPWM0_CSGCFG_C0PM_Pos) /*!< HRPWM0 CSGCFG: C0PM Mask */
\r
12151 #define HRPWM0_CSGCFG_C1PM_Pos 2 /*!< HRPWM0 CSGCFG: C1PM Position */
\r
12152 #define HRPWM0_CSGCFG_C1PM_Msk (0x03UL << HRPWM0_CSGCFG_C1PM_Pos) /*!< HRPWM0 CSGCFG: C1PM Mask */
\r
12153 #define HRPWM0_CSGCFG_C2PM_Pos 4 /*!< HRPWM0 CSGCFG: C2PM Position */
\r
12154 #define HRPWM0_CSGCFG_C2PM_Msk (0x03UL << HRPWM0_CSGCFG_C2PM_Pos) /*!< HRPWM0 CSGCFG: C2PM Mask */
\r
12155 #define HRPWM0_CSGCFG_C0CD_Pos 16 /*!< HRPWM0 CSGCFG: C0CD Position */
\r
12156 #define HRPWM0_CSGCFG_C0CD_Msk (0x01UL << HRPWM0_CSGCFG_C0CD_Pos) /*!< HRPWM0 CSGCFG: C0CD Mask */
\r
12157 #define HRPWM0_CSGCFG_C1CD_Pos 17 /*!< HRPWM0 CSGCFG: C1CD Position */
\r
12158 #define HRPWM0_CSGCFG_C1CD_Msk (0x01UL << HRPWM0_CSGCFG_C1CD_Pos) /*!< HRPWM0 CSGCFG: C1CD Mask */
\r
12159 #define HRPWM0_CSGCFG_C2CD_Pos 18 /*!< HRPWM0 CSGCFG: C2CD Position */
\r
12160 #define HRPWM0_CSGCFG_C2CD_Msk (0x01UL << HRPWM0_CSGCFG_C2CD_Pos) /*!< HRPWM0 CSGCFG: C2CD Mask */
\r
12162 /* ------------------------------- HRPWM0_CSGSETG ------------------------------- */
\r
12163 #define HRPWM0_CSGSETG_SD0R_Pos 0 /*!< HRPWM0 CSGSETG: SD0R Position */
\r
12164 #define HRPWM0_CSGSETG_SD0R_Msk (0x01UL << HRPWM0_CSGSETG_SD0R_Pos) /*!< HRPWM0 CSGSETG: SD0R Mask */
\r
12165 #define HRPWM0_CSGSETG_SC0R_Pos 1 /*!< HRPWM0 CSGSETG: SC0R Position */
\r
12166 #define HRPWM0_CSGSETG_SC0R_Msk (0x01UL << HRPWM0_CSGSETG_SC0R_Pos) /*!< HRPWM0 CSGSETG: SC0R Mask */
\r
12167 #define HRPWM0_CSGSETG_SC0P_Pos 2 /*!< HRPWM0 CSGSETG: SC0P Position */
\r
12168 #define HRPWM0_CSGSETG_SC0P_Msk (0x01UL << HRPWM0_CSGSETG_SC0P_Pos) /*!< HRPWM0 CSGSETG: SC0P Mask */
\r
12169 #define HRPWM0_CSGSETG_SD1R_Pos 4 /*!< HRPWM0 CSGSETG: SD1R Position */
\r
12170 #define HRPWM0_CSGSETG_SD1R_Msk (0x01UL << HRPWM0_CSGSETG_SD1R_Pos) /*!< HRPWM0 CSGSETG: SD1R Mask */
\r
12171 #define HRPWM0_CSGSETG_SC1R_Pos 5 /*!< HRPWM0 CSGSETG: SC1R Position */
\r
12172 #define HRPWM0_CSGSETG_SC1R_Msk (0x01UL << HRPWM0_CSGSETG_SC1R_Pos) /*!< HRPWM0 CSGSETG: SC1R Mask */
\r
12173 #define HRPWM0_CSGSETG_SC1P_Pos 6 /*!< HRPWM0 CSGSETG: SC1P Position */
\r
12174 #define HRPWM0_CSGSETG_SC1P_Msk (0x01UL << HRPWM0_CSGSETG_SC1P_Pos) /*!< HRPWM0 CSGSETG: SC1P Mask */
\r
12175 #define HRPWM0_CSGSETG_SD2R_Pos 8 /*!< HRPWM0 CSGSETG: SD2R Position */
\r
12176 #define HRPWM0_CSGSETG_SD2R_Msk (0x01UL << HRPWM0_CSGSETG_SD2R_Pos) /*!< HRPWM0 CSGSETG: SD2R Mask */
\r
12177 #define HRPWM0_CSGSETG_SC2R_Pos 9 /*!< HRPWM0 CSGSETG: SC2R Position */
\r
12178 #define HRPWM0_CSGSETG_SC2R_Msk (0x01UL << HRPWM0_CSGSETG_SC2R_Pos) /*!< HRPWM0 CSGSETG: SC2R Mask */
\r
12179 #define HRPWM0_CSGSETG_SC2P_Pos 10 /*!< HRPWM0 CSGSETG: SC2P Position */
\r
12180 #define HRPWM0_CSGSETG_SC2P_Msk (0x01UL << HRPWM0_CSGSETG_SC2P_Pos) /*!< HRPWM0 CSGSETG: SC2P Mask */
\r
12182 /* ------------------------------- HRPWM0_CSGCLRG ------------------------------- */
\r
12183 #define HRPWM0_CSGCLRG_CD0R_Pos 0 /*!< HRPWM0 CSGCLRG: CD0R Position */
\r
12184 #define HRPWM0_CSGCLRG_CD0R_Msk (0x01UL << HRPWM0_CSGCLRG_CD0R_Pos) /*!< HRPWM0 CSGCLRG: CD0R Mask */
\r
12185 #define HRPWM0_CSGCLRG_CC0R_Pos 1 /*!< HRPWM0 CSGCLRG: CC0R Position */
\r
12186 #define HRPWM0_CSGCLRG_CC0R_Msk (0x01UL << HRPWM0_CSGCLRG_CC0R_Pos) /*!< HRPWM0 CSGCLRG: CC0R Mask */
\r
12187 #define HRPWM0_CSGCLRG_CC0P_Pos 2 /*!< HRPWM0 CSGCLRG: CC0P Position */
\r
12188 #define HRPWM0_CSGCLRG_CC0P_Msk (0x01UL << HRPWM0_CSGCLRG_CC0P_Pos) /*!< HRPWM0 CSGCLRG: CC0P Mask */
\r
12189 #define HRPWM0_CSGCLRG_CD1R_Pos 4 /*!< HRPWM0 CSGCLRG: CD1R Position */
\r
12190 #define HRPWM0_CSGCLRG_CD1R_Msk (0x01UL << HRPWM0_CSGCLRG_CD1R_Pos) /*!< HRPWM0 CSGCLRG: CD1R Mask */
\r
12191 #define HRPWM0_CSGCLRG_CC1R_Pos 5 /*!< HRPWM0 CSGCLRG: CC1R Position */
\r
12192 #define HRPWM0_CSGCLRG_CC1R_Msk (0x01UL << HRPWM0_CSGCLRG_CC1R_Pos) /*!< HRPWM0 CSGCLRG: CC1R Mask */
\r
12193 #define HRPWM0_CSGCLRG_CC1P_Pos 6 /*!< HRPWM0 CSGCLRG: CC1P Position */
\r
12194 #define HRPWM0_CSGCLRG_CC1P_Msk (0x01UL << HRPWM0_CSGCLRG_CC1P_Pos) /*!< HRPWM0 CSGCLRG: CC1P Mask */
\r
12195 #define HRPWM0_CSGCLRG_CD2R_Pos 8 /*!< HRPWM0 CSGCLRG: CD2R Position */
\r
12196 #define HRPWM0_CSGCLRG_CD2R_Msk (0x01UL << HRPWM0_CSGCLRG_CD2R_Pos) /*!< HRPWM0 CSGCLRG: CD2R Mask */
\r
12197 #define HRPWM0_CSGCLRG_CC2R_Pos 9 /*!< HRPWM0 CSGCLRG: CC2R Position */
\r
12198 #define HRPWM0_CSGCLRG_CC2R_Msk (0x01UL << HRPWM0_CSGCLRG_CC2R_Pos) /*!< HRPWM0 CSGCLRG: CC2R Mask */
\r
12199 #define HRPWM0_CSGCLRG_CC2P_Pos 10 /*!< HRPWM0 CSGCLRG: CC2P Position */
\r
12200 #define HRPWM0_CSGCLRG_CC2P_Msk (0x01UL << HRPWM0_CSGCLRG_CC2P_Pos) /*!< HRPWM0 CSGCLRG: CC2P Mask */
\r
12202 /* ------------------------------- HRPWM0_CSGSTATG ------------------------------ */
\r
12203 #define HRPWM0_CSGSTATG_D0RB_Pos 0 /*!< HRPWM0 CSGSTATG: D0RB Position */
\r
12204 #define HRPWM0_CSGSTATG_D0RB_Msk (0x01UL << HRPWM0_CSGSTATG_D0RB_Pos) /*!< HRPWM0 CSGSTATG: D0RB Mask */
\r
12205 #define HRPWM0_CSGSTATG_C0RB_Pos 1 /*!< HRPWM0 CSGSTATG: C0RB Position */
\r
12206 #define HRPWM0_CSGSTATG_C0RB_Msk (0x01UL << HRPWM0_CSGSTATG_C0RB_Pos) /*!< HRPWM0 CSGSTATG: C0RB Mask */
\r
12207 #define HRPWM0_CSGSTATG_PSLS0_Pos 2 /*!< HRPWM0 CSGSTATG: PSLS0 Position */
\r
12208 #define HRPWM0_CSGSTATG_PSLS0_Msk (0x01UL << HRPWM0_CSGSTATG_PSLS0_Pos) /*!< HRPWM0 CSGSTATG: PSLS0 Mask */
\r
12209 #define HRPWM0_CSGSTATG_D1RB_Pos 4 /*!< HRPWM0 CSGSTATG: D1RB Position */
\r
12210 #define HRPWM0_CSGSTATG_D1RB_Msk (0x01UL << HRPWM0_CSGSTATG_D1RB_Pos) /*!< HRPWM0 CSGSTATG: D1RB Mask */
\r
12211 #define HRPWM0_CSGSTATG_C1RB_Pos 5 /*!< HRPWM0 CSGSTATG: C1RB Position */
\r
12212 #define HRPWM0_CSGSTATG_C1RB_Msk (0x01UL << HRPWM0_CSGSTATG_C1RB_Pos) /*!< HRPWM0 CSGSTATG: C1RB Mask */
\r
12213 #define HRPWM0_CSGSTATG_PSLS1_Pos 6 /*!< HRPWM0 CSGSTATG: PSLS1 Position */
\r
12214 #define HRPWM0_CSGSTATG_PSLS1_Msk (0x01UL << HRPWM0_CSGSTATG_PSLS1_Pos) /*!< HRPWM0 CSGSTATG: PSLS1 Mask */
\r
12215 #define HRPWM0_CSGSTATG_D2RB_Pos 8 /*!< HRPWM0 CSGSTATG: D2RB Position */
\r
12216 #define HRPWM0_CSGSTATG_D2RB_Msk (0x01UL << HRPWM0_CSGSTATG_D2RB_Pos) /*!< HRPWM0 CSGSTATG: D2RB Mask */
\r
12217 #define HRPWM0_CSGSTATG_C2RB_Pos 9 /*!< HRPWM0 CSGSTATG: C2RB Position */
\r
12218 #define HRPWM0_CSGSTATG_C2RB_Msk (0x01UL << HRPWM0_CSGSTATG_C2RB_Pos) /*!< HRPWM0 CSGSTATG: C2RB Mask */
\r
12219 #define HRPWM0_CSGSTATG_PSLS2_Pos 10 /*!< HRPWM0 CSGSTATG: PSLS2 Position */
\r
12220 #define HRPWM0_CSGSTATG_PSLS2_Msk (0x01UL << HRPWM0_CSGSTATG_PSLS2_Pos) /*!< HRPWM0 CSGSTATG: PSLS2 Mask */
\r
12222 /* -------------------------------- HRPWM0_CSGFCG ------------------------------- */
\r
12223 #define HRPWM0_CSGFCG_S0STR_Pos 0 /*!< HRPWM0 CSGFCG: S0STR Position */
\r
12224 #define HRPWM0_CSGFCG_S0STR_Msk (0x01UL << HRPWM0_CSGFCG_S0STR_Pos) /*!< HRPWM0 CSGFCG: S0STR Mask */
\r
12225 #define HRPWM0_CSGFCG_S0STP_Pos 1 /*!< HRPWM0 CSGFCG: S0STP Position */
\r
12226 #define HRPWM0_CSGFCG_S0STP_Msk (0x01UL << HRPWM0_CSGFCG_S0STP_Pos) /*!< HRPWM0 CSGFCG: S0STP Mask */
\r
12227 #define HRPWM0_CSGFCG_PS0STR_Pos 2 /*!< HRPWM0 CSGFCG: PS0STR Position */
\r
12228 #define HRPWM0_CSGFCG_PS0STR_Msk (0x01UL << HRPWM0_CSGFCG_PS0STR_Pos) /*!< HRPWM0 CSGFCG: PS0STR Mask */
\r
12229 #define HRPWM0_CSGFCG_PS0STP_Pos 3 /*!< HRPWM0 CSGFCG: PS0STP Position */
\r
12230 #define HRPWM0_CSGFCG_PS0STP_Msk (0x01UL << HRPWM0_CSGFCG_PS0STP_Pos) /*!< HRPWM0 CSGFCG: PS0STP Mask */
\r
12231 #define HRPWM0_CSGFCG_PS0CLR_Pos 4 /*!< HRPWM0 CSGFCG: PS0CLR Position */
\r
12232 #define HRPWM0_CSGFCG_PS0CLR_Msk (0x01UL << HRPWM0_CSGFCG_PS0CLR_Pos) /*!< HRPWM0 CSGFCG: PS0CLR Mask */
\r
12233 #define HRPWM0_CSGFCG_S1STR_Pos 8 /*!< HRPWM0 CSGFCG: S1STR Position */
\r
12234 #define HRPWM0_CSGFCG_S1STR_Msk (0x01UL << HRPWM0_CSGFCG_S1STR_Pos) /*!< HRPWM0 CSGFCG: S1STR Mask */
\r
12235 #define HRPWM0_CSGFCG_S1STP_Pos 9 /*!< HRPWM0 CSGFCG: S1STP Position */
\r
12236 #define HRPWM0_CSGFCG_S1STP_Msk (0x01UL << HRPWM0_CSGFCG_S1STP_Pos) /*!< HRPWM0 CSGFCG: S1STP Mask */
\r
12237 #define HRPWM0_CSGFCG_PS1STR_Pos 10 /*!< HRPWM0 CSGFCG: PS1STR Position */
\r
12238 #define HRPWM0_CSGFCG_PS1STR_Msk (0x01UL << HRPWM0_CSGFCG_PS1STR_Pos) /*!< HRPWM0 CSGFCG: PS1STR Mask */
\r
12239 #define HRPWM0_CSGFCG_PS1STP_Pos 11 /*!< HRPWM0 CSGFCG: PS1STP Position */
\r
12240 #define HRPWM0_CSGFCG_PS1STP_Msk (0x01UL << HRPWM0_CSGFCG_PS1STP_Pos) /*!< HRPWM0 CSGFCG: PS1STP Mask */
\r
12241 #define HRPWM0_CSGFCG_PS1CLR_Pos 12 /*!< HRPWM0 CSGFCG: PS1CLR Position */
\r
12242 #define HRPWM0_CSGFCG_PS1CLR_Msk (0x01UL << HRPWM0_CSGFCG_PS1CLR_Pos) /*!< HRPWM0 CSGFCG: PS1CLR Mask */
\r
12243 #define HRPWM0_CSGFCG_S2STR_Pos 16 /*!< HRPWM0 CSGFCG: S2STR Position */
\r
12244 #define HRPWM0_CSGFCG_S2STR_Msk (0x01UL << HRPWM0_CSGFCG_S2STR_Pos) /*!< HRPWM0 CSGFCG: S2STR Mask */
\r
12245 #define HRPWM0_CSGFCG_S2STP_Pos 17 /*!< HRPWM0 CSGFCG: S2STP Position */
\r
12246 #define HRPWM0_CSGFCG_S2STP_Msk (0x01UL << HRPWM0_CSGFCG_S2STP_Pos) /*!< HRPWM0 CSGFCG: S2STP Mask */
\r
12247 #define HRPWM0_CSGFCG_PS2STR_Pos 18 /*!< HRPWM0 CSGFCG: PS2STR Position */
\r
12248 #define HRPWM0_CSGFCG_PS2STR_Msk (0x01UL << HRPWM0_CSGFCG_PS2STR_Pos) /*!< HRPWM0 CSGFCG: PS2STR Mask */
\r
12249 #define HRPWM0_CSGFCG_PS2STP_Pos 19 /*!< HRPWM0 CSGFCG: PS2STP Position */
\r
12250 #define HRPWM0_CSGFCG_PS2STP_Msk (0x01UL << HRPWM0_CSGFCG_PS2STP_Pos) /*!< HRPWM0 CSGFCG: PS2STP Mask */
\r
12251 #define HRPWM0_CSGFCG_PS2CLR_Pos 20 /*!< HRPWM0 CSGFCG: PS2CLR Position */
\r
12252 #define HRPWM0_CSGFCG_PS2CLR_Msk (0x01UL << HRPWM0_CSGFCG_PS2CLR_Pos) /*!< HRPWM0 CSGFCG: PS2CLR Mask */
\r
12254 /* -------------------------------- HRPWM0_CSGFSG ------------------------------- */
\r
12255 #define HRPWM0_CSGFSG_S0RB_Pos 0 /*!< HRPWM0 CSGFSG: S0RB Position */
\r
12256 #define HRPWM0_CSGFSG_S0RB_Msk (0x01UL << HRPWM0_CSGFSG_S0RB_Pos) /*!< HRPWM0 CSGFSG: S0RB Mask */
\r
12257 #define HRPWM0_CSGFSG_P0RB_Pos 1 /*!< HRPWM0 CSGFSG: P0RB Position */
\r
12258 #define HRPWM0_CSGFSG_P0RB_Msk (0x01UL << HRPWM0_CSGFSG_P0RB_Pos) /*!< HRPWM0 CSGFSG: P0RB Mask */
\r
12259 #define HRPWM0_CSGFSG_S1RB_Pos 8 /*!< HRPWM0 CSGFSG: S1RB Position */
\r
12260 #define HRPWM0_CSGFSG_S1RB_Msk (0x01UL << HRPWM0_CSGFSG_S1RB_Pos) /*!< HRPWM0 CSGFSG: S1RB Mask */
\r
12261 #define HRPWM0_CSGFSG_P1RB_Pos 9 /*!< HRPWM0 CSGFSG: P1RB Position */
\r
12262 #define HRPWM0_CSGFSG_P1RB_Msk (0x01UL << HRPWM0_CSGFSG_P1RB_Pos) /*!< HRPWM0 CSGFSG: P1RB Mask */
\r
12263 #define HRPWM0_CSGFSG_S2RB_Pos 16 /*!< HRPWM0 CSGFSG: S2RB Position */
\r
12264 #define HRPWM0_CSGFSG_S2RB_Msk (0x01UL << HRPWM0_CSGFSG_S2RB_Pos) /*!< HRPWM0 CSGFSG: S2RB Mask */
\r
12265 #define HRPWM0_CSGFSG_P2RB_Pos 17 /*!< HRPWM0 CSGFSG: P2RB Position */
\r
12266 #define HRPWM0_CSGFSG_P2RB_Msk (0x01UL << HRPWM0_CSGFSG_P2RB_Pos) /*!< HRPWM0 CSGFSG: P2RB Mask */
\r
12268 /* -------------------------------- HRPWM0_CSGTRG ------------------------------- */
\r
12269 #define HRPWM0_CSGTRG_D0SES_Pos 0 /*!< HRPWM0 CSGTRG: D0SES Position */
\r
12270 #define HRPWM0_CSGTRG_D0SES_Msk (0x01UL << HRPWM0_CSGTRG_D0SES_Pos) /*!< HRPWM0 CSGTRG: D0SES Mask */
\r
12271 #define HRPWM0_CSGTRG_D0SVS_Pos 1 /*!< HRPWM0 CSGTRG: D0SVS Position */
\r
12272 #define HRPWM0_CSGTRG_D0SVS_Msk (0x01UL << HRPWM0_CSGTRG_D0SVS_Pos) /*!< HRPWM0 CSGTRG: D0SVS Mask */
\r
12273 #define HRPWM0_CSGTRG_D1SES_Pos 4 /*!< HRPWM0 CSGTRG: D1SES Position */
\r
12274 #define HRPWM0_CSGTRG_D1SES_Msk (0x01UL << HRPWM0_CSGTRG_D1SES_Pos) /*!< HRPWM0 CSGTRG: D1SES Mask */
\r
12275 #define HRPWM0_CSGTRG_D1SVS_Pos 5 /*!< HRPWM0 CSGTRG: D1SVS Position */
\r
12276 #define HRPWM0_CSGTRG_D1SVS_Msk (0x01UL << HRPWM0_CSGTRG_D1SVS_Pos) /*!< HRPWM0 CSGTRG: D1SVS Mask */
\r
12277 #define HRPWM0_CSGTRG_D2SES_Pos 8 /*!< HRPWM0 CSGTRG: D2SES Position */
\r
12278 #define HRPWM0_CSGTRG_D2SES_Msk (0x01UL << HRPWM0_CSGTRG_D2SES_Pos) /*!< HRPWM0 CSGTRG: D2SES Mask */
\r
12279 #define HRPWM0_CSGTRG_D2SVS_Pos 9 /*!< HRPWM0 CSGTRG: D2SVS Position */
\r
12280 #define HRPWM0_CSGTRG_D2SVS_Msk (0x01UL << HRPWM0_CSGTRG_D2SVS_Pos) /*!< HRPWM0 CSGTRG: D2SVS Mask */
\r
12282 /* -------------------------------- HRPWM0_CSGTRC ------------------------------- */
\r
12283 #define HRPWM0_CSGTRC_D0SEC_Pos 0 /*!< HRPWM0 CSGTRC: D0SEC Position */
\r
12284 #define HRPWM0_CSGTRC_D0SEC_Msk (0x01UL << HRPWM0_CSGTRC_D0SEC_Pos) /*!< HRPWM0 CSGTRC: D0SEC Mask */
\r
12285 #define HRPWM0_CSGTRC_D1SEC_Pos 4 /*!< HRPWM0 CSGTRC: D1SEC Position */
\r
12286 #define HRPWM0_CSGTRC_D1SEC_Msk (0x01UL << HRPWM0_CSGTRC_D1SEC_Pos) /*!< HRPWM0 CSGTRC: D1SEC Mask */
\r
12287 #define HRPWM0_CSGTRC_D2SEC_Pos 8 /*!< HRPWM0 CSGTRC: D2SEC Position */
\r
12288 #define HRPWM0_CSGTRC_D2SEC_Msk (0x01UL << HRPWM0_CSGTRC_D2SEC_Pos) /*!< HRPWM0 CSGTRC: D2SEC Mask */
\r
12290 /* ------------------------------- HRPWM0_CSGTRSG ------------------------------- */
\r
12291 #define HRPWM0_CSGTRSG_D0STE_Pos 0 /*!< HRPWM0 CSGTRSG: D0STE Position */
\r
12292 #define HRPWM0_CSGTRSG_D0STE_Msk (0x01UL << HRPWM0_CSGTRSG_D0STE_Pos) /*!< HRPWM0 CSGTRSG: D0STE Mask */
\r
12293 #define HRPWM0_CSGTRSG_SW0ST_Pos 1 /*!< HRPWM0 CSGTRSG: SW0ST Position */
\r
12294 #define HRPWM0_CSGTRSG_SW0ST_Msk (0x01UL << HRPWM0_CSGTRSG_SW0ST_Pos) /*!< HRPWM0 CSGTRSG: SW0ST Mask */
\r
12295 #define HRPWM0_CSGTRSG_D1STE_Pos 4 /*!< HRPWM0 CSGTRSG: D1STE Position */
\r
12296 #define HRPWM0_CSGTRSG_D1STE_Msk (0x01UL << HRPWM0_CSGTRSG_D1STE_Pos) /*!< HRPWM0 CSGTRSG: D1STE Mask */
\r
12297 #define HRPWM0_CSGTRSG_SW1ST_Pos 5 /*!< HRPWM0 CSGTRSG: SW1ST Position */
\r
12298 #define HRPWM0_CSGTRSG_SW1ST_Msk (0x01UL << HRPWM0_CSGTRSG_SW1ST_Pos) /*!< HRPWM0 CSGTRSG: SW1ST Mask */
\r
12299 #define HRPWM0_CSGTRSG_D2STE_Pos 8 /*!< HRPWM0 CSGTRSG: D2STE Position */
\r
12300 #define HRPWM0_CSGTRSG_D2STE_Msk (0x01UL << HRPWM0_CSGTRSG_D2STE_Pos) /*!< HRPWM0 CSGTRSG: D2STE Mask */
\r
12301 #define HRPWM0_CSGTRSG_SW2ST_Pos 9 /*!< HRPWM0 CSGTRSG: SW2ST Position */
\r
12302 #define HRPWM0_CSGTRSG_SW2ST_Msk (0x01UL << HRPWM0_CSGTRSG_SW2ST_Pos) /*!< HRPWM0 CSGTRSG: SW2ST Mask */
\r
12304 /* -------------------------------- HRPWM0_HRCCFG ------------------------------- */
\r
12305 #define HRPWM0_HRCCFG_HRCPM_Pos 0 /*!< HRPWM0 HRCCFG: HRCPM Position */
\r
12306 #define HRPWM0_HRCCFG_HRCPM_Msk (0x01UL << HRPWM0_HRCCFG_HRCPM_Pos) /*!< HRPWM0 HRCCFG: HRCPM Mask */
\r
12307 #define HRPWM0_HRCCFG_HRC0E_Pos 4 /*!< HRPWM0 HRCCFG: HRC0E Position */
\r
12308 #define HRPWM0_HRCCFG_HRC0E_Msk (0x01UL << HRPWM0_HRCCFG_HRC0E_Pos) /*!< HRPWM0 HRCCFG: HRC0E Mask */
\r
12309 #define HRPWM0_HRCCFG_HRC1E_Pos 5 /*!< HRPWM0 HRCCFG: HRC1E Position */
\r
12310 #define HRPWM0_HRCCFG_HRC1E_Msk (0x01UL << HRPWM0_HRCCFG_HRC1E_Pos) /*!< HRPWM0 HRCCFG: HRC1E Mask */
\r
12311 #define HRPWM0_HRCCFG_HRC2E_Pos 6 /*!< HRPWM0 HRCCFG: HRC2E Position */
\r
12312 #define HRPWM0_HRCCFG_HRC2E_Msk (0x01UL << HRPWM0_HRCCFG_HRC2E_Pos) /*!< HRPWM0 HRCCFG: HRC2E Mask */
\r
12313 #define HRPWM0_HRCCFG_HRC3E_Pos 7 /*!< HRPWM0 HRCCFG: HRC3E Position */
\r
12314 #define HRPWM0_HRCCFG_HRC3E_Msk (0x01UL << HRPWM0_HRCCFG_HRC3E_Pos) /*!< HRPWM0 HRCCFG: HRC3E Mask */
\r
12315 #define HRPWM0_HRCCFG_CLKC_Pos 16 /*!< HRPWM0 HRCCFG: CLKC Position */
\r
12316 #define HRPWM0_HRCCFG_CLKC_Msk (0x07UL << HRPWM0_HRCCFG_CLKC_Pos) /*!< HRPWM0 HRCCFG: CLKC Mask */
\r
12317 #define HRPWM0_HRCCFG_LRC0E_Pos 20 /*!< HRPWM0 HRCCFG: LRC0E Position */
\r
12318 #define HRPWM0_HRCCFG_LRC0E_Msk (0x01UL << HRPWM0_HRCCFG_LRC0E_Pos) /*!< HRPWM0 HRCCFG: LRC0E Mask */
\r
12319 #define HRPWM0_HRCCFG_LRC1E_Pos 21 /*!< HRPWM0 HRCCFG: LRC1E Position */
\r
12320 #define HRPWM0_HRCCFG_LRC1E_Msk (0x01UL << HRPWM0_HRCCFG_LRC1E_Pos) /*!< HRPWM0 HRCCFG: LRC1E Mask */
\r
12321 #define HRPWM0_HRCCFG_LRC2E_Pos 22 /*!< HRPWM0 HRCCFG: LRC2E Position */
\r
12322 #define HRPWM0_HRCCFG_LRC2E_Msk (0x01UL << HRPWM0_HRCCFG_LRC2E_Pos) /*!< HRPWM0 HRCCFG: LRC2E Mask */
\r
12323 #define HRPWM0_HRCCFG_LRC3E_Pos 23 /*!< HRPWM0 HRCCFG: LRC3E Position */
\r
12324 #define HRPWM0_HRCCFG_LRC3E_Msk (0x01UL << HRPWM0_HRCCFG_LRC3E_Pos) /*!< HRPWM0 HRCCFG: LRC3E Mask */
\r
12326 /* ------------------------------- HRPWM0_HRCSTRG ------------------------------- */
\r
12327 #define HRPWM0_HRCSTRG_H0ES_Pos 0 /*!< HRPWM0 HRCSTRG: H0ES Position */
\r
12328 #define HRPWM0_HRCSTRG_H0ES_Msk (0x01UL << HRPWM0_HRCSTRG_H0ES_Pos) /*!< HRPWM0 HRCSTRG: H0ES Mask */
\r
12329 #define HRPWM0_HRCSTRG_H0DES_Pos 1 /*!< HRPWM0 HRCSTRG: H0DES Position */
\r
12330 #define HRPWM0_HRCSTRG_H0DES_Msk (0x01UL << HRPWM0_HRCSTRG_H0DES_Pos) /*!< HRPWM0 HRCSTRG: H0DES Mask */
\r
12331 #define HRPWM0_HRCSTRG_H1ES_Pos 4 /*!< HRPWM0 HRCSTRG: H1ES Position */
\r
12332 #define HRPWM0_HRCSTRG_H1ES_Msk (0x01UL << HRPWM0_HRCSTRG_H1ES_Pos) /*!< HRPWM0 HRCSTRG: H1ES Mask */
\r
12333 #define HRPWM0_HRCSTRG_H1DES_Pos 5 /*!< HRPWM0 HRCSTRG: H1DES Position */
\r
12334 #define HRPWM0_HRCSTRG_H1DES_Msk (0x01UL << HRPWM0_HRCSTRG_H1DES_Pos) /*!< HRPWM0 HRCSTRG: H1DES Mask */
\r
12335 #define HRPWM0_HRCSTRG_H2ES_Pos 8 /*!< HRPWM0 HRCSTRG: H2ES Position */
\r
12336 #define HRPWM0_HRCSTRG_H2ES_Msk (0x01UL << HRPWM0_HRCSTRG_H2ES_Pos) /*!< HRPWM0 HRCSTRG: H2ES Mask */
\r
12337 #define HRPWM0_HRCSTRG_H2DES_Pos 9 /*!< HRPWM0 HRCSTRG: H2DES Position */
\r
12338 #define HRPWM0_HRCSTRG_H2DES_Msk (0x01UL << HRPWM0_HRCSTRG_H2DES_Pos) /*!< HRPWM0 HRCSTRG: H2DES Mask */
\r
12339 #define HRPWM0_HRCSTRG_H3ES_Pos 12 /*!< HRPWM0 HRCSTRG: H3ES Position */
\r
12340 #define HRPWM0_HRCSTRG_H3ES_Msk (0x01UL << HRPWM0_HRCSTRG_H3ES_Pos) /*!< HRPWM0 HRCSTRG: H3ES Mask */
\r
12341 #define HRPWM0_HRCSTRG_H3DES_Pos 13 /*!< HRPWM0 HRCSTRG: H3DES Position */
\r
12342 #define HRPWM0_HRCSTRG_H3DES_Msk (0x01UL << HRPWM0_HRCSTRG_H3DES_Pos) /*!< HRPWM0 HRCSTRG: H3DES Mask */
\r
12344 /* ------------------------------- HRPWM0_HRCCTRG ------------------------------- */
\r
12345 #define HRPWM0_HRCCTRG_H0EC_Pos 0 /*!< HRPWM0 HRCCTRG: H0EC Position */
\r
12346 #define HRPWM0_HRCCTRG_H0EC_Msk (0x01UL << HRPWM0_HRCCTRG_H0EC_Pos) /*!< HRPWM0 HRCCTRG: H0EC Mask */
\r
12347 #define HRPWM0_HRCCTRG_H0DEC_Pos 1 /*!< HRPWM0 HRCCTRG: H0DEC Position */
\r
12348 #define HRPWM0_HRCCTRG_H0DEC_Msk (0x01UL << HRPWM0_HRCCTRG_H0DEC_Pos) /*!< HRPWM0 HRCCTRG: H0DEC Mask */
\r
12349 #define HRPWM0_HRCCTRG_H1EC_Pos 4 /*!< HRPWM0 HRCCTRG: H1EC Position */
\r
12350 #define HRPWM0_HRCCTRG_H1EC_Msk (0x01UL << HRPWM0_HRCCTRG_H1EC_Pos) /*!< HRPWM0 HRCCTRG: H1EC Mask */
\r
12351 #define HRPWM0_HRCCTRG_H1DEC_Pos 5 /*!< HRPWM0 HRCCTRG: H1DEC Position */
\r
12352 #define HRPWM0_HRCCTRG_H1DEC_Msk (0x01UL << HRPWM0_HRCCTRG_H1DEC_Pos) /*!< HRPWM0 HRCCTRG: H1DEC Mask */
\r
12353 #define HRPWM0_HRCCTRG_H2CEC_Pos 8 /*!< HRPWM0 HRCCTRG: H2CEC Position */
\r
12354 #define HRPWM0_HRCCTRG_H2CEC_Msk (0x01UL << HRPWM0_HRCCTRG_H2CEC_Pos) /*!< HRPWM0 HRCCTRG: H2CEC Mask */
\r
12355 #define HRPWM0_HRCCTRG_H2DEC_Pos 9 /*!< HRPWM0 HRCCTRG: H2DEC Position */
\r
12356 #define HRPWM0_HRCCTRG_H2DEC_Msk (0x01UL << HRPWM0_HRCCTRG_H2DEC_Pos) /*!< HRPWM0 HRCCTRG: H2DEC Mask */
\r
12357 #define HRPWM0_HRCCTRG_H3EC_Pos 12 /*!< HRPWM0 HRCCTRG: H3EC Position */
\r
12358 #define HRPWM0_HRCCTRG_H3EC_Msk (0x01UL << HRPWM0_HRCCTRG_H3EC_Pos) /*!< HRPWM0 HRCCTRG: H3EC Mask */
\r
12359 #define HRPWM0_HRCCTRG_H3DEC_Pos 13 /*!< HRPWM0 HRCCTRG: H3DEC Position */
\r
12360 #define HRPWM0_HRCCTRG_H3DEC_Msk (0x01UL << HRPWM0_HRCCTRG_H3DEC_Pos) /*!< HRPWM0 HRCCTRG: H3DEC Mask */
\r
12362 /* ------------------------------- HRPWM0_HRCSTSG ------------------------------- */
\r
12363 #define HRPWM0_HRCSTSG_H0STE_Pos 0 /*!< HRPWM0 HRCSTSG: H0STE Position */
\r
12364 #define HRPWM0_HRCSTSG_H0STE_Msk (0x01UL << HRPWM0_HRCSTSG_H0STE_Pos) /*!< HRPWM0 HRCSTSG: H0STE Mask */
\r
12365 #define HRPWM0_HRCSTSG_H0DSTE_Pos 1 /*!< HRPWM0 HRCSTSG: H0DSTE Position */
\r
12366 #define HRPWM0_HRCSTSG_H0DSTE_Msk (0x01UL << HRPWM0_HRCSTSG_H0DSTE_Pos) /*!< HRPWM0 HRCSTSG: H0DSTE Mask */
\r
12367 #define HRPWM0_HRCSTSG_H1STE_Pos 4 /*!< HRPWM0 HRCSTSG: H1STE Position */
\r
12368 #define HRPWM0_HRCSTSG_H1STE_Msk (0x01UL << HRPWM0_HRCSTSG_H1STE_Pos) /*!< HRPWM0 HRCSTSG: H1STE Mask */
\r
12369 #define HRPWM0_HRCSTSG_H1DSTE_Pos 5 /*!< HRPWM0 HRCSTSG: H1DSTE Position */
\r
12370 #define HRPWM0_HRCSTSG_H1DSTE_Msk (0x01UL << HRPWM0_HRCSTSG_H1DSTE_Pos) /*!< HRPWM0 HRCSTSG: H1DSTE Mask */
\r
12371 #define HRPWM0_HRCSTSG_H2STE_Pos 8 /*!< HRPWM0 HRCSTSG: H2STE Position */
\r
12372 #define HRPWM0_HRCSTSG_H2STE_Msk (0x01UL << HRPWM0_HRCSTSG_H2STE_Pos) /*!< HRPWM0 HRCSTSG: H2STE Mask */
\r
12373 #define HRPWM0_HRCSTSG_H2DSTE_Pos 9 /*!< HRPWM0 HRCSTSG: H2DSTE Position */
\r
12374 #define HRPWM0_HRCSTSG_H2DSTE_Msk (0x01UL << HRPWM0_HRCSTSG_H2DSTE_Pos) /*!< HRPWM0 HRCSTSG: H2DSTE Mask */
\r
12375 #define HRPWM0_HRCSTSG_H3STE_Pos 12 /*!< HRPWM0 HRCSTSG: H3STE Position */
\r
12376 #define HRPWM0_HRCSTSG_H3STE_Msk (0x01UL << HRPWM0_HRCSTSG_H3STE_Pos) /*!< HRPWM0 HRCSTSG: H3STE Mask */
\r
12377 #define HRPWM0_HRCSTSG_H3DSTE_Pos 13 /*!< HRPWM0 HRCSTSG: H3DSTE Position */
\r
12378 #define HRPWM0_HRCSTSG_H3DSTE_Msk (0x01UL << HRPWM0_HRCSTSG_H3DSTE_Pos) /*!< HRPWM0 HRCSTSG: H3DSTE Mask */
\r
12380 /* -------------------------------- HRPWM0_HRGHRS ------------------------------- */
\r
12381 #define HRPWM0_HRGHRS_HRGR_Pos 0 /*!< HRPWM0 HRGHRS: HRGR Position */
\r
12382 #define HRPWM0_HRGHRS_HRGR_Msk (0x01UL << HRPWM0_HRGHRS_HRGR_Pos) /*!< HRPWM0 HRGHRS: HRGR Mask */
\r
12385 /* ================================================================================ */
\r
12386 /* ================ Group 'HRPWM0_CSG' Position & Mask ================ */
\r
12387 /* ================================================================================ */
\r
12390 /* ------------------------------- HRPWM0_CSG_DCI ------------------------------- */
\r
12391 #define HRPWM0_CSG_DCI_SVIS_Pos 0 /*!< HRPWM0_CSG DCI: SVIS Position */
\r
12392 #define HRPWM0_CSG_DCI_SVIS_Msk (0x0fUL << HRPWM0_CSG_DCI_SVIS_Pos) /*!< HRPWM0_CSG DCI: SVIS Mask */
\r
12393 #define HRPWM0_CSG_DCI_STRIS_Pos 4 /*!< HRPWM0_CSG DCI: STRIS Position */
\r
12394 #define HRPWM0_CSG_DCI_STRIS_Msk (0x0fUL << HRPWM0_CSG_DCI_STRIS_Pos) /*!< HRPWM0_CSG DCI: STRIS Mask */
\r
12395 #define HRPWM0_CSG_DCI_STPIS_Pos 8 /*!< HRPWM0_CSG DCI: STPIS Position */
\r
12396 #define HRPWM0_CSG_DCI_STPIS_Msk (0x0fUL << HRPWM0_CSG_DCI_STPIS_Pos) /*!< HRPWM0_CSG DCI: STPIS Mask */
\r
12397 #define HRPWM0_CSG_DCI_TRGIS_Pos 12 /*!< HRPWM0_CSG DCI: TRGIS Position */
\r
12398 #define HRPWM0_CSG_DCI_TRGIS_Msk (0x0fUL << HRPWM0_CSG_DCI_TRGIS_Pos) /*!< HRPWM0_CSG DCI: TRGIS Mask */
\r
12399 #define HRPWM0_CSG_DCI_STIS_Pos 16 /*!< HRPWM0_CSG DCI: STIS Position */
\r
12400 #define HRPWM0_CSG_DCI_STIS_Msk (0x0fUL << HRPWM0_CSG_DCI_STIS_Pos) /*!< HRPWM0_CSG DCI: STIS Mask */
\r
12401 #define HRPWM0_CSG_DCI_SCS_Pos 20 /*!< HRPWM0_CSG DCI: SCS Position */
\r
12402 #define HRPWM0_CSG_DCI_SCS_Msk (0x03UL << HRPWM0_CSG_DCI_SCS_Pos) /*!< HRPWM0_CSG DCI: SCS Mask */
\r
12404 /* ------------------------------- HRPWM0_CSG_IES ------------------------------- */
\r
12405 #define HRPWM0_CSG_IES_SVLS_Pos 0 /*!< HRPWM0_CSG IES: SVLS Position */
\r
12406 #define HRPWM0_CSG_IES_SVLS_Msk (0x03UL << HRPWM0_CSG_IES_SVLS_Pos) /*!< HRPWM0_CSG IES: SVLS Mask */
\r
12407 #define HRPWM0_CSG_IES_STRES_Pos 2 /*!< HRPWM0_CSG IES: STRES Position */
\r
12408 #define HRPWM0_CSG_IES_STRES_Msk (0x03UL << HRPWM0_CSG_IES_STRES_Pos) /*!< HRPWM0_CSG IES: STRES Mask */
\r
12409 #define HRPWM0_CSG_IES_STPES_Pos 4 /*!< HRPWM0_CSG IES: STPES Position */
\r
12410 #define HRPWM0_CSG_IES_STPES_Msk (0x03UL << HRPWM0_CSG_IES_STPES_Pos) /*!< HRPWM0_CSG IES: STPES Mask */
\r
12411 #define HRPWM0_CSG_IES_TRGES_Pos 6 /*!< HRPWM0_CSG IES: TRGES Position */
\r
12412 #define HRPWM0_CSG_IES_TRGES_Msk (0x03UL << HRPWM0_CSG_IES_TRGES_Pos) /*!< HRPWM0_CSG IES: TRGES Mask */
\r
12413 #define HRPWM0_CSG_IES_STES_Pos 8 /*!< HRPWM0_CSG IES: STES Position */
\r
12414 #define HRPWM0_CSG_IES_STES_Msk (0x03UL << HRPWM0_CSG_IES_STES_Pos) /*!< HRPWM0_CSG IES: STES Mask */
\r
12416 /* -------------------------------- HRPWM0_CSG_SC ------------------------------- */
\r
12417 #define HRPWM0_CSG_SC_PSRM_Pos 0 /*!< HRPWM0_CSG SC: PSRM Position */
\r
12418 #define HRPWM0_CSG_SC_PSRM_Msk (0x03UL << HRPWM0_CSG_SC_PSRM_Pos) /*!< HRPWM0_CSG SC: PSRM Mask */
\r
12419 #define HRPWM0_CSG_SC_PSTM_Pos 2 /*!< HRPWM0_CSG SC: PSTM Position */
\r
12420 #define HRPWM0_CSG_SC_PSTM_Msk (0x03UL << HRPWM0_CSG_SC_PSTM_Pos) /*!< HRPWM0_CSG SC: PSTM Mask */
\r
12421 #define HRPWM0_CSG_SC_FPD_Pos 4 /*!< HRPWM0_CSG SC: FPD Position */
\r
12422 #define HRPWM0_CSG_SC_FPD_Msk (0x01UL << HRPWM0_CSG_SC_FPD_Pos) /*!< HRPWM0_CSG SC: FPD Mask */
\r
12423 #define HRPWM0_CSG_SC_PSV_Pos 5 /*!< HRPWM0_CSG SC: PSV Position */
\r
12424 #define HRPWM0_CSG_SC_PSV_Msk (0x03UL << HRPWM0_CSG_SC_PSV_Pos) /*!< HRPWM0_CSG SC: PSV Mask */
\r
12425 #define HRPWM0_CSG_SC_SCM_Pos 8 /*!< HRPWM0_CSG SC: SCM Position */
\r
12426 #define HRPWM0_CSG_SC_SCM_Msk (0x03UL << HRPWM0_CSG_SC_SCM_Pos) /*!< HRPWM0_CSG SC: SCM Mask */
\r
12427 #define HRPWM0_CSG_SC_SSRM_Pos 10 /*!< HRPWM0_CSG SC: SSRM Position */
\r
12428 #define HRPWM0_CSG_SC_SSRM_Msk (0x03UL << HRPWM0_CSG_SC_SSRM_Pos) /*!< HRPWM0_CSG SC: SSRM Mask */
\r
12429 #define HRPWM0_CSG_SC_SSTM_Pos 12 /*!< HRPWM0_CSG SC: SSTM Position */
\r
12430 #define HRPWM0_CSG_SC_SSTM_Msk (0x03UL << HRPWM0_CSG_SC_SSTM_Pos) /*!< HRPWM0_CSG SC: SSTM Mask */
\r
12431 #define HRPWM0_CSG_SC_SVSC_Pos 14 /*!< HRPWM0_CSG SC: SVSC Position */
\r
12432 #define HRPWM0_CSG_SC_SVSC_Msk (0x03UL << HRPWM0_CSG_SC_SVSC_Pos) /*!< HRPWM0_CSG SC: SVSC Mask */
\r
12433 #define HRPWM0_CSG_SC_SWSM_Pos 16 /*!< HRPWM0_CSG SC: SWSM Position */
\r
12434 #define HRPWM0_CSG_SC_SWSM_Msk (0x03UL << HRPWM0_CSG_SC_SWSM_Pos) /*!< HRPWM0_CSG SC: SWSM Mask */
\r
12435 #define HRPWM0_CSG_SC_GCFG_Pos 18 /*!< HRPWM0_CSG SC: GCFG Position */
\r
12436 #define HRPWM0_CSG_SC_GCFG_Msk (0x03UL << HRPWM0_CSG_SC_GCFG_Pos) /*!< HRPWM0_CSG SC: GCFG Mask */
\r
12437 #define HRPWM0_CSG_SC_IST_Pos 20 /*!< HRPWM0_CSG SC: IST Position */
\r
12438 #define HRPWM0_CSG_SC_IST_Msk (0x01UL << HRPWM0_CSG_SC_IST_Pos) /*!< HRPWM0_CSG SC: IST Mask */
\r
12439 #define HRPWM0_CSG_SC_PSE_Pos 21 /*!< HRPWM0_CSG SC: PSE Position */
\r
12440 #define HRPWM0_CSG_SC_PSE_Msk (0x01UL << HRPWM0_CSG_SC_PSE_Pos) /*!< HRPWM0_CSG SC: PSE Mask */
\r
12441 #define HRPWM0_CSG_SC_PSWM_Pos 24 /*!< HRPWM0_CSG SC: PSWM Position */
\r
12442 #define HRPWM0_CSG_SC_PSWM_Msk (0x03UL << HRPWM0_CSG_SC_PSWM_Pos) /*!< HRPWM0_CSG SC: PSWM Mask */
\r
12444 /* -------------------------------- HRPWM0_CSG_PC ------------------------------- */
\r
12445 #define HRPWM0_CSG_PC_PSWV_Pos 0 /*!< HRPWM0_CSG PC: PSWV Position */
\r
12446 #define HRPWM0_CSG_PC_PSWV_Msk (0x3fUL << HRPWM0_CSG_PC_PSWV_Pos) /*!< HRPWM0_CSG PC: PSWV Mask */
\r
12448 /* ------------------------------- HRPWM0_CSG_DSV1 ------------------------------ */
\r
12449 #define HRPWM0_CSG_DSV1_DSV1_Pos 0 /*!< HRPWM0_CSG DSV1: DSV1 Position */
\r
12450 #define HRPWM0_CSG_DSV1_DSV1_Msk (0x000003ffUL << HRPWM0_CSG_DSV1_DSV1_Pos) /*!< HRPWM0_CSG DSV1: DSV1 Mask */
\r
12452 /* ------------------------------- HRPWM0_CSG_DSV2 ------------------------------ */
\r
12453 #define HRPWM0_CSG_DSV2_DSV2_Pos 0 /*!< HRPWM0_CSG DSV2: DSV2 Position */
\r
12454 #define HRPWM0_CSG_DSV2_DSV2_Msk (0x000003ffUL << HRPWM0_CSG_DSV2_DSV2_Pos) /*!< HRPWM0_CSG DSV2: DSV2 Mask */
\r
12456 /* ------------------------------ HRPWM0_CSG_SDSV1 ------------------------------ */
\r
12457 #define HRPWM0_CSG_SDSV1_SDSV1_Pos 0 /*!< HRPWM0_CSG SDSV1: SDSV1 Position */
\r
12458 #define HRPWM0_CSG_SDSV1_SDSV1_Msk (0x000003ffUL << HRPWM0_CSG_SDSV1_SDSV1_Pos) /*!< HRPWM0_CSG SDSV1: SDSV1 Mask */
\r
12460 /* ------------------------------- HRPWM0_CSG_SPC ------------------------------- */
\r
12461 #define HRPWM0_CSG_SPC_SPSWV_Pos 0 /*!< HRPWM0_CSG SPC: SPSWV Position */
\r
12462 #define HRPWM0_CSG_SPC_SPSWV_Msk (0x3fUL << HRPWM0_CSG_SPC_SPSWV_Pos) /*!< HRPWM0_CSG SPC: SPSWV Mask */
\r
12464 /* -------------------------------- HRPWM0_CSG_CC ------------------------------- */
\r
12465 #define HRPWM0_CSG_CC_IBS_Pos 0 /*!< HRPWM0_CSG CC: IBS Position */
\r
12466 #define HRPWM0_CSG_CC_IBS_Msk (0x0fUL << HRPWM0_CSG_CC_IBS_Pos) /*!< HRPWM0_CSG CC: IBS Mask */
\r
12467 #define HRPWM0_CSG_CC_IMCS_Pos 8 /*!< HRPWM0_CSG CC: IMCS Position */
\r
12468 #define HRPWM0_CSG_CC_IMCS_Msk (0x01UL << HRPWM0_CSG_CC_IMCS_Pos) /*!< HRPWM0_CSG CC: IMCS Mask */
\r
12469 #define HRPWM0_CSG_CC_IMCC_Pos 9 /*!< HRPWM0_CSG CC: IMCC Position */
\r
12470 #define HRPWM0_CSG_CC_IMCC_Msk (0x03UL << HRPWM0_CSG_CC_IMCC_Pos) /*!< HRPWM0_CSG CC: IMCC Mask */
\r
12471 #define HRPWM0_CSG_CC_ESE_Pos 11 /*!< HRPWM0_CSG CC: ESE Position */
\r
12472 #define HRPWM0_CSG_CC_ESE_Msk (0x01UL << HRPWM0_CSG_CC_ESE_Pos) /*!< HRPWM0_CSG CC: ESE Mask */
\r
12473 #define HRPWM0_CSG_CC_OIE_Pos 12 /*!< HRPWM0_CSG CC: OIE Position */
\r
12474 #define HRPWM0_CSG_CC_OIE_Msk (0x01UL << HRPWM0_CSG_CC_OIE_Pos) /*!< HRPWM0_CSG CC: OIE Mask */
\r
12475 #define HRPWM0_CSG_CC_OSE_Pos 13 /*!< HRPWM0_CSG CC: OSE Position */
\r
12476 #define HRPWM0_CSG_CC_OSE_Msk (0x01UL << HRPWM0_CSG_CC_OSE_Pos) /*!< HRPWM0_CSG CC: OSE Mask */
\r
12477 #define HRPWM0_CSG_CC_BLMC_Pos 14 /*!< HRPWM0_CSG CC: BLMC Position */
\r
12478 #define HRPWM0_CSG_CC_BLMC_Msk (0x03UL << HRPWM0_CSG_CC_BLMC_Pos) /*!< HRPWM0_CSG CC: BLMC Mask */
\r
12479 #define HRPWM0_CSG_CC_EBE_Pos 16 /*!< HRPWM0_CSG CC: EBE Position */
\r
12480 #define HRPWM0_CSG_CC_EBE_Msk (0x01UL << HRPWM0_CSG_CC_EBE_Pos) /*!< HRPWM0_CSG CC: EBE Mask */
\r
12481 #define HRPWM0_CSG_CC_COFE_Pos 17 /*!< HRPWM0_CSG CC: COFE Position */
\r
12482 #define HRPWM0_CSG_CC_COFE_Msk (0x01UL << HRPWM0_CSG_CC_COFE_Pos) /*!< HRPWM0_CSG CC: COFE Mask */
\r
12483 #define HRPWM0_CSG_CC_COFM_Pos 18 /*!< HRPWM0_CSG CC: COFM Position */
\r
12484 #define HRPWM0_CSG_CC_COFM_Msk (0x0fUL << HRPWM0_CSG_CC_COFM_Pos) /*!< HRPWM0_CSG CC: COFM Mask */
\r
12485 #define HRPWM0_CSG_CC_COFC_Pos 24 /*!< HRPWM0_CSG CC: COFC Position */
\r
12486 #define HRPWM0_CSG_CC_COFC_Msk (0x03UL << HRPWM0_CSG_CC_COFC_Pos) /*!< HRPWM0_CSG CC: COFC Mask */
\r
12488 /* ------------------------------- HRPWM0_CSG_PLC ------------------------------- */
\r
12489 #define HRPWM0_CSG_PLC_IPLS_Pos 0 /*!< HRPWM0_CSG PLC: IPLS Position */
\r
12490 #define HRPWM0_CSG_PLC_IPLS_Msk (0x0fUL << HRPWM0_CSG_PLC_IPLS_Pos) /*!< HRPWM0_CSG PLC: IPLS Mask */
\r
12491 #define HRPWM0_CSG_PLC_PLCL_Pos 8 /*!< HRPWM0_CSG PLC: PLCL Position */
\r
12492 #define HRPWM0_CSG_PLC_PLCL_Msk (0x03UL << HRPWM0_CSG_PLC_PLCL_Pos) /*!< HRPWM0_CSG PLC: PLCL Mask */
\r
12493 #define HRPWM0_CSG_PLC_PSL_Pos 10 /*!< HRPWM0_CSG PLC: PSL Position */
\r
12494 #define HRPWM0_CSG_PLC_PSL_Msk (0x01UL << HRPWM0_CSG_PLC_PSL_Pos) /*!< HRPWM0_CSG PLC: PSL Mask */
\r
12495 #define HRPWM0_CSG_PLC_PLSW_Pos 11 /*!< HRPWM0_CSG PLC: PLSW Position */
\r
12496 #define HRPWM0_CSG_PLC_PLSW_Msk (0x01UL << HRPWM0_CSG_PLC_PLSW_Pos) /*!< HRPWM0_CSG PLC: PLSW Mask */
\r
12497 #define HRPWM0_CSG_PLC_PLEC_Pos 12 /*!< HRPWM0_CSG PLC: PLEC Position */
\r
12498 #define HRPWM0_CSG_PLC_PLEC_Msk (0x03UL << HRPWM0_CSG_PLC_PLEC_Pos) /*!< HRPWM0_CSG PLC: PLEC Mask */
\r
12499 #define HRPWM0_CSG_PLC_PLXC_Pos 14 /*!< HRPWM0_CSG PLC: PLXC Position */
\r
12500 #define HRPWM0_CSG_PLC_PLXC_Msk (0x03UL << HRPWM0_CSG_PLC_PLXC_Pos) /*!< HRPWM0_CSG PLC: PLXC Mask */
\r
12502 /* ------------------------------- HRPWM0_CSG_BLV ------------------------------- */
\r
12503 #define HRPWM0_CSG_BLV_BLV_Pos 0 /*!< HRPWM0_CSG BLV: BLV Position */
\r
12504 #define HRPWM0_CSG_BLV_BLV_Msk (0x000000ffUL << HRPWM0_CSG_BLV_BLV_Pos) /*!< HRPWM0_CSG BLV: BLV Mask */
\r
12506 /* ------------------------------- HRPWM0_CSG_SRE ------------------------------- */
\r
12507 #define HRPWM0_CSG_SRE_VLS1E_Pos 0 /*!< HRPWM0_CSG SRE: VLS1E Position */
\r
12508 #define HRPWM0_CSG_SRE_VLS1E_Msk (0x01UL << HRPWM0_CSG_SRE_VLS1E_Pos) /*!< HRPWM0_CSG SRE: VLS1E Mask */
\r
12509 #define HRPWM0_CSG_SRE_VLS2E_Pos 1 /*!< HRPWM0_CSG SRE: VLS2E Position */
\r
12510 #define HRPWM0_CSG_SRE_VLS2E_Msk (0x01UL << HRPWM0_CSG_SRE_VLS2E_Pos) /*!< HRPWM0_CSG SRE: VLS2E Mask */
\r
12511 #define HRPWM0_CSG_SRE_TRGSE_Pos 2 /*!< HRPWM0_CSG SRE: TRGSE Position */
\r
12512 #define HRPWM0_CSG_SRE_TRGSE_Msk (0x01UL << HRPWM0_CSG_SRE_TRGSE_Pos) /*!< HRPWM0_CSG SRE: TRGSE Mask */
\r
12513 #define HRPWM0_CSG_SRE_STRSE_Pos 3 /*!< HRPWM0_CSG SRE: STRSE Position */
\r
12514 #define HRPWM0_CSG_SRE_STRSE_Msk (0x01UL << HRPWM0_CSG_SRE_STRSE_Pos) /*!< HRPWM0_CSG SRE: STRSE Mask */
\r
12515 #define HRPWM0_CSG_SRE_STPSE_Pos 4 /*!< HRPWM0_CSG SRE: STPSE Position */
\r
12516 #define HRPWM0_CSG_SRE_STPSE_Msk (0x01UL << HRPWM0_CSG_SRE_STPSE_Pos) /*!< HRPWM0_CSG SRE: STPSE Mask */
\r
12517 #define HRPWM0_CSG_SRE_STDE_Pos 5 /*!< HRPWM0_CSG SRE: STDE Position */
\r
12518 #define HRPWM0_CSG_SRE_STDE_Msk (0x01UL << HRPWM0_CSG_SRE_STDE_Pos) /*!< HRPWM0_CSG SRE: STDE Mask */
\r
12519 #define HRPWM0_CSG_SRE_CRSE_Pos 6 /*!< HRPWM0_CSG SRE: CRSE Position */
\r
12520 #define HRPWM0_CSG_SRE_CRSE_Msk (0x01UL << HRPWM0_CSG_SRE_CRSE_Pos) /*!< HRPWM0_CSG SRE: CRSE Mask */
\r
12521 #define HRPWM0_CSG_SRE_CFSE_Pos 7 /*!< HRPWM0_CSG SRE: CFSE Position */
\r
12522 #define HRPWM0_CSG_SRE_CFSE_Msk (0x01UL << HRPWM0_CSG_SRE_CFSE_Pos) /*!< HRPWM0_CSG SRE: CFSE Mask */
\r
12523 #define HRPWM0_CSG_SRE_CSEE_Pos 8 /*!< HRPWM0_CSG SRE: CSEE Position */
\r
12524 #define HRPWM0_CSG_SRE_CSEE_Msk (0x01UL << HRPWM0_CSG_SRE_CSEE_Pos) /*!< HRPWM0_CSG SRE: CSEE Mask */
\r
12526 /* ------------------------------- HRPWM0_CSG_SRS ------------------------------- */
\r
12527 #define HRPWM0_CSG_SRS_VLS1S_Pos 0 /*!< HRPWM0_CSG SRS: VLS1S Position */
\r
12528 #define HRPWM0_CSG_SRS_VLS1S_Msk (0x03UL << HRPWM0_CSG_SRS_VLS1S_Pos) /*!< HRPWM0_CSG SRS: VLS1S Mask */
\r
12529 #define HRPWM0_CSG_SRS_VLS2S_Pos 2 /*!< HRPWM0_CSG SRS: VLS2S Position */
\r
12530 #define HRPWM0_CSG_SRS_VLS2S_Msk (0x03UL << HRPWM0_CSG_SRS_VLS2S_Pos) /*!< HRPWM0_CSG SRS: VLS2S Mask */
\r
12531 #define HRPWM0_CSG_SRS_TRLS_Pos 4 /*!< HRPWM0_CSG SRS: TRLS Position */
\r
12532 #define HRPWM0_CSG_SRS_TRLS_Msk (0x03UL << HRPWM0_CSG_SRS_TRLS_Pos) /*!< HRPWM0_CSG SRS: TRLS Mask */
\r
12533 #define HRPWM0_CSG_SRS_SSLS_Pos 6 /*!< HRPWM0_CSG SRS: SSLS Position */
\r
12534 #define HRPWM0_CSG_SRS_SSLS_Msk (0x03UL << HRPWM0_CSG_SRS_SSLS_Pos) /*!< HRPWM0_CSG SRS: SSLS Mask */
\r
12535 #define HRPWM0_CSG_SRS_STLS_Pos 8 /*!< HRPWM0_CSG SRS: STLS Position */
\r
12536 #define HRPWM0_CSG_SRS_STLS_Msk (0x03UL << HRPWM0_CSG_SRS_STLS_Pos) /*!< HRPWM0_CSG SRS: STLS Mask */
\r
12537 #define HRPWM0_CSG_SRS_CRFLS_Pos 10 /*!< HRPWM0_CSG SRS: CRFLS Position */
\r
12538 #define HRPWM0_CSG_SRS_CRFLS_Msk (0x03UL << HRPWM0_CSG_SRS_CRFLS_Pos) /*!< HRPWM0_CSG SRS: CRFLS Mask */
\r
12539 #define HRPWM0_CSG_SRS_CSLS_Pos 12 /*!< HRPWM0_CSG SRS: CSLS Position */
\r
12540 #define HRPWM0_CSG_SRS_CSLS_Msk (0x03UL << HRPWM0_CSG_SRS_CSLS_Pos) /*!< HRPWM0_CSG SRS: CSLS Mask */
\r
12542 /* ------------------------------- HRPWM0_CSG_SWS ------------------------------- */
\r
12543 #define HRPWM0_CSG_SWS_SVLS1_Pos 0 /*!< HRPWM0_CSG SWS: SVLS1 Position */
\r
12544 #define HRPWM0_CSG_SWS_SVLS1_Msk (0x01UL << HRPWM0_CSG_SWS_SVLS1_Pos) /*!< HRPWM0_CSG SWS: SVLS1 Mask */
\r
12545 #define HRPWM0_CSG_SWS_SVLS2_Pos 1 /*!< HRPWM0_CSG SWS: SVLS2 Position */
\r
12546 #define HRPWM0_CSG_SWS_SVLS2_Msk (0x01UL << HRPWM0_CSG_SWS_SVLS2_Pos) /*!< HRPWM0_CSG SWS: SVLS2 Mask */
\r
12547 #define HRPWM0_CSG_SWS_STRGS_Pos 2 /*!< HRPWM0_CSG SWS: STRGS Position */
\r
12548 #define HRPWM0_CSG_SWS_STRGS_Msk (0x01UL << HRPWM0_CSG_SWS_STRGS_Pos) /*!< HRPWM0_CSG SWS: STRGS Mask */
\r
12549 #define HRPWM0_CSG_SWS_SSTRS_Pos 3 /*!< HRPWM0_CSG SWS: SSTRS Position */
\r
12550 #define HRPWM0_CSG_SWS_SSTRS_Msk (0x01UL << HRPWM0_CSG_SWS_SSTRS_Pos) /*!< HRPWM0_CSG SWS: SSTRS Mask */
\r
12551 #define HRPWM0_CSG_SWS_SSTPS_Pos 4 /*!< HRPWM0_CSG SWS: SSTPS Position */
\r
12552 #define HRPWM0_CSG_SWS_SSTPS_Msk (0x01UL << HRPWM0_CSG_SWS_SSTPS_Pos) /*!< HRPWM0_CSG SWS: SSTPS Mask */
\r
12553 #define HRPWM0_CSG_SWS_SSTD_Pos 5 /*!< HRPWM0_CSG SWS: SSTD Position */
\r
12554 #define HRPWM0_CSG_SWS_SSTD_Msk (0x01UL << HRPWM0_CSG_SWS_SSTD_Pos) /*!< HRPWM0_CSG SWS: SSTD Mask */
\r
12555 #define HRPWM0_CSG_SWS_SCRS_Pos 6 /*!< HRPWM0_CSG SWS: SCRS Position */
\r
12556 #define HRPWM0_CSG_SWS_SCRS_Msk (0x01UL << HRPWM0_CSG_SWS_SCRS_Pos) /*!< HRPWM0_CSG SWS: SCRS Mask */
\r
12557 #define HRPWM0_CSG_SWS_SCFS_Pos 7 /*!< HRPWM0_CSG SWS: SCFS Position */
\r
12558 #define HRPWM0_CSG_SWS_SCFS_Msk (0x01UL << HRPWM0_CSG_SWS_SCFS_Pos) /*!< HRPWM0_CSG SWS: SCFS Mask */
\r
12559 #define HRPWM0_CSG_SWS_SCSS_Pos 8 /*!< HRPWM0_CSG SWS: SCSS Position */
\r
12560 #define HRPWM0_CSG_SWS_SCSS_Msk (0x01UL << HRPWM0_CSG_SWS_SCSS_Pos) /*!< HRPWM0_CSG SWS: SCSS Mask */
\r
12562 /* ------------------------------- HRPWM0_CSG_SWC ------------------------------- */
\r
12563 #define HRPWM0_CSG_SWC_CVLS1_Pos 0 /*!< HRPWM0_CSG SWC: CVLS1 Position */
\r
12564 #define HRPWM0_CSG_SWC_CVLS1_Msk (0x01UL << HRPWM0_CSG_SWC_CVLS1_Pos) /*!< HRPWM0_CSG SWC: CVLS1 Mask */
\r
12565 #define HRPWM0_CSG_SWC_CVLS2_Pos 1 /*!< HRPWM0_CSG SWC: CVLS2 Position */
\r
12566 #define HRPWM0_CSG_SWC_CVLS2_Msk (0x01UL << HRPWM0_CSG_SWC_CVLS2_Pos) /*!< HRPWM0_CSG SWC: CVLS2 Mask */
\r
12567 #define HRPWM0_CSG_SWC_CTRGS_Pos 2 /*!< HRPWM0_CSG SWC: CTRGS Position */
\r
12568 #define HRPWM0_CSG_SWC_CTRGS_Msk (0x01UL << HRPWM0_CSG_SWC_CTRGS_Pos) /*!< HRPWM0_CSG SWC: CTRGS Mask */
\r
12569 #define HRPWM0_CSG_SWC_CSTRS_Pos 3 /*!< HRPWM0_CSG SWC: CSTRS Position */
\r
12570 #define HRPWM0_CSG_SWC_CSTRS_Msk (0x01UL << HRPWM0_CSG_SWC_CSTRS_Pos) /*!< HRPWM0_CSG SWC: CSTRS Mask */
\r
12571 #define HRPWM0_CSG_SWC_CSTPS_Pos 4 /*!< HRPWM0_CSG SWC: CSTPS Position */
\r
12572 #define HRPWM0_CSG_SWC_CSTPS_Msk (0x01UL << HRPWM0_CSG_SWC_CSTPS_Pos) /*!< HRPWM0_CSG SWC: CSTPS Mask */
\r
12573 #define HRPWM0_CSG_SWC_CSTD_Pos 5 /*!< HRPWM0_CSG SWC: CSTD Position */
\r
12574 #define HRPWM0_CSG_SWC_CSTD_Msk (0x01UL << HRPWM0_CSG_SWC_CSTD_Pos) /*!< HRPWM0_CSG SWC: CSTD Mask */
\r
12575 #define HRPWM0_CSG_SWC_CCRS_Pos 6 /*!< HRPWM0_CSG SWC: CCRS Position */
\r
12576 #define HRPWM0_CSG_SWC_CCRS_Msk (0x01UL << HRPWM0_CSG_SWC_CCRS_Pos) /*!< HRPWM0_CSG SWC: CCRS Mask */
\r
12577 #define HRPWM0_CSG_SWC_CCFS_Pos 7 /*!< HRPWM0_CSG SWC: CCFS Position */
\r
12578 #define HRPWM0_CSG_SWC_CCFS_Msk (0x01UL << HRPWM0_CSG_SWC_CCFS_Pos) /*!< HRPWM0_CSG SWC: CCFS Mask */
\r
12579 #define HRPWM0_CSG_SWC_CCSS_Pos 8 /*!< HRPWM0_CSG SWC: CCSS Position */
\r
12580 #define HRPWM0_CSG_SWC_CCSS_Msk (0x01UL << HRPWM0_CSG_SWC_CCSS_Pos) /*!< HRPWM0_CSG SWC: CCSS Mask */
\r
12582 /* ------------------------------ HRPWM0_CSG_ISTAT ------------------------------ */
\r
12583 #define HRPWM0_CSG_ISTAT_VLS1S_Pos 0 /*!< HRPWM0_CSG ISTAT: VLS1S Position */
\r
12584 #define HRPWM0_CSG_ISTAT_VLS1S_Msk (0x01UL << HRPWM0_CSG_ISTAT_VLS1S_Pos) /*!< HRPWM0_CSG ISTAT: VLS1S Mask */
\r
12585 #define HRPWM0_CSG_ISTAT_VLS2S_Pos 1 /*!< HRPWM0_CSG ISTAT: VLS2S Position */
\r
12586 #define HRPWM0_CSG_ISTAT_VLS2S_Msk (0x01UL << HRPWM0_CSG_ISTAT_VLS2S_Pos) /*!< HRPWM0_CSG ISTAT: VLS2S Mask */
\r
12587 #define HRPWM0_CSG_ISTAT_TRGSS_Pos 2 /*!< HRPWM0_CSG ISTAT: TRGSS Position */
\r
12588 #define HRPWM0_CSG_ISTAT_TRGSS_Msk (0x01UL << HRPWM0_CSG_ISTAT_TRGSS_Pos) /*!< HRPWM0_CSG ISTAT: TRGSS Mask */
\r
12589 #define HRPWM0_CSG_ISTAT_STRSS_Pos 3 /*!< HRPWM0_CSG ISTAT: STRSS Position */
\r
12590 #define HRPWM0_CSG_ISTAT_STRSS_Msk (0x01UL << HRPWM0_CSG_ISTAT_STRSS_Pos) /*!< HRPWM0_CSG ISTAT: STRSS Mask */
\r
12591 #define HRPWM0_CSG_ISTAT_STPSS_Pos 4 /*!< HRPWM0_CSG ISTAT: STPSS Position */
\r
12592 #define HRPWM0_CSG_ISTAT_STPSS_Msk (0x01UL << HRPWM0_CSG_ISTAT_STPSS_Pos) /*!< HRPWM0_CSG ISTAT: STPSS Mask */
\r
12593 #define HRPWM0_CSG_ISTAT_STDS_Pos 5 /*!< HRPWM0_CSG ISTAT: STDS Position */
\r
12594 #define HRPWM0_CSG_ISTAT_STDS_Msk (0x01UL << HRPWM0_CSG_ISTAT_STDS_Pos) /*!< HRPWM0_CSG ISTAT: STDS Mask */
\r
12595 #define HRPWM0_CSG_ISTAT_CRSS_Pos 6 /*!< HRPWM0_CSG ISTAT: CRSS Position */
\r
12596 #define HRPWM0_CSG_ISTAT_CRSS_Msk (0x01UL << HRPWM0_CSG_ISTAT_CRSS_Pos) /*!< HRPWM0_CSG ISTAT: CRSS Mask */
\r
12597 #define HRPWM0_CSG_ISTAT_CFSS_Pos 7 /*!< HRPWM0_CSG ISTAT: CFSS Position */
\r
12598 #define HRPWM0_CSG_ISTAT_CFSS_Msk (0x01UL << HRPWM0_CSG_ISTAT_CFSS_Pos) /*!< HRPWM0_CSG ISTAT: CFSS Mask */
\r
12599 #define HRPWM0_CSG_ISTAT_CSES_Pos 8 /*!< HRPWM0_CSG ISTAT: CSES Position */
\r
12600 #define HRPWM0_CSG_ISTAT_CSES_Msk (0x01UL << HRPWM0_CSG_ISTAT_CSES_Pos) /*!< HRPWM0_CSG ISTAT: CSES Mask */
\r
12603 /* ================================================================================ */
\r
12604 /* ================ struct 'HRPWM0_CSG0' Position & Mask ================ */
\r
12605 /* ================================================================================ */
\r
12608 /* ------------------------------- HRPWM0_CSG0_DCI ------------------------------ */
\r
12609 #define HRPWM0_CSG0_DCI_SVIS_Pos 0 /*!< HRPWM0_CSG0 DCI: SVIS Position */
\r
12610 #define HRPWM0_CSG0_DCI_SVIS_Msk (0x0fUL << HRPWM0_CSG0_DCI_SVIS_Pos) /*!< HRPWM0_CSG0 DCI: SVIS Mask */
\r
12611 #define HRPWM0_CSG0_DCI_STRIS_Pos 4 /*!< HRPWM0_CSG0 DCI: STRIS Position */
\r
12612 #define HRPWM0_CSG0_DCI_STRIS_Msk (0x0fUL << HRPWM0_CSG0_DCI_STRIS_Pos) /*!< HRPWM0_CSG0 DCI: STRIS Mask */
\r
12613 #define HRPWM0_CSG0_DCI_STPIS_Pos 8 /*!< HRPWM0_CSG0 DCI: STPIS Position */
\r
12614 #define HRPWM0_CSG0_DCI_STPIS_Msk (0x0fUL << HRPWM0_CSG0_DCI_STPIS_Pos) /*!< HRPWM0_CSG0 DCI: STPIS Mask */
\r
12615 #define HRPWM0_CSG0_DCI_TRGIS_Pos 12 /*!< HRPWM0_CSG0 DCI: TRGIS Position */
\r
12616 #define HRPWM0_CSG0_DCI_TRGIS_Msk (0x0fUL << HRPWM0_CSG0_DCI_TRGIS_Pos) /*!< HRPWM0_CSG0 DCI: TRGIS Mask */
\r
12617 #define HRPWM0_CSG0_DCI_STIS_Pos 16 /*!< HRPWM0_CSG0 DCI: STIS Position */
\r
12618 #define HRPWM0_CSG0_DCI_STIS_Msk (0x0fUL << HRPWM0_CSG0_DCI_STIS_Pos) /*!< HRPWM0_CSG0 DCI: STIS Mask */
\r
12619 #define HRPWM0_CSG0_DCI_SCS_Pos 20 /*!< HRPWM0_CSG0 DCI: SCS Position */
\r
12620 #define HRPWM0_CSG0_DCI_SCS_Msk (0x03UL << HRPWM0_CSG0_DCI_SCS_Pos) /*!< HRPWM0_CSG0 DCI: SCS Mask */
\r
12622 /* ------------------------------- HRPWM0_CSG0_IES ------------------------------ */
\r
12623 #define HRPWM0_CSG0_IES_SVLS_Pos 0 /*!< HRPWM0_CSG0 IES: SVLS Position */
\r
12624 #define HRPWM0_CSG0_IES_SVLS_Msk (0x03UL << HRPWM0_CSG0_IES_SVLS_Pos) /*!< HRPWM0_CSG0 IES: SVLS Mask */
\r
12625 #define HRPWM0_CSG0_IES_STRES_Pos 2 /*!< HRPWM0_CSG0 IES: STRES Position */
\r
12626 #define HRPWM0_CSG0_IES_STRES_Msk (0x03UL << HRPWM0_CSG0_IES_STRES_Pos) /*!< HRPWM0_CSG0 IES: STRES Mask */
\r
12627 #define HRPWM0_CSG0_IES_STPES_Pos 4 /*!< HRPWM0_CSG0 IES: STPES Position */
\r
12628 #define HRPWM0_CSG0_IES_STPES_Msk (0x03UL << HRPWM0_CSG0_IES_STPES_Pos) /*!< HRPWM0_CSG0 IES: STPES Mask */
\r
12629 #define HRPWM0_CSG0_IES_TRGES_Pos 6 /*!< HRPWM0_CSG0 IES: TRGES Position */
\r
12630 #define HRPWM0_CSG0_IES_TRGES_Msk (0x03UL << HRPWM0_CSG0_IES_TRGES_Pos) /*!< HRPWM0_CSG0 IES: TRGES Mask */
\r
12631 #define HRPWM0_CSG0_IES_STES_Pos 8 /*!< HRPWM0_CSG0 IES: STES Position */
\r
12632 #define HRPWM0_CSG0_IES_STES_Msk (0x03UL << HRPWM0_CSG0_IES_STES_Pos) /*!< HRPWM0_CSG0 IES: STES Mask */
\r
12634 /* ------------------------------- HRPWM0_CSG0_SC ------------------------------- */
\r
12635 #define HRPWM0_CSG0_SC_PSRM_Pos 0 /*!< HRPWM0_CSG0 SC: PSRM Position */
\r
12636 #define HRPWM0_CSG0_SC_PSRM_Msk (0x03UL << HRPWM0_CSG0_SC_PSRM_Pos) /*!< HRPWM0_CSG0 SC: PSRM Mask */
\r
12637 #define HRPWM0_CSG0_SC_PSTM_Pos 2 /*!< HRPWM0_CSG0 SC: PSTM Position */
\r
12638 #define HRPWM0_CSG0_SC_PSTM_Msk (0x03UL << HRPWM0_CSG0_SC_PSTM_Pos) /*!< HRPWM0_CSG0 SC: PSTM Mask */
\r
12639 #define HRPWM0_CSG0_SC_FPD_Pos 4 /*!< HRPWM0_CSG0 SC: FPD Position */
\r
12640 #define HRPWM0_CSG0_SC_FPD_Msk (0x01UL << HRPWM0_CSG0_SC_FPD_Pos) /*!< HRPWM0_CSG0 SC: FPD Mask */
\r
12641 #define HRPWM0_CSG0_SC_PSV_Pos 5 /*!< HRPWM0_CSG0 SC: PSV Position */
\r
12642 #define HRPWM0_CSG0_SC_PSV_Msk (0x03UL << HRPWM0_CSG0_SC_PSV_Pos) /*!< HRPWM0_CSG0 SC: PSV Mask */
\r
12643 #define HRPWM0_CSG0_SC_SCM_Pos 8 /*!< HRPWM0_CSG0 SC: SCM Position */
\r
12644 #define HRPWM0_CSG0_SC_SCM_Msk (0x03UL << HRPWM0_CSG0_SC_SCM_Pos) /*!< HRPWM0_CSG0 SC: SCM Mask */
\r
12645 #define HRPWM0_CSG0_SC_SSRM_Pos 10 /*!< HRPWM0_CSG0 SC: SSRM Position */
\r
12646 #define HRPWM0_CSG0_SC_SSRM_Msk (0x03UL << HRPWM0_CSG0_SC_SSRM_Pos) /*!< HRPWM0_CSG0 SC: SSRM Mask */
\r
12647 #define HRPWM0_CSG0_SC_SSTM_Pos 12 /*!< HRPWM0_CSG0 SC: SSTM Position */
\r
12648 #define HRPWM0_CSG0_SC_SSTM_Msk (0x03UL << HRPWM0_CSG0_SC_SSTM_Pos) /*!< HRPWM0_CSG0 SC: SSTM Mask */
\r
12649 #define HRPWM0_CSG0_SC_SVSC_Pos 14 /*!< HRPWM0_CSG0 SC: SVSC Position */
\r
12650 #define HRPWM0_CSG0_SC_SVSC_Msk (0x03UL << HRPWM0_CSG0_SC_SVSC_Pos) /*!< HRPWM0_CSG0 SC: SVSC Mask */
\r
12651 #define HRPWM0_CSG0_SC_SWSM_Pos 16 /*!< HRPWM0_CSG0 SC: SWSM Position */
\r
12652 #define HRPWM0_CSG0_SC_SWSM_Msk (0x03UL << HRPWM0_CSG0_SC_SWSM_Pos) /*!< HRPWM0_CSG0 SC: SWSM Mask */
\r
12653 #define HRPWM0_CSG0_SC_GCFG_Pos 18 /*!< HRPWM0_CSG0 SC: GCFG Position */
\r
12654 #define HRPWM0_CSG0_SC_GCFG_Msk (0x03UL << HRPWM0_CSG0_SC_GCFG_Pos) /*!< HRPWM0_CSG0 SC: GCFG Mask */
\r
12655 #define HRPWM0_CSG0_SC_IST_Pos 20 /*!< HRPWM0_CSG0 SC: IST Position */
\r
12656 #define HRPWM0_CSG0_SC_IST_Msk (0x01UL << HRPWM0_CSG0_SC_IST_Pos) /*!< HRPWM0_CSG0 SC: IST Mask */
\r
12657 #define HRPWM0_CSG0_SC_PSE_Pos 21 /*!< HRPWM0_CSG0 SC: PSE Position */
\r
12658 #define HRPWM0_CSG0_SC_PSE_Msk (0x01UL << HRPWM0_CSG0_SC_PSE_Pos) /*!< HRPWM0_CSG0 SC: PSE Mask */
\r
12659 #define HRPWM0_CSG0_SC_PSWM_Pos 24 /*!< HRPWM0_CSG0 SC: PSWM Position */
\r
12660 #define HRPWM0_CSG0_SC_PSWM_Msk (0x03UL << HRPWM0_CSG0_SC_PSWM_Pos) /*!< HRPWM0_CSG0 SC: PSWM Mask */
\r
12662 /* ------------------------------- HRPWM0_CSG0_PC ------------------------------- */
\r
12663 #define HRPWM0_CSG0_PC_PSWV_Pos 0 /*!< HRPWM0_CSG0 PC: PSWV Position */
\r
12664 #define HRPWM0_CSG0_PC_PSWV_Msk (0x3fUL << HRPWM0_CSG0_PC_PSWV_Pos) /*!< HRPWM0_CSG0 PC: PSWV Mask */
\r
12666 /* ------------------------------ HRPWM0_CSG0_DSV1 ------------------------------ */
\r
12667 #define HRPWM0_CSG0_DSV1_DSV1_Pos 0 /*!< HRPWM0_CSG0 DSV1: DSV1 Position */
\r
12668 #define HRPWM0_CSG0_DSV1_DSV1_Msk (0x000003ffUL << HRPWM0_CSG0_DSV1_DSV1_Pos) /*!< HRPWM0_CSG0 DSV1: DSV1 Mask */
\r
12670 /* ------------------------------ HRPWM0_CSG0_DSV2 ------------------------------ */
\r
12671 #define HRPWM0_CSG0_DSV2_DSV2_Pos 0 /*!< HRPWM0_CSG0 DSV2: DSV2 Position */
\r
12672 #define HRPWM0_CSG0_DSV2_DSV2_Msk (0x000003ffUL << HRPWM0_CSG0_DSV2_DSV2_Pos) /*!< HRPWM0_CSG0 DSV2: DSV2 Mask */
\r
12674 /* ------------------------------ HRPWM0_CSG0_SDSV1 ----------------------------- */
\r
12675 #define HRPWM0_CSG0_SDSV1_SDSV1_Pos 0 /*!< HRPWM0_CSG0 SDSV1: SDSV1 Position */
\r
12676 #define HRPWM0_CSG0_SDSV1_SDSV1_Msk (0x000003ffUL << HRPWM0_CSG0_SDSV1_SDSV1_Pos) /*!< HRPWM0_CSG0 SDSV1: SDSV1 Mask */
\r
12678 /* ------------------------------- HRPWM0_CSG0_SPC ------------------------------ */
\r
12679 #define HRPWM0_CSG0_SPC_SPSWV_Pos 0 /*!< HRPWM0_CSG0 SPC: SPSWV Position */
\r
12680 #define HRPWM0_CSG0_SPC_SPSWV_Msk (0x3fUL << HRPWM0_CSG0_SPC_SPSWV_Pos) /*!< HRPWM0_CSG0 SPC: SPSWV Mask */
\r
12682 /* ------------------------------- HRPWM0_CSG0_CC ------------------------------- */
\r
12683 #define HRPWM0_CSG0_CC_IBS_Pos 0 /*!< HRPWM0_CSG0 CC: IBS Position */
\r
12684 #define HRPWM0_CSG0_CC_IBS_Msk (0x0fUL << HRPWM0_CSG0_CC_IBS_Pos) /*!< HRPWM0_CSG0 CC: IBS Mask */
\r
12685 #define HRPWM0_CSG0_CC_IMCS_Pos 8 /*!< HRPWM0_CSG0 CC: IMCS Position */
\r
12686 #define HRPWM0_CSG0_CC_IMCS_Msk (0x01UL << HRPWM0_CSG0_CC_IMCS_Pos) /*!< HRPWM0_CSG0 CC: IMCS Mask */
\r
12687 #define HRPWM0_CSG0_CC_IMCC_Pos 9 /*!< HRPWM0_CSG0 CC: IMCC Position */
\r
12688 #define HRPWM0_CSG0_CC_IMCC_Msk (0x03UL << HRPWM0_CSG0_CC_IMCC_Pos) /*!< HRPWM0_CSG0 CC: IMCC Mask */
\r
12689 #define HRPWM0_CSG0_CC_ESE_Pos 11 /*!< HRPWM0_CSG0 CC: ESE Position */
\r
12690 #define HRPWM0_CSG0_CC_ESE_Msk (0x01UL << HRPWM0_CSG0_CC_ESE_Pos) /*!< HRPWM0_CSG0 CC: ESE Mask */
\r
12691 #define HRPWM0_CSG0_CC_OIE_Pos 12 /*!< HRPWM0_CSG0 CC: OIE Position */
\r
12692 #define HRPWM0_CSG0_CC_OIE_Msk (0x01UL << HRPWM0_CSG0_CC_OIE_Pos) /*!< HRPWM0_CSG0 CC: OIE Mask */
\r
12693 #define HRPWM0_CSG0_CC_OSE_Pos 13 /*!< HRPWM0_CSG0 CC: OSE Position */
\r
12694 #define HRPWM0_CSG0_CC_OSE_Msk (0x01UL << HRPWM0_CSG0_CC_OSE_Pos) /*!< HRPWM0_CSG0 CC: OSE Mask */
\r
12695 #define HRPWM0_CSG0_CC_BLMC_Pos 14 /*!< HRPWM0_CSG0 CC: BLMC Position */
\r
12696 #define HRPWM0_CSG0_CC_BLMC_Msk (0x03UL << HRPWM0_CSG0_CC_BLMC_Pos) /*!< HRPWM0_CSG0 CC: BLMC Mask */
\r
12697 #define HRPWM0_CSG0_CC_EBE_Pos 16 /*!< HRPWM0_CSG0 CC: EBE Position */
\r
12698 #define HRPWM0_CSG0_CC_EBE_Msk (0x01UL << HRPWM0_CSG0_CC_EBE_Pos) /*!< HRPWM0_CSG0 CC: EBE Mask */
\r
12699 #define HRPWM0_CSG0_CC_COFE_Pos 17 /*!< HRPWM0_CSG0 CC: COFE Position */
\r
12700 #define HRPWM0_CSG0_CC_COFE_Msk (0x01UL << HRPWM0_CSG0_CC_COFE_Pos) /*!< HRPWM0_CSG0 CC: COFE Mask */
\r
12701 #define HRPWM0_CSG0_CC_COFM_Pos 18 /*!< HRPWM0_CSG0 CC: COFM Position */
\r
12702 #define HRPWM0_CSG0_CC_COFM_Msk (0x0fUL << HRPWM0_CSG0_CC_COFM_Pos) /*!< HRPWM0_CSG0 CC: COFM Mask */
\r
12703 #define HRPWM0_CSG0_CC_COFC_Pos 24 /*!< HRPWM0_CSG0 CC: COFC Position */
\r
12704 #define HRPWM0_CSG0_CC_COFC_Msk (0x03UL << HRPWM0_CSG0_CC_COFC_Pos) /*!< HRPWM0_CSG0 CC: COFC Mask */
\r
12706 /* ------------------------------- HRPWM0_CSG0_PLC ------------------------------ */
\r
12707 #define HRPWM0_CSG0_PLC_IPLS_Pos 0 /*!< HRPWM0_CSG0 PLC: IPLS Position */
\r
12708 #define HRPWM0_CSG0_PLC_IPLS_Msk (0x0fUL << HRPWM0_CSG0_PLC_IPLS_Pos) /*!< HRPWM0_CSG0 PLC: IPLS Mask */
\r
12709 #define HRPWM0_CSG0_PLC_PLCL_Pos 8 /*!< HRPWM0_CSG0 PLC: PLCL Position */
\r
12710 #define HRPWM0_CSG0_PLC_PLCL_Msk (0x03UL << HRPWM0_CSG0_PLC_PLCL_Pos) /*!< HRPWM0_CSG0 PLC: PLCL Mask */
\r
12711 #define HRPWM0_CSG0_PLC_PSL_Pos 10 /*!< HRPWM0_CSG0 PLC: PSL Position */
\r
12712 #define HRPWM0_CSG0_PLC_PSL_Msk (0x01UL << HRPWM0_CSG0_PLC_PSL_Pos) /*!< HRPWM0_CSG0 PLC: PSL Mask */
\r
12713 #define HRPWM0_CSG0_PLC_PLSW_Pos 11 /*!< HRPWM0_CSG0 PLC: PLSW Position */
\r
12714 #define HRPWM0_CSG0_PLC_PLSW_Msk (0x01UL << HRPWM0_CSG0_PLC_PLSW_Pos) /*!< HRPWM0_CSG0 PLC: PLSW Mask */
\r
12715 #define HRPWM0_CSG0_PLC_PLEC_Pos 12 /*!< HRPWM0_CSG0 PLC: PLEC Position */
\r
12716 #define HRPWM0_CSG0_PLC_PLEC_Msk (0x03UL << HRPWM0_CSG0_PLC_PLEC_Pos) /*!< HRPWM0_CSG0 PLC: PLEC Mask */
\r
12717 #define HRPWM0_CSG0_PLC_PLXC_Pos 14 /*!< HRPWM0_CSG0 PLC: PLXC Position */
\r
12718 #define HRPWM0_CSG0_PLC_PLXC_Msk (0x03UL << HRPWM0_CSG0_PLC_PLXC_Pos) /*!< HRPWM0_CSG0 PLC: PLXC Mask */
\r
12720 /* ------------------------------- HRPWM0_CSG0_BLV ------------------------------ */
\r
12721 #define HRPWM0_CSG0_BLV_BLV_Pos 0 /*!< HRPWM0_CSG0 BLV: BLV Position */
\r
12722 #define HRPWM0_CSG0_BLV_BLV_Msk (0x000000ffUL << HRPWM0_CSG0_BLV_BLV_Pos) /*!< HRPWM0_CSG0 BLV: BLV Mask */
\r
12724 /* ------------------------------- HRPWM0_CSG0_SRE ------------------------------ */
\r
12725 #define HRPWM0_CSG0_SRE_VLS1E_Pos 0 /*!< HRPWM0_CSG0 SRE: VLS1E Position */
\r
12726 #define HRPWM0_CSG0_SRE_VLS1E_Msk (0x01UL << HRPWM0_CSG0_SRE_VLS1E_Pos) /*!< HRPWM0_CSG0 SRE: VLS1E Mask */
\r
12727 #define HRPWM0_CSG0_SRE_VLS2E_Pos 1 /*!< HRPWM0_CSG0 SRE: VLS2E Position */
\r
12728 #define HRPWM0_CSG0_SRE_VLS2E_Msk (0x01UL << HRPWM0_CSG0_SRE_VLS2E_Pos) /*!< HRPWM0_CSG0 SRE: VLS2E Mask */
\r
12729 #define HRPWM0_CSG0_SRE_TRGSE_Pos 2 /*!< HRPWM0_CSG0 SRE: TRGSE Position */
\r
12730 #define HRPWM0_CSG0_SRE_TRGSE_Msk (0x01UL << HRPWM0_CSG0_SRE_TRGSE_Pos) /*!< HRPWM0_CSG0 SRE: TRGSE Mask */
\r
12731 #define HRPWM0_CSG0_SRE_STRSE_Pos 3 /*!< HRPWM0_CSG0 SRE: STRSE Position */
\r
12732 #define HRPWM0_CSG0_SRE_STRSE_Msk (0x01UL << HRPWM0_CSG0_SRE_STRSE_Pos) /*!< HRPWM0_CSG0 SRE: STRSE Mask */
\r
12733 #define HRPWM0_CSG0_SRE_STPSE_Pos 4 /*!< HRPWM0_CSG0 SRE: STPSE Position */
\r
12734 #define HRPWM0_CSG0_SRE_STPSE_Msk (0x01UL << HRPWM0_CSG0_SRE_STPSE_Pos) /*!< HRPWM0_CSG0 SRE: STPSE Mask */
\r
12735 #define HRPWM0_CSG0_SRE_STDE_Pos 5 /*!< HRPWM0_CSG0 SRE: STDE Position */
\r
12736 #define HRPWM0_CSG0_SRE_STDE_Msk (0x01UL << HRPWM0_CSG0_SRE_STDE_Pos) /*!< HRPWM0_CSG0 SRE: STDE Mask */
\r
12737 #define HRPWM0_CSG0_SRE_CRSE_Pos 6 /*!< HRPWM0_CSG0 SRE: CRSE Position */
\r
12738 #define HRPWM0_CSG0_SRE_CRSE_Msk (0x01UL << HRPWM0_CSG0_SRE_CRSE_Pos) /*!< HRPWM0_CSG0 SRE: CRSE Mask */
\r
12739 #define HRPWM0_CSG0_SRE_CFSE_Pos 7 /*!< HRPWM0_CSG0 SRE: CFSE Position */
\r
12740 #define HRPWM0_CSG0_SRE_CFSE_Msk (0x01UL << HRPWM0_CSG0_SRE_CFSE_Pos) /*!< HRPWM0_CSG0 SRE: CFSE Mask */
\r
12741 #define HRPWM0_CSG0_SRE_CSEE_Pos 8 /*!< HRPWM0_CSG0 SRE: CSEE Position */
\r
12742 #define HRPWM0_CSG0_SRE_CSEE_Msk (0x01UL << HRPWM0_CSG0_SRE_CSEE_Pos) /*!< HRPWM0_CSG0 SRE: CSEE Mask */
\r
12744 /* ------------------------------- HRPWM0_CSG0_SRS ------------------------------ */
\r
12745 #define HRPWM0_CSG0_SRS_VLS1S_Pos 0 /*!< HRPWM0_CSG0 SRS: VLS1S Position */
\r
12746 #define HRPWM0_CSG0_SRS_VLS1S_Msk (0x03UL << HRPWM0_CSG0_SRS_VLS1S_Pos) /*!< HRPWM0_CSG0 SRS: VLS1S Mask */
\r
12747 #define HRPWM0_CSG0_SRS_VLS2S_Pos 2 /*!< HRPWM0_CSG0 SRS: VLS2S Position */
\r
12748 #define HRPWM0_CSG0_SRS_VLS2S_Msk (0x03UL << HRPWM0_CSG0_SRS_VLS2S_Pos) /*!< HRPWM0_CSG0 SRS: VLS2S Mask */
\r
12749 #define HRPWM0_CSG0_SRS_TRLS_Pos 4 /*!< HRPWM0_CSG0 SRS: TRLS Position */
\r
12750 #define HRPWM0_CSG0_SRS_TRLS_Msk (0x03UL << HRPWM0_CSG0_SRS_TRLS_Pos) /*!< HRPWM0_CSG0 SRS: TRLS Mask */
\r
12751 #define HRPWM0_CSG0_SRS_SSLS_Pos 6 /*!< HRPWM0_CSG0 SRS: SSLS Position */
\r
12752 #define HRPWM0_CSG0_SRS_SSLS_Msk (0x03UL << HRPWM0_CSG0_SRS_SSLS_Pos) /*!< HRPWM0_CSG0 SRS: SSLS Mask */
\r
12753 #define HRPWM0_CSG0_SRS_STLS_Pos 8 /*!< HRPWM0_CSG0 SRS: STLS Position */
\r
12754 #define HRPWM0_CSG0_SRS_STLS_Msk (0x03UL << HRPWM0_CSG0_SRS_STLS_Pos) /*!< HRPWM0_CSG0 SRS: STLS Mask */
\r
12755 #define HRPWM0_CSG0_SRS_CRFLS_Pos 10 /*!< HRPWM0_CSG0 SRS: CRFLS Position */
\r
12756 #define HRPWM0_CSG0_SRS_CRFLS_Msk (0x03UL << HRPWM0_CSG0_SRS_CRFLS_Pos) /*!< HRPWM0_CSG0 SRS: CRFLS Mask */
\r
12757 #define HRPWM0_CSG0_SRS_CSLS_Pos 12 /*!< HRPWM0_CSG0 SRS: CSLS Position */
\r
12758 #define HRPWM0_CSG0_SRS_CSLS_Msk (0x03UL << HRPWM0_CSG0_SRS_CSLS_Pos) /*!< HRPWM0_CSG0 SRS: CSLS Mask */
\r
12760 /* ------------------------------- HRPWM0_CSG0_SWS ------------------------------ */
\r
12761 #define HRPWM0_CSG0_SWS_SVLS1_Pos 0 /*!< HRPWM0_CSG0 SWS: SVLS1 Position */
\r
12762 #define HRPWM0_CSG0_SWS_SVLS1_Msk (0x01UL << HRPWM0_CSG0_SWS_SVLS1_Pos) /*!< HRPWM0_CSG0 SWS: SVLS1 Mask */
\r
12763 #define HRPWM0_CSG0_SWS_SVLS2_Pos 1 /*!< HRPWM0_CSG0 SWS: SVLS2 Position */
\r
12764 #define HRPWM0_CSG0_SWS_SVLS2_Msk (0x01UL << HRPWM0_CSG0_SWS_SVLS2_Pos) /*!< HRPWM0_CSG0 SWS: SVLS2 Mask */
\r
12765 #define HRPWM0_CSG0_SWS_STRGS_Pos 2 /*!< HRPWM0_CSG0 SWS: STRGS Position */
\r
12766 #define HRPWM0_CSG0_SWS_STRGS_Msk (0x01UL << HRPWM0_CSG0_SWS_STRGS_Pos) /*!< HRPWM0_CSG0 SWS: STRGS Mask */
\r
12767 #define HRPWM0_CSG0_SWS_SSTRS_Pos 3 /*!< HRPWM0_CSG0 SWS: SSTRS Position */
\r
12768 #define HRPWM0_CSG0_SWS_SSTRS_Msk (0x01UL << HRPWM0_CSG0_SWS_SSTRS_Pos) /*!< HRPWM0_CSG0 SWS: SSTRS Mask */
\r
12769 #define HRPWM0_CSG0_SWS_SSTPS_Pos 4 /*!< HRPWM0_CSG0 SWS: SSTPS Position */
\r
12770 #define HRPWM0_CSG0_SWS_SSTPS_Msk (0x01UL << HRPWM0_CSG0_SWS_SSTPS_Pos) /*!< HRPWM0_CSG0 SWS: SSTPS Mask */
\r
12771 #define HRPWM0_CSG0_SWS_SSTD_Pos 5 /*!< HRPWM0_CSG0 SWS: SSTD Position */
\r
12772 #define HRPWM0_CSG0_SWS_SSTD_Msk (0x01UL << HRPWM0_CSG0_SWS_SSTD_Pos) /*!< HRPWM0_CSG0 SWS: SSTD Mask */
\r
12773 #define HRPWM0_CSG0_SWS_SCRS_Pos 6 /*!< HRPWM0_CSG0 SWS: SCRS Position */
\r
12774 #define HRPWM0_CSG0_SWS_SCRS_Msk (0x01UL << HRPWM0_CSG0_SWS_SCRS_Pos) /*!< HRPWM0_CSG0 SWS: SCRS Mask */
\r
12775 #define HRPWM0_CSG0_SWS_SCFS_Pos 7 /*!< HRPWM0_CSG0 SWS: SCFS Position */
\r
12776 #define HRPWM0_CSG0_SWS_SCFS_Msk (0x01UL << HRPWM0_CSG0_SWS_SCFS_Pos) /*!< HRPWM0_CSG0 SWS: SCFS Mask */
\r
12777 #define HRPWM0_CSG0_SWS_SCSS_Pos 8 /*!< HRPWM0_CSG0 SWS: SCSS Position */
\r
12778 #define HRPWM0_CSG0_SWS_SCSS_Msk (0x01UL << HRPWM0_CSG0_SWS_SCSS_Pos) /*!< HRPWM0_CSG0 SWS: SCSS Mask */
\r
12780 /* ------------------------------- HRPWM0_CSG0_SWC ------------------------------ */
\r
12781 #define HRPWM0_CSG0_SWC_CVLS1_Pos 0 /*!< HRPWM0_CSG0 SWC: CVLS1 Position */
\r
12782 #define HRPWM0_CSG0_SWC_CVLS1_Msk (0x01UL << HRPWM0_CSG0_SWC_CVLS1_Pos) /*!< HRPWM0_CSG0 SWC: CVLS1 Mask */
\r
12783 #define HRPWM0_CSG0_SWC_CVLS2_Pos 1 /*!< HRPWM0_CSG0 SWC: CVLS2 Position */
\r
12784 #define HRPWM0_CSG0_SWC_CVLS2_Msk (0x01UL << HRPWM0_CSG0_SWC_CVLS2_Pos) /*!< HRPWM0_CSG0 SWC: CVLS2 Mask */
\r
12785 #define HRPWM0_CSG0_SWC_CTRGS_Pos 2 /*!< HRPWM0_CSG0 SWC: CTRGS Position */
\r
12786 #define HRPWM0_CSG0_SWC_CTRGS_Msk (0x01UL << HRPWM0_CSG0_SWC_CTRGS_Pos) /*!< HRPWM0_CSG0 SWC: CTRGS Mask */
\r
12787 #define HRPWM0_CSG0_SWC_CSTRS_Pos 3 /*!< HRPWM0_CSG0 SWC: CSTRS Position */
\r
12788 #define HRPWM0_CSG0_SWC_CSTRS_Msk (0x01UL << HRPWM0_CSG0_SWC_CSTRS_Pos) /*!< HRPWM0_CSG0 SWC: CSTRS Mask */
\r
12789 #define HRPWM0_CSG0_SWC_CSTPS_Pos 4 /*!< HRPWM0_CSG0 SWC: CSTPS Position */
\r
12790 #define HRPWM0_CSG0_SWC_CSTPS_Msk (0x01UL << HRPWM0_CSG0_SWC_CSTPS_Pos) /*!< HRPWM0_CSG0 SWC: CSTPS Mask */
\r
12791 #define HRPWM0_CSG0_SWC_CSTD_Pos 5 /*!< HRPWM0_CSG0 SWC: CSTD Position */
\r
12792 #define HRPWM0_CSG0_SWC_CSTD_Msk (0x01UL << HRPWM0_CSG0_SWC_CSTD_Pos) /*!< HRPWM0_CSG0 SWC: CSTD Mask */
\r
12793 #define HRPWM0_CSG0_SWC_CCRS_Pos 6 /*!< HRPWM0_CSG0 SWC: CCRS Position */
\r
12794 #define HRPWM0_CSG0_SWC_CCRS_Msk (0x01UL << HRPWM0_CSG0_SWC_CCRS_Pos) /*!< HRPWM0_CSG0 SWC: CCRS Mask */
\r
12795 #define HRPWM0_CSG0_SWC_CCFS_Pos 7 /*!< HRPWM0_CSG0 SWC: CCFS Position */
\r
12796 #define HRPWM0_CSG0_SWC_CCFS_Msk (0x01UL << HRPWM0_CSG0_SWC_CCFS_Pos) /*!< HRPWM0_CSG0 SWC: CCFS Mask */
\r
12797 #define HRPWM0_CSG0_SWC_CCSS_Pos 8 /*!< HRPWM0_CSG0 SWC: CCSS Position */
\r
12798 #define HRPWM0_CSG0_SWC_CCSS_Msk (0x01UL << HRPWM0_CSG0_SWC_CCSS_Pos) /*!< HRPWM0_CSG0 SWC: CCSS Mask */
\r
12800 /* ------------------------------ HRPWM0_CSG0_ISTAT ----------------------------- */
\r
12801 #define HRPWM0_CSG0_ISTAT_VLS1S_Pos 0 /*!< HRPWM0_CSG0 ISTAT: VLS1S Position */
\r
12802 #define HRPWM0_CSG0_ISTAT_VLS1S_Msk (0x01UL << HRPWM0_CSG0_ISTAT_VLS1S_Pos) /*!< HRPWM0_CSG0 ISTAT: VLS1S Mask */
\r
12803 #define HRPWM0_CSG0_ISTAT_VLS2S_Pos 1 /*!< HRPWM0_CSG0 ISTAT: VLS2S Position */
\r
12804 #define HRPWM0_CSG0_ISTAT_VLS2S_Msk (0x01UL << HRPWM0_CSG0_ISTAT_VLS2S_Pos) /*!< HRPWM0_CSG0 ISTAT: VLS2S Mask */
\r
12805 #define HRPWM0_CSG0_ISTAT_TRGSS_Pos 2 /*!< HRPWM0_CSG0 ISTAT: TRGSS Position */
\r
12806 #define HRPWM0_CSG0_ISTAT_TRGSS_Msk (0x01UL << HRPWM0_CSG0_ISTAT_TRGSS_Pos) /*!< HRPWM0_CSG0 ISTAT: TRGSS Mask */
\r
12807 #define HRPWM0_CSG0_ISTAT_STRSS_Pos 3 /*!< HRPWM0_CSG0 ISTAT: STRSS Position */
\r
12808 #define HRPWM0_CSG0_ISTAT_STRSS_Msk (0x01UL << HRPWM0_CSG0_ISTAT_STRSS_Pos) /*!< HRPWM0_CSG0 ISTAT: STRSS Mask */
\r
12809 #define HRPWM0_CSG0_ISTAT_STPSS_Pos 4 /*!< HRPWM0_CSG0 ISTAT: STPSS Position */
\r
12810 #define HRPWM0_CSG0_ISTAT_STPSS_Msk (0x01UL << HRPWM0_CSG0_ISTAT_STPSS_Pos) /*!< HRPWM0_CSG0 ISTAT: STPSS Mask */
\r
12811 #define HRPWM0_CSG0_ISTAT_STDS_Pos 5 /*!< HRPWM0_CSG0 ISTAT: STDS Position */
\r
12812 #define HRPWM0_CSG0_ISTAT_STDS_Msk (0x01UL << HRPWM0_CSG0_ISTAT_STDS_Pos) /*!< HRPWM0_CSG0 ISTAT: STDS Mask */
\r
12813 #define HRPWM0_CSG0_ISTAT_CRSS_Pos 6 /*!< HRPWM0_CSG0 ISTAT: CRSS Position */
\r
12814 #define HRPWM0_CSG0_ISTAT_CRSS_Msk (0x01UL << HRPWM0_CSG0_ISTAT_CRSS_Pos) /*!< HRPWM0_CSG0 ISTAT: CRSS Mask */
\r
12815 #define HRPWM0_CSG0_ISTAT_CFSS_Pos 7 /*!< HRPWM0_CSG0 ISTAT: CFSS Position */
\r
12816 #define HRPWM0_CSG0_ISTAT_CFSS_Msk (0x01UL << HRPWM0_CSG0_ISTAT_CFSS_Pos) /*!< HRPWM0_CSG0 ISTAT: CFSS Mask */
\r
12817 #define HRPWM0_CSG0_ISTAT_CSES_Pos 8 /*!< HRPWM0_CSG0 ISTAT: CSES Position */
\r
12818 #define HRPWM0_CSG0_ISTAT_CSES_Msk (0x01UL << HRPWM0_CSG0_ISTAT_CSES_Pos) /*!< HRPWM0_CSG0 ISTAT: CSES Mask */
\r
12821 /* ================================================================================ */
\r
12822 /* ================ struct 'HRPWM0_CSG1' Position & Mask ================ */
\r
12823 /* ================================================================================ */
\r
12826 /* ------------------------------- HRPWM0_CSG1_DCI ------------------------------ */
\r
12827 #define HRPWM0_CSG1_DCI_SVIS_Pos 0 /*!< HRPWM0_CSG1 DCI: SVIS Position */
\r
12828 #define HRPWM0_CSG1_DCI_SVIS_Msk (0x0fUL << HRPWM0_CSG1_DCI_SVIS_Pos) /*!< HRPWM0_CSG1 DCI: SVIS Mask */
\r
12829 #define HRPWM0_CSG1_DCI_STRIS_Pos 4 /*!< HRPWM0_CSG1 DCI: STRIS Position */
\r
12830 #define HRPWM0_CSG1_DCI_STRIS_Msk (0x0fUL << HRPWM0_CSG1_DCI_STRIS_Pos) /*!< HRPWM0_CSG1 DCI: STRIS Mask */
\r
12831 #define HRPWM0_CSG1_DCI_STPIS_Pos 8 /*!< HRPWM0_CSG1 DCI: STPIS Position */
\r
12832 #define HRPWM0_CSG1_DCI_STPIS_Msk (0x0fUL << HRPWM0_CSG1_DCI_STPIS_Pos) /*!< HRPWM0_CSG1 DCI: STPIS Mask */
\r
12833 #define HRPWM0_CSG1_DCI_TRGIS_Pos 12 /*!< HRPWM0_CSG1 DCI: TRGIS Position */
\r
12834 #define HRPWM0_CSG1_DCI_TRGIS_Msk (0x0fUL << HRPWM0_CSG1_DCI_TRGIS_Pos) /*!< HRPWM0_CSG1 DCI: TRGIS Mask */
\r
12835 #define HRPWM0_CSG1_DCI_STIS_Pos 16 /*!< HRPWM0_CSG1 DCI: STIS Position */
\r
12836 #define HRPWM0_CSG1_DCI_STIS_Msk (0x0fUL << HRPWM0_CSG1_DCI_STIS_Pos) /*!< HRPWM0_CSG1 DCI: STIS Mask */
\r
12837 #define HRPWM0_CSG1_DCI_SCS_Pos 20 /*!< HRPWM0_CSG1 DCI: SCS Position */
\r
12838 #define HRPWM0_CSG1_DCI_SCS_Msk (0x03UL << HRPWM0_CSG1_DCI_SCS_Pos) /*!< HRPWM0_CSG1 DCI: SCS Mask */
\r
12840 /* ------------------------------- HRPWM0_CSG1_IES ------------------------------ */
\r
12841 #define HRPWM0_CSG1_IES_SVLS_Pos 0 /*!< HRPWM0_CSG1 IES: SVLS Position */
\r
12842 #define HRPWM0_CSG1_IES_SVLS_Msk (0x03UL << HRPWM0_CSG1_IES_SVLS_Pos) /*!< HRPWM0_CSG1 IES: SVLS Mask */
\r
12843 #define HRPWM0_CSG1_IES_STRES_Pos 2 /*!< HRPWM0_CSG1 IES: STRES Position */
\r
12844 #define HRPWM0_CSG1_IES_STRES_Msk (0x03UL << HRPWM0_CSG1_IES_STRES_Pos) /*!< HRPWM0_CSG1 IES: STRES Mask */
\r
12845 #define HRPWM0_CSG1_IES_STPES_Pos 4 /*!< HRPWM0_CSG1 IES: STPES Position */
\r
12846 #define HRPWM0_CSG1_IES_STPES_Msk (0x03UL << HRPWM0_CSG1_IES_STPES_Pos) /*!< HRPWM0_CSG1 IES: STPES Mask */
\r
12847 #define HRPWM0_CSG1_IES_TRGES_Pos 6 /*!< HRPWM0_CSG1 IES: TRGES Position */
\r
12848 #define HRPWM0_CSG1_IES_TRGES_Msk (0x03UL << HRPWM0_CSG1_IES_TRGES_Pos) /*!< HRPWM0_CSG1 IES: TRGES Mask */
\r
12849 #define HRPWM0_CSG1_IES_STES_Pos 8 /*!< HRPWM0_CSG1 IES: STES Position */
\r
12850 #define HRPWM0_CSG1_IES_STES_Msk (0x03UL << HRPWM0_CSG1_IES_STES_Pos) /*!< HRPWM0_CSG1 IES: STES Mask */
\r
12852 /* ------------------------------- HRPWM0_CSG1_SC ------------------------------- */
\r
12853 #define HRPWM0_CSG1_SC_PSRM_Pos 0 /*!< HRPWM0_CSG1 SC: PSRM Position */
\r
12854 #define HRPWM0_CSG1_SC_PSRM_Msk (0x03UL << HRPWM0_CSG1_SC_PSRM_Pos) /*!< HRPWM0_CSG1 SC: PSRM Mask */
\r
12855 #define HRPWM0_CSG1_SC_PSTM_Pos 2 /*!< HRPWM0_CSG1 SC: PSTM Position */
\r
12856 #define HRPWM0_CSG1_SC_PSTM_Msk (0x03UL << HRPWM0_CSG1_SC_PSTM_Pos) /*!< HRPWM0_CSG1 SC: PSTM Mask */
\r
12857 #define HRPWM0_CSG1_SC_FPD_Pos 4 /*!< HRPWM0_CSG1 SC: FPD Position */
\r
12858 #define HRPWM0_CSG1_SC_FPD_Msk (0x01UL << HRPWM0_CSG1_SC_FPD_Pos) /*!< HRPWM0_CSG1 SC: FPD Mask */
\r
12859 #define HRPWM0_CSG1_SC_PSV_Pos 5 /*!< HRPWM0_CSG1 SC: PSV Position */
\r
12860 #define HRPWM0_CSG1_SC_PSV_Msk (0x03UL << HRPWM0_CSG1_SC_PSV_Pos) /*!< HRPWM0_CSG1 SC: PSV Mask */
\r
12861 #define HRPWM0_CSG1_SC_SCM_Pos 8 /*!< HRPWM0_CSG1 SC: SCM Position */
\r
12862 #define HRPWM0_CSG1_SC_SCM_Msk (0x03UL << HRPWM0_CSG1_SC_SCM_Pos) /*!< HRPWM0_CSG1 SC: SCM Mask */
\r
12863 #define HRPWM0_CSG1_SC_SSRM_Pos 10 /*!< HRPWM0_CSG1 SC: SSRM Position */
\r
12864 #define HRPWM0_CSG1_SC_SSRM_Msk (0x03UL << HRPWM0_CSG1_SC_SSRM_Pos) /*!< HRPWM0_CSG1 SC: SSRM Mask */
\r
12865 #define HRPWM0_CSG1_SC_SSTM_Pos 12 /*!< HRPWM0_CSG1 SC: SSTM Position */
\r
12866 #define HRPWM0_CSG1_SC_SSTM_Msk (0x03UL << HRPWM0_CSG1_SC_SSTM_Pos) /*!< HRPWM0_CSG1 SC: SSTM Mask */
\r
12867 #define HRPWM0_CSG1_SC_SVSC_Pos 14 /*!< HRPWM0_CSG1 SC: SVSC Position */
\r
12868 #define HRPWM0_CSG1_SC_SVSC_Msk (0x03UL << HRPWM0_CSG1_SC_SVSC_Pos) /*!< HRPWM0_CSG1 SC: SVSC Mask */
\r
12869 #define HRPWM0_CSG1_SC_SWSM_Pos 16 /*!< HRPWM0_CSG1 SC: SWSM Position */
\r
12870 #define HRPWM0_CSG1_SC_SWSM_Msk (0x03UL << HRPWM0_CSG1_SC_SWSM_Pos) /*!< HRPWM0_CSG1 SC: SWSM Mask */
\r
12871 #define HRPWM0_CSG1_SC_GCFG_Pos 18 /*!< HRPWM0_CSG1 SC: GCFG Position */
\r
12872 #define HRPWM0_CSG1_SC_GCFG_Msk (0x03UL << HRPWM0_CSG1_SC_GCFG_Pos) /*!< HRPWM0_CSG1 SC: GCFG Mask */
\r
12873 #define HRPWM0_CSG1_SC_IST_Pos 20 /*!< HRPWM0_CSG1 SC: IST Position */
\r
12874 #define HRPWM0_CSG1_SC_IST_Msk (0x01UL << HRPWM0_CSG1_SC_IST_Pos) /*!< HRPWM0_CSG1 SC: IST Mask */
\r
12875 #define HRPWM0_CSG1_SC_PSE_Pos 21 /*!< HRPWM0_CSG1 SC: PSE Position */
\r
12876 #define HRPWM0_CSG1_SC_PSE_Msk (0x01UL << HRPWM0_CSG1_SC_PSE_Pos) /*!< HRPWM0_CSG1 SC: PSE Mask */
\r
12877 #define HRPWM0_CSG1_SC_PSWM_Pos 24 /*!< HRPWM0_CSG1 SC: PSWM Position */
\r
12878 #define HRPWM0_CSG1_SC_PSWM_Msk (0x03UL << HRPWM0_CSG1_SC_PSWM_Pos) /*!< HRPWM0_CSG1 SC: PSWM Mask */
\r
12880 /* ------------------------------- HRPWM0_CSG1_PC ------------------------------- */
\r
12881 #define HRPWM0_CSG1_PC_PSWV_Pos 0 /*!< HRPWM0_CSG1 PC: PSWV Position */
\r
12882 #define HRPWM0_CSG1_PC_PSWV_Msk (0x3fUL << HRPWM0_CSG1_PC_PSWV_Pos) /*!< HRPWM0_CSG1 PC: PSWV Mask */
\r
12884 /* ------------------------------ HRPWM0_CSG1_DSV1 ------------------------------ */
\r
12885 #define HRPWM0_CSG1_DSV1_DSV1_Pos 0 /*!< HRPWM0_CSG1 DSV1: DSV1 Position */
\r
12886 #define HRPWM0_CSG1_DSV1_DSV1_Msk (0x000003ffUL << HRPWM0_CSG1_DSV1_DSV1_Pos) /*!< HRPWM0_CSG1 DSV1: DSV1 Mask */
\r
12888 /* ------------------------------ HRPWM0_CSG1_DSV2 ------------------------------ */
\r
12889 #define HRPWM0_CSG1_DSV2_DSV2_Pos 0 /*!< HRPWM0_CSG1 DSV2: DSV2 Position */
\r
12890 #define HRPWM0_CSG1_DSV2_DSV2_Msk (0x000003ffUL << HRPWM0_CSG1_DSV2_DSV2_Pos) /*!< HRPWM0_CSG1 DSV2: DSV2 Mask */
\r
12892 /* ------------------------------ HRPWM0_CSG1_SDSV1 ----------------------------- */
\r
12893 #define HRPWM0_CSG1_SDSV1_SDSV1_Pos 0 /*!< HRPWM0_CSG1 SDSV1: SDSV1 Position */
\r
12894 #define HRPWM0_CSG1_SDSV1_SDSV1_Msk (0x000003ffUL << HRPWM0_CSG1_SDSV1_SDSV1_Pos) /*!< HRPWM0_CSG1 SDSV1: SDSV1 Mask */
\r
12896 /* ------------------------------- HRPWM0_CSG1_SPC ------------------------------ */
\r
12897 #define HRPWM0_CSG1_SPC_SPSWV_Pos 0 /*!< HRPWM0_CSG1 SPC: SPSWV Position */
\r
12898 #define HRPWM0_CSG1_SPC_SPSWV_Msk (0x3fUL << HRPWM0_CSG1_SPC_SPSWV_Pos) /*!< HRPWM0_CSG1 SPC: SPSWV Mask */
\r
12900 /* ------------------------------- HRPWM0_CSG1_CC ------------------------------- */
\r
12901 #define HRPWM0_CSG1_CC_IBS_Pos 0 /*!< HRPWM0_CSG1 CC: IBS Position */
\r
12902 #define HRPWM0_CSG1_CC_IBS_Msk (0x0fUL << HRPWM0_CSG1_CC_IBS_Pos) /*!< HRPWM0_CSG1 CC: IBS Mask */
\r
12903 #define HRPWM0_CSG1_CC_IMCS_Pos 8 /*!< HRPWM0_CSG1 CC: IMCS Position */
\r
12904 #define HRPWM0_CSG1_CC_IMCS_Msk (0x01UL << HRPWM0_CSG1_CC_IMCS_Pos) /*!< HRPWM0_CSG1 CC: IMCS Mask */
\r
12905 #define HRPWM0_CSG1_CC_IMCC_Pos 9 /*!< HRPWM0_CSG1 CC: IMCC Position */
\r
12906 #define HRPWM0_CSG1_CC_IMCC_Msk (0x03UL << HRPWM0_CSG1_CC_IMCC_Pos) /*!< HRPWM0_CSG1 CC: IMCC Mask */
\r
12907 #define HRPWM0_CSG1_CC_ESE_Pos 11 /*!< HRPWM0_CSG1 CC: ESE Position */
\r
12908 #define HRPWM0_CSG1_CC_ESE_Msk (0x01UL << HRPWM0_CSG1_CC_ESE_Pos) /*!< HRPWM0_CSG1 CC: ESE Mask */
\r
12909 #define HRPWM0_CSG1_CC_OIE_Pos 12 /*!< HRPWM0_CSG1 CC: OIE Position */
\r
12910 #define HRPWM0_CSG1_CC_OIE_Msk (0x01UL << HRPWM0_CSG1_CC_OIE_Pos) /*!< HRPWM0_CSG1 CC: OIE Mask */
\r
12911 #define HRPWM0_CSG1_CC_OSE_Pos 13 /*!< HRPWM0_CSG1 CC: OSE Position */
\r
12912 #define HRPWM0_CSG1_CC_OSE_Msk (0x01UL << HRPWM0_CSG1_CC_OSE_Pos) /*!< HRPWM0_CSG1 CC: OSE Mask */
\r
12913 #define HRPWM0_CSG1_CC_BLMC_Pos 14 /*!< HRPWM0_CSG1 CC: BLMC Position */
\r
12914 #define HRPWM0_CSG1_CC_BLMC_Msk (0x03UL << HRPWM0_CSG1_CC_BLMC_Pos) /*!< HRPWM0_CSG1 CC: BLMC Mask */
\r
12915 #define HRPWM0_CSG1_CC_EBE_Pos 16 /*!< HRPWM0_CSG1 CC: EBE Position */
\r
12916 #define HRPWM0_CSG1_CC_EBE_Msk (0x01UL << HRPWM0_CSG1_CC_EBE_Pos) /*!< HRPWM0_CSG1 CC: EBE Mask */
\r
12917 #define HRPWM0_CSG1_CC_COFE_Pos 17 /*!< HRPWM0_CSG1 CC: COFE Position */
\r
12918 #define HRPWM0_CSG1_CC_COFE_Msk (0x01UL << HRPWM0_CSG1_CC_COFE_Pos) /*!< HRPWM0_CSG1 CC: COFE Mask */
\r
12919 #define HRPWM0_CSG1_CC_COFM_Pos 18 /*!< HRPWM0_CSG1 CC: COFM Position */
\r
12920 #define HRPWM0_CSG1_CC_COFM_Msk (0x0fUL << HRPWM0_CSG1_CC_COFM_Pos) /*!< HRPWM0_CSG1 CC: COFM Mask */
\r
12921 #define HRPWM0_CSG1_CC_COFC_Pos 24 /*!< HRPWM0_CSG1 CC: COFC Position */
\r
12922 #define HRPWM0_CSG1_CC_COFC_Msk (0x03UL << HRPWM0_CSG1_CC_COFC_Pos) /*!< HRPWM0_CSG1 CC: COFC Mask */
\r
12924 /* ------------------------------- HRPWM0_CSG1_PLC ------------------------------ */
\r
12925 #define HRPWM0_CSG1_PLC_IPLS_Pos 0 /*!< HRPWM0_CSG1 PLC: IPLS Position */
\r
12926 #define HRPWM0_CSG1_PLC_IPLS_Msk (0x0fUL << HRPWM0_CSG1_PLC_IPLS_Pos) /*!< HRPWM0_CSG1 PLC: IPLS Mask */
\r
12927 #define HRPWM0_CSG1_PLC_PLCL_Pos 8 /*!< HRPWM0_CSG1 PLC: PLCL Position */
\r
12928 #define HRPWM0_CSG1_PLC_PLCL_Msk (0x03UL << HRPWM0_CSG1_PLC_PLCL_Pos) /*!< HRPWM0_CSG1 PLC: PLCL Mask */
\r
12929 #define HRPWM0_CSG1_PLC_PSL_Pos 10 /*!< HRPWM0_CSG1 PLC: PSL Position */
\r
12930 #define HRPWM0_CSG1_PLC_PSL_Msk (0x01UL << HRPWM0_CSG1_PLC_PSL_Pos) /*!< HRPWM0_CSG1 PLC: PSL Mask */
\r
12931 #define HRPWM0_CSG1_PLC_PLSW_Pos 11 /*!< HRPWM0_CSG1 PLC: PLSW Position */
\r
12932 #define HRPWM0_CSG1_PLC_PLSW_Msk (0x01UL << HRPWM0_CSG1_PLC_PLSW_Pos) /*!< HRPWM0_CSG1 PLC: PLSW Mask */
\r
12933 #define HRPWM0_CSG1_PLC_PLEC_Pos 12 /*!< HRPWM0_CSG1 PLC: PLEC Position */
\r
12934 #define HRPWM0_CSG1_PLC_PLEC_Msk (0x03UL << HRPWM0_CSG1_PLC_PLEC_Pos) /*!< HRPWM0_CSG1 PLC: PLEC Mask */
\r
12935 #define HRPWM0_CSG1_PLC_PLXC_Pos 14 /*!< HRPWM0_CSG1 PLC: PLXC Position */
\r
12936 #define HRPWM0_CSG1_PLC_PLXC_Msk (0x03UL << HRPWM0_CSG1_PLC_PLXC_Pos) /*!< HRPWM0_CSG1 PLC: PLXC Mask */
\r
12938 /* ------------------------------- HRPWM0_CSG1_BLV ------------------------------ */
\r
12939 #define HRPWM0_CSG1_BLV_BLV_Pos 0 /*!< HRPWM0_CSG1 BLV: BLV Position */
\r
12940 #define HRPWM0_CSG1_BLV_BLV_Msk (0x000000ffUL << HRPWM0_CSG1_BLV_BLV_Pos) /*!< HRPWM0_CSG1 BLV: BLV Mask */
\r
12942 /* ------------------------------- HRPWM0_CSG1_SRE ------------------------------ */
\r
12943 #define HRPWM0_CSG1_SRE_VLS1E_Pos 0 /*!< HRPWM0_CSG1 SRE: VLS1E Position */
\r
12944 #define HRPWM0_CSG1_SRE_VLS1E_Msk (0x01UL << HRPWM0_CSG1_SRE_VLS1E_Pos) /*!< HRPWM0_CSG1 SRE: VLS1E Mask */
\r
12945 #define HRPWM0_CSG1_SRE_VLS2E_Pos 1 /*!< HRPWM0_CSG1 SRE: VLS2E Position */
\r
12946 #define HRPWM0_CSG1_SRE_VLS2E_Msk (0x01UL << HRPWM0_CSG1_SRE_VLS2E_Pos) /*!< HRPWM0_CSG1 SRE: VLS2E Mask */
\r
12947 #define HRPWM0_CSG1_SRE_TRGSE_Pos 2 /*!< HRPWM0_CSG1 SRE: TRGSE Position */
\r
12948 #define HRPWM0_CSG1_SRE_TRGSE_Msk (0x01UL << HRPWM0_CSG1_SRE_TRGSE_Pos) /*!< HRPWM0_CSG1 SRE: TRGSE Mask */
\r
12949 #define HRPWM0_CSG1_SRE_STRSE_Pos 3 /*!< HRPWM0_CSG1 SRE: STRSE Position */
\r
12950 #define HRPWM0_CSG1_SRE_STRSE_Msk (0x01UL << HRPWM0_CSG1_SRE_STRSE_Pos) /*!< HRPWM0_CSG1 SRE: STRSE Mask */
\r
12951 #define HRPWM0_CSG1_SRE_STPSE_Pos 4 /*!< HRPWM0_CSG1 SRE: STPSE Position */
\r
12952 #define HRPWM0_CSG1_SRE_STPSE_Msk (0x01UL << HRPWM0_CSG1_SRE_STPSE_Pos) /*!< HRPWM0_CSG1 SRE: STPSE Mask */
\r
12953 #define HRPWM0_CSG1_SRE_STDE_Pos 5 /*!< HRPWM0_CSG1 SRE: STDE Position */
\r
12954 #define HRPWM0_CSG1_SRE_STDE_Msk (0x01UL << HRPWM0_CSG1_SRE_STDE_Pos) /*!< HRPWM0_CSG1 SRE: STDE Mask */
\r
12955 #define HRPWM0_CSG1_SRE_CRSE_Pos 6 /*!< HRPWM0_CSG1 SRE: CRSE Position */
\r
12956 #define HRPWM0_CSG1_SRE_CRSE_Msk (0x01UL << HRPWM0_CSG1_SRE_CRSE_Pos) /*!< HRPWM0_CSG1 SRE: CRSE Mask */
\r
12957 #define HRPWM0_CSG1_SRE_CFSE_Pos 7 /*!< HRPWM0_CSG1 SRE: CFSE Position */
\r
12958 #define HRPWM0_CSG1_SRE_CFSE_Msk (0x01UL << HRPWM0_CSG1_SRE_CFSE_Pos) /*!< HRPWM0_CSG1 SRE: CFSE Mask */
\r
12959 #define HRPWM0_CSG1_SRE_CSEE_Pos 8 /*!< HRPWM0_CSG1 SRE: CSEE Position */
\r
12960 #define HRPWM0_CSG1_SRE_CSEE_Msk (0x01UL << HRPWM0_CSG1_SRE_CSEE_Pos) /*!< HRPWM0_CSG1 SRE: CSEE Mask */
\r
12962 /* ------------------------------- HRPWM0_CSG1_SRS ------------------------------ */
\r
12963 #define HRPWM0_CSG1_SRS_VLS1S_Pos 0 /*!< HRPWM0_CSG1 SRS: VLS1S Position */
\r
12964 #define HRPWM0_CSG1_SRS_VLS1S_Msk (0x03UL << HRPWM0_CSG1_SRS_VLS1S_Pos) /*!< HRPWM0_CSG1 SRS: VLS1S Mask */
\r
12965 #define HRPWM0_CSG1_SRS_VLS2S_Pos 2 /*!< HRPWM0_CSG1 SRS: VLS2S Position */
\r
12966 #define HRPWM0_CSG1_SRS_VLS2S_Msk (0x03UL << HRPWM0_CSG1_SRS_VLS2S_Pos) /*!< HRPWM0_CSG1 SRS: VLS2S Mask */
\r
12967 #define HRPWM0_CSG1_SRS_TRLS_Pos 4 /*!< HRPWM0_CSG1 SRS: TRLS Position */
\r
12968 #define HRPWM0_CSG1_SRS_TRLS_Msk (0x03UL << HRPWM0_CSG1_SRS_TRLS_Pos) /*!< HRPWM0_CSG1 SRS: TRLS Mask */
\r
12969 #define HRPWM0_CSG1_SRS_SSLS_Pos 6 /*!< HRPWM0_CSG1 SRS: SSLS Position */
\r
12970 #define HRPWM0_CSG1_SRS_SSLS_Msk (0x03UL << HRPWM0_CSG1_SRS_SSLS_Pos) /*!< HRPWM0_CSG1 SRS: SSLS Mask */
\r
12971 #define HRPWM0_CSG1_SRS_STLS_Pos 8 /*!< HRPWM0_CSG1 SRS: STLS Position */
\r
12972 #define HRPWM0_CSG1_SRS_STLS_Msk (0x03UL << HRPWM0_CSG1_SRS_STLS_Pos) /*!< HRPWM0_CSG1 SRS: STLS Mask */
\r
12973 #define HRPWM0_CSG1_SRS_CRFLS_Pos 10 /*!< HRPWM0_CSG1 SRS: CRFLS Position */
\r
12974 #define HRPWM0_CSG1_SRS_CRFLS_Msk (0x03UL << HRPWM0_CSG1_SRS_CRFLS_Pos) /*!< HRPWM0_CSG1 SRS: CRFLS Mask */
\r
12975 #define HRPWM0_CSG1_SRS_CSLS_Pos 12 /*!< HRPWM0_CSG1 SRS: CSLS Position */
\r
12976 #define HRPWM0_CSG1_SRS_CSLS_Msk (0x03UL << HRPWM0_CSG1_SRS_CSLS_Pos) /*!< HRPWM0_CSG1 SRS: CSLS Mask */
\r
12978 /* ------------------------------- HRPWM0_CSG1_SWS ------------------------------ */
\r
12979 #define HRPWM0_CSG1_SWS_SVLS1_Pos 0 /*!< HRPWM0_CSG1 SWS: SVLS1 Position */
\r
12980 #define HRPWM0_CSG1_SWS_SVLS1_Msk (0x01UL << HRPWM0_CSG1_SWS_SVLS1_Pos) /*!< HRPWM0_CSG1 SWS: SVLS1 Mask */
\r
12981 #define HRPWM0_CSG1_SWS_SVLS2_Pos 1 /*!< HRPWM0_CSG1 SWS: SVLS2 Position */
\r
12982 #define HRPWM0_CSG1_SWS_SVLS2_Msk (0x01UL << HRPWM0_CSG1_SWS_SVLS2_Pos) /*!< HRPWM0_CSG1 SWS: SVLS2 Mask */
\r
12983 #define HRPWM0_CSG1_SWS_STRGS_Pos 2 /*!< HRPWM0_CSG1 SWS: STRGS Position */
\r
12984 #define HRPWM0_CSG1_SWS_STRGS_Msk (0x01UL << HRPWM0_CSG1_SWS_STRGS_Pos) /*!< HRPWM0_CSG1 SWS: STRGS Mask */
\r
12985 #define HRPWM0_CSG1_SWS_SSTRS_Pos 3 /*!< HRPWM0_CSG1 SWS: SSTRS Position */
\r
12986 #define HRPWM0_CSG1_SWS_SSTRS_Msk (0x01UL << HRPWM0_CSG1_SWS_SSTRS_Pos) /*!< HRPWM0_CSG1 SWS: SSTRS Mask */
\r
12987 #define HRPWM0_CSG1_SWS_SSTPS_Pos 4 /*!< HRPWM0_CSG1 SWS: SSTPS Position */
\r
12988 #define HRPWM0_CSG1_SWS_SSTPS_Msk (0x01UL << HRPWM0_CSG1_SWS_SSTPS_Pos) /*!< HRPWM0_CSG1 SWS: SSTPS Mask */
\r
12989 #define HRPWM0_CSG1_SWS_SSTD_Pos 5 /*!< HRPWM0_CSG1 SWS: SSTD Position */
\r
12990 #define HRPWM0_CSG1_SWS_SSTD_Msk (0x01UL << HRPWM0_CSG1_SWS_SSTD_Pos) /*!< HRPWM0_CSG1 SWS: SSTD Mask */
\r
12991 #define HRPWM0_CSG1_SWS_SCRS_Pos 6 /*!< HRPWM0_CSG1 SWS: SCRS Position */
\r
12992 #define HRPWM0_CSG1_SWS_SCRS_Msk (0x01UL << HRPWM0_CSG1_SWS_SCRS_Pos) /*!< HRPWM0_CSG1 SWS: SCRS Mask */
\r
12993 #define HRPWM0_CSG1_SWS_SCFS_Pos 7 /*!< HRPWM0_CSG1 SWS: SCFS Position */
\r
12994 #define HRPWM0_CSG1_SWS_SCFS_Msk (0x01UL << HRPWM0_CSG1_SWS_SCFS_Pos) /*!< HRPWM0_CSG1 SWS: SCFS Mask */
\r
12995 #define HRPWM0_CSG1_SWS_SCSS_Pos 8 /*!< HRPWM0_CSG1 SWS: SCSS Position */
\r
12996 #define HRPWM0_CSG1_SWS_SCSS_Msk (0x01UL << HRPWM0_CSG1_SWS_SCSS_Pos) /*!< HRPWM0_CSG1 SWS: SCSS Mask */
\r
12998 /* ------------------------------- HRPWM0_CSG1_SWC ------------------------------ */
\r
12999 #define HRPWM0_CSG1_SWC_CVLS1_Pos 0 /*!< HRPWM0_CSG1 SWC: CVLS1 Position */
\r
13000 #define HRPWM0_CSG1_SWC_CVLS1_Msk (0x01UL << HRPWM0_CSG1_SWC_CVLS1_Pos) /*!< HRPWM0_CSG1 SWC: CVLS1 Mask */
\r
13001 #define HRPWM0_CSG1_SWC_CVLS2_Pos 1 /*!< HRPWM0_CSG1 SWC: CVLS2 Position */
\r
13002 #define HRPWM0_CSG1_SWC_CVLS2_Msk (0x01UL << HRPWM0_CSG1_SWC_CVLS2_Pos) /*!< HRPWM0_CSG1 SWC: CVLS2 Mask */
\r
13003 #define HRPWM0_CSG1_SWC_CTRGS_Pos 2 /*!< HRPWM0_CSG1 SWC: CTRGS Position */
\r
13004 #define HRPWM0_CSG1_SWC_CTRGS_Msk (0x01UL << HRPWM0_CSG1_SWC_CTRGS_Pos) /*!< HRPWM0_CSG1 SWC: CTRGS Mask */
\r
13005 #define HRPWM0_CSG1_SWC_CSTRS_Pos 3 /*!< HRPWM0_CSG1 SWC: CSTRS Position */
\r
13006 #define HRPWM0_CSG1_SWC_CSTRS_Msk (0x01UL << HRPWM0_CSG1_SWC_CSTRS_Pos) /*!< HRPWM0_CSG1 SWC: CSTRS Mask */
\r
13007 #define HRPWM0_CSG1_SWC_CSTPS_Pos 4 /*!< HRPWM0_CSG1 SWC: CSTPS Position */
\r
13008 #define HRPWM0_CSG1_SWC_CSTPS_Msk (0x01UL << HRPWM0_CSG1_SWC_CSTPS_Pos) /*!< HRPWM0_CSG1 SWC: CSTPS Mask */
\r
13009 #define HRPWM0_CSG1_SWC_CSTD_Pos 5 /*!< HRPWM0_CSG1 SWC: CSTD Position */
\r
13010 #define HRPWM0_CSG1_SWC_CSTD_Msk (0x01UL << HRPWM0_CSG1_SWC_CSTD_Pos) /*!< HRPWM0_CSG1 SWC: CSTD Mask */
\r
13011 #define HRPWM0_CSG1_SWC_CCRS_Pos 6 /*!< HRPWM0_CSG1 SWC: CCRS Position */
\r
13012 #define HRPWM0_CSG1_SWC_CCRS_Msk (0x01UL << HRPWM0_CSG1_SWC_CCRS_Pos) /*!< HRPWM0_CSG1 SWC: CCRS Mask */
\r
13013 #define HRPWM0_CSG1_SWC_CCFS_Pos 7 /*!< HRPWM0_CSG1 SWC: CCFS Position */
\r
13014 #define HRPWM0_CSG1_SWC_CCFS_Msk (0x01UL << HRPWM0_CSG1_SWC_CCFS_Pos) /*!< HRPWM0_CSG1 SWC: CCFS Mask */
\r
13015 #define HRPWM0_CSG1_SWC_CCSS_Pos 8 /*!< HRPWM0_CSG1 SWC: CCSS Position */
\r
13016 #define HRPWM0_CSG1_SWC_CCSS_Msk (0x01UL << HRPWM0_CSG1_SWC_CCSS_Pos) /*!< HRPWM0_CSG1 SWC: CCSS Mask */
\r
13018 /* ------------------------------ HRPWM0_CSG1_ISTAT ----------------------------- */
\r
13019 #define HRPWM0_CSG1_ISTAT_VLS1S_Pos 0 /*!< HRPWM0_CSG1 ISTAT: VLS1S Position */
\r
13020 #define HRPWM0_CSG1_ISTAT_VLS1S_Msk (0x01UL << HRPWM0_CSG1_ISTAT_VLS1S_Pos) /*!< HRPWM0_CSG1 ISTAT: VLS1S Mask */
\r
13021 #define HRPWM0_CSG1_ISTAT_VLS2S_Pos 1 /*!< HRPWM0_CSG1 ISTAT: VLS2S Position */
\r
13022 #define HRPWM0_CSG1_ISTAT_VLS2S_Msk (0x01UL << HRPWM0_CSG1_ISTAT_VLS2S_Pos) /*!< HRPWM0_CSG1 ISTAT: VLS2S Mask */
\r
13023 #define HRPWM0_CSG1_ISTAT_TRGSS_Pos 2 /*!< HRPWM0_CSG1 ISTAT: TRGSS Position */
\r
13024 #define HRPWM0_CSG1_ISTAT_TRGSS_Msk (0x01UL << HRPWM0_CSG1_ISTAT_TRGSS_Pos) /*!< HRPWM0_CSG1 ISTAT: TRGSS Mask */
\r
13025 #define HRPWM0_CSG1_ISTAT_STRSS_Pos 3 /*!< HRPWM0_CSG1 ISTAT: STRSS Position */
\r
13026 #define HRPWM0_CSG1_ISTAT_STRSS_Msk (0x01UL << HRPWM0_CSG1_ISTAT_STRSS_Pos) /*!< HRPWM0_CSG1 ISTAT: STRSS Mask */
\r
13027 #define HRPWM0_CSG1_ISTAT_STPSS_Pos 4 /*!< HRPWM0_CSG1 ISTAT: STPSS Position */
\r
13028 #define HRPWM0_CSG1_ISTAT_STPSS_Msk (0x01UL << HRPWM0_CSG1_ISTAT_STPSS_Pos) /*!< HRPWM0_CSG1 ISTAT: STPSS Mask */
\r
13029 #define HRPWM0_CSG1_ISTAT_STDS_Pos 5 /*!< HRPWM0_CSG1 ISTAT: STDS Position */
\r
13030 #define HRPWM0_CSG1_ISTAT_STDS_Msk (0x01UL << HRPWM0_CSG1_ISTAT_STDS_Pos) /*!< HRPWM0_CSG1 ISTAT: STDS Mask */
\r
13031 #define HRPWM0_CSG1_ISTAT_CRSS_Pos 6 /*!< HRPWM0_CSG1 ISTAT: CRSS Position */
\r
13032 #define HRPWM0_CSG1_ISTAT_CRSS_Msk (0x01UL << HRPWM0_CSG1_ISTAT_CRSS_Pos) /*!< HRPWM0_CSG1 ISTAT: CRSS Mask */
\r
13033 #define HRPWM0_CSG1_ISTAT_CFSS_Pos 7 /*!< HRPWM0_CSG1 ISTAT: CFSS Position */
\r
13034 #define HRPWM0_CSG1_ISTAT_CFSS_Msk (0x01UL << HRPWM0_CSG1_ISTAT_CFSS_Pos) /*!< HRPWM0_CSG1 ISTAT: CFSS Mask */
\r
13035 #define HRPWM0_CSG1_ISTAT_CSES_Pos 8 /*!< HRPWM0_CSG1 ISTAT: CSES Position */
\r
13036 #define HRPWM0_CSG1_ISTAT_CSES_Msk (0x01UL << HRPWM0_CSG1_ISTAT_CSES_Pos) /*!< HRPWM0_CSG1 ISTAT: CSES Mask */
\r
13039 /* ================================================================================ */
\r
13040 /* ================ struct 'HRPWM0_CSG2' Position & Mask ================ */
\r
13041 /* ================================================================================ */
\r
13044 /* ------------------------------- HRPWM0_CSG2_DCI ------------------------------ */
\r
13045 #define HRPWM0_CSG2_DCI_SVIS_Pos 0 /*!< HRPWM0_CSG2 DCI: SVIS Position */
\r
13046 #define HRPWM0_CSG2_DCI_SVIS_Msk (0x0fUL << HRPWM0_CSG2_DCI_SVIS_Pos) /*!< HRPWM0_CSG2 DCI: SVIS Mask */
\r
13047 #define HRPWM0_CSG2_DCI_STRIS_Pos 4 /*!< HRPWM0_CSG2 DCI: STRIS Position */
\r
13048 #define HRPWM0_CSG2_DCI_STRIS_Msk (0x0fUL << HRPWM0_CSG2_DCI_STRIS_Pos) /*!< HRPWM0_CSG2 DCI: STRIS Mask */
\r
13049 #define HRPWM0_CSG2_DCI_STPIS_Pos 8 /*!< HRPWM0_CSG2 DCI: STPIS Position */
\r
13050 #define HRPWM0_CSG2_DCI_STPIS_Msk (0x0fUL << HRPWM0_CSG2_DCI_STPIS_Pos) /*!< HRPWM0_CSG2 DCI: STPIS Mask */
\r
13051 #define HRPWM0_CSG2_DCI_TRGIS_Pos 12 /*!< HRPWM0_CSG2 DCI: TRGIS Position */
\r
13052 #define HRPWM0_CSG2_DCI_TRGIS_Msk (0x0fUL << HRPWM0_CSG2_DCI_TRGIS_Pos) /*!< HRPWM0_CSG2 DCI: TRGIS Mask */
\r
13053 #define HRPWM0_CSG2_DCI_STIS_Pos 16 /*!< HRPWM0_CSG2 DCI: STIS Position */
\r
13054 #define HRPWM0_CSG2_DCI_STIS_Msk (0x0fUL << HRPWM0_CSG2_DCI_STIS_Pos) /*!< HRPWM0_CSG2 DCI: STIS Mask */
\r
13055 #define HRPWM0_CSG2_DCI_SCS_Pos 20 /*!< HRPWM0_CSG2 DCI: SCS Position */
\r
13056 #define HRPWM0_CSG2_DCI_SCS_Msk (0x03UL << HRPWM0_CSG2_DCI_SCS_Pos) /*!< HRPWM0_CSG2 DCI: SCS Mask */
\r
13058 /* ------------------------------- HRPWM0_CSG2_IES ------------------------------ */
\r
13059 #define HRPWM0_CSG2_IES_SVLS_Pos 0 /*!< HRPWM0_CSG2 IES: SVLS Position */
\r
13060 #define HRPWM0_CSG2_IES_SVLS_Msk (0x03UL << HRPWM0_CSG2_IES_SVLS_Pos) /*!< HRPWM0_CSG2 IES: SVLS Mask */
\r
13061 #define HRPWM0_CSG2_IES_STRES_Pos 2 /*!< HRPWM0_CSG2 IES: STRES Position */
\r
13062 #define HRPWM0_CSG2_IES_STRES_Msk (0x03UL << HRPWM0_CSG2_IES_STRES_Pos) /*!< HRPWM0_CSG2 IES: STRES Mask */
\r
13063 #define HRPWM0_CSG2_IES_STPES_Pos 4 /*!< HRPWM0_CSG2 IES: STPES Position */
\r
13064 #define HRPWM0_CSG2_IES_STPES_Msk (0x03UL << HRPWM0_CSG2_IES_STPES_Pos) /*!< HRPWM0_CSG2 IES: STPES Mask */
\r
13065 #define HRPWM0_CSG2_IES_TRGES_Pos 6 /*!< HRPWM0_CSG2 IES: TRGES Position */
\r
13066 #define HRPWM0_CSG2_IES_TRGES_Msk (0x03UL << HRPWM0_CSG2_IES_TRGES_Pos) /*!< HRPWM0_CSG2 IES: TRGES Mask */
\r
13067 #define HRPWM0_CSG2_IES_STES_Pos 8 /*!< HRPWM0_CSG2 IES: STES Position */
\r
13068 #define HRPWM0_CSG2_IES_STES_Msk (0x03UL << HRPWM0_CSG2_IES_STES_Pos) /*!< HRPWM0_CSG2 IES: STES Mask */
\r
13070 /* ------------------------------- HRPWM0_CSG2_SC ------------------------------- */
\r
13071 #define HRPWM0_CSG2_SC_PSRM_Pos 0 /*!< HRPWM0_CSG2 SC: PSRM Position */
\r
13072 #define HRPWM0_CSG2_SC_PSRM_Msk (0x03UL << HRPWM0_CSG2_SC_PSRM_Pos) /*!< HRPWM0_CSG2 SC: PSRM Mask */
\r
13073 #define HRPWM0_CSG2_SC_PSTM_Pos 2 /*!< HRPWM0_CSG2 SC: PSTM Position */
\r
13074 #define HRPWM0_CSG2_SC_PSTM_Msk (0x03UL << HRPWM0_CSG2_SC_PSTM_Pos) /*!< HRPWM0_CSG2 SC: PSTM Mask */
\r
13075 #define HRPWM0_CSG2_SC_FPD_Pos 4 /*!< HRPWM0_CSG2 SC: FPD Position */
\r
13076 #define HRPWM0_CSG2_SC_FPD_Msk (0x01UL << HRPWM0_CSG2_SC_FPD_Pos) /*!< HRPWM0_CSG2 SC: FPD Mask */
\r
13077 #define HRPWM0_CSG2_SC_PSV_Pos 5 /*!< HRPWM0_CSG2 SC: PSV Position */
\r
13078 #define HRPWM0_CSG2_SC_PSV_Msk (0x03UL << HRPWM0_CSG2_SC_PSV_Pos) /*!< HRPWM0_CSG2 SC: PSV Mask */
\r
13079 #define HRPWM0_CSG2_SC_SCM_Pos 8 /*!< HRPWM0_CSG2 SC: SCM Position */
\r
13080 #define HRPWM0_CSG2_SC_SCM_Msk (0x03UL << HRPWM0_CSG2_SC_SCM_Pos) /*!< HRPWM0_CSG2 SC: SCM Mask */
\r
13081 #define HRPWM0_CSG2_SC_SSRM_Pos 10 /*!< HRPWM0_CSG2 SC: SSRM Position */
\r
13082 #define HRPWM0_CSG2_SC_SSRM_Msk (0x03UL << HRPWM0_CSG2_SC_SSRM_Pos) /*!< HRPWM0_CSG2 SC: SSRM Mask */
\r
13083 #define HRPWM0_CSG2_SC_SSTM_Pos 12 /*!< HRPWM0_CSG2 SC: SSTM Position */
\r
13084 #define HRPWM0_CSG2_SC_SSTM_Msk (0x03UL << HRPWM0_CSG2_SC_SSTM_Pos) /*!< HRPWM0_CSG2 SC: SSTM Mask */
\r
13085 #define HRPWM0_CSG2_SC_SVSC_Pos 14 /*!< HRPWM0_CSG2 SC: SVSC Position */
\r
13086 #define HRPWM0_CSG2_SC_SVSC_Msk (0x03UL << HRPWM0_CSG2_SC_SVSC_Pos) /*!< HRPWM0_CSG2 SC: SVSC Mask */
\r
13087 #define HRPWM0_CSG2_SC_SWSM_Pos 16 /*!< HRPWM0_CSG2 SC: SWSM Position */
\r
13088 #define HRPWM0_CSG2_SC_SWSM_Msk (0x03UL << HRPWM0_CSG2_SC_SWSM_Pos) /*!< HRPWM0_CSG2 SC: SWSM Mask */
\r
13089 #define HRPWM0_CSG2_SC_GCFG_Pos 18 /*!< HRPWM0_CSG2 SC: GCFG Position */
\r
13090 #define HRPWM0_CSG2_SC_GCFG_Msk (0x03UL << HRPWM0_CSG2_SC_GCFG_Pos) /*!< HRPWM0_CSG2 SC: GCFG Mask */
\r
13091 #define HRPWM0_CSG2_SC_IST_Pos 20 /*!< HRPWM0_CSG2 SC: IST Position */
\r
13092 #define HRPWM0_CSG2_SC_IST_Msk (0x01UL << HRPWM0_CSG2_SC_IST_Pos) /*!< HRPWM0_CSG2 SC: IST Mask */
\r
13093 #define HRPWM0_CSG2_SC_PSE_Pos 21 /*!< HRPWM0_CSG2 SC: PSE Position */
\r
13094 #define HRPWM0_CSG2_SC_PSE_Msk (0x01UL << HRPWM0_CSG2_SC_PSE_Pos) /*!< HRPWM0_CSG2 SC: PSE Mask */
\r
13095 #define HRPWM0_CSG2_SC_PSWM_Pos 24 /*!< HRPWM0_CSG2 SC: PSWM Position */
\r
13096 #define HRPWM0_CSG2_SC_PSWM_Msk (0x03UL << HRPWM0_CSG2_SC_PSWM_Pos) /*!< HRPWM0_CSG2 SC: PSWM Mask */
\r
13098 /* ------------------------------- HRPWM0_CSG2_PC ------------------------------- */
\r
13099 #define HRPWM0_CSG2_PC_PSWV_Pos 0 /*!< HRPWM0_CSG2 PC: PSWV Position */
\r
13100 #define HRPWM0_CSG2_PC_PSWV_Msk (0x3fUL << HRPWM0_CSG2_PC_PSWV_Pos) /*!< HRPWM0_CSG2 PC: PSWV Mask */
\r
13102 /* ------------------------------ HRPWM0_CSG2_DSV1 ------------------------------ */
\r
13103 #define HRPWM0_CSG2_DSV1_DSV1_Pos 0 /*!< HRPWM0_CSG2 DSV1: DSV1 Position */
\r
13104 #define HRPWM0_CSG2_DSV1_DSV1_Msk (0x000003ffUL << HRPWM0_CSG2_DSV1_DSV1_Pos) /*!< HRPWM0_CSG2 DSV1: DSV1 Mask */
\r
13106 /* ------------------------------ HRPWM0_CSG2_DSV2 ------------------------------ */
\r
13107 #define HRPWM0_CSG2_DSV2_DSV2_Pos 0 /*!< HRPWM0_CSG2 DSV2: DSV2 Position */
\r
13108 #define HRPWM0_CSG2_DSV2_DSV2_Msk (0x000003ffUL << HRPWM0_CSG2_DSV2_DSV2_Pos) /*!< HRPWM0_CSG2 DSV2: DSV2 Mask */
\r
13110 /* ------------------------------ HRPWM0_CSG2_SDSV1 ----------------------------- */
\r
13111 #define HRPWM0_CSG2_SDSV1_SDSV1_Pos 0 /*!< HRPWM0_CSG2 SDSV1: SDSV1 Position */
\r
13112 #define HRPWM0_CSG2_SDSV1_SDSV1_Msk (0x000003ffUL << HRPWM0_CSG2_SDSV1_SDSV1_Pos) /*!< HRPWM0_CSG2 SDSV1: SDSV1 Mask */
\r
13114 /* ------------------------------- HRPWM0_CSG2_SPC ------------------------------ */
\r
13115 #define HRPWM0_CSG2_SPC_SPSWV_Pos 0 /*!< HRPWM0_CSG2 SPC: SPSWV Position */
\r
13116 #define HRPWM0_CSG2_SPC_SPSWV_Msk (0x3fUL << HRPWM0_CSG2_SPC_SPSWV_Pos) /*!< HRPWM0_CSG2 SPC: SPSWV Mask */
\r
13118 /* ------------------------------- HRPWM0_CSG2_CC ------------------------------- */
\r
13119 #define HRPWM0_CSG2_CC_IBS_Pos 0 /*!< HRPWM0_CSG2 CC: IBS Position */
\r
13120 #define HRPWM0_CSG2_CC_IBS_Msk (0x0fUL << HRPWM0_CSG2_CC_IBS_Pos) /*!< HRPWM0_CSG2 CC: IBS Mask */
\r
13121 #define HRPWM0_CSG2_CC_IMCS_Pos 8 /*!< HRPWM0_CSG2 CC: IMCS Position */
\r
13122 #define HRPWM0_CSG2_CC_IMCS_Msk (0x01UL << HRPWM0_CSG2_CC_IMCS_Pos) /*!< HRPWM0_CSG2 CC: IMCS Mask */
\r
13123 #define HRPWM0_CSG2_CC_IMCC_Pos 9 /*!< HRPWM0_CSG2 CC: IMCC Position */
\r
13124 #define HRPWM0_CSG2_CC_IMCC_Msk (0x03UL << HRPWM0_CSG2_CC_IMCC_Pos) /*!< HRPWM0_CSG2 CC: IMCC Mask */
\r
13125 #define HRPWM0_CSG2_CC_ESE_Pos 11 /*!< HRPWM0_CSG2 CC: ESE Position */
\r
13126 #define HRPWM0_CSG2_CC_ESE_Msk (0x01UL << HRPWM0_CSG2_CC_ESE_Pos) /*!< HRPWM0_CSG2 CC: ESE Mask */
\r
13127 #define HRPWM0_CSG2_CC_OIE_Pos 12 /*!< HRPWM0_CSG2 CC: OIE Position */
\r
13128 #define HRPWM0_CSG2_CC_OIE_Msk (0x01UL << HRPWM0_CSG2_CC_OIE_Pos) /*!< HRPWM0_CSG2 CC: OIE Mask */
\r
13129 #define HRPWM0_CSG2_CC_OSE_Pos 13 /*!< HRPWM0_CSG2 CC: OSE Position */
\r
13130 #define HRPWM0_CSG2_CC_OSE_Msk (0x01UL << HRPWM0_CSG2_CC_OSE_Pos) /*!< HRPWM0_CSG2 CC: OSE Mask */
\r
13131 #define HRPWM0_CSG2_CC_BLMC_Pos 14 /*!< HRPWM0_CSG2 CC: BLMC Position */
\r
13132 #define HRPWM0_CSG2_CC_BLMC_Msk (0x03UL << HRPWM0_CSG2_CC_BLMC_Pos) /*!< HRPWM0_CSG2 CC: BLMC Mask */
\r
13133 #define HRPWM0_CSG2_CC_EBE_Pos 16 /*!< HRPWM0_CSG2 CC: EBE Position */
\r
13134 #define HRPWM0_CSG2_CC_EBE_Msk (0x01UL << HRPWM0_CSG2_CC_EBE_Pos) /*!< HRPWM0_CSG2 CC: EBE Mask */
\r
13135 #define HRPWM0_CSG2_CC_COFE_Pos 17 /*!< HRPWM0_CSG2 CC: COFE Position */
\r
13136 #define HRPWM0_CSG2_CC_COFE_Msk (0x01UL << HRPWM0_CSG2_CC_COFE_Pos) /*!< HRPWM0_CSG2 CC: COFE Mask */
\r
13137 #define HRPWM0_CSG2_CC_COFM_Pos 18 /*!< HRPWM0_CSG2 CC: COFM Position */
\r
13138 #define HRPWM0_CSG2_CC_COFM_Msk (0x0fUL << HRPWM0_CSG2_CC_COFM_Pos) /*!< HRPWM0_CSG2 CC: COFM Mask */
\r
13139 #define HRPWM0_CSG2_CC_COFC_Pos 24 /*!< HRPWM0_CSG2 CC: COFC Position */
\r
13140 #define HRPWM0_CSG2_CC_COFC_Msk (0x03UL << HRPWM0_CSG2_CC_COFC_Pos) /*!< HRPWM0_CSG2 CC: COFC Mask */
\r
13142 /* ------------------------------- HRPWM0_CSG2_PLC ------------------------------ */
\r
13143 #define HRPWM0_CSG2_PLC_IPLS_Pos 0 /*!< HRPWM0_CSG2 PLC: IPLS Position */
\r
13144 #define HRPWM0_CSG2_PLC_IPLS_Msk (0x0fUL << HRPWM0_CSG2_PLC_IPLS_Pos) /*!< HRPWM0_CSG2 PLC: IPLS Mask */
\r
13145 #define HRPWM0_CSG2_PLC_PLCL_Pos 8 /*!< HRPWM0_CSG2 PLC: PLCL Position */
\r
13146 #define HRPWM0_CSG2_PLC_PLCL_Msk (0x03UL << HRPWM0_CSG2_PLC_PLCL_Pos) /*!< HRPWM0_CSG2 PLC: PLCL Mask */
\r
13147 #define HRPWM0_CSG2_PLC_PSL_Pos 10 /*!< HRPWM0_CSG2 PLC: PSL Position */
\r
13148 #define HRPWM0_CSG2_PLC_PSL_Msk (0x01UL << HRPWM0_CSG2_PLC_PSL_Pos) /*!< HRPWM0_CSG2 PLC: PSL Mask */
\r
13149 #define HRPWM0_CSG2_PLC_PLSW_Pos 11 /*!< HRPWM0_CSG2 PLC: PLSW Position */
\r
13150 #define HRPWM0_CSG2_PLC_PLSW_Msk (0x01UL << HRPWM0_CSG2_PLC_PLSW_Pos) /*!< HRPWM0_CSG2 PLC: PLSW Mask */
\r
13151 #define HRPWM0_CSG2_PLC_PLEC_Pos 12 /*!< HRPWM0_CSG2 PLC: PLEC Position */
\r
13152 #define HRPWM0_CSG2_PLC_PLEC_Msk (0x03UL << HRPWM0_CSG2_PLC_PLEC_Pos) /*!< HRPWM0_CSG2 PLC: PLEC Mask */
\r
13153 #define HRPWM0_CSG2_PLC_PLXC_Pos 14 /*!< HRPWM0_CSG2 PLC: PLXC Position */
\r
13154 #define HRPWM0_CSG2_PLC_PLXC_Msk (0x03UL << HRPWM0_CSG2_PLC_PLXC_Pos) /*!< HRPWM0_CSG2 PLC: PLXC Mask */
\r
13156 /* ------------------------------- HRPWM0_CSG2_BLV ------------------------------ */
\r
13157 #define HRPWM0_CSG2_BLV_BLV_Pos 0 /*!< HRPWM0_CSG2 BLV: BLV Position */
\r
13158 #define HRPWM0_CSG2_BLV_BLV_Msk (0x000000ffUL << HRPWM0_CSG2_BLV_BLV_Pos) /*!< HRPWM0_CSG2 BLV: BLV Mask */
\r
13160 /* ------------------------------- HRPWM0_CSG2_SRE ------------------------------ */
\r
13161 #define HRPWM0_CSG2_SRE_VLS1E_Pos 0 /*!< HRPWM0_CSG2 SRE: VLS1E Position */
\r
13162 #define HRPWM0_CSG2_SRE_VLS1E_Msk (0x01UL << HRPWM0_CSG2_SRE_VLS1E_Pos) /*!< HRPWM0_CSG2 SRE: VLS1E Mask */
\r
13163 #define HRPWM0_CSG2_SRE_VLS2E_Pos 1 /*!< HRPWM0_CSG2 SRE: VLS2E Position */
\r
13164 #define HRPWM0_CSG2_SRE_VLS2E_Msk (0x01UL << HRPWM0_CSG2_SRE_VLS2E_Pos) /*!< HRPWM0_CSG2 SRE: VLS2E Mask */
\r
13165 #define HRPWM0_CSG2_SRE_TRGSE_Pos 2 /*!< HRPWM0_CSG2 SRE: TRGSE Position */
\r
13166 #define HRPWM0_CSG2_SRE_TRGSE_Msk (0x01UL << HRPWM0_CSG2_SRE_TRGSE_Pos) /*!< HRPWM0_CSG2 SRE: TRGSE Mask */
\r
13167 #define HRPWM0_CSG2_SRE_STRSE_Pos 3 /*!< HRPWM0_CSG2 SRE: STRSE Position */
\r
13168 #define HRPWM0_CSG2_SRE_STRSE_Msk (0x01UL << HRPWM0_CSG2_SRE_STRSE_Pos) /*!< HRPWM0_CSG2 SRE: STRSE Mask */
\r
13169 #define HRPWM0_CSG2_SRE_STPSE_Pos 4 /*!< HRPWM0_CSG2 SRE: STPSE Position */
\r
13170 #define HRPWM0_CSG2_SRE_STPSE_Msk (0x01UL << HRPWM0_CSG2_SRE_STPSE_Pos) /*!< HRPWM0_CSG2 SRE: STPSE Mask */
\r
13171 #define HRPWM0_CSG2_SRE_STDE_Pos 5 /*!< HRPWM0_CSG2 SRE: STDE Position */
\r
13172 #define HRPWM0_CSG2_SRE_STDE_Msk (0x01UL << HRPWM0_CSG2_SRE_STDE_Pos) /*!< HRPWM0_CSG2 SRE: STDE Mask */
\r
13173 #define HRPWM0_CSG2_SRE_CRSE_Pos 6 /*!< HRPWM0_CSG2 SRE: CRSE Position */
\r
13174 #define HRPWM0_CSG2_SRE_CRSE_Msk (0x01UL << HRPWM0_CSG2_SRE_CRSE_Pos) /*!< HRPWM0_CSG2 SRE: CRSE Mask */
\r
13175 #define HRPWM0_CSG2_SRE_CFSE_Pos 7 /*!< HRPWM0_CSG2 SRE: CFSE Position */
\r
13176 #define HRPWM0_CSG2_SRE_CFSE_Msk (0x01UL << HRPWM0_CSG2_SRE_CFSE_Pos) /*!< HRPWM0_CSG2 SRE: CFSE Mask */
\r
13177 #define HRPWM0_CSG2_SRE_CSEE_Pos 8 /*!< HRPWM0_CSG2 SRE: CSEE Position */
\r
13178 #define HRPWM0_CSG2_SRE_CSEE_Msk (0x01UL << HRPWM0_CSG2_SRE_CSEE_Pos) /*!< HRPWM0_CSG2 SRE: CSEE Mask */
\r
13180 /* ------------------------------- HRPWM0_CSG2_SRS ------------------------------ */
\r
13181 #define HRPWM0_CSG2_SRS_VLS1S_Pos 0 /*!< HRPWM0_CSG2 SRS: VLS1S Position */
\r
13182 #define HRPWM0_CSG2_SRS_VLS1S_Msk (0x03UL << HRPWM0_CSG2_SRS_VLS1S_Pos) /*!< HRPWM0_CSG2 SRS: VLS1S Mask */
\r
13183 #define HRPWM0_CSG2_SRS_VLS2S_Pos 2 /*!< HRPWM0_CSG2 SRS: VLS2S Position */
\r
13184 #define HRPWM0_CSG2_SRS_VLS2S_Msk (0x03UL << HRPWM0_CSG2_SRS_VLS2S_Pos) /*!< HRPWM0_CSG2 SRS: VLS2S Mask */
\r
13185 #define HRPWM0_CSG2_SRS_TRLS_Pos 4 /*!< HRPWM0_CSG2 SRS: TRLS Position */
\r
13186 #define HRPWM0_CSG2_SRS_TRLS_Msk (0x03UL << HRPWM0_CSG2_SRS_TRLS_Pos) /*!< HRPWM0_CSG2 SRS: TRLS Mask */
\r
13187 #define HRPWM0_CSG2_SRS_SSLS_Pos 6 /*!< HRPWM0_CSG2 SRS: SSLS Position */
\r
13188 #define HRPWM0_CSG2_SRS_SSLS_Msk (0x03UL << HRPWM0_CSG2_SRS_SSLS_Pos) /*!< HRPWM0_CSG2 SRS: SSLS Mask */
\r
13189 #define HRPWM0_CSG2_SRS_STLS_Pos 8 /*!< HRPWM0_CSG2 SRS: STLS Position */
\r
13190 #define HRPWM0_CSG2_SRS_STLS_Msk (0x03UL << HRPWM0_CSG2_SRS_STLS_Pos) /*!< HRPWM0_CSG2 SRS: STLS Mask */
\r
13191 #define HRPWM0_CSG2_SRS_CRFLS_Pos 10 /*!< HRPWM0_CSG2 SRS: CRFLS Position */
\r
13192 #define HRPWM0_CSG2_SRS_CRFLS_Msk (0x03UL << HRPWM0_CSG2_SRS_CRFLS_Pos) /*!< HRPWM0_CSG2 SRS: CRFLS Mask */
\r
13193 #define HRPWM0_CSG2_SRS_CSLS_Pos 12 /*!< HRPWM0_CSG2 SRS: CSLS Position */
\r
13194 #define HRPWM0_CSG2_SRS_CSLS_Msk (0x03UL << HRPWM0_CSG2_SRS_CSLS_Pos) /*!< HRPWM0_CSG2 SRS: CSLS Mask */
\r
13196 /* ------------------------------- HRPWM0_CSG2_SWS ------------------------------ */
\r
13197 #define HRPWM0_CSG2_SWS_SVLS1_Pos 0 /*!< HRPWM0_CSG2 SWS: SVLS1 Position */
\r
13198 #define HRPWM0_CSG2_SWS_SVLS1_Msk (0x01UL << HRPWM0_CSG2_SWS_SVLS1_Pos) /*!< HRPWM0_CSG2 SWS: SVLS1 Mask */
\r
13199 #define HRPWM0_CSG2_SWS_SVLS2_Pos 1 /*!< HRPWM0_CSG2 SWS: SVLS2 Position */
\r
13200 #define HRPWM0_CSG2_SWS_SVLS2_Msk (0x01UL << HRPWM0_CSG2_SWS_SVLS2_Pos) /*!< HRPWM0_CSG2 SWS: SVLS2 Mask */
\r
13201 #define HRPWM0_CSG2_SWS_STRGS_Pos 2 /*!< HRPWM0_CSG2 SWS: STRGS Position */
\r
13202 #define HRPWM0_CSG2_SWS_STRGS_Msk (0x01UL << HRPWM0_CSG2_SWS_STRGS_Pos) /*!< HRPWM0_CSG2 SWS: STRGS Mask */
\r
13203 #define HRPWM0_CSG2_SWS_SSTRS_Pos 3 /*!< HRPWM0_CSG2 SWS: SSTRS Position */
\r
13204 #define HRPWM0_CSG2_SWS_SSTRS_Msk (0x01UL << HRPWM0_CSG2_SWS_SSTRS_Pos) /*!< HRPWM0_CSG2 SWS: SSTRS Mask */
\r
13205 #define HRPWM0_CSG2_SWS_SSTPS_Pos 4 /*!< HRPWM0_CSG2 SWS: SSTPS Position */
\r
13206 #define HRPWM0_CSG2_SWS_SSTPS_Msk (0x01UL << HRPWM0_CSG2_SWS_SSTPS_Pos) /*!< HRPWM0_CSG2 SWS: SSTPS Mask */
\r
13207 #define HRPWM0_CSG2_SWS_SSTD_Pos 5 /*!< HRPWM0_CSG2 SWS: SSTD Position */
\r
13208 #define HRPWM0_CSG2_SWS_SSTD_Msk (0x01UL << HRPWM0_CSG2_SWS_SSTD_Pos) /*!< HRPWM0_CSG2 SWS: SSTD Mask */
\r
13209 #define HRPWM0_CSG2_SWS_SCRS_Pos 6 /*!< HRPWM0_CSG2 SWS: SCRS Position */
\r
13210 #define HRPWM0_CSG2_SWS_SCRS_Msk (0x01UL << HRPWM0_CSG2_SWS_SCRS_Pos) /*!< HRPWM0_CSG2 SWS: SCRS Mask */
\r
13211 #define HRPWM0_CSG2_SWS_SCFS_Pos 7 /*!< HRPWM0_CSG2 SWS: SCFS Position */
\r
13212 #define HRPWM0_CSG2_SWS_SCFS_Msk (0x01UL << HRPWM0_CSG2_SWS_SCFS_Pos) /*!< HRPWM0_CSG2 SWS: SCFS Mask */
\r
13213 #define HRPWM0_CSG2_SWS_SCSS_Pos 8 /*!< HRPWM0_CSG2 SWS: SCSS Position */
\r
13214 #define HRPWM0_CSG2_SWS_SCSS_Msk (0x01UL << HRPWM0_CSG2_SWS_SCSS_Pos) /*!< HRPWM0_CSG2 SWS: SCSS Mask */
\r
13216 /* ------------------------------- HRPWM0_CSG2_SWC ------------------------------ */
\r
13217 #define HRPWM0_CSG2_SWC_CVLS1_Pos 0 /*!< HRPWM0_CSG2 SWC: CVLS1 Position */
\r
13218 #define HRPWM0_CSG2_SWC_CVLS1_Msk (0x01UL << HRPWM0_CSG2_SWC_CVLS1_Pos) /*!< HRPWM0_CSG2 SWC: CVLS1 Mask */
\r
13219 #define HRPWM0_CSG2_SWC_CVLS2_Pos 1 /*!< HRPWM0_CSG2 SWC: CVLS2 Position */
\r
13220 #define HRPWM0_CSG2_SWC_CVLS2_Msk (0x01UL << HRPWM0_CSG2_SWC_CVLS2_Pos) /*!< HRPWM0_CSG2 SWC: CVLS2 Mask */
\r
13221 #define HRPWM0_CSG2_SWC_CTRGS_Pos 2 /*!< HRPWM0_CSG2 SWC: CTRGS Position */
\r
13222 #define HRPWM0_CSG2_SWC_CTRGS_Msk (0x01UL << HRPWM0_CSG2_SWC_CTRGS_Pos) /*!< HRPWM0_CSG2 SWC: CTRGS Mask */
\r
13223 #define HRPWM0_CSG2_SWC_CSTRS_Pos 3 /*!< HRPWM0_CSG2 SWC: CSTRS Position */
\r
13224 #define HRPWM0_CSG2_SWC_CSTRS_Msk (0x01UL << HRPWM0_CSG2_SWC_CSTRS_Pos) /*!< HRPWM0_CSG2 SWC: CSTRS Mask */
\r
13225 #define HRPWM0_CSG2_SWC_CSTPS_Pos 4 /*!< HRPWM0_CSG2 SWC: CSTPS Position */
\r
13226 #define HRPWM0_CSG2_SWC_CSTPS_Msk (0x01UL << HRPWM0_CSG2_SWC_CSTPS_Pos) /*!< HRPWM0_CSG2 SWC: CSTPS Mask */
\r
13227 #define HRPWM0_CSG2_SWC_CSTD_Pos 5 /*!< HRPWM0_CSG2 SWC: CSTD Position */
\r
13228 #define HRPWM0_CSG2_SWC_CSTD_Msk (0x01UL << HRPWM0_CSG2_SWC_CSTD_Pos) /*!< HRPWM0_CSG2 SWC: CSTD Mask */
\r
13229 #define HRPWM0_CSG2_SWC_CCRS_Pos 6 /*!< HRPWM0_CSG2 SWC: CCRS Position */
\r
13230 #define HRPWM0_CSG2_SWC_CCRS_Msk (0x01UL << HRPWM0_CSG2_SWC_CCRS_Pos) /*!< HRPWM0_CSG2 SWC: CCRS Mask */
\r
13231 #define HRPWM0_CSG2_SWC_CCFS_Pos 7 /*!< HRPWM0_CSG2 SWC: CCFS Position */
\r
13232 #define HRPWM0_CSG2_SWC_CCFS_Msk (0x01UL << HRPWM0_CSG2_SWC_CCFS_Pos) /*!< HRPWM0_CSG2 SWC: CCFS Mask */
\r
13233 #define HRPWM0_CSG2_SWC_CCSS_Pos 8 /*!< HRPWM0_CSG2 SWC: CCSS Position */
\r
13234 #define HRPWM0_CSG2_SWC_CCSS_Msk (0x01UL << HRPWM0_CSG2_SWC_CCSS_Pos) /*!< HRPWM0_CSG2 SWC: CCSS Mask */
\r
13236 /* ------------------------------ HRPWM0_CSG2_ISTAT ----------------------------- */
\r
13237 #define HRPWM0_CSG2_ISTAT_VLS1S_Pos 0 /*!< HRPWM0_CSG2 ISTAT: VLS1S Position */
\r
13238 #define HRPWM0_CSG2_ISTAT_VLS1S_Msk (0x01UL << HRPWM0_CSG2_ISTAT_VLS1S_Pos) /*!< HRPWM0_CSG2 ISTAT: VLS1S Mask */
\r
13239 #define HRPWM0_CSG2_ISTAT_VLS2S_Pos 1 /*!< HRPWM0_CSG2 ISTAT: VLS2S Position */
\r
13240 #define HRPWM0_CSG2_ISTAT_VLS2S_Msk (0x01UL << HRPWM0_CSG2_ISTAT_VLS2S_Pos) /*!< HRPWM0_CSG2 ISTAT: VLS2S Mask */
\r
13241 #define HRPWM0_CSG2_ISTAT_TRGSS_Pos 2 /*!< HRPWM0_CSG2 ISTAT: TRGSS Position */
\r
13242 #define HRPWM0_CSG2_ISTAT_TRGSS_Msk (0x01UL << HRPWM0_CSG2_ISTAT_TRGSS_Pos) /*!< HRPWM0_CSG2 ISTAT: TRGSS Mask */
\r
13243 #define HRPWM0_CSG2_ISTAT_STRSS_Pos 3 /*!< HRPWM0_CSG2 ISTAT: STRSS Position */
\r
13244 #define HRPWM0_CSG2_ISTAT_STRSS_Msk (0x01UL << HRPWM0_CSG2_ISTAT_STRSS_Pos) /*!< HRPWM0_CSG2 ISTAT: STRSS Mask */
\r
13245 #define HRPWM0_CSG2_ISTAT_STPSS_Pos 4 /*!< HRPWM0_CSG2 ISTAT: STPSS Position */
\r
13246 #define HRPWM0_CSG2_ISTAT_STPSS_Msk (0x01UL << HRPWM0_CSG2_ISTAT_STPSS_Pos) /*!< HRPWM0_CSG2 ISTAT: STPSS Mask */
\r
13247 #define HRPWM0_CSG2_ISTAT_STDS_Pos 5 /*!< HRPWM0_CSG2 ISTAT: STDS Position */
\r
13248 #define HRPWM0_CSG2_ISTAT_STDS_Msk (0x01UL << HRPWM0_CSG2_ISTAT_STDS_Pos) /*!< HRPWM0_CSG2 ISTAT: STDS Mask */
\r
13249 #define HRPWM0_CSG2_ISTAT_CRSS_Pos 6 /*!< HRPWM0_CSG2 ISTAT: CRSS Position */
\r
13250 #define HRPWM0_CSG2_ISTAT_CRSS_Msk (0x01UL << HRPWM0_CSG2_ISTAT_CRSS_Pos) /*!< HRPWM0_CSG2 ISTAT: CRSS Mask */
\r
13251 #define HRPWM0_CSG2_ISTAT_CFSS_Pos 7 /*!< HRPWM0_CSG2 ISTAT: CFSS Position */
\r
13252 #define HRPWM0_CSG2_ISTAT_CFSS_Msk (0x01UL << HRPWM0_CSG2_ISTAT_CFSS_Pos) /*!< HRPWM0_CSG2 ISTAT: CFSS Mask */
\r
13253 #define HRPWM0_CSG2_ISTAT_CSES_Pos 8 /*!< HRPWM0_CSG2 ISTAT: CSES Position */
\r
13254 #define HRPWM0_CSG2_ISTAT_CSES_Msk (0x01UL << HRPWM0_CSG2_ISTAT_CSES_Pos) /*!< HRPWM0_CSG2 ISTAT: CSES Mask */
\r
13257 /* ================================================================================ */
\r
13258 /* ================ Group 'HRPWM0_HRC' Position & Mask ================ */
\r
13259 /* ================================================================================ */
\r
13262 /* -------------------------------- HRPWM0_HRC_GC ------------------------------- */
\r
13263 #define HRPWM0_HRC_GC_HRM0_Pos 0 /*!< HRPWM0_HRC GC: HRM0 Position */
\r
13264 #define HRPWM0_HRC_GC_HRM0_Msk (0x03UL << HRPWM0_HRC_GC_HRM0_Pos) /*!< HRPWM0_HRC GC: HRM0 Mask */
\r
13265 #define HRPWM0_HRC_GC_HRM1_Pos 2 /*!< HRPWM0_HRC GC: HRM1 Position */
\r
13266 #define HRPWM0_HRC_GC_HRM1_Msk (0x03UL << HRPWM0_HRC_GC_HRM1_Pos) /*!< HRPWM0_HRC GC: HRM1 Mask */
\r
13267 #define HRPWM0_HRC_GC_DTE_Pos 8 /*!< HRPWM0_HRC GC: DTE Position */
\r
13268 #define HRPWM0_HRC_GC_DTE_Msk (0x01UL << HRPWM0_HRC_GC_DTE_Pos) /*!< HRPWM0_HRC GC: DTE Mask */
\r
13269 #define HRPWM0_HRC_GC_TR0E_Pos 9 /*!< HRPWM0_HRC GC: TR0E Position */
\r
13270 #define HRPWM0_HRC_GC_TR0E_Msk (0x01UL << HRPWM0_HRC_GC_TR0E_Pos) /*!< HRPWM0_HRC GC: TR0E Mask */
\r
13271 #define HRPWM0_HRC_GC_TR1E_Pos 10 /*!< HRPWM0_HRC GC: TR1E Position */
\r
13272 #define HRPWM0_HRC_GC_TR1E_Msk (0x01UL << HRPWM0_HRC_GC_TR1E_Pos) /*!< HRPWM0_HRC GC: TR1E Mask */
\r
13273 #define HRPWM0_HRC_GC_STC_Pos 11 /*!< HRPWM0_HRC GC: STC Position */
\r
13274 #define HRPWM0_HRC_GC_STC_Msk (0x01UL << HRPWM0_HRC_GC_STC_Pos) /*!< HRPWM0_HRC GC: STC Mask */
\r
13275 #define HRPWM0_HRC_GC_DSTC_Pos 12 /*!< HRPWM0_HRC GC: DSTC Position */
\r
13276 #define HRPWM0_HRC_GC_DSTC_Msk (0x01UL << HRPWM0_HRC_GC_DSTC_Pos) /*!< HRPWM0_HRC GC: DSTC Mask */
\r
13277 #define HRPWM0_HRC_GC_OCS0_Pos 13 /*!< HRPWM0_HRC GC: OCS0 Position */
\r
13278 #define HRPWM0_HRC_GC_OCS0_Msk (0x01UL << HRPWM0_HRC_GC_OCS0_Pos) /*!< HRPWM0_HRC GC: OCS0 Mask */
\r
13279 #define HRPWM0_HRC_GC_OCS1_Pos 14 /*!< HRPWM0_HRC GC: OCS1 Position */
\r
13280 #define HRPWM0_HRC_GC_OCS1_Msk (0x01UL << HRPWM0_HRC_GC_OCS1_Pos) /*!< HRPWM0_HRC GC: OCS1 Mask */
\r
13281 #define HRPWM0_HRC_GC_DTUS_Pos 16 /*!< HRPWM0_HRC GC: DTUS Position */
\r
13282 #define HRPWM0_HRC_GC_DTUS_Msk (0x01UL << HRPWM0_HRC_GC_DTUS_Pos) /*!< HRPWM0_HRC GC: DTUS Mask */
\r
13284 /* -------------------------------- HRPWM0_HRC_PL ------------------------------- */
\r
13285 #define HRPWM0_HRC_PL_PSL0_Pos 0 /*!< HRPWM0_HRC PL: PSL0 Position */
\r
13286 #define HRPWM0_HRC_PL_PSL0_Msk (0x01UL << HRPWM0_HRC_PL_PSL0_Pos) /*!< HRPWM0_HRC PL: PSL0 Mask */
\r
13287 #define HRPWM0_HRC_PL_PSL1_Pos 1 /*!< HRPWM0_HRC PL: PSL1 Position */
\r
13288 #define HRPWM0_HRC_PL_PSL1_Msk (0x01UL << HRPWM0_HRC_PL_PSL1_Pos) /*!< HRPWM0_HRC PL: PSL1 Mask */
\r
13290 /* ------------------------------- HRPWM0_HRC_GSEL ------------------------------ */
\r
13291 #define HRPWM0_HRC_GSEL_C0SS_Pos 0 /*!< HRPWM0_HRC GSEL: C0SS Position */
\r
13292 #define HRPWM0_HRC_GSEL_C0SS_Msk (0x07UL << HRPWM0_HRC_GSEL_C0SS_Pos) /*!< HRPWM0_HRC GSEL: C0SS Mask */
\r
13293 #define HRPWM0_HRC_GSEL_C0CS_Pos 3 /*!< HRPWM0_HRC GSEL: C0CS Position */
\r
13294 #define HRPWM0_HRC_GSEL_C0CS_Msk (0x07UL << HRPWM0_HRC_GSEL_C0CS_Pos) /*!< HRPWM0_HRC GSEL: C0CS Mask */
\r
13295 #define HRPWM0_HRC_GSEL_S0M_Pos 6 /*!< HRPWM0_HRC GSEL: S0M Position */
\r
13296 #define HRPWM0_HRC_GSEL_S0M_Msk (0x03UL << HRPWM0_HRC_GSEL_S0M_Pos) /*!< HRPWM0_HRC GSEL: S0M Mask */
\r
13297 #define HRPWM0_HRC_GSEL_C0M_Pos 8 /*!< HRPWM0_HRC GSEL: C0M Position */
\r
13298 #define HRPWM0_HRC_GSEL_C0M_Msk (0x03UL << HRPWM0_HRC_GSEL_C0M_Pos) /*!< HRPWM0_HRC GSEL: C0M Mask */
\r
13299 #define HRPWM0_HRC_GSEL_S0ES_Pos 10 /*!< HRPWM0_HRC GSEL: S0ES Position */
\r
13300 #define HRPWM0_HRC_GSEL_S0ES_Msk (0x03UL << HRPWM0_HRC_GSEL_S0ES_Pos) /*!< HRPWM0_HRC GSEL: S0ES Mask */
\r
13301 #define HRPWM0_HRC_GSEL_C0ES_Pos 12 /*!< HRPWM0_HRC GSEL: C0ES Position */
\r
13302 #define HRPWM0_HRC_GSEL_C0ES_Msk (0x03UL << HRPWM0_HRC_GSEL_C0ES_Pos) /*!< HRPWM0_HRC GSEL: C0ES Mask */
\r
13303 #define HRPWM0_HRC_GSEL_C1SS_Pos 16 /*!< HRPWM0_HRC GSEL: C1SS Position */
\r
13304 #define HRPWM0_HRC_GSEL_C1SS_Msk (0x07UL << HRPWM0_HRC_GSEL_C1SS_Pos) /*!< HRPWM0_HRC GSEL: C1SS Mask */
\r
13305 #define HRPWM0_HRC_GSEL_C1CS_Pos 19 /*!< HRPWM0_HRC GSEL: C1CS Position */
\r
13306 #define HRPWM0_HRC_GSEL_C1CS_Msk (0x07UL << HRPWM0_HRC_GSEL_C1CS_Pos) /*!< HRPWM0_HRC GSEL: C1CS Mask */
\r
13307 #define HRPWM0_HRC_GSEL_S1M_Pos 22 /*!< HRPWM0_HRC GSEL: S1M Position */
\r
13308 #define HRPWM0_HRC_GSEL_S1M_Msk (0x03UL << HRPWM0_HRC_GSEL_S1M_Pos) /*!< HRPWM0_HRC GSEL: S1M Mask */
\r
13309 #define HRPWM0_HRC_GSEL_C1M_Pos 24 /*!< HRPWM0_HRC GSEL: C1M Position */
\r
13310 #define HRPWM0_HRC_GSEL_C1M_Msk (0x03UL << HRPWM0_HRC_GSEL_C1M_Pos) /*!< HRPWM0_HRC GSEL: C1M Mask */
\r
13311 #define HRPWM0_HRC_GSEL_S1ES_Pos 26 /*!< HRPWM0_HRC GSEL: S1ES Position */
\r
13312 #define HRPWM0_HRC_GSEL_S1ES_Msk (0x03UL << HRPWM0_HRC_GSEL_S1ES_Pos) /*!< HRPWM0_HRC GSEL: S1ES Mask */
\r
13313 #define HRPWM0_HRC_GSEL_C1ES_Pos 28 /*!< HRPWM0_HRC GSEL: C1ES Position */
\r
13314 #define HRPWM0_HRC_GSEL_C1ES_Msk (0x03UL << HRPWM0_HRC_GSEL_C1ES_Pos) /*!< HRPWM0_HRC GSEL: C1ES Mask */
\r
13316 /* ------------------------------- HRPWM0_HRC_TSEL ------------------------------ */
\r
13317 #define HRPWM0_HRC_TSEL_TSEL0_Pos 0 /*!< HRPWM0_HRC TSEL: TSEL0 Position */
\r
13318 #define HRPWM0_HRC_TSEL_TSEL0_Msk (0x07UL << HRPWM0_HRC_TSEL_TSEL0_Pos) /*!< HRPWM0_HRC TSEL: TSEL0 Mask */
\r
13319 #define HRPWM0_HRC_TSEL_TSEL1_Pos 3 /*!< HRPWM0_HRC TSEL: TSEL1 Position */
\r
13320 #define HRPWM0_HRC_TSEL_TSEL1_Msk (0x07UL << HRPWM0_HRC_TSEL_TSEL1_Pos) /*!< HRPWM0_HRC TSEL: TSEL1 Mask */
\r
13321 #define HRPWM0_HRC_TSEL_TS0E_Pos 16 /*!< HRPWM0_HRC TSEL: TS0E Position */
\r
13322 #define HRPWM0_HRC_TSEL_TS0E_Msk (0x01UL << HRPWM0_HRC_TSEL_TS0E_Pos) /*!< HRPWM0_HRC TSEL: TS0E Mask */
\r
13323 #define HRPWM0_HRC_TSEL_TS1E_Pos 17 /*!< HRPWM0_HRC TSEL: TS1E Position */
\r
13324 #define HRPWM0_HRC_TSEL_TS1E_Msk (0x01UL << HRPWM0_HRC_TSEL_TS1E_Pos) /*!< HRPWM0_HRC TSEL: TS1E Mask */
\r
13326 /* -------------------------------- HRPWM0_HRC_SC ------------------------------- */
\r
13327 #define HRPWM0_HRC_SC_ST_Pos 0 /*!< HRPWM0_HRC SC: ST Position */
\r
13328 #define HRPWM0_HRC_SC_ST_Msk (0x01UL << HRPWM0_HRC_SC_ST_Pos) /*!< HRPWM0_HRC SC: ST Mask */
\r
13330 /* ------------------------------- HRPWM0_HRC_DCR ------------------------------- */
\r
13331 #define HRPWM0_HRC_DCR_DTRV_Pos 0 /*!< HRPWM0_HRC DCR: DTRV Position */
\r
13332 #define HRPWM0_HRC_DCR_DTRV_Msk (0x0000ffffUL << HRPWM0_HRC_DCR_DTRV_Pos) /*!< HRPWM0_HRC DCR: DTRV Mask */
\r
13334 /* ------------------------------- HRPWM0_HRC_DCF ------------------------------- */
\r
13335 #define HRPWM0_HRC_DCF_DTFV_Pos 0 /*!< HRPWM0_HRC DCF: DTFV Position */
\r
13336 #define HRPWM0_HRC_DCF_DTFV_Msk (0x0000ffffUL << HRPWM0_HRC_DCF_DTFV_Pos) /*!< HRPWM0_HRC DCF: DTFV Mask */
\r
13338 /* ------------------------------- HRPWM0_HRC_CR1 ------------------------------- */
\r
13339 #define HRPWM0_HRC_CR1_CR1_Pos 0 /*!< HRPWM0_HRC CR1: CR1 Position */
\r
13340 #define HRPWM0_HRC_CR1_CR1_Msk (0x000000ffUL << HRPWM0_HRC_CR1_CR1_Pos) /*!< HRPWM0_HRC CR1: CR1 Mask */
\r
13342 /* ------------------------------- HRPWM0_HRC_CR2 ------------------------------- */
\r
13343 #define HRPWM0_HRC_CR2_CR2_Pos 0 /*!< HRPWM0_HRC CR2: CR2 Position */
\r
13344 #define HRPWM0_HRC_CR2_CR2_Msk (0x000000ffUL << HRPWM0_HRC_CR2_CR2_Pos) /*!< HRPWM0_HRC CR2: CR2 Mask */
\r
13346 /* ------------------------------- HRPWM0_HRC_SSC ------------------------------- */
\r
13347 #define HRPWM0_HRC_SSC_SST_Pos 0 /*!< HRPWM0_HRC SSC: SST Position */
\r
13348 #define HRPWM0_HRC_SSC_SST_Msk (0x01UL << HRPWM0_HRC_SSC_SST_Pos) /*!< HRPWM0_HRC SSC: SST Mask */
\r
13350 /* ------------------------------- HRPWM0_HRC_SDCR ------------------------------ */
\r
13351 #define HRPWM0_HRC_SDCR_SDTRV_Pos 0 /*!< HRPWM0_HRC SDCR: SDTRV Position */
\r
13352 #define HRPWM0_HRC_SDCR_SDTRV_Msk (0x0000ffffUL << HRPWM0_HRC_SDCR_SDTRV_Pos) /*!< HRPWM0_HRC SDCR: SDTRV Mask */
\r
13354 /* ------------------------------- HRPWM0_HRC_SDCF ------------------------------ */
\r
13355 #define HRPWM0_HRC_SDCF_SDTFV_Pos 0 /*!< HRPWM0_HRC SDCF: SDTFV Position */
\r
13356 #define HRPWM0_HRC_SDCF_SDTFV_Msk (0x0000ffffUL << HRPWM0_HRC_SDCF_SDTFV_Pos) /*!< HRPWM0_HRC SDCF: SDTFV Mask */
\r
13358 /* ------------------------------- HRPWM0_HRC_SCR1 ------------------------------ */
\r
13359 #define HRPWM0_HRC_SCR1_SCR1_Pos 0 /*!< HRPWM0_HRC SCR1: SCR1 Position */
\r
13360 #define HRPWM0_HRC_SCR1_SCR1_Msk (0x000000ffUL << HRPWM0_HRC_SCR1_SCR1_Pos) /*!< HRPWM0_HRC SCR1: SCR1 Mask */
\r
13362 /* ------------------------------- HRPWM0_HRC_SCR2 ------------------------------ */
\r
13363 #define HRPWM0_HRC_SCR2_SCR2_Pos 0 /*!< HRPWM0_HRC SCR2: SCR2 Position */
\r
13364 #define HRPWM0_HRC_SCR2_SCR2_Msk (0x000000ffUL << HRPWM0_HRC_SCR2_SCR2_Pos) /*!< HRPWM0_HRC SCR2: SCR2 Mask */
\r
13367 /* ================================================================================ */
\r
13368 /* ================ struct 'HRPWM0_HRC0' Position & Mask ================ */
\r
13369 /* ================================================================================ */
\r
13372 /* ------------------------------- HRPWM0_HRC0_GC ------------------------------- */
\r
13373 #define HRPWM0_HRC0_GC_HRM0_Pos 0 /*!< HRPWM0_HRC0 GC: HRM0 Position */
\r
13374 #define HRPWM0_HRC0_GC_HRM0_Msk (0x03UL << HRPWM0_HRC0_GC_HRM0_Pos) /*!< HRPWM0_HRC0 GC: HRM0 Mask */
\r
13375 #define HRPWM0_HRC0_GC_HRM1_Pos 2 /*!< HRPWM0_HRC0 GC: HRM1 Position */
\r
13376 #define HRPWM0_HRC0_GC_HRM1_Msk (0x03UL << HRPWM0_HRC0_GC_HRM1_Pos) /*!< HRPWM0_HRC0 GC: HRM1 Mask */
\r
13377 #define HRPWM0_HRC0_GC_DTE_Pos 8 /*!< HRPWM0_HRC0 GC: DTE Position */
\r
13378 #define HRPWM0_HRC0_GC_DTE_Msk (0x01UL << HRPWM0_HRC0_GC_DTE_Pos) /*!< HRPWM0_HRC0 GC: DTE Mask */
\r
13379 #define HRPWM0_HRC0_GC_TR0E_Pos 9 /*!< HRPWM0_HRC0 GC: TR0E Position */
\r
13380 #define HRPWM0_HRC0_GC_TR0E_Msk (0x01UL << HRPWM0_HRC0_GC_TR0E_Pos) /*!< HRPWM0_HRC0 GC: TR0E Mask */
\r
13381 #define HRPWM0_HRC0_GC_TR1E_Pos 10 /*!< HRPWM0_HRC0 GC: TR1E Position */
\r
13382 #define HRPWM0_HRC0_GC_TR1E_Msk (0x01UL << HRPWM0_HRC0_GC_TR1E_Pos) /*!< HRPWM0_HRC0 GC: TR1E Mask */
\r
13383 #define HRPWM0_HRC0_GC_STC_Pos 11 /*!< HRPWM0_HRC0 GC: STC Position */
\r
13384 #define HRPWM0_HRC0_GC_STC_Msk (0x01UL << HRPWM0_HRC0_GC_STC_Pos) /*!< HRPWM0_HRC0 GC: STC Mask */
\r
13385 #define HRPWM0_HRC0_GC_DSTC_Pos 12 /*!< HRPWM0_HRC0 GC: DSTC Position */
\r
13386 #define HRPWM0_HRC0_GC_DSTC_Msk (0x01UL << HRPWM0_HRC0_GC_DSTC_Pos) /*!< HRPWM0_HRC0 GC: DSTC Mask */
\r
13387 #define HRPWM0_HRC0_GC_OCS0_Pos 13 /*!< HRPWM0_HRC0 GC: OCS0 Position */
\r
13388 #define HRPWM0_HRC0_GC_OCS0_Msk (0x01UL << HRPWM0_HRC0_GC_OCS0_Pos) /*!< HRPWM0_HRC0 GC: OCS0 Mask */
\r
13389 #define HRPWM0_HRC0_GC_OCS1_Pos 14 /*!< HRPWM0_HRC0 GC: OCS1 Position */
\r
13390 #define HRPWM0_HRC0_GC_OCS1_Msk (0x01UL << HRPWM0_HRC0_GC_OCS1_Pos) /*!< HRPWM0_HRC0 GC: OCS1 Mask */
\r
13391 #define HRPWM0_HRC0_GC_DTUS_Pos 16 /*!< HRPWM0_HRC0 GC: DTUS Position */
\r
13392 #define HRPWM0_HRC0_GC_DTUS_Msk (0x01UL << HRPWM0_HRC0_GC_DTUS_Pos) /*!< HRPWM0_HRC0 GC: DTUS Mask */
\r
13394 /* ------------------------------- HRPWM0_HRC0_PL ------------------------------- */
\r
13395 #define HRPWM0_HRC0_PL_PSL0_Pos 0 /*!< HRPWM0_HRC0 PL: PSL0 Position */
\r
13396 #define HRPWM0_HRC0_PL_PSL0_Msk (0x01UL << HRPWM0_HRC0_PL_PSL0_Pos) /*!< HRPWM0_HRC0 PL: PSL0 Mask */
\r
13397 #define HRPWM0_HRC0_PL_PSL1_Pos 1 /*!< HRPWM0_HRC0 PL: PSL1 Position */
\r
13398 #define HRPWM0_HRC0_PL_PSL1_Msk (0x01UL << HRPWM0_HRC0_PL_PSL1_Pos) /*!< HRPWM0_HRC0 PL: PSL1 Mask */
\r
13400 /* ------------------------------ HRPWM0_HRC0_GSEL ------------------------------ */
\r
13401 #define HRPWM0_HRC0_GSEL_C0SS_Pos 0 /*!< HRPWM0_HRC0 GSEL: C0SS Position */
\r
13402 #define HRPWM0_HRC0_GSEL_C0SS_Msk (0x07UL << HRPWM0_HRC0_GSEL_C0SS_Pos) /*!< HRPWM0_HRC0 GSEL: C0SS Mask */
\r
13403 #define HRPWM0_HRC0_GSEL_C0CS_Pos 3 /*!< HRPWM0_HRC0 GSEL: C0CS Position */
\r
13404 #define HRPWM0_HRC0_GSEL_C0CS_Msk (0x07UL << HRPWM0_HRC0_GSEL_C0CS_Pos) /*!< HRPWM0_HRC0 GSEL: C0CS Mask */
\r
13405 #define HRPWM0_HRC0_GSEL_S0M_Pos 6 /*!< HRPWM0_HRC0 GSEL: S0M Position */
\r
13406 #define HRPWM0_HRC0_GSEL_S0M_Msk (0x03UL << HRPWM0_HRC0_GSEL_S0M_Pos) /*!< HRPWM0_HRC0 GSEL: S0M Mask */
\r
13407 #define HRPWM0_HRC0_GSEL_C0M_Pos 8 /*!< HRPWM0_HRC0 GSEL: C0M Position */
\r
13408 #define HRPWM0_HRC0_GSEL_C0M_Msk (0x03UL << HRPWM0_HRC0_GSEL_C0M_Pos) /*!< HRPWM0_HRC0 GSEL: C0M Mask */
\r
13409 #define HRPWM0_HRC0_GSEL_S0ES_Pos 10 /*!< HRPWM0_HRC0 GSEL: S0ES Position */
\r
13410 #define HRPWM0_HRC0_GSEL_S0ES_Msk (0x03UL << HRPWM0_HRC0_GSEL_S0ES_Pos) /*!< HRPWM0_HRC0 GSEL: S0ES Mask */
\r
13411 #define HRPWM0_HRC0_GSEL_C0ES_Pos 12 /*!< HRPWM0_HRC0 GSEL: C0ES Position */
\r
13412 #define HRPWM0_HRC0_GSEL_C0ES_Msk (0x03UL << HRPWM0_HRC0_GSEL_C0ES_Pos) /*!< HRPWM0_HRC0 GSEL: C0ES Mask */
\r
13413 #define HRPWM0_HRC0_GSEL_C1SS_Pos 16 /*!< HRPWM0_HRC0 GSEL: C1SS Position */
\r
13414 #define HRPWM0_HRC0_GSEL_C1SS_Msk (0x07UL << HRPWM0_HRC0_GSEL_C1SS_Pos) /*!< HRPWM0_HRC0 GSEL: C1SS Mask */
\r
13415 #define HRPWM0_HRC0_GSEL_C1CS_Pos 19 /*!< HRPWM0_HRC0 GSEL: C1CS Position */
\r
13416 #define HRPWM0_HRC0_GSEL_C1CS_Msk (0x07UL << HRPWM0_HRC0_GSEL_C1CS_Pos) /*!< HRPWM0_HRC0 GSEL: C1CS Mask */
\r
13417 #define HRPWM0_HRC0_GSEL_S1M_Pos 22 /*!< HRPWM0_HRC0 GSEL: S1M Position */
\r
13418 #define HRPWM0_HRC0_GSEL_S1M_Msk (0x03UL << HRPWM0_HRC0_GSEL_S1M_Pos) /*!< HRPWM0_HRC0 GSEL: S1M Mask */
\r
13419 #define HRPWM0_HRC0_GSEL_C1M_Pos 24 /*!< HRPWM0_HRC0 GSEL: C1M Position */
\r
13420 #define HRPWM0_HRC0_GSEL_C1M_Msk (0x03UL << HRPWM0_HRC0_GSEL_C1M_Pos) /*!< HRPWM0_HRC0 GSEL: C1M Mask */
\r
13421 #define HRPWM0_HRC0_GSEL_S1ES_Pos 26 /*!< HRPWM0_HRC0 GSEL: S1ES Position */
\r
13422 #define HRPWM0_HRC0_GSEL_S1ES_Msk (0x03UL << HRPWM0_HRC0_GSEL_S1ES_Pos) /*!< HRPWM0_HRC0 GSEL: S1ES Mask */
\r
13423 #define HRPWM0_HRC0_GSEL_C1ES_Pos 28 /*!< HRPWM0_HRC0 GSEL: C1ES Position */
\r
13424 #define HRPWM0_HRC0_GSEL_C1ES_Msk (0x03UL << HRPWM0_HRC0_GSEL_C1ES_Pos) /*!< HRPWM0_HRC0 GSEL: C1ES Mask */
\r
13426 /* ------------------------------ HRPWM0_HRC0_TSEL ------------------------------ */
\r
13427 #define HRPWM0_HRC0_TSEL_TSEL0_Pos 0 /*!< HRPWM0_HRC0 TSEL: TSEL0 Position */
\r
13428 #define HRPWM0_HRC0_TSEL_TSEL0_Msk (0x07UL << HRPWM0_HRC0_TSEL_TSEL0_Pos) /*!< HRPWM0_HRC0 TSEL: TSEL0 Mask */
\r
13429 #define HRPWM0_HRC0_TSEL_TSEL1_Pos 3 /*!< HRPWM0_HRC0 TSEL: TSEL1 Position */
\r
13430 #define HRPWM0_HRC0_TSEL_TSEL1_Msk (0x07UL << HRPWM0_HRC0_TSEL_TSEL1_Pos) /*!< HRPWM0_HRC0 TSEL: TSEL1 Mask */
\r
13431 #define HRPWM0_HRC0_TSEL_TS0E_Pos 16 /*!< HRPWM0_HRC0 TSEL: TS0E Position */
\r
13432 #define HRPWM0_HRC0_TSEL_TS0E_Msk (0x01UL << HRPWM0_HRC0_TSEL_TS0E_Pos) /*!< HRPWM0_HRC0 TSEL: TS0E Mask */
\r
13433 #define HRPWM0_HRC0_TSEL_TS1E_Pos 17 /*!< HRPWM0_HRC0 TSEL: TS1E Position */
\r
13434 #define HRPWM0_HRC0_TSEL_TS1E_Msk (0x01UL << HRPWM0_HRC0_TSEL_TS1E_Pos) /*!< HRPWM0_HRC0 TSEL: TS1E Mask */
\r
13436 /* ------------------------------- HRPWM0_HRC0_SC ------------------------------- */
\r
13437 #define HRPWM0_HRC0_SC_ST_Pos 0 /*!< HRPWM0_HRC0 SC: ST Position */
\r
13438 #define HRPWM0_HRC0_SC_ST_Msk (0x01UL << HRPWM0_HRC0_SC_ST_Pos) /*!< HRPWM0_HRC0 SC: ST Mask */
\r
13440 /* ------------------------------- HRPWM0_HRC0_DCR ------------------------------ */
\r
13441 #define HRPWM0_HRC0_DCR_DTRV_Pos 0 /*!< HRPWM0_HRC0 DCR: DTRV Position */
\r
13442 #define HRPWM0_HRC0_DCR_DTRV_Msk (0x0000ffffUL << HRPWM0_HRC0_DCR_DTRV_Pos) /*!< HRPWM0_HRC0 DCR: DTRV Mask */
\r
13444 /* ------------------------------- HRPWM0_HRC0_DCF ------------------------------ */
\r
13445 #define HRPWM0_HRC0_DCF_DTFV_Pos 0 /*!< HRPWM0_HRC0 DCF: DTFV Position */
\r
13446 #define HRPWM0_HRC0_DCF_DTFV_Msk (0x0000ffffUL << HRPWM0_HRC0_DCF_DTFV_Pos) /*!< HRPWM0_HRC0 DCF: DTFV Mask */
\r
13448 /* ------------------------------- HRPWM0_HRC0_CR1 ------------------------------ */
\r
13449 #define HRPWM0_HRC0_CR1_CR1_Pos 0 /*!< HRPWM0_HRC0 CR1: CR1 Position */
\r
13450 #define HRPWM0_HRC0_CR1_CR1_Msk (0x000000ffUL << HRPWM0_HRC0_CR1_CR1_Pos) /*!< HRPWM0_HRC0 CR1: CR1 Mask */
\r
13452 /* ------------------------------- HRPWM0_HRC0_CR2 ------------------------------ */
\r
13453 #define HRPWM0_HRC0_CR2_CR2_Pos 0 /*!< HRPWM0_HRC0 CR2: CR2 Position */
\r
13454 #define HRPWM0_HRC0_CR2_CR2_Msk (0x000000ffUL << HRPWM0_HRC0_CR2_CR2_Pos) /*!< HRPWM0_HRC0 CR2: CR2 Mask */
\r
13456 /* ------------------------------- HRPWM0_HRC0_SSC ------------------------------ */
\r
13457 #define HRPWM0_HRC0_SSC_SST_Pos 0 /*!< HRPWM0_HRC0 SSC: SST Position */
\r
13458 #define HRPWM0_HRC0_SSC_SST_Msk (0x01UL << HRPWM0_HRC0_SSC_SST_Pos) /*!< HRPWM0_HRC0 SSC: SST Mask */
\r
13460 /* ------------------------------ HRPWM0_HRC0_SDCR ------------------------------ */
\r
13461 #define HRPWM0_HRC0_SDCR_SDTRV_Pos 0 /*!< HRPWM0_HRC0 SDCR: SDTRV Position */
\r
13462 #define HRPWM0_HRC0_SDCR_SDTRV_Msk (0x0000ffffUL << HRPWM0_HRC0_SDCR_SDTRV_Pos) /*!< HRPWM0_HRC0 SDCR: SDTRV Mask */
\r
13464 /* ------------------------------ HRPWM0_HRC0_SDCF ------------------------------ */
\r
13465 #define HRPWM0_HRC0_SDCF_SDTFV_Pos 0 /*!< HRPWM0_HRC0 SDCF: SDTFV Position */
\r
13466 #define HRPWM0_HRC0_SDCF_SDTFV_Msk (0x0000ffffUL << HRPWM0_HRC0_SDCF_SDTFV_Pos) /*!< HRPWM0_HRC0 SDCF: SDTFV Mask */
\r
13468 /* ------------------------------ HRPWM0_HRC0_SCR1 ------------------------------ */
\r
13469 #define HRPWM0_HRC0_SCR1_SCR1_Pos 0 /*!< HRPWM0_HRC0 SCR1: SCR1 Position */
\r
13470 #define HRPWM0_HRC0_SCR1_SCR1_Msk (0x000000ffUL << HRPWM0_HRC0_SCR1_SCR1_Pos) /*!< HRPWM0_HRC0 SCR1: SCR1 Mask */
\r
13472 /* ------------------------------ HRPWM0_HRC0_SCR2 ------------------------------ */
\r
13473 #define HRPWM0_HRC0_SCR2_SCR2_Pos 0 /*!< HRPWM0_HRC0 SCR2: SCR2 Position */
\r
13474 #define HRPWM0_HRC0_SCR2_SCR2_Msk (0x000000ffUL << HRPWM0_HRC0_SCR2_SCR2_Pos) /*!< HRPWM0_HRC0 SCR2: SCR2 Mask */
\r
13477 /* ================================================================================ */
\r
13478 /* ================ struct 'HRPWM0_HRC1' Position & Mask ================ */
\r
13479 /* ================================================================================ */
\r
13482 /* ------------------------------- HRPWM0_HRC1_GC ------------------------------- */
\r
13483 #define HRPWM0_HRC1_GC_HRM0_Pos 0 /*!< HRPWM0_HRC1 GC: HRM0 Position */
\r
13484 #define HRPWM0_HRC1_GC_HRM0_Msk (0x03UL << HRPWM0_HRC1_GC_HRM0_Pos) /*!< HRPWM0_HRC1 GC: HRM0 Mask */
\r
13485 #define HRPWM0_HRC1_GC_HRM1_Pos 2 /*!< HRPWM0_HRC1 GC: HRM1 Position */
\r
13486 #define HRPWM0_HRC1_GC_HRM1_Msk (0x03UL << HRPWM0_HRC1_GC_HRM1_Pos) /*!< HRPWM0_HRC1 GC: HRM1 Mask */
\r
13487 #define HRPWM0_HRC1_GC_DTE_Pos 8 /*!< HRPWM0_HRC1 GC: DTE Position */
\r
13488 #define HRPWM0_HRC1_GC_DTE_Msk (0x01UL << HRPWM0_HRC1_GC_DTE_Pos) /*!< HRPWM0_HRC1 GC: DTE Mask */
\r
13489 #define HRPWM0_HRC1_GC_TR0E_Pos 9 /*!< HRPWM0_HRC1 GC: TR0E Position */
\r
13490 #define HRPWM0_HRC1_GC_TR0E_Msk (0x01UL << HRPWM0_HRC1_GC_TR0E_Pos) /*!< HRPWM0_HRC1 GC: TR0E Mask */
\r
13491 #define HRPWM0_HRC1_GC_TR1E_Pos 10 /*!< HRPWM0_HRC1 GC: TR1E Position */
\r
13492 #define HRPWM0_HRC1_GC_TR1E_Msk (0x01UL << HRPWM0_HRC1_GC_TR1E_Pos) /*!< HRPWM0_HRC1 GC: TR1E Mask */
\r
13493 #define HRPWM0_HRC1_GC_STC_Pos 11 /*!< HRPWM0_HRC1 GC: STC Position */
\r
13494 #define HRPWM0_HRC1_GC_STC_Msk (0x01UL << HRPWM0_HRC1_GC_STC_Pos) /*!< HRPWM0_HRC1 GC: STC Mask */
\r
13495 #define HRPWM0_HRC1_GC_DSTC_Pos 12 /*!< HRPWM0_HRC1 GC: DSTC Position */
\r
13496 #define HRPWM0_HRC1_GC_DSTC_Msk (0x01UL << HRPWM0_HRC1_GC_DSTC_Pos) /*!< HRPWM0_HRC1 GC: DSTC Mask */
\r
13497 #define HRPWM0_HRC1_GC_OCS0_Pos 13 /*!< HRPWM0_HRC1 GC: OCS0 Position */
\r
13498 #define HRPWM0_HRC1_GC_OCS0_Msk (0x01UL << HRPWM0_HRC1_GC_OCS0_Pos) /*!< HRPWM0_HRC1 GC: OCS0 Mask */
\r
13499 #define HRPWM0_HRC1_GC_OCS1_Pos 14 /*!< HRPWM0_HRC1 GC: OCS1 Position */
\r
13500 #define HRPWM0_HRC1_GC_OCS1_Msk (0x01UL << HRPWM0_HRC1_GC_OCS1_Pos) /*!< HRPWM0_HRC1 GC: OCS1 Mask */
\r
13501 #define HRPWM0_HRC1_GC_DTUS_Pos 16 /*!< HRPWM0_HRC1 GC: DTUS Position */
\r
13502 #define HRPWM0_HRC1_GC_DTUS_Msk (0x01UL << HRPWM0_HRC1_GC_DTUS_Pos) /*!< HRPWM0_HRC1 GC: DTUS Mask */
\r
13504 /* ------------------------------- HRPWM0_HRC1_PL ------------------------------- */
\r
13505 #define HRPWM0_HRC1_PL_PSL0_Pos 0 /*!< HRPWM0_HRC1 PL: PSL0 Position */
\r
13506 #define HRPWM0_HRC1_PL_PSL0_Msk (0x01UL << HRPWM0_HRC1_PL_PSL0_Pos) /*!< HRPWM0_HRC1 PL: PSL0 Mask */
\r
13507 #define HRPWM0_HRC1_PL_PSL1_Pos 1 /*!< HRPWM0_HRC1 PL: PSL1 Position */
\r
13508 #define HRPWM0_HRC1_PL_PSL1_Msk (0x01UL << HRPWM0_HRC1_PL_PSL1_Pos) /*!< HRPWM0_HRC1 PL: PSL1 Mask */
\r
13510 /* ------------------------------ HRPWM0_HRC1_GSEL ------------------------------ */
\r
13511 #define HRPWM0_HRC1_GSEL_C0SS_Pos 0 /*!< HRPWM0_HRC1 GSEL: C0SS Position */
\r
13512 #define HRPWM0_HRC1_GSEL_C0SS_Msk (0x07UL << HRPWM0_HRC1_GSEL_C0SS_Pos) /*!< HRPWM0_HRC1 GSEL: C0SS Mask */
\r
13513 #define HRPWM0_HRC1_GSEL_C0CS_Pos 3 /*!< HRPWM0_HRC1 GSEL: C0CS Position */
\r
13514 #define HRPWM0_HRC1_GSEL_C0CS_Msk (0x07UL << HRPWM0_HRC1_GSEL_C0CS_Pos) /*!< HRPWM0_HRC1 GSEL: C0CS Mask */
\r
13515 #define HRPWM0_HRC1_GSEL_S0M_Pos 6 /*!< HRPWM0_HRC1 GSEL: S0M Position */
\r
13516 #define HRPWM0_HRC1_GSEL_S0M_Msk (0x03UL << HRPWM0_HRC1_GSEL_S0M_Pos) /*!< HRPWM0_HRC1 GSEL: S0M Mask */
\r
13517 #define HRPWM0_HRC1_GSEL_C0M_Pos 8 /*!< HRPWM0_HRC1 GSEL: C0M Position */
\r
13518 #define HRPWM0_HRC1_GSEL_C0M_Msk (0x03UL << HRPWM0_HRC1_GSEL_C0M_Pos) /*!< HRPWM0_HRC1 GSEL: C0M Mask */
\r
13519 #define HRPWM0_HRC1_GSEL_S0ES_Pos 10 /*!< HRPWM0_HRC1 GSEL: S0ES Position */
\r
13520 #define HRPWM0_HRC1_GSEL_S0ES_Msk (0x03UL << HRPWM0_HRC1_GSEL_S0ES_Pos) /*!< HRPWM0_HRC1 GSEL: S0ES Mask */
\r
13521 #define HRPWM0_HRC1_GSEL_C0ES_Pos 12 /*!< HRPWM0_HRC1 GSEL: C0ES Position */
\r
13522 #define HRPWM0_HRC1_GSEL_C0ES_Msk (0x03UL << HRPWM0_HRC1_GSEL_C0ES_Pos) /*!< HRPWM0_HRC1 GSEL: C0ES Mask */
\r
13523 #define HRPWM0_HRC1_GSEL_C1SS_Pos 16 /*!< HRPWM0_HRC1 GSEL: C1SS Position */
\r
13524 #define HRPWM0_HRC1_GSEL_C1SS_Msk (0x07UL << HRPWM0_HRC1_GSEL_C1SS_Pos) /*!< HRPWM0_HRC1 GSEL: C1SS Mask */
\r
13525 #define HRPWM0_HRC1_GSEL_C1CS_Pos 19 /*!< HRPWM0_HRC1 GSEL: C1CS Position */
\r
13526 #define HRPWM0_HRC1_GSEL_C1CS_Msk (0x07UL << HRPWM0_HRC1_GSEL_C1CS_Pos) /*!< HRPWM0_HRC1 GSEL: C1CS Mask */
\r
13527 #define HRPWM0_HRC1_GSEL_S1M_Pos 22 /*!< HRPWM0_HRC1 GSEL: S1M Position */
\r
13528 #define HRPWM0_HRC1_GSEL_S1M_Msk (0x03UL << HRPWM0_HRC1_GSEL_S1M_Pos) /*!< HRPWM0_HRC1 GSEL: S1M Mask */
\r
13529 #define HRPWM0_HRC1_GSEL_C1M_Pos 24 /*!< HRPWM0_HRC1 GSEL: C1M Position */
\r
13530 #define HRPWM0_HRC1_GSEL_C1M_Msk (0x03UL << HRPWM0_HRC1_GSEL_C1M_Pos) /*!< HRPWM0_HRC1 GSEL: C1M Mask */
\r
13531 #define HRPWM0_HRC1_GSEL_S1ES_Pos 26 /*!< HRPWM0_HRC1 GSEL: S1ES Position */
\r
13532 #define HRPWM0_HRC1_GSEL_S1ES_Msk (0x03UL << HRPWM0_HRC1_GSEL_S1ES_Pos) /*!< HRPWM0_HRC1 GSEL: S1ES Mask */
\r
13533 #define HRPWM0_HRC1_GSEL_C1ES_Pos 28 /*!< HRPWM0_HRC1 GSEL: C1ES Position */
\r
13534 #define HRPWM0_HRC1_GSEL_C1ES_Msk (0x03UL << HRPWM0_HRC1_GSEL_C1ES_Pos) /*!< HRPWM0_HRC1 GSEL: C1ES Mask */
\r
13536 /* ------------------------------ HRPWM0_HRC1_TSEL ------------------------------ */
\r
13537 #define HRPWM0_HRC1_TSEL_TSEL0_Pos 0 /*!< HRPWM0_HRC1 TSEL: TSEL0 Position */
\r
13538 #define HRPWM0_HRC1_TSEL_TSEL0_Msk (0x07UL << HRPWM0_HRC1_TSEL_TSEL0_Pos) /*!< HRPWM0_HRC1 TSEL: TSEL0 Mask */
\r
13539 #define HRPWM0_HRC1_TSEL_TSEL1_Pos 3 /*!< HRPWM0_HRC1 TSEL: TSEL1 Position */
\r
13540 #define HRPWM0_HRC1_TSEL_TSEL1_Msk (0x07UL << HRPWM0_HRC1_TSEL_TSEL1_Pos) /*!< HRPWM0_HRC1 TSEL: TSEL1 Mask */
\r
13541 #define HRPWM0_HRC1_TSEL_TS0E_Pos 16 /*!< HRPWM0_HRC1 TSEL: TS0E Position */
\r
13542 #define HRPWM0_HRC1_TSEL_TS0E_Msk (0x01UL << HRPWM0_HRC1_TSEL_TS0E_Pos) /*!< HRPWM0_HRC1 TSEL: TS0E Mask */
\r
13543 #define HRPWM0_HRC1_TSEL_TS1E_Pos 17 /*!< HRPWM0_HRC1 TSEL: TS1E Position */
\r
13544 #define HRPWM0_HRC1_TSEL_TS1E_Msk (0x01UL << HRPWM0_HRC1_TSEL_TS1E_Pos) /*!< HRPWM0_HRC1 TSEL: TS1E Mask */
\r
13546 /* ------------------------------- HRPWM0_HRC1_SC ------------------------------- */
\r
13547 #define HRPWM0_HRC1_SC_ST_Pos 0 /*!< HRPWM0_HRC1 SC: ST Position */
\r
13548 #define HRPWM0_HRC1_SC_ST_Msk (0x01UL << HRPWM0_HRC1_SC_ST_Pos) /*!< HRPWM0_HRC1 SC: ST Mask */
\r
13550 /* ------------------------------- HRPWM0_HRC1_DCR ------------------------------ */
\r
13551 #define HRPWM0_HRC1_DCR_DTRV_Pos 0 /*!< HRPWM0_HRC1 DCR: DTRV Position */
\r
13552 #define HRPWM0_HRC1_DCR_DTRV_Msk (0x0000ffffUL << HRPWM0_HRC1_DCR_DTRV_Pos) /*!< HRPWM0_HRC1 DCR: DTRV Mask */
\r
13554 /* ------------------------------- HRPWM0_HRC1_DCF ------------------------------ */
\r
13555 #define HRPWM0_HRC1_DCF_DTFV_Pos 0 /*!< HRPWM0_HRC1 DCF: DTFV Position */
\r
13556 #define HRPWM0_HRC1_DCF_DTFV_Msk (0x0000ffffUL << HRPWM0_HRC1_DCF_DTFV_Pos) /*!< HRPWM0_HRC1 DCF: DTFV Mask */
\r
13558 /* ------------------------------- HRPWM0_HRC1_CR1 ------------------------------ */
\r
13559 #define HRPWM0_HRC1_CR1_CR1_Pos 0 /*!< HRPWM0_HRC1 CR1: CR1 Position */
\r
13560 #define HRPWM0_HRC1_CR1_CR1_Msk (0x000000ffUL << HRPWM0_HRC1_CR1_CR1_Pos) /*!< HRPWM0_HRC1 CR1: CR1 Mask */
\r
13562 /* ------------------------------- HRPWM0_HRC1_CR2 ------------------------------ */
\r
13563 #define HRPWM0_HRC1_CR2_CR2_Pos 0 /*!< HRPWM0_HRC1 CR2: CR2 Position */
\r
13564 #define HRPWM0_HRC1_CR2_CR2_Msk (0x000000ffUL << HRPWM0_HRC1_CR2_CR2_Pos) /*!< HRPWM0_HRC1 CR2: CR2 Mask */
\r
13566 /* ------------------------------- HRPWM0_HRC1_SSC ------------------------------ */
\r
13567 #define HRPWM0_HRC1_SSC_SST_Pos 0 /*!< HRPWM0_HRC1 SSC: SST Position */
\r
13568 #define HRPWM0_HRC1_SSC_SST_Msk (0x01UL << HRPWM0_HRC1_SSC_SST_Pos) /*!< HRPWM0_HRC1 SSC: SST Mask */
\r
13570 /* ------------------------------ HRPWM0_HRC1_SDCR ------------------------------ */
\r
13571 #define HRPWM0_HRC1_SDCR_SDTRV_Pos 0 /*!< HRPWM0_HRC1 SDCR: SDTRV Position */
\r
13572 #define HRPWM0_HRC1_SDCR_SDTRV_Msk (0x0000ffffUL << HRPWM0_HRC1_SDCR_SDTRV_Pos) /*!< HRPWM0_HRC1 SDCR: SDTRV Mask */
\r
13574 /* ------------------------------ HRPWM0_HRC1_SDCF ------------------------------ */
\r
13575 #define HRPWM0_HRC1_SDCF_SDTFV_Pos 0 /*!< HRPWM0_HRC1 SDCF: SDTFV Position */
\r
13576 #define HRPWM0_HRC1_SDCF_SDTFV_Msk (0x0000ffffUL << HRPWM0_HRC1_SDCF_SDTFV_Pos) /*!< HRPWM0_HRC1 SDCF: SDTFV Mask */
\r
13578 /* ------------------------------ HRPWM0_HRC1_SCR1 ------------------------------ */
\r
13579 #define HRPWM0_HRC1_SCR1_SCR1_Pos 0 /*!< HRPWM0_HRC1 SCR1: SCR1 Position */
\r
13580 #define HRPWM0_HRC1_SCR1_SCR1_Msk (0x000000ffUL << HRPWM0_HRC1_SCR1_SCR1_Pos) /*!< HRPWM0_HRC1 SCR1: SCR1 Mask */
\r
13582 /* ------------------------------ HRPWM0_HRC1_SCR2 ------------------------------ */
\r
13583 #define HRPWM0_HRC1_SCR2_SCR2_Pos 0 /*!< HRPWM0_HRC1 SCR2: SCR2 Position */
\r
13584 #define HRPWM0_HRC1_SCR2_SCR2_Msk (0x000000ffUL << HRPWM0_HRC1_SCR2_SCR2_Pos) /*!< HRPWM0_HRC1 SCR2: SCR2 Mask */
\r
13587 /* ================================================================================ */
\r
13588 /* ================ struct 'HRPWM0_HRC2' Position & Mask ================ */
\r
13589 /* ================================================================================ */
\r
13592 /* ------------------------------- HRPWM0_HRC2_GC ------------------------------- */
\r
13593 #define HRPWM0_HRC2_GC_HRM0_Pos 0 /*!< HRPWM0_HRC2 GC: HRM0 Position */
\r
13594 #define HRPWM0_HRC2_GC_HRM0_Msk (0x03UL << HRPWM0_HRC2_GC_HRM0_Pos) /*!< HRPWM0_HRC2 GC: HRM0 Mask */
\r
13595 #define HRPWM0_HRC2_GC_HRM1_Pos 2 /*!< HRPWM0_HRC2 GC: HRM1 Position */
\r
13596 #define HRPWM0_HRC2_GC_HRM1_Msk (0x03UL << HRPWM0_HRC2_GC_HRM1_Pos) /*!< HRPWM0_HRC2 GC: HRM1 Mask */
\r
13597 #define HRPWM0_HRC2_GC_DTE_Pos 8 /*!< HRPWM0_HRC2 GC: DTE Position */
\r
13598 #define HRPWM0_HRC2_GC_DTE_Msk (0x01UL << HRPWM0_HRC2_GC_DTE_Pos) /*!< HRPWM0_HRC2 GC: DTE Mask */
\r
13599 #define HRPWM0_HRC2_GC_TR0E_Pos 9 /*!< HRPWM0_HRC2 GC: TR0E Position */
\r
13600 #define HRPWM0_HRC2_GC_TR0E_Msk (0x01UL << HRPWM0_HRC2_GC_TR0E_Pos) /*!< HRPWM0_HRC2 GC: TR0E Mask */
\r
13601 #define HRPWM0_HRC2_GC_TR1E_Pos 10 /*!< HRPWM0_HRC2 GC: TR1E Position */
\r
13602 #define HRPWM0_HRC2_GC_TR1E_Msk (0x01UL << HRPWM0_HRC2_GC_TR1E_Pos) /*!< HRPWM0_HRC2 GC: TR1E Mask */
\r
13603 #define HRPWM0_HRC2_GC_STC_Pos 11 /*!< HRPWM0_HRC2 GC: STC Position */
\r
13604 #define HRPWM0_HRC2_GC_STC_Msk (0x01UL << HRPWM0_HRC2_GC_STC_Pos) /*!< HRPWM0_HRC2 GC: STC Mask */
\r
13605 #define HRPWM0_HRC2_GC_DSTC_Pos 12 /*!< HRPWM0_HRC2 GC: DSTC Position */
\r
13606 #define HRPWM0_HRC2_GC_DSTC_Msk (0x01UL << HRPWM0_HRC2_GC_DSTC_Pos) /*!< HRPWM0_HRC2 GC: DSTC Mask */
\r
13607 #define HRPWM0_HRC2_GC_OCS0_Pos 13 /*!< HRPWM0_HRC2 GC: OCS0 Position */
\r
13608 #define HRPWM0_HRC2_GC_OCS0_Msk (0x01UL << HRPWM0_HRC2_GC_OCS0_Pos) /*!< HRPWM0_HRC2 GC: OCS0 Mask */
\r
13609 #define HRPWM0_HRC2_GC_OCS1_Pos 14 /*!< HRPWM0_HRC2 GC: OCS1 Position */
\r
13610 #define HRPWM0_HRC2_GC_OCS1_Msk (0x01UL << HRPWM0_HRC2_GC_OCS1_Pos) /*!< HRPWM0_HRC2 GC: OCS1 Mask */
\r
13611 #define HRPWM0_HRC2_GC_DTUS_Pos 16 /*!< HRPWM0_HRC2 GC: DTUS Position */
\r
13612 #define HRPWM0_HRC2_GC_DTUS_Msk (0x01UL << HRPWM0_HRC2_GC_DTUS_Pos) /*!< HRPWM0_HRC2 GC: DTUS Mask */
\r
13614 /* ------------------------------- HRPWM0_HRC2_PL ------------------------------- */
\r
13615 #define HRPWM0_HRC2_PL_PSL0_Pos 0 /*!< HRPWM0_HRC2 PL: PSL0 Position */
\r
13616 #define HRPWM0_HRC2_PL_PSL0_Msk (0x01UL << HRPWM0_HRC2_PL_PSL0_Pos) /*!< HRPWM0_HRC2 PL: PSL0 Mask */
\r
13617 #define HRPWM0_HRC2_PL_PSL1_Pos 1 /*!< HRPWM0_HRC2 PL: PSL1 Position */
\r
13618 #define HRPWM0_HRC2_PL_PSL1_Msk (0x01UL << HRPWM0_HRC2_PL_PSL1_Pos) /*!< HRPWM0_HRC2 PL: PSL1 Mask */
\r
13620 /* ------------------------------ HRPWM0_HRC2_GSEL ------------------------------ */
\r
13621 #define HRPWM0_HRC2_GSEL_C0SS_Pos 0 /*!< HRPWM0_HRC2 GSEL: C0SS Position */
\r
13622 #define HRPWM0_HRC2_GSEL_C0SS_Msk (0x07UL << HRPWM0_HRC2_GSEL_C0SS_Pos) /*!< HRPWM0_HRC2 GSEL: C0SS Mask */
\r
13623 #define HRPWM0_HRC2_GSEL_C0CS_Pos 3 /*!< HRPWM0_HRC2 GSEL: C0CS Position */
\r
13624 #define HRPWM0_HRC2_GSEL_C0CS_Msk (0x07UL << HRPWM0_HRC2_GSEL_C0CS_Pos) /*!< HRPWM0_HRC2 GSEL: C0CS Mask */
\r
13625 #define HRPWM0_HRC2_GSEL_S0M_Pos 6 /*!< HRPWM0_HRC2 GSEL: S0M Position */
\r
13626 #define HRPWM0_HRC2_GSEL_S0M_Msk (0x03UL << HRPWM0_HRC2_GSEL_S0M_Pos) /*!< HRPWM0_HRC2 GSEL: S0M Mask */
\r
13627 #define HRPWM0_HRC2_GSEL_C0M_Pos 8 /*!< HRPWM0_HRC2 GSEL: C0M Position */
\r
13628 #define HRPWM0_HRC2_GSEL_C0M_Msk (0x03UL << HRPWM0_HRC2_GSEL_C0M_Pos) /*!< HRPWM0_HRC2 GSEL: C0M Mask */
\r
13629 #define HRPWM0_HRC2_GSEL_S0ES_Pos 10 /*!< HRPWM0_HRC2 GSEL: S0ES Position */
\r
13630 #define HRPWM0_HRC2_GSEL_S0ES_Msk (0x03UL << HRPWM0_HRC2_GSEL_S0ES_Pos) /*!< HRPWM0_HRC2 GSEL: S0ES Mask */
\r
13631 #define HRPWM0_HRC2_GSEL_C0ES_Pos 12 /*!< HRPWM0_HRC2 GSEL: C0ES Position */
\r
13632 #define HRPWM0_HRC2_GSEL_C0ES_Msk (0x03UL << HRPWM0_HRC2_GSEL_C0ES_Pos) /*!< HRPWM0_HRC2 GSEL: C0ES Mask */
\r
13633 #define HRPWM0_HRC2_GSEL_C1SS_Pos 16 /*!< HRPWM0_HRC2 GSEL: C1SS Position */
\r
13634 #define HRPWM0_HRC2_GSEL_C1SS_Msk (0x07UL << HRPWM0_HRC2_GSEL_C1SS_Pos) /*!< HRPWM0_HRC2 GSEL: C1SS Mask */
\r
13635 #define HRPWM0_HRC2_GSEL_C1CS_Pos 19 /*!< HRPWM0_HRC2 GSEL: C1CS Position */
\r
13636 #define HRPWM0_HRC2_GSEL_C1CS_Msk (0x07UL << HRPWM0_HRC2_GSEL_C1CS_Pos) /*!< HRPWM0_HRC2 GSEL: C1CS Mask */
\r
13637 #define HRPWM0_HRC2_GSEL_S1M_Pos 22 /*!< HRPWM0_HRC2 GSEL: S1M Position */
\r
13638 #define HRPWM0_HRC2_GSEL_S1M_Msk (0x03UL << HRPWM0_HRC2_GSEL_S1M_Pos) /*!< HRPWM0_HRC2 GSEL: S1M Mask */
\r
13639 #define HRPWM0_HRC2_GSEL_C1M_Pos 24 /*!< HRPWM0_HRC2 GSEL: C1M Position */
\r
13640 #define HRPWM0_HRC2_GSEL_C1M_Msk (0x03UL << HRPWM0_HRC2_GSEL_C1M_Pos) /*!< HRPWM0_HRC2 GSEL: C1M Mask */
\r
13641 #define HRPWM0_HRC2_GSEL_S1ES_Pos 26 /*!< HRPWM0_HRC2 GSEL: S1ES Position */
\r
13642 #define HRPWM0_HRC2_GSEL_S1ES_Msk (0x03UL << HRPWM0_HRC2_GSEL_S1ES_Pos) /*!< HRPWM0_HRC2 GSEL: S1ES Mask */
\r
13643 #define HRPWM0_HRC2_GSEL_C1ES_Pos 28 /*!< HRPWM0_HRC2 GSEL: C1ES Position */
\r
13644 #define HRPWM0_HRC2_GSEL_C1ES_Msk (0x03UL << HRPWM0_HRC2_GSEL_C1ES_Pos) /*!< HRPWM0_HRC2 GSEL: C1ES Mask */
\r
13646 /* ------------------------------ HRPWM0_HRC2_TSEL ------------------------------ */
\r
13647 #define HRPWM0_HRC2_TSEL_TSEL0_Pos 0 /*!< HRPWM0_HRC2 TSEL: TSEL0 Position */
\r
13648 #define HRPWM0_HRC2_TSEL_TSEL0_Msk (0x07UL << HRPWM0_HRC2_TSEL_TSEL0_Pos) /*!< HRPWM0_HRC2 TSEL: TSEL0 Mask */
\r
13649 #define HRPWM0_HRC2_TSEL_TSEL1_Pos 3 /*!< HRPWM0_HRC2 TSEL: TSEL1 Position */
\r
13650 #define HRPWM0_HRC2_TSEL_TSEL1_Msk (0x07UL << HRPWM0_HRC2_TSEL_TSEL1_Pos) /*!< HRPWM0_HRC2 TSEL: TSEL1 Mask */
\r
13651 #define HRPWM0_HRC2_TSEL_TS0E_Pos 16 /*!< HRPWM0_HRC2 TSEL: TS0E Position */
\r
13652 #define HRPWM0_HRC2_TSEL_TS0E_Msk (0x01UL << HRPWM0_HRC2_TSEL_TS0E_Pos) /*!< HRPWM0_HRC2 TSEL: TS0E Mask */
\r
13653 #define HRPWM0_HRC2_TSEL_TS1E_Pos 17 /*!< HRPWM0_HRC2 TSEL: TS1E Position */
\r
13654 #define HRPWM0_HRC2_TSEL_TS1E_Msk (0x01UL << HRPWM0_HRC2_TSEL_TS1E_Pos) /*!< HRPWM0_HRC2 TSEL: TS1E Mask */
\r
13656 /* ------------------------------- HRPWM0_HRC2_SC ------------------------------- */
\r
13657 #define HRPWM0_HRC2_SC_ST_Pos 0 /*!< HRPWM0_HRC2 SC: ST Position */
\r
13658 #define HRPWM0_HRC2_SC_ST_Msk (0x01UL << HRPWM0_HRC2_SC_ST_Pos) /*!< HRPWM0_HRC2 SC: ST Mask */
\r
13660 /* ------------------------------- HRPWM0_HRC2_DCR ------------------------------ */
\r
13661 #define HRPWM0_HRC2_DCR_DTRV_Pos 0 /*!< HRPWM0_HRC2 DCR: DTRV Position */
\r
13662 #define HRPWM0_HRC2_DCR_DTRV_Msk (0x0000ffffUL << HRPWM0_HRC2_DCR_DTRV_Pos) /*!< HRPWM0_HRC2 DCR: DTRV Mask */
\r
13664 /* ------------------------------- HRPWM0_HRC2_DCF ------------------------------ */
\r
13665 #define HRPWM0_HRC2_DCF_DTFV_Pos 0 /*!< HRPWM0_HRC2 DCF: DTFV Position */
\r
13666 #define HRPWM0_HRC2_DCF_DTFV_Msk (0x0000ffffUL << HRPWM0_HRC2_DCF_DTFV_Pos) /*!< HRPWM0_HRC2 DCF: DTFV Mask */
\r
13668 /* ------------------------------- HRPWM0_HRC2_CR1 ------------------------------ */
\r
13669 #define HRPWM0_HRC2_CR1_CR1_Pos 0 /*!< HRPWM0_HRC2 CR1: CR1 Position */
\r
13670 #define HRPWM0_HRC2_CR1_CR1_Msk (0x000000ffUL << HRPWM0_HRC2_CR1_CR1_Pos) /*!< HRPWM0_HRC2 CR1: CR1 Mask */
\r
13672 /* ------------------------------- HRPWM0_HRC2_CR2 ------------------------------ */
\r
13673 #define HRPWM0_HRC2_CR2_CR2_Pos 0 /*!< HRPWM0_HRC2 CR2: CR2 Position */
\r
13674 #define HRPWM0_HRC2_CR2_CR2_Msk (0x000000ffUL << HRPWM0_HRC2_CR2_CR2_Pos) /*!< HRPWM0_HRC2 CR2: CR2 Mask */
\r
13676 /* ------------------------------- HRPWM0_HRC2_SSC ------------------------------ */
\r
13677 #define HRPWM0_HRC2_SSC_SST_Pos 0 /*!< HRPWM0_HRC2 SSC: SST Position */
\r
13678 #define HRPWM0_HRC2_SSC_SST_Msk (0x01UL << HRPWM0_HRC2_SSC_SST_Pos) /*!< HRPWM0_HRC2 SSC: SST Mask */
\r
13680 /* ------------------------------ HRPWM0_HRC2_SDCR ------------------------------ */
\r
13681 #define HRPWM0_HRC2_SDCR_SDTRV_Pos 0 /*!< HRPWM0_HRC2 SDCR: SDTRV Position */
\r
13682 #define HRPWM0_HRC2_SDCR_SDTRV_Msk (0x0000ffffUL << HRPWM0_HRC2_SDCR_SDTRV_Pos) /*!< HRPWM0_HRC2 SDCR: SDTRV Mask */
\r
13684 /* ------------------------------ HRPWM0_HRC2_SDCF ------------------------------ */
\r
13685 #define HRPWM0_HRC2_SDCF_SDTFV_Pos 0 /*!< HRPWM0_HRC2 SDCF: SDTFV Position */
\r
13686 #define HRPWM0_HRC2_SDCF_SDTFV_Msk (0x0000ffffUL << HRPWM0_HRC2_SDCF_SDTFV_Pos) /*!< HRPWM0_HRC2 SDCF: SDTFV Mask */
\r
13688 /* ------------------------------ HRPWM0_HRC2_SCR1 ------------------------------ */
\r
13689 #define HRPWM0_HRC2_SCR1_SCR1_Pos 0 /*!< HRPWM0_HRC2 SCR1: SCR1 Position */
\r
13690 #define HRPWM0_HRC2_SCR1_SCR1_Msk (0x000000ffUL << HRPWM0_HRC2_SCR1_SCR1_Pos) /*!< HRPWM0_HRC2 SCR1: SCR1 Mask */
\r
13692 /* ------------------------------ HRPWM0_HRC2_SCR2 ------------------------------ */
\r
13693 #define HRPWM0_HRC2_SCR2_SCR2_Pos 0 /*!< HRPWM0_HRC2 SCR2: SCR2 Position */
\r
13694 #define HRPWM0_HRC2_SCR2_SCR2_Msk (0x000000ffUL << HRPWM0_HRC2_SCR2_SCR2_Pos) /*!< HRPWM0_HRC2 SCR2: SCR2 Mask */
\r
13697 /* ================================================================================ */
\r
13698 /* ================ struct 'HRPWM0_HRC3' Position & Mask ================ */
\r
13699 /* ================================================================================ */
\r
13702 /* ------------------------------- HRPWM0_HRC3_GC ------------------------------- */
\r
13703 #define HRPWM0_HRC3_GC_HRM0_Pos 0 /*!< HRPWM0_HRC3 GC: HRM0 Position */
\r
13704 #define HRPWM0_HRC3_GC_HRM0_Msk (0x03UL << HRPWM0_HRC3_GC_HRM0_Pos) /*!< HRPWM0_HRC3 GC: HRM0 Mask */
\r
13705 #define HRPWM0_HRC3_GC_HRM1_Pos 2 /*!< HRPWM0_HRC3 GC: HRM1 Position */
\r
13706 #define HRPWM0_HRC3_GC_HRM1_Msk (0x03UL << HRPWM0_HRC3_GC_HRM1_Pos) /*!< HRPWM0_HRC3 GC: HRM1 Mask */
\r
13707 #define HRPWM0_HRC3_GC_DTE_Pos 8 /*!< HRPWM0_HRC3 GC: DTE Position */
\r
13708 #define HRPWM0_HRC3_GC_DTE_Msk (0x01UL << HRPWM0_HRC3_GC_DTE_Pos) /*!< HRPWM0_HRC3 GC: DTE Mask */
\r
13709 #define HRPWM0_HRC3_GC_TR0E_Pos 9 /*!< HRPWM0_HRC3 GC: TR0E Position */
\r
13710 #define HRPWM0_HRC3_GC_TR0E_Msk (0x01UL << HRPWM0_HRC3_GC_TR0E_Pos) /*!< HRPWM0_HRC3 GC: TR0E Mask */
\r
13711 #define HRPWM0_HRC3_GC_TR1E_Pos 10 /*!< HRPWM0_HRC3 GC: TR1E Position */
\r
13712 #define HRPWM0_HRC3_GC_TR1E_Msk (0x01UL << HRPWM0_HRC3_GC_TR1E_Pos) /*!< HRPWM0_HRC3 GC: TR1E Mask */
\r
13713 #define HRPWM0_HRC3_GC_STC_Pos 11 /*!< HRPWM0_HRC3 GC: STC Position */
\r
13714 #define HRPWM0_HRC3_GC_STC_Msk (0x01UL << HRPWM0_HRC3_GC_STC_Pos) /*!< HRPWM0_HRC3 GC: STC Mask */
\r
13715 #define HRPWM0_HRC3_GC_DSTC_Pos 12 /*!< HRPWM0_HRC3 GC: DSTC Position */
\r
13716 #define HRPWM0_HRC3_GC_DSTC_Msk (0x01UL << HRPWM0_HRC3_GC_DSTC_Pos) /*!< HRPWM0_HRC3 GC: DSTC Mask */
\r
13717 #define HRPWM0_HRC3_GC_OCS0_Pos 13 /*!< HRPWM0_HRC3 GC: OCS0 Position */
\r
13718 #define HRPWM0_HRC3_GC_OCS0_Msk (0x01UL << HRPWM0_HRC3_GC_OCS0_Pos) /*!< HRPWM0_HRC3 GC: OCS0 Mask */
\r
13719 #define HRPWM0_HRC3_GC_OCS1_Pos 14 /*!< HRPWM0_HRC3 GC: OCS1 Position */
\r
13720 #define HRPWM0_HRC3_GC_OCS1_Msk (0x01UL << HRPWM0_HRC3_GC_OCS1_Pos) /*!< HRPWM0_HRC3 GC: OCS1 Mask */
\r
13721 #define HRPWM0_HRC3_GC_DTUS_Pos 16 /*!< HRPWM0_HRC3 GC: DTUS Position */
\r
13722 #define HRPWM0_HRC3_GC_DTUS_Msk (0x01UL << HRPWM0_HRC3_GC_DTUS_Pos) /*!< HRPWM0_HRC3 GC: DTUS Mask */
\r
13724 /* ------------------------------- HRPWM0_HRC3_PL ------------------------------- */
\r
13725 #define HRPWM0_HRC3_PL_PSL0_Pos 0 /*!< HRPWM0_HRC3 PL: PSL0 Position */
\r
13726 #define HRPWM0_HRC3_PL_PSL0_Msk (0x01UL << HRPWM0_HRC3_PL_PSL0_Pos) /*!< HRPWM0_HRC3 PL: PSL0 Mask */
\r
13727 #define HRPWM0_HRC3_PL_PSL1_Pos 1 /*!< HRPWM0_HRC3 PL: PSL1 Position */
\r
13728 #define HRPWM0_HRC3_PL_PSL1_Msk (0x01UL << HRPWM0_HRC3_PL_PSL1_Pos) /*!< HRPWM0_HRC3 PL: PSL1 Mask */
\r
13730 /* ------------------------------ HRPWM0_HRC3_GSEL ------------------------------ */
\r
13731 #define HRPWM0_HRC3_GSEL_C0SS_Pos 0 /*!< HRPWM0_HRC3 GSEL: C0SS Position */
\r
13732 #define HRPWM0_HRC3_GSEL_C0SS_Msk (0x07UL << HRPWM0_HRC3_GSEL_C0SS_Pos) /*!< HRPWM0_HRC3 GSEL: C0SS Mask */
\r
13733 #define HRPWM0_HRC3_GSEL_C0CS_Pos 3 /*!< HRPWM0_HRC3 GSEL: C0CS Position */
\r
13734 #define HRPWM0_HRC3_GSEL_C0CS_Msk (0x07UL << HRPWM0_HRC3_GSEL_C0CS_Pos) /*!< HRPWM0_HRC3 GSEL: C0CS Mask */
\r
13735 #define HRPWM0_HRC3_GSEL_S0M_Pos 6 /*!< HRPWM0_HRC3 GSEL: S0M Position */
\r
13736 #define HRPWM0_HRC3_GSEL_S0M_Msk (0x03UL << HRPWM0_HRC3_GSEL_S0M_Pos) /*!< HRPWM0_HRC3 GSEL: S0M Mask */
\r
13737 #define HRPWM0_HRC3_GSEL_C0M_Pos 8 /*!< HRPWM0_HRC3 GSEL: C0M Position */
\r
13738 #define HRPWM0_HRC3_GSEL_C0M_Msk (0x03UL << HRPWM0_HRC3_GSEL_C0M_Pos) /*!< HRPWM0_HRC3 GSEL: C0M Mask */
\r
13739 #define HRPWM0_HRC3_GSEL_S0ES_Pos 10 /*!< HRPWM0_HRC3 GSEL: S0ES Position */
\r
13740 #define HRPWM0_HRC3_GSEL_S0ES_Msk (0x03UL << HRPWM0_HRC3_GSEL_S0ES_Pos) /*!< HRPWM0_HRC3 GSEL: S0ES Mask */
\r
13741 #define HRPWM0_HRC3_GSEL_C0ES_Pos 12 /*!< HRPWM0_HRC3 GSEL: C0ES Position */
\r
13742 #define HRPWM0_HRC3_GSEL_C0ES_Msk (0x03UL << HRPWM0_HRC3_GSEL_C0ES_Pos) /*!< HRPWM0_HRC3 GSEL: C0ES Mask */
\r
13743 #define HRPWM0_HRC3_GSEL_C1SS_Pos 16 /*!< HRPWM0_HRC3 GSEL: C1SS Position */
\r
13744 #define HRPWM0_HRC3_GSEL_C1SS_Msk (0x07UL << HRPWM0_HRC3_GSEL_C1SS_Pos) /*!< HRPWM0_HRC3 GSEL: C1SS Mask */
\r
13745 #define HRPWM0_HRC3_GSEL_C1CS_Pos 19 /*!< HRPWM0_HRC3 GSEL: C1CS Position */
\r
13746 #define HRPWM0_HRC3_GSEL_C1CS_Msk (0x07UL << HRPWM0_HRC3_GSEL_C1CS_Pos) /*!< HRPWM0_HRC3 GSEL: C1CS Mask */
\r
13747 #define HRPWM0_HRC3_GSEL_S1M_Pos 22 /*!< HRPWM0_HRC3 GSEL: S1M Position */
\r
13748 #define HRPWM0_HRC3_GSEL_S1M_Msk (0x03UL << HRPWM0_HRC3_GSEL_S1M_Pos) /*!< HRPWM0_HRC3 GSEL: S1M Mask */
\r
13749 #define HRPWM0_HRC3_GSEL_C1M_Pos 24 /*!< HRPWM0_HRC3 GSEL: C1M Position */
\r
13750 #define HRPWM0_HRC3_GSEL_C1M_Msk (0x03UL << HRPWM0_HRC3_GSEL_C1M_Pos) /*!< HRPWM0_HRC3 GSEL: C1M Mask */
\r
13751 #define HRPWM0_HRC3_GSEL_S1ES_Pos 26 /*!< HRPWM0_HRC3 GSEL: S1ES Position */
\r
13752 #define HRPWM0_HRC3_GSEL_S1ES_Msk (0x03UL << HRPWM0_HRC3_GSEL_S1ES_Pos) /*!< HRPWM0_HRC3 GSEL: S1ES Mask */
\r
13753 #define HRPWM0_HRC3_GSEL_C1ES_Pos 28 /*!< HRPWM0_HRC3 GSEL: C1ES Position */
\r
13754 #define HRPWM0_HRC3_GSEL_C1ES_Msk (0x03UL << HRPWM0_HRC3_GSEL_C1ES_Pos) /*!< HRPWM0_HRC3 GSEL: C1ES Mask */
\r
13756 /* ------------------------------ HRPWM0_HRC3_TSEL ------------------------------ */
\r
13757 #define HRPWM0_HRC3_TSEL_TSEL0_Pos 0 /*!< HRPWM0_HRC3 TSEL: TSEL0 Position */
\r
13758 #define HRPWM0_HRC3_TSEL_TSEL0_Msk (0x07UL << HRPWM0_HRC3_TSEL_TSEL0_Pos) /*!< HRPWM0_HRC3 TSEL: TSEL0 Mask */
\r
13759 #define HRPWM0_HRC3_TSEL_TSEL1_Pos 3 /*!< HRPWM0_HRC3 TSEL: TSEL1 Position */
\r
13760 #define HRPWM0_HRC3_TSEL_TSEL1_Msk (0x07UL << HRPWM0_HRC3_TSEL_TSEL1_Pos) /*!< HRPWM0_HRC3 TSEL: TSEL1 Mask */
\r
13761 #define HRPWM0_HRC3_TSEL_TS0E_Pos 16 /*!< HRPWM0_HRC3 TSEL: TS0E Position */
\r
13762 #define HRPWM0_HRC3_TSEL_TS0E_Msk (0x01UL << HRPWM0_HRC3_TSEL_TS0E_Pos) /*!< HRPWM0_HRC3 TSEL: TS0E Mask */
\r
13763 #define HRPWM0_HRC3_TSEL_TS1E_Pos 17 /*!< HRPWM0_HRC3 TSEL: TS1E Position */
\r
13764 #define HRPWM0_HRC3_TSEL_TS1E_Msk (0x01UL << HRPWM0_HRC3_TSEL_TS1E_Pos) /*!< HRPWM0_HRC3 TSEL: TS1E Mask */
\r
13766 /* ------------------------------- HRPWM0_HRC3_SC ------------------------------- */
\r
13767 #define HRPWM0_HRC3_SC_ST_Pos 0 /*!< HRPWM0_HRC3 SC: ST Position */
\r
13768 #define HRPWM0_HRC3_SC_ST_Msk (0x01UL << HRPWM0_HRC3_SC_ST_Pos) /*!< HRPWM0_HRC3 SC: ST Mask */
\r
13770 /* ------------------------------- HRPWM0_HRC3_DCR ------------------------------ */
\r
13771 #define HRPWM0_HRC3_DCR_DTRV_Pos 0 /*!< HRPWM0_HRC3 DCR: DTRV Position */
\r
13772 #define HRPWM0_HRC3_DCR_DTRV_Msk (0x0000ffffUL << HRPWM0_HRC3_DCR_DTRV_Pos) /*!< HRPWM0_HRC3 DCR: DTRV Mask */
\r
13774 /* ------------------------------- HRPWM0_HRC3_DCF ------------------------------ */
\r
13775 #define HRPWM0_HRC3_DCF_DTFV_Pos 0 /*!< HRPWM0_HRC3 DCF: DTFV Position */
\r
13776 #define HRPWM0_HRC3_DCF_DTFV_Msk (0x0000ffffUL << HRPWM0_HRC3_DCF_DTFV_Pos) /*!< HRPWM0_HRC3 DCF: DTFV Mask */
\r
13778 /* ------------------------------- HRPWM0_HRC3_CR1 ------------------------------ */
\r
13779 #define HRPWM0_HRC3_CR1_CR1_Pos 0 /*!< HRPWM0_HRC3 CR1: CR1 Position */
\r
13780 #define HRPWM0_HRC3_CR1_CR1_Msk (0x000000ffUL << HRPWM0_HRC3_CR1_CR1_Pos) /*!< HRPWM0_HRC3 CR1: CR1 Mask */
\r
13782 /* ------------------------------- HRPWM0_HRC3_CR2 ------------------------------ */
\r
13783 #define HRPWM0_HRC3_CR2_CR2_Pos 0 /*!< HRPWM0_HRC3 CR2: CR2 Position */
\r
13784 #define HRPWM0_HRC3_CR2_CR2_Msk (0x000000ffUL << HRPWM0_HRC3_CR2_CR2_Pos) /*!< HRPWM0_HRC3 CR2: CR2 Mask */
\r
13786 /* ------------------------------- HRPWM0_HRC3_SSC ------------------------------ */
\r
13787 #define HRPWM0_HRC3_SSC_SST_Pos 0 /*!< HRPWM0_HRC3 SSC: SST Position */
\r
13788 #define HRPWM0_HRC3_SSC_SST_Msk (0x01UL << HRPWM0_HRC3_SSC_SST_Pos) /*!< HRPWM0_HRC3 SSC: SST Mask */
\r
13790 /* ------------------------------ HRPWM0_HRC3_SDCR ------------------------------ */
\r
13791 #define HRPWM0_HRC3_SDCR_SDTRV_Pos 0 /*!< HRPWM0_HRC3 SDCR: SDTRV Position */
\r
13792 #define HRPWM0_HRC3_SDCR_SDTRV_Msk (0x0000ffffUL << HRPWM0_HRC3_SDCR_SDTRV_Pos) /*!< HRPWM0_HRC3 SDCR: SDTRV Mask */
\r
13794 /* ------------------------------ HRPWM0_HRC3_SDCF ------------------------------ */
\r
13795 #define HRPWM0_HRC3_SDCF_SDTFV_Pos 0 /*!< HRPWM0_HRC3 SDCF: SDTFV Position */
\r
13796 #define HRPWM0_HRC3_SDCF_SDTFV_Msk (0x0000ffffUL << HRPWM0_HRC3_SDCF_SDTFV_Pos) /*!< HRPWM0_HRC3 SDCF: SDTFV Mask */
\r
13798 /* ------------------------------ HRPWM0_HRC3_SCR1 ------------------------------ */
\r
13799 #define HRPWM0_HRC3_SCR1_SCR1_Pos 0 /*!< HRPWM0_HRC3 SCR1: SCR1 Position */
\r
13800 #define HRPWM0_HRC3_SCR1_SCR1_Msk (0x000000ffUL << HRPWM0_HRC3_SCR1_SCR1_Pos) /*!< HRPWM0_HRC3 SCR1: SCR1 Mask */
\r
13802 /* ------------------------------ HRPWM0_HRC3_SCR2 ------------------------------ */
\r
13803 #define HRPWM0_HRC3_SCR2_SCR2_Pos 0 /*!< HRPWM0_HRC3 SCR2: SCR2 Position */
\r
13804 #define HRPWM0_HRC3_SCR2_SCR2_Msk (0x000000ffUL << HRPWM0_HRC3_SCR2_SCR2_Pos) /*!< HRPWM0_HRC3 SCR2: SCR2 Mask */
\r
13807 /* ================================================================================ */
\r
13808 /* ================ Group 'POSIF' Position & Mask ================ */
\r
13809 /* ================================================================================ */
\r
13812 /* --------------------------------- POSIF_PCONF -------------------------------- */
\r
13813 #define POSIF_PCONF_FSEL_Pos 0 /*!< POSIF PCONF: FSEL Position */
\r
13814 #define POSIF_PCONF_FSEL_Msk (0x03UL << POSIF_PCONF_FSEL_Pos) /*!< POSIF PCONF: FSEL Mask */
\r
13815 #define POSIF_PCONF_QDCM_Pos 2 /*!< POSIF PCONF: QDCM Position */
\r
13816 #define POSIF_PCONF_QDCM_Msk (0x01UL << POSIF_PCONF_QDCM_Pos) /*!< POSIF PCONF: QDCM Mask */
\r
13817 #define POSIF_PCONF_HIDG_Pos 4 /*!< POSIF PCONF: HIDG Position */
\r
13818 #define POSIF_PCONF_HIDG_Msk (0x01UL << POSIF_PCONF_HIDG_Pos) /*!< POSIF PCONF: HIDG Mask */
\r
13819 #define POSIF_PCONF_MCUE_Pos 5 /*!< POSIF PCONF: MCUE Position */
\r
13820 #define POSIF_PCONF_MCUE_Msk (0x01UL << POSIF_PCONF_MCUE_Pos) /*!< POSIF PCONF: MCUE Mask */
\r
13821 #define POSIF_PCONF_INSEL0_Pos 8 /*!< POSIF PCONF: INSEL0 Position */
\r
13822 #define POSIF_PCONF_INSEL0_Msk (0x03UL << POSIF_PCONF_INSEL0_Pos) /*!< POSIF PCONF: INSEL0 Mask */
\r
13823 #define POSIF_PCONF_INSEL1_Pos 10 /*!< POSIF PCONF: INSEL1 Position */
\r
13824 #define POSIF_PCONF_INSEL1_Msk (0x03UL << POSIF_PCONF_INSEL1_Pos) /*!< POSIF PCONF: INSEL1 Mask */
\r
13825 #define POSIF_PCONF_INSEL2_Pos 12 /*!< POSIF PCONF: INSEL2 Position */
\r
13826 #define POSIF_PCONF_INSEL2_Msk (0x03UL << POSIF_PCONF_INSEL2_Pos) /*!< POSIF PCONF: INSEL2 Mask */
\r
13827 #define POSIF_PCONF_DSEL_Pos 16 /*!< POSIF PCONF: DSEL Position */
\r
13828 #define POSIF_PCONF_DSEL_Msk (0x01UL << POSIF_PCONF_DSEL_Pos) /*!< POSIF PCONF: DSEL Mask */
\r
13829 #define POSIF_PCONF_SPES_Pos 17 /*!< POSIF PCONF: SPES Position */
\r
13830 #define POSIF_PCONF_SPES_Msk (0x01UL << POSIF_PCONF_SPES_Pos) /*!< POSIF PCONF: SPES Mask */
\r
13831 #define POSIF_PCONF_MSETS_Pos 18 /*!< POSIF PCONF: MSETS Position */
\r
13832 #define POSIF_PCONF_MSETS_Msk (0x07UL << POSIF_PCONF_MSETS_Pos) /*!< POSIF PCONF: MSETS Mask */
\r
13833 #define POSIF_PCONF_MSES_Pos 21 /*!< POSIF PCONF: MSES Position */
\r
13834 #define POSIF_PCONF_MSES_Msk (0x01UL << POSIF_PCONF_MSES_Pos) /*!< POSIF PCONF: MSES Mask */
\r
13835 #define POSIF_PCONF_MSYNS_Pos 22 /*!< POSIF PCONF: MSYNS Position */
\r
13836 #define POSIF_PCONF_MSYNS_Msk (0x03UL << POSIF_PCONF_MSYNS_Pos) /*!< POSIF PCONF: MSYNS Mask */
\r
13837 #define POSIF_PCONF_EWIS_Pos 24 /*!< POSIF PCONF: EWIS Position */
\r
13838 #define POSIF_PCONF_EWIS_Msk (0x03UL << POSIF_PCONF_EWIS_Pos) /*!< POSIF PCONF: EWIS Mask */
\r
13839 #define POSIF_PCONF_EWIE_Pos 26 /*!< POSIF PCONF: EWIE Position */
\r
13840 #define POSIF_PCONF_EWIE_Msk (0x01UL << POSIF_PCONF_EWIE_Pos) /*!< POSIF PCONF: EWIE Mask */
\r
13841 #define POSIF_PCONF_EWIL_Pos 27 /*!< POSIF PCONF: EWIL Position */
\r
13842 #define POSIF_PCONF_EWIL_Msk (0x01UL << POSIF_PCONF_EWIL_Pos) /*!< POSIF PCONF: EWIL Mask */
\r
13843 #define POSIF_PCONF_LPC_Pos 28 /*!< POSIF PCONF: LPC Position */
\r
13844 #define POSIF_PCONF_LPC_Msk (0x07UL << POSIF_PCONF_LPC_Pos) /*!< POSIF PCONF: LPC Mask */
\r
13846 /* --------------------------------- POSIF_PSUS --------------------------------- */
\r
13847 #define POSIF_PSUS_QSUS_Pos 0 /*!< POSIF PSUS: QSUS Position */
\r
13848 #define POSIF_PSUS_QSUS_Msk (0x03UL << POSIF_PSUS_QSUS_Pos) /*!< POSIF PSUS: QSUS Mask */
\r
13849 #define POSIF_PSUS_MSUS_Pos 2 /*!< POSIF PSUS: MSUS Position */
\r
13850 #define POSIF_PSUS_MSUS_Msk (0x03UL << POSIF_PSUS_MSUS_Pos) /*!< POSIF PSUS: MSUS Mask */
\r
13852 /* --------------------------------- POSIF_PRUNS -------------------------------- */
\r
13853 #define POSIF_PRUNS_SRB_Pos 0 /*!< POSIF PRUNS: SRB Position */
\r
13854 #define POSIF_PRUNS_SRB_Msk (0x01UL << POSIF_PRUNS_SRB_Pos) /*!< POSIF PRUNS: SRB Mask */
\r
13856 /* --------------------------------- POSIF_PRUNC -------------------------------- */
\r
13857 #define POSIF_PRUNC_CRB_Pos 0 /*!< POSIF PRUNC: CRB Position */
\r
13858 #define POSIF_PRUNC_CRB_Msk (0x01UL << POSIF_PRUNC_CRB_Pos) /*!< POSIF PRUNC: CRB Mask */
\r
13859 #define POSIF_PRUNC_CSM_Pos 1 /*!< POSIF PRUNC: CSM Position */
\r
13860 #define POSIF_PRUNC_CSM_Msk (0x01UL << POSIF_PRUNC_CSM_Pos) /*!< POSIF PRUNC: CSM Mask */
\r
13862 /* --------------------------------- POSIF_PRUN --------------------------------- */
\r
13863 #define POSIF_PRUN_RB_Pos 0 /*!< POSIF PRUN: RB Position */
\r
13864 #define POSIF_PRUN_RB_Msk (0x01UL << POSIF_PRUN_RB_Pos) /*!< POSIF PRUN: RB Mask */
\r
13866 /* --------------------------------- POSIF_MIDR --------------------------------- */
\r
13867 #define POSIF_MIDR_MODR_Pos 0 /*!< POSIF MIDR: MODR Position */
\r
13868 #define POSIF_MIDR_MODR_Msk (0x000000ffUL << POSIF_MIDR_MODR_Pos) /*!< POSIF MIDR: MODR Mask */
\r
13869 #define POSIF_MIDR_MODT_Pos 8 /*!< POSIF MIDR: MODT Position */
\r
13870 #define POSIF_MIDR_MODT_Msk (0x000000ffUL << POSIF_MIDR_MODT_Pos) /*!< POSIF MIDR: MODT Mask */
\r
13871 #define POSIF_MIDR_MODN_Pos 16 /*!< POSIF MIDR: MODN Position */
\r
13872 #define POSIF_MIDR_MODN_Msk (0x0000ffffUL << POSIF_MIDR_MODN_Pos) /*!< POSIF MIDR: MODN Mask */
\r
13874 /* --------------------------------- POSIF_HALP --------------------------------- */
\r
13875 #define POSIF_HALP_HCP_Pos 0 /*!< POSIF HALP: HCP Position */
\r
13876 #define POSIF_HALP_HCP_Msk (0x07UL << POSIF_HALP_HCP_Pos) /*!< POSIF HALP: HCP Mask */
\r
13877 #define POSIF_HALP_HEP_Pos 3 /*!< POSIF HALP: HEP Position */
\r
13878 #define POSIF_HALP_HEP_Msk (0x07UL << POSIF_HALP_HEP_Pos) /*!< POSIF HALP: HEP Mask */
\r
13880 /* --------------------------------- POSIF_HALPS -------------------------------- */
\r
13881 #define POSIF_HALPS_HCPS_Pos 0 /*!< POSIF HALPS: HCPS Position */
\r
13882 #define POSIF_HALPS_HCPS_Msk (0x07UL << POSIF_HALPS_HCPS_Pos) /*!< POSIF HALPS: HCPS Mask */
\r
13883 #define POSIF_HALPS_HEPS_Pos 3 /*!< POSIF HALPS: HEPS Position */
\r
13884 #define POSIF_HALPS_HEPS_Msk (0x07UL << POSIF_HALPS_HEPS_Pos) /*!< POSIF HALPS: HEPS Mask */
\r
13886 /* ---------------------------------- POSIF_MCM --------------------------------- */
\r
13887 #define POSIF_MCM_MCMP_Pos 0 /*!< POSIF MCM: MCMP Position */
\r
13888 #define POSIF_MCM_MCMP_Msk (0x0000ffffUL << POSIF_MCM_MCMP_Pos) /*!< POSIF MCM: MCMP Mask */
\r
13890 /* --------------------------------- POSIF_MCSM --------------------------------- */
\r
13891 #define POSIF_MCSM_MCMPS_Pos 0 /*!< POSIF MCSM: MCMPS Position */
\r
13892 #define POSIF_MCSM_MCMPS_Msk (0x0000ffffUL << POSIF_MCSM_MCMPS_Pos) /*!< POSIF MCSM: MCMPS Mask */
\r
13894 /* --------------------------------- POSIF_MCMS --------------------------------- */
\r
13895 #define POSIF_MCMS_MNPS_Pos 0 /*!< POSIF MCMS: MNPS Position */
\r
13896 #define POSIF_MCMS_MNPS_Msk (0x01UL << POSIF_MCMS_MNPS_Pos) /*!< POSIF MCMS: MNPS Mask */
\r
13897 #define POSIF_MCMS_STHR_Pos 1 /*!< POSIF MCMS: STHR Position */
\r
13898 #define POSIF_MCMS_STHR_Msk (0x01UL << POSIF_MCMS_STHR_Pos) /*!< POSIF MCMS: STHR Mask */
\r
13899 #define POSIF_MCMS_STMR_Pos 2 /*!< POSIF MCMS: STMR Position */
\r
13900 #define POSIF_MCMS_STMR_Msk (0x01UL << POSIF_MCMS_STMR_Pos) /*!< POSIF MCMS: STMR Mask */
\r
13902 /* --------------------------------- POSIF_MCMC --------------------------------- */
\r
13903 #define POSIF_MCMC_MNPC_Pos 0 /*!< POSIF MCMC: MNPC Position */
\r
13904 #define POSIF_MCMC_MNPC_Msk (0x01UL << POSIF_MCMC_MNPC_Pos) /*!< POSIF MCMC: MNPC Mask */
\r
13905 #define POSIF_MCMC_MPC_Pos 1 /*!< POSIF MCMC: MPC Position */
\r
13906 #define POSIF_MCMC_MPC_Msk (0x01UL << POSIF_MCMC_MPC_Pos) /*!< POSIF MCMC: MPC Mask */
\r
13908 /* --------------------------------- POSIF_MCMF --------------------------------- */
\r
13909 #define POSIF_MCMF_MSS_Pos 0 /*!< POSIF MCMF: MSS Position */
\r
13910 #define POSIF_MCMF_MSS_Msk (0x01UL << POSIF_MCMF_MSS_Pos) /*!< POSIF MCMF: MSS Mask */
\r
13912 /* ---------------------------------- POSIF_QDC --------------------------------- */
\r
13913 #define POSIF_QDC_PALS_Pos 0 /*!< POSIF QDC: PALS Position */
\r
13914 #define POSIF_QDC_PALS_Msk (0x01UL << POSIF_QDC_PALS_Pos) /*!< POSIF QDC: PALS Mask */
\r
13915 #define POSIF_QDC_PBLS_Pos 1 /*!< POSIF QDC: PBLS Position */
\r
13916 #define POSIF_QDC_PBLS_Msk (0x01UL << POSIF_QDC_PBLS_Pos) /*!< POSIF QDC: PBLS Mask */
\r
13917 #define POSIF_QDC_PHS_Pos 2 /*!< POSIF QDC: PHS Position */
\r
13918 #define POSIF_QDC_PHS_Msk (0x01UL << POSIF_QDC_PHS_Pos) /*!< POSIF QDC: PHS Mask */
\r
13919 #define POSIF_QDC_ICM_Pos 4 /*!< POSIF QDC: ICM Position */
\r
13920 #define POSIF_QDC_ICM_Msk (0x03UL << POSIF_QDC_ICM_Pos) /*!< POSIF QDC: ICM Mask */
\r
13921 #define POSIF_QDC_DVAL_Pos 8 /*!< POSIF QDC: DVAL Position */
\r
13922 #define POSIF_QDC_DVAL_Msk (0x01UL << POSIF_QDC_DVAL_Pos) /*!< POSIF QDC: DVAL Mask */
\r
13924 /* --------------------------------- POSIF_PFLG --------------------------------- */
\r
13925 #define POSIF_PFLG_CHES_Pos 0 /*!< POSIF PFLG: CHES Position */
\r
13926 #define POSIF_PFLG_CHES_Msk (0x01UL << POSIF_PFLG_CHES_Pos) /*!< POSIF PFLG: CHES Mask */
\r
13927 #define POSIF_PFLG_WHES_Pos 1 /*!< POSIF PFLG: WHES Position */
\r
13928 #define POSIF_PFLG_WHES_Msk (0x01UL << POSIF_PFLG_WHES_Pos) /*!< POSIF PFLG: WHES Mask */
\r
13929 #define POSIF_PFLG_HIES_Pos 2 /*!< POSIF PFLG: HIES Position */
\r
13930 #define POSIF_PFLG_HIES_Msk (0x01UL << POSIF_PFLG_HIES_Pos) /*!< POSIF PFLG: HIES Mask */
\r
13931 #define POSIF_PFLG_MSTS_Pos 4 /*!< POSIF PFLG: MSTS Position */
\r
13932 #define POSIF_PFLG_MSTS_Msk (0x01UL << POSIF_PFLG_MSTS_Pos) /*!< POSIF PFLG: MSTS Mask */
\r
13933 #define POSIF_PFLG_INDXS_Pos 8 /*!< POSIF PFLG: INDXS Position */
\r
13934 #define POSIF_PFLG_INDXS_Msk (0x01UL << POSIF_PFLG_INDXS_Pos) /*!< POSIF PFLG: INDXS Mask */
\r
13935 #define POSIF_PFLG_ERRS_Pos 9 /*!< POSIF PFLG: ERRS Position */
\r
13936 #define POSIF_PFLG_ERRS_Msk (0x01UL << POSIF_PFLG_ERRS_Pos) /*!< POSIF PFLG: ERRS Mask */
\r
13937 #define POSIF_PFLG_CNTS_Pos 10 /*!< POSIF PFLG: CNTS Position */
\r
13938 #define POSIF_PFLG_CNTS_Msk (0x01UL << POSIF_PFLG_CNTS_Pos) /*!< POSIF PFLG: CNTS Mask */
\r
13939 #define POSIF_PFLG_DIRS_Pos 11 /*!< POSIF PFLG: DIRS Position */
\r
13940 #define POSIF_PFLG_DIRS_Msk (0x01UL << POSIF_PFLG_DIRS_Pos) /*!< POSIF PFLG: DIRS Mask */
\r
13941 #define POSIF_PFLG_PCLKS_Pos 12 /*!< POSIF PFLG: PCLKS Position */
\r
13942 #define POSIF_PFLG_PCLKS_Msk (0x01UL << POSIF_PFLG_PCLKS_Pos) /*!< POSIF PFLG: PCLKS Mask */
\r
13944 /* --------------------------------- POSIF_PFLGE -------------------------------- */
\r
13945 #define POSIF_PFLGE_ECHE_Pos 0 /*!< POSIF PFLGE: ECHE Position */
\r
13946 #define POSIF_PFLGE_ECHE_Msk (0x01UL << POSIF_PFLGE_ECHE_Pos) /*!< POSIF PFLGE: ECHE Mask */
\r
13947 #define POSIF_PFLGE_EWHE_Pos 1 /*!< POSIF PFLGE: EWHE Position */
\r
13948 #define POSIF_PFLGE_EWHE_Msk (0x01UL << POSIF_PFLGE_EWHE_Pos) /*!< POSIF PFLGE: EWHE Mask */
\r
13949 #define POSIF_PFLGE_EHIE_Pos 2 /*!< POSIF PFLGE: EHIE Position */
\r
13950 #define POSIF_PFLGE_EHIE_Msk (0x01UL << POSIF_PFLGE_EHIE_Pos) /*!< POSIF PFLGE: EHIE Mask */
\r
13951 #define POSIF_PFLGE_EMST_Pos 4 /*!< POSIF PFLGE: EMST Position */
\r
13952 #define POSIF_PFLGE_EMST_Msk (0x01UL << POSIF_PFLGE_EMST_Pos) /*!< POSIF PFLGE: EMST Mask */
\r
13953 #define POSIF_PFLGE_EINDX_Pos 8 /*!< POSIF PFLGE: EINDX Position */
\r
13954 #define POSIF_PFLGE_EINDX_Msk (0x01UL << POSIF_PFLGE_EINDX_Pos) /*!< POSIF PFLGE: EINDX Mask */
\r
13955 #define POSIF_PFLGE_EERR_Pos 9 /*!< POSIF PFLGE: EERR Position */
\r
13956 #define POSIF_PFLGE_EERR_Msk (0x01UL << POSIF_PFLGE_EERR_Pos) /*!< POSIF PFLGE: EERR Mask */
\r
13957 #define POSIF_PFLGE_ECNT_Pos 10 /*!< POSIF PFLGE: ECNT Position */
\r
13958 #define POSIF_PFLGE_ECNT_Msk (0x01UL << POSIF_PFLGE_ECNT_Pos) /*!< POSIF PFLGE: ECNT Mask */
\r
13959 #define POSIF_PFLGE_EDIR_Pos 11 /*!< POSIF PFLGE: EDIR Position */
\r
13960 #define POSIF_PFLGE_EDIR_Msk (0x01UL << POSIF_PFLGE_EDIR_Pos) /*!< POSIF PFLGE: EDIR Mask */
\r
13961 #define POSIF_PFLGE_EPCLK_Pos 12 /*!< POSIF PFLGE: EPCLK Position */
\r
13962 #define POSIF_PFLGE_EPCLK_Msk (0x01UL << POSIF_PFLGE_EPCLK_Pos) /*!< POSIF PFLGE: EPCLK Mask */
\r
13963 #define POSIF_PFLGE_CHESEL_Pos 16 /*!< POSIF PFLGE: CHESEL Position */
\r
13964 #define POSIF_PFLGE_CHESEL_Msk (0x01UL << POSIF_PFLGE_CHESEL_Pos) /*!< POSIF PFLGE: CHESEL Mask */
\r
13965 #define POSIF_PFLGE_WHESEL_Pos 17 /*!< POSIF PFLGE: WHESEL Position */
\r
13966 #define POSIF_PFLGE_WHESEL_Msk (0x01UL << POSIF_PFLGE_WHESEL_Pos) /*!< POSIF PFLGE: WHESEL Mask */
\r
13967 #define POSIF_PFLGE_HIESEL_Pos 18 /*!< POSIF PFLGE: HIESEL Position */
\r
13968 #define POSIF_PFLGE_HIESEL_Msk (0x01UL << POSIF_PFLGE_HIESEL_Pos) /*!< POSIF PFLGE: HIESEL Mask */
\r
13969 #define POSIF_PFLGE_MSTSEL_Pos 20 /*!< POSIF PFLGE: MSTSEL Position */
\r
13970 #define POSIF_PFLGE_MSTSEL_Msk (0x01UL << POSIF_PFLGE_MSTSEL_Pos) /*!< POSIF PFLGE: MSTSEL Mask */
\r
13971 #define POSIF_PFLGE_INDSEL_Pos 24 /*!< POSIF PFLGE: INDSEL Position */
\r
13972 #define POSIF_PFLGE_INDSEL_Msk (0x01UL << POSIF_PFLGE_INDSEL_Pos) /*!< POSIF PFLGE: INDSEL Mask */
\r
13973 #define POSIF_PFLGE_ERRSEL_Pos 25 /*!< POSIF PFLGE: ERRSEL Position */
\r
13974 #define POSIF_PFLGE_ERRSEL_Msk (0x01UL << POSIF_PFLGE_ERRSEL_Pos) /*!< POSIF PFLGE: ERRSEL Mask */
\r
13975 #define POSIF_PFLGE_CNTSEL_Pos 26 /*!< POSIF PFLGE: CNTSEL Position */
\r
13976 #define POSIF_PFLGE_CNTSEL_Msk (0x01UL << POSIF_PFLGE_CNTSEL_Pos) /*!< POSIF PFLGE: CNTSEL Mask */
\r
13977 #define POSIF_PFLGE_DIRSEL_Pos 27 /*!< POSIF PFLGE: DIRSEL Position */
\r
13978 #define POSIF_PFLGE_DIRSEL_Msk (0x01UL << POSIF_PFLGE_DIRSEL_Pos) /*!< POSIF PFLGE: DIRSEL Mask */
\r
13979 #define POSIF_PFLGE_PCLSEL_Pos 28 /*!< POSIF PFLGE: PCLSEL Position */
\r
13980 #define POSIF_PFLGE_PCLSEL_Msk (0x01UL << POSIF_PFLGE_PCLSEL_Pos) /*!< POSIF PFLGE: PCLSEL Mask */
\r
13982 /* --------------------------------- POSIF_SPFLG -------------------------------- */
\r
13983 #define POSIF_SPFLG_SCHE_Pos 0 /*!< POSIF SPFLG: SCHE Position */
\r
13984 #define POSIF_SPFLG_SCHE_Msk (0x01UL << POSIF_SPFLG_SCHE_Pos) /*!< POSIF SPFLG: SCHE Mask */
\r
13985 #define POSIF_SPFLG_SWHE_Pos 1 /*!< POSIF SPFLG: SWHE Position */
\r
13986 #define POSIF_SPFLG_SWHE_Msk (0x01UL << POSIF_SPFLG_SWHE_Pos) /*!< POSIF SPFLG: SWHE Mask */
\r
13987 #define POSIF_SPFLG_SHIE_Pos 2 /*!< POSIF SPFLG: SHIE Position */
\r
13988 #define POSIF_SPFLG_SHIE_Msk (0x01UL << POSIF_SPFLG_SHIE_Pos) /*!< POSIF SPFLG: SHIE Mask */
\r
13989 #define POSIF_SPFLG_SMST_Pos 4 /*!< POSIF SPFLG: SMST Position */
\r
13990 #define POSIF_SPFLG_SMST_Msk (0x01UL << POSIF_SPFLG_SMST_Pos) /*!< POSIF SPFLG: SMST Mask */
\r
13991 #define POSIF_SPFLG_SINDX_Pos 8 /*!< POSIF SPFLG: SINDX Position */
\r
13992 #define POSIF_SPFLG_SINDX_Msk (0x01UL << POSIF_SPFLG_SINDX_Pos) /*!< POSIF SPFLG: SINDX Mask */
\r
13993 #define POSIF_SPFLG_SERR_Pos 9 /*!< POSIF SPFLG: SERR Position */
\r
13994 #define POSIF_SPFLG_SERR_Msk (0x01UL << POSIF_SPFLG_SERR_Pos) /*!< POSIF SPFLG: SERR Mask */
\r
13995 #define POSIF_SPFLG_SCNT_Pos 10 /*!< POSIF SPFLG: SCNT Position */
\r
13996 #define POSIF_SPFLG_SCNT_Msk (0x01UL << POSIF_SPFLG_SCNT_Pos) /*!< POSIF SPFLG: SCNT Mask */
\r
13997 #define POSIF_SPFLG_SDIR_Pos 11 /*!< POSIF SPFLG: SDIR Position */
\r
13998 #define POSIF_SPFLG_SDIR_Msk (0x01UL << POSIF_SPFLG_SDIR_Pos) /*!< POSIF SPFLG: SDIR Mask */
\r
13999 #define POSIF_SPFLG_SPCLK_Pos 12 /*!< POSIF SPFLG: SPCLK Position */
\r
14000 #define POSIF_SPFLG_SPCLK_Msk (0x01UL << POSIF_SPFLG_SPCLK_Pos) /*!< POSIF SPFLG: SPCLK Mask */
\r
14002 /* --------------------------------- POSIF_RPFLG -------------------------------- */
\r
14003 #define POSIF_RPFLG_RCHE_Pos 0 /*!< POSIF RPFLG: RCHE Position */
\r
14004 #define POSIF_RPFLG_RCHE_Msk (0x01UL << POSIF_RPFLG_RCHE_Pos) /*!< POSIF RPFLG: RCHE Mask */
\r
14005 #define POSIF_RPFLG_RWHE_Pos 1 /*!< POSIF RPFLG: RWHE Position */
\r
14006 #define POSIF_RPFLG_RWHE_Msk (0x01UL << POSIF_RPFLG_RWHE_Pos) /*!< POSIF RPFLG: RWHE Mask */
\r
14007 #define POSIF_RPFLG_RHIE_Pos 2 /*!< POSIF RPFLG: RHIE Position */
\r
14008 #define POSIF_RPFLG_RHIE_Msk (0x01UL << POSIF_RPFLG_RHIE_Pos) /*!< POSIF RPFLG: RHIE Mask */
\r
14009 #define POSIF_RPFLG_RMST_Pos 4 /*!< POSIF RPFLG: RMST Position */
\r
14010 #define POSIF_RPFLG_RMST_Msk (0x01UL << POSIF_RPFLG_RMST_Pos) /*!< POSIF RPFLG: RMST Mask */
\r
14011 #define POSIF_RPFLG_RINDX_Pos 8 /*!< POSIF RPFLG: RINDX Position */
\r
14012 #define POSIF_RPFLG_RINDX_Msk (0x01UL << POSIF_RPFLG_RINDX_Pos) /*!< POSIF RPFLG: RINDX Mask */
\r
14013 #define POSIF_RPFLG_RERR_Pos 9 /*!< POSIF RPFLG: RERR Position */
\r
14014 #define POSIF_RPFLG_RERR_Msk (0x01UL << POSIF_RPFLG_RERR_Pos) /*!< POSIF RPFLG: RERR Mask */
\r
14015 #define POSIF_RPFLG_RCNT_Pos 10 /*!< POSIF RPFLG: RCNT Position */
\r
14016 #define POSIF_RPFLG_RCNT_Msk (0x01UL << POSIF_RPFLG_RCNT_Pos) /*!< POSIF RPFLG: RCNT Mask */
\r
14017 #define POSIF_RPFLG_RDIR_Pos 11 /*!< POSIF RPFLG: RDIR Position */
\r
14018 #define POSIF_RPFLG_RDIR_Msk (0x01UL << POSIF_RPFLG_RDIR_Pos) /*!< POSIF RPFLG: RDIR Mask */
\r
14019 #define POSIF_RPFLG_RPCLK_Pos 12 /*!< POSIF RPFLG: RPCLK Position */
\r
14020 #define POSIF_RPFLG_RPCLK_Msk (0x01UL << POSIF_RPFLG_RPCLK_Pos) /*!< POSIF RPFLG: RPCLK Mask */
\r
14022 /* --------------------------------- POSIF_PDBG --------------------------------- */
\r
14023 #define POSIF_PDBG_QCSV_Pos 0 /*!< POSIF PDBG: QCSV Position */
\r
14024 #define POSIF_PDBG_QCSV_Msk (0x03UL << POSIF_PDBG_QCSV_Pos) /*!< POSIF PDBG: QCSV Mask */
\r
14025 #define POSIF_PDBG_QPSV_Pos 2 /*!< POSIF PDBG: QPSV Position */
\r
14026 #define POSIF_PDBG_QPSV_Msk (0x03UL << POSIF_PDBG_QPSV_Pos) /*!< POSIF PDBG: QPSV Mask */
\r
14027 #define POSIF_PDBG_IVAL_Pos 4 /*!< POSIF PDBG: IVAL Position */
\r
14028 #define POSIF_PDBG_IVAL_Msk (0x01UL << POSIF_PDBG_IVAL_Pos) /*!< POSIF PDBG: IVAL Mask */
\r
14029 #define POSIF_PDBG_HSP_Pos 5 /*!< POSIF PDBG: HSP Position */
\r
14030 #define POSIF_PDBG_HSP_Msk (0x07UL << POSIF_PDBG_HSP_Pos) /*!< POSIF PDBG: HSP Mask */
\r
14031 #define POSIF_PDBG_LPP0_Pos 8 /*!< POSIF PDBG: LPP0 Position */
\r
14032 #define POSIF_PDBG_LPP0_Msk (0x3fUL << POSIF_PDBG_LPP0_Pos) /*!< POSIF PDBG: LPP0 Mask */
\r
14033 #define POSIF_PDBG_LPP1_Pos 16 /*!< POSIF PDBG: LPP1 Position */
\r
14034 #define POSIF_PDBG_LPP1_Msk (0x3fUL << POSIF_PDBG_LPP1_Pos) /*!< POSIF PDBG: LPP1 Mask */
\r
14035 #define POSIF_PDBG_LPP2_Pos 22 /*!< POSIF PDBG: LPP2 Position */
\r
14036 #define POSIF_PDBG_LPP2_Msk (0x3fUL << POSIF_PDBG_LPP2_Pos) /*!< POSIF PDBG: LPP2 Mask */
\r
14039 /* ================================================================================ */
\r
14040 /* ================ struct 'PORT0' Position & Mask ================ */
\r
14041 /* ================================================================================ */
\r
14044 /* ---------------------------------- PORT0_OUT --------------------------------- */
\r
14045 #define PORT0_OUT_P0_Pos 0 /*!< PORT0 OUT: P0 Position */
\r
14046 #define PORT0_OUT_P0_Msk (0x01UL << PORT0_OUT_P0_Pos) /*!< PORT0 OUT: P0 Mask */
\r
14047 #define PORT0_OUT_P1_Pos 1 /*!< PORT0 OUT: P1 Position */
\r
14048 #define PORT0_OUT_P1_Msk (0x01UL << PORT0_OUT_P1_Pos) /*!< PORT0 OUT: P1 Mask */
\r
14049 #define PORT0_OUT_P2_Pos 2 /*!< PORT0 OUT: P2 Position */
\r
14050 #define PORT0_OUT_P2_Msk (0x01UL << PORT0_OUT_P2_Pos) /*!< PORT0 OUT: P2 Mask */
\r
14051 #define PORT0_OUT_P3_Pos 3 /*!< PORT0 OUT: P3 Position */
\r
14052 #define PORT0_OUT_P3_Msk (0x01UL << PORT0_OUT_P3_Pos) /*!< PORT0 OUT: P3 Mask */
\r
14053 #define PORT0_OUT_P4_Pos 4 /*!< PORT0 OUT: P4 Position */
\r
14054 #define PORT0_OUT_P4_Msk (0x01UL << PORT0_OUT_P4_Pos) /*!< PORT0 OUT: P4 Mask */
\r
14055 #define PORT0_OUT_P5_Pos 5 /*!< PORT0 OUT: P5 Position */
\r
14056 #define PORT0_OUT_P5_Msk (0x01UL << PORT0_OUT_P5_Pos) /*!< PORT0 OUT: P5 Mask */
\r
14057 #define PORT0_OUT_P6_Pos 6 /*!< PORT0 OUT: P6 Position */
\r
14058 #define PORT0_OUT_P6_Msk (0x01UL << PORT0_OUT_P6_Pos) /*!< PORT0 OUT: P6 Mask */
\r
14059 #define PORT0_OUT_P7_Pos 7 /*!< PORT0 OUT: P7 Position */
\r
14060 #define PORT0_OUT_P7_Msk (0x01UL << PORT0_OUT_P7_Pos) /*!< PORT0 OUT: P7 Mask */
\r
14061 #define PORT0_OUT_P8_Pos 8 /*!< PORT0 OUT: P8 Position */
\r
14062 #define PORT0_OUT_P8_Msk (0x01UL << PORT0_OUT_P8_Pos) /*!< PORT0 OUT: P8 Mask */
\r
14063 #define PORT0_OUT_P9_Pos 9 /*!< PORT0 OUT: P9 Position */
\r
14064 #define PORT0_OUT_P9_Msk (0x01UL << PORT0_OUT_P9_Pos) /*!< PORT0 OUT: P9 Mask */
\r
14065 #define PORT0_OUT_P10_Pos 10 /*!< PORT0 OUT: P10 Position */
\r
14066 #define PORT0_OUT_P10_Msk (0x01UL << PORT0_OUT_P10_Pos) /*!< PORT0 OUT: P10 Mask */
\r
14067 #define PORT0_OUT_P11_Pos 11 /*!< PORT0 OUT: P11 Position */
\r
14068 #define PORT0_OUT_P11_Msk (0x01UL << PORT0_OUT_P11_Pos) /*!< PORT0 OUT: P11 Mask */
\r
14069 #define PORT0_OUT_P12_Pos 12 /*!< PORT0 OUT: P12 Position */
\r
14070 #define PORT0_OUT_P12_Msk (0x01UL << PORT0_OUT_P12_Pos) /*!< PORT0 OUT: P12 Mask */
\r
14071 #define PORT0_OUT_P13_Pos 13 /*!< PORT0 OUT: P13 Position */
\r
14072 #define PORT0_OUT_P13_Msk (0x01UL << PORT0_OUT_P13_Pos) /*!< PORT0 OUT: P13 Mask */
\r
14073 #define PORT0_OUT_P14_Pos 14 /*!< PORT0 OUT: P14 Position */
\r
14074 #define PORT0_OUT_P14_Msk (0x01UL << PORT0_OUT_P14_Pos) /*!< PORT0 OUT: P14 Mask */
\r
14075 #define PORT0_OUT_P15_Pos 15 /*!< PORT0 OUT: P15 Position */
\r
14076 #define PORT0_OUT_P15_Msk (0x01UL << PORT0_OUT_P15_Pos) /*!< PORT0 OUT: P15 Mask */
\r
14078 /* ---------------------------------- PORT0_OMR --------------------------------- */
\r
14079 #define PORT0_OMR_PS0_Pos 0 /*!< PORT0 OMR: PS0 Position */
\r
14080 #define PORT0_OMR_PS0_Msk (0x01UL << PORT0_OMR_PS0_Pos) /*!< PORT0 OMR: PS0 Mask */
\r
14081 #define PORT0_OMR_PS1_Pos 1 /*!< PORT0 OMR: PS1 Position */
\r
14082 #define PORT0_OMR_PS1_Msk (0x01UL << PORT0_OMR_PS1_Pos) /*!< PORT0 OMR: PS1 Mask */
\r
14083 #define PORT0_OMR_PS2_Pos 2 /*!< PORT0 OMR: PS2 Position */
\r
14084 #define PORT0_OMR_PS2_Msk (0x01UL << PORT0_OMR_PS2_Pos) /*!< PORT0 OMR: PS2 Mask */
\r
14085 #define PORT0_OMR_PS3_Pos 3 /*!< PORT0 OMR: PS3 Position */
\r
14086 #define PORT0_OMR_PS3_Msk (0x01UL << PORT0_OMR_PS3_Pos) /*!< PORT0 OMR: PS3 Mask */
\r
14087 #define PORT0_OMR_PS4_Pos 4 /*!< PORT0 OMR: PS4 Position */
\r
14088 #define PORT0_OMR_PS4_Msk (0x01UL << PORT0_OMR_PS4_Pos) /*!< PORT0 OMR: PS4 Mask */
\r
14089 #define PORT0_OMR_PS5_Pos 5 /*!< PORT0 OMR: PS5 Position */
\r
14090 #define PORT0_OMR_PS5_Msk (0x01UL << PORT0_OMR_PS5_Pos) /*!< PORT0 OMR: PS5 Mask */
\r
14091 #define PORT0_OMR_PS6_Pos 6 /*!< PORT0 OMR: PS6 Position */
\r
14092 #define PORT0_OMR_PS6_Msk (0x01UL << PORT0_OMR_PS6_Pos) /*!< PORT0 OMR: PS6 Mask */
\r
14093 #define PORT0_OMR_PS7_Pos 7 /*!< PORT0 OMR: PS7 Position */
\r
14094 #define PORT0_OMR_PS7_Msk (0x01UL << PORT0_OMR_PS7_Pos) /*!< PORT0 OMR: PS7 Mask */
\r
14095 #define PORT0_OMR_PS8_Pos 8 /*!< PORT0 OMR: PS8 Position */
\r
14096 #define PORT0_OMR_PS8_Msk (0x01UL << PORT0_OMR_PS8_Pos) /*!< PORT0 OMR: PS8 Mask */
\r
14097 #define PORT0_OMR_PS9_Pos 9 /*!< PORT0 OMR: PS9 Position */
\r
14098 #define PORT0_OMR_PS9_Msk (0x01UL << PORT0_OMR_PS9_Pos) /*!< PORT0 OMR: PS9 Mask */
\r
14099 #define PORT0_OMR_PS10_Pos 10 /*!< PORT0 OMR: PS10 Position */
\r
14100 #define PORT0_OMR_PS10_Msk (0x01UL << PORT0_OMR_PS10_Pos) /*!< PORT0 OMR: PS10 Mask */
\r
14101 #define PORT0_OMR_PS11_Pos 11 /*!< PORT0 OMR: PS11 Position */
\r
14102 #define PORT0_OMR_PS11_Msk (0x01UL << PORT0_OMR_PS11_Pos) /*!< PORT0 OMR: PS11 Mask */
\r
14103 #define PORT0_OMR_PS12_Pos 12 /*!< PORT0 OMR: PS12 Position */
\r
14104 #define PORT0_OMR_PS12_Msk (0x01UL << PORT0_OMR_PS12_Pos) /*!< PORT0 OMR: PS12 Mask */
\r
14105 #define PORT0_OMR_PS13_Pos 13 /*!< PORT0 OMR: PS13 Position */
\r
14106 #define PORT0_OMR_PS13_Msk (0x01UL << PORT0_OMR_PS13_Pos) /*!< PORT0 OMR: PS13 Mask */
\r
14107 #define PORT0_OMR_PS14_Pos 14 /*!< PORT0 OMR: PS14 Position */
\r
14108 #define PORT0_OMR_PS14_Msk (0x01UL << PORT0_OMR_PS14_Pos) /*!< PORT0 OMR: PS14 Mask */
\r
14109 #define PORT0_OMR_PS15_Pos 15 /*!< PORT0 OMR: PS15 Position */
\r
14110 #define PORT0_OMR_PS15_Msk (0x01UL << PORT0_OMR_PS15_Pos) /*!< PORT0 OMR: PS15 Mask */
\r
14111 #define PORT0_OMR_PR0_Pos 16 /*!< PORT0 OMR: PR0 Position */
\r
14112 #define PORT0_OMR_PR0_Msk (0x01UL << PORT0_OMR_PR0_Pos) /*!< PORT0 OMR: PR0 Mask */
\r
14113 #define PORT0_OMR_PR1_Pos 17 /*!< PORT0 OMR: PR1 Position */
\r
14114 #define PORT0_OMR_PR1_Msk (0x01UL << PORT0_OMR_PR1_Pos) /*!< PORT0 OMR: PR1 Mask */
\r
14115 #define PORT0_OMR_PR2_Pos 18 /*!< PORT0 OMR: PR2 Position */
\r
14116 #define PORT0_OMR_PR2_Msk (0x01UL << PORT0_OMR_PR2_Pos) /*!< PORT0 OMR: PR2 Mask */
\r
14117 #define PORT0_OMR_PR3_Pos 19 /*!< PORT0 OMR: PR3 Position */
\r
14118 #define PORT0_OMR_PR3_Msk (0x01UL << PORT0_OMR_PR3_Pos) /*!< PORT0 OMR: PR3 Mask */
\r
14119 #define PORT0_OMR_PR4_Pos 20 /*!< PORT0 OMR: PR4 Position */
\r
14120 #define PORT0_OMR_PR4_Msk (0x01UL << PORT0_OMR_PR4_Pos) /*!< PORT0 OMR: PR4 Mask */
\r
14121 #define PORT0_OMR_PR5_Pos 21 /*!< PORT0 OMR: PR5 Position */
\r
14122 #define PORT0_OMR_PR5_Msk (0x01UL << PORT0_OMR_PR5_Pos) /*!< PORT0 OMR: PR5 Mask */
\r
14123 #define PORT0_OMR_PR6_Pos 22 /*!< PORT0 OMR: PR6 Position */
\r
14124 #define PORT0_OMR_PR6_Msk (0x01UL << PORT0_OMR_PR6_Pos) /*!< PORT0 OMR: PR6 Mask */
\r
14125 #define PORT0_OMR_PR7_Pos 23 /*!< PORT0 OMR: PR7 Position */
\r
14126 #define PORT0_OMR_PR7_Msk (0x01UL << PORT0_OMR_PR7_Pos) /*!< PORT0 OMR: PR7 Mask */
\r
14127 #define PORT0_OMR_PR8_Pos 24 /*!< PORT0 OMR: PR8 Position */
\r
14128 #define PORT0_OMR_PR8_Msk (0x01UL << PORT0_OMR_PR8_Pos) /*!< PORT0 OMR: PR8 Mask */
\r
14129 #define PORT0_OMR_PR9_Pos 25 /*!< PORT0 OMR: PR9 Position */
\r
14130 #define PORT0_OMR_PR9_Msk (0x01UL << PORT0_OMR_PR9_Pos) /*!< PORT0 OMR: PR9 Mask */
\r
14131 #define PORT0_OMR_PR10_Pos 26 /*!< PORT0 OMR: PR10 Position */
\r
14132 #define PORT0_OMR_PR10_Msk (0x01UL << PORT0_OMR_PR10_Pos) /*!< PORT0 OMR: PR10 Mask */
\r
14133 #define PORT0_OMR_PR11_Pos 27 /*!< PORT0 OMR: PR11 Position */
\r
14134 #define PORT0_OMR_PR11_Msk (0x01UL << PORT0_OMR_PR11_Pos) /*!< PORT0 OMR: PR11 Mask */
\r
14135 #define PORT0_OMR_PR12_Pos 28 /*!< PORT0 OMR: PR12 Position */
\r
14136 #define PORT0_OMR_PR12_Msk (0x01UL << PORT0_OMR_PR12_Pos) /*!< PORT0 OMR: PR12 Mask */
\r
14137 #define PORT0_OMR_PR13_Pos 29 /*!< PORT0 OMR: PR13 Position */
\r
14138 #define PORT0_OMR_PR13_Msk (0x01UL << PORT0_OMR_PR13_Pos) /*!< PORT0 OMR: PR13 Mask */
\r
14139 #define PORT0_OMR_PR14_Pos 30 /*!< PORT0 OMR: PR14 Position */
\r
14140 #define PORT0_OMR_PR14_Msk (0x01UL << PORT0_OMR_PR14_Pos) /*!< PORT0 OMR: PR14 Mask */
\r
14141 #define PORT0_OMR_PR15_Pos 31 /*!< PORT0 OMR: PR15 Position */
\r
14142 #define PORT0_OMR_PR15_Msk (0x01UL << PORT0_OMR_PR15_Pos) /*!< PORT0 OMR: PR15 Mask */
\r
14144 /* --------------------------------- PORT0_IOCR0 -------------------------------- */
\r
14145 #define PORT0_IOCR0_PC0_Pos 3 /*!< PORT0 IOCR0: PC0 Position */
\r
14146 #define PORT0_IOCR0_PC0_Msk (0x1fUL << PORT0_IOCR0_PC0_Pos) /*!< PORT0 IOCR0: PC0 Mask */
\r
14147 #define PORT0_IOCR0_PC1_Pos 11 /*!< PORT0 IOCR0: PC1 Position */
\r
14148 #define PORT0_IOCR0_PC1_Msk (0x1fUL << PORT0_IOCR0_PC1_Pos) /*!< PORT0 IOCR0: PC1 Mask */
\r
14149 #define PORT0_IOCR0_PC2_Pos 19 /*!< PORT0 IOCR0: PC2 Position */
\r
14150 #define PORT0_IOCR0_PC2_Msk (0x1fUL << PORT0_IOCR0_PC2_Pos) /*!< PORT0 IOCR0: PC2 Mask */
\r
14151 #define PORT0_IOCR0_PC3_Pos 27 /*!< PORT0 IOCR0: PC3 Position */
\r
14152 #define PORT0_IOCR0_PC3_Msk (0x1fUL << PORT0_IOCR0_PC3_Pos) /*!< PORT0 IOCR0: PC3 Mask */
\r
14154 /* --------------------------------- PORT0_IOCR4 -------------------------------- */
\r
14155 #define PORT0_IOCR4_PC4_Pos 3 /*!< PORT0 IOCR4: PC4 Position */
\r
14156 #define PORT0_IOCR4_PC4_Msk (0x1fUL << PORT0_IOCR4_PC4_Pos) /*!< PORT0 IOCR4: PC4 Mask */
\r
14157 #define PORT0_IOCR4_PC5_Pos 11 /*!< PORT0 IOCR4: PC5 Position */
\r
14158 #define PORT0_IOCR4_PC5_Msk (0x1fUL << PORT0_IOCR4_PC5_Pos) /*!< PORT0 IOCR4: PC5 Mask */
\r
14159 #define PORT0_IOCR4_PC6_Pos 19 /*!< PORT0 IOCR4: PC6 Position */
\r
14160 #define PORT0_IOCR4_PC6_Msk (0x1fUL << PORT0_IOCR4_PC6_Pos) /*!< PORT0 IOCR4: PC6 Mask */
\r
14161 #define PORT0_IOCR4_PC7_Pos 27 /*!< PORT0 IOCR4: PC7 Position */
\r
14162 #define PORT0_IOCR4_PC7_Msk (0x1fUL << PORT0_IOCR4_PC7_Pos) /*!< PORT0 IOCR4: PC7 Mask */
\r
14164 /* --------------------------------- PORT0_IOCR8 -------------------------------- */
\r
14165 #define PORT0_IOCR8_PC8_Pos 3 /*!< PORT0 IOCR8: PC8 Position */
\r
14166 #define PORT0_IOCR8_PC8_Msk (0x1fUL << PORT0_IOCR8_PC8_Pos) /*!< PORT0 IOCR8: PC8 Mask */
\r
14167 #define PORT0_IOCR8_PC9_Pos 11 /*!< PORT0 IOCR8: PC9 Position */
\r
14168 #define PORT0_IOCR8_PC9_Msk (0x1fUL << PORT0_IOCR8_PC9_Pos) /*!< PORT0 IOCR8: PC9 Mask */
\r
14169 #define PORT0_IOCR8_PC10_Pos 19 /*!< PORT0 IOCR8: PC10 Position */
\r
14170 #define PORT0_IOCR8_PC10_Msk (0x1fUL << PORT0_IOCR8_PC10_Pos) /*!< PORT0 IOCR8: PC10 Mask */
\r
14171 #define PORT0_IOCR8_PC11_Pos 27 /*!< PORT0 IOCR8: PC11 Position */
\r
14172 #define PORT0_IOCR8_PC11_Msk (0x1fUL << PORT0_IOCR8_PC11_Pos) /*!< PORT0 IOCR8: PC11 Mask */
\r
14174 /* -------------------------------- PORT0_IOCR12 -------------------------------- */
\r
14175 #define PORT0_IOCR12_PC12_Pos 3 /*!< PORT0 IOCR12: PC12 Position */
\r
14176 #define PORT0_IOCR12_PC12_Msk (0x1fUL << PORT0_IOCR12_PC12_Pos) /*!< PORT0 IOCR12: PC12 Mask */
\r
14177 #define PORT0_IOCR12_PC13_Pos 11 /*!< PORT0 IOCR12: PC13 Position */
\r
14178 #define PORT0_IOCR12_PC13_Msk (0x1fUL << PORT0_IOCR12_PC13_Pos) /*!< PORT0 IOCR12: PC13 Mask */
\r
14179 #define PORT0_IOCR12_PC14_Pos 19 /*!< PORT0 IOCR12: PC14 Position */
\r
14180 #define PORT0_IOCR12_PC14_Msk (0x1fUL << PORT0_IOCR12_PC14_Pos) /*!< PORT0 IOCR12: PC14 Mask */
\r
14181 #define PORT0_IOCR12_PC15_Pos 27 /*!< PORT0 IOCR12: PC15 Position */
\r
14182 #define PORT0_IOCR12_PC15_Msk (0x1fUL << PORT0_IOCR12_PC15_Pos) /*!< PORT0 IOCR12: PC15 Mask */
\r
14184 /* ---------------------------------- PORT0_IN ---------------------------------- */
\r
14185 #define PORT0_IN_P0_Pos 0 /*!< PORT0 IN: P0 Position */
\r
14186 #define PORT0_IN_P0_Msk (0x01UL << PORT0_IN_P0_Pos) /*!< PORT0 IN: P0 Mask */
\r
14187 #define PORT0_IN_P1_Pos 1 /*!< PORT0 IN: P1 Position */
\r
14188 #define PORT0_IN_P1_Msk (0x01UL << PORT0_IN_P1_Pos) /*!< PORT0 IN: P1 Mask */
\r
14189 #define PORT0_IN_P2_Pos 2 /*!< PORT0 IN: P2 Position */
\r
14190 #define PORT0_IN_P2_Msk (0x01UL << PORT0_IN_P2_Pos) /*!< PORT0 IN: P2 Mask */
\r
14191 #define PORT0_IN_P3_Pos 3 /*!< PORT0 IN: P3 Position */
\r
14192 #define PORT0_IN_P3_Msk (0x01UL << PORT0_IN_P3_Pos) /*!< PORT0 IN: P3 Mask */
\r
14193 #define PORT0_IN_P4_Pos 4 /*!< PORT0 IN: P4 Position */
\r
14194 #define PORT0_IN_P4_Msk (0x01UL << PORT0_IN_P4_Pos) /*!< PORT0 IN: P4 Mask */
\r
14195 #define PORT0_IN_P5_Pos 5 /*!< PORT0 IN: P5 Position */
\r
14196 #define PORT0_IN_P5_Msk (0x01UL << PORT0_IN_P5_Pos) /*!< PORT0 IN: P5 Mask */
\r
14197 #define PORT0_IN_P6_Pos 6 /*!< PORT0 IN: P6 Position */
\r
14198 #define PORT0_IN_P6_Msk (0x01UL << PORT0_IN_P6_Pos) /*!< PORT0 IN: P6 Mask */
\r
14199 #define PORT0_IN_P7_Pos 7 /*!< PORT0 IN: P7 Position */
\r
14200 #define PORT0_IN_P7_Msk (0x01UL << PORT0_IN_P7_Pos) /*!< PORT0 IN: P7 Mask */
\r
14201 #define PORT0_IN_P8_Pos 8 /*!< PORT0 IN: P8 Position */
\r
14202 #define PORT0_IN_P8_Msk (0x01UL << PORT0_IN_P8_Pos) /*!< PORT0 IN: P8 Mask */
\r
14203 #define PORT0_IN_P9_Pos 9 /*!< PORT0 IN: P9 Position */
\r
14204 #define PORT0_IN_P9_Msk (0x01UL << PORT0_IN_P9_Pos) /*!< PORT0 IN: P9 Mask */
\r
14205 #define PORT0_IN_P10_Pos 10 /*!< PORT0 IN: P10 Position */
\r
14206 #define PORT0_IN_P10_Msk (0x01UL << PORT0_IN_P10_Pos) /*!< PORT0 IN: P10 Mask */
\r
14207 #define PORT0_IN_P11_Pos 11 /*!< PORT0 IN: P11 Position */
\r
14208 #define PORT0_IN_P11_Msk (0x01UL << PORT0_IN_P11_Pos) /*!< PORT0 IN: P11 Mask */
\r
14209 #define PORT0_IN_P12_Pos 12 /*!< PORT0 IN: P12 Position */
\r
14210 #define PORT0_IN_P12_Msk (0x01UL << PORT0_IN_P12_Pos) /*!< PORT0 IN: P12 Mask */
\r
14211 #define PORT0_IN_P13_Pos 13 /*!< PORT0 IN: P13 Position */
\r
14212 #define PORT0_IN_P13_Msk (0x01UL << PORT0_IN_P13_Pos) /*!< PORT0 IN: P13 Mask */
\r
14213 #define PORT0_IN_P14_Pos 14 /*!< PORT0 IN: P14 Position */
\r
14214 #define PORT0_IN_P14_Msk (0x01UL << PORT0_IN_P14_Pos) /*!< PORT0 IN: P14 Mask */
\r
14215 #define PORT0_IN_P15_Pos 15 /*!< PORT0 IN: P15 Position */
\r
14216 #define PORT0_IN_P15_Msk (0x01UL << PORT0_IN_P15_Pos) /*!< PORT0 IN: P15 Mask */
\r
14218 /* --------------------------------- PORT0_PDR0 --------------------------------- */
\r
14219 #define PORT0_PDR0_PD0_Pos 0 /*!< PORT0 PDR0: PD0 Position */
\r
14220 #define PORT0_PDR0_PD0_Msk (0x07UL << PORT0_PDR0_PD0_Pos) /*!< PORT0 PDR0: PD0 Mask */
\r
14221 #define PORT0_PDR0_PD1_Pos 4 /*!< PORT0 PDR0: PD1 Position */
\r
14222 #define PORT0_PDR0_PD1_Msk (0x07UL << PORT0_PDR0_PD1_Pos) /*!< PORT0 PDR0: PD1 Mask */
\r
14223 #define PORT0_PDR0_PD2_Pos 8 /*!< PORT0 PDR0: PD2 Position */
\r
14224 #define PORT0_PDR0_PD2_Msk (0x07UL << PORT0_PDR0_PD2_Pos) /*!< PORT0 PDR0: PD2 Mask */
\r
14225 #define PORT0_PDR0_PD3_Pos 12 /*!< PORT0 PDR0: PD3 Position */
\r
14226 #define PORT0_PDR0_PD3_Msk (0x07UL << PORT0_PDR0_PD3_Pos) /*!< PORT0 PDR0: PD3 Mask */
\r
14227 #define PORT0_PDR0_PD4_Pos 16 /*!< PORT0 PDR0: PD4 Position */
\r
14228 #define PORT0_PDR0_PD4_Msk (0x07UL << PORT0_PDR0_PD4_Pos) /*!< PORT0 PDR0: PD4 Mask */
\r
14229 #define PORT0_PDR0_PD5_Pos 20 /*!< PORT0 PDR0: PD5 Position */
\r
14230 #define PORT0_PDR0_PD5_Msk (0x07UL << PORT0_PDR0_PD5_Pos) /*!< PORT0 PDR0: PD5 Mask */
\r
14231 #define PORT0_PDR0_PD6_Pos 24 /*!< PORT0 PDR0: PD6 Position */
\r
14232 #define PORT0_PDR0_PD6_Msk (0x07UL << PORT0_PDR0_PD6_Pos) /*!< PORT0 PDR0: PD6 Mask */
\r
14233 #define PORT0_PDR0_PD7_Pos 28 /*!< PORT0 PDR0: PD7 Position */
\r
14234 #define PORT0_PDR0_PD7_Msk (0x07UL << PORT0_PDR0_PD7_Pos) /*!< PORT0 PDR0: PD7 Mask */
\r
14236 /* --------------------------------- PORT0_PDR1 --------------------------------- */
\r
14237 #define PORT0_PDR1_PD8_Pos 0 /*!< PORT0 PDR1: PD8 Position */
\r
14238 #define PORT0_PDR1_PD8_Msk (0x07UL << PORT0_PDR1_PD8_Pos) /*!< PORT0 PDR1: PD8 Mask */
\r
14239 #define PORT0_PDR1_PD9_Pos 4 /*!< PORT0 PDR1: PD9 Position */
\r
14240 #define PORT0_PDR1_PD9_Msk (0x07UL << PORT0_PDR1_PD9_Pos) /*!< PORT0 PDR1: PD9 Mask */
\r
14241 #define PORT0_PDR1_PD10_Pos 8 /*!< PORT0 PDR1: PD10 Position */
\r
14242 #define PORT0_PDR1_PD10_Msk (0x07UL << PORT0_PDR1_PD10_Pos) /*!< PORT0 PDR1: PD10 Mask */
\r
14243 #define PORT0_PDR1_PD11_Pos 12 /*!< PORT0 PDR1: PD11 Position */
\r
14244 #define PORT0_PDR1_PD11_Msk (0x07UL << PORT0_PDR1_PD11_Pos) /*!< PORT0 PDR1: PD11 Mask */
\r
14245 #define PORT0_PDR1_PD12_Pos 16 /*!< PORT0 PDR1: PD12 Position */
\r
14246 #define PORT0_PDR1_PD12_Msk (0x07UL << PORT0_PDR1_PD12_Pos) /*!< PORT0 PDR1: PD12 Mask */
\r
14247 #define PORT0_PDR1_PD13_Pos 20 /*!< PORT0 PDR1: PD13 Position */
\r
14248 #define PORT0_PDR1_PD13_Msk (0x07UL << PORT0_PDR1_PD13_Pos) /*!< PORT0 PDR1: PD13 Mask */
\r
14249 #define PORT0_PDR1_PD14_Pos 24 /*!< PORT0 PDR1: PD14 Position */
\r
14250 #define PORT0_PDR1_PD14_Msk (0x07UL << PORT0_PDR1_PD14_Pos) /*!< PORT0 PDR1: PD14 Mask */
\r
14251 #define PORT0_PDR1_PD15_Pos 28 /*!< PORT0 PDR1: PD15 Position */
\r
14252 #define PORT0_PDR1_PD15_Msk (0x07UL << PORT0_PDR1_PD15_Pos) /*!< PORT0 PDR1: PD15 Mask */
\r
14254 /* --------------------------------- PORT0_PDISC -------------------------------- */
\r
14255 #define PORT0_PDISC_PDIS0_Pos 0 /*!< PORT0 PDISC: PDIS0 Position */
\r
14256 #define PORT0_PDISC_PDIS0_Msk (0x01UL << PORT0_PDISC_PDIS0_Pos) /*!< PORT0 PDISC: PDIS0 Mask */
\r
14257 #define PORT0_PDISC_PDIS1_Pos 1 /*!< PORT0 PDISC: PDIS1 Position */
\r
14258 #define PORT0_PDISC_PDIS1_Msk (0x01UL << PORT0_PDISC_PDIS1_Pos) /*!< PORT0 PDISC: PDIS1 Mask */
\r
14259 #define PORT0_PDISC_PDIS2_Pos 2 /*!< PORT0 PDISC: PDIS2 Position */
\r
14260 #define PORT0_PDISC_PDIS2_Msk (0x01UL << PORT0_PDISC_PDIS2_Pos) /*!< PORT0 PDISC: PDIS2 Mask */
\r
14261 #define PORT0_PDISC_PDIS3_Pos 3 /*!< PORT0 PDISC: PDIS3 Position */
\r
14262 #define PORT0_PDISC_PDIS3_Msk (0x01UL << PORT0_PDISC_PDIS3_Pos) /*!< PORT0 PDISC: PDIS3 Mask */
\r
14263 #define PORT0_PDISC_PDIS4_Pos 4 /*!< PORT0 PDISC: PDIS4 Position */
\r
14264 #define PORT0_PDISC_PDIS4_Msk (0x01UL << PORT0_PDISC_PDIS4_Pos) /*!< PORT0 PDISC: PDIS4 Mask */
\r
14265 #define PORT0_PDISC_PDIS5_Pos 5 /*!< PORT0 PDISC: PDIS5 Position */
\r
14266 #define PORT0_PDISC_PDIS5_Msk (0x01UL << PORT0_PDISC_PDIS5_Pos) /*!< PORT0 PDISC: PDIS5 Mask */
\r
14267 #define PORT0_PDISC_PDIS6_Pos 6 /*!< PORT0 PDISC: PDIS6 Position */
\r
14268 #define PORT0_PDISC_PDIS6_Msk (0x01UL << PORT0_PDISC_PDIS6_Pos) /*!< PORT0 PDISC: PDIS6 Mask */
\r
14269 #define PORT0_PDISC_PDIS7_Pos 7 /*!< PORT0 PDISC: PDIS7 Position */
\r
14270 #define PORT0_PDISC_PDIS7_Msk (0x01UL << PORT0_PDISC_PDIS7_Pos) /*!< PORT0 PDISC: PDIS7 Mask */
\r
14271 #define PORT0_PDISC_PDIS8_Pos 8 /*!< PORT0 PDISC: PDIS8 Position */
\r
14272 #define PORT0_PDISC_PDIS8_Msk (0x01UL << PORT0_PDISC_PDIS8_Pos) /*!< PORT0 PDISC: PDIS8 Mask */
\r
14273 #define PORT0_PDISC_PDIS9_Pos 9 /*!< PORT0 PDISC: PDIS9 Position */
\r
14274 #define PORT0_PDISC_PDIS9_Msk (0x01UL << PORT0_PDISC_PDIS9_Pos) /*!< PORT0 PDISC: PDIS9 Mask */
\r
14275 #define PORT0_PDISC_PDIS10_Pos 10 /*!< PORT0 PDISC: PDIS10 Position */
\r
14276 #define PORT0_PDISC_PDIS10_Msk (0x01UL << PORT0_PDISC_PDIS10_Pos) /*!< PORT0 PDISC: PDIS10 Mask */
\r
14277 #define PORT0_PDISC_PDIS11_Pos 11 /*!< PORT0 PDISC: PDIS11 Position */
\r
14278 #define PORT0_PDISC_PDIS11_Msk (0x01UL << PORT0_PDISC_PDIS11_Pos) /*!< PORT0 PDISC: PDIS11 Mask */
\r
14279 #define PORT0_PDISC_PDIS12_Pos 12 /*!< PORT0 PDISC: PDIS12 Position */
\r
14280 #define PORT0_PDISC_PDIS12_Msk (0x01UL << PORT0_PDISC_PDIS12_Pos) /*!< PORT0 PDISC: PDIS12 Mask */
\r
14281 #define PORT0_PDISC_PDIS13_Pos 13 /*!< PORT0 PDISC: PDIS13 Position */
\r
14282 #define PORT0_PDISC_PDIS13_Msk (0x01UL << PORT0_PDISC_PDIS13_Pos) /*!< PORT0 PDISC: PDIS13 Mask */
\r
14283 #define PORT0_PDISC_PDIS14_Pos 14 /*!< PORT0 PDISC: PDIS14 Position */
\r
14284 #define PORT0_PDISC_PDIS14_Msk (0x01UL << PORT0_PDISC_PDIS14_Pos) /*!< PORT0 PDISC: PDIS14 Mask */
\r
14285 #define PORT0_PDISC_PDIS15_Pos 15 /*!< PORT0 PDISC: PDIS15 Position */
\r
14286 #define PORT0_PDISC_PDIS15_Msk (0x01UL << PORT0_PDISC_PDIS15_Pos) /*!< PORT0 PDISC: PDIS15 Mask */
\r
14288 /* ---------------------------------- PORT0_PPS --------------------------------- */
\r
14289 #define PORT0_PPS_PPS0_Pos 0 /*!< PORT0 PPS: PPS0 Position */
\r
14290 #define PORT0_PPS_PPS0_Msk (0x01UL << PORT0_PPS_PPS0_Pos) /*!< PORT0 PPS: PPS0 Mask */
\r
14291 #define PORT0_PPS_PPS1_Pos 1 /*!< PORT0 PPS: PPS1 Position */
\r
14292 #define PORT0_PPS_PPS1_Msk (0x01UL << PORT0_PPS_PPS1_Pos) /*!< PORT0 PPS: PPS1 Mask */
\r
14293 #define PORT0_PPS_PPS2_Pos 2 /*!< PORT0 PPS: PPS2 Position */
\r
14294 #define PORT0_PPS_PPS2_Msk (0x01UL << PORT0_PPS_PPS2_Pos) /*!< PORT0 PPS: PPS2 Mask */
\r
14295 #define PORT0_PPS_PPS3_Pos 3 /*!< PORT0 PPS: PPS3 Position */
\r
14296 #define PORT0_PPS_PPS3_Msk (0x01UL << PORT0_PPS_PPS3_Pos) /*!< PORT0 PPS: PPS3 Mask */
\r
14297 #define PORT0_PPS_PPS4_Pos 4 /*!< PORT0 PPS: PPS4 Position */
\r
14298 #define PORT0_PPS_PPS4_Msk (0x01UL << PORT0_PPS_PPS4_Pos) /*!< PORT0 PPS: PPS4 Mask */
\r
14299 #define PORT0_PPS_PPS5_Pos 5 /*!< PORT0 PPS: PPS5 Position */
\r
14300 #define PORT0_PPS_PPS5_Msk (0x01UL << PORT0_PPS_PPS5_Pos) /*!< PORT0 PPS: PPS5 Mask */
\r
14301 #define PORT0_PPS_PPS6_Pos 6 /*!< PORT0 PPS: PPS6 Position */
\r
14302 #define PORT0_PPS_PPS6_Msk (0x01UL << PORT0_PPS_PPS6_Pos) /*!< PORT0 PPS: PPS6 Mask */
\r
14303 #define PORT0_PPS_PPS7_Pos 7 /*!< PORT0 PPS: PPS7 Position */
\r
14304 #define PORT0_PPS_PPS7_Msk (0x01UL << PORT0_PPS_PPS7_Pos) /*!< PORT0 PPS: PPS7 Mask */
\r
14305 #define PORT0_PPS_PPS8_Pos 8 /*!< PORT0 PPS: PPS8 Position */
\r
14306 #define PORT0_PPS_PPS8_Msk (0x01UL << PORT0_PPS_PPS8_Pos) /*!< PORT0 PPS: PPS8 Mask */
\r
14307 #define PORT0_PPS_PPS9_Pos 9 /*!< PORT0 PPS: PPS9 Position */
\r
14308 #define PORT0_PPS_PPS9_Msk (0x01UL << PORT0_PPS_PPS9_Pos) /*!< PORT0 PPS: PPS9 Mask */
\r
14309 #define PORT0_PPS_PPS10_Pos 10 /*!< PORT0 PPS: PPS10 Position */
\r
14310 #define PORT0_PPS_PPS10_Msk (0x01UL << PORT0_PPS_PPS10_Pos) /*!< PORT0 PPS: PPS10 Mask */
\r
14311 #define PORT0_PPS_PPS11_Pos 11 /*!< PORT0 PPS: PPS11 Position */
\r
14312 #define PORT0_PPS_PPS11_Msk (0x01UL << PORT0_PPS_PPS11_Pos) /*!< PORT0 PPS: PPS11 Mask */
\r
14313 #define PORT0_PPS_PPS12_Pos 12 /*!< PORT0 PPS: PPS12 Position */
\r
14314 #define PORT0_PPS_PPS12_Msk (0x01UL << PORT0_PPS_PPS12_Pos) /*!< PORT0 PPS: PPS12 Mask */
\r
14315 #define PORT0_PPS_PPS13_Pos 13 /*!< PORT0 PPS: PPS13 Position */
\r
14316 #define PORT0_PPS_PPS13_Msk (0x01UL << PORT0_PPS_PPS13_Pos) /*!< PORT0 PPS: PPS13 Mask */
\r
14317 #define PORT0_PPS_PPS14_Pos 14 /*!< PORT0 PPS: PPS14 Position */
\r
14318 #define PORT0_PPS_PPS14_Msk (0x01UL << PORT0_PPS_PPS14_Pos) /*!< PORT0 PPS: PPS14 Mask */
\r
14319 #define PORT0_PPS_PPS15_Pos 15 /*!< PORT0 PPS: PPS15 Position */
\r
14320 #define PORT0_PPS_PPS15_Msk (0x01UL << PORT0_PPS_PPS15_Pos) /*!< PORT0 PPS: PPS15 Mask */
\r
14322 /* --------------------------------- PORT0_HWSEL -------------------------------- */
\r
14323 #define PORT0_HWSEL_HW0_Pos 0 /*!< PORT0 HWSEL: HW0 Position */
\r
14324 #define PORT0_HWSEL_HW0_Msk (0x03UL << PORT0_HWSEL_HW0_Pos) /*!< PORT0 HWSEL: HW0 Mask */
\r
14325 #define PORT0_HWSEL_HW1_Pos 2 /*!< PORT0 HWSEL: HW1 Position */
\r
14326 #define PORT0_HWSEL_HW1_Msk (0x03UL << PORT0_HWSEL_HW1_Pos) /*!< PORT0 HWSEL: HW1 Mask */
\r
14327 #define PORT0_HWSEL_HW2_Pos 4 /*!< PORT0 HWSEL: HW2 Position */
\r
14328 #define PORT0_HWSEL_HW2_Msk (0x03UL << PORT0_HWSEL_HW2_Pos) /*!< PORT0 HWSEL: HW2 Mask */
\r
14329 #define PORT0_HWSEL_HW3_Pos 6 /*!< PORT0 HWSEL: HW3 Position */
\r
14330 #define PORT0_HWSEL_HW3_Msk (0x03UL << PORT0_HWSEL_HW3_Pos) /*!< PORT0 HWSEL: HW3 Mask */
\r
14331 #define PORT0_HWSEL_HW4_Pos 8 /*!< PORT0 HWSEL: HW4 Position */
\r
14332 #define PORT0_HWSEL_HW4_Msk (0x03UL << PORT0_HWSEL_HW4_Pos) /*!< PORT0 HWSEL: HW4 Mask */
\r
14333 #define PORT0_HWSEL_HW5_Pos 10 /*!< PORT0 HWSEL: HW5 Position */
\r
14334 #define PORT0_HWSEL_HW5_Msk (0x03UL << PORT0_HWSEL_HW5_Pos) /*!< PORT0 HWSEL: HW5 Mask */
\r
14335 #define PORT0_HWSEL_HW6_Pos 12 /*!< PORT0 HWSEL: HW6 Position */
\r
14336 #define PORT0_HWSEL_HW6_Msk (0x03UL << PORT0_HWSEL_HW6_Pos) /*!< PORT0 HWSEL: HW6 Mask */
\r
14337 #define PORT0_HWSEL_HW7_Pos 14 /*!< PORT0 HWSEL: HW7 Position */
\r
14338 #define PORT0_HWSEL_HW7_Msk (0x03UL << PORT0_HWSEL_HW7_Pos) /*!< PORT0 HWSEL: HW7 Mask */
\r
14339 #define PORT0_HWSEL_HW8_Pos 16 /*!< PORT0 HWSEL: HW8 Position */
\r
14340 #define PORT0_HWSEL_HW8_Msk (0x03UL << PORT0_HWSEL_HW8_Pos) /*!< PORT0 HWSEL: HW8 Mask */
\r
14341 #define PORT0_HWSEL_HW9_Pos 18 /*!< PORT0 HWSEL: HW9 Position */
\r
14342 #define PORT0_HWSEL_HW9_Msk (0x03UL << PORT0_HWSEL_HW9_Pos) /*!< PORT0 HWSEL: HW9 Mask */
\r
14343 #define PORT0_HWSEL_HW10_Pos 20 /*!< PORT0 HWSEL: HW10 Position */
\r
14344 #define PORT0_HWSEL_HW10_Msk (0x03UL << PORT0_HWSEL_HW10_Pos) /*!< PORT0 HWSEL: HW10 Mask */
\r
14345 #define PORT0_HWSEL_HW11_Pos 22 /*!< PORT0 HWSEL: HW11 Position */
\r
14346 #define PORT0_HWSEL_HW11_Msk (0x03UL << PORT0_HWSEL_HW11_Pos) /*!< PORT0 HWSEL: HW11 Mask */
\r
14347 #define PORT0_HWSEL_HW12_Pos 24 /*!< PORT0 HWSEL: HW12 Position */
\r
14348 #define PORT0_HWSEL_HW12_Msk (0x03UL << PORT0_HWSEL_HW12_Pos) /*!< PORT0 HWSEL: HW12 Mask */
\r
14349 #define PORT0_HWSEL_HW13_Pos 26 /*!< PORT0 HWSEL: HW13 Position */
\r
14350 #define PORT0_HWSEL_HW13_Msk (0x03UL << PORT0_HWSEL_HW13_Pos) /*!< PORT0 HWSEL: HW13 Mask */
\r
14351 #define PORT0_HWSEL_HW14_Pos 28 /*!< PORT0 HWSEL: HW14 Position */
\r
14352 #define PORT0_HWSEL_HW14_Msk (0x03UL << PORT0_HWSEL_HW14_Pos) /*!< PORT0 HWSEL: HW14 Mask */
\r
14353 #define PORT0_HWSEL_HW15_Pos 30 /*!< PORT0 HWSEL: HW15 Position */
\r
14354 #define PORT0_HWSEL_HW15_Msk (0x03UL << PORT0_HWSEL_HW15_Pos) /*!< PORT0 HWSEL: HW15 Mask */
\r
14357 /* ================================================================================ */
\r
14358 /* ================ struct 'PORT1' Position & Mask ================ */
\r
14359 /* ================================================================================ */
\r
14362 /* ---------------------------------- PORT1_OUT --------------------------------- */
\r
14363 #define PORT1_OUT_P0_Pos 0 /*!< PORT1 OUT: P0 Position */
\r
14364 #define PORT1_OUT_P0_Msk (0x01UL << PORT1_OUT_P0_Pos) /*!< PORT1 OUT: P0 Mask */
\r
14365 #define PORT1_OUT_P1_Pos 1 /*!< PORT1 OUT: P1 Position */
\r
14366 #define PORT1_OUT_P1_Msk (0x01UL << PORT1_OUT_P1_Pos) /*!< PORT1 OUT: P1 Mask */
\r
14367 #define PORT1_OUT_P2_Pos 2 /*!< PORT1 OUT: P2 Position */
\r
14368 #define PORT1_OUT_P2_Msk (0x01UL << PORT1_OUT_P2_Pos) /*!< PORT1 OUT: P2 Mask */
\r
14369 #define PORT1_OUT_P3_Pos 3 /*!< PORT1 OUT: P3 Position */
\r
14370 #define PORT1_OUT_P3_Msk (0x01UL << PORT1_OUT_P3_Pos) /*!< PORT1 OUT: P3 Mask */
\r
14371 #define PORT1_OUT_P4_Pos 4 /*!< PORT1 OUT: P4 Position */
\r
14372 #define PORT1_OUT_P4_Msk (0x01UL << PORT1_OUT_P4_Pos) /*!< PORT1 OUT: P4 Mask */
\r
14373 #define PORT1_OUT_P5_Pos 5 /*!< PORT1 OUT: P5 Position */
\r
14374 #define PORT1_OUT_P5_Msk (0x01UL << PORT1_OUT_P5_Pos) /*!< PORT1 OUT: P5 Mask */
\r
14375 #define PORT1_OUT_P6_Pos 6 /*!< PORT1 OUT: P6 Position */
\r
14376 #define PORT1_OUT_P6_Msk (0x01UL << PORT1_OUT_P6_Pos) /*!< PORT1 OUT: P6 Mask */
\r
14377 #define PORT1_OUT_P7_Pos 7 /*!< PORT1 OUT: P7 Position */
\r
14378 #define PORT1_OUT_P7_Msk (0x01UL << PORT1_OUT_P7_Pos) /*!< PORT1 OUT: P7 Mask */
\r
14379 #define PORT1_OUT_P8_Pos 8 /*!< PORT1 OUT: P8 Position */
\r
14380 #define PORT1_OUT_P8_Msk (0x01UL << PORT1_OUT_P8_Pos) /*!< PORT1 OUT: P8 Mask */
\r
14381 #define PORT1_OUT_P9_Pos 9 /*!< PORT1 OUT: P9 Position */
\r
14382 #define PORT1_OUT_P9_Msk (0x01UL << PORT1_OUT_P9_Pos) /*!< PORT1 OUT: P9 Mask */
\r
14383 #define PORT1_OUT_P10_Pos 10 /*!< PORT1 OUT: P10 Position */
\r
14384 #define PORT1_OUT_P10_Msk (0x01UL << PORT1_OUT_P10_Pos) /*!< PORT1 OUT: P10 Mask */
\r
14385 #define PORT1_OUT_P11_Pos 11 /*!< PORT1 OUT: P11 Position */
\r
14386 #define PORT1_OUT_P11_Msk (0x01UL << PORT1_OUT_P11_Pos) /*!< PORT1 OUT: P11 Mask */
\r
14387 #define PORT1_OUT_P12_Pos 12 /*!< PORT1 OUT: P12 Position */
\r
14388 #define PORT1_OUT_P12_Msk (0x01UL << PORT1_OUT_P12_Pos) /*!< PORT1 OUT: P12 Mask */
\r
14389 #define PORT1_OUT_P13_Pos 13 /*!< PORT1 OUT: P13 Position */
\r
14390 #define PORT1_OUT_P13_Msk (0x01UL << PORT1_OUT_P13_Pos) /*!< PORT1 OUT: P13 Mask */
\r
14391 #define PORT1_OUT_P14_Pos 14 /*!< PORT1 OUT: P14 Position */
\r
14392 #define PORT1_OUT_P14_Msk (0x01UL << PORT1_OUT_P14_Pos) /*!< PORT1 OUT: P14 Mask */
\r
14393 #define PORT1_OUT_P15_Pos 15 /*!< PORT1 OUT: P15 Position */
\r
14394 #define PORT1_OUT_P15_Msk (0x01UL << PORT1_OUT_P15_Pos) /*!< PORT1 OUT: P15 Mask */
\r
14396 /* ---------------------------------- PORT1_OMR --------------------------------- */
\r
14397 #define PORT1_OMR_PS0_Pos 0 /*!< PORT1 OMR: PS0 Position */
\r
14398 #define PORT1_OMR_PS0_Msk (0x01UL << PORT1_OMR_PS0_Pos) /*!< PORT1 OMR: PS0 Mask */
\r
14399 #define PORT1_OMR_PS1_Pos 1 /*!< PORT1 OMR: PS1 Position */
\r
14400 #define PORT1_OMR_PS1_Msk (0x01UL << PORT1_OMR_PS1_Pos) /*!< PORT1 OMR: PS1 Mask */
\r
14401 #define PORT1_OMR_PS2_Pos 2 /*!< PORT1 OMR: PS2 Position */
\r
14402 #define PORT1_OMR_PS2_Msk (0x01UL << PORT1_OMR_PS2_Pos) /*!< PORT1 OMR: PS2 Mask */
\r
14403 #define PORT1_OMR_PS3_Pos 3 /*!< PORT1 OMR: PS3 Position */
\r
14404 #define PORT1_OMR_PS3_Msk (0x01UL << PORT1_OMR_PS3_Pos) /*!< PORT1 OMR: PS3 Mask */
\r
14405 #define PORT1_OMR_PS4_Pos 4 /*!< PORT1 OMR: PS4 Position */
\r
14406 #define PORT1_OMR_PS4_Msk (0x01UL << PORT1_OMR_PS4_Pos) /*!< PORT1 OMR: PS4 Mask */
\r
14407 #define PORT1_OMR_PS5_Pos 5 /*!< PORT1 OMR: PS5 Position */
\r
14408 #define PORT1_OMR_PS5_Msk (0x01UL << PORT1_OMR_PS5_Pos) /*!< PORT1 OMR: PS5 Mask */
\r
14409 #define PORT1_OMR_PS6_Pos 6 /*!< PORT1 OMR: PS6 Position */
\r
14410 #define PORT1_OMR_PS6_Msk (0x01UL << PORT1_OMR_PS6_Pos) /*!< PORT1 OMR: PS6 Mask */
\r
14411 #define PORT1_OMR_PS7_Pos 7 /*!< PORT1 OMR: PS7 Position */
\r
14412 #define PORT1_OMR_PS7_Msk (0x01UL << PORT1_OMR_PS7_Pos) /*!< PORT1 OMR: PS7 Mask */
\r
14413 #define PORT1_OMR_PS8_Pos 8 /*!< PORT1 OMR: PS8 Position */
\r
14414 #define PORT1_OMR_PS8_Msk (0x01UL << PORT1_OMR_PS8_Pos) /*!< PORT1 OMR: PS8 Mask */
\r
14415 #define PORT1_OMR_PS9_Pos 9 /*!< PORT1 OMR: PS9 Position */
\r
14416 #define PORT1_OMR_PS9_Msk (0x01UL << PORT1_OMR_PS9_Pos) /*!< PORT1 OMR: PS9 Mask */
\r
14417 #define PORT1_OMR_PS10_Pos 10 /*!< PORT1 OMR: PS10 Position */
\r
14418 #define PORT1_OMR_PS10_Msk (0x01UL << PORT1_OMR_PS10_Pos) /*!< PORT1 OMR: PS10 Mask */
\r
14419 #define PORT1_OMR_PS11_Pos 11 /*!< PORT1 OMR: PS11 Position */
\r
14420 #define PORT1_OMR_PS11_Msk (0x01UL << PORT1_OMR_PS11_Pos) /*!< PORT1 OMR: PS11 Mask */
\r
14421 #define PORT1_OMR_PS12_Pos 12 /*!< PORT1 OMR: PS12 Position */
\r
14422 #define PORT1_OMR_PS12_Msk (0x01UL << PORT1_OMR_PS12_Pos) /*!< PORT1 OMR: PS12 Mask */
\r
14423 #define PORT1_OMR_PS13_Pos 13 /*!< PORT1 OMR: PS13 Position */
\r
14424 #define PORT1_OMR_PS13_Msk (0x01UL << PORT1_OMR_PS13_Pos) /*!< PORT1 OMR: PS13 Mask */
\r
14425 #define PORT1_OMR_PS14_Pos 14 /*!< PORT1 OMR: PS14 Position */
\r
14426 #define PORT1_OMR_PS14_Msk (0x01UL << PORT1_OMR_PS14_Pos) /*!< PORT1 OMR: PS14 Mask */
\r
14427 #define PORT1_OMR_PS15_Pos 15 /*!< PORT1 OMR: PS15 Position */
\r
14428 #define PORT1_OMR_PS15_Msk (0x01UL << PORT1_OMR_PS15_Pos) /*!< PORT1 OMR: PS15 Mask */
\r
14429 #define PORT1_OMR_PR0_Pos 16 /*!< PORT1 OMR: PR0 Position */
\r
14430 #define PORT1_OMR_PR0_Msk (0x01UL << PORT1_OMR_PR0_Pos) /*!< PORT1 OMR: PR0 Mask */
\r
14431 #define PORT1_OMR_PR1_Pos 17 /*!< PORT1 OMR: PR1 Position */
\r
14432 #define PORT1_OMR_PR1_Msk (0x01UL << PORT1_OMR_PR1_Pos) /*!< PORT1 OMR: PR1 Mask */
\r
14433 #define PORT1_OMR_PR2_Pos 18 /*!< PORT1 OMR: PR2 Position */
\r
14434 #define PORT1_OMR_PR2_Msk (0x01UL << PORT1_OMR_PR2_Pos) /*!< PORT1 OMR: PR2 Mask */
\r
14435 #define PORT1_OMR_PR3_Pos 19 /*!< PORT1 OMR: PR3 Position */
\r
14436 #define PORT1_OMR_PR3_Msk (0x01UL << PORT1_OMR_PR3_Pos) /*!< PORT1 OMR: PR3 Mask */
\r
14437 #define PORT1_OMR_PR4_Pos 20 /*!< PORT1 OMR: PR4 Position */
\r
14438 #define PORT1_OMR_PR4_Msk (0x01UL << PORT1_OMR_PR4_Pos) /*!< PORT1 OMR: PR4 Mask */
\r
14439 #define PORT1_OMR_PR5_Pos 21 /*!< PORT1 OMR: PR5 Position */
\r
14440 #define PORT1_OMR_PR5_Msk (0x01UL << PORT1_OMR_PR5_Pos) /*!< PORT1 OMR: PR5 Mask */
\r
14441 #define PORT1_OMR_PR6_Pos 22 /*!< PORT1 OMR: PR6 Position */
\r
14442 #define PORT1_OMR_PR6_Msk (0x01UL << PORT1_OMR_PR6_Pos) /*!< PORT1 OMR: PR6 Mask */
\r
14443 #define PORT1_OMR_PR7_Pos 23 /*!< PORT1 OMR: PR7 Position */
\r
14444 #define PORT1_OMR_PR7_Msk (0x01UL << PORT1_OMR_PR7_Pos) /*!< PORT1 OMR: PR7 Mask */
\r
14445 #define PORT1_OMR_PR8_Pos 24 /*!< PORT1 OMR: PR8 Position */
\r
14446 #define PORT1_OMR_PR8_Msk (0x01UL << PORT1_OMR_PR8_Pos) /*!< PORT1 OMR: PR8 Mask */
\r
14447 #define PORT1_OMR_PR9_Pos 25 /*!< PORT1 OMR: PR9 Position */
\r
14448 #define PORT1_OMR_PR9_Msk (0x01UL << PORT1_OMR_PR9_Pos) /*!< PORT1 OMR: PR9 Mask */
\r
14449 #define PORT1_OMR_PR10_Pos 26 /*!< PORT1 OMR: PR10 Position */
\r
14450 #define PORT1_OMR_PR10_Msk (0x01UL << PORT1_OMR_PR10_Pos) /*!< PORT1 OMR: PR10 Mask */
\r
14451 #define PORT1_OMR_PR11_Pos 27 /*!< PORT1 OMR: PR11 Position */
\r
14452 #define PORT1_OMR_PR11_Msk (0x01UL << PORT1_OMR_PR11_Pos) /*!< PORT1 OMR: PR11 Mask */
\r
14453 #define PORT1_OMR_PR12_Pos 28 /*!< PORT1 OMR: PR12 Position */
\r
14454 #define PORT1_OMR_PR12_Msk (0x01UL << PORT1_OMR_PR12_Pos) /*!< PORT1 OMR: PR12 Mask */
\r
14455 #define PORT1_OMR_PR13_Pos 29 /*!< PORT1 OMR: PR13 Position */
\r
14456 #define PORT1_OMR_PR13_Msk (0x01UL << PORT1_OMR_PR13_Pos) /*!< PORT1 OMR: PR13 Mask */
\r
14457 #define PORT1_OMR_PR14_Pos 30 /*!< PORT1 OMR: PR14 Position */
\r
14458 #define PORT1_OMR_PR14_Msk (0x01UL << PORT1_OMR_PR14_Pos) /*!< PORT1 OMR: PR14 Mask */
\r
14459 #define PORT1_OMR_PR15_Pos 31 /*!< PORT1 OMR: PR15 Position */
\r
14460 #define PORT1_OMR_PR15_Msk (0x01UL << PORT1_OMR_PR15_Pos) /*!< PORT1 OMR: PR15 Mask */
\r
14462 /* --------------------------------- PORT1_IOCR0 -------------------------------- */
\r
14463 #define PORT1_IOCR0_PC0_Pos 3 /*!< PORT1 IOCR0: PC0 Position */
\r
14464 #define PORT1_IOCR0_PC0_Msk (0x1fUL << PORT1_IOCR0_PC0_Pos) /*!< PORT1 IOCR0: PC0 Mask */
\r
14465 #define PORT1_IOCR0_PC1_Pos 11 /*!< PORT1 IOCR0: PC1 Position */
\r
14466 #define PORT1_IOCR0_PC1_Msk (0x1fUL << PORT1_IOCR0_PC1_Pos) /*!< PORT1 IOCR0: PC1 Mask */
\r
14467 #define PORT1_IOCR0_PC2_Pos 19 /*!< PORT1 IOCR0: PC2 Position */
\r
14468 #define PORT1_IOCR0_PC2_Msk (0x1fUL << PORT1_IOCR0_PC2_Pos) /*!< PORT1 IOCR0: PC2 Mask */
\r
14469 #define PORT1_IOCR0_PC3_Pos 27 /*!< PORT1 IOCR0: PC3 Position */
\r
14470 #define PORT1_IOCR0_PC3_Msk (0x1fUL << PORT1_IOCR0_PC3_Pos) /*!< PORT1 IOCR0: PC3 Mask */
\r
14472 /* --------------------------------- PORT1_IOCR4 -------------------------------- */
\r
14473 #define PORT1_IOCR4_PC4_Pos 3 /*!< PORT1 IOCR4: PC4 Position */
\r
14474 #define PORT1_IOCR4_PC4_Msk (0x1fUL << PORT1_IOCR4_PC4_Pos) /*!< PORT1 IOCR4: PC4 Mask */
\r
14475 #define PORT1_IOCR4_PC5_Pos 11 /*!< PORT1 IOCR4: PC5 Position */
\r
14476 #define PORT1_IOCR4_PC5_Msk (0x1fUL << PORT1_IOCR4_PC5_Pos) /*!< PORT1 IOCR4: PC5 Mask */
\r
14477 #define PORT1_IOCR4_PC6_Pos 19 /*!< PORT1 IOCR4: PC6 Position */
\r
14478 #define PORT1_IOCR4_PC6_Msk (0x1fUL << PORT1_IOCR4_PC6_Pos) /*!< PORT1 IOCR4: PC6 Mask */
\r
14479 #define PORT1_IOCR4_PC7_Pos 27 /*!< PORT1 IOCR4: PC7 Position */
\r
14480 #define PORT1_IOCR4_PC7_Msk (0x1fUL << PORT1_IOCR4_PC7_Pos) /*!< PORT1 IOCR4: PC7 Mask */
\r
14482 /* --------------------------------- PORT1_IOCR8 -------------------------------- */
\r
14483 #define PORT1_IOCR8_PC8_Pos 3 /*!< PORT1 IOCR8: PC8 Position */
\r
14484 #define PORT1_IOCR8_PC8_Msk (0x1fUL << PORT1_IOCR8_PC8_Pos) /*!< PORT1 IOCR8: PC8 Mask */
\r
14485 #define PORT1_IOCR8_PC9_Pos 11 /*!< PORT1 IOCR8: PC9 Position */
\r
14486 #define PORT1_IOCR8_PC9_Msk (0x1fUL << PORT1_IOCR8_PC9_Pos) /*!< PORT1 IOCR8: PC9 Mask */
\r
14487 #define PORT1_IOCR8_PC10_Pos 19 /*!< PORT1 IOCR8: PC10 Position */
\r
14488 #define PORT1_IOCR8_PC10_Msk (0x1fUL << PORT1_IOCR8_PC10_Pos) /*!< PORT1 IOCR8: PC10 Mask */
\r
14489 #define PORT1_IOCR8_PC11_Pos 27 /*!< PORT1 IOCR8: PC11 Position */
\r
14490 #define PORT1_IOCR8_PC11_Msk (0x1fUL << PORT1_IOCR8_PC11_Pos) /*!< PORT1 IOCR8: PC11 Mask */
\r
14492 /* -------------------------------- PORT1_IOCR12 -------------------------------- */
\r
14493 #define PORT1_IOCR12_PC12_Pos 3 /*!< PORT1 IOCR12: PC12 Position */
\r
14494 #define PORT1_IOCR12_PC12_Msk (0x1fUL << PORT1_IOCR12_PC12_Pos) /*!< PORT1 IOCR12: PC12 Mask */
\r
14495 #define PORT1_IOCR12_PC13_Pos 11 /*!< PORT1 IOCR12: PC13 Position */
\r
14496 #define PORT1_IOCR12_PC13_Msk (0x1fUL << PORT1_IOCR12_PC13_Pos) /*!< PORT1 IOCR12: PC13 Mask */
\r
14497 #define PORT1_IOCR12_PC14_Pos 19 /*!< PORT1 IOCR12: PC14 Position */
\r
14498 #define PORT1_IOCR12_PC14_Msk (0x1fUL << PORT1_IOCR12_PC14_Pos) /*!< PORT1 IOCR12: PC14 Mask */
\r
14499 #define PORT1_IOCR12_PC15_Pos 27 /*!< PORT1 IOCR12: PC15 Position */
\r
14500 #define PORT1_IOCR12_PC15_Msk (0x1fUL << PORT1_IOCR12_PC15_Pos) /*!< PORT1 IOCR12: PC15 Mask */
\r
14502 /* ---------------------------------- PORT1_IN ---------------------------------- */
\r
14503 #define PORT1_IN_P0_Pos 0 /*!< PORT1 IN: P0 Position */
\r
14504 #define PORT1_IN_P0_Msk (0x01UL << PORT1_IN_P0_Pos) /*!< PORT1 IN: P0 Mask */
\r
14505 #define PORT1_IN_P1_Pos 1 /*!< PORT1 IN: P1 Position */
\r
14506 #define PORT1_IN_P1_Msk (0x01UL << PORT1_IN_P1_Pos) /*!< PORT1 IN: P1 Mask */
\r
14507 #define PORT1_IN_P2_Pos 2 /*!< PORT1 IN: P2 Position */
\r
14508 #define PORT1_IN_P2_Msk (0x01UL << PORT1_IN_P2_Pos) /*!< PORT1 IN: P2 Mask */
\r
14509 #define PORT1_IN_P3_Pos 3 /*!< PORT1 IN: P3 Position */
\r
14510 #define PORT1_IN_P3_Msk (0x01UL << PORT1_IN_P3_Pos) /*!< PORT1 IN: P3 Mask */
\r
14511 #define PORT1_IN_P4_Pos 4 /*!< PORT1 IN: P4 Position */
\r
14512 #define PORT1_IN_P4_Msk (0x01UL << PORT1_IN_P4_Pos) /*!< PORT1 IN: P4 Mask */
\r
14513 #define PORT1_IN_P5_Pos 5 /*!< PORT1 IN: P5 Position */
\r
14514 #define PORT1_IN_P5_Msk (0x01UL << PORT1_IN_P5_Pos) /*!< PORT1 IN: P5 Mask */
\r
14515 #define PORT1_IN_P6_Pos 6 /*!< PORT1 IN: P6 Position */
\r
14516 #define PORT1_IN_P6_Msk (0x01UL << PORT1_IN_P6_Pos) /*!< PORT1 IN: P6 Mask */
\r
14517 #define PORT1_IN_P7_Pos 7 /*!< PORT1 IN: P7 Position */
\r
14518 #define PORT1_IN_P7_Msk (0x01UL << PORT1_IN_P7_Pos) /*!< PORT1 IN: P7 Mask */
\r
14519 #define PORT1_IN_P8_Pos 8 /*!< PORT1 IN: P8 Position */
\r
14520 #define PORT1_IN_P8_Msk (0x01UL << PORT1_IN_P8_Pos) /*!< PORT1 IN: P8 Mask */
\r
14521 #define PORT1_IN_P9_Pos 9 /*!< PORT1 IN: P9 Position */
\r
14522 #define PORT1_IN_P9_Msk (0x01UL << PORT1_IN_P9_Pos) /*!< PORT1 IN: P9 Mask */
\r
14523 #define PORT1_IN_P10_Pos 10 /*!< PORT1 IN: P10 Position */
\r
14524 #define PORT1_IN_P10_Msk (0x01UL << PORT1_IN_P10_Pos) /*!< PORT1 IN: P10 Mask */
\r
14525 #define PORT1_IN_P11_Pos 11 /*!< PORT1 IN: P11 Position */
\r
14526 #define PORT1_IN_P11_Msk (0x01UL << PORT1_IN_P11_Pos) /*!< PORT1 IN: P11 Mask */
\r
14527 #define PORT1_IN_P12_Pos 12 /*!< PORT1 IN: P12 Position */
\r
14528 #define PORT1_IN_P12_Msk (0x01UL << PORT1_IN_P12_Pos) /*!< PORT1 IN: P12 Mask */
\r
14529 #define PORT1_IN_P13_Pos 13 /*!< PORT1 IN: P13 Position */
\r
14530 #define PORT1_IN_P13_Msk (0x01UL << PORT1_IN_P13_Pos) /*!< PORT1 IN: P13 Mask */
\r
14531 #define PORT1_IN_P14_Pos 14 /*!< PORT1 IN: P14 Position */
\r
14532 #define PORT1_IN_P14_Msk (0x01UL << PORT1_IN_P14_Pos) /*!< PORT1 IN: P14 Mask */
\r
14533 #define PORT1_IN_P15_Pos 15 /*!< PORT1 IN: P15 Position */
\r
14534 #define PORT1_IN_P15_Msk (0x01UL << PORT1_IN_P15_Pos) /*!< PORT1 IN: P15 Mask */
\r
14536 /* --------------------------------- PORT1_PDR0 --------------------------------- */
\r
14537 #define PORT1_PDR0_PD0_Pos 0 /*!< PORT1 PDR0: PD0 Position */
\r
14538 #define PORT1_PDR0_PD0_Msk (0x07UL << PORT1_PDR0_PD0_Pos) /*!< PORT1 PDR0: PD0 Mask */
\r
14539 #define PORT1_PDR0_PD1_Pos 4 /*!< PORT1 PDR0: PD1 Position */
\r
14540 #define PORT1_PDR0_PD1_Msk (0x07UL << PORT1_PDR0_PD1_Pos) /*!< PORT1 PDR0: PD1 Mask */
\r
14541 #define PORT1_PDR0_PD2_Pos 8 /*!< PORT1 PDR0: PD2 Position */
\r
14542 #define PORT1_PDR0_PD2_Msk (0x07UL << PORT1_PDR0_PD2_Pos) /*!< PORT1 PDR0: PD2 Mask */
\r
14543 #define PORT1_PDR0_PD3_Pos 12 /*!< PORT1 PDR0: PD3 Position */
\r
14544 #define PORT1_PDR0_PD3_Msk (0x07UL << PORT1_PDR0_PD3_Pos) /*!< PORT1 PDR0: PD3 Mask */
\r
14545 #define PORT1_PDR0_PD4_Pos 16 /*!< PORT1 PDR0: PD4 Position */
\r
14546 #define PORT1_PDR0_PD4_Msk (0x07UL << PORT1_PDR0_PD4_Pos) /*!< PORT1 PDR0: PD4 Mask */
\r
14547 #define PORT1_PDR0_PD5_Pos 20 /*!< PORT1 PDR0: PD5 Position */
\r
14548 #define PORT1_PDR0_PD5_Msk (0x07UL << PORT1_PDR0_PD5_Pos) /*!< PORT1 PDR0: PD5 Mask */
\r
14549 #define PORT1_PDR0_PD6_Pos 24 /*!< PORT1 PDR0: PD6 Position */
\r
14550 #define PORT1_PDR0_PD6_Msk (0x07UL << PORT1_PDR0_PD6_Pos) /*!< PORT1 PDR0: PD6 Mask */
\r
14551 #define PORT1_PDR0_PD7_Pos 28 /*!< PORT1 PDR0: PD7 Position */
\r
14552 #define PORT1_PDR0_PD7_Msk (0x07UL << PORT1_PDR0_PD7_Pos) /*!< PORT1 PDR0: PD7 Mask */
\r
14554 /* --------------------------------- PORT1_PDR1 --------------------------------- */
\r
14555 #define PORT1_PDR1_PD8_Pos 0 /*!< PORT1 PDR1: PD8 Position */
\r
14556 #define PORT1_PDR1_PD8_Msk (0x07UL << PORT1_PDR1_PD8_Pos) /*!< PORT1 PDR1: PD8 Mask */
\r
14557 #define PORT1_PDR1_PD9_Pos 4 /*!< PORT1 PDR1: PD9 Position */
\r
14558 #define PORT1_PDR1_PD9_Msk (0x07UL << PORT1_PDR1_PD9_Pos) /*!< PORT1 PDR1: PD9 Mask */
\r
14559 #define PORT1_PDR1_PD10_Pos 8 /*!< PORT1 PDR1: PD10 Position */
\r
14560 #define PORT1_PDR1_PD10_Msk (0x07UL << PORT1_PDR1_PD10_Pos) /*!< PORT1 PDR1: PD10 Mask */
\r
14561 #define PORT1_PDR1_PD11_Pos 12 /*!< PORT1 PDR1: PD11 Position */
\r
14562 #define PORT1_PDR1_PD11_Msk (0x07UL << PORT1_PDR1_PD11_Pos) /*!< PORT1 PDR1: PD11 Mask */
\r
14563 #define PORT1_PDR1_PD12_Pos 16 /*!< PORT1 PDR1: PD12 Position */
\r
14564 #define PORT1_PDR1_PD12_Msk (0x07UL << PORT1_PDR1_PD12_Pos) /*!< PORT1 PDR1: PD12 Mask */
\r
14565 #define PORT1_PDR1_PD13_Pos 20 /*!< PORT1 PDR1: PD13 Position */
\r
14566 #define PORT1_PDR1_PD13_Msk (0x07UL << PORT1_PDR1_PD13_Pos) /*!< PORT1 PDR1: PD13 Mask */
\r
14567 #define PORT1_PDR1_PD14_Pos 24 /*!< PORT1 PDR1: PD14 Position */
\r
14568 #define PORT1_PDR1_PD14_Msk (0x07UL << PORT1_PDR1_PD14_Pos) /*!< PORT1 PDR1: PD14 Mask */
\r
14569 #define PORT1_PDR1_PD15_Pos 28 /*!< PORT1 PDR1: PD15 Position */
\r
14570 #define PORT1_PDR1_PD15_Msk (0x07UL << PORT1_PDR1_PD15_Pos) /*!< PORT1 PDR1: PD15 Mask */
\r
14572 /* --------------------------------- PORT1_PDISC -------------------------------- */
\r
14573 #define PORT1_PDISC_PDIS0_Pos 0 /*!< PORT1 PDISC: PDIS0 Position */
\r
14574 #define PORT1_PDISC_PDIS0_Msk (0x01UL << PORT1_PDISC_PDIS0_Pos) /*!< PORT1 PDISC: PDIS0 Mask */
\r
14575 #define PORT1_PDISC_PDIS1_Pos 1 /*!< PORT1 PDISC: PDIS1 Position */
\r
14576 #define PORT1_PDISC_PDIS1_Msk (0x01UL << PORT1_PDISC_PDIS1_Pos) /*!< PORT1 PDISC: PDIS1 Mask */
\r
14577 #define PORT1_PDISC_PDIS2_Pos 2 /*!< PORT1 PDISC: PDIS2 Position */
\r
14578 #define PORT1_PDISC_PDIS2_Msk (0x01UL << PORT1_PDISC_PDIS2_Pos) /*!< PORT1 PDISC: PDIS2 Mask */
\r
14579 #define PORT1_PDISC_PDIS3_Pos 3 /*!< PORT1 PDISC: PDIS3 Position */
\r
14580 #define PORT1_PDISC_PDIS3_Msk (0x01UL << PORT1_PDISC_PDIS3_Pos) /*!< PORT1 PDISC: PDIS3 Mask */
\r
14581 #define PORT1_PDISC_PDIS4_Pos 4 /*!< PORT1 PDISC: PDIS4 Position */
\r
14582 #define PORT1_PDISC_PDIS4_Msk (0x01UL << PORT1_PDISC_PDIS4_Pos) /*!< PORT1 PDISC: PDIS4 Mask */
\r
14583 #define PORT1_PDISC_PDIS5_Pos 5 /*!< PORT1 PDISC: PDIS5 Position */
\r
14584 #define PORT1_PDISC_PDIS5_Msk (0x01UL << PORT1_PDISC_PDIS5_Pos) /*!< PORT1 PDISC: PDIS5 Mask */
\r
14585 #define PORT1_PDISC_PDIS6_Pos 6 /*!< PORT1 PDISC: PDIS6 Position */
\r
14586 #define PORT1_PDISC_PDIS6_Msk (0x01UL << PORT1_PDISC_PDIS6_Pos) /*!< PORT1 PDISC: PDIS6 Mask */
\r
14587 #define PORT1_PDISC_PDIS7_Pos 7 /*!< PORT1 PDISC: PDIS7 Position */
\r
14588 #define PORT1_PDISC_PDIS7_Msk (0x01UL << PORT1_PDISC_PDIS7_Pos) /*!< PORT1 PDISC: PDIS7 Mask */
\r
14589 #define PORT1_PDISC_PDIS8_Pos 8 /*!< PORT1 PDISC: PDIS8 Position */
\r
14590 #define PORT1_PDISC_PDIS8_Msk (0x01UL << PORT1_PDISC_PDIS8_Pos) /*!< PORT1 PDISC: PDIS8 Mask */
\r
14591 #define PORT1_PDISC_PDIS9_Pos 9 /*!< PORT1 PDISC: PDIS9 Position */
\r
14592 #define PORT1_PDISC_PDIS9_Msk (0x01UL << PORT1_PDISC_PDIS9_Pos) /*!< PORT1 PDISC: PDIS9 Mask */
\r
14593 #define PORT1_PDISC_PDIS10_Pos 10 /*!< PORT1 PDISC: PDIS10 Position */
\r
14594 #define PORT1_PDISC_PDIS10_Msk (0x01UL << PORT1_PDISC_PDIS10_Pos) /*!< PORT1 PDISC: PDIS10 Mask */
\r
14595 #define PORT1_PDISC_PDIS11_Pos 11 /*!< PORT1 PDISC: PDIS11 Position */
\r
14596 #define PORT1_PDISC_PDIS11_Msk (0x01UL << PORT1_PDISC_PDIS11_Pos) /*!< PORT1 PDISC: PDIS11 Mask */
\r
14597 #define PORT1_PDISC_PDIS12_Pos 12 /*!< PORT1 PDISC: PDIS12 Position */
\r
14598 #define PORT1_PDISC_PDIS12_Msk (0x01UL << PORT1_PDISC_PDIS12_Pos) /*!< PORT1 PDISC: PDIS12 Mask */
\r
14599 #define PORT1_PDISC_PDIS13_Pos 13 /*!< PORT1 PDISC: PDIS13 Position */
\r
14600 #define PORT1_PDISC_PDIS13_Msk (0x01UL << PORT1_PDISC_PDIS13_Pos) /*!< PORT1 PDISC: PDIS13 Mask */
\r
14601 #define PORT1_PDISC_PDIS14_Pos 14 /*!< PORT1 PDISC: PDIS14 Position */
\r
14602 #define PORT1_PDISC_PDIS14_Msk (0x01UL << PORT1_PDISC_PDIS14_Pos) /*!< PORT1 PDISC: PDIS14 Mask */
\r
14603 #define PORT1_PDISC_PDIS15_Pos 15 /*!< PORT1 PDISC: PDIS15 Position */
\r
14604 #define PORT1_PDISC_PDIS15_Msk (0x01UL << PORT1_PDISC_PDIS15_Pos) /*!< PORT1 PDISC: PDIS15 Mask */
\r
14606 /* ---------------------------------- PORT1_PPS --------------------------------- */
\r
14607 #define PORT1_PPS_PPS0_Pos 0 /*!< PORT1 PPS: PPS0 Position */
\r
14608 #define PORT1_PPS_PPS0_Msk (0x01UL << PORT1_PPS_PPS0_Pos) /*!< PORT1 PPS: PPS0 Mask */
\r
14609 #define PORT1_PPS_PPS1_Pos 1 /*!< PORT1 PPS: PPS1 Position */
\r
14610 #define PORT1_PPS_PPS1_Msk (0x01UL << PORT1_PPS_PPS1_Pos) /*!< PORT1 PPS: PPS1 Mask */
\r
14611 #define PORT1_PPS_PPS2_Pos 2 /*!< PORT1 PPS: PPS2 Position */
\r
14612 #define PORT1_PPS_PPS2_Msk (0x01UL << PORT1_PPS_PPS2_Pos) /*!< PORT1 PPS: PPS2 Mask */
\r
14613 #define PORT1_PPS_PPS3_Pos 3 /*!< PORT1 PPS: PPS3 Position */
\r
14614 #define PORT1_PPS_PPS3_Msk (0x01UL << PORT1_PPS_PPS3_Pos) /*!< PORT1 PPS: PPS3 Mask */
\r
14615 #define PORT1_PPS_PPS4_Pos 4 /*!< PORT1 PPS: PPS4 Position */
\r
14616 #define PORT1_PPS_PPS4_Msk (0x01UL << PORT1_PPS_PPS4_Pos) /*!< PORT1 PPS: PPS4 Mask */
\r
14617 #define PORT1_PPS_PPS5_Pos 5 /*!< PORT1 PPS: PPS5 Position */
\r
14618 #define PORT1_PPS_PPS5_Msk (0x01UL << PORT1_PPS_PPS5_Pos) /*!< PORT1 PPS: PPS5 Mask */
\r
14619 #define PORT1_PPS_PPS6_Pos 6 /*!< PORT1 PPS: PPS6 Position */
\r
14620 #define PORT1_PPS_PPS6_Msk (0x01UL << PORT1_PPS_PPS6_Pos) /*!< PORT1 PPS: PPS6 Mask */
\r
14621 #define PORT1_PPS_PPS7_Pos 7 /*!< PORT1 PPS: PPS7 Position */
\r
14622 #define PORT1_PPS_PPS7_Msk (0x01UL << PORT1_PPS_PPS7_Pos) /*!< PORT1 PPS: PPS7 Mask */
\r
14623 #define PORT1_PPS_PPS8_Pos 8 /*!< PORT1 PPS: PPS8 Position */
\r
14624 #define PORT1_PPS_PPS8_Msk (0x01UL << PORT1_PPS_PPS8_Pos) /*!< PORT1 PPS: PPS8 Mask */
\r
14625 #define PORT1_PPS_PPS9_Pos 9 /*!< PORT1 PPS: PPS9 Position */
\r
14626 #define PORT1_PPS_PPS9_Msk (0x01UL << PORT1_PPS_PPS9_Pos) /*!< PORT1 PPS: PPS9 Mask */
\r
14627 #define PORT1_PPS_PPS10_Pos 10 /*!< PORT1 PPS: PPS10 Position */
\r
14628 #define PORT1_PPS_PPS10_Msk (0x01UL << PORT1_PPS_PPS10_Pos) /*!< PORT1 PPS: PPS10 Mask */
\r
14629 #define PORT1_PPS_PPS11_Pos 11 /*!< PORT1 PPS: PPS11 Position */
\r
14630 #define PORT1_PPS_PPS11_Msk (0x01UL << PORT1_PPS_PPS11_Pos) /*!< PORT1 PPS: PPS11 Mask */
\r
14631 #define PORT1_PPS_PPS12_Pos 12 /*!< PORT1 PPS: PPS12 Position */
\r
14632 #define PORT1_PPS_PPS12_Msk (0x01UL << PORT1_PPS_PPS12_Pos) /*!< PORT1 PPS: PPS12 Mask */
\r
14633 #define PORT1_PPS_PPS13_Pos 13 /*!< PORT1 PPS: PPS13 Position */
\r
14634 #define PORT1_PPS_PPS13_Msk (0x01UL << PORT1_PPS_PPS13_Pos) /*!< PORT1 PPS: PPS13 Mask */
\r
14635 #define PORT1_PPS_PPS14_Pos 14 /*!< PORT1 PPS: PPS14 Position */
\r
14636 #define PORT1_PPS_PPS14_Msk (0x01UL << PORT1_PPS_PPS14_Pos) /*!< PORT1 PPS: PPS14 Mask */
\r
14637 #define PORT1_PPS_PPS15_Pos 15 /*!< PORT1 PPS: PPS15 Position */
\r
14638 #define PORT1_PPS_PPS15_Msk (0x01UL << PORT1_PPS_PPS15_Pos) /*!< PORT1 PPS: PPS15 Mask */
\r
14640 /* --------------------------------- PORT1_HWSEL -------------------------------- */
\r
14641 #define PORT1_HWSEL_HW0_Pos 0 /*!< PORT1 HWSEL: HW0 Position */
\r
14642 #define PORT1_HWSEL_HW0_Msk (0x03UL << PORT1_HWSEL_HW0_Pos) /*!< PORT1 HWSEL: HW0 Mask */
\r
14643 #define PORT1_HWSEL_HW1_Pos 2 /*!< PORT1 HWSEL: HW1 Position */
\r
14644 #define PORT1_HWSEL_HW1_Msk (0x03UL << PORT1_HWSEL_HW1_Pos) /*!< PORT1 HWSEL: HW1 Mask */
\r
14645 #define PORT1_HWSEL_HW2_Pos 4 /*!< PORT1 HWSEL: HW2 Position */
\r
14646 #define PORT1_HWSEL_HW2_Msk (0x03UL << PORT1_HWSEL_HW2_Pos) /*!< PORT1 HWSEL: HW2 Mask */
\r
14647 #define PORT1_HWSEL_HW3_Pos 6 /*!< PORT1 HWSEL: HW3 Position */
\r
14648 #define PORT1_HWSEL_HW3_Msk (0x03UL << PORT1_HWSEL_HW3_Pos) /*!< PORT1 HWSEL: HW3 Mask */
\r
14649 #define PORT1_HWSEL_HW4_Pos 8 /*!< PORT1 HWSEL: HW4 Position */
\r
14650 #define PORT1_HWSEL_HW4_Msk (0x03UL << PORT1_HWSEL_HW4_Pos) /*!< PORT1 HWSEL: HW4 Mask */
\r
14651 #define PORT1_HWSEL_HW5_Pos 10 /*!< PORT1 HWSEL: HW5 Position */
\r
14652 #define PORT1_HWSEL_HW5_Msk (0x03UL << PORT1_HWSEL_HW5_Pos) /*!< PORT1 HWSEL: HW5 Mask */
\r
14653 #define PORT1_HWSEL_HW6_Pos 12 /*!< PORT1 HWSEL: HW6 Position */
\r
14654 #define PORT1_HWSEL_HW6_Msk (0x03UL << PORT1_HWSEL_HW6_Pos) /*!< PORT1 HWSEL: HW6 Mask */
\r
14655 #define PORT1_HWSEL_HW7_Pos 14 /*!< PORT1 HWSEL: HW7 Position */
\r
14656 #define PORT1_HWSEL_HW7_Msk (0x03UL << PORT1_HWSEL_HW7_Pos) /*!< PORT1 HWSEL: HW7 Mask */
\r
14657 #define PORT1_HWSEL_HW8_Pos 16 /*!< PORT1 HWSEL: HW8 Position */
\r
14658 #define PORT1_HWSEL_HW8_Msk (0x03UL << PORT1_HWSEL_HW8_Pos) /*!< PORT1 HWSEL: HW8 Mask */
\r
14659 #define PORT1_HWSEL_HW9_Pos 18 /*!< PORT1 HWSEL: HW9 Position */
\r
14660 #define PORT1_HWSEL_HW9_Msk (0x03UL << PORT1_HWSEL_HW9_Pos) /*!< PORT1 HWSEL: HW9 Mask */
\r
14661 #define PORT1_HWSEL_HW10_Pos 20 /*!< PORT1 HWSEL: HW10 Position */
\r
14662 #define PORT1_HWSEL_HW10_Msk (0x03UL << PORT1_HWSEL_HW10_Pos) /*!< PORT1 HWSEL: HW10 Mask */
\r
14663 #define PORT1_HWSEL_HW11_Pos 22 /*!< PORT1 HWSEL: HW11 Position */
\r
14664 #define PORT1_HWSEL_HW11_Msk (0x03UL << PORT1_HWSEL_HW11_Pos) /*!< PORT1 HWSEL: HW11 Mask */
\r
14665 #define PORT1_HWSEL_HW12_Pos 24 /*!< PORT1 HWSEL: HW12 Position */
\r
14666 #define PORT1_HWSEL_HW12_Msk (0x03UL << PORT1_HWSEL_HW12_Pos) /*!< PORT1 HWSEL: HW12 Mask */
\r
14667 #define PORT1_HWSEL_HW13_Pos 26 /*!< PORT1 HWSEL: HW13 Position */
\r
14668 #define PORT1_HWSEL_HW13_Msk (0x03UL << PORT1_HWSEL_HW13_Pos) /*!< PORT1 HWSEL: HW13 Mask */
\r
14669 #define PORT1_HWSEL_HW14_Pos 28 /*!< PORT1 HWSEL: HW14 Position */
\r
14670 #define PORT1_HWSEL_HW14_Msk (0x03UL << PORT1_HWSEL_HW14_Pos) /*!< PORT1 HWSEL: HW14 Mask */
\r
14671 #define PORT1_HWSEL_HW15_Pos 30 /*!< PORT1 HWSEL: HW15 Position */
\r
14672 #define PORT1_HWSEL_HW15_Msk (0x03UL << PORT1_HWSEL_HW15_Pos) /*!< PORT1 HWSEL: HW15 Mask */
\r
14675 /* ================================================================================ */
\r
14676 /* ================ struct 'PORT2' Position & Mask ================ */
\r
14677 /* ================================================================================ */
\r
14680 /* ---------------------------------- PORT2_OUT --------------------------------- */
\r
14681 #define PORT2_OUT_P0_Pos 0 /*!< PORT2 OUT: P0 Position */
\r
14682 #define PORT2_OUT_P0_Msk (0x01UL << PORT2_OUT_P0_Pos) /*!< PORT2 OUT: P0 Mask */
\r
14683 #define PORT2_OUT_P1_Pos 1 /*!< PORT2 OUT: P1 Position */
\r
14684 #define PORT2_OUT_P1_Msk (0x01UL << PORT2_OUT_P1_Pos) /*!< PORT2 OUT: P1 Mask */
\r
14685 #define PORT2_OUT_P2_Pos 2 /*!< PORT2 OUT: P2 Position */
\r
14686 #define PORT2_OUT_P2_Msk (0x01UL << PORT2_OUT_P2_Pos) /*!< PORT2 OUT: P2 Mask */
\r
14687 #define PORT2_OUT_P3_Pos 3 /*!< PORT2 OUT: P3 Position */
\r
14688 #define PORT2_OUT_P3_Msk (0x01UL << PORT2_OUT_P3_Pos) /*!< PORT2 OUT: P3 Mask */
\r
14689 #define PORT2_OUT_P4_Pos 4 /*!< PORT2 OUT: P4 Position */
\r
14690 #define PORT2_OUT_P4_Msk (0x01UL << PORT2_OUT_P4_Pos) /*!< PORT2 OUT: P4 Mask */
\r
14691 #define PORT2_OUT_P5_Pos 5 /*!< PORT2 OUT: P5 Position */
\r
14692 #define PORT2_OUT_P5_Msk (0x01UL << PORT2_OUT_P5_Pos) /*!< PORT2 OUT: P5 Mask */
\r
14693 #define PORT2_OUT_P6_Pos 6 /*!< PORT2 OUT: P6 Position */
\r
14694 #define PORT2_OUT_P6_Msk (0x01UL << PORT2_OUT_P6_Pos) /*!< PORT2 OUT: P6 Mask */
\r
14695 #define PORT2_OUT_P7_Pos 7 /*!< PORT2 OUT: P7 Position */
\r
14696 #define PORT2_OUT_P7_Msk (0x01UL << PORT2_OUT_P7_Pos) /*!< PORT2 OUT: P7 Mask */
\r
14697 #define PORT2_OUT_P8_Pos 8 /*!< PORT2 OUT: P8 Position */
\r
14698 #define PORT2_OUT_P8_Msk (0x01UL << PORT2_OUT_P8_Pos) /*!< PORT2 OUT: P8 Mask */
\r
14699 #define PORT2_OUT_P9_Pos 9 /*!< PORT2 OUT: P9 Position */
\r
14700 #define PORT2_OUT_P9_Msk (0x01UL << PORT2_OUT_P9_Pos) /*!< PORT2 OUT: P9 Mask */
\r
14701 #define PORT2_OUT_P10_Pos 10 /*!< PORT2 OUT: P10 Position */
\r
14702 #define PORT2_OUT_P10_Msk (0x01UL << PORT2_OUT_P10_Pos) /*!< PORT2 OUT: P10 Mask */
\r
14703 #define PORT2_OUT_P11_Pos 11 /*!< PORT2 OUT: P11 Position */
\r
14704 #define PORT2_OUT_P11_Msk (0x01UL << PORT2_OUT_P11_Pos) /*!< PORT2 OUT: P11 Mask */
\r
14705 #define PORT2_OUT_P12_Pos 12 /*!< PORT2 OUT: P12 Position */
\r
14706 #define PORT2_OUT_P12_Msk (0x01UL << PORT2_OUT_P12_Pos) /*!< PORT2 OUT: P12 Mask */
\r
14707 #define PORT2_OUT_P13_Pos 13 /*!< PORT2 OUT: P13 Position */
\r
14708 #define PORT2_OUT_P13_Msk (0x01UL << PORT2_OUT_P13_Pos) /*!< PORT2 OUT: P13 Mask */
\r
14709 #define PORT2_OUT_P14_Pos 14 /*!< PORT2 OUT: P14 Position */
\r
14710 #define PORT2_OUT_P14_Msk (0x01UL << PORT2_OUT_P14_Pos) /*!< PORT2 OUT: P14 Mask */
\r
14711 #define PORT2_OUT_P15_Pos 15 /*!< PORT2 OUT: P15 Position */
\r
14712 #define PORT2_OUT_P15_Msk (0x01UL << PORT2_OUT_P15_Pos) /*!< PORT2 OUT: P15 Mask */
\r
14714 /* ---------------------------------- PORT2_OMR --------------------------------- */
\r
14715 #define PORT2_OMR_PS0_Pos 0 /*!< PORT2 OMR: PS0 Position */
\r
14716 #define PORT2_OMR_PS0_Msk (0x01UL << PORT2_OMR_PS0_Pos) /*!< PORT2 OMR: PS0 Mask */
\r
14717 #define PORT2_OMR_PS1_Pos 1 /*!< PORT2 OMR: PS1 Position */
\r
14718 #define PORT2_OMR_PS1_Msk (0x01UL << PORT2_OMR_PS1_Pos) /*!< PORT2 OMR: PS1 Mask */
\r
14719 #define PORT2_OMR_PS2_Pos 2 /*!< PORT2 OMR: PS2 Position */
\r
14720 #define PORT2_OMR_PS2_Msk (0x01UL << PORT2_OMR_PS2_Pos) /*!< PORT2 OMR: PS2 Mask */
\r
14721 #define PORT2_OMR_PS3_Pos 3 /*!< PORT2 OMR: PS3 Position */
\r
14722 #define PORT2_OMR_PS3_Msk (0x01UL << PORT2_OMR_PS3_Pos) /*!< PORT2 OMR: PS3 Mask */
\r
14723 #define PORT2_OMR_PS4_Pos 4 /*!< PORT2 OMR: PS4 Position */
\r
14724 #define PORT2_OMR_PS4_Msk (0x01UL << PORT2_OMR_PS4_Pos) /*!< PORT2 OMR: PS4 Mask */
\r
14725 #define PORT2_OMR_PS5_Pos 5 /*!< PORT2 OMR: PS5 Position */
\r
14726 #define PORT2_OMR_PS5_Msk (0x01UL << PORT2_OMR_PS5_Pos) /*!< PORT2 OMR: PS5 Mask */
\r
14727 #define PORT2_OMR_PS6_Pos 6 /*!< PORT2 OMR: PS6 Position */
\r
14728 #define PORT2_OMR_PS6_Msk (0x01UL << PORT2_OMR_PS6_Pos) /*!< PORT2 OMR: PS6 Mask */
\r
14729 #define PORT2_OMR_PS7_Pos 7 /*!< PORT2 OMR: PS7 Position */
\r
14730 #define PORT2_OMR_PS7_Msk (0x01UL << PORT2_OMR_PS7_Pos) /*!< PORT2 OMR: PS7 Mask */
\r
14731 #define PORT2_OMR_PS8_Pos 8 /*!< PORT2 OMR: PS8 Position */
\r
14732 #define PORT2_OMR_PS8_Msk (0x01UL << PORT2_OMR_PS8_Pos) /*!< PORT2 OMR: PS8 Mask */
\r
14733 #define PORT2_OMR_PS9_Pos 9 /*!< PORT2 OMR: PS9 Position */
\r
14734 #define PORT2_OMR_PS9_Msk (0x01UL << PORT2_OMR_PS9_Pos) /*!< PORT2 OMR: PS9 Mask */
\r
14735 #define PORT2_OMR_PS10_Pos 10 /*!< PORT2 OMR: PS10 Position */
\r
14736 #define PORT2_OMR_PS10_Msk (0x01UL << PORT2_OMR_PS10_Pos) /*!< PORT2 OMR: PS10 Mask */
\r
14737 #define PORT2_OMR_PS11_Pos 11 /*!< PORT2 OMR: PS11 Position */
\r
14738 #define PORT2_OMR_PS11_Msk (0x01UL << PORT2_OMR_PS11_Pos) /*!< PORT2 OMR: PS11 Mask */
\r
14739 #define PORT2_OMR_PS12_Pos 12 /*!< PORT2 OMR: PS12 Position */
\r
14740 #define PORT2_OMR_PS12_Msk (0x01UL << PORT2_OMR_PS12_Pos) /*!< PORT2 OMR: PS12 Mask */
\r
14741 #define PORT2_OMR_PS13_Pos 13 /*!< PORT2 OMR: PS13 Position */
\r
14742 #define PORT2_OMR_PS13_Msk (0x01UL << PORT2_OMR_PS13_Pos) /*!< PORT2 OMR: PS13 Mask */
\r
14743 #define PORT2_OMR_PS14_Pos 14 /*!< PORT2 OMR: PS14 Position */
\r
14744 #define PORT2_OMR_PS14_Msk (0x01UL << PORT2_OMR_PS14_Pos) /*!< PORT2 OMR: PS14 Mask */
\r
14745 #define PORT2_OMR_PS15_Pos 15 /*!< PORT2 OMR: PS15 Position */
\r
14746 #define PORT2_OMR_PS15_Msk (0x01UL << PORT2_OMR_PS15_Pos) /*!< PORT2 OMR: PS15 Mask */
\r
14747 #define PORT2_OMR_PR0_Pos 16 /*!< PORT2 OMR: PR0 Position */
\r
14748 #define PORT2_OMR_PR0_Msk (0x01UL << PORT2_OMR_PR0_Pos) /*!< PORT2 OMR: PR0 Mask */
\r
14749 #define PORT2_OMR_PR1_Pos 17 /*!< PORT2 OMR: PR1 Position */
\r
14750 #define PORT2_OMR_PR1_Msk (0x01UL << PORT2_OMR_PR1_Pos) /*!< PORT2 OMR: PR1 Mask */
\r
14751 #define PORT2_OMR_PR2_Pos 18 /*!< PORT2 OMR: PR2 Position */
\r
14752 #define PORT2_OMR_PR2_Msk (0x01UL << PORT2_OMR_PR2_Pos) /*!< PORT2 OMR: PR2 Mask */
\r
14753 #define PORT2_OMR_PR3_Pos 19 /*!< PORT2 OMR: PR3 Position */
\r
14754 #define PORT2_OMR_PR3_Msk (0x01UL << PORT2_OMR_PR3_Pos) /*!< PORT2 OMR: PR3 Mask */
\r
14755 #define PORT2_OMR_PR4_Pos 20 /*!< PORT2 OMR: PR4 Position */
\r
14756 #define PORT2_OMR_PR4_Msk (0x01UL << PORT2_OMR_PR4_Pos) /*!< PORT2 OMR: PR4 Mask */
\r
14757 #define PORT2_OMR_PR5_Pos 21 /*!< PORT2 OMR: PR5 Position */
\r
14758 #define PORT2_OMR_PR5_Msk (0x01UL << PORT2_OMR_PR5_Pos) /*!< PORT2 OMR: PR5 Mask */
\r
14759 #define PORT2_OMR_PR6_Pos 22 /*!< PORT2 OMR: PR6 Position */
\r
14760 #define PORT2_OMR_PR6_Msk (0x01UL << PORT2_OMR_PR6_Pos) /*!< PORT2 OMR: PR6 Mask */
\r
14761 #define PORT2_OMR_PR7_Pos 23 /*!< PORT2 OMR: PR7 Position */
\r
14762 #define PORT2_OMR_PR7_Msk (0x01UL << PORT2_OMR_PR7_Pos) /*!< PORT2 OMR: PR7 Mask */
\r
14763 #define PORT2_OMR_PR8_Pos 24 /*!< PORT2 OMR: PR8 Position */
\r
14764 #define PORT2_OMR_PR8_Msk (0x01UL << PORT2_OMR_PR8_Pos) /*!< PORT2 OMR: PR8 Mask */
\r
14765 #define PORT2_OMR_PR9_Pos 25 /*!< PORT2 OMR: PR9 Position */
\r
14766 #define PORT2_OMR_PR9_Msk (0x01UL << PORT2_OMR_PR9_Pos) /*!< PORT2 OMR: PR9 Mask */
\r
14767 #define PORT2_OMR_PR10_Pos 26 /*!< PORT2 OMR: PR10 Position */
\r
14768 #define PORT2_OMR_PR10_Msk (0x01UL << PORT2_OMR_PR10_Pos) /*!< PORT2 OMR: PR10 Mask */
\r
14769 #define PORT2_OMR_PR11_Pos 27 /*!< PORT2 OMR: PR11 Position */
\r
14770 #define PORT2_OMR_PR11_Msk (0x01UL << PORT2_OMR_PR11_Pos) /*!< PORT2 OMR: PR11 Mask */
\r
14771 #define PORT2_OMR_PR12_Pos 28 /*!< PORT2 OMR: PR12 Position */
\r
14772 #define PORT2_OMR_PR12_Msk (0x01UL << PORT2_OMR_PR12_Pos) /*!< PORT2 OMR: PR12 Mask */
\r
14773 #define PORT2_OMR_PR13_Pos 29 /*!< PORT2 OMR: PR13 Position */
\r
14774 #define PORT2_OMR_PR13_Msk (0x01UL << PORT2_OMR_PR13_Pos) /*!< PORT2 OMR: PR13 Mask */
\r
14775 #define PORT2_OMR_PR14_Pos 30 /*!< PORT2 OMR: PR14 Position */
\r
14776 #define PORT2_OMR_PR14_Msk (0x01UL << PORT2_OMR_PR14_Pos) /*!< PORT2 OMR: PR14 Mask */
\r
14777 #define PORT2_OMR_PR15_Pos 31 /*!< PORT2 OMR: PR15 Position */
\r
14778 #define PORT2_OMR_PR15_Msk (0x01UL << PORT2_OMR_PR15_Pos) /*!< PORT2 OMR: PR15 Mask */
\r
14780 /* --------------------------------- PORT2_IOCR0 -------------------------------- */
\r
14781 #define PORT2_IOCR0_PC0_Pos 3 /*!< PORT2 IOCR0: PC0 Position */
\r
14782 #define PORT2_IOCR0_PC0_Msk (0x1fUL << PORT2_IOCR0_PC0_Pos) /*!< PORT2 IOCR0: PC0 Mask */
\r
14783 #define PORT2_IOCR0_PC1_Pos 11 /*!< PORT2 IOCR0: PC1 Position */
\r
14784 #define PORT2_IOCR0_PC1_Msk (0x1fUL << PORT2_IOCR0_PC1_Pos) /*!< PORT2 IOCR0: PC1 Mask */
\r
14785 #define PORT2_IOCR0_PC2_Pos 19 /*!< PORT2 IOCR0: PC2 Position */
\r
14786 #define PORT2_IOCR0_PC2_Msk (0x1fUL << PORT2_IOCR0_PC2_Pos) /*!< PORT2 IOCR0: PC2 Mask */
\r
14787 #define PORT2_IOCR0_PC3_Pos 27 /*!< PORT2 IOCR0: PC3 Position */
\r
14788 #define PORT2_IOCR0_PC3_Msk (0x1fUL << PORT2_IOCR0_PC3_Pos) /*!< PORT2 IOCR0: PC3 Mask */
\r
14790 /* --------------------------------- PORT2_IOCR4 -------------------------------- */
\r
14791 #define PORT2_IOCR4_PC4_Pos 3 /*!< PORT2 IOCR4: PC4 Position */
\r
14792 #define PORT2_IOCR4_PC4_Msk (0x1fUL << PORT2_IOCR4_PC4_Pos) /*!< PORT2 IOCR4: PC4 Mask */
\r
14793 #define PORT2_IOCR4_PC5_Pos 11 /*!< PORT2 IOCR4: PC5 Position */
\r
14794 #define PORT2_IOCR4_PC5_Msk (0x1fUL << PORT2_IOCR4_PC5_Pos) /*!< PORT2 IOCR4: PC5 Mask */
\r
14795 #define PORT2_IOCR4_PC6_Pos 19 /*!< PORT2 IOCR4: PC6 Position */
\r
14796 #define PORT2_IOCR4_PC6_Msk (0x1fUL << PORT2_IOCR4_PC6_Pos) /*!< PORT2 IOCR4: PC6 Mask */
\r
14797 #define PORT2_IOCR4_PC7_Pos 27 /*!< PORT2 IOCR4: PC7 Position */
\r
14798 #define PORT2_IOCR4_PC7_Msk (0x1fUL << PORT2_IOCR4_PC7_Pos) /*!< PORT2 IOCR4: PC7 Mask */
\r
14800 /* --------------------------------- PORT2_IOCR8 -------------------------------- */
\r
14801 #define PORT2_IOCR8_PC8_Pos 3 /*!< PORT2 IOCR8: PC8 Position */
\r
14802 #define PORT2_IOCR8_PC8_Msk (0x1fUL << PORT2_IOCR8_PC8_Pos) /*!< PORT2 IOCR8: PC8 Mask */
\r
14803 #define PORT2_IOCR8_PC9_Pos 11 /*!< PORT2 IOCR8: PC9 Position */
\r
14804 #define PORT2_IOCR8_PC9_Msk (0x1fUL << PORT2_IOCR8_PC9_Pos) /*!< PORT2 IOCR8: PC9 Mask */
\r
14805 #define PORT2_IOCR8_PC10_Pos 19 /*!< PORT2 IOCR8: PC10 Position */
\r
14806 #define PORT2_IOCR8_PC10_Msk (0x1fUL << PORT2_IOCR8_PC10_Pos) /*!< PORT2 IOCR8: PC10 Mask */
\r
14807 #define PORT2_IOCR8_PC11_Pos 27 /*!< PORT2 IOCR8: PC11 Position */
\r
14808 #define PORT2_IOCR8_PC11_Msk (0x1fUL << PORT2_IOCR8_PC11_Pos) /*!< PORT2 IOCR8: PC11 Mask */
\r
14810 /* -------------------------------- PORT2_IOCR12 -------------------------------- */
\r
14811 #define PORT2_IOCR12_PC12_Pos 3 /*!< PORT2 IOCR12: PC12 Position */
\r
14812 #define PORT2_IOCR12_PC12_Msk (0x1fUL << PORT2_IOCR12_PC12_Pos) /*!< PORT2 IOCR12: PC12 Mask */
\r
14813 #define PORT2_IOCR12_PC13_Pos 11 /*!< PORT2 IOCR12: PC13 Position */
\r
14814 #define PORT2_IOCR12_PC13_Msk (0x1fUL << PORT2_IOCR12_PC13_Pos) /*!< PORT2 IOCR12: PC13 Mask */
\r
14815 #define PORT2_IOCR12_PC14_Pos 19 /*!< PORT2 IOCR12: PC14 Position */
\r
14816 #define PORT2_IOCR12_PC14_Msk (0x1fUL << PORT2_IOCR12_PC14_Pos) /*!< PORT2 IOCR12: PC14 Mask */
\r
14817 #define PORT2_IOCR12_PC15_Pos 27 /*!< PORT2 IOCR12: PC15 Position */
\r
14818 #define PORT2_IOCR12_PC15_Msk (0x1fUL << PORT2_IOCR12_PC15_Pos) /*!< PORT2 IOCR12: PC15 Mask */
\r
14820 /* ---------------------------------- PORT2_IN ---------------------------------- */
\r
14821 #define PORT2_IN_P0_Pos 0 /*!< PORT2 IN: P0 Position */
\r
14822 #define PORT2_IN_P0_Msk (0x01UL << PORT2_IN_P0_Pos) /*!< PORT2 IN: P0 Mask */
\r
14823 #define PORT2_IN_P1_Pos 1 /*!< PORT2 IN: P1 Position */
\r
14824 #define PORT2_IN_P1_Msk (0x01UL << PORT2_IN_P1_Pos) /*!< PORT2 IN: P1 Mask */
\r
14825 #define PORT2_IN_P2_Pos 2 /*!< PORT2 IN: P2 Position */
\r
14826 #define PORT2_IN_P2_Msk (0x01UL << PORT2_IN_P2_Pos) /*!< PORT2 IN: P2 Mask */
\r
14827 #define PORT2_IN_P3_Pos 3 /*!< PORT2 IN: P3 Position */
\r
14828 #define PORT2_IN_P3_Msk (0x01UL << PORT2_IN_P3_Pos) /*!< PORT2 IN: P3 Mask */
\r
14829 #define PORT2_IN_P4_Pos 4 /*!< PORT2 IN: P4 Position */
\r
14830 #define PORT2_IN_P4_Msk (0x01UL << PORT2_IN_P4_Pos) /*!< PORT2 IN: P4 Mask */
\r
14831 #define PORT2_IN_P5_Pos 5 /*!< PORT2 IN: P5 Position */
\r
14832 #define PORT2_IN_P5_Msk (0x01UL << PORT2_IN_P5_Pos) /*!< PORT2 IN: P5 Mask */
\r
14833 #define PORT2_IN_P6_Pos 6 /*!< PORT2 IN: P6 Position */
\r
14834 #define PORT2_IN_P6_Msk (0x01UL << PORT2_IN_P6_Pos) /*!< PORT2 IN: P6 Mask */
\r
14835 #define PORT2_IN_P7_Pos 7 /*!< PORT2 IN: P7 Position */
\r
14836 #define PORT2_IN_P7_Msk (0x01UL << PORT2_IN_P7_Pos) /*!< PORT2 IN: P7 Mask */
\r
14837 #define PORT2_IN_P8_Pos 8 /*!< PORT2 IN: P8 Position */
\r
14838 #define PORT2_IN_P8_Msk (0x01UL << PORT2_IN_P8_Pos) /*!< PORT2 IN: P8 Mask */
\r
14839 #define PORT2_IN_P9_Pos 9 /*!< PORT2 IN: P9 Position */
\r
14840 #define PORT2_IN_P9_Msk (0x01UL << PORT2_IN_P9_Pos) /*!< PORT2 IN: P9 Mask */
\r
14841 #define PORT2_IN_P10_Pos 10 /*!< PORT2 IN: P10 Position */
\r
14842 #define PORT2_IN_P10_Msk (0x01UL << PORT2_IN_P10_Pos) /*!< PORT2 IN: P10 Mask */
\r
14843 #define PORT2_IN_P11_Pos 11 /*!< PORT2 IN: P11 Position */
\r
14844 #define PORT2_IN_P11_Msk (0x01UL << PORT2_IN_P11_Pos) /*!< PORT2 IN: P11 Mask */
\r
14845 #define PORT2_IN_P12_Pos 12 /*!< PORT2 IN: P12 Position */
\r
14846 #define PORT2_IN_P12_Msk (0x01UL << PORT2_IN_P12_Pos) /*!< PORT2 IN: P12 Mask */
\r
14847 #define PORT2_IN_P13_Pos 13 /*!< PORT2 IN: P13 Position */
\r
14848 #define PORT2_IN_P13_Msk (0x01UL << PORT2_IN_P13_Pos) /*!< PORT2 IN: P13 Mask */
\r
14849 #define PORT2_IN_P14_Pos 14 /*!< PORT2 IN: P14 Position */
\r
14850 #define PORT2_IN_P14_Msk (0x01UL << PORT2_IN_P14_Pos) /*!< PORT2 IN: P14 Mask */
\r
14851 #define PORT2_IN_P15_Pos 15 /*!< PORT2 IN: P15 Position */
\r
14852 #define PORT2_IN_P15_Msk (0x01UL << PORT2_IN_P15_Pos) /*!< PORT2 IN: P15 Mask */
\r
14854 /* --------------------------------- PORT2_PDR0 --------------------------------- */
\r
14855 #define PORT2_PDR0_PD0_Pos 0 /*!< PORT2 PDR0: PD0 Position */
\r
14856 #define PORT2_PDR0_PD0_Msk (0x07UL << PORT2_PDR0_PD0_Pos) /*!< PORT2 PDR0: PD0 Mask */
\r
14857 #define PORT2_PDR0_PD1_Pos 4 /*!< PORT2 PDR0: PD1 Position */
\r
14858 #define PORT2_PDR0_PD1_Msk (0x07UL << PORT2_PDR0_PD1_Pos) /*!< PORT2 PDR0: PD1 Mask */
\r
14859 #define PORT2_PDR0_PD2_Pos 8 /*!< PORT2 PDR0: PD2 Position */
\r
14860 #define PORT2_PDR0_PD2_Msk (0x07UL << PORT2_PDR0_PD2_Pos) /*!< PORT2 PDR0: PD2 Mask */
\r
14861 #define PORT2_PDR0_PD3_Pos 12 /*!< PORT2 PDR0: PD3 Position */
\r
14862 #define PORT2_PDR0_PD3_Msk (0x07UL << PORT2_PDR0_PD3_Pos) /*!< PORT2 PDR0: PD3 Mask */
\r
14863 #define PORT2_PDR0_PD4_Pos 16 /*!< PORT2 PDR0: PD4 Position */
\r
14864 #define PORT2_PDR0_PD4_Msk (0x07UL << PORT2_PDR0_PD4_Pos) /*!< PORT2 PDR0: PD4 Mask */
\r
14865 #define PORT2_PDR0_PD5_Pos 20 /*!< PORT2 PDR0: PD5 Position */
\r
14866 #define PORT2_PDR0_PD5_Msk (0x07UL << PORT2_PDR0_PD5_Pos) /*!< PORT2 PDR0: PD5 Mask */
\r
14867 #define PORT2_PDR0_PD6_Pos 24 /*!< PORT2 PDR0: PD6 Position */
\r
14868 #define PORT2_PDR0_PD6_Msk (0x07UL << PORT2_PDR0_PD6_Pos) /*!< PORT2 PDR0: PD6 Mask */
\r
14869 #define PORT2_PDR0_PD7_Pos 28 /*!< PORT2 PDR0: PD7 Position */
\r
14870 #define PORT2_PDR0_PD7_Msk (0x07UL << PORT2_PDR0_PD7_Pos) /*!< PORT2 PDR0: PD7 Mask */
\r
14872 /* --------------------------------- PORT2_PDR1 --------------------------------- */
\r
14873 #define PORT2_PDR1_PD8_Pos 0 /*!< PORT2 PDR1: PD8 Position */
\r
14874 #define PORT2_PDR1_PD8_Msk (0x07UL << PORT2_PDR1_PD8_Pos) /*!< PORT2 PDR1: PD8 Mask */
\r
14875 #define PORT2_PDR1_PD9_Pos 4 /*!< PORT2 PDR1: PD9 Position */
\r
14876 #define PORT2_PDR1_PD9_Msk (0x07UL << PORT2_PDR1_PD9_Pos) /*!< PORT2 PDR1: PD9 Mask */
\r
14877 #define PORT2_PDR1_PD10_Pos 8 /*!< PORT2 PDR1: PD10 Position */
\r
14878 #define PORT2_PDR1_PD10_Msk (0x07UL << PORT2_PDR1_PD10_Pos) /*!< PORT2 PDR1: PD10 Mask */
\r
14879 #define PORT2_PDR1_PD11_Pos 12 /*!< PORT2 PDR1: PD11 Position */
\r
14880 #define PORT2_PDR1_PD11_Msk (0x07UL << PORT2_PDR1_PD11_Pos) /*!< PORT2 PDR1: PD11 Mask */
\r
14881 #define PORT2_PDR1_PD12_Pos 16 /*!< PORT2 PDR1: PD12 Position */
\r
14882 #define PORT2_PDR1_PD12_Msk (0x07UL << PORT2_PDR1_PD12_Pos) /*!< PORT2 PDR1: PD12 Mask */
\r
14883 #define PORT2_PDR1_PD13_Pos 20 /*!< PORT2 PDR1: PD13 Position */
\r
14884 #define PORT2_PDR1_PD13_Msk (0x07UL << PORT2_PDR1_PD13_Pos) /*!< PORT2 PDR1: PD13 Mask */
\r
14885 #define PORT2_PDR1_PD14_Pos 24 /*!< PORT2 PDR1: PD14 Position */
\r
14886 #define PORT2_PDR1_PD14_Msk (0x07UL << PORT2_PDR1_PD14_Pos) /*!< PORT2 PDR1: PD14 Mask */
\r
14887 #define PORT2_PDR1_PD15_Pos 28 /*!< PORT2 PDR1: PD15 Position */
\r
14888 #define PORT2_PDR1_PD15_Msk (0x07UL << PORT2_PDR1_PD15_Pos) /*!< PORT2 PDR1: PD15 Mask */
\r
14890 /* --------------------------------- PORT2_PDISC -------------------------------- */
\r
14891 #define PORT2_PDISC_PDIS0_Pos 0 /*!< PORT2 PDISC: PDIS0 Position */
\r
14892 #define PORT2_PDISC_PDIS0_Msk (0x01UL << PORT2_PDISC_PDIS0_Pos) /*!< PORT2 PDISC: PDIS0 Mask */
\r
14893 #define PORT2_PDISC_PDIS1_Pos 1 /*!< PORT2 PDISC: PDIS1 Position */
\r
14894 #define PORT2_PDISC_PDIS1_Msk (0x01UL << PORT2_PDISC_PDIS1_Pos) /*!< PORT2 PDISC: PDIS1 Mask */
\r
14895 #define PORT2_PDISC_PDIS2_Pos 2 /*!< PORT2 PDISC: PDIS2 Position */
\r
14896 #define PORT2_PDISC_PDIS2_Msk (0x01UL << PORT2_PDISC_PDIS2_Pos) /*!< PORT2 PDISC: PDIS2 Mask */
\r
14897 #define PORT2_PDISC_PDIS3_Pos 3 /*!< PORT2 PDISC: PDIS3 Position */
\r
14898 #define PORT2_PDISC_PDIS3_Msk (0x01UL << PORT2_PDISC_PDIS3_Pos) /*!< PORT2 PDISC: PDIS3 Mask */
\r
14899 #define PORT2_PDISC_PDIS4_Pos 4 /*!< PORT2 PDISC: PDIS4 Position */
\r
14900 #define PORT2_PDISC_PDIS4_Msk (0x01UL << PORT2_PDISC_PDIS4_Pos) /*!< PORT2 PDISC: PDIS4 Mask */
\r
14901 #define PORT2_PDISC_PDIS5_Pos 5 /*!< PORT2 PDISC: PDIS5 Position */
\r
14902 #define PORT2_PDISC_PDIS5_Msk (0x01UL << PORT2_PDISC_PDIS5_Pos) /*!< PORT2 PDISC: PDIS5 Mask */
\r
14903 #define PORT2_PDISC_PDIS6_Pos 6 /*!< PORT2 PDISC: PDIS6 Position */
\r
14904 #define PORT2_PDISC_PDIS6_Msk (0x01UL << PORT2_PDISC_PDIS6_Pos) /*!< PORT2 PDISC: PDIS6 Mask */
\r
14905 #define PORT2_PDISC_PDIS7_Pos 7 /*!< PORT2 PDISC: PDIS7 Position */
\r
14906 #define PORT2_PDISC_PDIS7_Msk (0x01UL << PORT2_PDISC_PDIS7_Pos) /*!< PORT2 PDISC: PDIS7 Mask */
\r
14907 #define PORT2_PDISC_PDIS8_Pos 8 /*!< PORT2 PDISC: PDIS8 Position */
\r
14908 #define PORT2_PDISC_PDIS8_Msk (0x01UL << PORT2_PDISC_PDIS8_Pos) /*!< PORT2 PDISC: PDIS8 Mask */
\r
14909 #define PORT2_PDISC_PDIS9_Pos 9 /*!< PORT2 PDISC: PDIS9 Position */
\r
14910 #define PORT2_PDISC_PDIS9_Msk (0x01UL << PORT2_PDISC_PDIS9_Pos) /*!< PORT2 PDISC: PDIS9 Mask */
\r
14911 #define PORT2_PDISC_PDIS10_Pos 10 /*!< PORT2 PDISC: PDIS10 Position */
\r
14912 #define PORT2_PDISC_PDIS10_Msk (0x01UL << PORT2_PDISC_PDIS10_Pos) /*!< PORT2 PDISC: PDIS10 Mask */
\r
14913 #define PORT2_PDISC_PDIS11_Pos 11 /*!< PORT2 PDISC: PDIS11 Position */
\r
14914 #define PORT2_PDISC_PDIS11_Msk (0x01UL << PORT2_PDISC_PDIS11_Pos) /*!< PORT2 PDISC: PDIS11 Mask */
\r
14915 #define PORT2_PDISC_PDIS12_Pos 12 /*!< PORT2 PDISC: PDIS12 Position */
\r
14916 #define PORT2_PDISC_PDIS12_Msk (0x01UL << PORT2_PDISC_PDIS12_Pos) /*!< PORT2 PDISC: PDIS12 Mask */
\r
14917 #define PORT2_PDISC_PDIS13_Pos 13 /*!< PORT2 PDISC: PDIS13 Position */
\r
14918 #define PORT2_PDISC_PDIS13_Msk (0x01UL << PORT2_PDISC_PDIS13_Pos) /*!< PORT2 PDISC: PDIS13 Mask */
\r
14919 #define PORT2_PDISC_PDIS14_Pos 14 /*!< PORT2 PDISC: PDIS14 Position */
\r
14920 #define PORT2_PDISC_PDIS14_Msk (0x01UL << PORT2_PDISC_PDIS14_Pos) /*!< PORT2 PDISC: PDIS14 Mask */
\r
14921 #define PORT2_PDISC_PDIS15_Pos 15 /*!< PORT2 PDISC: PDIS15 Position */
\r
14922 #define PORT2_PDISC_PDIS15_Msk (0x01UL << PORT2_PDISC_PDIS15_Pos) /*!< PORT2 PDISC: PDIS15 Mask */
\r
14924 /* ---------------------------------- PORT2_PPS --------------------------------- */
\r
14925 #define PORT2_PPS_PPS0_Pos 0 /*!< PORT2 PPS: PPS0 Position */
\r
14926 #define PORT2_PPS_PPS0_Msk (0x01UL << PORT2_PPS_PPS0_Pos) /*!< PORT2 PPS: PPS0 Mask */
\r
14927 #define PORT2_PPS_PPS1_Pos 1 /*!< PORT2 PPS: PPS1 Position */
\r
14928 #define PORT2_PPS_PPS1_Msk (0x01UL << PORT2_PPS_PPS1_Pos) /*!< PORT2 PPS: PPS1 Mask */
\r
14929 #define PORT2_PPS_PPS2_Pos 2 /*!< PORT2 PPS: PPS2 Position */
\r
14930 #define PORT2_PPS_PPS2_Msk (0x01UL << PORT2_PPS_PPS2_Pos) /*!< PORT2 PPS: PPS2 Mask */
\r
14931 #define PORT2_PPS_PPS3_Pos 3 /*!< PORT2 PPS: PPS3 Position */
\r
14932 #define PORT2_PPS_PPS3_Msk (0x01UL << PORT2_PPS_PPS3_Pos) /*!< PORT2 PPS: PPS3 Mask */
\r
14933 #define PORT2_PPS_PPS4_Pos 4 /*!< PORT2 PPS: PPS4 Position */
\r
14934 #define PORT2_PPS_PPS4_Msk (0x01UL << PORT2_PPS_PPS4_Pos) /*!< PORT2 PPS: PPS4 Mask */
\r
14935 #define PORT2_PPS_PPS5_Pos 5 /*!< PORT2 PPS: PPS5 Position */
\r
14936 #define PORT2_PPS_PPS5_Msk (0x01UL << PORT2_PPS_PPS5_Pos) /*!< PORT2 PPS: PPS5 Mask */
\r
14937 #define PORT2_PPS_PPS6_Pos 6 /*!< PORT2 PPS: PPS6 Position */
\r
14938 #define PORT2_PPS_PPS6_Msk (0x01UL << PORT2_PPS_PPS6_Pos) /*!< PORT2 PPS: PPS6 Mask */
\r
14939 #define PORT2_PPS_PPS7_Pos 7 /*!< PORT2 PPS: PPS7 Position */
\r
14940 #define PORT2_PPS_PPS7_Msk (0x01UL << PORT2_PPS_PPS7_Pos) /*!< PORT2 PPS: PPS7 Mask */
\r
14941 #define PORT2_PPS_PPS8_Pos 8 /*!< PORT2 PPS: PPS8 Position */
\r
14942 #define PORT2_PPS_PPS8_Msk (0x01UL << PORT2_PPS_PPS8_Pos) /*!< PORT2 PPS: PPS8 Mask */
\r
14943 #define PORT2_PPS_PPS9_Pos 9 /*!< PORT2 PPS: PPS9 Position */
\r
14944 #define PORT2_PPS_PPS9_Msk (0x01UL << PORT2_PPS_PPS9_Pos) /*!< PORT2 PPS: PPS9 Mask */
\r
14945 #define PORT2_PPS_PPS10_Pos 10 /*!< PORT2 PPS: PPS10 Position */
\r
14946 #define PORT2_PPS_PPS10_Msk (0x01UL << PORT2_PPS_PPS10_Pos) /*!< PORT2 PPS: PPS10 Mask */
\r
14947 #define PORT2_PPS_PPS11_Pos 11 /*!< PORT2 PPS: PPS11 Position */
\r
14948 #define PORT2_PPS_PPS11_Msk (0x01UL << PORT2_PPS_PPS11_Pos) /*!< PORT2 PPS: PPS11 Mask */
\r
14949 #define PORT2_PPS_PPS12_Pos 12 /*!< PORT2 PPS: PPS12 Position */
\r
14950 #define PORT2_PPS_PPS12_Msk (0x01UL << PORT2_PPS_PPS12_Pos) /*!< PORT2 PPS: PPS12 Mask */
\r
14951 #define PORT2_PPS_PPS13_Pos 13 /*!< PORT2 PPS: PPS13 Position */
\r
14952 #define PORT2_PPS_PPS13_Msk (0x01UL << PORT2_PPS_PPS13_Pos) /*!< PORT2 PPS: PPS13 Mask */
\r
14953 #define PORT2_PPS_PPS14_Pos 14 /*!< PORT2 PPS: PPS14 Position */
\r
14954 #define PORT2_PPS_PPS14_Msk (0x01UL << PORT2_PPS_PPS14_Pos) /*!< PORT2 PPS: PPS14 Mask */
\r
14955 #define PORT2_PPS_PPS15_Pos 15 /*!< PORT2 PPS: PPS15 Position */
\r
14956 #define PORT2_PPS_PPS15_Msk (0x01UL << PORT2_PPS_PPS15_Pos) /*!< PORT2 PPS: PPS15 Mask */
\r
14958 /* --------------------------------- PORT2_HWSEL -------------------------------- */
\r
14959 #define PORT2_HWSEL_HW0_Pos 0 /*!< PORT2 HWSEL: HW0 Position */
\r
14960 #define PORT2_HWSEL_HW0_Msk (0x03UL << PORT2_HWSEL_HW0_Pos) /*!< PORT2 HWSEL: HW0 Mask */
\r
14961 #define PORT2_HWSEL_HW1_Pos 2 /*!< PORT2 HWSEL: HW1 Position */
\r
14962 #define PORT2_HWSEL_HW1_Msk (0x03UL << PORT2_HWSEL_HW1_Pos) /*!< PORT2 HWSEL: HW1 Mask */
\r
14963 #define PORT2_HWSEL_HW2_Pos 4 /*!< PORT2 HWSEL: HW2 Position */
\r
14964 #define PORT2_HWSEL_HW2_Msk (0x03UL << PORT2_HWSEL_HW2_Pos) /*!< PORT2 HWSEL: HW2 Mask */
\r
14965 #define PORT2_HWSEL_HW3_Pos 6 /*!< PORT2 HWSEL: HW3 Position */
\r
14966 #define PORT2_HWSEL_HW3_Msk (0x03UL << PORT2_HWSEL_HW3_Pos) /*!< PORT2 HWSEL: HW3 Mask */
\r
14967 #define PORT2_HWSEL_HW4_Pos 8 /*!< PORT2 HWSEL: HW4 Position */
\r
14968 #define PORT2_HWSEL_HW4_Msk (0x03UL << PORT2_HWSEL_HW4_Pos) /*!< PORT2 HWSEL: HW4 Mask */
\r
14969 #define PORT2_HWSEL_HW5_Pos 10 /*!< PORT2 HWSEL: HW5 Position */
\r
14970 #define PORT2_HWSEL_HW5_Msk (0x03UL << PORT2_HWSEL_HW5_Pos) /*!< PORT2 HWSEL: HW5 Mask */
\r
14971 #define PORT2_HWSEL_HW6_Pos 12 /*!< PORT2 HWSEL: HW6 Position */
\r
14972 #define PORT2_HWSEL_HW6_Msk (0x03UL << PORT2_HWSEL_HW6_Pos) /*!< PORT2 HWSEL: HW6 Mask */
\r
14973 #define PORT2_HWSEL_HW7_Pos 14 /*!< PORT2 HWSEL: HW7 Position */
\r
14974 #define PORT2_HWSEL_HW7_Msk (0x03UL << PORT2_HWSEL_HW7_Pos) /*!< PORT2 HWSEL: HW7 Mask */
\r
14975 #define PORT2_HWSEL_HW8_Pos 16 /*!< PORT2 HWSEL: HW8 Position */
\r
14976 #define PORT2_HWSEL_HW8_Msk (0x03UL << PORT2_HWSEL_HW8_Pos) /*!< PORT2 HWSEL: HW8 Mask */
\r
14977 #define PORT2_HWSEL_HW9_Pos 18 /*!< PORT2 HWSEL: HW9 Position */
\r
14978 #define PORT2_HWSEL_HW9_Msk (0x03UL << PORT2_HWSEL_HW9_Pos) /*!< PORT2 HWSEL: HW9 Mask */
\r
14979 #define PORT2_HWSEL_HW10_Pos 20 /*!< PORT2 HWSEL: HW10 Position */
\r
14980 #define PORT2_HWSEL_HW10_Msk (0x03UL << PORT2_HWSEL_HW10_Pos) /*!< PORT2 HWSEL: HW10 Mask */
\r
14981 #define PORT2_HWSEL_HW11_Pos 22 /*!< PORT2 HWSEL: HW11 Position */
\r
14982 #define PORT2_HWSEL_HW11_Msk (0x03UL << PORT2_HWSEL_HW11_Pos) /*!< PORT2 HWSEL: HW11 Mask */
\r
14983 #define PORT2_HWSEL_HW12_Pos 24 /*!< PORT2 HWSEL: HW12 Position */
\r
14984 #define PORT2_HWSEL_HW12_Msk (0x03UL << PORT2_HWSEL_HW12_Pos) /*!< PORT2 HWSEL: HW12 Mask */
\r
14985 #define PORT2_HWSEL_HW13_Pos 26 /*!< PORT2 HWSEL: HW13 Position */
\r
14986 #define PORT2_HWSEL_HW13_Msk (0x03UL << PORT2_HWSEL_HW13_Pos) /*!< PORT2 HWSEL: HW13 Mask */
\r
14987 #define PORT2_HWSEL_HW14_Pos 28 /*!< PORT2 HWSEL: HW14 Position */
\r
14988 #define PORT2_HWSEL_HW14_Msk (0x03UL << PORT2_HWSEL_HW14_Pos) /*!< PORT2 HWSEL: HW14 Mask */
\r
14989 #define PORT2_HWSEL_HW15_Pos 30 /*!< PORT2 HWSEL: HW15 Position */
\r
14990 #define PORT2_HWSEL_HW15_Msk (0x03UL << PORT2_HWSEL_HW15_Pos) /*!< PORT2 HWSEL: HW15 Mask */
\r
14993 /* ================================================================================ */
\r
14994 /* ================ struct 'PORT3' Position & Mask ================ */
\r
14995 /* ================================================================================ */
\r
14998 /* ---------------------------------- PORT3_OUT --------------------------------- */
\r
14999 #define PORT3_OUT_P0_Pos 0 /*!< PORT3 OUT: P0 Position */
\r
15000 #define PORT3_OUT_P0_Msk (0x01UL << PORT3_OUT_P0_Pos) /*!< PORT3 OUT: P0 Mask */
\r
15001 #define PORT3_OUT_P1_Pos 1 /*!< PORT3 OUT: P1 Position */
\r
15002 #define PORT3_OUT_P1_Msk (0x01UL << PORT3_OUT_P1_Pos) /*!< PORT3 OUT: P1 Mask */
\r
15003 #define PORT3_OUT_P2_Pos 2 /*!< PORT3 OUT: P2 Position */
\r
15004 #define PORT3_OUT_P2_Msk (0x01UL << PORT3_OUT_P2_Pos) /*!< PORT3 OUT: P2 Mask */
\r
15005 #define PORT3_OUT_P3_Pos 3 /*!< PORT3 OUT: P3 Position */
\r
15006 #define PORT3_OUT_P3_Msk (0x01UL << PORT3_OUT_P3_Pos) /*!< PORT3 OUT: P3 Mask */
\r
15007 #define PORT3_OUT_P4_Pos 4 /*!< PORT3 OUT: P4 Position */
\r
15008 #define PORT3_OUT_P4_Msk (0x01UL << PORT3_OUT_P4_Pos) /*!< PORT3 OUT: P4 Mask */
\r
15009 #define PORT3_OUT_P5_Pos 5 /*!< PORT3 OUT: P5 Position */
\r
15010 #define PORT3_OUT_P5_Msk (0x01UL << PORT3_OUT_P5_Pos) /*!< PORT3 OUT: P5 Mask */
\r
15011 #define PORT3_OUT_P6_Pos 6 /*!< PORT3 OUT: P6 Position */
\r
15012 #define PORT3_OUT_P6_Msk (0x01UL << PORT3_OUT_P6_Pos) /*!< PORT3 OUT: P6 Mask */
\r
15013 #define PORT3_OUT_P7_Pos 7 /*!< PORT3 OUT: P7 Position */
\r
15014 #define PORT3_OUT_P7_Msk (0x01UL << PORT3_OUT_P7_Pos) /*!< PORT3 OUT: P7 Mask */
\r
15015 #define PORT3_OUT_P8_Pos 8 /*!< PORT3 OUT: P8 Position */
\r
15016 #define PORT3_OUT_P8_Msk (0x01UL << PORT3_OUT_P8_Pos) /*!< PORT3 OUT: P8 Mask */
\r
15017 #define PORT3_OUT_P9_Pos 9 /*!< PORT3 OUT: P9 Position */
\r
15018 #define PORT3_OUT_P9_Msk (0x01UL << PORT3_OUT_P9_Pos) /*!< PORT3 OUT: P9 Mask */
\r
15019 #define PORT3_OUT_P10_Pos 10 /*!< PORT3 OUT: P10 Position */
\r
15020 #define PORT3_OUT_P10_Msk (0x01UL << PORT3_OUT_P10_Pos) /*!< PORT3 OUT: P10 Mask */
\r
15021 #define PORT3_OUT_P11_Pos 11 /*!< PORT3 OUT: P11 Position */
\r
15022 #define PORT3_OUT_P11_Msk (0x01UL << PORT3_OUT_P11_Pos) /*!< PORT3 OUT: P11 Mask */
\r
15023 #define PORT3_OUT_P12_Pos 12 /*!< PORT3 OUT: P12 Position */
\r
15024 #define PORT3_OUT_P12_Msk (0x01UL << PORT3_OUT_P12_Pos) /*!< PORT3 OUT: P12 Mask */
\r
15025 #define PORT3_OUT_P13_Pos 13 /*!< PORT3 OUT: P13 Position */
\r
15026 #define PORT3_OUT_P13_Msk (0x01UL << PORT3_OUT_P13_Pos) /*!< PORT3 OUT: P13 Mask */
\r
15027 #define PORT3_OUT_P14_Pos 14 /*!< PORT3 OUT: P14 Position */
\r
15028 #define PORT3_OUT_P14_Msk (0x01UL << PORT3_OUT_P14_Pos) /*!< PORT3 OUT: P14 Mask */
\r
15029 #define PORT3_OUT_P15_Pos 15 /*!< PORT3 OUT: P15 Position */
\r
15030 #define PORT3_OUT_P15_Msk (0x01UL << PORT3_OUT_P15_Pos) /*!< PORT3 OUT: P15 Mask */
\r
15032 /* ---------------------------------- PORT3_OMR --------------------------------- */
\r
15033 #define PORT3_OMR_PS0_Pos 0 /*!< PORT3 OMR: PS0 Position */
\r
15034 #define PORT3_OMR_PS0_Msk (0x01UL << PORT3_OMR_PS0_Pos) /*!< PORT3 OMR: PS0 Mask */
\r
15035 #define PORT3_OMR_PS1_Pos 1 /*!< PORT3 OMR: PS1 Position */
\r
15036 #define PORT3_OMR_PS1_Msk (0x01UL << PORT3_OMR_PS1_Pos) /*!< PORT3 OMR: PS1 Mask */
\r
15037 #define PORT3_OMR_PS2_Pos 2 /*!< PORT3 OMR: PS2 Position */
\r
15038 #define PORT3_OMR_PS2_Msk (0x01UL << PORT3_OMR_PS2_Pos) /*!< PORT3 OMR: PS2 Mask */
\r
15039 #define PORT3_OMR_PS3_Pos 3 /*!< PORT3 OMR: PS3 Position */
\r
15040 #define PORT3_OMR_PS3_Msk (0x01UL << PORT3_OMR_PS3_Pos) /*!< PORT3 OMR: PS3 Mask */
\r
15041 #define PORT3_OMR_PS4_Pos 4 /*!< PORT3 OMR: PS4 Position */
\r
15042 #define PORT3_OMR_PS4_Msk (0x01UL << PORT3_OMR_PS4_Pos) /*!< PORT3 OMR: PS4 Mask */
\r
15043 #define PORT3_OMR_PS5_Pos 5 /*!< PORT3 OMR: PS5 Position */
\r
15044 #define PORT3_OMR_PS5_Msk (0x01UL << PORT3_OMR_PS5_Pos) /*!< PORT3 OMR: PS5 Mask */
\r
15045 #define PORT3_OMR_PS6_Pos 6 /*!< PORT3 OMR: PS6 Position */
\r
15046 #define PORT3_OMR_PS6_Msk (0x01UL << PORT3_OMR_PS6_Pos) /*!< PORT3 OMR: PS6 Mask */
\r
15047 #define PORT3_OMR_PS7_Pos 7 /*!< PORT3 OMR: PS7 Position */
\r
15048 #define PORT3_OMR_PS7_Msk (0x01UL << PORT3_OMR_PS7_Pos) /*!< PORT3 OMR: PS7 Mask */
\r
15049 #define PORT3_OMR_PS8_Pos 8 /*!< PORT3 OMR: PS8 Position */
\r
15050 #define PORT3_OMR_PS8_Msk (0x01UL << PORT3_OMR_PS8_Pos) /*!< PORT3 OMR: PS8 Mask */
\r
15051 #define PORT3_OMR_PS9_Pos 9 /*!< PORT3 OMR: PS9 Position */
\r
15052 #define PORT3_OMR_PS9_Msk (0x01UL << PORT3_OMR_PS9_Pos) /*!< PORT3 OMR: PS9 Mask */
\r
15053 #define PORT3_OMR_PS10_Pos 10 /*!< PORT3 OMR: PS10 Position */
\r
15054 #define PORT3_OMR_PS10_Msk (0x01UL << PORT3_OMR_PS10_Pos) /*!< PORT3 OMR: PS10 Mask */
\r
15055 #define PORT3_OMR_PS11_Pos 11 /*!< PORT3 OMR: PS11 Position */
\r
15056 #define PORT3_OMR_PS11_Msk (0x01UL << PORT3_OMR_PS11_Pos) /*!< PORT3 OMR: PS11 Mask */
\r
15057 #define PORT3_OMR_PS12_Pos 12 /*!< PORT3 OMR: PS12 Position */
\r
15058 #define PORT3_OMR_PS12_Msk (0x01UL << PORT3_OMR_PS12_Pos) /*!< PORT3 OMR: PS12 Mask */
\r
15059 #define PORT3_OMR_PS13_Pos 13 /*!< PORT3 OMR: PS13 Position */
\r
15060 #define PORT3_OMR_PS13_Msk (0x01UL << PORT3_OMR_PS13_Pos) /*!< PORT3 OMR: PS13 Mask */
\r
15061 #define PORT3_OMR_PS14_Pos 14 /*!< PORT3 OMR: PS14 Position */
\r
15062 #define PORT3_OMR_PS14_Msk (0x01UL << PORT3_OMR_PS14_Pos) /*!< PORT3 OMR: PS14 Mask */
\r
15063 #define PORT3_OMR_PS15_Pos 15 /*!< PORT3 OMR: PS15 Position */
\r
15064 #define PORT3_OMR_PS15_Msk (0x01UL << PORT3_OMR_PS15_Pos) /*!< PORT3 OMR: PS15 Mask */
\r
15065 #define PORT3_OMR_PR0_Pos 16 /*!< PORT3 OMR: PR0 Position */
\r
15066 #define PORT3_OMR_PR0_Msk (0x01UL << PORT3_OMR_PR0_Pos) /*!< PORT3 OMR: PR0 Mask */
\r
15067 #define PORT3_OMR_PR1_Pos 17 /*!< PORT3 OMR: PR1 Position */
\r
15068 #define PORT3_OMR_PR1_Msk (0x01UL << PORT3_OMR_PR1_Pos) /*!< PORT3 OMR: PR1 Mask */
\r
15069 #define PORT3_OMR_PR2_Pos 18 /*!< PORT3 OMR: PR2 Position */
\r
15070 #define PORT3_OMR_PR2_Msk (0x01UL << PORT3_OMR_PR2_Pos) /*!< PORT3 OMR: PR2 Mask */
\r
15071 #define PORT3_OMR_PR3_Pos 19 /*!< PORT3 OMR: PR3 Position */
\r
15072 #define PORT3_OMR_PR3_Msk (0x01UL << PORT3_OMR_PR3_Pos) /*!< PORT3 OMR: PR3 Mask */
\r
15073 #define PORT3_OMR_PR4_Pos 20 /*!< PORT3 OMR: PR4 Position */
\r
15074 #define PORT3_OMR_PR4_Msk (0x01UL << PORT3_OMR_PR4_Pos) /*!< PORT3 OMR: PR4 Mask */
\r
15075 #define PORT3_OMR_PR5_Pos 21 /*!< PORT3 OMR: PR5 Position */
\r
15076 #define PORT3_OMR_PR5_Msk (0x01UL << PORT3_OMR_PR5_Pos) /*!< PORT3 OMR: PR5 Mask */
\r
15077 #define PORT3_OMR_PR6_Pos 22 /*!< PORT3 OMR: PR6 Position */
\r
15078 #define PORT3_OMR_PR6_Msk (0x01UL << PORT3_OMR_PR6_Pos) /*!< PORT3 OMR: PR6 Mask */
\r
15079 #define PORT3_OMR_PR7_Pos 23 /*!< PORT3 OMR: PR7 Position */
\r
15080 #define PORT3_OMR_PR7_Msk (0x01UL << PORT3_OMR_PR7_Pos) /*!< PORT3 OMR: PR7 Mask */
\r
15081 #define PORT3_OMR_PR8_Pos 24 /*!< PORT3 OMR: PR8 Position */
\r
15082 #define PORT3_OMR_PR8_Msk (0x01UL << PORT3_OMR_PR8_Pos) /*!< PORT3 OMR: PR8 Mask */
\r
15083 #define PORT3_OMR_PR9_Pos 25 /*!< PORT3 OMR: PR9 Position */
\r
15084 #define PORT3_OMR_PR9_Msk (0x01UL << PORT3_OMR_PR9_Pos) /*!< PORT3 OMR: PR9 Mask */
\r
15085 #define PORT3_OMR_PR10_Pos 26 /*!< PORT3 OMR: PR10 Position */
\r
15086 #define PORT3_OMR_PR10_Msk (0x01UL << PORT3_OMR_PR10_Pos) /*!< PORT3 OMR: PR10 Mask */
\r
15087 #define PORT3_OMR_PR11_Pos 27 /*!< PORT3 OMR: PR11 Position */
\r
15088 #define PORT3_OMR_PR11_Msk (0x01UL << PORT3_OMR_PR11_Pos) /*!< PORT3 OMR: PR11 Mask */
\r
15089 #define PORT3_OMR_PR12_Pos 28 /*!< PORT3 OMR: PR12 Position */
\r
15090 #define PORT3_OMR_PR12_Msk (0x01UL << PORT3_OMR_PR12_Pos) /*!< PORT3 OMR: PR12 Mask */
\r
15091 #define PORT3_OMR_PR13_Pos 29 /*!< PORT3 OMR: PR13 Position */
\r
15092 #define PORT3_OMR_PR13_Msk (0x01UL << PORT3_OMR_PR13_Pos) /*!< PORT3 OMR: PR13 Mask */
\r
15093 #define PORT3_OMR_PR14_Pos 30 /*!< PORT3 OMR: PR14 Position */
\r
15094 #define PORT3_OMR_PR14_Msk (0x01UL << PORT3_OMR_PR14_Pos) /*!< PORT3 OMR: PR14 Mask */
\r
15095 #define PORT3_OMR_PR15_Pos 31 /*!< PORT3 OMR: PR15 Position */
\r
15096 #define PORT3_OMR_PR15_Msk (0x01UL << PORT3_OMR_PR15_Pos) /*!< PORT3 OMR: PR15 Mask */
\r
15098 /* --------------------------------- PORT3_IOCR0 -------------------------------- */
\r
15099 #define PORT3_IOCR0_PC0_Pos 3 /*!< PORT3 IOCR0: PC0 Position */
\r
15100 #define PORT3_IOCR0_PC0_Msk (0x1fUL << PORT3_IOCR0_PC0_Pos) /*!< PORT3 IOCR0: PC0 Mask */
\r
15101 #define PORT3_IOCR0_PC1_Pos 11 /*!< PORT3 IOCR0: PC1 Position */
\r
15102 #define PORT3_IOCR0_PC1_Msk (0x1fUL << PORT3_IOCR0_PC1_Pos) /*!< PORT3 IOCR0: PC1 Mask */
\r
15103 #define PORT3_IOCR0_PC2_Pos 19 /*!< PORT3 IOCR0: PC2 Position */
\r
15104 #define PORT3_IOCR0_PC2_Msk (0x1fUL << PORT3_IOCR0_PC2_Pos) /*!< PORT3 IOCR0: PC2 Mask */
\r
15105 #define PORT3_IOCR0_PC3_Pos 27 /*!< PORT3 IOCR0: PC3 Position */
\r
15106 #define PORT3_IOCR0_PC3_Msk (0x1fUL << PORT3_IOCR0_PC3_Pos) /*!< PORT3 IOCR0: PC3 Mask */
\r
15108 /* --------------------------------- PORT3_IOCR4 -------------------------------- */
\r
15109 #define PORT3_IOCR4_PC4_Pos 3 /*!< PORT3 IOCR4: PC4 Position */
\r
15110 #define PORT3_IOCR4_PC4_Msk (0x1fUL << PORT3_IOCR4_PC4_Pos) /*!< PORT3 IOCR4: PC4 Mask */
\r
15111 #define PORT3_IOCR4_PC5_Pos 11 /*!< PORT3 IOCR4: PC5 Position */
\r
15112 #define PORT3_IOCR4_PC5_Msk (0x1fUL << PORT3_IOCR4_PC5_Pos) /*!< PORT3 IOCR4: PC5 Mask */
\r
15113 #define PORT3_IOCR4_PC6_Pos 19 /*!< PORT3 IOCR4: PC6 Position */
\r
15114 #define PORT3_IOCR4_PC6_Msk (0x1fUL << PORT3_IOCR4_PC6_Pos) /*!< PORT3 IOCR4: PC6 Mask */
\r
15115 #define PORT3_IOCR4_PC7_Pos 27 /*!< PORT3 IOCR4: PC7 Position */
\r
15116 #define PORT3_IOCR4_PC7_Msk (0x1fUL << PORT3_IOCR4_PC7_Pos) /*!< PORT3 IOCR4: PC7 Mask */
\r
15118 /* ---------------------------------- PORT3_IN ---------------------------------- */
\r
15119 #define PORT3_IN_P0_Pos 0 /*!< PORT3 IN: P0 Position */
\r
15120 #define PORT3_IN_P0_Msk (0x01UL << PORT3_IN_P0_Pos) /*!< PORT3 IN: P0 Mask */
\r
15121 #define PORT3_IN_P1_Pos 1 /*!< PORT3 IN: P1 Position */
\r
15122 #define PORT3_IN_P1_Msk (0x01UL << PORT3_IN_P1_Pos) /*!< PORT3 IN: P1 Mask */
\r
15123 #define PORT3_IN_P2_Pos 2 /*!< PORT3 IN: P2 Position */
\r
15124 #define PORT3_IN_P2_Msk (0x01UL << PORT3_IN_P2_Pos) /*!< PORT3 IN: P2 Mask */
\r
15125 #define PORT3_IN_P3_Pos 3 /*!< PORT3 IN: P3 Position */
\r
15126 #define PORT3_IN_P3_Msk (0x01UL << PORT3_IN_P3_Pos) /*!< PORT3 IN: P3 Mask */
\r
15127 #define PORT3_IN_P4_Pos 4 /*!< PORT3 IN: P4 Position */
\r
15128 #define PORT3_IN_P4_Msk (0x01UL << PORT3_IN_P4_Pos) /*!< PORT3 IN: P4 Mask */
\r
15129 #define PORT3_IN_P5_Pos 5 /*!< PORT3 IN: P5 Position */
\r
15130 #define PORT3_IN_P5_Msk (0x01UL << PORT3_IN_P5_Pos) /*!< PORT3 IN: P5 Mask */
\r
15131 #define PORT3_IN_P6_Pos 6 /*!< PORT3 IN: P6 Position */
\r
15132 #define PORT3_IN_P6_Msk (0x01UL << PORT3_IN_P6_Pos) /*!< PORT3 IN: P6 Mask */
\r
15133 #define PORT3_IN_P7_Pos 7 /*!< PORT3 IN: P7 Position */
\r
15134 #define PORT3_IN_P7_Msk (0x01UL << PORT3_IN_P7_Pos) /*!< PORT3 IN: P7 Mask */
\r
15135 #define PORT3_IN_P8_Pos 8 /*!< PORT3 IN: P8 Position */
\r
15136 #define PORT3_IN_P8_Msk (0x01UL << PORT3_IN_P8_Pos) /*!< PORT3 IN: P8 Mask */
\r
15137 #define PORT3_IN_P9_Pos 9 /*!< PORT3 IN: P9 Position */
\r
15138 #define PORT3_IN_P9_Msk (0x01UL << PORT3_IN_P9_Pos) /*!< PORT3 IN: P9 Mask */
\r
15139 #define PORT3_IN_P10_Pos 10 /*!< PORT3 IN: P10 Position */
\r
15140 #define PORT3_IN_P10_Msk (0x01UL << PORT3_IN_P10_Pos) /*!< PORT3 IN: P10 Mask */
\r
15141 #define PORT3_IN_P11_Pos 11 /*!< PORT3 IN: P11 Position */
\r
15142 #define PORT3_IN_P11_Msk (0x01UL << PORT3_IN_P11_Pos) /*!< PORT3 IN: P11 Mask */
\r
15143 #define PORT3_IN_P12_Pos 12 /*!< PORT3 IN: P12 Position */
\r
15144 #define PORT3_IN_P12_Msk (0x01UL << PORT3_IN_P12_Pos) /*!< PORT3 IN: P12 Mask */
\r
15145 #define PORT3_IN_P13_Pos 13 /*!< PORT3 IN: P13 Position */
\r
15146 #define PORT3_IN_P13_Msk (0x01UL << PORT3_IN_P13_Pos) /*!< PORT3 IN: P13 Mask */
\r
15147 #define PORT3_IN_P14_Pos 14 /*!< PORT3 IN: P14 Position */
\r
15148 #define PORT3_IN_P14_Msk (0x01UL << PORT3_IN_P14_Pos) /*!< PORT3 IN: P14 Mask */
\r
15149 #define PORT3_IN_P15_Pos 15 /*!< PORT3 IN: P15 Position */
\r
15150 #define PORT3_IN_P15_Msk (0x01UL << PORT3_IN_P15_Pos) /*!< PORT3 IN: P15 Mask */
\r
15152 /* --------------------------------- PORT3_PDR0 --------------------------------- */
\r
15153 #define PORT3_PDR0_PD0_Pos 0 /*!< PORT3 PDR0: PD0 Position */
\r
15154 #define PORT3_PDR0_PD0_Msk (0x07UL << PORT3_PDR0_PD0_Pos) /*!< PORT3 PDR0: PD0 Mask */
\r
15155 #define PORT3_PDR0_PD1_Pos 4 /*!< PORT3 PDR0: PD1 Position */
\r
15156 #define PORT3_PDR0_PD1_Msk (0x07UL << PORT3_PDR0_PD1_Pos) /*!< PORT3 PDR0: PD1 Mask */
\r
15157 #define PORT3_PDR0_PD2_Pos 8 /*!< PORT3 PDR0: PD2 Position */
\r
15158 #define PORT3_PDR0_PD2_Msk (0x07UL << PORT3_PDR0_PD2_Pos) /*!< PORT3 PDR0: PD2 Mask */
\r
15159 #define PORT3_PDR0_PD3_Pos 12 /*!< PORT3 PDR0: PD3 Position */
\r
15160 #define PORT3_PDR0_PD3_Msk (0x07UL << PORT3_PDR0_PD3_Pos) /*!< PORT3 PDR0: PD3 Mask */
\r
15161 #define PORT3_PDR0_PD4_Pos 16 /*!< PORT3 PDR0: PD4 Position */
\r
15162 #define PORT3_PDR0_PD4_Msk (0x07UL << PORT3_PDR0_PD4_Pos) /*!< PORT3 PDR0: PD4 Mask */
\r
15163 #define PORT3_PDR0_PD5_Pos 20 /*!< PORT3 PDR0: PD5 Position */
\r
15164 #define PORT3_PDR0_PD5_Msk (0x07UL << PORT3_PDR0_PD5_Pos) /*!< PORT3 PDR0: PD5 Mask */
\r
15165 #define PORT3_PDR0_PD6_Pos 24 /*!< PORT3 PDR0: PD6 Position */
\r
15166 #define PORT3_PDR0_PD6_Msk (0x07UL << PORT3_PDR0_PD6_Pos) /*!< PORT3 PDR0: PD6 Mask */
\r
15167 #define PORT3_PDR0_PD7_Pos 28 /*!< PORT3 PDR0: PD7 Position */
\r
15168 #define PORT3_PDR0_PD7_Msk (0x07UL << PORT3_PDR0_PD7_Pos) /*!< PORT3 PDR0: PD7 Mask */
\r
15170 /* --------------------------------- PORT3_PDISC -------------------------------- */
\r
15171 #define PORT3_PDISC_PDIS0_Pos 0 /*!< PORT3 PDISC: PDIS0 Position */
\r
15172 #define PORT3_PDISC_PDIS0_Msk (0x01UL << PORT3_PDISC_PDIS0_Pos) /*!< PORT3 PDISC: PDIS0 Mask */
\r
15173 #define PORT3_PDISC_PDIS1_Pos 1 /*!< PORT3 PDISC: PDIS1 Position */
\r
15174 #define PORT3_PDISC_PDIS1_Msk (0x01UL << PORT3_PDISC_PDIS1_Pos) /*!< PORT3 PDISC: PDIS1 Mask */
\r
15175 #define PORT3_PDISC_PDIS2_Pos 2 /*!< PORT3 PDISC: PDIS2 Position */
\r
15176 #define PORT3_PDISC_PDIS2_Msk (0x01UL << PORT3_PDISC_PDIS2_Pos) /*!< PORT3 PDISC: PDIS2 Mask */
\r
15177 #define PORT3_PDISC_PDIS3_Pos 3 /*!< PORT3 PDISC: PDIS3 Position */
\r
15178 #define PORT3_PDISC_PDIS3_Msk (0x01UL << PORT3_PDISC_PDIS3_Pos) /*!< PORT3 PDISC: PDIS3 Mask */
\r
15179 #define PORT3_PDISC_PDIS4_Pos 4 /*!< PORT3 PDISC: PDIS4 Position */
\r
15180 #define PORT3_PDISC_PDIS4_Msk (0x01UL << PORT3_PDISC_PDIS4_Pos) /*!< PORT3 PDISC: PDIS4 Mask */
\r
15181 #define PORT3_PDISC_PDIS5_Pos 5 /*!< PORT3 PDISC: PDIS5 Position */
\r
15182 #define PORT3_PDISC_PDIS5_Msk (0x01UL << PORT3_PDISC_PDIS5_Pos) /*!< PORT3 PDISC: PDIS5 Mask */
\r
15183 #define PORT3_PDISC_PDIS6_Pos 6 /*!< PORT3 PDISC: PDIS6 Position */
\r
15184 #define PORT3_PDISC_PDIS6_Msk (0x01UL << PORT3_PDISC_PDIS6_Pos) /*!< PORT3 PDISC: PDIS6 Mask */
\r
15185 #define PORT3_PDISC_PDIS7_Pos 7 /*!< PORT3 PDISC: PDIS7 Position */
\r
15186 #define PORT3_PDISC_PDIS7_Msk (0x01UL << PORT3_PDISC_PDIS7_Pos) /*!< PORT3 PDISC: PDIS7 Mask */
\r
15187 #define PORT3_PDISC_PDIS8_Pos 8 /*!< PORT3 PDISC: PDIS8 Position */
\r
15188 #define PORT3_PDISC_PDIS8_Msk (0x01UL << PORT3_PDISC_PDIS8_Pos) /*!< PORT3 PDISC: PDIS8 Mask */
\r
15189 #define PORT3_PDISC_PDIS9_Pos 9 /*!< PORT3 PDISC: PDIS9 Position */
\r
15190 #define PORT3_PDISC_PDIS9_Msk (0x01UL << PORT3_PDISC_PDIS9_Pos) /*!< PORT3 PDISC: PDIS9 Mask */
\r
15191 #define PORT3_PDISC_PDIS10_Pos 10 /*!< PORT3 PDISC: PDIS10 Position */
\r
15192 #define PORT3_PDISC_PDIS10_Msk (0x01UL << PORT3_PDISC_PDIS10_Pos) /*!< PORT3 PDISC: PDIS10 Mask */
\r
15193 #define PORT3_PDISC_PDIS11_Pos 11 /*!< PORT3 PDISC: PDIS11 Position */
\r
15194 #define PORT3_PDISC_PDIS11_Msk (0x01UL << PORT3_PDISC_PDIS11_Pos) /*!< PORT3 PDISC: PDIS11 Mask */
\r
15195 #define PORT3_PDISC_PDIS12_Pos 12 /*!< PORT3 PDISC: PDIS12 Position */
\r
15196 #define PORT3_PDISC_PDIS12_Msk (0x01UL << PORT3_PDISC_PDIS12_Pos) /*!< PORT3 PDISC: PDIS12 Mask */
\r
15197 #define PORT3_PDISC_PDIS13_Pos 13 /*!< PORT3 PDISC: PDIS13 Position */
\r
15198 #define PORT3_PDISC_PDIS13_Msk (0x01UL << PORT3_PDISC_PDIS13_Pos) /*!< PORT3 PDISC: PDIS13 Mask */
\r
15199 #define PORT3_PDISC_PDIS14_Pos 14 /*!< PORT3 PDISC: PDIS14 Position */
\r
15200 #define PORT3_PDISC_PDIS14_Msk (0x01UL << PORT3_PDISC_PDIS14_Pos) /*!< PORT3 PDISC: PDIS14 Mask */
\r
15201 #define PORT3_PDISC_PDIS15_Pos 15 /*!< PORT3 PDISC: PDIS15 Position */
\r
15202 #define PORT3_PDISC_PDIS15_Msk (0x01UL << PORT3_PDISC_PDIS15_Pos) /*!< PORT3 PDISC: PDIS15 Mask */
\r
15204 /* ---------------------------------- PORT3_PPS --------------------------------- */
\r
15205 #define PORT3_PPS_PPS0_Pos 0 /*!< PORT3 PPS: PPS0 Position */
\r
15206 #define PORT3_PPS_PPS0_Msk (0x01UL << PORT3_PPS_PPS0_Pos) /*!< PORT3 PPS: PPS0 Mask */
\r
15207 #define PORT3_PPS_PPS1_Pos 1 /*!< PORT3 PPS: PPS1 Position */
\r
15208 #define PORT3_PPS_PPS1_Msk (0x01UL << PORT3_PPS_PPS1_Pos) /*!< PORT3 PPS: PPS1 Mask */
\r
15209 #define PORT3_PPS_PPS2_Pos 2 /*!< PORT3 PPS: PPS2 Position */
\r
15210 #define PORT3_PPS_PPS2_Msk (0x01UL << PORT3_PPS_PPS2_Pos) /*!< PORT3 PPS: PPS2 Mask */
\r
15211 #define PORT3_PPS_PPS3_Pos 3 /*!< PORT3 PPS: PPS3 Position */
\r
15212 #define PORT3_PPS_PPS3_Msk (0x01UL << PORT3_PPS_PPS3_Pos) /*!< PORT3 PPS: PPS3 Mask */
\r
15213 #define PORT3_PPS_PPS4_Pos 4 /*!< PORT3 PPS: PPS4 Position */
\r
15214 #define PORT3_PPS_PPS4_Msk (0x01UL << PORT3_PPS_PPS4_Pos) /*!< PORT3 PPS: PPS4 Mask */
\r
15215 #define PORT3_PPS_PPS5_Pos 5 /*!< PORT3 PPS: PPS5 Position */
\r
15216 #define PORT3_PPS_PPS5_Msk (0x01UL << PORT3_PPS_PPS5_Pos) /*!< PORT3 PPS: PPS5 Mask */
\r
15217 #define PORT3_PPS_PPS6_Pos 6 /*!< PORT3 PPS: PPS6 Position */
\r
15218 #define PORT3_PPS_PPS6_Msk (0x01UL << PORT3_PPS_PPS6_Pos) /*!< PORT3 PPS: PPS6 Mask */
\r
15219 #define PORT3_PPS_PPS7_Pos 7 /*!< PORT3 PPS: PPS7 Position */
\r
15220 #define PORT3_PPS_PPS7_Msk (0x01UL << PORT3_PPS_PPS7_Pos) /*!< PORT3 PPS: PPS7 Mask */
\r
15221 #define PORT3_PPS_PPS8_Pos 8 /*!< PORT3 PPS: PPS8 Position */
\r
15222 #define PORT3_PPS_PPS8_Msk (0x01UL << PORT3_PPS_PPS8_Pos) /*!< PORT3 PPS: PPS8 Mask */
\r
15223 #define PORT3_PPS_PPS9_Pos 9 /*!< PORT3 PPS: PPS9 Position */
\r
15224 #define PORT3_PPS_PPS9_Msk (0x01UL << PORT3_PPS_PPS9_Pos) /*!< PORT3 PPS: PPS9 Mask */
\r
15225 #define PORT3_PPS_PPS10_Pos 10 /*!< PORT3 PPS: PPS10 Position */
\r
15226 #define PORT3_PPS_PPS10_Msk (0x01UL << PORT3_PPS_PPS10_Pos) /*!< PORT3 PPS: PPS10 Mask */
\r
15227 #define PORT3_PPS_PPS11_Pos 11 /*!< PORT3 PPS: PPS11 Position */
\r
15228 #define PORT3_PPS_PPS11_Msk (0x01UL << PORT3_PPS_PPS11_Pos) /*!< PORT3 PPS: PPS11 Mask */
\r
15229 #define PORT3_PPS_PPS12_Pos 12 /*!< PORT3 PPS: PPS12 Position */
\r
15230 #define PORT3_PPS_PPS12_Msk (0x01UL << PORT3_PPS_PPS12_Pos) /*!< PORT3 PPS: PPS12 Mask */
\r
15231 #define PORT3_PPS_PPS13_Pos 13 /*!< PORT3 PPS: PPS13 Position */
\r
15232 #define PORT3_PPS_PPS13_Msk (0x01UL << PORT3_PPS_PPS13_Pos) /*!< PORT3 PPS: PPS13 Mask */
\r
15233 #define PORT3_PPS_PPS14_Pos 14 /*!< PORT3 PPS: PPS14 Position */
\r
15234 #define PORT3_PPS_PPS14_Msk (0x01UL << PORT3_PPS_PPS14_Pos) /*!< PORT3 PPS: PPS14 Mask */
\r
15235 #define PORT3_PPS_PPS15_Pos 15 /*!< PORT3 PPS: PPS15 Position */
\r
15236 #define PORT3_PPS_PPS15_Msk (0x01UL << PORT3_PPS_PPS15_Pos) /*!< PORT3 PPS: PPS15 Mask */
\r
15238 /* --------------------------------- PORT3_HWSEL -------------------------------- */
\r
15239 #define PORT3_HWSEL_HW0_Pos 0 /*!< PORT3 HWSEL: HW0 Position */
\r
15240 #define PORT3_HWSEL_HW0_Msk (0x03UL << PORT3_HWSEL_HW0_Pos) /*!< PORT3 HWSEL: HW0 Mask */
\r
15241 #define PORT3_HWSEL_HW1_Pos 2 /*!< PORT3 HWSEL: HW1 Position */
\r
15242 #define PORT3_HWSEL_HW1_Msk (0x03UL << PORT3_HWSEL_HW1_Pos) /*!< PORT3 HWSEL: HW1 Mask */
\r
15243 #define PORT3_HWSEL_HW2_Pos 4 /*!< PORT3 HWSEL: HW2 Position */
\r
15244 #define PORT3_HWSEL_HW2_Msk (0x03UL << PORT3_HWSEL_HW2_Pos) /*!< PORT3 HWSEL: HW2 Mask */
\r
15245 #define PORT3_HWSEL_HW3_Pos 6 /*!< PORT3 HWSEL: HW3 Position */
\r
15246 #define PORT3_HWSEL_HW3_Msk (0x03UL << PORT3_HWSEL_HW3_Pos) /*!< PORT3 HWSEL: HW3 Mask */
\r
15247 #define PORT3_HWSEL_HW4_Pos 8 /*!< PORT3 HWSEL: HW4 Position */
\r
15248 #define PORT3_HWSEL_HW4_Msk (0x03UL << PORT3_HWSEL_HW4_Pos) /*!< PORT3 HWSEL: HW4 Mask */
\r
15249 #define PORT3_HWSEL_HW5_Pos 10 /*!< PORT3 HWSEL: HW5 Position */
\r
15250 #define PORT3_HWSEL_HW5_Msk (0x03UL << PORT3_HWSEL_HW5_Pos) /*!< PORT3 HWSEL: HW5 Mask */
\r
15251 #define PORT3_HWSEL_HW6_Pos 12 /*!< PORT3 HWSEL: HW6 Position */
\r
15252 #define PORT3_HWSEL_HW6_Msk (0x03UL << PORT3_HWSEL_HW6_Pos) /*!< PORT3 HWSEL: HW6 Mask */
\r
15253 #define PORT3_HWSEL_HW7_Pos 14 /*!< PORT3 HWSEL: HW7 Position */
\r
15254 #define PORT3_HWSEL_HW7_Msk (0x03UL << PORT3_HWSEL_HW7_Pos) /*!< PORT3 HWSEL: HW7 Mask */
\r
15255 #define PORT3_HWSEL_HW8_Pos 16 /*!< PORT3 HWSEL: HW8 Position */
\r
15256 #define PORT3_HWSEL_HW8_Msk (0x03UL << PORT3_HWSEL_HW8_Pos) /*!< PORT3 HWSEL: HW8 Mask */
\r
15257 #define PORT3_HWSEL_HW9_Pos 18 /*!< PORT3 HWSEL: HW9 Position */
\r
15258 #define PORT3_HWSEL_HW9_Msk (0x03UL << PORT3_HWSEL_HW9_Pos) /*!< PORT3 HWSEL: HW9 Mask */
\r
15259 #define PORT3_HWSEL_HW10_Pos 20 /*!< PORT3 HWSEL: HW10 Position */
\r
15260 #define PORT3_HWSEL_HW10_Msk (0x03UL << PORT3_HWSEL_HW10_Pos) /*!< PORT3 HWSEL: HW10 Mask */
\r
15261 #define PORT3_HWSEL_HW11_Pos 22 /*!< PORT3 HWSEL: HW11 Position */
\r
15262 #define PORT3_HWSEL_HW11_Msk (0x03UL << PORT3_HWSEL_HW11_Pos) /*!< PORT3 HWSEL: HW11 Mask */
\r
15263 #define PORT3_HWSEL_HW12_Pos 24 /*!< PORT3 HWSEL: HW12 Position */
\r
15264 #define PORT3_HWSEL_HW12_Msk (0x03UL << PORT3_HWSEL_HW12_Pos) /*!< PORT3 HWSEL: HW12 Mask */
\r
15265 #define PORT3_HWSEL_HW13_Pos 26 /*!< PORT3 HWSEL: HW13 Position */
\r
15266 #define PORT3_HWSEL_HW13_Msk (0x03UL << PORT3_HWSEL_HW13_Pos) /*!< PORT3 HWSEL: HW13 Mask */
\r
15267 #define PORT3_HWSEL_HW14_Pos 28 /*!< PORT3 HWSEL: HW14 Position */
\r
15268 #define PORT3_HWSEL_HW14_Msk (0x03UL << PORT3_HWSEL_HW14_Pos) /*!< PORT3 HWSEL: HW14 Mask */
\r
15269 #define PORT3_HWSEL_HW15_Pos 30 /*!< PORT3 HWSEL: HW15 Position */
\r
15270 #define PORT3_HWSEL_HW15_Msk (0x03UL << PORT3_HWSEL_HW15_Pos) /*!< PORT3 HWSEL: HW15 Mask */
\r
15273 /* ================================================================================ */
\r
15274 /* ================ struct 'PORT4' Position & Mask ================ */
\r
15275 /* ================================================================================ */
\r
15278 /* ---------------------------------- PORT4_OUT --------------------------------- */
\r
15279 #define PORT4_OUT_P0_Pos 0 /*!< PORT4 OUT: P0 Position */
\r
15280 #define PORT4_OUT_P0_Msk (0x01UL << PORT4_OUT_P0_Pos) /*!< PORT4 OUT: P0 Mask */
\r
15281 #define PORT4_OUT_P1_Pos 1 /*!< PORT4 OUT: P1 Position */
\r
15282 #define PORT4_OUT_P1_Msk (0x01UL << PORT4_OUT_P1_Pos) /*!< PORT4 OUT: P1 Mask */
\r
15283 #define PORT4_OUT_P2_Pos 2 /*!< PORT4 OUT: P2 Position */
\r
15284 #define PORT4_OUT_P2_Msk (0x01UL << PORT4_OUT_P2_Pos) /*!< PORT4 OUT: P2 Mask */
\r
15285 #define PORT4_OUT_P3_Pos 3 /*!< PORT4 OUT: P3 Position */
\r
15286 #define PORT4_OUT_P3_Msk (0x01UL << PORT4_OUT_P3_Pos) /*!< PORT4 OUT: P3 Mask */
\r
15287 #define PORT4_OUT_P4_Pos 4 /*!< PORT4 OUT: P4 Position */
\r
15288 #define PORT4_OUT_P4_Msk (0x01UL << PORT4_OUT_P4_Pos) /*!< PORT4 OUT: P4 Mask */
\r
15289 #define PORT4_OUT_P5_Pos 5 /*!< PORT4 OUT: P5 Position */
\r
15290 #define PORT4_OUT_P5_Msk (0x01UL << PORT4_OUT_P5_Pos) /*!< PORT4 OUT: P5 Mask */
\r
15291 #define PORT4_OUT_P6_Pos 6 /*!< PORT4 OUT: P6 Position */
\r
15292 #define PORT4_OUT_P6_Msk (0x01UL << PORT4_OUT_P6_Pos) /*!< PORT4 OUT: P6 Mask */
\r
15293 #define PORT4_OUT_P7_Pos 7 /*!< PORT4 OUT: P7 Position */
\r
15294 #define PORT4_OUT_P7_Msk (0x01UL << PORT4_OUT_P7_Pos) /*!< PORT4 OUT: P7 Mask */
\r
15295 #define PORT4_OUT_P8_Pos 8 /*!< PORT4 OUT: P8 Position */
\r
15296 #define PORT4_OUT_P8_Msk (0x01UL << PORT4_OUT_P8_Pos) /*!< PORT4 OUT: P8 Mask */
\r
15297 #define PORT4_OUT_P9_Pos 9 /*!< PORT4 OUT: P9 Position */
\r
15298 #define PORT4_OUT_P9_Msk (0x01UL << PORT4_OUT_P9_Pos) /*!< PORT4 OUT: P9 Mask */
\r
15299 #define PORT4_OUT_P10_Pos 10 /*!< PORT4 OUT: P10 Position */
\r
15300 #define PORT4_OUT_P10_Msk (0x01UL << PORT4_OUT_P10_Pos) /*!< PORT4 OUT: P10 Mask */
\r
15301 #define PORT4_OUT_P11_Pos 11 /*!< PORT4 OUT: P11 Position */
\r
15302 #define PORT4_OUT_P11_Msk (0x01UL << PORT4_OUT_P11_Pos) /*!< PORT4 OUT: P11 Mask */
\r
15303 #define PORT4_OUT_P12_Pos 12 /*!< PORT4 OUT: P12 Position */
\r
15304 #define PORT4_OUT_P12_Msk (0x01UL << PORT4_OUT_P12_Pos) /*!< PORT4 OUT: P12 Mask */
\r
15305 #define PORT4_OUT_P13_Pos 13 /*!< PORT4 OUT: P13 Position */
\r
15306 #define PORT4_OUT_P13_Msk (0x01UL << PORT4_OUT_P13_Pos) /*!< PORT4 OUT: P13 Mask */
\r
15307 #define PORT4_OUT_P14_Pos 14 /*!< PORT4 OUT: P14 Position */
\r
15308 #define PORT4_OUT_P14_Msk (0x01UL << PORT4_OUT_P14_Pos) /*!< PORT4 OUT: P14 Mask */
\r
15309 #define PORT4_OUT_P15_Pos 15 /*!< PORT4 OUT: P15 Position */
\r
15310 #define PORT4_OUT_P15_Msk (0x01UL << PORT4_OUT_P15_Pos) /*!< PORT4 OUT: P15 Mask */
\r
15312 /* ---------------------------------- PORT4_OMR --------------------------------- */
\r
15313 #define PORT4_OMR_PS0_Pos 0 /*!< PORT4 OMR: PS0 Position */
\r
15314 #define PORT4_OMR_PS0_Msk (0x01UL << PORT4_OMR_PS0_Pos) /*!< PORT4 OMR: PS0 Mask */
\r
15315 #define PORT4_OMR_PS1_Pos 1 /*!< PORT4 OMR: PS1 Position */
\r
15316 #define PORT4_OMR_PS1_Msk (0x01UL << PORT4_OMR_PS1_Pos) /*!< PORT4 OMR: PS1 Mask */
\r
15317 #define PORT4_OMR_PS2_Pos 2 /*!< PORT4 OMR: PS2 Position */
\r
15318 #define PORT4_OMR_PS2_Msk (0x01UL << PORT4_OMR_PS2_Pos) /*!< PORT4 OMR: PS2 Mask */
\r
15319 #define PORT4_OMR_PS3_Pos 3 /*!< PORT4 OMR: PS3 Position */
\r
15320 #define PORT4_OMR_PS3_Msk (0x01UL << PORT4_OMR_PS3_Pos) /*!< PORT4 OMR: PS3 Mask */
\r
15321 #define PORT4_OMR_PS4_Pos 4 /*!< PORT4 OMR: PS4 Position */
\r
15322 #define PORT4_OMR_PS4_Msk (0x01UL << PORT4_OMR_PS4_Pos) /*!< PORT4 OMR: PS4 Mask */
\r
15323 #define PORT4_OMR_PS5_Pos 5 /*!< PORT4 OMR: PS5 Position */
\r
15324 #define PORT4_OMR_PS5_Msk (0x01UL << PORT4_OMR_PS5_Pos) /*!< PORT4 OMR: PS5 Mask */
\r
15325 #define PORT4_OMR_PS6_Pos 6 /*!< PORT4 OMR: PS6 Position */
\r
15326 #define PORT4_OMR_PS6_Msk (0x01UL << PORT4_OMR_PS6_Pos) /*!< PORT4 OMR: PS6 Mask */
\r
15327 #define PORT4_OMR_PS7_Pos 7 /*!< PORT4 OMR: PS7 Position */
\r
15328 #define PORT4_OMR_PS7_Msk (0x01UL << PORT4_OMR_PS7_Pos) /*!< PORT4 OMR: PS7 Mask */
\r
15329 #define PORT4_OMR_PS8_Pos 8 /*!< PORT4 OMR: PS8 Position */
\r
15330 #define PORT4_OMR_PS8_Msk (0x01UL << PORT4_OMR_PS8_Pos) /*!< PORT4 OMR: PS8 Mask */
\r
15331 #define PORT4_OMR_PS9_Pos 9 /*!< PORT4 OMR: PS9 Position */
\r
15332 #define PORT4_OMR_PS9_Msk (0x01UL << PORT4_OMR_PS9_Pos) /*!< PORT4 OMR: PS9 Mask */
\r
15333 #define PORT4_OMR_PS10_Pos 10 /*!< PORT4 OMR: PS10 Position */
\r
15334 #define PORT4_OMR_PS10_Msk (0x01UL << PORT4_OMR_PS10_Pos) /*!< PORT4 OMR: PS10 Mask */
\r
15335 #define PORT4_OMR_PS11_Pos 11 /*!< PORT4 OMR: PS11 Position */
\r
15336 #define PORT4_OMR_PS11_Msk (0x01UL << PORT4_OMR_PS11_Pos) /*!< PORT4 OMR: PS11 Mask */
\r
15337 #define PORT4_OMR_PS12_Pos 12 /*!< PORT4 OMR: PS12 Position */
\r
15338 #define PORT4_OMR_PS12_Msk (0x01UL << PORT4_OMR_PS12_Pos) /*!< PORT4 OMR: PS12 Mask */
\r
15339 #define PORT4_OMR_PS13_Pos 13 /*!< PORT4 OMR: PS13 Position */
\r
15340 #define PORT4_OMR_PS13_Msk (0x01UL << PORT4_OMR_PS13_Pos) /*!< PORT4 OMR: PS13 Mask */
\r
15341 #define PORT4_OMR_PS14_Pos 14 /*!< PORT4 OMR: PS14 Position */
\r
15342 #define PORT4_OMR_PS14_Msk (0x01UL << PORT4_OMR_PS14_Pos) /*!< PORT4 OMR: PS14 Mask */
\r
15343 #define PORT4_OMR_PS15_Pos 15 /*!< PORT4 OMR: PS15 Position */
\r
15344 #define PORT4_OMR_PS15_Msk (0x01UL << PORT4_OMR_PS15_Pos) /*!< PORT4 OMR: PS15 Mask */
\r
15345 #define PORT4_OMR_PR0_Pos 16 /*!< PORT4 OMR: PR0 Position */
\r
15346 #define PORT4_OMR_PR0_Msk (0x01UL << PORT4_OMR_PR0_Pos) /*!< PORT4 OMR: PR0 Mask */
\r
15347 #define PORT4_OMR_PR1_Pos 17 /*!< PORT4 OMR: PR1 Position */
\r
15348 #define PORT4_OMR_PR1_Msk (0x01UL << PORT4_OMR_PR1_Pos) /*!< PORT4 OMR: PR1 Mask */
\r
15349 #define PORT4_OMR_PR2_Pos 18 /*!< PORT4 OMR: PR2 Position */
\r
15350 #define PORT4_OMR_PR2_Msk (0x01UL << PORT4_OMR_PR2_Pos) /*!< PORT4 OMR: PR2 Mask */
\r
15351 #define PORT4_OMR_PR3_Pos 19 /*!< PORT4 OMR: PR3 Position */
\r
15352 #define PORT4_OMR_PR3_Msk (0x01UL << PORT4_OMR_PR3_Pos) /*!< PORT4 OMR: PR3 Mask */
\r
15353 #define PORT4_OMR_PR4_Pos 20 /*!< PORT4 OMR: PR4 Position */
\r
15354 #define PORT4_OMR_PR4_Msk (0x01UL << PORT4_OMR_PR4_Pos) /*!< PORT4 OMR: PR4 Mask */
\r
15355 #define PORT4_OMR_PR5_Pos 21 /*!< PORT4 OMR: PR5 Position */
\r
15356 #define PORT4_OMR_PR5_Msk (0x01UL << PORT4_OMR_PR5_Pos) /*!< PORT4 OMR: PR5 Mask */
\r
15357 #define PORT4_OMR_PR6_Pos 22 /*!< PORT4 OMR: PR6 Position */
\r
15358 #define PORT4_OMR_PR6_Msk (0x01UL << PORT4_OMR_PR6_Pos) /*!< PORT4 OMR: PR6 Mask */
\r
15359 #define PORT4_OMR_PR7_Pos 23 /*!< PORT4 OMR: PR7 Position */
\r
15360 #define PORT4_OMR_PR7_Msk (0x01UL << PORT4_OMR_PR7_Pos) /*!< PORT4 OMR: PR7 Mask */
\r
15361 #define PORT4_OMR_PR8_Pos 24 /*!< PORT4 OMR: PR8 Position */
\r
15362 #define PORT4_OMR_PR8_Msk (0x01UL << PORT4_OMR_PR8_Pos) /*!< PORT4 OMR: PR8 Mask */
\r
15363 #define PORT4_OMR_PR9_Pos 25 /*!< PORT4 OMR: PR9 Position */
\r
15364 #define PORT4_OMR_PR9_Msk (0x01UL << PORT4_OMR_PR9_Pos) /*!< PORT4 OMR: PR9 Mask */
\r
15365 #define PORT4_OMR_PR10_Pos 26 /*!< PORT4 OMR: PR10 Position */
\r
15366 #define PORT4_OMR_PR10_Msk (0x01UL << PORT4_OMR_PR10_Pos) /*!< PORT4 OMR: PR10 Mask */
\r
15367 #define PORT4_OMR_PR11_Pos 27 /*!< PORT4 OMR: PR11 Position */
\r
15368 #define PORT4_OMR_PR11_Msk (0x01UL << PORT4_OMR_PR11_Pos) /*!< PORT4 OMR: PR11 Mask */
\r
15369 #define PORT4_OMR_PR12_Pos 28 /*!< PORT4 OMR: PR12 Position */
\r
15370 #define PORT4_OMR_PR12_Msk (0x01UL << PORT4_OMR_PR12_Pos) /*!< PORT4 OMR: PR12 Mask */
\r
15371 #define PORT4_OMR_PR13_Pos 29 /*!< PORT4 OMR: PR13 Position */
\r
15372 #define PORT4_OMR_PR13_Msk (0x01UL << PORT4_OMR_PR13_Pos) /*!< PORT4 OMR: PR13 Mask */
\r
15373 #define PORT4_OMR_PR14_Pos 30 /*!< PORT4 OMR: PR14 Position */
\r
15374 #define PORT4_OMR_PR14_Msk (0x01UL << PORT4_OMR_PR14_Pos) /*!< PORT4 OMR: PR14 Mask */
\r
15375 #define PORT4_OMR_PR15_Pos 31 /*!< PORT4 OMR: PR15 Position */
\r
15376 #define PORT4_OMR_PR15_Msk (0x01UL << PORT4_OMR_PR15_Pos) /*!< PORT4 OMR: PR15 Mask */
\r
15378 /* --------------------------------- PORT4_IOCR0 -------------------------------- */
\r
15379 #define PORT4_IOCR0_PC0_Pos 3 /*!< PORT4 IOCR0: PC0 Position */
\r
15380 #define PORT4_IOCR0_PC0_Msk (0x1fUL << PORT4_IOCR0_PC0_Pos) /*!< PORT4 IOCR0: PC0 Mask */
\r
15381 #define PORT4_IOCR0_PC1_Pos 11 /*!< PORT4 IOCR0: PC1 Position */
\r
15382 #define PORT4_IOCR0_PC1_Msk (0x1fUL << PORT4_IOCR0_PC1_Pos) /*!< PORT4 IOCR0: PC1 Mask */
\r
15383 #define PORT4_IOCR0_PC2_Pos 19 /*!< PORT4 IOCR0: PC2 Position */
\r
15384 #define PORT4_IOCR0_PC2_Msk (0x1fUL << PORT4_IOCR0_PC2_Pos) /*!< PORT4 IOCR0: PC2 Mask */
\r
15385 #define PORT4_IOCR0_PC3_Pos 27 /*!< PORT4 IOCR0: PC3 Position */
\r
15386 #define PORT4_IOCR0_PC3_Msk (0x1fUL << PORT4_IOCR0_PC3_Pos) /*!< PORT4 IOCR0: PC3 Mask */
\r
15388 /* ---------------------------------- PORT4_IN ---------------------------------- */
\r
15389 #define PORT4_IN_P0_Pos 0 /*!< PORT4 IN: P0 Position */
\r
15390 #define PORT4_IN_P0_Msk (0x01UL << PORT4_IN_P0_Pos) /*!< PORT4 IN: P0 Mask */
\r
15391 #define PORT4_IN_P1_Pos 1 /*!< PORT4 IN: P1 Position */
\r
15392 #define PORT4_IN_P1_Msk (0x01UL << PORT4_IN_P1_Pos) /*!< PORT4 IN: P1 Mask */
\r
15393 #define PORT4_IN_P2_Pos 2 /*!< PORT4 IN: P2 Position */
\r
15394 #define PORT4_IN_P2_Msk (0x01UL << PORT4_IN_P2_Pos) /*!< PORT4 IN: P2 Mask */
\r
15395 #define PORT4_IN_P3_Pos 3 /*!< PORT4 IN: P3 Position */
\r
15396 #define PORT4_IN_P3_Msk (0x01UL << PORT4_IN_P3_Pos) /*!< PORT4 IN: P3 Mask */
\r
15397 #define PORT4_IN_P4_Pos 4 /*!< PORT4 IN: P4 Position */
\r
15398 #define PORT4_IN_P4_Msk (0x01UL << PORT4_IN_P4_Pos) /*!< PORT4 IN: P4 Mask */
\r
15399 #define PORT4_IN_P5_Pos 5 /*!< PORT4 IN: P5 Position */
\r
15400 #define PORT4_IN_P5_Msk (0x01UL << PORT4_IN_P5_Pos) /*!< PORT4 IN: P5 Mask */
\r
15401 #define PORT4_IN_P6_Pos 6 /*!< PORT4 IN: P6 Position */
\r
15402 #define PORT4_IN_P6_Msk (0x01UL << PORT4_IN_P6_Pos) /*!< PORT4 IN: P6 Mask */
\r
15403 #define PORT4_IN_P7_Pos 7 /*!< PORT4 IN: P7 Position */
\r
15404 #define PORT4_IN_P7_Msk (0x01UL << PORT4_IN_P7_Pos) /*!< PORT4 IN: P7 Mask */
\r
15405 #define PORT4_IN_P8_Pos 8 /*!< PORT4 IN: P8 Position */
\r
15406 #define PORT4_IN_P8_Msk (0x01UL << PORT4_IN_P8_Pos) /*!< PORT4 IN: P8 Mask */
\r
15407 #define PORT4_IN_P9_Pos 9 /*!< PORT4 IN: P9 Position */
\r
15408 #define PORT4_IN_P9_Msk (0x01UL << PORT4_IN_P9_Pos) /*!< PORT4 IN: P9 Mask */
\r
15409 #define PORT4_IN_P10_Pos 10 /*!< PORT4 IN: P10 Position */
\r
15410 #define PORT4_IN_P10_Msk (0x01UL << PORT4_IN_P10_Pos) /*!< PORT4 IN: P10 Mask */
\r
15411 #define PORT4_IN_P11_Pos 11 /*!< PORT4 IN: P11 Position */
\r
15412 #define PORT4_IN_P11_Msk (0x01UL << PORT4_IN_P11_Pos) /*!< PORT4 IN: P11 Mask */
\r
15413 #define PORT4_IN_P12_Pos 12 /*!< PORT4 IN: P12 Position */
\r
15414 #define PORT4_IN_P12_Msk (0x01UL << PORT4_IN_P12_Pos) /*!< PORT4 IN: P12 Mask */
\r
15415 #define PORT4_IN_P13_Pos 13 /*!< PORT4 IN: P13 Position */
\r
15416 #define PORT4_IN_P13_Msk (0x01UL << PORT4_IN_P13_Pos) /*!< PORT4 IN: P13 Mask */
\r
15417 #define PORT4_IN_P14_Pos 14 /*!< PORT4 IN: P14 Position */
\r
15418 #define PORT4_IN_P14_Msk (0x01UL << PORT4_IN_P14_Pos) /*!< PORT4 IN: P14 Mask */
\r
15419 #define PORT4_IN_P15_Pos 15 /*!< PORT4 IN: P15 Position */
\r
15420 #define PORT4_IN_P15_Msk (0x01UL << PORT4_IN_P15_Pos) /*!< PORT4 IN: P15 Mask */
\r
15422 /* --------------------------------- PORT4_PDR0 --------------------------------- */
\r
15423 #define PORT4_PDR0_PD0_Pos 0 /*!< PORT4 PDR0: PD0 Position */
\r
15424 #define PORT4_PDR0_PD0_Msk (0x07UL << PORT4_PDR0_PD0_Pos) /*!< PORT4 PDR0: PD0 Mask */
\r
15425 #define PORT4_PDR0_PD1_Pos 4 /*!< PORT4 PDR0: PD1 Position */
\r
15426 #define PORT4_PDR0_PD1_Msk (0x07UL << PORT4_PDR0_PD1_Pos) /*!< PORT4 PDR0: PD1 Mask */
\r
15427 #define PORT4_PDR0_PD2_Pos 8 /*!< PORT4 PDR0: PD2 Position */
\r
15428 #define PORT4_PDR0_PD2_Msk (0x07UL << PORT4_PDR0_PD2_Pos) /*!< PORT4 PDR0: PD2 Mask */
\r
15429 #define PORT4_PDR0_PD3_Pos 12 /*!< PORT4 PDR0: PD3 Position */
\r
15430 #define PORT4_PDR0_PD3_Msk (0x07UL << PORT4_PDR0_PD3_Pos) /*!< PORT4 PDR0: PD3 Mask */
\r
15431 #define PORT4_PDR0_PD4_Pos 16 /*!< PORT4 PDR0: PD4 Position */
\r
15432 #define PORT4_PDR0_PD4_Msk (0x07UL << PORT4_PDR0_PD4_Pos) /*!< PORT4 PDR0: PD4 Mask */
\r
15433 #define PORT4_PDR0_PD5_Pos 20 /*!< PORT4 PDR0: PD5 Position */
\r
15434 #define PORT4_PDR0_PD5_Msk (0x07UL << PORT4_PDR0_PD5_Pos) /*!< PORT4 PDR0: PD5 Mask */
\r
15435 #define PORT4_PDR0_PD6_Pos 24 /*!< PORT4 PDR0: PD6 Position */
\r
15436 #define PORT4_PDR0_PD6_Msk (0x07UL << PORT4_PDR0_PD6_Pos) /*!< PORT4 PDR0: PD6 Mask */
\r
15437 #define PORT4_PDR0_PD7_Pos 28 /*!< PORT4 PDR0: PD7 Position */
\r
15438 #define PORT4_PDR0_PD7_Msk (0x07UL << PORT4_PDR0_PD7_Pos) /*!< PORT4 PDR0: PD7 Mask */
\r
15440 /* --------------------------------- PORT4_PDISC -------------------------------- */
\r
15441 #define PORT4_PDISC_PDIS0_Pos 0 /*!< PORT4 PDISC: PDIS0 Position */
\r
15442 #define PORT4_PDISC_PDIS0_Msk (0x01UL << PORT4_PDISC_PDIS0_Pos) /*!< PORT4 PDISC: PDIS0 Mask */
\r
15443 #define PORT4_PDISC_PDIS1_Pos 1 /*!< PORT4 PDISC: PDIS1 Position */
\r
15444 #define PORT4_PDISC_PDIS1_Msk (0x01UL << PORT4_PDISC_PDIS1_Pos) /*!< PORT4 PDISC: PDIS1 Mask */
\r
15445 #define PORT4_PDISC_PDIS2_Pos 2 /*!< PORT4 PDISC: PDIS2 Position */
\r
15446 #define PORT4_PDISC_PDIS2_Msk (0x01UL << PORT4_PDISC_PDIS2_Pos) /*!< PORT4 PDISC: PDIS2 Mask */
\r
15447 #define PORT4_PDISC_PDIS3_Pos 3 /*!< PORT4 PDISC: PDIS3 Position */
\r
15448 #define PORT4_PDISC_PDIS3_Msk (0x01UL << PORT4_PDISC_PDIS3_Pos) /*!< PORT4 PDISC: PDIS3 Mask */
\r
15449 #define PORT4_PDISC_PDIS4_Pos 4 /*!< PORT4 PDISC: PDIS4 Position */
\r
15450 #define PORT4_PDISC_PDIS4_Msk (0x01UL << PORT4_PDISC_PDIS4_Pos) /*!< PORT4 PDISC: PDIS4 Mask */
\r
15451 #define PORT4_PDISC_PDIS5_Pos 5 /*!< PORT4 PDISC: PDIS5 Position */
\r
15452 #define PORT4_PDISC_PDIS5_Msk (0x01UL << PORT4_PDISC_PDIS5_Pos) /*!< PORT4 PDISC: PDIS5 Mask */
\r
15453 #define PORT4_PDISC_PDIS6_Pos 6 /*!< PORT4 PDISC: PDIS6 Position */
\r
15454 #define PORT4_PDISC_PDIS6_Msk (0x01UL << PORT4_PDISC_PDIS6_Pos) /*!< PORT4 PDISC: PDIS6 Mask */
\r
15455 #define PORT4_PDISC_PDIS7_Pos 7 /*!< PORT4 PDISC: PDIS7 Position */
\r
15456 #define PORT4_PDISC_PDIS7_Msk (0x01UL << PORT4_PDISC_PDIS7_Pos) /*!< PORT4 PDISC: PDIS7 Mask */
\r
15457 #define PORT4_PDISC_PDIS8_Pos 8 /*!< PORT4 PDISC: PDIS8 Position */
\r
15458 #define PORT4_PDISC_PDIS8_Msk (0x01UL << PORT4_PDISC_PDIS8_Pos) /*!< PORT4 PDISC: PDIS8 Mask */
\r
15459 #define PORT4_PDISC_PDIS9_Pos 9 /*!< PORT4 PDISC: PDIS9 Position */
\r
15460 #define PORT4_PDISC_PDIS9_Msk (0x01UL << PORT4_PDISC_PDIS9_Pos) /*!< PORT4 PDISC: PDIS9 Mask */
\r
15461 #define PORT4_PDISC_PDIS10_Pos 10 /*!< PORT4 PDISC: PDIS10 Position */
\r
15462 #define PORT4_PDISC_PDIS10_Msk (0x01UL << PORT4_PDISC_PDIS10_Pos) /*!< PORT4 PDISC: PDIS10 Mask */
\r
15463 #define PORT4_PDISC_PDIS11_Pos 11 /*!< PORT4 PDISC: PDIS11 Position */
\r
15464 #define PORT4_PDISC_PDIS11_Msk (0x01UL << PORT4_PDISC_PDIS11_Pos) /*!< PORT4 PDISC: PDIS11 Mask */
\r
15465 #define PORT4_PDISC_PDIS12_Pos 12 /*!< PORT4 PDISC: PDIS12 Position */
\r
15466 #define PORT4_PDISC_PDIS12_Msk (0x01UL << PORT4_PDISC_PDIS12_Pos) /*!< PORT4 PDISC: PDIS12 Mask */
\r
15467 #define PORT4_PDISC_PDIS13_Pos 13 /*!< PORT4 PDISC: PDIS13 Position */
\r
15468 #define PORT4_PDISC_PDIS13_Msk (0x01UL << PORT4_PDISC_PDIS13_Pos) /*!< PORT4 PDISC: PDIS13 Mask */
\r
15469 #define PORT4_PDISC_PDIS14_Pos 14 /*!< PORT4 PDISC: PDIS14 Position */
\r
15470 #define PORT4_PDISC_PDIS14_Msk (0x01UL << PORT4_PDISC_PDIS14_Pos) /*!< PORT4 PDISC: PDIS14 Mask */
\r
15471 #define PORT4_PDISC_PDIS15_Pos 15 /*!< PORT4 PDISC: PDIS15 Position */
\r
15472 #define PORT4_PDISC_PDIS15_Msk (0x01UL << PORT4_PDISC_PDIS15_Pos) /*!< PORT4 PDISC: PDIS15 Mask */
\r
15474 /* ---------------------------------- PORT4_PPS --------------------------------- */
\r
15475 #define PORT4_PPS_PPS0_Pos 0 /*!< PORT4 PPS: PPS0 Position */
\r
15476 #define PORT4_PPS_PPS0_Msk (0x01UL << PORT4_PPS_PPS0_Pos) /*!< PORT4 PPS: PPS0 Mask */
\r
15477 #define PORT4_PPS_PPS1_Pos 1 /*!< PORT4 PPS: PPS1 Position */
\r
15478 #define PORT4_PPS_PPS1_Msk (0x01UL << PORT4_PPS_PPS1_Pos) /*!< PORT4 PPS: PPS1 Mask */
\r
15479 #define PORT4_PPS_PPS2_Pos 2 /*!< PORT4 PPS: PPS2 Position */
\r
15480 #define PORT4_PPS_PPS2_Msk (0x01UL << PORT4_PPS_PPS2_Pos) /*!< PORT4 PPS: PPS2 Mask */
\r
15481 #define PORT4_PPS_PPS3_Pos 3 /*!< PORT4 PPS: PPS3 Position */
\r
15482 #define PORT4_PPS_PPS3_Msk (0x01UL << PORT4_PPS_PPS3_Pos) /*!< PORT4 PPS: PPS3 Mask */
\r
15483 #define PORT4_PPS_PPS4_Pos 4 /*!< PORT4 PPS: PPS4 Position */
\r
15484 #define PORT4_PPS_PPS4_Msk (0x01UL << PORT4_PPS_PPS4_Pos) /*!< PORT4 PPS: PPS4 Mask */
\r
15485 #define PORT4_PPS_PPS5_Pos 5 /*!< PORT4 PPS: PPS5 Position */
\r
15486 #define PORT4_PPS_PPS5_Msk (0x01UL << PORT4_PPS_PPS5_Pos) /*!< PORT4 PPS: PPS5 Mask */
\r
15487 #define PORT4_PPS_PPS6_Pos 6 /*!< PORT4 PPS: PPS6 Position */
\r
15488 #define PORT4_PPS_PPS6_Msk (0x01UL << PORT4_PPS_PPS6_Pos) /*!< PORT4 PPS: PPS6 Mask */
\r
15489 #define PORT4_PPS_PPS7_Pos 7 /*!< PORT4 PPS: PPS7 Position */
\r
15490 #define PORT4_PPS_PPS7_Msk (0x01UL << PORT4_PPS_PPS7_Pos) /*!< PORT4 PPS: PPS7 Mask */
\r
15491 #define PORT4_PPS_PPS8_Pos 8 /*!< PORT4 PPS: PPS8 Position */
\r
15492 #define PORT4_PPS_PPS8_Msk (0x01UL << PORT4_PPS_PPS8_Pos) /*!< PORT4 PPS: PPS8 Mask */
\r
15493 #define PORT4_PPS_PPS9_Pos 9 /*!< PORT4 PPS: PPS9 Position */
\r
15494 #define PORT4_PPS_PPS9_Msk (0x01UL << PORT4_PPS_PPS9_Pos) /*!< PORT4 PPS: PPS9 Mask */
\r
15495 #define PORT4_PPS_PPS10_Pos 10 /*!< PORT4 PPS: PPS10 Position */
\r
15496 #define PORT4_PPS_PPS10_Msk (0x01UL << PORT4_PPS_PPS10_Pos) /*!< PORT4 PPS: PPS10 Mask */
\r
15497 #define PORT4_PPS_PPS11_Pos 11 /*!< PORT4 PPS: PPS11 Position */
\r
15498 #define PORT4_PPS_PPS11_Msk (0x01UL << PORT4_PPS_PPS11_Pos) /*!< PORT4 PPS: PPS11 Mask */
\r
15499 #define PORT4_PPS_PPS12_Pos 12 /*!< PORT4 PPS: PPS12 Position */
\r
15500 #define PORT4_PPS_PPS12_Msk (0x01UL << PORT4_PPS_PPS12_Pos) /*!< PORT4 PPS: PPS12 Mask */
\r
15501 #define PORT4_PPS_PPS13_Pos 13 /*!< PORT4 PPS: PPS13 Position */
\r
15502 #define PORT4_PPS_PPS13_Msk (0x01UL << PORT4_PPS_PPS13_Pos) /*!< PORT4 PPS: PPS13 Mask */
\r
15503 #define PORT4_PPS_PPS14_Pos 14 /*!< PORT4 PPS: PPS14 Position */
\r
15504 #define PORT4_PPS_PPS14_Msk (0x01UL << PORT4_PPS_PPS14_Pos) /*!< PORT4 PPS: PPS14 Mask */
\r
15505 #define PORT4_PPS_PPS15_Pos 15 /*!< PORT4 PPS: PPS15 Position */
\r
15506 #define PORT4_PPS_PPS15_Msk (0x01UL << PORT4_PPS_PPS15_Pos) /*!< PORT4 PPS: PPS15 Mask */
\r
15508 /* --------------------------------- PORT4_HWSEL -------------------------------- */
\r
15509 #define PORT4_HWSEL_HW0_Pos 0 /*!< PORT4 HWSEL: HW0 Position */
\r
15510 #define PORT4_HWSEL_HW0_Msk (0x03UL << PORT4_HWSEL_HW0_Pos) /*!< PORT4 HWSEL: HW0 Mask */
\r
15511 #define PORT4_HWSEL_HW1_Pos 2 /*!< PORT4 HWSEL: HW1 Position */
\r
15512 #define PORT4_HWSEL_HW1_Msk (0x03UL << PORT4_HWSEL_HW1_Pos) /*!< PORT4 HWSEL: HW1 Mask */
\r
15513 #define PORT4_HWSEL_HW2_Pos 4 /*!< PORT4 HWSEL: HW2 Position */
\r
15514 #define PORT4_HWSEL_HW2_Msk (0x03UL << PORT4_HWSEL_HW2_Pos) /*!< PORT4 HWSEL: HW2 Mask */
\r
15515 #define PORT4_HWSEL_HW3_Pos 6 /*!< PORT4 HWSEL: HW3 Position */
\r
15516 #define PORT4_HWSEL_HW3_Msk (0x03UL << PORT4_HWSEL_HW3_Pos) /*!< PORT4 HWSEL: HW3 Mask */
\r
15517 #define PORT4_HWSEL_HW4_Pos 8 /*!< PORT4 HWSEL: HW4 Position */
\r
15518 #define PORT4_HWSEL_HW4_Msk (0x03UL << PORT4_HWSEL_HW4_Pos) /*!< PORT4 HWSEL: HW4 Mask */
\r
15519 #define PORT4_HWSEL_HW5_Pos 10 /*!< PORT4 HWSEL: HW5 Position */
\r
15520 #define PORT4_HWSEL_HW5_Msk (0x03UL << PORT4_HWSEL_HW5_Pos) /*!< PORT4 HWSEL: HW5 Mask */
\r
15521 #define PORT4_HWSEL_HW6_Pos 12 /*!< PORT4 HWSEL: HW6 Position */
\r
15522 #define PORT4_HWSEL_HW6_Msk (0x03UL << PORT4_HWSEL_HW6_Pos) /*!< PORT4 HWSEL: HW6 Mask */
\r
15523 #define PORT4_HWSEL_HW7_Pos 14 /*!< PORT4 HWSEL: HW7 Position */
\r
15524 #define PORT4_HWSEL_HW7_Msk (0x03UL << PORT4_HWSEL_HW7_Pos) /*!< PORT4 HWSEL: HW7 Mask */
\r
15525 #define PORT4_HWSEL_HW8_Pos 16 /*!< PORT4 HWSEL: HW8 Position */
\r
15526 #define PORT4_HWSEL_HW8_Msk (0x03UL << PORT4_HWSEL_HW8_Pos) /*!< PORT4 HWSEL: HW8 Mask */
\r
15527 #define PORT4_HWSEL_HW9_Pos 18 /*!< PORT4 HWSEL: HW9 Position */
\r
15528 #define PORT4_HWSEL_HW9_Msk (0x03UL << PORT4_HWSEL_HW9_Pos) /*!< PORT4 HWSEL: HW9 Mask */
\r
15529 #define PORT4_HWSEL_HW10_Pos 20 /*!< PORT4 HWSEL: HW10 Position */
\r
15530 #define PORT4_HWSEL_HW10_Msk (0x03UL << PORT4_HWSEL_HW10_Pos) /*!< PORT4 HWSEL: HW10 Mask */
\r
15531 #define PORT4_HWSEL_HW11_Pos 22 /*!< PORT4 HWSEL: HW11 Position */
\r
15532 #define PORT4_HWSEL_HW11_Msk (0x03UL << PORT4_HWSEL_HW11_Pos) /*!< PORT4 HWSEL: HW11 Mask */
\r
15533 #define PORT4_HWSEL_HW12_Pos 24 /*!< PORT4 HWSEL: HW12 Position */
\r
15534 #define PORT4_HWSEL_HW12_Msk (0x03UL << PORT4_HWSEL_HW12_Pos) /*!< PORT4 HWSEL: HW12 Mask */
\r
15535 #define PORT4_HWSEL_HW13_Pos 26 /*!< PORT4 HWSEL: HW13 Position */
\r
15536 #define PORT4_HWSEL_HW13_Msk (0x03UL << PORT4_HWSEL_HW13_Pos) /*!< PORT4 HWSEL: HW13 Mask */
\r
15537 #define PORT4_HWSEL_HW14_Pos 28 /*!< PORT4 HWSEL: HW14 Position */
\r
15538 #define PORT4_HWSEL_HW14_Msk (0x03UL << PORT4_HWSEL_HW14_Pos) /*!< PORT4 HWSEL: HW14 Mask */
\r
15539 #define PORT4_HWSEL_HW15_Pos 30 /*!< PORT4 HWSEL: HW15 Position */
\r
15540 #define PORT4_HWSEL_HW15_Msk (0x03UL << PORT4_HWSEL_HW15_Pos) /*!< PORT4 HWSEL: HW15 Mask */
\r
15543 /* ================================================================================ */
\r
15544 /* ================ struct 'PORT5' Position & Mask ================ */
\r
15545 /* ================================================================================ */
\r
15548 /* ---------------------------------- PORT5_OUT --------------------------------- */
\r
15549 #define PORT5_OUT_P0_Pos 0 /*!< PORT5 OUT: P0 Position */
\r
15550 #define PORT5_OUT_P0_Msk (0x01UL << PORT5_OUT_P0_Pos) /*!< PORT5 OUT: P0 Mask */
\r
15551 #define PORT5_OUT_P1_Pos 1 /*!< PORT5 OUT: P1 Position */
\r
15552 #define PORT5_OUT_P1_Msk (0x01UL << PORT5_OUT_P1_Pos) /*!< PORT5 OUT: P1 Mask */
\r
15553 #define PORT5_OUT_P2_Pos 2 /*!< PORT5 OUT: P2 Position */
\r
15554 #define PORT5_OUT_P2_Msk (0x01UL << PORT5_OUT_P2_Pos) /*!< PORT5 OUT: P2 Mask */
\r
15555 #define PORT5_OUT_P3_Pos 3 /*!< PORT5 OUT: P3 Position */
\r
15556 #define PORT5_OUT_P3_Msk (0x01UL << PORT5_OUT_P3_Pos) /*!< PORT5 OUT: P3 Mask */
\r
15557 #define PORT5_OUT_P4_Pos 4 /*!< PORT5 OUT: P4 Position */
\r
15558 #define PORT5_OUT_P4_Msk (0x01UL << PORT5_OUT_P4_Pos) /*!< PORT5 OUT: P4 Mask */
\r
15559 #define PORT5_OUT_P5_Pos 5 /*!< PORT5 OUT: P5 Position */
\r
15560 #define PORT5_OUT_P5_Msk (0x01UL << PORT5_OUT_P5_Pos) /*!< PORT5 OUT: P5 Mask */
\r
15561 #define PORT5_OUT_P6_Pos 6 /*!< PORT5 OUT: P6 Position */
\r
15562 #define PORT5_OUT_P6_Msk (0x01UL << PORT5_OUT_P6_Pos) /*!< PORT5 OUT: P6 Mask */
\r
15563 #define PORT5_OUT_P7_Pos 7 /*!< PORT5 OUT: P7 Position */
\r
15564 #define PORT5_OUT_P7_Msk (0x01UL << PORT5_OUT_P7_Pos) /*!< PORT5 OUT: P7 Mask */
\r
15565 #define PORT5_OUT_P8_Pos 8 /*!< PORT5 OUT: P8 Position */
\r
15566 #define PORT5_OUT_P8_Msk (0x01UL << PORT5_OUT_P8_Pos) /*!< PORT5 OUT: P8 Mask */
\r
15567 #define PORT5_OUT_P9_Pos 9 /*!< PORT5 OUT: P9 Position */
\r
15568 #define PORT5_OUT_P9_Msk (0x01UL << PORT5_OUT_P9_Pos) /*!< PORT5 OUT: P9 Mask */
\r
15569 #define PORT5_OUT_P10_Pos 10 /*!< PORT5 OUT: P10 Position */
\r
15570 #define PORT5_OUT_P10_Msk (0x01UL << PORT5_OUT_P10_Pos) /*!< PORT5 OUT: P10 Mask */
\r
15571 #define PORT5_OUT_P11_Pos 11 /*!< PORT5 OUT: P11 Position */
\r
15572 #define PORT5_OUT_P11_Msk (0x01UL << PORT5_OUT_P11_Pos) /*!< PORT5 OUT: P11 Mask */
\r
15573 #define PORT5_OUT_P12_Pos 12 /*!< PORT5 OUT: P12 Position */
\r
15574 #define PORT5_OUT_P12_Msk (0x01UL << PORT5_OUT_P12_Pos) /*!< PORT5 OUT: P12 Mask */
\r
15575 #define PORT5_OUT_P13_Pos 13 /*!< PORT5 OUT: P13 Position */
\r
15576 #define PORT5_OUT_P13_Msk (0x01UL << PORT5_OUT_P13_Pos) /*!< PORT5 OUT: P13 Mask */
\r
15577 #define PORT5_OUT_P14_Pos 14 /*!< PORT5 OUT: P14 Position */
\r
15578 #define PORT5_OUT_P14_Msk (0x01UL << PORT5_OUT_P14_Pos) /*!< PORT5 OUT: P14 Mask */
\r
15579 #define PORT5_OUT_P15_Pos 15 /*!< PORT5 OUT: P15 Position */
\r
15580 #define PORT5_OUT_P15_Msk (0x01UL << PORT5_OUT_P15_Pos) /*!< PORT5 OUT: P15 Mask */
\r
15582 /* ---------------------------------- PORT5_OMR --------------------------------- */
\r
15583 #define PORT5_OMR_PS0_Pos 0 /*!< PORT5 OMR: PS0 Position */
\r
15584 #define PORT5_OMR_PS0_Msk (0x01UL << PORT5_OMR_PS0_Pos) /*!< PORT5 OMR: PS0 Mask */
\r
15585 #define PORT5_OMR_PS1_Pos 1 /*!< PORT5 OMR: PS1 Position */
\r
15586 #define PORT5_OMR_PS1_Msk (0x01UL << PORT5_OMR_PS1_Pos) /*!< PORT5 OMR: PS1 Mask */
\r
15587 #define PORT5_OMR_PS2_Pos 2 /*!< PORT5 OMR: PS2 Position */
\r
15588 #define PORT5_OMR_PS2_Msk (0x01UL << PORT5_OMR_PS2_Pos) /*!< PORT5 OMR: PS2 Mask */
\r
15589 #define PORT5_OMR_PS3_Pos 3 /*!< PORT5 OMR: PS3 Position */
\r
15590 #define PORT5_OMR_PS3_Msk (0x01UL << PORT5_OMR_PS3_Pos) /*!< PORT5 OMR: PS3 Mask */
\r
15591 #define PORT5_OMR_PS4_Pos 4 /*!< PORT5 OMR: PS4 Position */
\r
15592 #define PORT5_OMR_PS4_Msk (0x01UL << PORT5_OMR_PS4_Pos) /*!< PORT5 OMR: PS4 Mask */
\r
15593 #define PORT5_OMR_PS5_Pos 5 /*!< PORT5 OMR: PS5 Position */
\r
15594 #define PORT5_OMR_PS5_Msk (0x01UL << PORT5_OMR_PS5_Pos) /*!< PORT5 OMR: PS5 Mask */
\r
15595 #define PORT5_OMR_PS6_Pos 6 /*!< PORT5 OMR: PS6 Position */
\r
15596 #define PORT5_OMR_PS6_Msk (0x01UL << PORT5_OMR_PS6_Pos) /*!< PORT5 OMR: PS6 Mask */
\r
15597 #define PORT5_OMR_PS7_Pos 7 /*!< PORT5 OMR: PS7 Position */
\r
15598 #define PORT5_OMR_PS7_Msk (0x01UL << PORT5_OMR_PS7_Pos) /*!< PORT5 OMR: PS7 Mask */
\r
15599 #define PORT5_OMR_PS8_Pos 8 /*!< PORT5 OMR: PS8 Position */
\r
15600 #define PORT5_OMR_PS8_Msk (0x01UL << PORT5_OMR_PS8_Pos) /*!< PORT5 OMR: PS8 Mask */
\r
15601 #define PORT5_OMR_PS9_Pos 9 /*!< PORT5 OMR: PS9 Position */
\r
15602 #define PORT5_OMR_PS9_Msk (0x01UL << PORT5_OMR_PS9_Pos) /*!< PORT5 OMR: PS9 Mask */
\r
15603 #define PORT5_OMR_PS10_Pos 10 /*!< PORT5 OMR: PS10 Position */
\r
15604 #define PORT5_OMR_PS10_Msk (0x01UL << PORT5_OMR_PS10_Pos) /*!< PORT5 OMR: PS10 Mask */
\r
15605 #define PORT5_OMR_PS11_Pos 11 /*!< PORT5 OMR: PS11 Position */
\r
15606 #define PORT5_OMR_PS11_Msk (0x01UL << PORT5_OMR_PS11_Pos) /*!< PORT5 OMR: PS11 Mask */
\r
15607 #define PORT5_OMR_PS12_Pos 12 /*!< PORT5 OMR: PS12 Position */
\r
15608 #define PORT5_OMR_PS12_Msk (0x01UL << PORT5_OMR_PS12_Pos) /*!< PORT5 OMR: PS12 Mask */
\r
15609 #define PORT5_OMR_PS13_Pos 13 /*!< PORT5 OMR: PS13 Position */
\r
15610 #define PORT5_OMR_PS13_Msk (0x01UL << PORT5_OMR_PS13_Pos) /*!< PORT5 OMR: PS13 Mask */
\r
15611 #define PORT5_OMR_PS14_Pos 14 /*!< PORT5 OMR: PS14 Position */
\r
15612 #define PORT5_OMR_PS14_Msk (0x01UL << PORT5_OMR_PS14_Pos) /*!< PORT5 OMR: PS14 Mask */
\r
15613 #define PORT5_OMR_PS15_Pos 15 /*!< PORT5 OMR: PS15 Position */
\r
15614 #define PORT5_OMR_PS15_Msk (0x01UL << PORT5_OMR_PS15_Pos) /*!< PORT5 OMR: PS15 Mask */
\r
15615 #define PORT5_OMR_PR0_Pos 16 /*!< PORT5 OMR: PR0 Position */
\r
15616 #define PORT5_OMR_PR0_Msk (0x01UL << PORT5_OMR_PR0_Pos) /*!< PORT5 OMR: PR0 Mask */
\r
15617 #define PORT5_OMR_PR1_Pos 17 /*!< PORT5 OMR: PR1 Position */
\r
15618 #define PORT5_OMR_PR1_Msk (0x01UL << PORT5_OMR_PR1_Pos) /*!< PORT5 OMR: PR1 Mask */
\r
15619 #define PORT5_OMR_PR2_Pos 18 /*!< PORT5 OMR: PR2 Position */
\r
15620 #define PORT5_OMR_PR2_Msk (0x01UL << PORT5_OMR_PR2_Pos) /*!< PORT5 OMR: PR2 Mask */
\r
15621 #define PORT5_OMR_PR3_Pos 19 /*!< PORT5 OMR: PR3 Position */
\r
15622 #define PORT5_OMR_PR3_Msk (0x01UL << PORT5_OMR_PR3_Pos) /*!< PORT5 OMR: PR3 Mask */
\r
15623 #define PORT5_OMR_PR4_Pos 20 /*!< PORT5 OMR: PR4 Position */
\r
15624 #define PORT5_OMR_PR4_Msk (0x01UL << PORT5_OMR_PR4_Pos) /*!< PORT5 OMR: PR4 Mask */
\r
15625 #define PORT5_OMR_PR5_Pos 21 /*!< PORT5 OMR: PR5 Position */
\r
15626 #define PORT5_OMR_PR5_Msk (0x01UL << PORT5_OMR_PR5_Pos) /*!< PORT5 OMR: PR5 Mask */
\r
15627 #define PORT5_OMR_PR6_Pos 22 /*!< PORT5 OMR: PR6 Position */
\r
15628 #define PORT5_OMR_PR6_Msk (0x01UL << PORT5_OMR_PR6_Pos) /*!< PORT5 OMR: PR6 Mask */
\r
15629 #define PORT5_OMR_PR7_Pos 23 /*!< PORT5 OMR: PR7 Position */
\r
15630 #define PORT5_OMR_PR7_Msk (0x01UL << PORT5_OMR_PR7_Pos) /*!< PORT5 OMR: PR7 Mask */
\r
15631 #define PORT5_OMR_PR8_Pos 24 /*!< PORT5 OMR: PR8 Position */
\r
15632 #define PORT5_OMR_PR8_Msk (0x01UL << PORT5_OMR_PR8_Pos) /*!< PORT5 OMR: PR8 Mask */
\r
15633 #define PORT5_OMR_PR9_Pos 25 /*!< PORT5 OMR: PR9 Position */
\r
15634 #define PORT5_OMR_PR9_Msk (0x01UL << PORT5_OMR_PR9_Pos) /*!< PORT5 OMR: PR9 Mask */
\r
15635 #define PORT5_OMR_PR10_Pos 26 /*!< PORT5 OMR: PR10 Position */
\r
15636 #define PORT5_OMR_PR10_Msk (0x01UL << PORT5_OMR_PR10_Pos) /*!< PORT5 OMR: PR10 Mask */
\r
15637 #define PORT5_OMR_PR11_Pos 27 /*!< PORT5 OMR: PR11 Position */
\r
15638 #define PORT5_OMR_PR11_Msk (0x01UL << PORT5_OMR_PR11_Pos) /*!< PORT5 OMR: PR11 Mask */
\r
15639 #define PORT5_OMR_PR12_Pos 28 /*!< PORT5 OMR: PR12 Position */
\r
15640 #define PORT5_OMR_PR12_Msk (0x01UL << PORT5_OMR_PR12_Pos) /*!< PORT5 OMR: PR12 Mask */
\r
15641 #define PORT5_OMR_PR13_Pos 29 /*!< PORT5 OMR: PR13 Position */
\r
15642 #define PORT5_OMR_PR13_Msk (0x01UL << PORT5_OMR_PR13_Pos) /*!< PORT5 OMR: PR13 Mask */
\r
15643 #define PORT5_OMR_PR14_Pos 30 /*!< PORT5 OMR: PR14 Position */
\r
15644 #define PORT5_OMR_PR14_Msk (0x01UL << PORT5_OMR_PR14_Pos) /*!< PORT5 OMR: PR14 Mask */
\r
15645 #define PORT5_OMR_PR15_Pos 31 /*!< PORT5 OMR: PR15 Position */
\r
15646 #define PORT5_OMR_PR15_Msk (0x01UL << PORT5_OMR_PR15_Pos) /*!< PORT5 OMR: PR15 Mask */
\r
15648 /* --------------------------------- PORT5_IOCR0 -------------------------------- */
\r
15649 #define PORT5_IOCR0_PC0_Pos 3 /*!< PORT5 IOCR0: PC0 Position */
\r
15650 #define PORT5_IOCR0_PC0_Msk (0x1fUL << PORT5_IOCR0_PC0_Pos) /*!< PORT5 IOCR0: PC0 Mask */
\r
15651 #define PORT5_IOCR0_PC1_Pos 11 /*!< PORT5 IOCR0: PC1 Position */
\r
15652 #define PORT5_IOCR0_PC1_Msk (0x1fUL << PORT5_IOCR0_PC1_Pos) /*!< PORT5 IOCR0: PC1 Mask */
\r
15653 #define PORT5_IOCR0_PC2_Pos 19 /*!< PORT5 IOCR0: PC2 Position */
\r
15654 #define PORT5_IOCR0_PC2_Msk (0x1fUL << PORT5_IOCR0_PC2_Pos) /*!< PORT5 IOCR0: PC2 Mask */
\r
15655 #define PORT5_IOCR0_PC3_Pos 27 /*!< PORT5 IOCR0: PC3 Position */
\r
15656 #define PORT5_IOCR0_PC3_Msk (0x1fUL << PORT5_IOCR0_PC3_Pos) /*!< PORT5 IOCR0: PC3 Mask */
\r
15658 /* --------------------------------- PORT5_IOCR4 -------------------------------- */
\r
15659 #define PORT5_IOCR4_PC4_Pos 3 /*!< PORT5 IOCR4: PC4 Position */
\r
15660 #define PORT5_IOCR4_PC4_Msk (0x1fUL << PORT5_IOCR4_PC4_Pos) /*!< PORT5 IOCR4: PC4 Mask */
\r
15661 #define PORT5_IOCR4_PC5_Pos 11 /*!< PORT5 IOCR4: PC5 Position */
\r
15662 #define PORT5_IOCR4_PC5_Msk (0x1fUL << PORT5_IOCR4_PC5_Pos) /*!< PORT5 IOCR4: PC5 Mask */
\r
15663 #define PORT5_IOCR4_PC6_Pos 19 /*!< PORT5 IOCR4: PC6 Position */
\r
15664 #define PORT5_IOCR4_PC6_Msk (0x1fUL << PORT5_IOCR4_PC6_Pos) /*!< PORT5 IOCR4: PC6 Mask */
\r
15665 #define PORT5_IOCR4_PC7_Pos 27 /*!< PORT5 IOCR4: PC7 Position */
\r
15666 #define PORT5_IOCR4_PC7_Msk (0x1fUL << PORT5_IOCR4_PC7_Pos) /*!< PORT5 IOCR4: PC7 Mask */
\r
15668 /* ---------------------------------- PORT5_IN ---------------------------------- */
\r
15669 #define PORT5_IN_P0_Pos 0 /*!< PORT5 IN: P0 Position */
\r
15670 #define PORT5_IN_P0_Msk (0x01UL << PORT5_IN_P0_Pos) /*!< PORT5 IN: P0 Mask */
\r
15671 #define PORT5_IN_P1_Pos 1 /*!< PORT5 IN: P1 Position */
\r
15672 #define PORT5_IN_P1_Msk (0x01UL << PORT5_IN_P1_Pos) /*!< PORT5 IN: P1 Mask */
\r
15673 #define PORT5_IN_P2_Pos 2 /*!< PORT5 IN: P2 Position */
\r
15674 #define PORT5_IN_P2_Msk (0x01UL << PORT5_IN_P2_Pos) /*!< PORT5 IN: P2 Mask */
\r
15675 #define PORT5_IN_P3_Pos 3 /*!< PORT5 IN: P3 Position */
\r
15676 #define PORT5_IN_P3_Msk (0x01UL << PORT5_IN_P3_Pos) /*!< PORT5 IN: P3 Mask */
\r
15677 #define PORT5_IN_P4_Pos 4 /*!< PORT5 IN: P4 Position */
\r
15678 #define PORT5_IN_P4_Msk (0x01UL << PORT5_IN_P4_Pos) /*!< PORT5 IN: P4 Mask */
\r
15679 #define PORT5_IN_P5_Pos 5 /*!< PORT5 IN: P5 Position */
\r
15680 #define PORT5_IN_P5_Msk (0x01UL << PORT5_IN_P5_Pos) /*!< PORT5 IN: P5 Mask */
\r
15681 #define PORT5_IN_P6_Pos 6 /*!< PORT5 IN: P6 Position */
\r
15682 #define PORT5_IN_P6_Msk (0x01UL << PORT5_IN_P6_Pos) /*!< PORT5 IN: P6 Mask */
\r
15683 #define PORT5_IN_P7_Pos 7 /*!< PORT5 IN: P7 Position */
\r
15684 #define PORT5_IN_P7_Msk (0x01UL << PORT5_IN_P7_Pos) /*!< PORT5 IN: P7 Mask */
\r
15685 #define PORT5_IN_P8_Pos 8 /*!< PORT5 IN: P8 Position */
\r
15686 #define PORT5_IN_P8_Msk (0x01UL << PORT5_IN_P8_Pos) /*!< PORT5 IN: P8 Mask */
\r
15687 #define PORT5_IN_P9_Pos 9 /*!< PORT5 IN: P9 Position */
\r
15688 #define PORT5_IN_P9_Msk (0x01UL << PORT5_IN_P9_Pos) /*!< PORT5 IN: P9 Mask */
\r
15689 #define PORT5_IN_P10_Pos 10 /*!< PORT5 IN: P10 Position */
\r
15690 #define PORT5_IN_P10_Msk (0x01UL << PORT5_IN_P10_Pos) /*!< PORT5 IN: P10 Mask */
\r
15691 #define PORT5_IN_P11_Pos 11 /*!< PORT5 IN: P11 Position */
\r
15692 #define PORT5_IN_P11_Msk (0x01UL << PORT5_IN_P11_Pos) /*!< PORT5 IN: P11 Mask */
\r
15693 #define PORT5_IN_P12_Pos 12 /*!< PORT5 IN: P12 Position */
\r
15694 #define PORT5_IN_P12_Msk (0x01UL << PORT5_IN_P12_Pos) /*!< PORT5 IN: P12 Mask */
\r
15695 #define PORT5_IN_P13_Pos 13 /*!< PORT5 IN: P13 Position */
\r
15696 #define PORT5_IN_P13_Msk (0x01UL << PORT5_IN_P13_Pos) /*!< PORT5 IN: P13 Mask */
\r
15697 #define PORT5_IN_P14_Pos 14 /*!< PORT5 IN: P14 Position */
\r
15698 #define PORT5_IN_P14_Msk (0x01UL << PORT5_IN_P14_Pos) /*!< PORT5 IN: P14 Mask */
\r
15699 #define PORT5_IN_P15_Pos 15 /*!< PORT5 IN: P15 Position */
\r
15700 #define PORT5_IN_P15_Msk (0x01UL << PORT5_IN_P15_Pos) /*!< PORT5 IN: P15 Mask */
\r
15702 /* --------------------------------- PORT5_PDR0 --------------------------------- */
\r
15703 #define PORT5_PDR0_PD0_Pos 0 /*!< PORT5 PDR0: PD0 Position */
\r
15704 #define PORT5_PDR0_PD0_Msk (0x07UL << PORT5_PDR0_PD0_Pos) /*!< PORT5 PDR0: PD0 Mask */
\r
15705 #define PORT5_PDR0_PD1_Pos 4 /*!< PORT5 PDR0: PD1 Position */
\r
15706 #define PORT5_PDR0_PD1_Msk (0x07UL << PORT5_PDR0_PD1_Pos) /*!< PORT5 PDR0: PD1 Mask */
\r
15707 #define PORT5_PDR0_PD2_Pos 8 /*!< PORT5 PDR0: PD2 Position */
\r
15708 #define PORT5_PDR0_PD2_Msk (0x07UL << PORT5_PDR0_PD2_Pos) /*!< PORT5 PDR0: PD2 Mask */
\r
15709 #define PORT5_PDR0_PD3_Pos 12 /*!< PORT5 PDR0: PD3 Position */
\r
15710 #define PORT5_PDR0_PD3_Msk (0x07UL << PORT5_PDR0_PD3_Pos) /*!< PORT5 PDR0: PD3 Mask */
\r
15711 #define PORT5_PDR0_PD4_Pos 16 /*!< PORT5 PDR0: PD4 Position */
\r
15712 #define PORT5_PDR0_PD4_Msk (0x07UL << PORT5_PDR0_PD4_Pos) /*!< PORT5 PDR0: PD4 Mask */
\r
15713 #define PORT5_PDR0_PD5_Pos 20 /*!< PORT5 PDR0: PD5 Position */
\r
15714 #define PORT5_PDR0_PD5_Msk (0x07UL << PORT5_PDR0_PD5_Pos) /*!< PORT5 PDR0: PD5 Mask */
\r
15715 #define PORT5_PDR0_PD6_Pos 24 /*!< PORT5 PDR0: PD6 Position */
\r
15716 #define PORT5_PDR0_PD6_Msk (0x07UL << PORT5_PDR0_PD6_Pos) /*!< PORT5 PDR0: PD6 Mask */
\r
15717 #define PORT5_PDR0_PD7_Pos 28 /*!< PORT5 PDR0: PD7 Position */
\r
15718 #define PORT5_PDR0_PD7_Msk (0x07UL << PORT5_PDR0_PD7_Pos) /*!< PORT5 PDR0: PD7 Mask */
\r
15720 /* --------------------------------- PORT5_PDISC -------------------------------- */
\r
15721 #define PORT5_PDISC_PDIS0_Pos 0 /*!< PORT5 PDISC: PDIS0 Position */
\r
15722 #define PORT5_PDISC_PDIS0_Msk (0x01UL << PORT5_PDISC_PDIS0_Pos) /*!< PORT5 PDISC: PDIS0 Mask */
\r
15723 #define PORT5_PDISC_PDIS1_Pos 1 /*!< PORT5 PDISC: PDIS1 Position */
\r
15724 #define PORT5_PDISC_PDIS1_Msk (0x01UL << PORT5_PDISC_PDIS1_Pos) /*!< PORT5 PDISC: PDIS1 Mask */
\r
15725 #define PORT5_PDISC_PDIS2_Pos 2 /*!< PORT5 PDISC: PDIS2 Position */
\r
15726 #define PORT5_PDISC_PDIS2_Msk (0x01UL << PORT5_PDISC_PDIS2_Pos) /*!< PORT5 PDISC: PDIS2 Mask */
\r
15727 #define PORT5_PDISC_PDIS3_Pos 3 /*!< PORT5 PDISC: PDIS3 Position */
\r
15728 #define PORT5_PDISC_PDIS3_Msk (0x01UL << PORT5_PDISC_PDIS3_Pos) /*!< PORT5 PDISC: PDIS3 Mask */
\r
15729 #define PORT5_PDISC_PDIS4_Pos 4 /*!< PORT5 PDISC: PDIS4 Position */
\r
15730 #define PORT5_PDISC_PDIS4_Msk (0x01UL << PORT5_PDISC_PDIS4_Pos) /*!< PORT5 PDISC: PDIS4 Mask */
\r
15731 #define PORT5_PDISC_PDIS5_Pos 5 /*!< PORT5 PDISC: PDIS5 Position */
\r
15732 #define PORT5_PDISC_PDIS5_Msk (0x01UL << PORT5_PDISC_PDIS5_Pos) /*!< PORT5 PDISC: PDIS5 Mask */
\r
15733 #define PORT5_PDISC_PDIS6_Pos 6 /*!< PORT5 PDISC: PDIS6 Position */
\r
15734 #define PORT5_PDISC_PDIS6_Msk (0x01UL << PORT5_PDISC_PDIS6_Pos) /*!< PORT5 PDISC: PDIS6 Mask */
\r
15735 #define PORT5_PDISC_PDIS7_Pos 7 /*!< PORT5 PDISC: PDIS7 Position */
\r
15736 #define PORT5_PDISC_PDIS7_Msk (0x01UL << PORT5_PDISC_PDIS7_Pos) /*!< PORT5 PDISC: PDIS7 Mask */
\r
15737 #define PORT5_PDISC_PDIS8_Pos 8 /*!< PORT5 PDISC: PDIS8 Position */
\r
15738 #define PORT5_PDISC_PDIS8_Msk (0x01UL << PORT5_PDISC_PDIS8_Pos) /*!< PORT5 PDISC: PDIS8 Mask */
\r
15739 #define PORT5_PDISC_PDIS9_Pos 9 /*!< PORT5 PDISC: PDIS9 Position */
\r
15740 #define PORT5_PDISC_PDIS9_Msk (0x01UL << PORT5_PDISC_PDIS9_Pos) /*!< PORT5 PDISC: PDIS9 Mask */
\r
15741 #define PORT5_PDISC_PDIS10_Pos 10 /*!< PORT5 PDISC: PDIS10 Position */
\r
15742 #define PORT5_PDISC_PDIS10_Msk (0x01UL << PORT5_PDISC_PDIS10_Pos) /*!< PORT5 PDISC: PDIS10 Mask */
\r
15743 #define PORT5_PDISC_PDIS11_Pos 11 /*!< PORT5 PDISC: PDIS11 Position */
\r
15744 #define PORT5_PDISC_PDIS11_Msk (0x01UL << PORT5_PDISC_PDIS11_Pos) /*!< PORT5 PDISC: PDIS11 Mask */
\r
15745 #define PORT5_PDISC_PDIS12_Pos 12 /*!< PORT5 PDISC: PDIS12 Position */
\r
15746 #define PORT5_PDISC_PDIS12_Msk (0x01UL << PORT5_PDISC_PDIS12_Pos) /*!< PORT5 PDISC: PDIS12 Mask */
\r
15747 #define PORT5_PDISC_PDIS13_Pos 13 /*!< PORT5 PDISC: PDIS13 Position */
\r
15748 #define PORT5_PDISC_PDIS13_Msk (0x01UL << PORT5_PDISC_PDIS13_Pos) /*!< PORT5 PDISC: PDIS13 Mask */
\r
15749 #define PORT5_PDISC_PDIS14_Pos 14 /*!< PORT5 PDISC: PDIS14 Position */
\r
15750 #define PORT5_PDISC_PDIS14_Msk (0x01UL << PORT5_PDISC_PDIS14_Pos) /*!< PORT5 PDISC: PDIS14 Mask */
\r
15751 #define PORT5_PDISC_PDIS15_Pos 15 /*!< PORT5 PDISC: PDIS15 Position */
\r
15752 #define PORT5_PDISC_PDIS15_Msk (0x01UL << PORT5_PDISC_PDIS15_Pos) /*!< PORT5 PDISC: PDIS15 Mask */
\r
15754 /* ---------------------------------- PORT5_PPS --------------------------------- */
\r
15755 #define PORT5_PPS_PPS0_Pos 0 /*!< PORT5 PPS: PPS0 Position */
\r
15756 #define PORT5_PPS_PPS0_Msk (0x01UL << PORT5_PPS_PPS0_Pos) /*!< PORT5 PPS: PPS0 Mask */
\r
15757 #define PORT5_PPS_PPS1_Pos 1 /*!< PORT5 PPS: PPS1 Position */
\r
15758 #define PORT5_PPS_PPS1_Msk (0x01UL << PORT5_PPS_PPS1_Pos) /*!< PORT5 PPS: PPS1 Mask */
\r
15759 #define PORT5_PPS_PPS2_Pos 2 /*!< PORT5 PPS: PPS2 Position */
\r
15760 #define PORT5_PPS_PPS2_Msk (0x01UL << PORT5_PPS_PPS2_Pos) /*!< PORT5 PPS: PPS2 Mask */
\r
15761 #define PORT5_PPS_PPS3_Pos 3 /*!< PORT5 PPS: PPS3 Position */
\r
15762 #define PORT5_PPS_PPS3_Msk (0x01UL << PORT5_PPS_PPS3_Pos) /*!< PORT5 PPS: PPS3 Mask */
\r
15763 #define PORT5_PPS_PPS4_Pos 4 /*!< PORT5 PPS: PPS4 Position */
\r
15764 #define PORT5_PPS_PPS4_Msk (0x01UL << PORT5_PPS_PPS4_Pos) /*!< PORT5 PPS: PPS4 Mask */
\r
15765 #define PORT5_PPS_PPS5_Pos 5 /*!< PORT5 PPS: PPS5 Position */
\r
15766 #define PORT5_PPS_PPS5_Msk (0x01UL << PORT5_PPS_PPS5_Pos) /*!< PORT5 PPS: PPS5 Mask */
\r
15767 #define PORT5_PPS_PPS6_Pos 6 /*!< PORT5 PPS: PPS6 Position */
\r
15768 #define PORT5_PPS_PPS6_Msk (0x01UL << PORT5_PPS_PPS6_Pos) /*!< PORT5 PPS: PPS6 Mask */
\r
15769 #define PORT5_PPS_PPS7_Pos 7 /*!< PORT5 PPS: PPS7 Position */
\r
15770 #define PORT5_PPS_PPS7_Msk (0x01UL << PORT5_PPS_PPS7_Pos) /*!< PORT5 PPS: PPS7 Mask */
\r
15771 #define PORT5_PPS_PPS8_Pos 8 /*!< PORT5 PPS: PPS8 Position */
\r
15772 #define PORT5_PPS_PPS8_Msk (0x01UL << PORT5_PPS_PPS8_Pos) /*!< PORT5 PPS: PPS8 Mask */
\r
15773 #define PORT5_PPS_PPS9_Pos 9 /*!< PORT5 PPS: PPS9 Position */
\r
15774 #define PORT5_PPS_PPS9_Msk (0x01UL << PORT5_PPS_PPS9_Pos) /*!< PORT5 PPS: PPS9 Mask */
\r
15775 #define PORT5_PPS_PPS10_Pos 10 /*!< PORT5 PPS: PPS10 Position */
\r
15776 #define PORT5_PPS_PPS10_Msk (0x01UL << PORT5_PPS_PPS10_Pos) /*!< PORT5 PPS: PPS10 Mask */
\r
15777 #define PORT5_PPS_PPS11_Pos 11 /*!< PORT5 PPS: PPS11 Position */
\r
15778 #define PORT5_PPS_PPS11_Msk (0x01UL << PORT5_PPS_PPS11_Pos) /*!< PORT5 PPS: PPS11 Mask */
\r
15779 #define PORT5_PPS_PPS12_Pos 12 /*!< PORT5 PPS: PPS12 Position */
\r
15780 #define PORT5_PPS_PPS12_Msk (0x01UL << PORT5_PPS_PPS12_Pos) /*!< PORT5 PPS: PPS12 Mask */
\r
15781 #define PORT5_PPS_PPS13_Pos 13 /*!< PORT5 PPS: PPS13 Position */
\r
15782 #define PORT5_PPS_PPS13_Msk (0x01UL << PORT5_PPS_PPS13_Pos) /*!< PORT5 PPS: PPS13 Mask */
\r
15783 #define PORT5_PPS_PPS14_Pos 14 /*!< PORT5 PPS: PPS14 Position */
\r
15784 #define PORT5_PPS_PPS14_Msk (0x01UL << PORT5_PPS_PPS14_Pos) /*!< PORT5 PPS: PPS14 Mask */
\r
15785 #define PORT5_PPS_PPS15_Pos 15 /*!< PORT5 PPS: PPS15 Position */
\r
15786 #define PORT5_PPS_PPS15_Msk (0x01UL << PORT5_PPS_PPS15_Pos) /*!< PORT5 PPS: PPS15 Mask */
\r
15788 /* --------------------------------- PORT5_HWSEL -------------------------------- */
\r
15789 #define PORT5_HWSEL_HW0_Pos 0 /*!< PORT5 HWSEL: HW0 Position */
\r
15790 #define PORT5_HWSEL_HW0_Msk (0x03UL << PORT5_HWSEL_HW0_Pos) /*!< PORT5 HWSEL: HW0 Mask */
\r
15791 #define PORT5_HWSEL_HW1_Pos 2 /*!< PORT5 HWSEL: HW1 Position */
\r
15792 #define PORT5_HWSEL_HW1_Msk (0x03UL << PORT5_HWSEL_HW1_Pos) /*!< PORT5 HWSEL: HW1 Mask */
\r
15793 #define PORT5_HWSEL_HW2_Pos 4 /*!< PORT5 HWSEL: HW2 Position */
\r
15794 #define PORT5_HWSEL_HW2_Msk (0x03UL << PORT5_HWSEL_HW2_Pos) /*!< PORT5 HWSEL: HW2 Mask */
\r
15795 #define PORT5_HWSEL_HW3_Pos 6 /*!< PORT5 HWSEL: HW3 Position */
\r
15796 #define PORT5_HWSEL_HW3_Msk (0x03UL << PORT5_HWSEL_HW3_Pos) /*!< PORT5 HWSEL: HW3 Mask */
\r
15797 #define PORT5_HWSEL_HW4_Pos 8 /*!< PORT5 HWSEL: HW4 Position */
\r
15798 #define PORT5_HWSEL_HW4_Msk (0x03UL << PORT5_HWSEL_HW4_Pos) /*!< PORT5 HWSEL: HW4 Mask */
\r
15799 #define PORT5_HWSEL_HW5_Pos 10 /*!< PORT5 HWSEL: HW5 Position */
\r
15800 #define PORT5_HWSEL_HW5_Msk (0x03UL << PORT5_HWSEL_HW5_Pos) /*!< PORT5 HWSEL: HW5 Mask */
\r
15801 #define PORT5_HWSEL_HW6_Pos 12 /*!< PORT5 HWSEL: HW6 Position */
\r
15802 #define PORT5_HWSEL_HW6_Msk (0x03UL << PORT5_HWSEL_HW6_Pos) /*!< PORT5 HWSEL: HW6 Mask */
\r
15803 #define PORT5_HWSEL_HW7_Pos 14 /*!< PORT5 HWSEL: HW7 Position */
\r
15804 #define PORT5_HWSEL_HW7_Msk (0x03UL << PORT5_HWSEL_HW7_Pos) /*!< PORT5 HWSEL: HW7 Mask */
\r
15805 #define PORT5_HWSEL_HW8_Pos 16 /*!< PORT5 HWSEL: HW8 Position */
\r
15806 #define PORT5_HWSEL_HW8_Msk (0x03UL << PORT5_HWSEL_HW8_Pos) /*!< PORT5 HWSEL: HW8 Mask */
\r
15807 #define PORT5_HWSEL_HW9_Pos 18 /*!< PORT5 HWSEL: HW9 Position */
\r
15808 #define PORT5_HWSEL_HW9_Msk (0x03UL << PORT5_HWSEL_HW9_Pos) /*!< PORT5 HWSEL: HW9 Mask */
\r
15809 #define PORT5_HWSEL_HW10_Pos 20 /*!< PORT5 HWSEL: HW10 Position */
\r
15810 #define PORT5_HWSEL_HW10_Msk (0x03UL << PORT5_HWSEL_HW10_Pos) /*!< PORT5 HWSEL: HW10 Mask */
\r
15811 #define PORT5_HWSEL_HW11_Pos 22 /*!< PORT5 HWSEL: HW11 Position */
\r
15812 #define PORT5_HWSEL_HW11_Msk (0x03UL << PORT5_HWSEL_HW11_Pos) /*!< PORT5 HWSEL: HW11 Mask */
\r
15813 #define PORT5_HWSEL_HW12_Pos 24 /*!< PORT5 HWSEL: HW12 Position */
\r
15814 #define PORT5_HWSEL_HW12_Msk (0x03UL << PORT5_HWSEL_HW12_Pos) /*!< PORT5 HWSEL: HW12 Mask */
\r
15815 #define PORT5_HWSEL_HW13_Pos 26 /*!< PORT5 HWSEL: HW13 Position */
\r
15816 #define PORT5_HWSEL_HW13_Msk (0x03UL << PORT5_HWSEL_HW13_Pos) /*!< PORT5 HWSEL: HW13 Mask */
\r
15817 #define PORT5_HWSEL_HW14_Pos 28 /*!< PORT5 HWSEL: HW14 Position */
\r
15818 #define PORT5_HWSEL_HW14_Msk (0x03UL << PORT5_HWSEL_HW14_Pos) /*!< PORT5 HWSEL: HW14 Mask */
\r
15819 #define PORT5_HWSEL_HW15_Pos 30 /*!< PORT5 HWSEL: HW15 Position */
\r
15820 #define PORT5_HWSEL_HW15_Msk (0x03UL << PORT5_HWSEL_HW15_Pos) /*!< PORT5 HWSEL: HW15 Mask */
\r
15823 /* ================================================================================ */
\r
15824 /* ================ struct 'PORT14' Position & Mask ================ */
\r
15825 /* ================================================================================ */
\r
15828 /* --------------------------------- PORT14_OUT --------------------------------- */
\r
15829 #define PORT14_OUT_P0_Pos 0 /*!< PORT14 OUT: P0 Position */
\r
15830 #define PORT14_OUT_P0_Msk (0x01UL << PORT14_OUT_P0_Pos) /*!< PORT14 OUT: P0 Mask */
\r
15831 #define PORT14_OUT_P1_Pos 1 /*!< PORT14 OUT: P1 Position */
\r
15832 #define PORT14_OUT_P1_Msk (0x01UL << PORT14_OUT_P1_Pos) /*!< PORT14 OUT: P1 Mask */
\r
15833 #define PORT14_OUT_P2_Pos 2 /*!< PORT14 OUT: P2 Position */
\r
15834 #define PORT14_OUT_P2_Msk (0x01UL << PORT14_OUT_P2_Pos) /*!< PORT14 OUT: P2 Mask */
\r
15835 #define PORT14_OUT_P3_Pos 3 /*!< PORT14 OUT: P3 Position */
\r
15836 #define PORT14_OUT_P3_Msk (0x01UL << PORT14_OUT_P3_Pos) /*!< PORT14 OUT: P3 Mask */
\r
15837 #define PORT14_OUT_P4_Pos 4 /*!< PORT14 OUT: P4 Position */
\r
15838 #define PORT14_OUT_P4_Msk (0x01UL << PORT14_OUT_P4_Pos) /*!< PORT14 OUT: P4 Mask */
\r
15839 #define PORT14_OUT_P5_Pos 5 /*!< PORT14 OUT: P5 Position */
\r
15840 #define PORT14_OUT_P5_Msk (0x01UL << PORT14_OUT_P5_Pos) /*!< PORT14 OUT: P5 Mask */
\r
15841 #define PORT14_OUT_P6_Pos 6 /*!< PORT14 OUT: P6 Position */
\r
15842 #define PORT14_OUT_P6_Msk (0x01UL << PORT14_OUT_P6_Pos) /*!< PORT14 OUT: P6 Mask */
\r
15843 #define PORT14_OUT_P7_Pos 7 /*!< PORT14 OUT: P7 Position */
\r
15844 #define PORT14_OUT_P7_Msk (0x01UL << PORT14_OUT_P7_Pos) /*!< PORT14 OUT: P7 Mask */
\r
15845 #define PORT14_OUT_P8_Pos 8 /*!< PORT14 OUT: P8 Position */
\r
15846 #define PORT14_OUT_P8_Msk (0x01UL << PORT14_OUT_P8_Pos) /*!< PORT14 OUT: P8 Mask */
\r
15847 #define PORT14_OUT_P9_Pos 9 /*!< PORT14 OUT: P9 Position */
\r
15848 #define PORT14_OUT_P9_Msk (0x01UL << PORT14_OUT_P9_Pos) /*!< PORT14 OUT: P9 Mask */
\r
15849 #define PORT14_OUT_P10_Pos 10 /*!< PORT14 OUT: P10 Position */
\r
15850 #define PORT14_OUT_P10_Msk (0x01UL << PORT14_OUT_P10_Pos) /*!< PORT14 OUT: P10 Mask */
\r
15851 #define PORT14_OUT_P11_Pos 11 /*!< PORT14 OUT: P11 Position */
\r
15852 #define PORT14_OUT_P11_Msk (0x01UL << PORT14_OUT_P11_Pos) /*!< PORT14 OUT: P11 Mask */
\r
15853 #define PORT14_OUT_P12_Pos 12 /*!< PORT14 OUT: P12 Position */
\r
15854 #define PORT14_OUT_P12_Msk (0x01UL << PORT14_OUT_P12_Pos) /*!< PORT14 OUT: P12 Mask */
\r
15855 #define PORT14_OUT_P13_Pos 13 /*!< PORT14 OUT: P13 Position */
\r
15856 #define PORT14_OUT_P13_Msk (0x01UL << PORT14_OUT_P13_Pos) /*!< PORT14 OUT: P13 Mask */
\r
15857 #define PORT14_OUT_P14_Pos 14 /*!< PORT14 OUT: P14 Position */
\r
15858 #define PORT14_OUT_P14_Msk (0x01UL << PORT14_OUT_P14_Pos) /*!< PORT14 OUT: P14 Mask */
\r
15859 #define PORT14_OUT_P15_Pos 15 /*!< PORT14 OUT: P15 Position */
\r
15860 #define PORT14_OUT_P15_Msk (0x01UL << PORT14_OUT_P15_Pos) /*!< PORT14 OUT: P15 Mask */
\r
15862 /* --------------------------------- PORT14_OMR --------------------------------- */
\r
15863 #define PORT14_OMR_PS0_Pos 0 /*!< PORT14 OMR: PS0 Position */
\r
15864 #define PORT14_OMR_PS0_Msk (0x01UL << PORT14_OMR_PS0_Pos) /*!< PORT14 OMR: PS0 Mask */
\r
15865 #define PORT14_OMR_PS1_Pos 1 /*!< PORT14 OMR: PS1 Position */
\r
15866 #define PORT14_OMR_PS1_Msk (0x01UL << PORT14_OMR_PS1_Pos) /*!< PORT14 OMR: PS1 Mask */
\r
15867 #define PORT14_OMR_PS2_Pos 2 /*!< PORT14 OMR: PS2 Position */
\r
15868 #define PORT14_OMR_PS2_Msk (0x01UL << PORT14_OMR_PS2_Pos) /*!< PORT14 OMR: PS2 Mask */
\r
15869 #define PORT14_OMR_PS3_Pos 3 /*!< PORT14 OMR: PS3 Position */
\r
15870 #define PORT14_OMR_PS3_Msk (0x01UL << PORT14_OMR_PS3_Pos) /*!< PORT14 OMR: PS3 Mask */
\r
15871 #define PORT14_OMR_PS4_Pos 4 /*!< PORT14 OMR: PS4 Position */
\r
15872 #define PORT14_OMR_PS4_Msk (0x01UL << PORT14_OMR_PS4_Pos) /*!< PORT14 OMR: PS4 Mask */
\r
15873 #define PORT14_OMR_PS5_Pos 5 /*!< PORT14 OMR: PS5 Position */
\r
15874 #define PORT14_OMR_PS5_Msk (0x01UL << PORT14_OMR_PS5_Pos) /*!< PORT14 OMR: PS5 Mask */
\r
15875 #define PORT14_OMR_PS6_Pos 6 /*!< PORT14 OMR: PS6 Position */
\r
15876 #define PORT14_OMR_PS6_Msk (0x01UL << PORT14_OMR_PS6_Pos) /*!< PORT14 OMR: PS6 Mask */
\r
15877 #define PORT14_OMR_PS7_Pos 7 /*!< PORT14 OMR: PS7 Position */
\r
15878 #define PORT14_OMR_PS7_Msk (0x01UL << PORT14_OMR_PS7_Pos) /*!< PORT14 OMR: PS7 Mask */
\r
15879 #define PORT14_OMR_PS8_Pos 8 /*!< PORT14 OMR: PS8 Position */
\r
15880 #define PORT14_OMR_PS8_Msk (0x01UL << PORT14_OMR_PS8_Pos) /*!< PORT14 OMR: PS8 Mask */
\r
15881 #define PORT14_OMR_PS9_Pos 9 /*!< PORT14 OMR: PS9 Position */
\r
15882 #define PORT14_OMR_PS9_Msk (0x01UL << PORT14_OMR_PS9_Pos) /*!< PORT14 OMR: PS9 Mask */
\r
15883 #define PORT14_OMR_PS10_Pos 10 /*!< PORT14 OMR: PS10 Position */
\r
15884 #define PORT14_OMR_PS10_Msk (0x01UL << PORT14_OMR_PS10_Pos) /*!< PORT14 OMR: PS10 Mask */
\r
15885 #define PORT14_OMR_PS11_Pos 11 /*!< PORT14 OMR: PS11 Position */
\r
15886 #define PORT14_OMR_PS11_Msk (0x01UL << PORT14_OMR_PS11_Pos) /*!< PORT14 OMR: PS11 Mask */
\r
15887 #define PORT14_OMR_PS12_Pos 12 /*!< PORT14 OMR: PS12 Position */
\r
15888 #define PORT14_OMR_PS12_Msk (0x01UL << PORT14_OMR_PS12_Pos) /*!< PORT14 OMR: PS12 Mask */
\r
15889 #define PORT14_OMR_PS13_Pos 13 /*!< PORT14 OMR: PS13 Position */
\r
15890 #define PORT14_OMR_PS13_Msk (0x01UL << PORT14_OMR_PS13_Pos) /*!< PORT14 OMR: PS13 Mask */
\r
15891 #define PORT14_OMR_PS14_Pos 14 /*!< PORT14 OMR: PS14 Position */
\r
15892 #define PORT14_OMR_PS14_Msk (0x01UL << PORT14_OMR_PS14_Pos) /*!< PORT14 OMR: PS14 Mask */
\r
15893 #define PORT14_OMR_PS15_Pos 15 /*!< PORT14 OMR: PS15 Position */
\r
15894 #define PORT14_OMR_PS15_Msk (0x01UL << PORT14_OMR_PS15_Pos) /*!< PORT14 OMR: PS15 Mask */
\r
15895 #define PORT14_OMR_PR0_Pos 16 /*!< PORT14 OMR: PR0 Position */
\r
15896 #define PORT14_OMR_PR0_Msk (0x01UL << PORT14_OMR_PR0_Pos) /*!< PORT14 OMR: PR0 Mask */
\r
15897 #define PORT14_OMR_PR1_Pos 17 /*!< PORT14 OMR: PR1 Position */
\r
15898 #define PORT14_OMR_PR1_Msk (0x01UL << PORT14_OMR_PR1_Pos) /*!< PORT14 OMR: PR1 Mask */
\r
15899 #define PORT14_OMR_PR2_Pos 18 /*!< PORT14 OMR: PR2 Position */
\r
15900 #define PORT14_OMR_PR2_Msk (0x01UL << PORT14_OMR_PR2_Pos) /*!< PORT14 OMR: PR2 Mask */
\r
15901 #define PORT14_OMR_PR3_Pos 19 /*!< PORT14 OMR: PR3 Position */
\r
15902 #define PORT14_OMR_PR3_Msk (0x01UL << PORT14_OMR_PR3_Pos) /*!< PORT14 OMR: PR3 Mask */
\r
15903 #define PORT14_OMR_PR4_Pos 20 /*!< PORT14 OMR: PR4 Position */
\r
15904 #define PORT14_OMR_PR4_Msk (0x01UL << PORT14_OMR_PR4_Pos) /*!< PORT14 OMR: PR4 Mask */
\r
15905 #define PORT14_OMR_PR5_Pos 21 /*!< PORT14 OMR: PR5 Position */
\r
15906 #define PORT14_OMR_PR5_Msk (0x01UL << PORT14_OMR_PR5_Pos) /*!< PORT14 OMR: PR5 Mask */
\r
15907 #define PORT14_OMR_PR6_Pos 22 /*!< PORT14 OMR: PR6 Position */
\r
15908 #define PORT14_OMR_PR6_Msk (0x01UL << PORT14_OMR_PR6_Pos) /*!< PORT14 OMR: PR6 Mask */
\r
15909 #define PORT14_OMR_PR7_Pos 23 /*!< PORT14 OMR: PR7 Position */
\r
15910 #define PORT14_OMR_PR7_Msk (0x01UL << PORT14_OMR_PR7_Pos) /*!< PORT14 OMR: PR7 Mask */
\r
15911 #define PORT14_OMR_PR8_Pos 24 /*!< PORT14 OMR: PR8 Position */
\r
15912 #define PORT14_OMR_PR8_Msk (0x01UL << PORT14_OMR_PR8_Pos) /*!< PORT14 OMR: PR8 Mask */
\r
15913 #define PORT14_OMR_PR9_Pos 25 /*!< PORT14 OMR: PR9 Position */
\r
15914 #define PORT14_OMR_PR9_Msk (0x01UL << PORT14_OMR_PR9_Pos) /*!< PORT14 OMR: PR9 Mask */
\r
15915 #define PORT14_OMR_PR10_Pos 26 /*!< PORT14 OMR: PR10 Position */
\r
15916 #define PORT14_OMR_PR10_Msk (0x01UL << PORT14_OMR_PR10_Pos) /*!< PORT14 OMR: PR10 Mask */
\r
15917 #define PORT14_OMR_PR11_Pos 27 /*!< PORT14 OMR: PR11 Position */
\r
15918 #define PORT14_OMR_PR11_Msk (0x01UL << PORT14_OMR_PR11_Pos) /*!< PORT14 OMR: PR11 Mask */
\r
15919 #define PORT14_OMR_PR12_Pos 28 /*!< PORT14 OMR: PR12 Position */
\r
15920 #define PORT14_OMR_PR12_Msk (0x01UL << PORT14_OMR_PR12_Pos) /*!< PORT14 OMR: PR12 Mask */
\r
15921 #define PORT14_OMR_PR13_Pos 29 /*!< PORT14 OMR: PR13 Position */
\r
15922 #define PORT14_OMR_PR13_Msk (0x01UL << PORT14_OMR_PR13_Pos) /*!< PORT14 OMR: PR13 Mask */
\r
15923 #define PORT14_OMR_PR14_Pos 30 /*!< PORT14 OMR: PR14 Position */
\r
15924 #define PORT14_OMR_PR14_Msk (0x01UL << PORT14_OMR_PR14_Pos) /*!< PORT14 OMR: PR14 Mask */
\r
15925 #define PORT14_OMR_PR15_Pos 31 /*!< PORT14 OMR: PR15 Position */
\r
15926 #define PORT14_OMR_PR15_Msk (0x01UL << PORT14_OMR_PR15_Pos) /*!< PORT14 OMR: PR15 Mask */
\r
15928 /* -------------------------------- PORT14_IOCR0 -------------------------------- */
\r
15929 #define PORT14_IOCR0_PC0_Pos 3 /*!< PORT14 IOCR0: PC0 Position */
\r
15930 #define PORT14_IOCR0_PC0_Msk (0x1fUL << PORT14_IOCR0_PC0_Pos) /*!< PORT14 IOCR0: PC0 Mask */
\r
15931 #define PORT14_IOCR0_PC1_Pos 11 /*!< PORT14 IOCR0: PC1 Position */
\r
15932 #define PORT14_IOCR0_PC1_Msk (0x1fUL << PORT14_IOCR0_PC1_Pos) /*!< PORT14 IOCR0: PC1 Mask */
\r
15933 #define PORT14_IOCR0_PC2_Pos 19 /*!< PORT14 IOCR0: PC2 Position */
\r
15934 #define PORT14_IOCR0_PC2_Msk (0x1fUL << PORT14_IOCR0_PC2_Pos) /*!< PORT14 IOCR0: PC2 Mask */
\r
15935 #define PORT14_IOCR0_PC3_Pos 27 /*!< PORT14 IOCR0: PC3 Position */
\r
15936 #define PORT14_IOCR0_PC3_Msk (0x1fUL << PORT14_IOCR0_PC3_Pos) /*!< PORT14 IOCR0: PC3 Mask */
\r
15938 /* -------------------------------- PORT14_IOCR4 -------------------------------- */
\r
15939 #define PORT14_IOCR4_PC4_Pos 3 /*!< PORT14 IOCR4: PC4 Position */
\r
15940 #define PORT14_IOCR4_PC4_Msk (0x1fUL << PORT14_IOCR4_PC4_Pos) /*!< PORT14 IOCR4: PC4 Mask */
\r
15941 #define PORT14_IOCR4_PC5_Pos 11 /*!< PORT14 IOCR4: PC5 Position */
\r
15942 #define PORT14_IOCR4_PC5_Msk (0x1fUL << PORT14_IOCR4_PC5_Pos) /*!< PORT14 IOCR4: PC5 Mask */
\r
15943 #define PORT14_IOCR4_PC6_Pos 19 /*!< PORT14 IOCR4: PC6 Position */
\r
15944 #define PORT14_IOCR4_PC6_Msk (0x1fUL << PORT14_IOCR4_PC6_Pos) /*!< PORT14 IOCR4: PC6 Mask */
\r
15945 #define PORT14_IOCR4_PC7_Pos 27 /*!< PORT14 IOCR4: PC7 Position */
\r
15946 #define PORT14_IOCR4_PC7_Msk (0x1fUL << PORT14_IOCR4_PC7_Pos) /*!< PORT14 IOCR4: PC7 Mask */
\r
15948 /* -------------------------------- PORT14_IOCR8 -------------------------------- */
\r
15949 #define PORT14_IOCR8_PC8_Pos 3 /*!< PORT14 IOCR8: PC8 Position */
\r
15950 #define PORT14_IOCR8_PC8_Msk (0x1fUL << PORT14_IOCR8_PC8_Pos) /*!< PORT14 IOCR8: PC8 Mask */
\r
15951 #define PORT14_IOCR8_PC9_Pos 11 /*!< PORT14 IOCR8: PC9 Position */
\r
15952 #define PORT14_IOCR8_PC9_Msk (0x1fUL << PORT14_IOCR8_PC9_Pos) /*!< PORT14 IOCR8: PC9 Mask */
\r
15953 #define PORT14_IOCR8_PC10_Pos 19 /*!< PORT14 IOCR8: PC10 Position */
\r
15954 #define PORT14_IOCR8_PC10_Msk (0x1fUL << PORT14_IOCR8_PC10_Pos) /*!< PORT14 IOCR8: PC10 Mask */
\r
15955 #define PORT14_IOCR8_PC11_Pos 27 /*!< PORT14 IOCR8: PC11 Position */
\r
15956 #define PORT14_IOCR8_PC11_Msk (0x1fUL << PORT14_IOCR8_PC11_Pos) /*!< PORT14 IOCR8: PC11 Mask */
\r
15958 /* -------------------------------- PORT14_IOCR12 ------------------------------- */
\r
15959 #define PORT14_IOCR12_PC12_Pos 3 /*!< PORT14 IOCR12: PC12 Position */
\r
15960 #define PORT14_IOCR12_PC12_Msk (0x1fUL << PORT14_IOCR12_PC12_Pos) /*!< PORT14 IOCR12: PC12 Mask */
\r
15961 #define PORT14_IOCR12_PC13_Pos 11 /*!< PORT14 IOCR12: PC13 Position */
\r
15962 #define PORT14_IOCR12_PC13_Msk (0x1fUL << PORT14_IOCR12_PC13_Pos) /*!< PORT14 IOCR12: PC13 Mask */
\r
15963 #define PORT14_IOCR12_PC14_Pos 19 /*!< PORT14 IOCR12: PC14 Position */
\r
15964 #define PORT14_IOCR12_PC14_Msk (0x1fUL << PORT14_IOCR12_PC14_Pos) /*!< PORT14 IOCR12: PC14 Mask */
\r
15965 #define PORT14_IOCR12_PC15_Pos 27 /*!< PORT14 IOCR12: PC15 Position */
\r
15966 #define PORT14_IOCR12_PC15_Msk (0x1fUL << PORT14_IOCR12_PC15_Pos) /*!< PORT14 IOCR12: PC15 Mask */
\r
15968 /* ---------------------------------- PORT14_IN --------------------------------- */
\r
15969 #define PORT14_IN_P0_Pos 0 /*!< PORT14 IN: P0 Position */
\r
15970 #define PORT14_IN_P0_Msk (0x01UL << PORT14_IN_P0_Pos) /*!< PORT14 IN: P0 Mask */
\r
15971 #define PORT14_IN_P1_Pos 1 /*!< PORT14 IN: P1 Position */
\r
15972 #define PORT14_IN_P1_Msk (0x01UL << PORT14_IN_P1_Pos) /*!< PORT14 IN: P1 Mask */
\r
15973 #define PORT14_IN_P2_Pos 2 /*!< PORT14 IN: P2 Position */
\r
15974 #define PORT14_IN_P2_Msk (0x01UL << PORT14_IN_P2_Pos) /*!< PORT14 IN: P2 Mask */
\r
15975 #define PORT14_IN_P3_Pos 3 /*!< PORT14 IN: P3 Position */
\r
15976 #define PORT14_IN_P3_Msk (0x01UL << PORT14_IN_P3_Pos) /*!< PORT14 IN: P3 Mask */
\r
15977 #define PORT14_IN_P4_Pos 4 /*!< PORT14 IN: P4 Position */
\r
15978 #define PORT14_IN_P4_Msk (0x01UL << PORT14_IN_P4_Pos) /*!< PORT14 IN: P4 Mask */
\r
15979 #define PORT14_IN_P5_Pos 5 /*!< PORT14 IN: P5 Position */
\r
15980 #define PORT14_IN_P5_Msk (0x01UL << PORT14_IN_P5_Pos) /*!< PORT14 IN: P5 Mask */
\r
15981 #define PORT14_IN_P6_Pos 6 /*!< PORT14 IN: P6 Position */
\r
15982 #define PORT14_IN_P6_Msk (0x01UL << PORT14_IN_P6_Pos) /*!< PORT14 IN: P6 Mask */
\r
15983 #define PORT14_IN_P7_Pos 7 /*!< PORT14 IN: P7 Position */
\r
15984 #define PORT14_IN_P7_Msk (0x01UL << PORT14_IN_P7_Pos) /*!< PORT14 IN: P7 Mask */
\r
15985 #define PORT14_IN_P8_Pos 8 /*!< PORT14 IN: P8 Position */
\r
15986 #define PORT14_IN_P8_Msk (0x01UL << PORT14_IN_P8_Pos) /*!< PORT14 IN: P8 Mask */
\r
15987 #define PORT14_IN_P9_Pos 9 /*!< PORT14 IN: P9 Position */
\r
15988 #define PORT14_IN_P9_Msk (0x01UL << PORT14_IN_P9_Pos) /*!< PORT14 IN: P9 Mask */
\r
15989 #define PORT14_IN_P10_Pos 10 /*!< PORT14 IN: P10 Position */
\r
15990 #define PORT14_IN_P10_Msk (0x01UL << PORT14_IN_P10_Pos) /*!< PORT14 IN: P10 Mask */
\r
15991 #define PORT14_IN_P11_Pos 11 /*!< PORT14 IN: P11 Position */
\r
15992 #define PORT14_IN_P11_Msk (0x01UL << PORT14_IN_P11_Pos) /*!< PORT14 IN: P11 Mask */
\r
15993 #define PORT14_IN_P12_Pos 12 /*!< PORT14 IN: P12 Position */
\r
15994 #define PORT14_IN_P12_Msk (0x01UL << PORT14_IN_P12_Pos) /*!< PORT14 IN: P12 Mask */
\r
15995 #define PORT14_IN_P13_Pos 13 /*!< PORT14 IN: P13 Position */
\r
15996 #define PORT14_IN_P13_Msk (0x01UL << PORT14_IN_P13_Pos) /*!< PORT14 IN: P13 Mask */
\r
15997 #define PORT14_IN_P14_Pos 14 /*!< PORT14 IN: P14 Position */
\r
15998 #define PORT14_IN_P14_Msk (0x01UL << PORT14_IN_P14_Pos) /*!< PORT14 IN: P14 Mask */
\r
15999 #define PORT14_IN_P15_Pos 15 /*!< PORT14 IN: P15 Position */
\r
16000 #define PORT14_IN_P15_Msk (0x01UL << PORT14_IN_P15_Pos) /*!< PORT14 IN: P15 Mask */
\r
16002 /* -------------------------------- PORT14_PDISC -------------------------------- */
\r
16003 #define PORT14_PDISC_PDIS0_Pos 0 /*!< PORT14 PDISC: PDIS0 Position */
\r
16004 #define PORT14_PDISC_PDIS0_Msk (0x01UL << PORT14_PDISC_PDIS0_Pos) /*!< PORT14 PDISC: PDIS0 Mask */
\r
16005 #define PORT14_PDISC_PDIS1_Pos 1 /*!< PORT14 PDISC: PDIS1 Position */
\r
16006 #define PORT14_PDISC_PDIS1_Msk (0x01UL << PORT14_PDISC_PDIS1_Pos) /*!< PORT14 PDISC: PDIS1 Mask */
\r
16007 #define PORT14_PDISC_PDIS2_Pos 2 /*!< PORT14 PDISC: PDIS2 Position */
\r
16008 #define PORT14_PDISC_PDIS2_Msk (0x01UL << PORT14_PDISC_PDIS2_Pos) /*!< PORT14 PDISC: PDIS2 Mask */
\r
16009 #define PORT14_PDISC_PDIS3_Pos 3 /*!< PORT14 PDISC: PDIS3 Position */
\r
16010 #define PORT14_PDISC_PDIS3_Msk (0x01UL << PORT14_PDISC_PDIS3_Pos) /*!< PORT14 PDISC: PDIS3 Mask */
\r
16011 #define PORT14_PDISC_PDIS4_Pos 4 /*!< PORT14 PDISC: PDIS4 Position */
\r
16012 #define PORT14_PDISC_PDIS4_Msk (0x01UL << PORT14_PDISC_PDIS4_Pos) /*!< PORT14 PDISC: PDIS4 Mask */
\r
16013 #define PORT14_PDISC_PDIS5_Pos 5 /*!< PORT14 PDISC: PDIS5 Position */
\r
16014 #define PORT14_PDISC_PDIS5_Msk (0x01UL << PORT14_PDISC_PDIS5_Pos) /*!< PORT14 PDISC: PDIS5 Mask */
\r
16015 #define PORT14_PDISC_PDIS6_Pos 6 /*!< PORT14 PDISC: PDIS6 Position */
\r
16016 #define PORT14_PDISC_PDIS6_Msk (0x01UL << PORT14_PDISC_PDIS6_Pos) /*!< PORT14 PDISC: PDIS6 Mask */
\r
16017 #define PORT14_PDISC_PDIS7_Pos 7 /*!< PORT14 PDISC: PDIS7 Position */
\r
16018 #define PORT14_PDISC_PDIS7_Msk (0x01UL << PORT14_PDISC_PDIS7_Pos) /*!< PORT14 PDISC: PDIS7 Mask */
\r
16019 #define PORT14_PDISC_PDIS8_Pos 8 /*!< PORT14 PDISC: PDIS8 Position */
\r
16020 #define PORT14_PDISC_PDIS8_Msk (0x01UL << PORT14_PDISC_PDIS8_Pos) /*!< PORT14 PDISC: PDIS8 Mask */
\r
16021 #define PORT14_PDISC_PDIS9_Pos 9 /*!< PORT14 PDISC: PDIS9 Position */
\r
16022 #define PORT14_PDISC_PDIS9_Msk (0x01UL << PORT14_PDISC_PDIS9_Pos) /*!< PORT14 PDISC: PDIS9 Mask */
\r
16023 #define PORT14_PDISC_PDIS10_Pos 10 /*!< PORT14 PDISC: PDIS10 Position */
\r
16024 #define PORT14_PDISC_PDIS10_Msk (0x01UL << PORT14_PDISC_PDIS10_Pos) /*!< PORT14 PDISC: PDIS10 Mask */
\r
16025 #define PORT14_PDISC_PDIS11_Pos 11 /*!< PORT14 PDISC: PDIS11 Position */
\r
16026 #define PORT14_PDISC_PDIS11_Msk (0x01UL << PORT14_PDISC_PDIS11_Pos) /*!< PORT14 PDISC: PDIS11 Mask */
\r
16027 #define PORT14_PDISC_PDIS12_Pos 12 /*!< PORT14 PDISC: PDIS12 Position */
\r
16028 #define PORT14_PDISC_PDIS12_Msk (0x01UL << PORT14_PDISC_PDIS12_Pos) /*!< PORT14 PDISC: PDIS12 Mask */
\r
16029 #define PORT14_PDISC_PDIS13_Pos 13 /*!< PORT14 PDISC: PDIS13 Position */
\r
16030 #define PORT14_PDISC_PDIS13_Msk (0x01UL << PORT14_PDISC_PDIS13_Pos) /*!< PORT14 PDISC: PDIS13 Mask */
\r
16031 #define PORT14_PDISC_PDIS14_Pos 14 /*!< PORT14 PDISC: PDIS14 Position */
\r
16032 #define PORT14_PDISC_PDIS14_Msk (0x01UL << PORT14_PDISC_PDIS14_Pos) /*!< PORT14 PDISC: PDIS14 Mask */
\r
16033 #define PORT14_PDISC_PDIS15_Pos 15 /*!< PORT14 PDISC: PDIS15 Position */
\r
16034 #define PORT14_PDISC_PDIS15_Msk (0x01UL << PORT14_PDISC_PDIS15_Pos) /*!< PORT14 PDISC: PDIS15 Mask */
\r
16036 /* --------------------------------- PORT14_PPS --------------------------------- */
\r
16037 #define PORT14_PPS_PPS0_Pos 0 /*!< PORT14 PPS: PPS0 Position */
\r
16038 #define PORT14_PPS_PPS0_Msk (0x01UL << PORT14_PPS_PPS0_Pos) /*!< PORT14 PPS: PPS0 Mask */
\r
16039 #define PORT14_PPS_PPS1_Pos 1 /*!< PORT14 PPS: PPS1 Position */
\r
16040 #define PORT14_PPS_PPS1_Msk (0x01UL << PORT14_PPS_PPS1_Pos) /*!< PORT14 PPS: PPS1 Mask */
\r
16041 #define PORT14_PPS_PPS2_Pos 2 /*!< PORT14 PPS: PPS2 Position */
\r
16042 #define PORT14_PPS_PPS2_Msk (0x01UL << PORT14_PPS_PPS2_Pos) /*!< PORT14 PPS: PPS2 Mask */
\r
16043 #define PORT14_PPS_PPS3_Pos 3 /*!< PORT14 PPS: PPS3 Position */
\r
16044 #define PORT14_PPS_PPS3_Msk (0x01UL << PORT14_PPS_PPS3_Pos) /*!< PORT14 PPS: PPS3 Mask */
\r
16045 #define PORT14_PPS_PPS4_Pos 4 /*!< PORT14 PPS: PPS4 Position */
\r
16046 #define PORT14_PPS_PPS4_Msk (0x01UL << PORT14_PPS_PPS4_Pos) /*!< PORT14 PPS: PPS4 Mask */
\r
16047 #define PORT14_PPS_PPS5_Pos 5 /*!< PORT14 PPS: PPS5 Position */
\r
16048 #define PORT14_PPS_PPS5_Msk (0x01UL << PORT14_PPS_PPS5_Pos) /*!< PORT14 PPS: PPS5 Mask */
\r
16049 #define PORT14_PPS_PPS6_Pos 6 /*!< PORT14 PPS: PPS6 Position */
\r
16050 #define PORT14_PPS_PPS6_Msk (0x01UL << PORT14_PPS_PPS6_Pos) /*!< PORT14 PPS: PPS6 Mask */
\r
16051 #define PORT14_PPS_PPS7_Pos 7 /*!< PORT14 PPS: PPS7 Position */
\r
16052 #define PORT14_PPS_PPS7_Msk (0x01UL << PORT14_PPS_PPS7_Pos) /*!< PORT14 PPS: PPS7 Mask */
\r
16053 #define PORT14_PPS_PPS8_Pos 8 /*!< PORT14 PPS: PPS8 Position */
\r
16054 #define PORT14_PPS_PPS8_Msk (0x01UL << PORT14_PPS_PPS8_Pos) /*!< PORT14 PPS: PPS8 Mask */
\r
16055 #define PORT14_PPS_PPS9_Pos 9 /*!< PORT14 PPS: PPS9 Position */
\r
16056 #define PORT14_PPS_PPS9_Msk (0x01UL << PORT14_PPS_PPS9_Pos) /*!< PORT14 PPS: PPS9 Mask */
\r
16057 #define PORT14_PPS_PPS10_Pos 10 /*!< PORT14 PPS: PPS10 Position */
\r
16058 #define PORT14_PPS_PPS10_Msk (0x01UL << PORT14_PPS_PPS10_Pos) /*!< PORT14 PPS: PPS10 Mask */
\r
16059 #define PORT14_PPS_PPS11_Pos 11 /*!< PORT14 PPS: PPS11 Position */
\r
16060 #define PORT14_PPS_PPS11_Msk (0x01UL << PORT14_PPS_PPS11_Pos) /*!< PORT14 PPS: PPS11 Mask */
\r
16061 #define PORT14_PPS_PPS12_Pos 12 /*!< PORT14 PPS: PPS12 Position */
\r
16062 #define PORT14_PPS_PPS12_Msk (0x01UL << PORT14_PPS_PPS12_Pos) /*!< PORT14 PPS: PPS12 Mask */
\r
16063 #define PORT14_PPS_PPS13_Pos 13 /*!< PORT14 PPS: PPS13 Position */
\r
16064 #define PORT14_PPS_PPS13_Msk (0x01UL << PORT14_PPS_PPS13_Pos) /*!< PORT14 PPS: PPS13 Mask */
\r
16065 #define PORT14_PPS_PPS14_Pos 14 /*!< PORT14 PPS: PPS14 Position */
\r
16066 #define PORT14_PPS_PPS14_Msk (0x01UL << PORT14_PPS_PPS14_Pos) /*!< PORT14 PPS: PPS14 Mask */
\r
16067 #define PORT14_PPS_PPS15_Pos 15 /*!< PORT14 PPS: PPS15 Position */
\r
16068 #define PORT14_PPS_PPS15_Msk (0x01UL << PORT14_PPS_PPS15_Pos) /*!< PORT14 PPS: PPS15 Mask */
\r
16070 /* -------------------------------- PORT14_HWSEL -------------------------------- */
\r
16071 #define PORT14_HWSEL_HW0_Pos 0 /*!< PORT14 HWSEL: HW0 Position */
\r
16072 #define PORT14_HWSEL_HW0_Msk (0x03UL << PORT14_HWSEL_HW0_Pos) /*!< PORT14 HWSEL: HW0 Mask */
\r
16073 #define PORT14_HWSEL_HW1_Pos 2 /*!< PORT14 HWSEL: HW1 Position */
\r
16074 #define PORT14_HWSEL_HW1_Msk (0x03UL << PORT14_HWSEL_HW1_Pos) /*!< PORT14 HWSEL: HW1 Mask */
\r
16075 #define PORT14_HWSEL_HW2_Pos 4 /*!< PORT14 HWSEL: HW2 Position */
\r
16076 #define PORT14_HWSEL_HW2_Msk (0x03UL << PORT14_HWSEL_HW2_Pos) /*!< PORT14 HWSEL: HW2 Mask */
\r
16077 #define PORT14_HWSEL_HW3_Pos 6 /*!< PORT14 HWSEL: HW3 Position */
\r
16078 #define PORT14_HWSEL_HW3_Msk (0x03UL << PORT14_HWSEL_HW3_Pos) /*!< PORT14 HWSEL: HW3 Mask */
\r
16079 #define PORT14_HWSEL_HW4_Pos 8 /*!< PORT14 HWSEL: HW4 Position */
\r
16080 #define PORT14_HWSEL_HW4_Msk (0x03UL << PORT14_HWSEL_HW4_Pos) /*!< PORT14 HWSEL: HW4 Mask */
\r
16081 #define PORT14_HWSEL_HW5_Pos 10 /*!< PORT14 HWSEL: HW5 Position */
\r
16082 #define PORT14_HWSEL_HW5_Msk (0x03UL << PORT14_HWSEL_HW5_Pos) /*!< PORT14 HWSEL: HW5 Mask */
\r
16083 #define PORT14_HWSEL_HW6_Pos 12 /*!< PORT14 HWSEL: HW6 Position */
\r
16084 #define PORT14_HWSEL_HW6_Msk (0x03UL << PORT14_HWSEL_HW6_Pos) /*!< PORT14 HWSEL: HW6 Mask */
\r
16085 #define PORT14_HWSEL_HW7_Pos 14 /*!< PORT14 HWSEL: HW7 Position */
\r
16086 #define PORT14_HWSEL_HW7_Msk (0x03UL << PORT14_HWSEL_HW7_Pos) /*!< PORT14 HWSEL: HW7 Mask */
\r
16087 #define PORT14_HWSEL_HW8_Pos 16 /*!< PORT14 HWSEL: HW8 Position */
\r
16088 #define PORT14_HWSEL_HW8_Msk (0x03UL << PORT14_HWSEL_HW8_Pos) /*!< PORT14 HWSEL: HW8 Mask */
\r
16089 #define PORT14_HWSEL_HW9_Pos 18 /*!< PORT14 HWSEL: HW9 Position */
\r
16090 #define PORT14_HWSEL_HW9_Msk (0x03UL << PORT14_HWSEL_HW9_Pos) /*!< PORT14 HWSEL: HW9 Mask */
\r
16091 #define PORT14_HWSEL_HW10_Pos 20 /*!< PORT14 HWSEL: HW10 Position */
\r
16092 #define PORT14_HWSEL_HW10_Msk (0x03UL << PORT14_HWSEL_HW10_Pos) /*!< PORT14 HWSEL: HW10 Mask */
\r
16093 #define PORT14_HWSEL_HW11_Pos 22 /*!< PORT14 HWSEL: HW11 Position */
\r
16094 #define PORT14_HWSEL_HW11_Msk (0x03UL << PORT14_HWSEL_HW11_Pos) /*!< PORT14 HWSEL: HW11 Mask */
\r
16095 #define PORT14_HWSEL_HW12_Pos 24 /*!< PORT14 HWSEL: HW12 Position */
\r
16096 #define PORT14_HWSEL_HW12_Msk (0x03UL << PORT14_HWSEL_HW12_Pos) /*!< PORT14 HWSEL: HW12 Mask */
\r
16097 #define PORT14_HWSEL_HW13_Pos 26 /*!< PORT14 HWSEL: HW13 Position */
\r
16098 #define PORT14_HWSEL_HW13_Msk (0x03UL << PORT14_HWSEL_HW13_Pos) /*!< PORT14 HWSEL: HW13 Mask */
\r
16099 #define PORT14_HWSEL_HW14_Pos 28 /*!< PORT14 HWSEL: HW14 Position */
\r
16100 #define PORT14_HWSEL_HW14_Msk (0x03UL << PORT14_HWSEL_HW14_Pos) /*!< PORT14 HWSEL: HW14 Mask */
\r
16101 #define PORT14_HWSEL_HW15_Pos 30 /*!< PORT14 HWSEL: HW15 Position */
\r
16102 #define PORT14_HWSEL_HW15_Msk (0x03UL << PORT14_HWSEL_HW15_Pos) /*!< PORT14 HWSEL: HW15 Mask */
\r
16105 /* ================================================================================ */
\r
16106 /* ================ struct 'PORT15' Position & Mask ================ */
\r
16107 /* ================================================================================ */
\r
16110 /* --------------------------------- PORT15_OUT --------------------------------- */
\r
16111 #define PORT15_OUT_P0_Pos 0 /*!< PORT15 OUT: P0 Position */
\r
16112 #define PORT15_OUT_P0_Msk (0x01UL << PORT15_OUT_P0_Pos) /*!< PORT15 OUT: P0 Mask */
\r
16113 #define PORT15_OUT_P1_Pos 1 /*!< PORT15 OUT: P1 Position */
\r
16114 #define PORT15_OUT_P1_Msk (0x01UL << PORT15_OUT_P1_Pos) /*!< PORT15 OUT: P1 Mask */
\r
16115 #define PORT15_OUT_P2_Pos 2 /*!< PORT15 OUT: P2 Position */
\r
16116 #define PORT15_OUT_P2_Msk (0x01UL << PORT15_OUT_P2_Pos) /*!< PORT15 OUT: P2 Mask */
\r
16117 #define PORT15_OUT_P3_Pos 3 /*!< PORT15 OUT: P3 Position */
\r
16118 #define PORT15_OUT_P3_Msk (0x01UL << PORT15_OUT_P3_Pos) /*!< PORT15 OUT: P3 Mask */
\r
16119 #define PORT15_OUT_P4_Pos 4 /*!< PORT15 OUT: P4 Position */
\r
16120 #define PORT15_OUT_P4_Msk (0x01UL << PORT15_OUT_P4_Pos) /*!< PORT15 OUT: P4 Mask */
\r
16121 #define PORT15_OUT_P5_Pos 5 /*!< PORT15 OUT: P5 Position */
\r
16122 #define PORT15_OUT_P5_Msk (0x01UL << PORT15_OUT_P5_Pos) /*!< PORT15 OUT: P5 Mask */
\r
16123 #define PORT15_OUT_P6_Pos 6 /*!< PORT15 OUT: P6 Position */
\r
16124 #define PORT15_OUT_P6_Msk (0x01UL << PORT15_OUT_P6_Pos) /*!< PORT15 OUT: P6 Mask */
\r
16125 #define PORT15_OUT_P7_Pos 7 /*!< PORT15 OUT: P7 Position */
\r
16126 #define PORT15_OUT_P7_Msk (0x01UL << PORT15_OUT_P7_Pos) /*!< PORT15 OUT: P7 Mask */
\r
16127 #define PORT15_OUT_P8_Pos 8 /*!< PORT15 OUT: P8 Position */
\r
16128 #define PORT15_OUT_P8_Msk (0x01UL << PORT15_OUT_P8_Pos) /*!< PORT15 OUT: P8 Mask */
\r
16129 #define PORT15_OUT_P9_Pos 9 /*!< PORT15 OUT: P9 Position */
\r
16130 #define PORT15_OUT_P9_Msk (0x01UL << PORT15_OUT_P9_Pos) /*!< PORT15 OUT: P9 Mask */
\r
16131 #define PORT15_OUT_P10_Pos 10 /*!< PORT15 OUT: P10 Position */
\r
16132 #define PORT15_OUT_P10_Msk (0x01UL << PORT15_OUT_P10_Pos) /*!< PORT15 OUT: P10 Mask */
\r
16133 #define PORT15_OUT_P11_Pos 11 /*!< PORT15 OUT: P11 Position */
\r
16134 #define PORT15_OUT_P11_Msk (0x01UL << PORT15_OUT_P11_Pos) /*!< PORT15 OUT: P11 Mask */
\r
16135 #define PORT15_OUT_P12_Pos 12 /*!< PORT15 OUT: P12 Position */
\r
16136 #define PORT15_OUT_P12_Msk (0x01UL << PORT15_OUT_P12_Pos) /*!< PORT15 OUT: P12 Mask */
\r
16137 #define PORT15_OUT_P13_Pos 13 /*!< PORT15 OUT: P13 Position */
\r
16138 #define PORT15_OUT_P13_Msk (0x01UL << PORT15_OUT_P13_Pos) /*!< PORT15 OUT: P13 Mask */
\r
16139 #define PORT15_OUT_P14_Pos 14 /*!< PORT15 OUT: P14 Position */
\r
16140 #define PORT15_OUT_P14_Msk (0x01UL << PORT15_OUT_P14_Pos) /*!< PORT15 OUT: P14 Mask */
\r
16141 #define PORT15_OUT_P15_Pos 15 /*!< PORT15 OUT: P15 Position */
\r
16142 #define PORT15_OUT_P15_Msk (0x01UL << PORT15_OUT_P15_Pos) /*!< PORT15 OUT: P15 Mask */
\r
16144 /* --------------------------------- PORT15_OMR --------------------------------- */
\r
16145 #define PORT15_OMR_PS0_Pos 0 /*!< PORT15 OMR: PS0 Position */
\r
16146 #define PORT15_OMR_PS0_Msk (0x01UL << PORT15_OMR_PS0_Pos) /*!< PORT15 OMR: PS0 Mask */
\r
16147 #define PORT15_OMR_PS1_Pos 1 /*!< PORT15 OMR: PS1 Position */
\r
16148 #define PORT15_OMR_PS1_Msk (0x01UL << PORT15_OMR_PS1_Pos) /*!< PORT15 OMR: PS1 Mask */
\r
16149 #define PORT15_OMR_PS2_Pos 2 /*!< PORT15 OMR: PS2 Position */
\r
16150 #define PORT15_OMR_PS2_Msk (0x01UL << PORT15_OMR_PS2_Pos) /*!< PORT15 OMR: PS2 Mask */
\r
16151 #define PORT15_OMR_PS3_Pos 3 /*!< PORT15 OMR: PS3 Position */
\r
16152 #define PORT15_OMR_PS3_Msk (0x01UL << PORT15_OMR_PS3_Pos) /*!< PORT15 OMR: PS3 Mask */
\r
16153 #define PORT15_OMR_PS4_Pos 4 /*!< PORT15 OMR: PS4 Position */
\r
16154 #define PORT15_OMR_PS4_Msk (0x01UL << PORT15_OMR_PS4_Pos) /*!< PORT15 OMR: PS4 Mask */
\r
16155 #define PORT15_OMR_PS5_Pos 5 /*!< PORT15 OMR: PS5 Position */
\r
16156 #define PORT15_OMR_PS5_Msk (0x01UL << PORT15_OMR_PS5_Pos) /*!< PORT15 OMR: PS5 Mask */
\r
16157 #define PORT15_OMR_PS6_Pos 6 /*!< PORT15 OMR: PS6 Position */
\r
16158 #define PORT15_OMR_PS6_Msk (0x01UL << PORT15_OMR_PS6_Pos) /*!< PORT15 OMR: PS6 Mask */
\r
16159 #define PORT15_OMR_PS7_Pos 7 /*!< PORT15 OMR: PS7 Position */
\r
16160 #define PORT15_OMR_PS7_Msk (0x01UL << PORT15_OMR_PS7_Pos) /*!< PORT15 OMR: PS7 Mask */
\r
16161 #define PORT15_OMR_PS8_Pos 8 /*!< PORT15 OMR: PS8 Position */
\r
16162 #define PORT15_OMR_PS8_Msk (0x01UL << PORT15_OMR_PS8_Pos) /*!< PORT15 OMR: PS8 Mask */
\r
16163 #define PORT15_OMR_PS9_Pos 9 /*!< PORT15 OMR: PS9 Position */
\r
16164 #define PORT15_OMR_PS9_Msk (0x01UL << PORT15_OMR_PS9_Pos) /*!< PORT15 OMR: PS9 Mask */
\r
16165 #define PORT15_OMR_PS10_Pos 10 /*!< PORT15 OMR: PS10 Position */
\r
16166 #define PORT15_OMR_PS10_Msk (0x01UL << PORT15_OMR_PS10_Pos) /*!< PORT15 OMR: PS10 Mask */
\r
16167 #define PORT15_OMR_PS11_Pos 11 /*!< PORT15 OMR: PS11 Position */
\r
16168 #define PORT15_OMR_PS11_Msk (0x01UL << PORT15_OMR_PS11_Pos) /*!< PORT15 OMR: PS11 Mask */
\r
16169 #define PORT15_OMR_PS12_Pos 12 /*!< PORT15 OMR: PS12 Position */
\r
16170 #define PORT15_OMR_PS12_Msk (0x01UL << PORT15_OMR_PS12_Pos) /*!< PORT15 OMR: PS12 Mask */
\r
16171 #define PORT15_OMR_PS13_Pos 13 /*!< PORT15 OMR: PS13 Position */
\r
16172 #define PORT15_OMR_PS13_Msk (0x01UL << PORT15_OMR_PS13_Pos) /*!< PORT15 OMR: PS13 Mask */
\r
16173 #define PORT15_OMR_PS14_Pos 14 /*!< PORT15 OMR: PS14 Position */
\r
16174 #define PORT15_OMR_PS14_Msk (0x01UL << PORT15_OMR_PS14_Pos) /*!< PORT15 OMR: PS14 Mask */
\r
16175 #define PORT15_OMR_PS15_Pos 15 /*!< PORT15 OMR: PS15 Position */
\r
16176 #define PORT15_OMR_PS15_Msk (0x01UL << PORT15_OMR_PS15_Pos) /*!< PORT15 OMR: PS15 Mask */
\r
16177 #define PORT15_OMR_PR0_Pos 16 /*!< PORT15 OMR: PR0 Position */
\r
16178 #define PORT15_OMR_PR0_Msk (0x01UL << PORT15_OMR_PR0_Pos) /*!< PORT15 OMR: PR0 Mask */
\r
16179 #define PORT15_OMR_PR1_Pos 17 /*!< PORT15 OMR: PR1 Position */
\r
16180 #define PORT15_OMR_PR1_Msk (0x01UL << PORT15_OMR_PR1_Pos) /*!< PORT15 OMR: PR1 Mask */
\r
16181 #define PORT15_OMR_PR2_Pos 18 /*!< PORT15 OMR: PR2 Position */
\r
16182 #define PORT15_OMR_PR2_Msk (0x01UL << PORT15_OMR_PR2_Pos) /*!< PORT15 OMR: PR2 Mask */
\r
16183 #define PORT15_OMR_PR3_Pos 19 /*!< PORT15 OMR: PR3 Position */
\r
16184 #define PORT15_OMR_PR3_Msk (0x01UL << PORT15_OMR_PR3_Pos) /*!< PORT15 OMR: PR3 Mask */
\r
16185 #define PORT15_OMR_PR4_Pos 20 /*!< PORT15 OMR: PR4 Position */
\r
16186 #define PORT15_OMR_PR4_Msk (0x01UL << PORT15_OMR_PR4_Pos) /*!< PORT15 OMR: PR4 Mask */
\r
16187 #define PORT15_OMR_PR5_Pos 21 /*!< PORT15 OMR: PR5 Position */
\r
16188 #define PORT15_OMR_PR5_Msk (0x01UL << PORT15_OMR_PR5_Pos) /*!< PORT15 OMR: PR5 Mask */
\r
16189 #define PORT15_OMR_PR6_Pos 22 /*!< PORT15 OMR: PR6 Position */
\r
16190 #define PORT15_OMR_PR6_Msk (0x01UL << PORT15_OMR_PR6_Pos) /*!< PORT15 OMR: PR6 Mask */
\r
16191 #define PORT15_OMR_PR7_Pos 23 /*!< PORT15 OMR: PR7 Position */
\r
16192 #define PORT15_OMR_PR7_Msk (0x01UL << PORT15_OMR_PR7_Pos) /*!< PORT15 OMR: PR7 Mask */
\r
16193 #define PORT15_OMR_PR8_Pos 24 /*!< PORT15 OMR: PR8 Position */
\r
16194 #define PORT15_OMR_PR8_Msk (0x01UL << PORT15_OMR_PR8_Pos) /*!< PORT15 OMR: PR8 Mask */
\r
16195 #define PORT15_OMR_PR9_Pos 25 /*!< PORT15 OMR: PR9 Position */
\r
16196 #define PORT15_OMR_PR9_Msk (0x01UL << PORT15_OMR_PR9_Pos) /*!< PORT15 OMR: PR9 Mask */
\r
16197 #define PORT15_OMR_PR10_Pos 26 /*!< PORT15 OMR: PR10 Position */
\r
16198 #define PORT15_OMR_PR10_Msk (0x01UL << PORT15_OMR_PR10_Pos) /*!< PORT15 OMR: PR10 Mask */
\r
16199 #define PORT15_OMR_PR11_Pos 27 /*!< PORT15 OMR: PR11 Position */
\r
16200 #define PORT15_OMR_PR11_Msk (0x01UL << PORT15_OMR_PR11_Pos) /*!< PORT15 OMR: PR11 Mask */
\r
16201 #define PORT15_OMR_PR12_Pos 28 /*!< PORT15 OMR: PR12 Position */
\r
16202 #define PORT15_OMR_PR12_Msk (0x01UL << PORT15_OMR_PR12_Pos) /*!< PORT15 OMR: PR12 Mask */
\r
16203 #define PORT15_OMR_PR13_Pos 29 /*!< PORT15 OMR: PR13 Position */
\r
16204 #define PORT15_OMR_PR13_Msk (0x01UL << PORT15_OMR_PR13_Pos) /*!< PORT15 OMR: PR13 Mask */
\r
16205 #define PORT15_OMR_PR14_Pos 30 /*!< PORT15 OMR: PR14 Position */
\r
16206 #define PORT15_OMR_PR14_Msk (0x01UL << PORT15_OMR_PR14_Pos) /*!< PORT15 OMR: PR14 Mask */
\r
16207 #define PORT15_OMR_PR15_Pos 31 /*!< PORT15 OMR: PR15 Position */
\r
16208 #define PORT15_OMR_PR15_Msk (0x01UL << PORT15_OMR_PR15_Pos) /*!< PORT15 OMR: PR15 Mask */
\r
16210 /* -------------------------------- PORT15_IOCR0 -------------------------------- */
\r
16211 #define PORT15_IOCR0_PC0_Pos 3 /*!< PORT15 IOCR0: PC0 Position */
\r
16212 #define PORT15_IOCR0_PC0_Msk (0x1fUL << PORT15_IOCR0_PC0_Pos) /*!< PORT15 IOCR0: PC0 Mask */
\r
16213 #define PORT15_IOCR0_PC1_Pos 11 /*!< PORT15 IOCR0: PC1 Position */
\r
16214 #define PORT15_IOCR0_PC1_Msk (0x1fUL << PORT15_IOCR0_PC1_Pos) /*!< PORT15 IOCR0: PC1 Mask */
\r
16215 #define PORT15_IOCR0_PC2_Pos 19 /*!< PORT15 IOCR0: PC2 Position */
\r
16216 #define PORT15_IOCR0_PC2_Msk (0x1fUL << PORT15_IOCR0_PC2_Pos) /*!< PORT15 IOCR0: PC2 Mask */
\r
16217 #define PORT15_IOCR0_PC3_Pos 27 /*!< PORT15 IOCR0: PC3 Position */
\r
16218 #define PORT15_IOCR0_PC3_Msk (0x1fUL << PORT15_IOCR0_PC3_Pos) /*!< PORT15 IOCR0: PC3 Mask */
\r
16220 /* -------------------------------- PORT15_IOCR4 -------------------------------- */
\r
16221 #define PORT15_IOCR4_PC4_Pos 3 /*!< PORT15 IOCR4: PC4 Position */
\r
16222 #define PORT15_IOCR4_PC4_Msk (0x1fUL << PORT15_IOCR4_PC4_Pos) /*!< PORT15 IOCR4: PC4 Mask */
\r
16223 #define PORT15_IOCR4_PC5_Pos 11 /*!< PORT15 IOCR4: PC5 Position */
\r
16224 #define PORT15_IOCR4_PC5_Msk (0x1fUL << PORT15_IOCR4_PC5_Pos) /*!< PORT15 IOCR4: PC5 Mask */
\r
16225 #define PORT15_IOCR4_PC6_Pos 19 /*!< PORT15 IOCR4: PC6 Position */
\r
16226 #define PORT15_IOCR4_PC6_Msk (0x1fUL << PORT15_IOCR4_PC6_Pos) /*!< PORT15 IOCR4: PC6 Mask */
\r
16227 #define PORT15_IOCR4_PC7_Pos 27 /*!< PORT15 IOCR4: PC7 Position */
\r
16228 #define PORT15_IOCR4_PC7_Msk (0x1fUL << PORT15_IOCR4_PC7_Pos) /*!< PORT15 IOCR4: PC7 Mask */
\r
16230 /* -------------------------------- PORT15_IOCR8 -------------------------------- */
\r
16231 #define PORT15_IOCR8_PC8_Pos 3 /*!< PORT15 IOCR8: PC8 Position */
\r
16232 #define PORT15_IOCR8_PC8_Msk (0x1fUL << PORT15_IOCR8_PC8_Pos) /*!< PORT15 IOCR8: PC8 Mask */
\r
16233 #define PORT15_IOCR8_PC9_Pos 11 /*!< PORT15 IOCR8: PC9 Position */
\r
16234 #define PORT15_IOCR8_PC9_Msk (0x1fUL << PORT15_IOCR8_PC9_Pos) /*!< PORT15 IOCR8: PC9 Mask */
\r
16235 #define PORT15_IOCR8_PC10_Pos 19 /*!< PORT15 IOCR8: PC10 Position */
\r
16236 #define PORT15_IOCR8_PC10_Msk (0x1fUL << PORT15_IOCR8_PC10_Pos) /*!< PORT15 IOCR8: PC10 Mask */
\r
16237 #define PORT15_IOCR8_PC11_Pos 27 /*!< PORT15 IOCR8: PC11 Position */
\r
16238 #define PORT15_IOCR8_PC11_Msk (0x1fUL << PORT15_IOCR8_PC11_Pos) /*!< PORT15 IOCR8: PC11 Mask */
\r
16240 /* ---------------------------------- PORT15_IN --------------------------------- */
\r
16241 #define PORT15_IN_P0_Pos 0 /*!< PORT15 IN: P0 Position */
\r
16242 #define PORT15_IN_P0_Msk (0x01UL << PORT15_IN_P0_Pos) /*!< PORT15 IN: P0 Mask */
\r
16243 #define PORT15_IN_P1_Pos 1 /*!< PORT15 IN: P1 Position */
\r
16244 #define PORT15_IN_P1_Msk (0x01UL << PORT15_IN_P1_Pos) /*!< PORT15 IN: P1 Mask */
\r
16245 #define PORT15_IN_P2_Pos 2 /*!< PORT15 IN: P2 Position */
\r
16246 #define PORT15_IN_P2_Msk (0x01UL << PORT15_IN_P2_Pos) /*!< PORT15 IN: P2 Mask */
\r
16247 #define PORT15_IN_P3_Pos 3 /*!< PORT15 IN: P3 Position */
\r
16248 #define PORT15_IN_P3_Msk (0x01UL << PORT15_IN_P3_Pos) /*!< PORT15 IN: P3 Mask */
\r
16249 #define PORT15_IN_P4_Pos 4 /*!< PORT15 IN: P4 Position */
\r
16250 #define PORT15_IN_P4_Msk (0x01UL << PORT15_IN_P4_Pos) /*!< PORT15 IN: P4 Mask */
\r
16251 #define PORT15_IN_P5_Pos 5 /*!< PORT15 IN: P5 Position */
\r
16252 #define PORT15_IN_P5_Msk (0x01UL << PORT15_IN_P5_Pos) /*!< PORT15 IN: P5 Mask */
\r
16253 #define PORT15_IN_P6_Pos 6 /*!< PORT15 IN: P6 Position */
\r
16254 #define PORT15_IN_P6_Msk (0x01UL << PORT15_IN_P6_Pos) /*!< PORT15 IN: P6 Mask */
\r
16255 #define PORT15_IN_P7_Pos 7 /*!< PORT15 IN: P7 Position */
\r
16256 #define PORT15_IN_P7_Msk (0x01UL << PORT15_IN_P7_Pos) /*!< PORT15 IN: P7 Mask */
\r
16257 #define PORT15_IN_P8_Pos 8 /*!< PORT15 IN: P8 Position */
\r
16258 #define PORT15_IN_P8_Msk (0x01UL << PORT15_IN_P8_Pos) /*!< PORT15 IN: P8 Mask */
\r
16259 #define PORT15_IN_P9_Pos 9 /*!< PORT15 IN: P9 Position */
\r
16260 #define PORT15_IN_P9_Msk (0x01UL << PORT15_IN_P9_Pos) /*!< PORT15 IN: P9 Mask */
\r
16261 #define PORT15_IN_P10_Pos 10 /*!< PORT15 IN: P10 Position */
\r
16262 #define PORT15_IN_P10_Msk (0x01UL << PORT15_IN_P10_Pos) /*!< PORT15 IN: P10 Mask */
\r
16263 #define PORT15_IN_P11_Pos 11 /*!< PORT15 IN: P11 Position */
\r
16264 #define PORT15_IN_P11_Msk (0x01UL << PORT15_IN_P11_Pos) /*!< PORT15 IN: P11 Mask */
\r
16265 #define PORT15_IN_P12_Pos 12 /*!< PORT15 IN: P12 Position */
\r
16266 #define PORT15_IN_P12_Msk (0x01UL << PORT15_IN_P12_Pos) /*!< PORT15 IN: P12 Mask */
\r
16267 #define PORT15_IN_P13_Pos 13 /*!< PORT15 IN: P13 Position */
\r
16268 #define PORT15_IN_P13_Msk (0x01UL << PORT15_IN_P13_Pos) /*!< PORT15 IN: P13 Mask */
\r
16269 #define PORT15_IN_P14_Pos 14 /*!< PORT15 IN: P14 Position */
\r
16270 #define PORT15_IN_P14_Msk (0x01UL << PORT15_IN_P14_Pos) /*!< PORT15 IN: P14 Mask */
\r
16271 #define PORT15_IN_P15_Pos 15 /*!< PORT15 IN: P15 Position */
\r
16272 #define PORT15_IN_P15_Msk (0x01UL << PORT15_IN_P15_Pos) /*!< PORT15 IN: P15 Mask */
\r
16274 /* -------------------------------- PORT15_PDISC -------------------------------- */
\r
16275 #define PORT15_PDISC_PDIS0_Pos 0 /*!< PORT15 PDISC: PDIS0 Position */
\r
16276 #define PORT15_PDISC_PDIS0_Msk (0x01UL << PORT15_PDISC_PDIS0_Pos) /*!< PORT15 PDISC: PDIS0 Mask */
\r
16277 #define PORT15_PDISC_PDIS1_Pos 1 /*!< PORT15 PDISC: PDIS1 Position */
\r
16278 #define PORT15_PDISC_PDIS1_Msk (0x01UL << PORT15_PDISC_PDIS1_Pos) /*!< PORT15 PDISC: PDIS1 Mask */
\r
16279 #define PORT15_PDISC_PDIS2_Pos 2 /*!< PORT15 PDISC: PDIS2 Position */
\r
16280 #define PORT15_PDISC_PDIS2_Msk (0x01UL << PORT15_PDISC_PDIS2_Pos) /*!< PORT15 PDISC: PDIS2 Mask */
\r
16281 #define PORT15_PDISC_PDIS3_Pos 3 /*!< PORT15 PDISC: PDIS3 Position */
\r
16282 #define PORT15_PDISC_PDIS3_Msk (0x01UL << PORT15_PDISC_PDIS3_Pos) /*!< PORT15 PDISC: PDIS3 Mask */
\r
16283 #define PORT15_PDISC_PDIS4_Pos 4 /*!< PORT15 PDISC: PDIS4 Position */
\r
16284 #define PORT15_PDISC_PDIS4_Msk (0x01UL << PORT15_PDISC_PDIS4_Pos) /*!< PORT15 PDISC: PDIS4 Mask */
\r
16285 #define PORT15_PDISC_PDIS5_Pos 5 /*!< PORT15 PDISC: PDIS5 Position */
\r
16286 #define PORT15_PDISC_PDIS5_Msk (0x01UL << PORT15_PDISC_PDIS5_Pos) /*!< PORT15 PDISC: PDIS5 Mask */
\r
16287 #define PORT15_PDISC_PDIS6_Pos 6 /*!< PORT15 PDISC: PDIS6 Position */
\r
16288 #define PORT15_PDISC_PDIS6_Msk (0x01UL << PORT15_PDISC_PDIS6_Pos) /*!< PORT15 PDISC: PDIS6 Mask */
\r
16289 #define PORT15_PDISC_PDIS7_Pos 7 /*!< PORT15 PDISC: PDIS7 Position */
\r
16290 #define PORT15_PDISC_PDIS7_Msk (0x01UL << PORT15_PDISC_PDIS7_Pos) /*!< PORT15 PDISC: PDIS7 Mask */
\r
16291 #define PORT15_PDISC_PDIS8_Pos 8 /*!< PORT15 PDISC: PDIS8 Position */
\r
16292 #define PORT15_PDISC_PDIS8_Msk (0x01UL << PORT15_PDISC_PDIS8_Pos) /*!< PORT15 PDISC: PDIS8 Mask */
\r
16293 #define PORT15_PDISC_PDIS9_Pos 9 /*!< PORT15 PDISC: PDIS9 Position */
\r
16294 #define PORT15_PDISC_PDIS9_Msk (0x01UL << PORT15_PDISC_PDIS9_Pos) /*!< PORT15 PDISC: PDIS9 Mask */
\r
16295 #define PORT15_PDISC_PDIS10_Pos 10 /*!< PORT15 PDISC: PDIS10 Position */
\r
16296 #define PORT15_PDISC_PDIS10_Msk (0x01UL << PORT15_PDISC_PDIS10_Pos) /*!< PORT15 PDISC: PDIS10 Mask */
\r
16297 #define PORT15_PDISC_PDIS11_Pos 11 /*!< PORT15 PDISC: PDIS11 Position */
\r
16298 #define PORT15_PDISC_PDIS11_Msk (0x01UL << PORT15_PDISC_PDIS11_Pos) /*!< PORT15 PDISC: PDIS11 Mask */
\r
16299 #define PORT15_PDISC_PDIS12_Pos 12 /*!< PORT15 PDISC: PDIS12 Position */
\r
16300 #define PORT15_PDISC_PDIS12_Msk (0x01UL << PORT15_PDISC_PDIS12_Pos) /*!< PORT15 PDISC: PDIS12 Mask */
\r
16301 #define PORT15_PDISC_PDIS13_Pos 13 /*!< PORT15 PDISC: PDIS13 Position */
\r
16302 #define PORT15_PDISC_PDIS13_Msk (0x01UL << PORT15_PDISC_PDIS13_Pos) /*!< PORT15 PDISC: PDIS13 Mask */
\r
16303 #define PORT15_PDISC_PDIS14_Pos 14 /*!< PORT15 PDISC: PDIS14 Position */
\r
16304 #define PORT15_PDISC_PDIS14_Msk (0x01UL << PORT15_PDISC_PDIS14_Pos) /*!< PORT15 PDISC: PDIS14 Mask */
\r
16305 #define PORT15_PDISC_PDIS15_Pos 15 /*!< PORT15 PDISC: PDIS15 Position */
\r
16306 #define PORT15_PDISC_PDIS15_Msk (0x01UL << PORT15_PDISC_PDIS15_Pos) /*!< PORT15 PDISC: PDIS15 Mask */
\r
16308 /* --------------------------------- PORT15_PPS --------------------------------- */
\r
16309 #define PORT15_PPS_PPS0_Pos 0 /*!< PORT15 PPS: PPS0 Position */
\r
16310 #define PORT15_PPS_PPS0_Msk (0x01UL << PORT15_PPS_PPS0_Pos) /*!< PORT15 PPS: PPS0 Mask */
\r
16311 #define PORT15_PPS_PPS1_Pos 1 /*!< PORT15 PPS: PPS1 Position */
\r
16312 #define PORT15_PPS_PPS1_Msk (0x01UL << PORT15_PPS_PPS1_Pos) /*!< PORT15 PPS: PPS1 Mask */
\r
16313 #define PORT15_PPS_PPS2_Pos 2 /*!< PORT15 PPS: PPS2 Position */
\r
16314 #define PORT15_PPS_PPS2_Msk (0x01UL << PORT15_PPS_PPS2_Pos) /*!< PORT15 PPS: PPS2 Mask */
\r
16315 #define PORT15_PPS_PPS3_Pos 3 /*!< PORT15 PPS: PPS3 Position */
\r
16316 #define PORT15_PPS_PPS3_Msk (0x01UL << PORT15_PPS_PPS3_Pos) /*!< PORT15 PPS: PPS3 Mask */
\r
16317 #define PORT15_PPS_PPS4_Pos 4 /*!< PORT15 PPS: PPS4 Position */
\r
16318 #define PORT15_PPS_PPS4_Msk (0x01UL << PORT15_PPS_PPS4_Pos) /*!< PORT15 PPS: PPS4 Mask */
\r
16319 #define PORT15_PPS_PPS5_Pos 5 /*!< PORT15 PPS: PPS5 Position */
\r
16320 #define PORT15_PPS_PPS5_Msk (0x01UL << PORT15_PPS_PPS5_Pos) /*!< PORT15 PPS: PPS5 Mask */
\r
16321 #define PORT15_PPS_PPS6_Pos 6 /*!< PORT15 PPS: PPS6 Position */
\r
16322 #define PORT15_PPS_PPS6_Msk (0x01UL << PORT15_PPS_PPS6_Pos) /*!< PORT15 PPS: PPS6 Mask */
\r
16323 #define PORT15_PPS_PPS7_Pos 7 /*!< PORT15 PPS: PPS7 Position */
\r
16324 #define PORT15_PPS_PPS7_Msk (0x01UL << PORT15_PPS_PPS7_Pos) /*!< PORT15 PPS: PPS7 Mask */
\r
16325 #define PORT15_PPS_PPS8_Pos 8 /*!< PORT15 PPS: PPS8 Position */
\r
16326 #define PORT15_PPS_PPS8_Msk (0x01UL << PORT15_PPS_PPS8_Pos) /*!< PORT15 PPS: PPS8 Mask */
\r
16327 #define PORT15_PPS_PPS9_Pos 9 /*!< PORT15 PPS: PPS9 Position */
\r
16328 #define PORT15_PPS_PPS9_Msk (0x01UL << PORT15_PPS_PPS9_Pos) /*!< PORT15 PPS: PPS9 Mask */
\r
16329 #define PORT15_PPS_PPS10_Pos 10 /*!< PORT15 PPS: PPS10 Position */
\r
16330 #define PORT15_PPS_PPS10_Msk (0x01UL << PORT15_PPS_PPS10_Pos) /*!< PORT15 PPS: PPS10 Mask */
\r
16331 #define PORT15_PPS_PPS11_Pos 11 /*!< PORT15 PPS: PPS11 Position */
\r
16332 #define PORT15_PPS_PPS11_Msk (0x01UL << PORT15_PPS_PPS11_Pos) /*!< PORT15 PPS: PPS11 Mask */
\r
16333 #define PORT15_PPS_PPS12_Pos 12 /*!< PORT15 PPS: PPS12 Position */
\r
16334 #define PORT15_PPS_PPS12_Msk (0x01UL << PORT15_PPS_PPS12_Pos) /*!< PORT15 PPS: PPS12 Mask */
\r
16335 #define PORT15_PPS_PPS13_Pos 13 /*!< PORT15 PPS: PPS13 Position */
\r
16336 #define PORT15_PPS_PPS13_Msk (0x01UL << PORT15_PPS_PPS13_Pos) /*!< PORT15 PPS: PPS13 Mask */
\r
16337 #define PORT15_PPS_PPS14_Pos 14 /*!< PORT15 PPS: PPS14 Position */
\r
16338 #define PORT15_PPS_PPS14_Msk (0x01UL << PORT15_PPS_PPS14_Pos) /*!< PORT15 PPS: PPS14 Mask */
\r
16339 #define PORT15_PPS_PPS15_Pos 15 /*!< PORT15 PPS: PPS15 Position */
\r
16340 #define PORT15_PPS_PPS15_Msk (0x01UL << PORT15_PPS_PPS15_Pos) /*!< PORT15 PPS: PPS15 Mask */
\r
16342 /* -------------------------------- PORT15_HWSEL -------------------------------- */
\r
16343 #define PORT15_HWSEL_HW0_Pos 0 /*!< PORT15 HWSEL: HW0 Position */
\r
16344 #define PORT15_HWSEL_HW0_Msk (0x03UL << PORT15_HWSEL_HW0_Pos) /*!< PORT15 HWSEL: HW0 Mask */
\r
16345 #define PORT15_HWSEL_HW1_Pos 2 /*!< PORT15 HWSEL: HW1 Position */
\r
16346 #define PORT15_HWSEL_HW1_Msk (0x03UL << PORT15_HWSEL_HW1_Pos) /*!< PORT15 HWSEL: HW1 Mask */
\r
16347 #define PORT15_HWSEL_HW2_Pos 4 /*!< PORT15 HWSEL: HW2 Position */
\r
16348 #define PORT15_HWSEL_HW2_Msk (0x03UL << PORT15_HWSEL_HW2_Pos) /*!< PORT15 HWSEL: HW2 Mask */
\r
16349 #define PORT15_HWSEL_HW3_Pos 6 /*!< PORT15 HWSEL: HW3 Position */
\r
16350 #define PORT15_HWSEL_HW3_Msk (0x03UL << PORT15_HWSEL_HW3_Pos) /*!< PORT15 HWSEL: HW3 Mask */
\r
16351 #define PORT15_HWSEL_HW4_Pos 8 /*!< PORT15 HWSEL: HW4 Position */
\r
16352 #define PORT15_HWSEL_HW4_Msk (0x03UL << PORT15_HWSEL_HW4_Pos) /*!< PORT15 HWSEL: HW4 Mask */
\r
16353 #define PORT15_HWSEL_HW5_Pos 10 /*!< PORT15 HWSEL: HW5 Position */
\r
16354 #define PORT15_HWSEL_HW5_Msk (0x03UL << PORT15_HWSEL_HW5_Pos) /*!< PORT15 HWSEL: HW5 Mask */
\r
16355 #define PORT15_HWSEL_HW6_Pos 12 /*!< PORT15 HWSEL: HW6 Position */
\r
16356 #define PORT15_HWSEL_HW6_Msk (0x03UL << PORT15_HWSEL_HW6_Pos) /*!< PORT15 HWSEL: HW6 Mask */
\r
16357 #define PORT15_HWSEL_HW7_Pos 14 /*!< PORT15 HWSEL: HW7 Position */
\r
16358 #define PORT15_HWSEL_HW7_Msk (0x03UL << PORT15_HWSEL_HW7_Pos) /*!< PORT15 HWSEL: HW7 Mask */
\r
16359 #define PORT15_HWSEL_HW8_Pos 16 /*!< PORT15 HWSEL: HW8 Position */
\r
16360 #define PORT15_HWSEL_HW8_Msk (0x03UL << PORT15_HWSEL_HW8_Pos) /*!< PORT15 HWSEL: HW8 Mask */
\r
16361 #define PORT15_HWSEL_HW9_Pos 18 /*!< PORT15 HWSEL: HW9 Position */
\r
16362 #define PORT15_HWSEL_HW9_Msk (0x03UL << PORT15_HWSEL_HW9_Pos) /*!< PORT15 HWSEL: HW9 Mask */
\r
16363 #define PORT15_HWSEL_HW10_Pos 20 /*!< PORT15 HWSEL: HW10 Position */
\r
16364 #define PORT15_HWSEL_HW10_Msk (0x03UL << PORT15_HWSEL_HW10_Pos) /*!< PORT15 HWSEL: HW10 Mask */
\r
16365 #define PORT15_HWSEL_HW11_Pos 22 /*!< PORT15 HWSEL: HW11 Position */
\r
16366 #define PORT15_HWSEL_HW11_Msk (0x03UL << PORT15_HWSEL_HW11_Pos) /*!< PORT15 HWSEL: HW11 Mask */
\r
16367 #define PORT15_HWSEL_HW12_Pos 24 /*!< PORT15 HWSEL: HW12 Position */
\r
16368 #define PORT15_HWSEL_HW12_Msk (0x03UL << PORT15_HWSEL_HW12_Pos) /*!< PORT15 HWSEL: HW12 Mask */
\r
16369 #define PORT15_HWSEL_HW13_Pos 26 /*!< PORT15 HWSEL: HW13 Position */
\r
16370 #define PORT15_HWSEL_HW13_Msk (0x03UL << PORT15_HWSEL_HW13_Pos) /*!< PORT15 HWSEL: HW13 Mask */
\r
16371 #define PORT15_HWSEL_HW14_Pos 28 /*!< PORT15 HWSEL: HW14 Position */
\r
16372 #define PORT15_HWSEL_HW14_Msk (0x03UL << PORT15_HWSEL_HW14_Pos) /*!< PORT15 HWSEL: HW14 Mask */
\r
16373 #define PORT15_HWSEL_HW15_Pos 30 /*!< PORT15 HWSEL: HW15 Position */
\r
16374 #define PORT15_HWSEL_HW15_Msk (0x03UL << PORT15_HWSEL_HW15_Pos) /*!< PORT15 HWSEL: HW15 Mask */
\r
16378 /* ================================================================================ */
\r
16379 /* ================ Peripheral memory map ================ */
\r
16380 /* ================================================================================ */
\r
16382 #define PPB_BASE 0xE000E000UL
\r
16383 #define DLR_BASE 0x50004900UL
\r
16384 #define ERU0_BASE 0x50004800UL
\r
16385 #define ERU1_BASE 0x40044000UL
\r
16386 #define GPDMA0_BASE 0x500142C0UL
\r
16387 #define GPDMA0_CH0_BASE 0x50014000UL
\r
16388 #define GPDMA0_CH1_BASE 0x50014058UL
\r
16389 #define GPDMA0_CH2_BASE 0x500140B0UL
\r
16390 #define GPDMA0_CH3_BASE 0x50014108UL
\r
16391 #define GPDMA0_CH4_BASE 0x50014160UL
\r
16392 #define GPDMA0_CH5_BASE 0x500141B8UL
\r
16393 #define GPDMA0_CH6_BASE 0x50014210UL
\r
16394 #define GPDMA0_CH7_BASE 0x50014268UL
\r
16395 #define FCE_BASE 0x50020000UL
\r
16396 #define FCE_KE0_BASE 0x50020020UL
\r
16397 #define FCE_KE1_BASE 0x50020040UL
\r
16398 #define FCE_KE2_BASE 0x50020060UL
\r
16399 #define FCE_KE3_BASE 0x50020080UL
\r
16400 #define PBA0_BASE 0x40000000UL
\r
16401 #define PBA1_BASE 0x48000000UL
\r
16402 #define FLASH0_BASE 0x58001000UL
\r
16403 #define PREF_BASE 0x58004000UL
\r
16404 #define PMU0_BASE 0x58000508UL
\r
16405 #define WDT_BASE 0x50008000UL
\r
16406 #define RTC_BASE 0x50004A00UL
\r
16407 #define SCU_CLK_BASE 0x50004600UL
\r
16408 #define SCU_OSC_BASE 0x50004700UL
\r
16409 #define SCU_PLL_BASE 0x50004710UL
\r
16410 #define SCU_GENERAL_BASE 0x50004000UL
\r
16411 #define SCU_INTERRUPT_BASE 0x50004074UL
\r
16412 #define SCU_PARITY_BASE 0x5000413CUL
\r
16413 #define SCU_TRAP_BASE 0x50004160UL
\r
16414 #define SCU_HIBERNATE_BASE 0x50004300UL
\r
16415 #define SCU_POWER_BASE 0x50004200UL
\r
16416 #define SCU_RESET_BASE 0x50004400UL
\r
16417 #define LEDTS0_BASE 0x48010000UL
\r
16418 #define ETH0_CON_BASE 0x50004040UL
\r
16419 #define ETH0_BASE 0x5000C000UL
\r
16420 #define USB0_BASE 0x50040000UL
\r
16421 #define USB_EP_BASE 0x50040900UL
\r
16422 #define USB0_EP1_BASE 0x50040920UL
\r
16423 #define USB0_EP2_BASE 0x50040940UL
\r
16424 #define USB0_EP3_BASE 0x50040960UL
\r
16425 #define USB0_EP4_BASE 0x50040980UL
\r
16426 #define USB0_EP5_BASE 0x500409A0UL
\r
16427 #define USB0_EP6_BASE 0x500409C0UL
\r
16428 #define USB0_CH0_BASE 0x50040500UL
\r
16429 #define USB0_CH1_BASE 0x50040520UL
\r
16430 #define USB0_CH2_BASE 0x50040540UL
\r
16431 #define USB0_CH3_BASE 0x50040560UL
\r
16432 #define USB0_CH4_BASE 0x50040580UL
\r
16433 #define USB0_CH5_BASE 0x500405A0UL
\r
16434 #define USB0_CH6_BASE 0x500405C0UL
\r
16435 #define USB0_CH7_BASE 0x500405E0UL
\r
16436 #define USB0_CH8_BASE 0x50040600UL
\r
16437 #define USB0_CH9_BASE 0x50040620UL
\r
16438 #define USB0_CH10_BASE 0x50040640UL
\r
16439 #define USB0_CH11_BASE 0x50040660UL
\r
16440 #define USB0_CH12_BASE 0x50040680UL
\r
16441 #define USB0_CH13_BASE 0x500406A0UL
\r
16442 #define USIC0_BASE 0x40030008UL
\r
16443 #define USIC1_BASE 0x48020008UL
\r
16444 #define USIC0_CH0_BASE 0x40030000UL
\r
16445 #define USIC0_CH1_BASE 0x40030200UL
\r
16446 #define USIC1_CH0_BASE 0x48020000UL
\r
16447 #define USIC1_CH1_BASE 0x48020200UL
\r
16448 #define CAN_BASE 0x48014000UL
\r
16449 #define CAN_NODE0_BASE 0x48014200UL
\r
16450 #define CAN_NODE1_BASE 0x48014300UL
\r
16451 #define CAN_MO0_BASE 0x48015000UL
\r
16452 #define CAN_MO1_BASE 0x48015020UL
\r
16453 #define CAN_MO2_BASE 0x48015040UL
\r
16454 #define CAN_MO3_BASE 0x48015060UL
\r
16455 #define CAN_MO4_BASE 0x48015080UL
\r
16456 #define CAN_MO5_BASE 0x480150A0UL
\r
16457 #define CAN_MO6_BASE 0x480150C0UL
\r
16458 #define CAN_MO7_BASE 0x480150E0UL
\r
16459 #define CAN_MO8_BASE 0x48015100UL
\r
16460 #define CAN_MO9_BASE 0x48015120UL
\r
16461 #define CAN_MO10_BASE 0x48015140UL
\r
16462 #define CAN_MO11_BASE 0x48015160UL
\r
16463 #define CAN_MO12_BASE 0x48015180UL
\r
16464 #define CAN_MO13_BASE 0x480151A0UL
\r
16465 #define CAN_MO14_BASE 0x480151C0UL
\r
16466 #define CAN_MO15_BASE 0x480151E0UL
\r
16467 #define CAN_MO16_BASE 0x48015200UL
\r
16468 #define CAN_MO17_BASE 0x48015220UL
\r
16469 #define CAN_MO18_BASE 0x48015240UL
\r
16470 #define CAN_MO19_BASE 0x48015260UL
\r
16471 #define CAN_MO20_BASE 0x48015280UL
\r
16472 #define CAN_MO21_BASE 0x480152A0UL
\r
16473 #define CAN_MO22_BASE 0x480152C0UL
\r
16474 #define CAN_MO23_BASE 0x480152E0UL
\r
16475 #define CAN_MO24_BASE 0x48015300UL
\r
16476 #define CAN_MO25_BASE 0x48015320UL
\r
16477 #define CAN_MO26_BASE 0x48015340UL
\r
16478 #define CAN_MO27_BASE 0x48015360UL
\r
16479 #define CAN_MO28_BASE 0x48015380UL
\r
16480 #define CAN_MO29_BASE 0x480153A0UL
\r
16481 #define CAN_MO30_BASE 0x480153C0UL
\r
16482 #define CAN_MO31_BASE 0x480153E0UL
\r
16483 #define CAN_MO32_BASE 0x48015400UL
\r
16484 #define CAN_MO33_BASE 0x48015420UL
\r
16485 #define CAN_MO34_BASE 0x48015440UL
\r
16486 #define CAN_MO35_BASE 0x48015460UL
\r
16487 #define CAN_MO36_BASE 0x48015480UL
\r
16488 #define CAN_MO37_BASE 0x480154A0UL
\r
16489 #define CAN_MO38_BASE 0x480154C0UL
\r
16490 #define CAN_MO39_BASE 0x480154E0UL
\r
16491 #define CAN_MO40_BASE 0x48015500UL
\r
16492 #define CAN_MO41_BASE 0x48015520UL
\r
16493 #define CAN_MO42_BASE 0x48015540UL
\r
16494 #define CAN_MO43_BASE 0x48015560UL
\r
16495 #define CAN_MO44_BASE 0x48015580UL
\r
16496 #define CAN_MO45_BASE 0x480155A0UL
\r
16497 #define CAN_MO46_BASE 0x480155C0UL
\r
16498 #define CAN_MO47_BASE 0x480155E0UL
\r
16499 #define CAN_MO48_BASE 0x48015600UL
\r
16500 #define CAN_MO49_BASE 0x48015620UL
\r
16501 #define CAN_MO50_BASE 0x48015640UL
\r
16502 #define CAN_MO51_BASE 0x48015660UL
\r
16503 #define CAN_MO52_BASE 0x48015680UL
\r
16504 #define CAN_MO53_BASE 0x480156A0UL
\r
16505 #define CAN_MO54_BASE 0x480156C0UL
\r
16506 #define CAN_MO55_BASE 0x480156E0UL
\r
16507 #define CAN_MO56_BASE 0x48015700UL
\r
16508 #define CAN_MO57_BASE 0x48015720UL
\r
16509 #define CAN_MO58_BASE 0x48015740UL
\r
16510 #define CAN_MO59_BASE 0x48015760UL
\r
16511 #define CAN_MO60_BASE 0x48015780UL
\r
16512 #define CAN_MO61_BASE 0x480157A0UL
\r
16513 #define CAN_MO62_BASE 0x480157C0UL
\r
16514 #define CAN_MO63_BASE 0x480157E0UL
\r
16515 #define VADC_BASE 0x40004000UL
\r
16516 #define VADC_G0_BASE 0x40004400UL
\r
16517 #define VADC_G1_BASE 0x40004800UL
\r
16518 #define VADC_G2_BASE 0x40004C00UL
\r
16519 #define VADC_G3_BASE 0x40005000UL
\r
16520 #define DSD_BASE 0x40008000UL
\r
16521 #define DSD_CH0_BASE 0x40008100UL
\r
16522 #define DSD_CH1_BASE 0x40008200UL
\r
16523 #define DSD_CH2_BASE 0x40008300UL
\r
16524 #define DSD_CH3_BASE 0x40008400UL
\r
16525 #define DAC_BASE 0x48018000UL
\r
16526 #define CCU40_BASE 0x4000C000UL
\r
16527 #define CCU41_BASE 0x40010000UL
\r
16528 #define CCU42_BASE 0x40014000UL
\r
16529 #define CCU43_BASE 0x48004000UL
\r
16530 #define CCU40_CC40_BASE 0x4000C100UL
\r
16531 #define CCU40_CC41_BASE 0x4000C200UL
\r
16532 #define CCU40_CC42_BASE 0x4000C300UL
\r
16533 #define CCU40_CC43_BASE 0x4000C400UL
\r
16534 #define CCU41_CC40_BASE 0x40010100UL
\r
16535 #define CCU41_CC41_BASE 0x40010200UL
\r
16536 #define CCU41_CC42_BASE 0x40010300UL
\r
16537 #define CCU41_CC43_BASE 0x40010400UL
\r
16538 #define CCU42_CC40_BASE 0x40014100UL
\r
16539 #define CCU42_CC41_BASE 0x40014200UL
\r
16540 #define CCU42_CC42_BASE 0x40014300UL
\r
16541 #define CCU42_CC43_BASE 0x40014400UL
\r
16542 #define CCU43_CC40_BASE 0x48004100UL
\r
16543 #define CCU43_CC41_BASE 0x48004200UL
\r
16544 #define CCU43_CC42_BASE 0x48004300UL
\r
16545 #define CCU43_CC43_BASE 0x48004400UL
\r
16546 #define CCU80_BASE 0x40020000UL
\r
16547 #define CCU81_BASE 0x40024000UL
\r
16548 #define CCU80_CC80_BASE 0x40020100UL
\r
16549 #define CCU80_CC81_BASE 0x40020200UL
\r
16550 #define CCU80_CC82_BASE 0x40020300UL
\r
16551 #define CCU80_CC83_BASE 0x40020400UL
\r
16552 #define CCU81_CC80_BASE 0x40024100UL
\r
16553 #define CCU81_CC81_BASE 0x40024200UL
\r
16554 #define CCU81_CC82_BASE 0x40024300UL
\r
16555 #define CCU81_CC83_BASE 0x40024400UL
\r
16556 #define HRPWM0_BASE 0x40020900UL
\r
16557 #define HRPWM0_CSG0_BASE 0x40020A00UL
\r
16558 #define HRPWM0_CSG1_BASE 0x40020B00UL
\r
16559 #define HRPWM0_CSG2_BASE 0x40020C00UL
\r
16560 #define HRPWM0_HRC0_BASE 0x40021300UL
\r
16561 #define HRPWM0_HRC1_BASE 0x40021400UL
\r
16562 #define HRPWM0_HRC2_BASE 0x40021500UL
\r
16563 #define HRPWM0_HRC3_BASE 0x40021600UL
\r
16564 #define POSIF0_BASE 0x40028000UL
\r
16565 #define POSIF1_BASE 0x4002C000UL
\r
16566 #define PORT0_BASE 0x48028000UL
\r
16567 #define PORT1_BASE 0x48028100UL
\r
16568 #define PORT2_BASE 0x48028200UL
\r
16569 #define PORT3_BASE 0x48028300UL
\r
16570 #define PORT4_BASE 0x48028400UL
\r
16571 #define PORT5_BASE 0x48028500UL
\r
16572 #define PORT14_BASE 0x48028E00UL
\r
16573 #define PORT15_BASE 0x48028F00UL
\r
16576 /* ================================================================================ */
\r
16577 /* ================ Peripheral declaration ================ */
\r
16578 /* ================================================================================ */
\r
16580 #define PPB ((PPB_Type *) PPB_BASE)
\r
16581 #define DLR ((DLR_GLOBAL_TypeDef *) DLR_BASE)
\r
16582 #define ERU0 ((ERU_GLOBAL_TypeDef *) ERU0_BASE)
\r
16583 #define ERU1 ((ERU_GLOBAL_TypeDef *) ERU1_BASE)
\r
16584 #define GPDMA0 ((GPDMA0_GLOBAL_TypeDef *) GPDMA0_BASE)
\r
16585 #define GPDMA0_CH0 ((GPDMA0_CH_TypeDef *) GPDMA0_CH0_BASE)
\r
16586 #define GPDMA0_CH1 ((GPDMA0_CH_TypeDef *) GPDMA0_CH1_BASE)
\r
16587 #define GPDMA0_CH2 ((GPDMA0_CH_TypeDef *) GPDMA0_CH2_BASE)
\r
16588 #define GPDMA0_CH3 ((GPDMA0_CH_TypeDef *) GPDMA0_CH3_BASE)
\r
16589 #define GPDMA0_CH4 ((GPDMA0_CH_TypeDef *) GPDMA0_CH4_BASE)
\r
16590 #define GPDMA0_CH5 ((GPDMA0_CH_TypeDef *) GPDMA0_CH5_BASE)
\r
16591 #define GPDMA0_CH6 ((GPDMA0_CH_TypeDef *) GPDMA0_CH6_BASE)
\r
16592 #define GPDMA0_CH7 ((GPDMA0_CH_TypeDef *) GPDMA0_CH7_BASE)
\r
16593 #define FCE ((FCE_GLOBAL_TypeDef *) FCE_BASE)
\r
16594 #define FCE_KE0 ((FCE_KE_TypeDef *) FCE_KE0_BASE)
\r
16595 #define FCE_KE1 ((FCE_KE_TypeDef *) FCE_KE1_BASE)
\r
16596 #define FCE_KE2 ((FCE_KE_TypeDef *) FCE_KE2_BASE)
\r
16597 #define FCE_KE3 ((FCE_KE_TypeDef *) FCE_KE3_BASE)
\r
16598 #define PBA0 ((PBA_GLOBAL_TypeDef *) PBA0_BASE)
\r
16599 #define PBA1 ((PBA_GLOBAL_TypeDef *) PBA1_BASE)
\r
16600 #define FLASH0 ((FLASH0_GLOBAL_TypeDef *) FLASH0_BASE)
\r
16601 #define PREF ((PREF_GLOBAL_TypeDef *) PREF_BASE)
\r
16602 #define PMU0 ((PMU0_GLOBAL_TypeDef *) PMU0_BASE)
\r
16603 #define WDT ((WDT_GLOBAL_TypeDef *) WDT_BASE)
\r
16604 #define RTC ((RTC_GLOBAL_TypeDef *) RTC_BASE)
\r
16605 #define SCU_CLK ((SCU_CLK_TypeDef *) SCU_CLK_BASE)
\r
16606 #define SCU_OSC ((SCU_OSC_TypeDef *) SCU_OSC_BASE)
\r
16607 #define SCU_PLL ((SCU_PLL_TypeDef *) SCU_PLL_BASE)
\r
16608 #define SCU_GENERAL ((SCU_GENERAL_TypeDef *) SCU_GENERAL_BASE)
\r
16609 #define SCU_INTERRUPT ((SCU_INTERRUPT_TypeDef *) SCU_INTERRUPT_BASE)
\r
16610 #define SCU_PARITY ((SCU_PARITY_TypeDef *) SCU_PARITY_BASE)
\r
16611 #define SCU_TRAP ((SCU_TRAP_TypeDef *) SCU_TRAP_BASE)
\r
16612 #define SCU_HIBERNATE ((SCU_HIBERNATE_TypeDef *) SCU_HIBERNATE_BASE)
\r
16613 #define SCU_POWER ((SCU_POWER_TypeDef *) SCU_POWER_BASE)
\r
16614 #define SCU_RESET ((SCU_RESET_TypeDef *) SCU_RESET_BASE)
\r
16615 #define LEDTS0 ((LEDTS0_GLOBAL_TypeDef *) LEDTS0_BASE)
\r
16616 #define ETH0_CON ((ETH0_CON_GLOBAL_TypeDef *) ETH0_CON_BASE)
\r
16617 #define ETH0 ((ETH_GLOBAL_TypeDef *) ETH0_BASE)
\r
16618 #define USB0 ((USB0_GLOBAL_TypeDef *) USB0_BASE)
\r
16619 #define USB0_EP0 ((USB0_EP0_TypeDef *) USB_EP_BASE)
\r
16620 #define USB0_EP1 ((USB0_EP_TypeDef *) USB0_EP1_BASE)
\r
16621 #define USB0_EP2 ((USB0_EP_TypeDef *) USB0_EP2_BASE)
\r
16622 #define USB0_EP3 ((USB0_EP_TypeDef *) USB0_EP3_BASE)
\r
16623 #define USB0_EP4 ((USB0_EP_TypeDef *) USB0_EP4_BASE)
\r
16624 #define USB0_EP5 ((USB0_EP_TypeDef *) USB0_EP5_BASE)
\r
16625 #define USB0_EP6 ((USB0_EP_TypeDef *) USB0_EP6_BASE)
\r
16626 #define USB0_CH0 ((USB0_CH_TypeDef *) USB0_CH0_BASE)
\r
16627 #define USB0_CH1 ((USB0_CH_TypeDef *) USB0_CH1_BASE)
\r
16628 #define USB0_CH2 ((USB0_CH_TypeDef *) USB0_CH2_BASE)
\r
16629 #define USB0_CH3 ((USB0_CH_TypeDef *) USB0_CH3_BASE)
\r
16630 #define USB0_CH4 ((USB0_CH_TypeDef *) USB0_CH4_BASE)
\r
16631 #define USB0_CH5 ((USB0_CH_TypeDef *) USB0_CH5_BASE)
\r
16632 #define USB0_CH6 ((USB0_CH_TypeDef *) USB0_CH6_BASE)
\r
16633 #define USB0_CH7 ((USB0_CH_TypeDef *) USB0_CH7_BASE)
\r
16634 #define USB0_CH8 ((USB0_CH_TypeDef *) USB0_CH8_BASE)
\r
16635 #define USB0_CH9 ((USB0_CH_TypeDef *) USB0_CH9_BASE)
\r
16636 #define USB0_CH10 ((USB0_CH_TypeDef *) USB0_CH10_BASE)
\r
16637 #define USB0_CH11 ((USB0_CH_TypeDef *) USB0_CH11_BASE)
\r
16638 #define USB0_CH12 ((USB0_CH_TypeDef *) USB0_CH12_BASE)
\r
16639 #define USB0_CH13 ((USB0_CH_TypeDef *) USB0_CH13_BASE)
\r
16640 #define USIC0 ((USIC_GLOBAL_TypeDef *) USIC0_BASE)
\r
16641 #define USIC1 ((USIC_GLOBAL_TypeDef *) USIC1_BASE)
\r
16642 #define USIC0_CH0 ((USIC_CH_TypeDef *) USIC0_CH0_BASE)
\r
16643 #define USIC0_CH1 ((USIC_CH_TypeDef *) USIC0_CH1_BASE)
\r
16644 #define USIC1_CH0 ((USIC_CH_TypeDef *) USIC1_CH0_BASE)
\r
16645 #define USIC1_CH1 ((USIC_CH_TypeDef *) USIC1_CH1_BASE)
\r
16646 #define CAN ((CAN_GLOBAL_TypeDef *) CAN_BASE)
\r
16647 #define CAN_NODE0 ((CAN_NODE_TypeDef *) CAN_NODE0_BASE)
\r
16648 #define CAN_NODE1 ((CAN_NODE_TypeDef *) CAN_NODE1_BASE)
\r
16649 #define CAN_MO0 ((CAN_MO_TypeDef *) CAN_MO0_BASE)
\r
16650 #define CAN_MO1 ((CAN_MO_TypeDef *) CAN_MO1_BASE)
\r
16651 #define CAN_MO2 ((CAN_MO_TypeDef *) CAN_MO2_BASE)
\r
16652 #define CAN_MO3 ((CAN_MO_TypeDef *) CAN_MO3_BASE)
\r
16653 #define CAN_MO4 ((CAN_MO_TypeDef *) CAN_MO4_BASE)
\r
16654 #define CAN_MO5 ((CAN_MO_TypeDef *) CAN_MO5_BASE)
\r
16655 #define CAN_MO6 ((CAN_MO_TypeDef *) CAN_MO6_BASE)
\r
16656 #define CAN_MO7 ((CAN_MO_TypeDef *) CAN_MO7_BASE)
\r
16657 #define CAN_MO8 ((CAN_MO_TypeDef *) CAN_MO8_BASE)
\r
16658 #define CAN_MO9 ((CAN_MO_TypeDef *) CAN_MO9_BASE)
\r
16659 #define CAN_MO10 ((CAN_MO_TypeDef *) CAN_MO10_BASE)
\r
16660 #define CAN_MO11 ((CAN_MO_TypeDef *) CAN_MO11_BASE)
\r
16661 #define CAN_MO12 ((CAN_MO_TypeDef *) CAN_MO12_BASE)
\r
16662 #define CAN_MO13 ((CAN_MO_TypeDef *) CAN_MO13_BASE)
\r
16663 #define CAN_MO14 ((CAN_MO_TypeDef *) CAN_MO14_BASE)
\r
16664 #define CAN_MO15 ((CAN_MO_TypeDef *) CAN_MO15_BASE)
\r
16665 #define CAN_MO16 ((CAN_MO_TypeDef *) CAN_MO16_BASE)
\r
16666 #define CAN_MO17 ((CAN_MO_TypeDef *) CAN_MO17_BASE)
\r
16667 #define CAN_MO18 ((CAN_MO_TypeDef *) CAN_MO18_BASE)
\r
16668 #define CAN_MO19 ((CAN_MO_TypeDef *) CAN_MO19_BASE)
\r
16669 #define CAN_MO20 ((CAN_MO_TypeDef *) CAN_MO20_BASE)
\r
16670 #define CAN_MO21 ((CAN_MO_TypeDef *) CAN_MO21_BASE)
\r
16671 #define CAN_MO22 ((CAN_MO_TypeDef *) CAN_MO22_BASE)
\r
16672 #define CAN_MO23 ((CAN_MO_TypeDef *) CAN_MO23_BASE)
\r
16673 #define CAN_MO24 ((CAN_MO_TypeDef *) CAN_MO24_BASE)
\r
16674 #define CAN_MO25 ((CAN_MO_TypeDef *) CAN_MO25_BASE)
\r
16675 #define CAN_MO26 ((CAN_MO_TypeDef *) CAN_MO26_BASE)
\r
16676 #define CAN_MO27 ((CAN_MO_TypeDef *) CAN_MO27_BASE)
\r
16677 #define CAN_MO28 ((CAN_MO_TypeDef *) CAN_MO28_BASE)
\r
16678 #define CAN_MO29 ((CAN_MO_TypeDef *) CAN_MO29_BASE)
\r
16679 #define CAN_MO30 ((CAN_MO_TypeDef *) CAN_MO30_BASE)
\r
16680 #define CAN_MO31 ((CAN_MO_TypeDef *) CAN_MO31_BASE)
\r
16681 #define CAN_MO32 ((CAN_MO_TypeDef *) CAN_MO32_BASE)
\r
16682 #define CAN_MO33 ((CAN_MO_TypeDef *) CAN_MO33_BASE)
\r
16683 #define CAN_MO34 ((CAN_MO_TypeDef *) CAN_MO34_BASE)
\r
16684 #define CAN_MO35 ((CAN_MO_TypeDef *) CAN_MO35_BASE)
\r
16685 #define CAN_MO36 ((CAN_MO_TypeDef *) CAN_MO36_BASE)
\r
16686 #define CAN_MO37 ((CAN_MO_TypeDef *) CAN_MO37_BASE)
\r
16687 #define CAN_MO38 ((CAN_MO_TypeDef *) CAN_MO38_BASE)
\r
16688 #define CAN_MO39 ((CAN_MO_TypeDef *) CAN_MO39_BASE)
\r
16689 #define CAN_MO40 ((CAN_MO_TypeDef *) CAN_MO40_BASE)
\r
16690 #define CAN_MO41 ((CAN_MO_TypeDef *) CAN_MO41_BASE)
\r
16691 #define CAN_MO42 ((CAN_MO_TypeDef *) CAN_MO42_BASE)
\r
16692 #define CAN_MO43 ((CAN_MO_TypeDef *) CAN_MO43_BASE)
\r
16693 #define CAN_MO44 ((CAN_MO_TypeDef *) CAN_MO44_BASE)
\r
16694 #define CAN_MO45 ((CAN_MO_TypeDef *) CAN_MO45_BASE)
\r
16695 #define CAN_MO46 ((CAN_MO_TypeDef *) CAN_MO46_BASE)
\r
16696 #define CAN_MO47 ((CAN_MO_TypeDef *) CAN_MO47_BASE)
\r
16697 #define CAN_MO48 ((CAN_MO_TypeDef *) CAN_MO48_BASE)
\r
16698 #define CAN_MO49 ((CAN_MO_TypeDef *) CAN_MO49_BASE)
\r
16699 #define CAN_MO50 ((CAN_MO_TypeDef *) CAN_MO50_BASE)
\r
16700 #define CAN_MO51 ((CAN_MO_TypeDef *) CAN_MO51_BASE)
\r
16701 #define CAN_MO52 ((CAN_MO_TypeDef *) CAN_MO52_BASE)
\r
16702 #define CAN_MO53 ((CAN_MO_TypeDef *) CAN_MO53_BASE)
\r
16703 #define CAN_MO54 ((CAN_MO_TypeDef *) CAN_MO54_BASE)
\r
16704 #define CAN_MO55 ((CAN_MO_TypeDef *) CAN_MO55_BASE)
\r
16705 #define CAN_MO56 ((CAN_MO_TypeDef *) CAN_MO56_BASE)
\r
16706 #define CAN_MO57 ((CAN_MO_TypeDef *) CAN_MO57_BASE)
\r
16707 #define CAN_MO58 ((CAN_MO_TypeDef *) CAN_MO58_BASE)
\r
16708 #define CAN_MO59 ((CAN_MO_TypeDef *) CAN_MO59_BASE)
\r
16709 #define CAN_MO60 ((CAN_MO_TypeDef *) CAN_MO60_BASE)
\r
16710 #define CAN_MO61 ((CAN_MO_TypeDef *) CAN_MO61_BASE)
\r
16711 #define CAN_MO62 ((CAN_MO_TypeDef *) CAN_MO62_BASE)
\r
16712 #define CAN_MO63 ((CAN_MO_TypeDef *) CAN_MO63_BASE)
\r
16713 #define VADC ((VADC_GLOBAL_TypeDef *) VADC_BASE)
\r
16714 #define VADC_G0 ((VADC_G_TypeDef *) VADC_G0_BASE)
\r
16715 #define VADC_G1 ((VADC_G_TypeDef *) VADC_G1_BASE)
\r
16716 #define VADC_G2 ((VADC_G_TypeDef *) VADC_G2_BASE)
\r
16717 #define VADC_G3 ((VADC_G_TypeDef *) VADC_G3_BASE)
\r
16718 #define DSD ((DSD_GLOBAL_TypeDef *) DSD_BASE)
\r
16719 #define DSD_CH0 ((DSD_CH_TypeDef *) DSD_CH0_BASE)
\r
16720 #define DSD_CH1 ((DSD_CH_TypeDef *) DSD_CH1_BASE)
\r
16721 #define DSD_CH2 ((DSD_CH_TypeDef *) DSD_CH2_BASE)
\r
16722 #define DSD_CH3 ((DSD_CH_TypeDef *) DSD_CH3_BASE)
\r
16723 #define DAC ((DAC_GLOBAL_TypeDef *) DAC_BASE)
\r
16724 #define CCU40 ((CCU4_GLOBAL_TypeDef *) CCU40_BASE)
\r
16725 #define CCU41 ((CCU4_GLOBAL_TypeDef *) CCU41_BASE)
\r
16726 #define CCU42 ((CCU4_GLOBAL_TypeDef *) CCU42_BASE)
\r
16727 #define CCU43 ((CCU4_GLOBAL_TypeDef *) CCU43_BASE)
\r
16728 #define CCU40_CC40 ((CCU4_CC4_TypeDef *) CCU40_CC40_BASE)
\r
16729 #define CCU40_CC41 ((CCU4_CC4_TypeDef *) CCU40_CC41_BASE)
\r
16730 #define CCU40_CC42 ((CCU4_CC4_TypeDef *) CCU40_CC42_BASE)
\r
16731 #define CCU40_CC43 ((CCU4_CC4_TypeDef *) CCU40_CC43_BASE)
\r
16732 #define CCU41_CC40 ((CCU4_CC4_TypeDef *) CCU41_CC40_BASE)
\r
16733 #define CCU41_CC41 ((CCU4_CC4_TypeDef *) CCU41_CC41_BASE)
\r
16734 #define CCU41_CC42 ((CCU4_CC4_TypeDef *) CCU41_CC42_BASE)
\r
16735 #define CCU41_CC43 ((CCU4_CC4_TypeDef *) CCU41_CC43_BASE)
\r
16736 #define CCU42_CC40 ((CCU4_CC4_TypeDef *) CCU42_CC40_BASE)
\r
16737 #define CCU42_CC41 ((CCU4_CC4_TypeDef *) CCU42_CC41_BASE)
\r
16738 #define CCU42_CC42 ((CCU4_CC4_TypeDef *) CCU42_CC42_BASE)
\r
16739 #define CCU42_CC43 ((CCU4_CC4_TypeDef *) CCU42_CC43_BASE)
\r
16740 #define CCU43_CC40 ((CCU4_CC4_TypeDef *) CCU43_CC40_BASE)
\r
16741 #define CCU43_CC41 ((CCU4_CC4_TypeDef *) CCU43_CC41_BASE)
\r
16742 #define CCU43_CC42 ((CCU4_CC4_TypeDef *) CCU43_CC42_BASE)
\r
16743 #define CCU43_CC43 ((CCU4_CC4_TypeDef *) CCU43_CC43_BASE)
\r
16744 #define CCU80 ((CCU8_GLOBAL_TypeDef *) CCU80_BASE)
\r
16745 #define CCU81 ((CCU8_GLOBAL_TypeDef *) CCU81_BASE)
\r
16746 #define CCU80_CC80 ((CCU8_CC8_TypeDef *) CCU80_CC80_BASE)
\r
16747 #define CCU80_CC81 ((CCU8_CC8_TypeDef *) CCU80_CC81_BASE)
\r
16748 #define CCU80_CC82 ((CCU8_CC8_TypeDef *) CCU80_CC82_BASE)
\r
16749 #define CCU80_CC83 ((CCU8_CC8_TypeDef *) CCU80_CC83_BASE)
\r
16750 #define CCU81_CC80 ((CCU8_CC8_TypeDef *) CCU81_CC80_BASE)
\r
16751 #define CCU81_CC81 ((CCU8_CC8_TypeDef *) CCU81_CC81_BASE)
\r
16752 #define CCU81_CC82 ((CCU8_CC8_TypeDef *) CCU81_CC82_BASE)
\r
16753 #define CCU81_CC83 ((CCU8_CC8_TypeDef *) CCU81_CC83_BASE)
\r
16754 #define HRPWM0 ((HRPWM0_Type *) HRPWM0_BASE)
\r
16755 #define HRPWM0_CSG0 ((HRPWM0_CSG_Type *) HRPWM0_CSG0_BASE)
\r
16756 #define HRPWM0_CSG1 ((HRPWM0_CSG_Type *) HRPWM0_CSG1_BASE)
\r
16757 #define HRPWM0_CSG2 ((HRPWM0_CSG_Type *) HRPWM0_CSG2_BASE)
\r
16758 #define HRPWM0_HRC0 ((HRPWM0_HRC_Type *) HRPWM0_HRC0_BASE)
\r
16759 #define HRPWM0_HRC1 ((HRPWM0_HRC_Type *) HRPWM0_HRC1_BASE)
\r
16760 #define HRPWM0_HRC2 ((HRPWM0_HRC_Type *) HRPWM0_HRC2_BASE)
\r
16761 #define HRPWM0_HRC3 ((HRPWM0_HRC_Type *) HRPWM0_HRC3_BASE)
\r
16762 #define POSIF0 ((POSIF_GLOBAL_TypeDef *) POSIF0_BASE)
\r
16763 #define POSIF1 ((POSIF_GLOBAL_TypeDef *) POSIF1_BASE)
\r
16764 #define PORT0 ((PORT0_Type *) PORT0_BASE)
\r
16765 #define PORT1 ((PORT1_Type *) PORT1_BASE)
\r
16766 #define PORT2 ((PORT2_Type *) PORT2_BASE)
\r
16767 #define PORT3 ((PORT3_Type *) PORT3_BASE)
\r
16768 #define PORT4 ((PORT4_Type *) PORT4_BASE)
\r
16769 #define PORT5 ((PORT5_Type *) PORT5_BASE)
\r
16770 #define PORT14 ((PORT14_Type *) PORT14_BASE)
\r
16771 #define PORT15 ((PORT15_Type *) PORT15_BASE)
\r
16774 /** @} */ /* End of group Device_Peripheral_Registers */
\r
16775 /** @} */ /* End of group XMC4400 */
\r
16776 /** @} */ /* End of group Infineon */
\r
16778 #ifdef __cplusplus
\r
16783 #endif /* XMC4400_H */
\r
projects / freertos / blob