1 /**************************************************************************//**
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2 * @file system_XMC4500.c
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3 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
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4 * for the Infineon XMC4500 Device Series
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5 * @version V3.0.1 Alpha
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6 * @date 17. September 2012
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9 * Copyright (C) 2011 ARM Limited. All rights reserved.
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12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
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13 * processor based microcontrollers. This file can be freely distributed
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14 * within development tools that are supporting such ARM based processors.
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17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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23 ******************************************************************************/
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25 #include "system_XMC4500.h"
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26 #include <XMC4500.h>
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28 /*----------------------------------------------------------------------------
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29 Clock Variable definitions
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30 *----------------------------------------------------------------------------*/
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31 /*!< System Clock Frequency (Core Clock)*/
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32 uint32_t SystemCoreClock;
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34 /* clock definitions, do not modify! */
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35 #define SCU_CLOCK_CRYSTAL 1
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36 #define SCU_CLOCK_BACK_UP_FACTORY 2
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37 #define SCU_CLOCK_BACK_UP_AUTOMATIC 3
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40 #define HIB_CLOCK_FOSI 1
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41 #define HIB_CLOCK_OSCULP 2
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47 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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52 /*--------------------- Watchdog Configuration -------------------------------
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54 // <e> Watchdog Configuration
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55 // <o1.0> Disable Watchdog
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60 #define WDTENB_nVal 0x00000001
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62 /*--------------------- CLOCK Configuration -------------------------------
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64 // <e> Main Clock Configuration
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65 // <o1.0..1> CPU clock divider
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66 // <0=> fCPU = fSYS
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67 // <1=> fCPU = fSYS / 2
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68 // <o2.0..1> Peripheral Bus clock divider
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70 // <1=> fPB = fCPU / 2
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71 // <o3.0..1> CCU Bus clock divider
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73 // <1=> fCCU = fCPU / 2
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79 #define SCU_CLOCK_SETUP 1
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80 #define SCU_CPUCLKCR_DIV 0x00000000
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81 #define SCU_PBCLKCR_DIV 0x00000000
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82 #define SCU_CCUCLKCR_DIV 0x00000000
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83 /* not avalible in config wizzard*/
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85 * mandatory clock parameters **************************************************
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87 * source for clock generation
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88 * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
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90 **************************************************************************************/
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91 // Selection of imput lock for PLL
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92 /*************************************************************************************/
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93 #define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
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94 //#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY
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95 //#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC
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97 /*************************************************************************************/
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98 // Standby clock selection for Backup clock source trimming
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99 /*************************************************************************************/
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100 #define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP
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101 //#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI
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103 /*************************************************************************************/
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104 // Global clock parameters
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105 /*************************************************************************************/
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106 #define CLOCK_FSYS 120000000
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107 #define CLOCK_CRYSTAL_FREQUENCY 12000000
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108 #define CLOCK_BACK_UP 24000000
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110 /*************************************************************************************/
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111 /* OSC_HP setup parameters */
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112 /*************************************************************************************/
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113 #define SCU_OSC_HP_MODE 0xF0
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114 #define SCU_OSCHPWDGDIV 2
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116 /*************************************************************************************/
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117 /* MAIN PLL setup parameters */
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118 /*************************************************************************************/
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119 //Divider settings for external crystal @ 12 MHz
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120 /*************************************************************************************/
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121 #define SCU_PLL_K1DIV 1
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122 #define SCU_PLL_K2DIV 3
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123 #define SCU_PLL_PDIV 1
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124 #define SCU_PLL_NDIV 79
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126 /*************************************************************************************/
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127 //Divider settings for use of backup clock source trimmed
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128 /*************************************************************************************/
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129 //#define SCU_PLL_K1DIV 1
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130 //#define SCU_PLL_K2DIV 3
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131 //#define SCU_PLL_PDIV 3
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132 //#define SCU_PLL_NDIV 79
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133 /*************************************************************************************/
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135 /*--------------------- USB CLOCK Configuration ---------------------------
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137 // <e> USB Clock Configuration
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143 #define SCU_USB_CLOCK_SETUP 0
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144 /* not avalible in config wizzard*/
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145 #define SCU_USBPLL_PDIV 0
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146 #define SCU_USBPLL_NDIV 31
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147 #define SCU_USBDIV 3
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149 /*--------------------- Flash Wait State Configuration -------------------------------
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151 // <e> Flash Wait State Configuration
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152 // <o1.0..3> Flash Wait State
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161 #define PMU_FLASH 1
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162 #define PMU_FLASH_WS 0x00000000
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165 /*--------------------- CLOCKOUT Configuration -------------------------------
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167 // <e> Clock OUT Configuration
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168 // <o1.0..1> Clockout Source Selection
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169 // <0=> System Clock
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170 // <2=> Divided value of USB PLL output
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171 // <3=> Divided value of PLL Clock
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172 // <o2.0..4> Clockout divider <1-10><#-1>
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173 // <o3.0..1> Clockout Pin Selection
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182 #define SCU_CLOCKOUT_SETUP 0
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183 #define SCU_CLOCKOUT_SOURCE 0x00000003
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184 #define SCU_CLOCKOUT_DIV 0x00000009
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185 #define SCU_CLOCKOUT_PIN 0x00000001
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187 /*----------------------------------------------------------------------------
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188 Clock Variable definitions
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189 *----------------------------------------------------------------------------*/
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190 /*!< System Clock Frequency (Core Clock)*/
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191 #if SCU_CLOCK_SETUP
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192 uint32_t SystemCoreClock = CLOCK_FSYS;
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194 uint32_t SystemCoreClock = CLOCK_BACK_UP;
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197 /*----------------------------------------------------------------------------
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198 static functions declarations
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199 *----------------------------------------------------------------------------*/
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200 #if (SCU_CLOCK_SETUP == 1)
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201 static int SystemClockSetup(void);
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204 #if (SCU_USB_CLOCK_SETUP == 1)
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205 static int USBClockSetup(void);
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210 * @brief Setup the microcontroller system.
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211 * Initialize the PLL and update the
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212 * SystemCoreClock variable.
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216 void SystemInit(void)
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220 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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221 SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
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222 (3UL << 11*2) ); /* set CP11 Full Access */
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225 /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
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226 SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
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228 /* Setup the WDT */
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231 WDT->CTR &= ~WDTENB_nVal;
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235 /* Setup the Flash Wait State */
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237 temp = FLASH0->FCON;
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238 temp &= ~FLASH_FCON_WSPFLASH_Msk;
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239 temp |= PMU_FLASH_WS+3;
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240 FLASH0->FCON = temp;
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244 /* Setup the clockout */
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245 #if SCU_CLOCKOUT_SETUP
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247 SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
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248 /*set PLL div for clkout */
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249 SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;
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251 if (SCU_CLOCKOUT_PIN) {
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252 PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
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253 PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
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254 //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */
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257 PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
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258 //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */
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264 /* Setup the System clock */
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265 #if SCU_CLOCK_SETUP
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266 SystemClockSetup();
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269 /*----------------------------------------------------------------------------
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270 Clock Variable definitions
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271 *----------------------------------------------------------------------------*/
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272 SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
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275 /* Setup the USB PL */
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276 #if SCU_USB_CLOCK_SETUP
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286 * @brief Update SystemCoreClock according to Clock Register Values
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291 void SystemCoreClockUpdate(void)
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295 unsigned int K2DIV;
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296 unsigned int long VCO;
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299 /*----------------------------------------------------------------------------
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300 Clock Variable definitions
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301 *----------------------------------------------------------------------------*/
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302 if (SCU_CLK->SYSCLKCR == 0x00010000)
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304 if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
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305 /* check if PLL is locked */
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306 /* read back divider settings */
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307 PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
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308 NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
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309 K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
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311 if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
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312 /* the selected clock is the Backup clock fofi */
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313 VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
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314 SystemCoreClock = VCO/K2DIV;
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315 /* in case the sysclock div is used */
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316 SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
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321 /* the selected clock is the PLL external oscillator */
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322 VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
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323 SystemCoreClock = VCO/K2DIV;
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324 /* in case the sysclock div is used */
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325 SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
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333 SystemCoreClock = CLOCK_BACK_UP;
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346 #if (SCU_CLOCK_SETUP == 1)
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347 static int SystemClockSetup(void)
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350 unsigned int long VCO;
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351 int stepping_K2DIV;
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353 /* this weak function enables DAVE3 clock App usage */
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354 if(AllowPLLInitByStartup()){
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356 /* check if PLL is switched on */
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357 if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
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358 /* enable PLL first */
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359 SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
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363 /* Enable OSC_HP if not already on*/
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364 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
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366 /********************************************************************************************************************/
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367 /* Use external crystal for PLL clock input */
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368 /********************************************************************************************************************/
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370 if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
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371 SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
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372 /* setup OSC WDG devider */
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373 SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
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374 /* select external OSC as PLL input */
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375 SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
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376 /* restart OSC Watchdog */
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377 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
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379 /* Timeout for wait loop ~150ms */
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380 /********************************/
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381 SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
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382 SysTick->VAL = 0; /* Load the SysTick Counter Value */
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383 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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384 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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387 ;/* wait for ~150ms */
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388 }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
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390 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
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391 if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
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392 return(0);/* Return Error */
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396 else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
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398 /********************************************************************************************************************/
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399 /* Use factory trimming Back-up clock for PLL clock input */
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400 /********************************************************************************************************************/
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401 /* PLL Back up clock selected */
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402 SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
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405 else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
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407 /********************************************************************************************************************/
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408 /* Use automatic trimming Back-up clock for PLL clock input */
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409 /********************************************************************************************************************/
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410 /* check for HIB Domain enabled */
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411 if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
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412 SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
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414 /* check for HIB Domain is not in reset state */
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415 if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
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416 SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
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418 /* PLL Back up clock selected */
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419 SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
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421 if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
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423 /****************************************************************************************************************/
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424 /* Use fOSI as source of the standby clock */
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425 /****************************************************************************************************************/
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426 SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
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428 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
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429 for(temp=0;temp<=0xFFFF;temp++);
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431 SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
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433 else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
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435 /****************************************************************************************************************/
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436 /* Use fULP as source of the standby clock */
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437 /****************************************************************************************************************/
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438 /*check OSCUL if running correct*/
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439 if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
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441 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
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443 SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
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444 /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
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445 /* select OSCUL clock for RTC*/
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446 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
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447 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
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448 /*enable OSCULP WDG Alarm Enable*/
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449 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
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450 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
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451 /*wait now for clock is stable */
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454 SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
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455 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
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456 for(temp=0;temp<=0xFFFF;temp++);
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458 while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
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460 SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
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461 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
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463 // now OSCULP is running and can be used
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464 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
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465 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
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467 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
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468 /*TRIAL for delay loop*/
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469 for(temp=0;temp<=0xFFFF;temp++);
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471 SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
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472 /*TRIAL for delay loop*/
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473 for(temp=0;temp<=0xFFFF;temp++);
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478 /********************************************************************************************************************/
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479 /* Setup and look the main PLL */
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480 /********************************************************************************************************************/
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482 if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
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483 /* Systen is still running from internal clock */
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484 /* select FOFI as system clock */
\r
485 if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
\r
488 /*calulation for stepping*/
\r
489 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
\r
490 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
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491 VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
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493 stepping_K2DIV = (VCO/24000000)-1;
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494 /* Go to bypass the Main PLL */
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495 SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
\r
496 /* disconnect OSC_HP to PLL */
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497 SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
\r
498 /* Setup devider settings for main PLL */
\r
499 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
\r
500 /* we may have to set OSCDISCDIS */
\r
501 SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
\r
502 /* connect OSC_HP to PLL */
\r
503 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
\r
504 /* restart PLL Lock detection */
\r
505 SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
\r
506 /* wait for PLL Lock */
\r
507 /* setup time out loop */
\r
508 /* Timeout for wait loo ~150ms */
\r
509 /********************************/
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510 SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
\r
511 SysTick->VAL = 0; /* Load the SysTick Counter Value */
\r
512 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
513 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
515 while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
\r
516 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
\r
518 if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
\r
520 /* Go back to the Main PLL */
\r
521 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
\r
526 /*********************************************************
\r
527 here we need to setup the system clock divider
\r
528 *********************************************************/
\r
530 SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
\r
531 SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
\r
532 SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
\r
535 /* Switch system clock to PLL */
\r
536 SCU_CLK->SYSCLKCR |= 0x00010000;
\r
538 /* we may have to reset OSCDISCDIS */
\r
539 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
\r
542 /*********************************************************/
\r
543 /* Delay for next K2 step ~50µs */
\r
544 /*********************************************************/
\r
545 SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
\r
546 SysTick->VAL = 0; /* Load the SysTick Counter Value */
\r
547 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
548 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
550 while (SysTick->VAL >= 100); /* wait for ~50µs */
\r
551 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
\r
552 /*********************************************************/
\r
554 /*********************************************************
\r
555 here the ramp up of the system clock starts FSys < 60MHz
\r
556 *********************************************************/
\r
557 if (CLOCK_FSYS > 60000000){
\r
558 /*calulation for stepping*/
\r
559 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
\r
560 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
\r
561 VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
\r
563 stepping_K2DIV = (VCO/60000000)-1;
\r
565 /* Setup devider settings for main PLL */
\r
566 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
\r
570 /* Setup devider settings for main PLL */
\r
571 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
\r
572 SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
\r
576 /*********************************************************/
\r
577 /* Delay for next K2 step ~50µs */
\r
578 /*********************************************************/
\r
579 SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
\r
580 SysTick->VAL = 0; /* Load the SysTick Counter Value */
\r
581 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
582 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
584 while (SysTick->VAL >= 100); /* wait for ~50µs */
\r
585 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
\r
586 /********************************/
\r
588 /*********************************************************
\r
589 here the ramp up of the system clock starts FSys < 90MHz
\r
590 *********************************************************/
\r
591 if (CLOCK_FSYS > 90000000){
\r
592 /*calulation for stepping*/
\r
593 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
\r
594 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
\r
595 VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
\r
597 stepping_K2DIV = (VCO/90000000)-1;
\r
599 /* Setup devider settings for main PLL */
\r
600 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
\r
604 /* Setup devider settings for main PLL */
\r
605 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
\r
606 SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
\r
610 /*********************************************************/
\r
611 /* Delay for next K2 step ~50µs */
\r
612 /*********************************************************/
\r
613 SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
\r
614 SysTick->VAL = 0; /* Load the SysTick Counter Value */
\r
615 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
616 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
618 while (SysTick->VAL >= 100); /* wait for ~50µs */
\r
619 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
\r
620 /********************************/
\r
622 /* Setup devider settings for main PLL */
\r
623 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
\r
625 SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
\r
627 }/* end this weak function enables DAVE3 clock App usage */
\r
639 #if (SCU_USB_CLOCK_SETUP == 1)
\r
640 static int USBClockSetup(void)
\r
642 /* this weak function enables DAVE3 clock App usage */
\r
643 if(AllowPLLInitByStartup()){
\r
645 /* check if PLL is switched on */
\r
646 if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
\r
647 /* enable PLL first */
\r
648 SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
\r
651 /* check and if not already running enable OSC_HP */
\r
652 if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
\r
653 /* check if Main PLL is switched on for OSC WD*/
\r
654 if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
\r
655 /* enable PLL first */
\r
656 SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
\r
658 SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
\r
659 /* setup OSC WDG devider */
\r
660 SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
\r
661 /* restart OSC Watchdog */
\r
662 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
\r
664 /* Timeout for wait loop ~150ms */
\r
665 /********************************/
\r
666 SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
\r
667 SysTick->VAL = 0; /* Load the SysTick Counter Value */
\r
668 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
669 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
672 ;/* wait for ~150ms */
\r
673 }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
\r
675 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
\r
676 if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
\r
677 return(0);/* Return Error */
\r
682 /* Setup USB PLL */
\r
683 /* Go to bypass the Main PLL */
\r
684 SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
\r
685 /* disconnect OSC_FI to PLL */
\r
686 SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
\r
687 /* Setup devider settings for main PLL */
\r
688 SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
\r
689 /* Setup USBDIV settings USB clock */
\r
690 SCU_CLK->USBCLKCR = SCU_USBDIV;
\r
691 /* we may have to set OSCDISCDIS */
\r
692 SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
\r
693 /* connect OSC_FI to PLL */
\r
694 SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
\r
695 /* restart PLL Lock detection */
\r
696 SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
\r
697 /* wait for PLL Lock */
\r
698 while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
\r
700 }/* end this weak function enables DAVE3 clock App usage */
\r