1 ;*****************************************************************************/
\r
2 ; * @file startup_XMC4400.s
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3 ; * @brief CMSIS Cortex-M4 Core Device Startup File for
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4 ; * Infineon XMC4400 Device Series
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6 ; * @date 05. February 2013
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9 ; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
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12 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M
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13 ; * processor based microcontrollers. This file can be freely distributed
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14 ; * within development tools that are supporting such ARM based processors.
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17 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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18 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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19 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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20 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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21 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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23 ; ******************************************************************************/
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25 ;/* ********************* Version History *********************************** */
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26 ;/* ***************************************************************************
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27 ; V0.2 , August 2012, First version
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28 ; V1.0 , February 2013, FIX for CPU prefetch bug implemented
\r
29 ;**************************************************************************** */
\r
32 ;* <<< Use Configuration Wizard in Context Menu >>>
\r
34 ; Amount of memory (in bytes) allocated for Stack
\r
35 ; Tailor this value to your application needs
\r
36 ; <h> Stack Configuration
\r
37 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
\r
40 Stack_Size EQU 0x00000400
\r
42 AREA STACK, NOINIT, READWRITE, ALIGN=3
\r
43 Stack_Mem SPACE Stack_Size
\r
47 ; <h> Heap Configuration
\r
48 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
\r
51 Heap_Size EQU 0x00000200
\r
53 AREA HEAP, NOINIT, READWRITE, ALIGN=3
\r
55 Heap_Mem SPACE Heap_Size
\r
62 ;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
\r
64 ; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
\r
65 ; * A veneer defined below will first
\r
66 ; * be executed which in turn branches to the final exception handler.
\r
68 ; * In addition to defining the veneers, the vector table must for these buggy
\r
69 ; * devices contain the veneers.
\r
72 ;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define
\r
73 ;or use define below
\r
74 GBLL WORKAROUND_PMU_CM001
\r
76 ;/* A macro to setup a vector table entry based on STEP ID */
\r
77 IF :DEF:WORKAROUND_PMU_CM001
\r
80 DCD $Handler._Veneer
\r
89 ;/* A macro to ease definition of the various handlers based on STEP ID */
\r
90 IF :DEF:WORKAROUND_PMU_CM001
\r
92 ;/* First define the final exception handler */
\r
94 ExcpHandler $Handler_Func
\r
97 EXPORT $Handler_Func [WEAK]
\r
101 ;/* And then define a veneer that will branch to the final excp handler */
\r
102 $Handler_Func._Veneer\
\r
104 EXPORT $Handler_Func._Veneer [WEAK]
\r
105 LDR R0, =$Handler_Func
\r
116 ;/* No prefetch bug, hence define only the final exception handler */
\r
118 ExcpHandler $Handler_Func
\r
121 EXPORT $Handler_Func [WEAK]
\r
127 ;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
\r
130 ;* ================== START OF VECTOR TABLE DEFINITION ====================== */
\r
131 ;* Vector Table - This gets programed into VTOR register */
\r
132 AREA RESET, DATA, READONLY
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134 EXPORT __Vectors_End
\r
135 EXPORT __Vectors_Size
\r
140 DCD __initial_sp ; Top of Stack
\r
141 DCD Reset_Handler ; Reset Handler
\r
143 ExcpVector NMI_Handler ; NMI Handler
\r
144 ExcpVector HardFault_Handler ; Hard Fault Handler
\r
145 ExcpVector MemManage_Handler ; MPU Fault Handler
\r
146 ExcpVector BusFault_Handler ; Bus Fault Handler
\r
147 ExcpVector UsageFault_Handler ; Usage Fault Handler
\r
152 ExcpVector SVC_Handler ; SVCall Handler
\r
153 ExcpVector DebugMon_Handler ; Debug Monitor Handler
\r
155 DCD PendSV_Handler ; PendSV Handler
\r
156 ExcpVector SysTick_Handler ; SysTick Handler
\r
158 ; Interrupt Handlers for Service Requests (SR) from XMC4400 Peripherals
\r
159 ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0
\r
160 ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0
\r
161 ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1
\r
162 ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2
\r
163 ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3
\r
164 ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0
\r
165 ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1
\r
166 ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2
\r
167 ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3
\r
171 ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0
\r
173 ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
\r
174 ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
\r
175 ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
\r
176 ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
\r
177 ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
\r
178 ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
\r
179 ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
\r
180 ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
\r
181 ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
\r
182 ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
\r
183 ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
\r
184 ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
\r
185 ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0
\r
186 ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1
\r
187 ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2
\r
188 ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3
\r
189 ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0
\r
190 ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1
\r
191 ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2
\r
192 ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3
\r
193 ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD0_0
\r
194 ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD0_1
\r
195 ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD0_2
\r
196 ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD0_3
\r
197 ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD0_4
\r
198 ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD0_5
\r
199 ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD0_6
\r
200 ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD0_7
\r
201 ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0
\r
202 ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1
\r
203 ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0
\r
204 ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1
\r
205 ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2
\r
206 ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3
\r
207 ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0
\r
208 ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1
\r
209 ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2
\r
210 ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3
\r
211 ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0
\r
212 ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1
\r
213 ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2
\r
214 ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3
\r
215 ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0
\r
216 ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1
\r
217 ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2
\r
218 ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3
\r
219 ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0
\r
220 ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1
\r
221 ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2
\r
222 ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3
\r
223 ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0
\r
224 ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1
\r
225 ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2
\r
226 ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3
\r
227 ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
\r
228 ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
\r
229 ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0
\r
230 ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1
\r
231 ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0
\r
232 ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1
\r
233 ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2
\r
234 ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3
\r
235 ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0
\r
236 ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1
\r
237 ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2
\r
238 ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3
\r
239 ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4
\r
240 ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5
\r
241 ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6
\r
242 ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7
\r
243 ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0
\r
244 ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1
\r
245 ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2
\r
246 ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3
\r
247 ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4
\r
248 ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5
\r
249 ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0
\r
250 ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1
\r
251 ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2
\r
252 ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3
\r
253 ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4
\r
254 ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5
\r
261 ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
\r
263 ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0
\r
264 ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
\r
266 ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0
\r
267 ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0
\r
273 __Vectors_Size EQU __Vectors_End - __Vectors
\r
275 ;* ================== END OF VECTOR TABLE DEFINITION ======================= */
\r
277 ;* ================== START OF VECTOR ROUTINES ============================= */
\r
279 AREA |.text|, CODE, READONLY
\r
281 ;* Reset Handler */
\r
283 EXPORT Reset_Handler [WEAK]
\r
287 ; Remap vector table
\r
289 LDR R1, =0xE000ED08 ;*VTOR register
\r
292 ;* C routines are likely to be called. Setup the stack now
\r
293 LDR SP,=__initial_sp
\r
295 LDR R0, = SystemInit
\r
298 ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
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299 ;weakly defined here though for a potential override.
\r
301 LDR R0, = SystemInit_DAVE3
\r
304 ;* Reset stack pointer before zipping off to user application
\r
305 LDR SP,=__initial_sp
\r
316 ;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
\r
320 ;/* Default exception Handlers - Users may override this default functionality by
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321 ; defining handlers of the same name in their C code */
\r
323 ExcpHandler NMI_Handler
\r
324 ExcpHandler HardFault_Handler
\r
325 ExcpHandler MemManage_Handler
\r
326 ExcpHandler BusFault_Handler
\r
327 ExcpHandler UsageFault_Handler
\r
328 ExcpHandler SVC_Handler
\r
329 ExcpHandler DebugMon_Handler
\r
330 ExcpHandler PendSV_Handler
\r
331 ExcpHandler SysTick_Handler
\r
333 ;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
\r
335 ;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
\r
338 ExcpHandler SCU_0_IRQHandler
\r
339 ExcpHandler ERU0_0_IRQHandler
\r
340 ExcpHandler ERU0_1_IRQHandler
\r
341 ExcpHandler ERU0_2_IRQHandler
\r
342 ExcpHandler ERU0_3_IRQHandler
\r
343 ExcpHandler ERU1_0_IRQHandler
\r
344 ExcpHandler ERU1_1_IRQHandler
\r
345 ExcpHandler ERU1_2_IRQHandler
\r
346 ExcpHandler ERU1_3_IRQHandler
\r
347 ExcpHandler PMU0_0_IRQHandler
\r
348 ExcpHandler VADC0_C0_0_IRQHandler
\r
349 ExcpHandler VADC0_C0_1_IRQHandler
\r
350 ExcpHandler VADC0_C0_2_IRQHandler
\r
351 ExcpHandler VADC0_C0_3_IRQHandler
\r
352 ExcpHandler VADC0_G0_0_IRQHandler
\r
353 ExcpHandler VADC0_G0_1_IRQHandler
\r
354 ExcpHandler VADC0_G0_2_IRQHandler
\r
355 ExcpHandler VADC0_G0_3_IRQHandler
\r
356 ExcpHandler VADC0_G1_0_IRQHandler
\r
357 ExcpHandler VADC0_G1_1_IRQHandler
\r
358 ExcpHandler VADC0_G1_2_IRQHandler
\r
359 ExcpHandler VADC0_G1_3_IRQHandler
\r
360 ExcpHandler VADC0_G2_0_IRQHandler
\r
361 ExcpHandler VADC0_G2_1_IRQHandler
\r
362 ExcpHandler VADC0_G2_2_IRQHandler
\r
363 ExcpHandler VADC0_G2_3_IRQHandler
\r
364 ExcpHandler VADC0_G3_0_IRQHandler
\r
365 ExcpHandler VADC0_G3_1_IRQHandler
\r
366 ExcpHandler VADC0_G3_2_IRQHandler
\r
367 ExcpHandler VADC0_G3_3_IRQHandler
\r
368 ExcpHandler DSD0_0_IRQHandler
\r
369 ExcpHandler DSD0_1_IRQHandler
\r
370 ExcpHandler DSD0_2_IRQHandler
\r
371 ExcpHandler DSD0_3_IRQHandler
\r
372 ExcpHandler DSD0_4_IRQHandler
\r
373 ExcpHandler DSD0_5_IRQHandler
\r
374 ExcpHandler DSD0_6_IRQHandler
\r
375 ExcpHandler DSD0_7_IRQHandler
\r
376 ExcpHandler DAC0_0_IRQHandler
\r
377 ExcpHandler DAC0_1_IRQHandler
\r
378 ExcpHandler CCU40_0_IRQHandler
\r
379 ExcpHandler CCU40_1_IRQHandler
\r
380 ExcpHandler CCU40_2_IRQHandler
\r
381 ExcpHandler CCU40_3_IRQHandler
\r
382 ExcpHandler CCU41_0_IRQHandler
\r
383 ExcpHandler CCU41_1_IRQHandler
\r
384 ExcpHandler CCU41_2_IRQHandler
\r
385 ExcpHandler CCU41_3_IRQHandler
\r
386 ExcpHandler CCU42_0_IRQHandler
\r
387 ExcpHandler CCU42_1_IRQHandler
\r
388 ExcpHandler CCU42_2_IRQHandler
\r
389 ExcpHandler CCU42_3_IRQHandler
\r
390 ExcpHandler CCU43_0_IRQHandler
\r
391 ExcpHandler CCU43_1_IRQHandler
\r
392 ExcpHandler CCU43_2_IRQHandler
\r
393 ExcpHandler CCU43_3_IRQHandler
\r
394 ExcpHandler CCU80_0_IRQHandler
\r
395 ExcpHandler CCU80_1_IRQHandler
\r
396 ExcpHandler CCU80_2_IRQHandler
\r
397 ExcpHandler CCU80_3_IRQHandler
\r
398 ExcpHandler CCU81_0_IRQHandler
\r
399 ExcpHandler CCU81_1_IRQHandler
\r
400 ExcpHandler CCU81_2_IRQHandler
\r
401 ExcpHandler CCU81_3_IRQHandler
\r
402 ExcpHandler POSIF0_0_IRQHandler
\r
403 ExcpHandler POSIF0_1_IRQHandler
\r
404 ExcpHandler POSIF1_0_IRQHandler
\r
405 ExcpHandler POSIF1_1_IRQHandler
\r
406 ExcpHandler HRPWM_0_IRQHandler
\r
407 ExcpHandler HRPWM_1_IRQHandler
\r
408 ExcpHandler HRPWM_2_IRQHandler
\r
409 ExcpHandler HRPWM_3_IRQHandler
\r
410 ExcpHandler CAN0_0_IRQHandler
\r
411 ExcpHandler CAN0_1_IRQHandler
\r
412 ExcpHandler CAN0_2_IRQHandler
\r
413 ExcpHandler CAN0_3_IRQHandler
\r
414 ExcpHandler CAN0_4_IRQHandler
\r
415 ExcpHandler CAN0_5_IRQHandler
\r
416 ExcpHandler CAN0_6_IRQHandler
\r
417 ExcpHandler CAN0_7_IRQHandler
\r
418 ExcpHandler USIC0_0_IRQHandler
\r
419 ExcpHandler USIC0_1_IRQHandler
\r
420 ExcpHandler USIC0_2_IRQHandler
\r
421 ExcpHandler USIC0_3_IRQHandler
\r
422 ExcpHandler USIC0_4_IRQHandler
\r
423 ExcpHandler USIC0_5_IRQHandler
\r
424 ExcpHandler USIC1_0_IRQHandler
\r
425 ExcpHandler USIC1_1_IRQHandler
\r
426 ExcpHandler USIC1_2_IRQHandler
\r
427 ExcpHandler USIC1_3_IRQHandler
\r
428 ExcpHandler USIC1_4_IRQHandler
\r
429 ExcpHandler USIC1_5_IRQHandler
\r
430 ExcpHandler LEDTS0_0_IRQHandler
\r
431 ExcpHandler FCE0_0_IRQHandler
\r
432 ExcpHandler GPDMA0_0_IRQHandler
\r
433 ExcpHandler USB0_0_IRQHandler
\r
434 ExcpHandler ETH0_0_IRQHandler
\r
436 ;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
\r
438 ;* Definition of the default weak SystemInit_DAVE3 function.
\r
439 ;* This function will be called by the CMSIS SystemInit function.
\r
440 ;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
\r
441 ;* which will overule this weak definition
\r
442 SystemInit_DAVE3 PROC
\r
443 EXPORT SystemInit_DAVE3 [WEAK]
\r
448 ;* Definition of the default weak DAVE3 function for clock App usage.
\r
449 ;* AllowPLLInitByStartup Handler */
\r
450 AllowPLLInitByStartup PROC
\r
451 EXPORT AllowPLLInitByStartup [WEAK]
\r
458 ;*******************************************************************************
\r
459 ; User Stack and Heap initialization
\r
460 ;*******************************************************************************
\r
463 EXPORT __initial_sp
\r
465 EXPORT __heap_limit
\r
469 IMPORT __use_two_region_memory
\r
470 EXPORT __user_initial_stackheap
\r
472 __user_initial_stackheap
\r
475 LDR R1, =(Stack_Mem + Stack_Size)
\r
476 LDR R2, = (Heap_Mem + Heap_Size)
\r
477 LDR R3, = Stack_Mem
\r
486 ;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****
\r