1 ;*****************************************************************************/
\r
2 ; * @file startup_XMC4500.s
\r
3 ; * @brief CMSIS Cortex-M4 Core Device Startup File for
\r
4 ; * Infineon XMC4500 Device Series
\r
6 ; * @date 05. February 2013
\r
9 ; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
\r
12 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M
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13 ; * processor based microcontrollers. This file can be freely distributed
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14 ; * within development tools that are supporting such ARM based processors.
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17 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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18 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
\r
19 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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20 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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21 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
\r
23 ; ******************************************************************************/
\r
25 ;/* ********************* Version History *********************************** */
\r
26 ;/* ***************************************************************************
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27 ; V1.00 , February 2012, First version
\r
28 ; V1.10 , August 2012, Adding Dave3 init function call
\r
29 ; V1.20 , February 2013, FIX for CPU prefetch bug implemented
\r
30 ;**************************************************************************** */
\r
33 ;* <<< Use Configuration Wizard in Context Menu >>>
\r
35 ; Amount of memory (in bytes) allocated for Stack
\r
36 ; Tailor this value to your application needs
\r
37 ; <h> Stack Configuration
\r
38 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
\r
41 Stack_Size EQU 0x00000400
\r
43 AREA STACK, NOINIT, READWRITE, ALIGN=3
\r
44 Stack_Mem SPACE Stack_Size
\r
48 ; <h> Heap Configuration
\r
49 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
\r
52 Heap_Size EQU 0x00000200
\r
54 AREA HEAP, NOINIT, READWRITE, ALIGN=3
\r
56 Heap_Mem SPACE Heap_Size
\r
63 ;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
\r
65 ; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).
\r
66 ; * A veneer defined below will first
\r
67 ; * be executed which in turn branches to the final exception handler.
\r
69 ; * In addition to defining the veneers, the vector table must for these buggy
\r
70 ; * devices contain the veneers.
\r
73 ;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define
\r
74 ;or use define below
\r
75 GBLL WORKAROUND_PMU_CM001
\r
77 ;/* A macro to setup a vector table entry based on STEP ID */
\r
78 IF :DEF:WORKAROUND_PMU_CM001
\r
81 DCD $Handler._Veneer
\r
90 ;/* A macro to ease definition of the various handlers based on STEP ID */
\r
91 IF :DEF:WORKAROUND_PMU_CM001
\r
93 ;/* First define the final exception handler */
\r
95 ExcpHandler $Handler_Func
\r
98 EXPORT $Handler_Func [WEAK]
\r
102 ;/* And then define a veneer that will branch to the final excp handler */
\r
103 $Handler_Func._Veneer\
\r
105 EXPORT $Handler_Func._Veneer [WEAK]
\r
106 LDR R0, =$Handler_Func
\r
117 ;/* No prefetch bug, hence define only the final exception handler */
\r
119 ExcpHandler $Handler_Func
\r
122 EXPORT $Handler_Func [WEAK]
\r
128 ;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */
\r
131 ;* ================== START OF VECTOR TABLE DEFINITION ====================== */
\r
132 ;* Vector Table - This gets programed into VTOR register */
\r
133 AREA RESET, DATA, READONLY
\r
135 EXPORT __Vectors_End
\r
136 EXPORT __Vectors_Size
\r
141 DCD __initial_sp ; Top of Stack
\r
142 DCD Reset_Handler ; Reset Handler
\r
144 ExcpVector NMI_Handler ; NMI Handler
\r
145 ExcpVector HardFault_Handler ; Hard Fault Handler
\r
146 ExcpVector MemManage_Handler ; MPU Fault Handler
\r
147 ExcpVector BusFault_Handler ; Bus Fault Handler
\r
148 ExcpVector UsageFault_Handler ; Usage Fault Handler
\r
153 DCD SVC_Handler ; SVCall Handler
\r
154 ExcpVector DebugMon_Handler ; Debug Monitor Handler
\r
156 DCD PendSV_Handler ; PendSV Handler
\r
157 DCD SysTick_Handler ; SysTick Handler
\r
159 ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals
\r
160 ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0
\r
161 ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0
\r
162 ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1
\r
163 ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2
\r
164 ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3
\r
165 ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0
\r
166 ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1
\r
167 ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2
\r
168 ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3
\r
172 ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0
\r
174 ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
\r
175 ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
\r
176 ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
\r
177 ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
\r
178 ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
\r
179 ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
\r
180 ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
\r
181 ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
\r
182 ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
\r
183 ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
\r
184 ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
\r
185 ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
\r
186 ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0
\r
187 ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1
\r
188 ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2
\r
189 ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3
\r
190 ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0
\r
191 ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1
\r
192 ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2
\r
193 ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3
\r
194 ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD0_0
\r
195 ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD0_1
\r
196 ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD0_2
\r
197 ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD0_3
\r
198 ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD0_4
\r
199 ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD0_5
\r
200 ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD0_6
\r
201 ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD0_7
\r
202 ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0
\r
203 ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1
\r
204 ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0
\r
205 ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1
\r
206 ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2
\r
207 ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3
\r
208 ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0
\r
209 ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1
\r
210 ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2
\r
211 ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3
\r
212 ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0
\r
213 ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1
\r
214 ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2
\r
215 ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3
\r
216 ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0
\r
217 ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1
\r
218 ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2
\r
219 ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3
\r
220 ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0
\r
221 ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1
\r
222 ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2
\r
223 ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3
\r
224 ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0
\r
225 ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1
\r
226 ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2
\r
227 ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3
\r
228 ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
\r
229 ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
\r
230 ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0
\r
231 ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1
\r
236 ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0
\r
237 ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1
\r
238 ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2
\r
239 ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3
\r
240 ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4
\r
241 ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5
\r
242 ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6
\r
243 ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7
\r
244 ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0
\r
245 ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1
\r
246 ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2
\r
247 ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3
\r
248 ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4
\r
249 ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5
\r
250 ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0
\r
251 ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1
\r
252 ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2
\r
253 ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3
\r
254 ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4
\r
255 ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5
\r
256 ExcpVector USIC2_0_IRQHandler ; Handler name for SR USIC2_0
\r
257 ExcpVector USIC2_1_IRQHandler ; Handler name for SR USIC2_1
\r
258 ExcpVector USIC2_2_IRQHandler ; Handler name for SR USIC2_2
\r
259 ExcpVector USIC2_3_IRQHandler ; Handler name for SR USIC2_3
\r
260 ExcpVector USIC2_4_IRQHandler ; Handler name for SR USIC2_4
\r
261 ExcpVector USIC2_5_IRQHandler ; Handler name for SR USIC2_5
\r
262 ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
\r
264 ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0
\r
265 ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
\r
266 ExcpVector SDMMC0_0_IRQHandler ; Handler name for SR SDMMC0_0
\r
267 ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0
\r
268 ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0
\r
270 ExcpVector GPDMA1_0_IRQHandler ; Handler name for SR GPDMA1_0
\r
274 __Vectors_Size EQU __Vectors_End - __Vectors
\r
276 ;* ================== END OF VECTOR TABLE DEFINITION ======================= */
\r
278 ;* ================== START OF VECTOR ROUTINES ============================= */
\r
280 AREA |.text|, CODE, READONLY
\r
282 ;* Reset Handler */
\r
284 EXPORT Reset_Handler [WEAK]
\r
288 ; Remap vector table
\r
290 LDR R1, =0xE000ED08 ;*VTOR register
\r
293 ;* C routines are likely to be called. Setup the stack now
\r
294 LDR SP,=__initial_sp
\r
296 LDR R0, = SystemInit
\r
299 ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
\r
300 ;weakly defined here though for a potential override.
\r
302 LDR R0, = SystemInit_DAVE3
\r
305 ;* Reset stack pointer before zipping off to user application
\r
306 LDR SP,=__initial_sp
\r
317 ;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
\r
321 ;/* Default exception Handlers - Users may override this default functionality by
\r
322 ; defining handlers of the same name in their C code */
\r
324 ExcpHandler NMI_Handler
\r
325 ExcpHandler HardFault_Handler
\r
326 ExcpHandler MemManage_Handler
\r
327 ExcpHandler BusFault_Handler
\r
328 ExcpHandler UsageFault_Handler
\r
329 ExcpHandler SVC_Handler
\r
330 ExcpHandler DebugMon_Handler
\r
331 ExcpHandler PendSV_Handler
\r
332 ExcpHandler SysTick_Handler
\r
334 ;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
\r
336 ;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
\r
339 ExcpHandler SCU_0_IRQHandler
\r
340 ExcpHandler ERU0_0_IRQHandler
\r
341 ExcpHandler ERU0_1_IRQHandler
\r
342 ExcpHandler ERU0_2_IRQHandler
\r
343 ExcpHandler ERU0_3_IRQHandler
\r
344 ExcpHandler ERU1_0_IRQHandler
\r
345 ExcpHandler ERU1_1_IRQHandler
\r
346 ExcpHandler ERU1_2_IRQHandler
\r
347 ExcpHandler ERU1_3_IRQHandler
\r
348 ExcpHandler PMU0_0_IRQHandler
\r
349 ExcpHandler VADC0_C0_0_IRQHandler
\r
350 ExcpHandler VADC0_C0_1_IRQHandler
\r
351 ExcpHandler VADC0_C0_2_IRQHandler
\r
352 ExcpHandler VADC0_C0_3_IRQHandler
\r
353 ExcpHandler VADC0_G0_0_IRQHandler
\r
354 ExcpHandler VADC0_G0_1_IRQHandler
\r
355 ExcpHandler VADC0_G0_2_IRQHandler
\r
356 ExcpHandler VADC0_G0_3_IRQHandler
\r
357 ExcpHandler VADC0_G1_0_IRQHandler
\r
358 ExcpHandler VADC0_G1_1_IRQHandler
\r
359 ExcpHandler VADC0_G1_2_IRQHandler
\r
360 ExcpHandler VADC0_G1_3_IRQHandler
\r
361 ExcpHandler VADC0_G2_0_IRQHandler
\r
362 ExcpHandler VADC0_G2_1_IRQHandler
\r
363 ExcpHandler VADC0_G2_2_IRQHandler
\r
364 ExcpHandler VADC0_G2_3_IRQHandler
\r
365 ExcpHandler VADC0_G3_0_IRQHandler
\r
366 ExcpHandler VADC0_G3_1_IRQHandler
\r
367 ExcpHandler VADC0_G3_2_IRQHandler
\r
368 ExcpHandler VADC0_G3_3_IRQHandler
\r
369 ExcpHandler DSD0_0_IRQHandler
\r
370 ExcpHandler DSD0_1_IRQHandler
\r
371 ExcpHandler DSD0_2_IRQHandler
\r
372 ExcpHandler DSD0_3_IRQHandler
\r
373 ExcpHandler DSD0_4_IRQHandler
\r
374 ExcpHandler DSD0_5_IRQHandler
\r
375 ExcpHandler DSD0_6_IRQHandler
\r
376 ExcpHandler DSD0_7_IRQHandler
\r
377 ExcpHandler DAC0_0_IRQHandler
\r
378 ExcpHandler DAC0_1_IRQHandler
\r
379 ExcpHandler CCU40_0_IRQHandler
\r
380 ExcpHandler CCU40_1_IRQHandler
\r
381 ExcpHandler CCU40_2_IRQHandler
\r
382 ExcpHandler CCU40_3_IRQHandler
\r
383 ExcpHandler CCU41_0_IRQHandler
\r
384 ExcpHandler CCU41_1_IRQHandler
\r
385 ExcpHandler CCU41_2_IRQHandler
\r
386 ExcpHandler CCU41_3_IRQHandler
\r
387 ExcpHandler CCU42_0_IRQHandler
\r
388 ExcpHandler CCU42_1_IRQHandler
\r
389 ExcpHandler CCU42_2_IRQHandler
\r
390 ExcpHandler CCU42_3_IRQHandler
\r
391 ExcpHandler CCU43_0_IRQHandler
\r
392 ExcpHandler CCU43_1_IRQHandler
\r
393 ExcpHandler CCU43_2_IRQHandler
\r
394 ExcpHandler CCU43_3_IRQHandler
\r
395 ExcpHandler CCU80_0_IRQHandler
\r
396 ExcpHandler CCU80_1_IRQHandler
\r
397 ExcpHandler CCU80_2_IRQHandler
\r
398 ExcpHandler CCU80_3_IRQHandler
\r
399 ExcpHandler CCU81_0_IRQHandler
\r
400 ExcpHandler CCU81_1_IRQHandler
\r
401 ExcpHandler CCU81_2_IRQHandler
\r
402 ExcpHandler CCU81_3_IRQHandler
\r
403 ExcpHandler POSIF0_0_IRQHandler
\r
404 ExcpHandler POSIF0_1_IRQHandler
\r
405 ExcpHandler POSIF1_0_IRQHandler
\r
406 ExcpHandler POSIF1_1_IRQHandler
\r
407 ExcpHandler CAN0_0_IRQHandler
\r
408 ExcpHandler CAN0_1_IRQHandler
\r
409 ExcpHandler CAN0_2_IRQHandler
\r
410 ExcpHandler CAN0_3_IRQHandler
\r
411 ExcpHandler CAN0_4_IRQHandler
\r
412 ExcpHandler CAN0_5_IRQHandler
\r
413 ExcpHandler CAN0_6_IRQHandler
\r
414 ExcpHandler CAN0_7_IRQHandler
\r
415 ExcpHandler USIC0_0_IRQHandler
\r
416 ExcpHandler USIC0_1_IRQHandler
\r
417 ExcpHandler USIC0_2_IRQHandler
\r
418 ExcpHandler USIC0_3_IRQHandler
\r
419 ExcpHandler USIC0_4_IRQHandler
\r
420 ExcpHandler USIC0_5_IRQHandler
\r
421 ExcpHandler USIC1_0_IRQHandler
\r
422 ExcpHandler USIC1_1_IRQHandler
\r
423 ExcpHandler USIC1_2_IRQHandler
\r
424 ExcpHandler USIC1_3_IRQHandler
\r
425 ExcpHandler USIC1_4_IRQHandler
\r
426 ExcpHandler USIC1_5_IRQHandler
\r
427 ExcpHandler USIC2_0_IRQHandler
\r
428 ExcpHandler USIC2_1_IRQHandler
\r
429 ExcpHandler USIC2_2_IRQHandler
\r
430 ExcpHandler USIC2_3_IRQHandler
\r
431 ExcpHandler USIC2_4_IRQHandler
\r
432 ExcpHandler USIC2_5_IRQHandler
\r
433 ExcpHandler LEDTS0_0_IRQHandler
\r
434 ExcpHandler FCE0_0_IRQHandler
\r
435 ExcpHandler GPDMA0_0_IRQHandler
\r
436 ExcpHandler SDMMC0_0_IRQHandler
\r
437 ExcpHandler USB0_0_IRQHandler
\r
438 ExcpHandler ETH0_0_IRQHandler
\r
439 ExcpHandler GPDMA1_0_IRQHandler
\r
441 ;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
\r
443 ;* Definition of the default weak SystemInit_DAVE3 function.
\r
444 ;* This function will be called by the CMSIS SystemInit function.
\r
445 ;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
\r
446 ;* which will overule this weak definition
\r
447 SystemInit_DAVE3 PROC
\r
448 EXPORT SystemInit_DAVE3 [WEAK]
\r
453 ;* Definition of the default weak DAVE3 function for clock App usage.
\r
454 ;* AllowPLLInitByStartup Handler */
\r
455 AllowPLLInitByStartup PROC
\r
456 EXPORT AllowPLLInitByStartup [WEAK]
\r
463 ;*******************************************************************************
\r
464 ; User Stack and Heap initialization
\r
465 ;*******************************************************************************
\r
468 EXPORT __initial_sp
\r
470 EXPORT __heap_limit
\r
474 IMPORT __use_two_region_memory
\r
475 EXPORT __user_initial_stackheap
\r
477 __user_initial_stackheap
\r
480 LDR R1, =(Stack_Mem + Stack_Size)
\r
481 LDR R2, = (Heap_Mem + Heap_Size)
\r
482 LDR R3, = Stack_Mem
\r
491 ;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE*****
\r