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   1 /**************************************************************************//**\r
   2  * @file     system_XMC4200.c\r
   3  * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
   4  *           for the Infineon XMC4000 Device Series\r
   5  * @version  V3.0.1 Alpha\r
   6  * @date     26. September 2012\r
   7  *\r
   8  * @note\r
   9  * Copyright (C) 2011 ARM Limited. All rights reserved.\r
  10  *\r
  11  * @par\r
  12  * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
  13  * processor based microcontrollers.  This file can be freely distributed \r
  14  * within development tools that are supporting such ARM based processors. \r
  15  *\r
  16  * @par\r
  17  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
  18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
  19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
  20  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
  21  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
  22  *\r
  23  ******************************************************************************/\r
  24 \r
  25 #include <system_XMC4200.h>\r
  26 #include <XMC4200.h>\r
  27 \r
  28 /*----------------------------------------------------------------------------\r
  29   Clock Variable definitions\r
  30  *----------------------------------------------------------------------------*/\r
  31 /*!< System Clock Frequency (Core Clock)*/\r
  32 uint32_t SystemCoreClock;\r
  33 \r
  34 /* clock definitions, do not modify! */\r
  35 #define SCU_CLOCK_CRYSTAL               1\r
  36 #define SCU_CLOCK_BACK_UP_FACTORY                       2\r
  37 #define SCU_CLOCK_BACK_UP_AUTOMATIC             3\r
  38 \r
  39 \r
  40 #define HIB_CLOCK_FOSI                                  1                                \r
  41 #define HIB_CLOCK_OSCULP                                2\r
  42 \r
  43 \r
  44 \r
  45 \r
  46 /*\r
  47 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
  48 */\r
  49 \r
  50 \r
  51 \r
  52 /*--------------------- Watchdog Configuration -------------------------------\r
  53 //\r
  54 // <e> Watchdog Configuration\r
  55 //     <o1.0> Disable Watchdog\r
  56 //\r
  57 // </e>\r
  58 */\r
  59 #define WDT_SETUP               1\r
  60 #define WDTENB_nVal             0x00000001\r
  61 \r
  62 /*--------------------- CLOCK Configuration -------------------------------\r
  63 //\r
  64 // <e> Main Clock Configuration\r
  65 //     <o1.0..1> CPU clock divider\r
  66 //                     <0=> fCPU = fSYS \r
  67 //                     <1=> fCPU = fSYS / 2\r
  68 //     <o2.0..1>  Peripheral Bus clock divider\r
  69 //                     <0=> fPB = fCPU\r
  70 //                     <1=> fPB = fCPU / 2\r
  71 //     <o3.0..1>  CCU Bus clock divider\r
  72 //                     <0=> fCCU = fCPU\r
  73 //                     <1=> fCCU = fCPU / 2\r
  74 //\r
  75 // </e>\r
  76 // \r
  77 */\r
  78 \r
  79 #define SCU_CLOCK_SETUP               1\r
  80 #define SCU_CPUCLKCR_DIV                0x00000000\r
  81 #define SCU_PBCLKCR_DIV             0x00000000\r
  82 #define SCU_CCUCLKCR_DIV                0x00000000\r
  83 /* not avalible in config wizzard*/\r
  84 /*                              \r
  85 * mandatory clock parameters **************************************************                         \r
  86 *                               \r
  87 * source for clock generation                           \r
  88 * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)                         \r
  89 *                               \r
  90 **************************************************************************************/                         \r
  91 // Selection of imput lock for PLL      \r
  92 /*************************************************************************************/\r
  93 #define SCU_PLL_CLOCK_INPUT     SCU_CLOCK_CRYSTAL\r
  94 //#define       SCU_PLL_CLOCK_INPUT     SCU_CLOCK_BACK_UP_FACTORY\r
  95 //#define       SCU_PLL_CLOCK_INPUT     SCU_CLOCK_BACK_UP_AUTOMATIC\r
  96 \r
  97 /*************************************************************************************/\r
  98 // Standby clock selection for Backup clock source trimming\r
  99 /*************************************************************************************/\r
 100 #define SCU_STANDBY_CLOCK  HIB_CLOCK_OSCULP\r
 101 //#define       SCU_STANDBY_CLOCK  HIB_CLOCK_FOSI\r
 102 \r
 103 /*************************************************************************************/\r
 104 // Global clock parameters\r
 105 /*************************************************************************************/\r
 106 #define CLOCK_FSYS                                                      80000000\r
 107 #define CLOCK_CRYSTAL_FREQUENCY 12000000                \r
 108 #define CLOCK_BACK_UP                                           24000000                \r
 109                                 \r
 110 /*************************************************************************************/\r
 111 /* OSC_HP setup parameters */                           \r
 112 /*************************************************************************************/\r
 113 #define SCU_OSC_HP_MODE 0xF0\r
 114 #define SCU_OSCHPWDGDIV 2               \r
 115                                 \r
 116 /*************************************************************************************/\r
 117 /* MAIN PLL setup parameters */                         \r
 118 /*************************************************************************************/\r
 119 //Divider settings for external crystal @ 12 MHz \r
 120 /*************************************************************************************/\r
 121 #define         SCU_PLL_K1DIV   1\r
 122 #define         SCU_PLL_K1DIV   1               \r
 123 #define         SCU_PLL_K2DIV   5               \r
 124 #define         SCU_PLL_PDIV    1               \r
 125 #define         SCU_PLL_NDIV    79              \r
 126                                 \r
 127 /*************************************************************************************/\r
 128 //Divider settings for use of backup clock source trimmed\r
 129 /*************************************************************************************/\r
 130 //#define       SCU_PLL_K1DIV   1               \r
 131 //#define       SCU_PLL_K2DIV   5               \r
 132 //#define       SCU_PLL_PDIV    3               \r
 133 //#define       SCU_PLL_NDIV    79              \r
 134 /*************************************************************************************/\r
 135         \r
 136 \r
 137 /*--------------------- USB CLOCK Configuration ---------------------------\r
 138 //\r
 139 // <e> USB Clock Configuration\r
 140 //\r
 141 // </e>\r
 142 // \r
 143 */\r
 144 \r
 145 #define SCU_USB_CLOCK_SETUP              0\r
 146 /* not avalible in config wizzard*/\r
 147 #define         SCU_USBPLL_PDIV 0               \r
 148 #define         SCU_USBPLL_NDIV 31              \r
 149 #define         SCU_USBDIV      3               \r
 150 \r
 151 /*--------------------- Flash Wait State Configuration -------------------------------\r
 152 //\r
 153 // <e> Flash Wait State Configuration\r
 154 //     <o1.0..3>   Flash Wait State\r
 155 //                     <0=> 3 WS\r
 156 //                     <1=> 4 WS\r
 157 //                     <2=> 5 WS     \r
 158 //                                                                               <3=> 6 WS\r
 159 // </e>\r
 160 // \r
 161 */\r
 162 \r
 163 #define PMU_FLASH             1\r
 164 #define PMU_FLASH_WS                                    0x00000000\r
 165 \r
 166 \r
 167 /*--------------------- CLOCKOUT Configuration -------------------------------\r
 168 //\r
 169 // <e> Clock OUT Configuration\r
 170 //     <o1.0..1>   Clockout Source Selection\r
 171 //                     <0=> System Clock\r
 172 //                     <2=> Divided value of USB PLL output\r
 173 //                     <3=> Divided value of PLL Clock\r
 174 //     <o2.0..4>   Clockout divider <1-10><#-1>\r
 175 //     <o3.0..1>   Clockout Pin Selection\r
 176 //                     <0=> P1.15\r
 177 //                     <1=> P0.8\r
 178 //                     \r
 179 //\r
 180 // </e>\r
 181 // \r
 182 */\r
 183 \r
 184 #define SCU_CLOCKOUT_SETUP               0\r
 185 #define SCU_CLOCKOUT_SOURCE             0x00000000\r
 186 #define SCU_CLOCKOUT_DIV                0x00000009\r
 187 #define SCU_CLOCKOUT_PIN                0x00000001\r
 188 \r
 189 /*----------------------------------------------------------------------------\r
 190   Clock Variable definitions\r
 191  *----------------------------------------------------------------------------*/\r
 192 /*!< System Clock Frequency (Core Clock)*/\r
 193 #if SCU_CLOCK_SETUP\r
 194 uint32_t SystemCoreClock = CLOCK_FSYS;\r
 195 #else\r
 196 uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
 197 #endif\r
 198 \r
 199 /*----------------------------------------------------------------------------\r
 200   static functions declarations\r
 201  *----------------------------------------------------------------------------*/\r
 202 #if (SCU_CLOCK_SETUP == 1)\r
 203 static int SystemClockSetup(void);\r
 204 #endif\r
 205 \r
 206 #if (SCU_USB_CLOCK_SETUP == 1)\r
 207 static int USBClockSetup(void);\r
 208 #endif\r
 209 \r
 210 \r
 211 /**\r
 212   * @brief  Setup the microcontroller system.\r
 213   *         Initialize the PLL and update the \r
 214   *         SystemCoreClock variable.\r
 215   * @param  None\r
 216   * @retval None\r
 217   */\r
 218 void SystemInit(void)\r
 219 {\r
 220 int temp;\r
 221         \r
 222 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
 223 SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */\r
 224                (3UL << 11*2)  );               /* set CP11 Full Access */\r
 225 #endif\r
 226         \r
 227 /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
 228 SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
 229         \r
 230 /* Setup the WDT */\r
 231 #if WDT_SETUP\r
 232 \r
 233 WDT->CTR &= ~WDTENB_nVal; \r
 234 \r
 235 #endif\r
 236 \r
 237 \r
 238 /* Setup the Flash Wait State */\r
 239 #if PMU_FLASH\r
 240 temp = FLASH0->FCON; \r
 241 temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
 242 temp |= PMU_FLASH_WS+3;\r
 243 FLASH0->FCON = temp;\r
 244 #endif\r
 245 \r
 246         \r
 247 /* Setup the clockout */\r
 248 #if SCU_CLOCKOUT_SETUP\r
 249 \r
 250 SCU_CLK->EXTCLKCR       |= SCU_CLOCKOUT_SOURCE;\r
 251 /*set PLL div for clkout */\r
 252 SCU_CLK->EXTCLKCR       |= SCU_CLOCKOUT_DIV<<16;\r
 253 \r
 254 if (SCU_CLOCKOUT_PIN) {\r
 255                                                 PORT0->IOCR8 = 0x00000088;   /*P0.8 --> ALT1 select +  HWSEL */\r
 256                                             PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
 257                                             PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk);  /*set to strong driver */\r
 258                                                 }\r
 259 else {\r
 260                 PORT1->IOCR12 = 0x88000000;                    /*P1.15--> ALT1 select */\r
 261             PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk);  /*set to strong driver */\r
 262                 }\r
 263 \r
 264 #endif\r
 265 \r
 266 \r
 267 /* Setup the System clock */ \r
 268 #if SCU_CLOCK_SETUP\r
 269 SystemClockSetup();\r
 270 #endif\r
 271 \r
 272 /*----------------------------------------------------------------------------\r
 273   Clock Variable definitions\r
 274  *----------------------------------------------------------------------------*/\r
 275 SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
 276 \r
 277 \r
 278 /* Setup the USB PL */ \r
 279 #if SCU_USB_CLOCK_SETUP\r
 280 USBClockSetup();\r
 281 #endif\r
 282 \r
 283 \r
 284 \r
 285 }\r
 286 \r
 287 \r
 288 /**\r
 289   * @brief  Update SystemCoreClock according to Clock Register Values\r
 290   * @note   -  \r
 291   * @param  None\r
 292   * @retval None\r
 293   */\r
 294 void SystemCoreClockUpdate(void)\r
 295 {\r
 296 unsigned int PDIV;\r
 297 unsigned int NDIV;\r
 298 unsigned int K2DIV;\r
 299 unsigned int long VCO;\r
 300 \r
 301 \r
 302 /*----------------------------------------------------------------------------\r
 303   Clock Variable definitions\r
 304  *----------------------------------------------------------------------------*/\r
 305 if (SCU_CLK->SYSCLKCR ==  0x00010000)\r
 306 {\r
 307         if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
 308                 /* check if PLL is locked */\r
 309                 /* read back divider settings */\r
 310                  PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
 311                  NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
 312                  K2DIV  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
 313 \r
 314                 if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
 315                 /* the selected clock is the Backup clock fofi */\r
 316                 VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
 317                 SystemCoreClock = VCO/K2DIV;\r
 318                 /* in case the sysclock div is used */\r
 319                 SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
 320                 \r
 321                 }\r
 322                 else\r
 323                 {\r
 324                 /* the selected clock is the PLL external oscillator */         \r
 325                 VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
 326                 SystemCoreClock = VCO/K2DIV;\r
 327                 /* in case the sysclock div is used */\r
 328                 SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
 329                 } \r
 330         \r
 331         \r
 332         }\r
 333 }\r
 334 else\r
 335 {\r
 336 SystemCoreClock = CLOCK_BACK_UP;\r
 337 }\r
 338 \r
 339 \r
 340 }\r
 341 \r
 342 \r
 343 /**\r
 344   * @brief  -\r
 345   * @note   -  \r
 346   * @param  None\r
 347   * @retval None\r
 348   */\r
 349 #if (SCU_CLOCK_SETUP == 1)\r
 350 static int SystemClockSetup(void)\r
 351 {\r
 352 int temp;\r
 353 unsigned int long VCO=0;\r
 354 int stepping_K2DIV;     \r
 355 \r
 356 /* this weak function enables DAVE3 clock App usage */  \r
 357 if(AllowPLLInitByStartup()){\r
 358          \r
 359 /* check if PLL is switched on */\r
 360 if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
 361 /* enable PLL first */\r
 362   SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
 363 \r
 364 } \r
 365 \r
 366 /* Enable OSC_HP if not already on*/\r
 367   if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
 368   {\r
 369         /********************************************************************************************************************/\r
 370         /*   Use external crystal for PLL clock input                                                                            */\r
 371         /********************************************************************************************************************/\r
 372 \r
 373    if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
 374            SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);     /*enable the OSC_HP*/\r
 375            /* setup OSC WDG devider */\r
 376            SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);         \r
 377            /* select external OSC as PLL input */\r
 378            SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
 379            /* restart OSC Watchdog */\r
 380            SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  \r
 381 \r
 382        /* Timeout for wait loop ~150ms */\r
 383            /********************************/\r
 384            SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
 385            SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 386            SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 387                            SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
 388            do \r
 389            {\r
 390        ;/* wait for ~150ms  */\r
 391            }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
 392 \r
 393            SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 394            if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
 395            return(0);/* Return Error */\r
 396 \r
 397     }\r
 398   }\r
 399   else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
 400         {\r
 401         /********************************************************************************************************************/\r
 402         /*   Use factory trimming Back-up clock for PLL clock input                                                                            */\r
 403         /********************************************************************************************************************/\r
 404                 /* PLL Back up clock selected */\r
 405                 SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
 406                         \r
 407         }\r
 408   else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
 409   {\r
 410         /********************************************************************************************************************/\r
 411         /*   Use automatic trimming Back-up clock for PLL clock input                                                                            */\r
 412         /********************************************************************************************************************/\r
 413         /* check for HIB Domain enabled  */\r
 414         if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
 415                 SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
 416 \r
 417    /* check for HIB Domain is not in reset state  */\r
 418         if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
 419             SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
 420 \r
 421                         /* PLL Back up clock selected */\r
 422                 SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
 423         \r
 424                 if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
 425                         {\r
 426                         /****************************************************************************************************************/\r
 427                         /*   Use fOSI as source of the standby clock                                                                             */\r
 428                         /****************************************************************************************************************/\r
 429                         SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
 430                         \r
 431                         SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
 432                         for(temp=0;temp<=0xFFFF;temp++);\r
 433 \r
 434                         SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
 435                         }\r
 436                 else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
 437                         {\r
 438                         /****************************************************************************************************************/\r
 439                         /*   Use fULP as source of the standby clock                                                                            */\r
 440                         /****************************************************************************************************************/\r
 441                         /*check OSCUL if running correct*/\r
 442                         if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
 443                                 {\r
 444                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
 445 \r
 446                                         SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
 447                                         /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
 448                                         /* select OSCUL clock for RTC*/\r
 449                                         SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
 450                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
 451                                         /*enable OSCULP WDG Alarm Enable*/\r
 452                                         SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
 453                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
 454                                         /*wait now for clock is stable */\r
 455                                         do\r
 456                                         {\r
 457                                         SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
 458                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
 459                                         for(temp=0;temp<=0xFFFF;temp++);\r
 460                                         }\r
 461                                         while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); \r
 462 \r
 463                                         SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
 464                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
 465                                 }       \r
 466                         // now OSCULP is running and can be used                 \r
 467                         SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
 468                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
 469                         \r
 470                         SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
 471                         /*TRIAL for delay loop*/\r
 472                         for(temp=0;temp<=0xFFFF;temp++);\r
 473                         \r
 474                         SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
 475                         /*TRIAL for delay loop*/\r
 476                         for(temp=0;temp<=0xFFFF;temp++);\r
 477                         \r
 478                         }\r
 479   }\r
 480 \r
 481         /********************************************************************************************************************/\r
 482         /*   Setup and look the main PLL                                                                                    */\r
 483         /********************************************************************************************************************/\r
 484 \r
 485 if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
 486         /* Systen is still running from internal clock */\r
 487                    /* select FOFI as system clock */\r
 488                    if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
 489 \r
 490 \r
 491                          /*calulation for stepping*/\r
 492                          if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 493                          if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
 494                                         VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 495          \r
 496                          stepping_K2DIV = (VCO/24000000)-1;     \r
 497                          /* Go to bypass the Main PLL */\r
 498                    SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
 499                    /* disconnect OSC_HP to PLL */\r
 500                    SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
 501                    /* Setup devider settings for main PLL */\r
 502                    SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 503                    /* we may have to set OSCDISCDIS */\r
 504                    SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
 505                    /* connect OSC_HP to PLL */\r
 506                    SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
 507                    /* restart PLL Lock detection */\r
 508                    SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
 509                    /* wait for PLL Lock */\r
 510                    /* setup time out loop */\r
 511                /* Timeout for wait loo ~150ms */\r
 512                    /********************************/\r
 513                    SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
 514                    SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 515                    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 516                                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
 517                    \r
 518                    while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
 519                SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 520 \r
 521                    if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
 522                                 {\r
 523                                 /* Go back to the Main PLL */\r
 524                                 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
 525                                 }\r
 526                                 else return(0);\r
 527                  \r
 528         \r
 529            /*********************************************************\r
 530            here we need to setup the system clock divider\r
 531            *********************************************************/\r
 532         \r
 533                 SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
 534                 SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;     \r
 535                 SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
 536         \r
 537 \r
 538                 /* Switch system clock to PLL */\r
 539            SCU_CLK->SYSCLKCR |=  0x00010000; \r
 540                                 \r
 541            /* we may have to reset OSCDISCDIS */\r
 542            SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
 543                                 \r
 544                                                                                                                                   \r
 545                  /*********************************************************/\r
 546                  /* Delay for next K2 step ~50µs */\r
 547                  /*********************************************************/\r
 548                  SysTick->LOAD  = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
 549                  SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 550                  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 551                                                                                  SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
 552         \r
 553                  while (SysTick->VAL >= 100);                                                              /* wait for ~50µs  */\r
 554                  SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 555                  /*********************************************************/\r
 556 \r
 557            /*********************************************************\r
 558            here the ramp up of the system clock starts FSys < 60MHz\r
 559            *********************************************************/\r
 560                 if (CLOCK_FSYS > 60000000){\r
 561                          /*calulation for stepping*/\r
 562                          if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 563                          if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
 564                                         VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 565          \r
 566                          stepping_K2DIV = (VCO/60000000)-1;     \r
 567 \r
 568                          /* Setup devider settings for main PLL */\r
 569                                 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 570                  }\r
 571                  else\r
 572                  {\r
 573                                 /* Setup devider settings for main PLL */\r
 574                                 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 575                     SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
 576                           return(1);\r
 577                  }\r
 578 \r
 579                  /*********************************************************/\r
 580                  /* Delay for next K2 step ~50µs */\r
 581                  /*********************************************************/\r
 582            SysTick->LOAD  = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
 583            SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 584            SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 585                            SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
 586         \r
 587            while (SysTick->VAL >= 100);                                                            /* wait for ~50µs  */\r
 588            SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 589            /********************************/\r
 590         \r
 591    /*********************************************************\r
 592            here the ramp up of the system clock starts FSys < 90MHz\r
 593            *********************************************************/\r
 594                 if (CLOCK_FSYS > 90000000){\r
 595                          /*calulation for stepping*/\r
 596                          if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 597                          if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
 598                                         VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 599 \r
 600                          stepping_K2DIV = (VCO/90000000)-1;                     \r
 601 \r
 602                          /* Setup devider settings for main PLL */\r
 603                                 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 604                  }\r
 605                  else\r
 606                  {\r
 607                                 /* Setup devider settings for main PLL */\r
 608                                 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 609               SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
 610                                 return(1);\r
 611                  }\r
 612         \r
 613                  /*********************************************************/\r
 614                  /* Delay for next K2 step ~50µs */\r
 615                  /*********************************************************/\r
 616            SysTick->LOAD  = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
 617            SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 618            SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 619                            SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
 620         \r
 621            while (SysTick->VAL >= 100);                                                            /* wait for ~50µs  */\r
 622            SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 623            /********************************/\r
 624         \r
 625            /* Setup devider settings for main PLL */\r
 626            SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 627         \r
 628            SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
 629         }\r
 630  }/* end this weak function enables DAVE3 clock App usage */    \r
 631    return(1);\r
 632 \r
 633 }\r
 634 #endif\r
 635 \r
 636 /**\r
 637   * @brief  -\r
 638   * @note   -  \r
 639   * @param  None\r
 640   * @retval None\r
 641   */\r
 642 #if (SCU_USB_CLOCK_SETUP == 1)\r
 643 static int USBClockSetup(void)\r
 644 {\r
 645 /* this weak function enables DAVE3 clock App usage */  \r
 646 if(AllowPLLInitByStartup()){\r
 647         \r
 648 /* check if PLL is switched on */\r
 649 if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
 650         /* enable PLL first */\r
 651   SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
 652 }\r
 653 \r
 654 /* check and if not already running enable OSC_HP */\r
 655    if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
 656                  /* check if Main PLL is switched on for OSC WD*/\r
 657                  if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
 658                         /* enable PLL first */\r
 659                         SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
 660                  }\r
 661            SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);     /*enable the OSC_HP*/\r
 662            /* setup OSC WDG devider */\r
 663            SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);         \r
 664            /* restart OSC Watchdog */\r
 665            SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  \r
 666         \r
 667        /* Timeout for wait loop ~150ms */\r
 668            /********************************/\r
 669            SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
 670            SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 671            SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 672                            SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
 673            do \r
 674            {\r
 675        ;/* wait for ~150ms  */\r
 676            }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
 677 \r
 678            SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 679            if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
 680            return(0);/* Return Error */\r
 681         \r
 682   }\r
 683 \r
 684 \r
 685 /* Setup USB PLL */\r
 686    /* Go to bypass the Main PLL */\r
 687    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
 688    /* disconnect OSC_FI to PLL */\r
 689    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
 690    /* Setup devider settings for main PLL */\r
 691    SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
 692    /* Setup USBDIV settings USB clock */\r
 693    SCU_CLK->USBCLKCR = SCU_USBDIV;\r
 694    /* we may have to set OSCDISCDIS */\r
 695    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
 696    /* connect OSC_FI to PLL */\r
 697    SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
 698    /* restart PLL Lock detection */\r
 699    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
 700    /* wait for PLL Lock */\r
 701    while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
 702    \r
 703  }/* end this weak function enables DAVE3 clock App usage */    \r
 704    return(1);\r
 705 \r
 706 }\r
 707 #endif\r
 708 \r