1 /**************************************************************************//**
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2 * @file system_XMC4200.c
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3 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
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4 * for the Infineon XMC4000 Device Series
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5 * @version V3.0.1 Alpha
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6 * @date 26. September 2012
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9 * Copyright (C) 2011 ARM Limited. All rights reserved.
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12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
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13 * processor based microcontrollers. This file can be freely distributed
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14 * within development tools that are supporting such ARM based processors.
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17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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23 ******************************************************************************/
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25 #include <system_XMC4200.h>
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26 #include <XMC4200.h>
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28 /*----------------------------------------------------------------------------
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29 Clock Variable definitions
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30 *----------------------------------------------------------------------------*/
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31 /*!< System Clock Frequency (Core Clock)*/
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32 uint32_t SystemCoreClock;
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34 /* clock definitions, do not modify! */
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35 #define SCU_CLOCK_CRYSTAL 1
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36 #define SCU_CLOCK_BACK_UP_FACTORY 2
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37 #define SCU_CLOCK_BACK_UP_AUTOMATIC 3
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40 #define HIB_CLOCK_FOSI 1
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41 #define HIB_CLOCK_OSCULP 2
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47 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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52 /*--------------------- Watchdog Configuration -------------------------------
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54 // <e> Watchdog Configuration
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55 // <o1.0> Disable Watchdog
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60 #define WDTENB_nVal 0x00000001
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62 /*--------------------- CLOCK Configuration -------------------------------
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64 // <e> Main Clock Configuration
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65 // <o1.0..1> CPU clock divider
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66 // <0=> fCPU = fSYS
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67 // <1=> fCPU = fSYS / 2
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68 // <o2.0..1> Peripheral Bus clock divider
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70 // <1=> fPB = fCPU / 2
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71 // <o3.0..1> CCU Bus clock divider
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73 // <1=> fCCU = fCPU / 2
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79 #define SCU_CLOCK_SETUP 1
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80 #define SCU_CPUCLKCR_DIV 0x00000000
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81 #define SCU_PBCLKCR_DIV 0x00000000
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82 #define SCU_CCUCLKCR_DIV 0x00000000
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83 /* not avalible in config wizzard*/
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85 * mandatory clock parameters **************************************************
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87 * source for clock generation
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88 * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)
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90 **************************************************************************************/
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91 // Selection of imput lock for PLL
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92 /*************************************************************************************/
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93 #define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL
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94 //#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY
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95 //#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC
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97 /*************************************************************************************/
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98 // Standby clock selection for Backup clock source trimming
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99 /*************************************************************************************/
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100 #define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP
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101 //#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI
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103 /*************************************************************************************/
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104 // Global clock parameters
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105 /*************************************************************************************/
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106 #define CLOCK_FSYS 80000000
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107 #define CLOCK_CRYSTAL_FREQUENCY 12000000
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108 #define CLOCK_BACK_UP 24000000
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110 /*************************************************************************************/
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111 /* OSC_HP setup parameters */
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112 /*************************************************************************************/
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113 #define SCU_OSC_HP_MODE 0xF0
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114 #define SCU_OSCHPWDGDIV 2
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116 /*************************************************************************************/
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117 /* MAIN PLL setup parameters */
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118 /*************************************************************************************/
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119 //Divider settings for external crystal @ 12 MHz
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120 /*************************************************************************************/
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121 #define SCU_PLL_K1DIV 1
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122 #define SCU_PLL_K1DIV 1
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123 #define SCU_PLL_K2DIV 5
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124 #define SCU_PLL_PDIV 1
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125 #define SCU_PLL_NDIV 79
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127 /*************************************************************************************/
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128 //Divider settings for use of backup clock source trimmed
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129 /*************************************************************************************/
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130 //#define SCU_PLL_K1DIV 1
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131 //#define SCU_PLL_K2DIV 5
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132 //#define SCU_PLL_PDIV 3
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133 //#define SCU_PLL_NDIV 79
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134 /*************************************************************************************/
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137 /*--------------------- USB CLOCK Configuration ---------------------------
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139 // <e> USB Clock Configuration
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145 #define SCU_USB_CLOCK_SETUP 0
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146 /* not avalible in config wizzard*/
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147 #define SCU_USBPLL_PDIV 0
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148 #define SCU_USBPLL_NDIV 31
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149 #define SCU_USBDIV 3
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151 /*--------------------- Flash Wait State Configuration -------------------------------
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153 // <e> Flash Wait State Configuration
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154 // <o1.0..3> Flash Wait State
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163 #define PMU_FLASH 1
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164 #define PMU_FLASH_WS 0x00000000
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167 /*--------------------- CLOCKOUT Configuration -------------------------------
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169 // <e> Clock OUT Configuration
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170 // <o1.0..1> Clockout Source Selection
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171 // <0=> System Clock
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172 // <2=> Divided value of USB PLL output
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173 // <3=> Divided value of PLL Clock
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174 // <o2.0..4> Clockout divider <1-10><#-1>
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175 // <o3.0..1> Clockout Pin Selection
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184 #define SCU_CLOCKOUT_SETUP 0
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185 #define SCU_CLOCKOUT_SOURCE 0x00000000
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186 #define SCU_CLOCKOUT_DIV 0x00000009
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187 #define SCU_CLOCKOUT_PIN 0x00000001
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189 /*----------------------------------------------------------------------------
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190 Clock Variable definitions
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191 *----------------------------------------------------------------------------*/
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192 /*!< System Clock Frequency (Core Clock)*/
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193 #if SCU_CLOCK_SETUP
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194 uint32_t SystemCoreClock = CLOCK_FSYS;
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196 uint32_t SystemCoreClock = CLOCK_BACK_UP;
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199 /*----------------------------------------------------------------------------
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200 static functions declarations
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201 *----------------------------------------------------------------------------*/
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202 #if (SCU_CLOCK_SETUP == 1)
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203 static int SystemClockSetup(void);
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206 #if (SCU_USB_CLOCK_SETUP == 1)
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207 static int USBClockSetup(void);
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212 * @brief Setup the microcontroller system.
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213 * Initialize the PLL and update the
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214 * SystemCoreClock variable.
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218 void SystemInit(void)
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222 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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223 SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
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224 (3UL << 11*2) ); /* set CP11 Full Access */
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227 /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
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228 SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
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230 /* Setup the WDT */
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233 WDT->CTR &= ~WDTENB_nVal;
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238 /* Setup the Flash Wait State */
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240 temp = FLASH0->FCON;
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241 temp &= ~FLASH_FCON_WSPFLASH_Msk;
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242 temp |= PMU_FLASH_WS+3;
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243 FLASH0->FCON = temp;
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247 /* Setup the clockout */
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248 #if SCU_CLOCKOUT_SETUP
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250 SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;
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251 /*set PLL div for clkout */
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252 SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;
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254 if (SCU_CLOCKOUT_PIN) {
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255 PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */
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256 PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);
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257 PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */
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260 PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */
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261 PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */
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267 /* Setup the System clock */
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268 #if SCU_CLOCK_SETUP
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269 SystemClockSetup();
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272 /*----------------------------------------------------------------------------
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273 Clock Variable definitions
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274 *----------------------------------------------------------------------------*/
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275 SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/
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278 /* Setup the USB PL */
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279 #if SCU_USB_CLOCK_SETUP
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289 * @brief Update SystemCoreClock according to Clock Register Values
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294 void SystemCoreClockUpdate(void)
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298 unsigned int K2DIV;
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299 unsigned int long VCO;
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302 /*----------------------------------------------------------------------------
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303 Clock Variable definitions
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304 *----------------------------------------------------------------------------*/
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305 if (SCU_CLK->SYSCLKCR == 0x00010000)
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307 if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){
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308 /* check if PLL is locked */
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309 /* read back divider settings */
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310 PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;
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311 NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;
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312 K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;
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314 if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){
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315 /* the selected clock is the Backup clock fofi */
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316 VCO = (CLOCK_BACK_UP/PDIV)*NDIV;
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317 SystemCoreClock = VCO/K2DIV;
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318 /* in case the sysclock div is used */
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319 SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
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324 /* the selected clock is the PLL external oscillator */
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325 VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;
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326 SystemCoreClock = VCO/K2DIV;
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327 /* in case the sysclock div is used */
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328 SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);
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336 SystemCoreClock = CLOCK_BACK_UP;
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349 #if (SCU_CLOCK_SETUP == 1)
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350 static int SystemClockSetup(void)
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353 unsigned int long VCO=0;
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354 int stepping_K2DIV;
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356 /* this weak function enables DAVE3 clock App usage */
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357 if(AllowPLLInitByStartup()){
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359 /* check if PLL is switched on */
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360 if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
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361 /* enable PLL first */
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362 SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
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366 /* Enable OSC_HP if not already on*/
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367 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)
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369 /********************************************************************************************************************/
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370 /* Use external crystal for PLL clock input */
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371 /********************************************************************************************************************/
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373 if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
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374 SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
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375 /* setup OSC WDG devider */
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376 SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
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377 /* select external OSC as PLL input */
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378 SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
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379 /* restart OSC Watchdog */
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380 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
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382 /* Timeout for wait loop ~150ms */
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383 /********************************/
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384 SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
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385 SysTick->VAL = 0; /* Load the SysTick Counter Value */
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386 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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387 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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390 ;/* wait for ~150ms */
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391 }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
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393 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
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394 if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
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395 return(0);/* Return Error */
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399 else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)
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401 /********************************************************************************************************************/
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402 /* Use factory trimming Back-up clock for PLL clock input */
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403 /********************************************************************************************************************/
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404 /* PLL Back up clock selected */
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405 SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
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408 else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)
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410 /********************************************************************************************************************/
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411 /* Use automatic trimming Back-up clock for PLL clock input */
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412 /********************************************************************************************************************/
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413 /* check for HIB Domain enabled */
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414 if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
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415 SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/
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417 /* check for HIB Domain is not in reset state */
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418 if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)
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419 SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/
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421 /* PLL Back up clock selected */
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422 SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
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424 if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)
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426 /****************************************************************************************************************/
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427 /* Use fOSI as source of the standby clock */
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428 /****************************************************************************************************************/
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429 SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
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431 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
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432 for(temp=0;temp<=0xFFFF;temp++);
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434 SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
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436 else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)
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438 /****************************************************************************************************************/
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439 /* Use fULP as source of the standby clock */
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440 /****************************************************************************************************************/
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441 /*check OSCUL if running correct*/
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442 if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)
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444 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);
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446 SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/
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447 /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/
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448 /* select OSCUL clock for RTC*/
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449 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;
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450 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
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451 /*enable OSCULP WDG Alarm Enable*/
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452 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
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453 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
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454 /*wait now for clock is stable */
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457 SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
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458 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
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459 for(temp=0;temp<=0xFFFF;temp++);
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461 while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);
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463 SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
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464 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);
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466 // now OSCULP is running and can be used
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467 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
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468 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);
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470 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;
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471 /*TRIAL for delay loop*/
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472 for(temp=0;temp<=0xFFFF;temp++);
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474 SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
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475 /*TRIAL for delay loop*/
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476 for(temp=0;temp<=0xFFFF;temp++);
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481 /********************************************************************************************************************/
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482 /* Setup and look the main PLL */
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483 /********************************************************************************************************************/
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485 if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){
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486 /* Systen is still running from internal clock */
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487 /* select FOFI as system clock */
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488 if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/
\r
491 /*calulation for stepping*/
\r
492 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
\r
493 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
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494 VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
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496 stepping_K2DIV = (VCO/24000000)-1;
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497 /* Go to bypass the Main PLL */
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498 SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
\r
499 /* disconnect OSC_HP to PLL */
\r
500 SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
\r
501 /* Setup devider settings for main PLL */
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502 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
\r
503 /* we may have to set OSCDISCDIS */
\r
504 SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
\r
505 /* connect OSC_HP to PLL */
\r
506 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
\r
507 /* restart PLL Lock detection */
\r
508 SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
\r
509 /* wait for PLL Lock */
\r
510 /* setup time out loop */
\r
511 /* Timeout for wait loo ~150ms */
\r
512 /********************************/
\r
513 SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
\r
514 SysTick->VAL = 0; /* Load the SysTick Counter Value */
\r
515 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
516 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
518 while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));
\r
519 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
\r
521 if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)
\r
523 /* Go back to the Main PLL */
\r
524 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
\r
529 /*********************************************************
\r
530 here we need to setup the system clock divider
\r
531 *********************************************************/
\r
533 SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;
\r
534 SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;
\r
535 SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;
\r
538 /* Switch system clock to PLL */
\r
539 SCU_CLK->SYSCLKCR |= 0x00010000;
\r
541 /* we may have to reset OSCDISCDIS */
\r
542 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
\r
545 /*********************************************************/
\r
546 /* Delay for next K2 step ~50µs */
\r
547 /*********************************************************/
\r
548 SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
\r
549 SysTick->VAL = 0; /* Load the SysTick Counter Value */
\r
550 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
551 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
553 while (SysTick->VAL >= 100); /* wait for ~50µs */
\r
554 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
\r
555 /*********************************************************/
\r
557 /*********************************************************
\r
558 here the ramp up of the system clock starts FSys < 60MHz
\r
559 *********************************************************/
\r
560 if (CLOCK_FSYS > 60000000){
\r
561 /*calulation for stepping*/
\r
562 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
\r
563 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
\r
564 VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
\r
566 stepping_K2DIV = (VCO/60000000)-1;
\r
568 /* Setup devider settings for main PLL */
\r
569 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
\r
573 /* Setup devider settings for main PLL */
\r
574 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
\r
575 SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
\r
579 /*********************************************************/
\r
580 /* Delay for next K2 step ~50µs */
\r
581 /*********************************************************/
\r
582 SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;
\r
583 SysTick->VAL = 0; /* Load the SysTick Counter Value */
\r
584 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
585 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
587 while (SysTick->VAL >= 100); /* wait for ~50µs */
\r
588 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
\r
589 /********************************/
\r
591 /*********************************************************
\r
592 here the ramp up of the system clock starts FSys < 90MHz
\r
593 *********************************************************/
\r
594 if (CLOCK_FSYS > 90000000){
\r
595 /*calulation for stepping*/
\r
596 if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
\r
597 if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))
\r
598 VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);
\r
600 stepping_K2DIV = (VCO/90000000)-1;
\r
602 /* Setup devider settings for main PLL */
\r
603 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));
\r
607 /* Setup devider settings for main PLL */
\r
608 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
\r
609 SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
\r
613 /*********************************************************/
\r
614 /* Delay for next K2 step ~50µs */
\r
615 /*********************************************************/
\r
616 SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;
\r
617 SysTick->VAL = 0; /* Load the SysTick Counter Value */
\r
618 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
619 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
621 while (SysTick->VAL >= 100); /* wait for ~50µs */
\r
622 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
\r
623 /********************************/
\r
625 /* Setup devider settings for main PLL */
\r
626 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));
\r
628 SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */
\r
630 }/* end this weak function enables DAVE3 clock App usage */
\r
642 #if (SCU_USB_CLOCK_SETUP == 1)
\r
643 static int USBClockSetup(void)
\r
645 /* this weak function enables DAVE3 clock App usage */
\r
646 if(AllowPLLInitByStartup()){
\r
648 /* check if PLL is switched on */
\r
649 if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){
\r
650 /* enable PLL first */
\r
651 SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
\r
654 /* check and if not already running enable OSC_HP */
\r
655 if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){
\r
656 /* check if Main PLL is switched on for OSC WD*/
\r
657 if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){
\r
658 /* enable PLL first */
\r
659 SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
\r
661 SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/
\r
662 /* setup OSC WDG devider */
\r
663 SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);
\r
664 /* restart OSC Watchdog */
\r
665 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
\r
667 /* Timeout for wait loop ~150ms */
\r
668 /********************************/
\r
669 SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */
\r
670 SysTick->VAL = 0; /* Load the SysTick Counter Value */
\r
671 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
672 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
675 ;/* wait for ~150ms */
\r
676 }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));
\r
678 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */
\r
679 if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)
\r
680 return(0);/* Return Error */
\r
685 /* Setup USB PLL */
\r
686 /* Go to bypass the Main PLL */
\r
687 SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
\r
688 /* disconnect OSC_FI to PLL */
\r
689 SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
\r
690 /* Setup devider settings for main PLL */
\r
691 SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));
\r
692 /* Setup USBDIV settings USB clock */
\r
693 SCU_CLK->USBCLKCR = SCU_USBDIV;
\r
694 /* we may have to set OSCDISCDIS */
\r
695 SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
\r
696 /* connect OSC_FI to PLL */
\r
697 SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
\r
698 /* restart PLL Lock detection */
\r
699 SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
\r
700 /* wait for PLL Lock */
\r
701 while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));
\r
703 }/* end this weak function enables DAVE3 clock App usage */
\r