1 /****************************************************************************/
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4 * XMC4000 Device Series
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8 Copyright (C) 2011-2012 Infineon Technologies AG. All rights reserved.
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12 * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon's
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13 * microcontrollers. This file can be freely distributed
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14 * within development tools that are supporting such microcontrollers.
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17 * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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20 * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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23 ******************************************************************************/
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25 /** @mainpage CMSIS device specific (XMC4500) peripheral access layer.
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28 * This file provides the XMC4500 Device specific peripheral access layer for
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29 * all peripherals. This file contains all the data structures and the address
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30 * mapping of the device specific peripherals.
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32 * The file also provides interrupt numbers (IRQHandler) for all core and device
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33 * specific exceptions and interrupts.
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37 #ifndef __XMC4500_H__
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38 #define __XMC4500_H__
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46 /********************************************
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47 ** Start of section using anonymous unions **
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48 *********************************************/
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49 #if defined(__CC_ARM)
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52 #elif defined(__ICCARM__)
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53 #pragma language=extended
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54 #elif defined(__GNUC__)
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55 /* anonymous unions are enabled by default */
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56 #elif defined(__TMS470__)
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57 /* anonymous unions are enabled by default */
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58 #elif defined(__TASKING__)
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59 #pragma warning 586
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61 #warning Not supported compiler type
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65 * ==========================================================================
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66 * --------------------- __NVIC_PRIO_BITS -----------------------------------
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67 * ==========================================================================
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69 #ifndef __NVIC_PRIO_BITS
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70 #define __NVIC_PRIO_BITS (6)
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74 * ==========================================================================
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75 * ----------------------------- M4 Stuff -----------------------------------
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76 * ==========================================================================
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78 #define __CM4_REV 0x0001 /**< Core revision r0p1 */
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79 #define __MPU_PRESENT 1 /**< MPU present or not */
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80 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
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81 #define __FPU_PRESENT 1 /**< FPU present or not */
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84 * ==========================================================================
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85 * ---------- Interrupt Number Definition -----------------------------------
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86 * ==========================================================================
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91 /****** Cortex-M3 Processor Exceptions Numbers **********************************/
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92 NMI_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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93 MemManage_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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94 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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95 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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96 SVC_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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97 DebugMon_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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98 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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99 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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101 /****** XMC45xx Specific Interrupt Numbers ***************************************/
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102 SCU_0_IRQn = 0, /*!< SCU SR0 Interrupt */
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103 ERU0_0_IRQn = 1, /*!< SCU SR1 Interrupt */
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104 ERU0_1_IRQn = 2, /*!< SCU SR2 Interrupt */
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105 ERU0_2_IRQn = 3, /*!< SCU SR3 Interrupt */
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106 ERU0_3_IRQn = 4, /*!< SCU SR4 Interrupt */
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107 ERU1_0_IRQn = 5, /*!< SCU SR5 Interrupt */
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108 ERU1_1_IRQn = 6, /*!< SCU SR6 Interrupt */
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109 ERU1_2_IRQn = 7, /*!< SCU SR7 Interrupt */
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110 ERU1_3_IRQn = 8, /*!< SCU SR8 Interrupt */
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111 PMU0_0_IRQn = 12, /*!< PMU SR0 Interrupt */
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112 VADC0_C0_0_IRQn = 14, /*!< VADC SR0 Interrupt */
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113 VADC0_C0_1_IRQn = 15, /*!< VADC SR1 Interrupt */
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114 VADC0_C0_2_IRQn = 16, /*!< VADC SR2 Interrupt */
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115 VADC0_C0_3_IRQn = 17, /*!< VADC SR3 Interrupt */
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116 VADC0_G0_0_IRQn = 18, /*!< VADC SR4 Interrupt */
\r
117 VADC0_G0_1_IRQn = 19, /*!< VADC SR5 Interrupt */
\r
118 VADC0_G0_2_IRQn = 20, /*!< VADC SR6 Interrupt */
\r
119 VADC0_G0_3_IRQn = 21, /*!< VADC SR7 Interrupt */
\r
120 VADC0_G1_0_IRQn = 22, /*!< VADC SR8 Interrupt */
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121 VADC0_G1_1_IRQn = 23, /*!< VADC SR9 Interrupt */
\r
122 VADC0_G1_2_IRQn = 24, /*!< VADC SR10 Interrupt */
\r
123 VADC0_G1_3_IRQn = 25, /*!< VADC SR11 Interrupt */
\r
124 VADC0_G2_0_IRQn = 26, /*!< VADC SR12 Interrupt */
\r
125 VADC0_G2_1_IRQn = 27, /*!< VADC SR13 Interrupt */
\r
126 VADC0_G2_2_IRQn = 28, /*!< VADC SR14 Interrupt */
\r
127 VADC0_G2_3_IRQn = 29, /*!< VADC SR15 Interrupt */
\r
128 VADC0_G3_0_IRQn = 30, /*!< VADC SR16 Interrupt */
\r
129 VADC0_G3_1_IRQn = 31, /*!< VADC SR17 Interrupt */
\r
130 VADC0_G3_2_IRQn = 32, /*!< VADC SR18 Interrupt */
\r
131 VADC0_G3_3_IRQn = 33, /*!< VADC SR19 Interrupt */
\r
132 DSD0_M_0_IRQn = 34, /*!< DSD SR0 Interrupt */
\r
133 DSD0_M_1_IRQn = 35, /*!< DSD SR1 Interrupt */
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134 DSD0_M_2_IRQn = 36, /*!< DSD SR2 Interrupt */
\r
135 DSD0_M_3_IRQn = 37, /*!< DSD SR3 Interrupt */
\r
136 DSD0_A_4_IRQn = 38, /*!< DSD SR4 Interrupt */
\r
137 DSD0_A_5_IRQn = 39, /*!< DSD SR5 Interrupt */
\r
138 DSD0_A_6_IRQn = 40, /*!< DSD SR6 Interrupt */
\r
139 DSD0_A_7_IRQn = 41, /*!< DSD SR7 Interrupt */
\r
140 DAC0_0_IRQn = 42, /*!< DAC SR0 Interrupt */
\r
141 DAC1_1_IRQn = 43, /*!< DAC SR1 Interrupt */
\r
142 CCU40_0_IRQn = 44, /*!< CCU40 SR0 Interrupt */
\r
143 CCU40_1_IRQn = 45, /*!< CCU40 SR1 Interrupt */
\r
144 CCU40_2_IRQn = 46, /*!< CCU40 SR2 Interrupt */
\r
145 CCU40_3_IRQn = 47, /*!< CCU40 SR3 Interrupt */
\r
146 CCU41_0_IRQn = 48, /*!< CCU41 SR0 Interrupt */
\r
147 CCU41_1_IRQn = 49, /*!< CCU41 SR1 Interrupt */
\r
148 CCU41_2_IRQn = 50, /*!< CCU41 SR2 Interrupt */
\r
149 CCU41_3_IRQn = 51, /*!< CCU41 SR3 Interrupt */
\r
150 CCU42_0_IRQn = 52, /*!< CCU42 SR0 Interrupt */
\r
151 CCU42_1_IRQn = 53, /*!< CCU42 SR1 Interrupt */
\r
152 CCU42_2_IRQn = 54, /*!< CCU42 SR2 Interrupt */
\r
153 CCU42_3_IRQn = 55, /*!< CCU42 SR3 Interrupt */
\r
154 CCU43_0_IRQn = 56, /*!< CCU43 SR0 Interrupt */
\r
155 CCU43_1_IRQn = 57, /*!< CCU43 SR1 Interrupt */
\r
156 CCU43_2_IRQn = 58, /*!< CCU43 SR2 Interrupt */
\r
157 CCU43_3_IRQn = 59, /*!< CCU43 SR3 Interrupt */
\r
158 CCU80_0_IRQn = 60, /*!< CCU80 SR0 Interrupt */
\r
159 CCU80_1_IRQn = 61, /*!< CCU80 SR1 Interrupt */
\r
160 CCU80_2_IRQn = 62, /*!< CCU80 SR2 Interrupt */
\r
161 CCU80_3_IRQn = 63, /*!< CCU80 SR3 Interrupt */
\r
162 CCU81_0_IRQn = 64, /*!< CCU81 SR0 Interrupt */
\r
163 CCU81_1_IRQn = 65, /*!< CCU81 SR1 Interrupt */
\r
164 CCU81_2_IRQn = 66, /*!< CCU81 SR2 Interrupt */
\r
165 CCU81_3_IRQn = 67, /*!< CCU81 SR3 Interrupt */
\r
166 POSIF0_0_IRQn = 68, /*!< POSIF0 SR0 Interrupt */
\r
167 POSIF0_1_IRQn = 69, /*!< POSIF0 SR1 Interrupt */
\r
168 POSIF1_0_IRQn = 70, /*!< POSIF1 SR0 Interrupt */
\r
169 POSIF1_1_IRQn = 71, /*!< POSIF1 SR1 Interrupt */
\r
170 CAN0_0_IRQn = 76, /*!< MCAN SR0 Interrupt */
\r
171 CAN0_1_IRQn = 77, /*!< MCAN SR1 Interrupt */
\r
172 CAN0_2_IRQn = 78, /*!< MCAN SR2 Interrupt */
\r
173 CAN0_3_IRQn = 79, /*!< MCAN SR3 Interrupt */
\r
174 CAN0_4_IRQn = 80, /*!< MCAN SR4 Interrupt */
\r
175 CAN0_5_IRQn = 81, /*!< MCAN SR5 Interrupt */
\r
176 CAN0_6_IRQn = 82, /*!< MCAN SR6 Interrupt */
\r
177 CAN0_7_IRQn = 83, /*!< MCAN SR7 Interrupt */
\r
178 USIC0_0_IRQn = 84, /*!< USIC0 SR0 Interrupt */
\r
179 USIC0_1_IRQn = 85, /*!< USIC0 SR1 Interrupt */
\r
180 USIC0_2_IRQn = 86, /*!< USIC0 SR2 Interrupt */
\r
181 USIC0_3_IRQn = 87, /*!< USIC0 SR3 Interrupt */
\r
182 USIC0_4_IRQn = 88, /*!< USIC0 SR4 Interrupt */
\r
183 USIC0_5_IRQn = 89, /*!< USIC0 SR5 Interrupt */
\r
184 USIC1_0_IRQn = 90, /*!< USIC1 SR0 Interrupt */
\r
185 USIC1_1_IRQn = 91, /*!< USIC1 SR1 Interrupt */
\r
186 USIC1_2_IRQn = 92, /*!< USIC1 SR2 Interrupt */
\r
187 USIC1_3_IRQn = 93, /*!< USIC1 SR3 Interrupt */
\r
188 USIC1_4_IRQn = 94, /*!< USIC1 SR4 Interrupt */
\r
189 USIC1_5_IRQn = 95, /*!< USIC1 SR5 Interrupt */
\r
190 USIC2_0_IRQn = 96, /*!< USIC2 SR0 Interrupt */
\r
191 USIC2_1_IRQn = 97, /*!< USIC2 SR1 Interrupt */
\r
192 USIC2_2_IRQn = 98, /*!< USIC2 SR2 Interrupt */
\r
193 USIC2_3_IRQn = 99, /*!< USIC2 SR3 Interrupt */
\r
194 USIC2_4_IRQn = 100, /*!< USIC2 SR4 Interrupt */
\r
195 USIC2_5_IRQn = 101, /*!< USIC2 SR5 Interrupt */
\r
196 LEDTS0_0_IRQn = 102, /*!< LEDTSU SR0 Interrupt */
\r
197 FCE0_0_IRQn = 104, /*!< FCE SR0 Interrupt */
\r
198 GPDMA0_0_IRQn = 105, /*!< GPDMA SR0 Interrupt */
\r
199 SDMMC0_0_IRQn = 106, /*!< MMCI SR0 Interrupt */
\r
200 USB0_0_IRQn = 107, /*!< USB SR0 Interrupt */
\r
201 ETH0_0_IRQn = 108, /*!< ETH SR0 Interrupt */
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202 GPDMA1_0_IRQn = 110 /*!< GPDMA1 SR0 Interrupt */
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207 * ==========================================================================
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208 * ----------- Processor and Core Peripheral Section ------------------------
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209 * ==========================================================================
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212 /** Macro to write new value to the bits in register */
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213 #define WR_REG(reg, mask, pos, val) { \
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215 reg |= (val << pos) & mask;\
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218 /** Macro to read the bits in register */
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219 #define RD_REG(reg, mask, pos) (((reg)&mask) >> pos)
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220 /** Macro to set the particular bit in register */
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221 #define SET_BIT(reg, pos) (reg) |= (1U<<pos)
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222 /** Macro to clear the particular bit in register */
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223 #define CLR_BIT(reg, pos) (reg) &= ~(1U<<pos)
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225 #include <core_cm4.h> /* Cortex-M4 processor and core peripherals */
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227 /******************************************************************************/
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228 /* Device Specific Peripheral registers structures */
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229 /******************************************************************************/
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231 /***************************************************************************/
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233 /***************************************************************************/
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236 *CAN GLOBAL registers
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239 __IO uint32_t CLC; /*!<CAN Clock Control Register Offset 0x0000*/
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240 __I uint32_t RESERVED1;
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241 __I uint32_t ID; /*!<Module Identification Register Offset 0x0008*/
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242 __IO uint32_t FDR; /*!<CAN Fractional Divider Register Offset 0x000C*/
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243 __I uint32_t RESERVED2[60];
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244 __I uint32_t LIST[8]; /*!<List Register 0 Offset 0x0100*/
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245 __I uint32_t RESERVED3[8];
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246 __IO uint32_t MSPND[8]; /*!<Message Pending Register 0 Offset 0x0140*/
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247 __I uint32_t RESERVED4[8];
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248 __I uint32_t MSID[8]; /*!<Message Index Register 0 Offset 0x0180*/
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249 __I uint32_t RESERVED5[8];
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250 __IO uint32_t MSIMASK; /*!<Message Index Mask Register Offset 0x01C0*/
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251 __IO uint32_t PANCTR; /*!<Panel Control Register Offset 0x01C4*/
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252 __IO uint32_t MCR; /*!<Module Control Register Offset 0x01C8*/
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253 __O uint32_t MITR; /*!<Module Interrupt Trigger Register Offset 0x01CC*/
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254 }CAN_GLOBAL_TypeDef;
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257 *CAN NODE registers
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260 __IO uint32_t NCR; /*!<Node 0 Control Register Offset 0x0200*/
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261 __IO uint32_t NSR; /*!<Node 0 Status Register Offset 0x0204*/
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262 __IO uint32_t NIPR; /*!<Node 0 Interrupt Pointer Register Offset 0x0208*/
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263 __IO uint32_t NPCR; /*!<Node 0 Port Control Register Offset 0x020C*/
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264 __IO uint32_t NBTR; /*!<Node 0 Bit Timing Register Offset 0x0210*/
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265 __IO uint32_t NECNT; /*!<Node 0 Error Counter Register Offset 0x0214*/
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266 __IO uint32_t NFCR; /*!<Node 0 Frame Counter Register Offset 0x0218*/
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273 __IO uint32_t MOFCR; /*!<Message Object 0 Function Control Register Offset 0x1000*/
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274 __IO uint32_t MOFGPR; /*!<Message Object 0 FIFO/Gateway Pointer Register Offset 0x1004*/
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275 __IO uint32_t MOIPR; /*!<Message Object 0 Interrupt Pointer Register Offset 0x1008*/
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276 __IO uint32_t MOAMR; /*!<Message Object 0 Acceptance Mask Register Offset 0x100C*/
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277 __IO uint32_t MODATAL; /*!<Message Object 0 Data Register Low Offset 0x1010*/
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278 __IO uint32_t MODATAH; /*!<Message Object 0 Data Register High Offset 0x1014*/
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279 __IO uint32_t MOAR; /*!<Message Object 0 Arbitration Register Offset 0x1018*/
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282 __O uint32_t MOCTR; /*!<Message Object 0 Control Register Offset 0x101C*/
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283 __I uint32_t MOSTAT; /*!<Message Object 0 Status Register Offset 0x101C*/
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287 #define CAN_BASE ((uint32_t)0x48014000U)
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288 #define CAN_GLOBAL_BASE (0x0000U)
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289 #define CAN_NODE0_BASE (0x0200U)
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290 #define CAN_NODE1_BASE (0x0300U)
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291 #define CAN_NODE2_BASE (0x0400U)
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292 #define CAN_MO0_BASE (0x1000U)
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293 #define CAN_MO1_BASE (0x1020U)
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294 #define CAN_MO2_BASE (0x1040U)
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295 #define CAN_MO3_BASE (0x1060U)
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296 #define CAN_MO4_BASE (0x1080U)
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297 #define CAN_MO5_BASE (0x10A0U)
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298 #define CAN_MO6_BASE (0x10C0U)
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299 #define CAN_MO7_BASE (0x10E0U)
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300 #define CAN_MO8_BASE (0x1100U)
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301 #define CAN_MO9_BASE (0x1120U)
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302 #define CAN_MO10_BASE (0x1140U)
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303 #define CAN_MO11_BASE (0x1160U)
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304 #define CAN_MO12_BASE (0x1180U)
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305 #define CAN_MO13_BASE (0x11A0U)
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306 #define CAN_MO14_BASE (0x11C0U)
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307 #define CAN_MO15_BASE (0x11E0U)
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308 #define CAN_MO16_BASE (0x1200U)
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309 #define CAN_MO17_BASE (0x1220U)
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310 #define CAN_MO18_BASE (0x1240U)
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311 #define CAN_MO19_BASE (0x1260U)
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312 #define CAN_MO20_BASE (0x1280U)
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313 #define CAN_MO21_BASE (0x12A0U)
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314 #define CAN_MO22_BASE (0x12C0U)
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315 #define CAN_MO23_BASE (0x12E0U)
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316 #define CAN_MO24_BASE (0x1300U)
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317 #define CAN_MO25_BASE (0x1320U)
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318 #define CAN_MO26_BASE (0x1340U)
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319 #define CAN_MO27_BASE (0x1360U)
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320 #define CAN_MO28_BASE (0x1380U)
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321 #define CAN_MO29_BASE (0x13A0U)
\r
322 #define CAN_MO30_BASE (0x13C0U)
\r
323 #define CAN_MO31_BASE (0x13E0U)
\r
324 #define CAN_MO32_BASE (0x1400U)
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325 #define CAN_MO33_BASE (0x1420U)
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326 #define CAN_MO34_BASE (0x1440U)
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327 #define CAN_MO35_BASE (0x1460U)
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328 #define CAN_MO36_BASE (0x1480U)
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329 #define CAN_MO37_BASE (0x14A0U)
\r
330 #define CAN_MO38_BASE (0x14C0U)
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331 #define CAN_MO39_BASE (0x14E0U)
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332 #define CAN_MO40_BASE (0x1500U)
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333 #define CAN_MO41_BASE (0x1520U)
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334 #define CAN_MO42_BASE (0x1540U)
\r
335 #define CAN_MO43_BASE (0x1560U)
\r
336 #define CAN_MO44_BASE (0x1580U)
\r
337 #define CAN_MO45_BASE (0x15A0U)
\r
338 #define CAN_MO46_BASE (0x15C0U)
\r
339 #define CAN_MO47_BASE (0x15E0U)
\r
340 #define CAN_MO48_BASE (0x1600U)
\r
341 #define CAN_MO49_BASE (0x1620U)
\r
342 #define CAN_MO50_BASE (0x1640U)
\r
343 #define CAN_MO51_BASE (0x1660U)
\r
344 #define CAN_MO52_BASE (0x1680U)
\r
345 #define CAN_MO53_BASE (0x16A0U)
\r
346 #define CAN_MO54_BASE (0x16C0U)
\r
347 #define CAN_MO55_BASE (0x16E0U)
\r
348 #define CAN_MO56_BASE (0x1700U)
\r
349 #define CAN_MO57_BASE (0x1720U)
\r
350 #define CAN_MO58_BASE (0x1740U)
\r
351 #define CAN_MO59_BASE (0x1760U)
\r
352 #define CAN_MO60_BASE (0x1780U)
\r
353 #define CAN_MO61_BASE (0x17A0U)
\r
354 #define CAN_MO62_BASE (0x17C0U)
\r
355 #define CAN_MO63_BASE (0x17E0U)
\r
356 /***************************************************************************/
\r
357 /* Peripheral Declaration */
\r
358 /***************************************************************************/
\r
359 #define CAN ((CAN_GLOBAL_TypeDef*)(CAN_BASE + CAN_GLOBAL_BASE))
\r
360 #define CAN_NODE0 ((CAN_NODE_TypeDef*)(CAN_BASE + CAN_NODE0_BASE))
\r
361 #define CAN_NODE1 ((CAN_NODE_TypeDef*)(CAN_BASE + CAN_NODE1_BASE))
\r
362 #define CAN_NODE2 ((CAN_NODE_TypeDef*)(CAN_BASE + CAN_NODE2_BASE))
\r
363 #define CAN_MO0 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO0_BASE))
\r
364 #define CAN_MO1 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO1_BASE))
\r
365 #define CAN_MO2 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO2_BASE))
\r
366 #define CAN_MO3 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO3_BASE))
\r
367 #define CAN_MO4 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO4_BASE))
\r
368 #define CAN_MO5 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO5_BASE))
\r
369 #define CAN_MO6 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO6_BASE))
\r
370 #define CAN_MO7 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO7_BASE))
\r
371 #define CAN_MO8 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO8_BASE))
\r
372 #define CAN_MO9 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO9_BASE))
\r
373 #define CAN_MO10 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO10_BASE))
\r
374 #define CAN_MO11 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO11_BASE))
\r
375 #define CAN_MO12 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO12_BASE))
\r
376 #define CAN_MO13 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO13_BASE))
\r
377 #define CAN_MO14 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO14_BASE))
\r
378 #define CAN_MO15 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO15_BASE))
\r
379 #define CAN_MO16 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO16_BASE))
\r
380 #define CAN_MO17 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO17_BASE))
\r
381 #define CAN_MO18 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO18_BASE))
\r
382 #define CAN_MO19 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO19_BASE))
\r
383 #define CAN_MO20 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO20_BASE))
\r
384 #define CAN_MO21 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO21_BASE))
\r
385 #define CAN_MO22 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO22_BASE))
\r
386 #define CAN_MO23 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO23_BASE))
\r
387 #define CAN_MO24 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO24_BASE))
\r
388 #define CAN_MO25 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO25_BASE))
\r
389 #define CAN_MO26 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO26_BASE))
\r
390 #define CAN_MO27 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO27_BASE))
\r
391 #define CAN_MO28 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO28_BASE))
\r
392 #define CAN_MO29 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO29_BASE))
\r
393 #define CAN_MO30 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO30_BASE))
\r
394 #define CAN_MO31 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO31_BASE))
\r
395 #define CAN_MO32 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO32_BASE))
\r
396 #define CAN_MO33 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO33_BASE))
\r
397 #define CAN_MO34 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO34_BASE))
\r
398 #define CAN_MO35 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO35_BASE))
\r
399 #define CAN_MO36 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO36_BASE))
\r
400 #define CAN_MO37 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO37_BASE))
\r
401 #define CAN_MO38 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO38_BASE))
\r
402 #define CAN_MO39 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO39_BASE))
\r
403 #define CAN_MO40 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO40_BASE))
\r
404 #define CAN_MO41 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO41_BASE))
\r
405 #define CAN_MO42 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO42_BASE))
\r
406 #define CAN_MO43 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO43_BASE))
\r
407 #define CAN_MO44 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO44_BASE))
\r
408 #define CAN_MO45 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO45_BASE))
\r
409 #define CAN_MO46 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO46_BASE))
\r
410 #define CAN_MO47 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO47_BASE))
\r
411 #define CAN_MO48 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO48_BASE))
\r
412 #define CAN_MO49 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO49_BASE))
\r
413 #define CAN_MO50 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO50_BASE))
\r
414 #define CAN_MO51 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO51_BASE))
\r
415 #define CAN_MO52 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO52_BASE))
\r
416 #define CAN_MO53 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO53_BASE))
\r
417 #define CAN_MO54 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO54_BASE))
\r
418 #define CAN_MO55 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO55_BASE))
\r
419 #define CAN_MO56 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO56_BASE))
\r
420 #define CAN_MO57 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO57_BASE))
\r
421 #define CAN_MO58 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO58_BASE))
\r
422 #define CAN_MO59 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO59_BASE))
\r
423 #define CAN_MO60 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO60_BASE))
\r
424 #define CAN_MO61 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO61_BASE))
\r
425 #define CAN_MO62 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO62_BASE))
\r
426 #define CAN_MO63 ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO63_BASE))
\r
428 /***************************************************************************/
\r
430 /***************************************************************************/
\r
433 *CAPCOM4 Global Registers
\r
436 __IO uint32_t GCTRL; /*!<Global Control Register Offset 0x0000*/
\r
437 __I uint32_t GSTAT; /*!<Global Status Register Offset 0x0004*/
\r
438 __O uint32_t GIDLS; /*!<Global Idle Set Offset 0x0008*/
\r
439 __O uint32_t GIDLC; /*!<Global Idle Clear Offset 0x000C*/
\r
440 __O uint32_t GCSS; /*!<Global Channel Set Offset 0x0010*/
\r
441 __O uint32_t GCSC; /*!<Global Channel Clear Offset 0x0014*/
\r
442 __I uint32_t GCST; /*!<Global Channel Status Offset 0x0018*/
\r
443 __I uint32_t RESERVED1[13];
\r
444 __I uint32_t ECRD; /*!<Extended Capture Mode Read Offset 0x0050*/
\r
445 __I uint32_t RESERVED2[11];
\r
446 __I uint32_t MIDR; /*!<Module Identification Offset 0x0080*/
\r
447 }CCU4_GLOBAL_TypeDef;
\r
453 __IO uint32_t INS; /*!<Input Selector Configuration Offset 0x0100*/
\r
454 __IO uint32_t CMC; /*!<Connection Matrix Control Offset 0x0104*/
\r
455 __I uint32_t TCST; /*!<Slice Timer Status Offset 0x0108*/
\r
456 __O uint32_t TCSET; /*!<Slice Timer Run Set Offset 0x010C*/
\r
457 __O uint32_t TCCLR; /*!<Slice Timer Clear Offset 0x0110*/
\r
458 __IO uint32_t TC; /*!<Slice Timer Control Offset 0x0114*/
\r
459 __IO uint32_t PSL; /*!<Passive Level Config Offset 0x0118*/
\r
460 __I uint32_t DIT; /*!<Dither Config Offset 0x011C*/
\r
461 __IO uint32_t DITS; /*!<Dither Shadow Register Offset 0x0120*/
\r
462 __IO uint32_t PSC; /*!<Prescaler Control Offset 0x0124*/
\r
463 __IO uint32_t FPC; /*!<Floating Prescaler Control Offset 0x0128*/
\r
464 __IO uint32_t FPCS; /*!<Floating Prescaler Shadow Offset 0x012C*/
\r
465 __I uint32_t PR; /*!<Timer Period Value Offset 0x0130*/
\r
466 __IO uint32_t PRS; /*!<Timer Shadow Period Value Offset 0x0134*/
\r
467 __I uint32_t CR; /*!<Timer Compare Value Offset 0x0138*/
\r
468 __IO uint32_t CRS; /*!<Timer Shadow Compare Value Offset 0x013C*/
\r
469 __I uint32_t RESERVED1[12];
\r
470 __IO uint32_t TIMER; /*!<Timer Value Offset 0x0170*/
\r
471 __I uint32_t CV[4]; /*!<Capture Register 0 Offset 0x0174*/
\r
472 __I uint32_t RESERVED2[7];
\r
473 __I uint32_t INTS; /*!<Interrupt Status Offset 0x01A0*/
\r
474 __IO uint32_t INTE; /*!<Interrupt Enable Control Offset 0x01A4*/
\r
475 __IO uint32_t SRS; /*!<Service Request Selector Offset 0x01A8*/
\r
476 __O uint32_t SWS; /*!<Interrupt Status Set Offset 0x01AC*/
\r
477 __O uint32_t SWR; /*!<Interrupt Status Clear Offset 0x01B0*/
\r
480 #define CCU40_BASE ((uint32_t)0x4000C000U)
\r
481 #define CCU41_BASE ((uint32_t)0x40010000U)
\r
482 #define CCU42_BASE ((uint32_t)0x40014000U)
\r
483 #define CCU43_BASE ((uint32_t)0x48004000U)
\r
484 #define CCU4_GLOBAL_BASE (0x0000U)
\r
485 #define CCU40_CC40_BASE (0x0100U)
\r
486 #define CCU40_CC41_BASE (0x0200U)
\r
487 #define CCU40_CC42_BASE (0x0300U)
\r
488 #define CCU40_CC43_BASE (0x0400U)
\r
489 /***************************************************************************/
\r
490 /* Peripheral Declaration */
\r
491 /***************************************************************************/
\r
492 #define CCU40 ((CCU4_GLOBAL_TypeDef*)(CCU40_BASE + CCU4_GLOBAL_BASE))
\r
493 #define CCU40_CC40 ((CCU4_CC4_TypeDef*)(CCU40_BASE + CCU40_CC40_BASE))
\r
494 #define CCU40_CC41 ((CCU4_CC4_TypeDef*)(CCU40_BASE + CCU40_CC41_BASE))
\r
495 #define CCU40_CC42 ((CCU4_CC4_TypeDef*)(CCU40_BASE + CCU40_CC42_BASE))
\r
496 #define CCU40_CC43 ((CCU4_CC4_TypeDef*)(CCU40_BASE + CCU40_CC43_BASE))
\r
497 #define CCU41 ((CCU4_GLOBAL_TypeDef*)(CCU41_BASE + CCU4_GLOBAL_BASE))
\r
498 #define CCU41_CC40 ((CCU4_CC4_TypeDef*)(CCU41_BASE + CCU40_CC40_BASE))
\r
499 #define CCU41_CC41 ((CCU4_CC4_TypeDef*)(CCU41_BASE + CCU40_CC41_BASE))
\r
500 #define CCU41_CC42 ((CCU4_CC4_TypeDef*)(CCU41_BASE + CCU40_CC42_BASE))
\r
501 #define CCU41_CC43 ((CCU4_CC4_TypeDef*)(CCU41_BASE + CCU40_CC43_BASE))
\r
502 #define CCU42 ((CCU4_GLOBAL_TypeDef*)(CCU42_BASE + CCU4_GLOBAL_BASE))
\r
503 #define CCU42_CC40 ((CCU4_CC4_TypeDef*)(CCU42_BASE + CCU40_CC40_BASE))
\r
504 #define CCU42_CC41 ((CCU4_CC4_TypeDef*)(CCU42_BASE + CCU40_CC41_BASE))
\r
505 #define CCU42_CC42 ((CCU4_CC4_TypeDef*)(CCU42_BASE + CCU40_CC42_BASE))
\r
506 #define CCU42_CC43 ((CCU4_CC4_TypeDef*)(CCU42_BASE + CCU40_CC43_BASE))
\r
507 #define CCU43 ((CCU4_GLOBAL_TypeDef*)(CCU43_BASE + CCU4_GLOBAL_BASE))
\r
508 #define CCU43_CC40 ((CCU4_CC4_TypeDef*)(CCU43_BASE + CCU40_CC40_BASE))
\r
509 #define CCU43_CC41 ((CCU4_CC4_TypeDef*)(CCU43_BASE + CCU40_CC41_BASE))
\r
510 #define CCU43_CC42 ((CCU4_CC4_TypeDef*)(CCU43_BASE + CCU40_CC42_BASE))
\r
511 #define CCU43_CC43 ((CCU4_CC4_TypeDef*)(CCU43_BASE + CCU40_CC43_BASE))
\r
513 /***************************************************************************/
\r
515 /***************************************************************************/
\r
518 *CAPCOM8 Global Registers
\r
521 __IO uint32_t GCTRL; /*!<Global Control Register Offset 0x0000*/
\r
522 __I uint32_t GSTAT; /*!<Global Status Register Offset 0x0004*/
\r
523 __O uint32_t GIDLS; /*!<Global Idle Set Offset 0x0008*/
\r
524 __O uint32_t GIDLC; /*!<Global Idle Clear Offset 0x000C*/
\r
525 __O uint32_t GCSS; /*!<Global Channel Set Offset 0x0010*/
\r
526 __O uint32_t GCSC; /*!<Global Channel Clear Offset 0x0014*/
\r
527 __I uint32_t GCST; /*!<Global Channel status Offset 0x0018*/
\r
528 __IO uint32_t GPCHK; /*!<Parity Checker Configuration Offset 0x001C*/
\r
529 __I uint32_t RESERVED1[12];
\r
530 __I uint32_t ECRD; /*!<Extended Capture Mode Read Offset 0x0050*/
\r
531 __I uint32_t RESERVED2[11];
\r
532 __I uint32_t MIDR; /*!<Module Identification Offset 0x0080*/
\r
533 }CCU8_GLOBAL_TypeDef;
\r
539 __IO uint32_t INS; /*!<Input Selector Configuration Offset 0x0100*/
\r
540 __IO uint32_t CMC; /*!<Connection Matrix Control Offset 0x0104*/
\r
541 __I uint32_t TCST; /*!<Slice Timer Status Offset 0x0108*/
\r
542 __O uint32_t TCSET; /*!<Slice Timer Run Set Offset 0x010C*/
\r
543 __O uint32_t TCCLR; /*!<Slice Timer Clear Offset 0x0110*/
\r
544 __IO uint32_t TC; /*!<Slice Timer Control Offset 0x0114*/
\r
545 __IO uint32_t PSL; /*!<Passive Level Config Offset 0x0118*/
\r
546 __I uint32_t DIT; /*!<Dither Config Offset 0x011C*/
\r
547 __IO uint32_t DITS; /*!<Dither Shadow Register Offset 0x0120*/
\r
548 __IO uint32_t PSC; /*!<Prescaler Control Offset 0x0124*/
\r
549 __IO uint32_t FPC; /*!<Floating Prescaler Control Offset 0x0128*/
\r
550 __IO uint32_t FPCS; /*!<Floating Prescaler Shadow Offset 0x012C*/
\r
551 __I uint32_t PR; /*!<Timer Period Value Offset 0x0130*/
\r
552 __IO uint32_t PRS; /*!<Timer Shadow Period Value Offset 0x0134*/
\r
553 __I uint32_t CR1; /*!<Channel 1 Compare Value Offset 0x0138*/
\r
554 __IO uint32_t CR1S; /*!<Channel 1 Compare Shadow Value Offset 0x013C*/
\r
555 __I uint32_t CR2; /*!<Channel 2 Compare Value Offset 0x0140*/
\r
556 __IO uint32_t CR2S; /*!<Channel 2 Compare Shadow Value Offset 0x0144*/
\r
557 __IO uint32_t CHC; /*!<Channel Control Offset 0x0148*/
\r
558 __IO uint32_t DTC; /*!<Dead Time Control Offset 0x014C*/
\r
559 __IO uint32_t DC1R; /*!<Channel 1 Dead Time Values Offset 0x0150*/
\r
560 __IO uint32_t DC2R; /*!<Channel 2 Dead Time Values Offset 0x0154*/
\r
561 __I uint32_t RESERVED1[6];
\r
562 __IO uint32_t TIMER; /*!<Timer Value Offset 0x0170*/
\r
563 __I uint32_t CV[4]; /*!<Capture Register 0 Offset 0x0174*/
\r
564 __I uint32_t RESERVED2[7];
\r
565 __I uint32_t INTS; /*!<Interrupt Status Offset 0x01A0*/
\r
566 __IO uint32_t INTE; /*!<Interrupt Enable Control Offset 0x01A4*/
\r
567 __IO uint32_t SRS; /*!<Service Request Selector Offset 0x01A8*/
\r
568 __O uint32_t SWS; /*!<Interrupt Status Set Offset 0x01AC*/
\r
569 __O uint32_t SWR; /*!<Interrupt Status Clear Offset 0x01B0*/
\r
572 #define CCU80_BASE ((uint32_t)0x40020000U)
\r
573 #define CCU81_BASE ((uint32_t)0x40024000U)
\r
574 #define CCU8_GLOBAL_BASE (0x0000U)
\r
575 #define CCU80_CC80_BASE (0x0100U)
\r
576 #define CCU80_CC81_BASE (0x0200U)
\r
577 #define CCU80_CC82_BASE (0x0300U)
\r
578 #define CCU80_CC83_BASE (0x0400U)
\r
579 /***************************************************************************/
\r
580 /* Peripheral Declaration */
\r
581 /***************************************************************************/
\r
582 #define CCU80 ((CCU8_GLOBAL_TypeDef*)(CCU80_BASE + CCU8_GLOBAL_BASE))
\r
583 #define CCU80_CC80 ((CCU8_CC8_TypeDef*)(CCU80_BASE + CCU80_CC80_BASE))
\r
584 #define CCU80_CC81 ((CCU8_CC8_TypeDef*)(CCU80_BASE + CCU80_CC81_BASE))
\r
585 #define CCU80_CC82 ((CCU8_CC8_TypeDef*)(CCU80_BASE + CCU80_CC82_BASE))
\r
586 #define CCU80_CC83 ((CCU8_CC8_TypeDef*)(CCU80_BASE + CCU80_CC83_BASE))
\r
587 #define CCU81 ((CCU8_GLOBAL_TypeDef*)(CCU81_BASE + CCU8_GLOBAL_BASE))
\r
588 #define CCU81_CC80 ((CCU8_CC8_TypeDef*)(CCU81_BASE + CCU80_CC80_BASE))
\r
589 #define CCU81_CC81 ((CCU8_CC8_TypeDef*)(CCU81_BASE + CCU80_CC81_BASE))
\r
590 #define CCU81_CC82 ((CCU8_CC8_TypeDef*)(CCU81_BASE + CCU80_CC82_BASE))
\r
591 #define CCU81_CC83 ((CCU8_CC8_TypeDef*)(CCU81_BASE + CCU80_CC83_BASE))
\r
593 /***************************************************************************/
\r
595 /***************************************************************************/
\r
598 *DAC Kernel Registers
\r
601 __I uint32_t ID; /*!<Module Identification Register Offset 0x0000*/
\r
602 __IO uint32_t DAC0CFG0; /*!<DAC0 Configuration Register 0 Offset 0x0004*/
\r
603 __IO uint32_t DAC0CFG1; /*!<DAC0 Configuration Register 1 Offset 0x0008*/
\r
604 __IO uint32_t DAC1CFG0; /*!<DAC1 Configuration Register 0 Offset 0x000C*/
\r
605 __IO uint32_t DAC1CFG1; /*!<DAC1 Configuration Register 1 Offset 0x0010*/
\r
606 __IO uint32_t DAC0DATA; /*!<DAC0 Data Register Offset 0x0014*/
\r
607 __IO uint32_t DAC1DATA; /*!<DAC1 Data Register Offset 0x0018*/
\r
608 __IO uint32_t DAC01DATA; /*!<DAC01 Data Register Offset 0x001C*/
\r
609 __IO uint32_t DAC0PATL; /*!<DAC0 Lower Pattern Register Offset 0x0020*/
\r
610 __IO uint32_t DAC0PATH; /*!<DAC0 Higher Pattern Register Offset 0x0024*/
\r
611 __IO uint32_t DAC1PATL; /*!<DAC1 Lower Pattern Register Offset 0x0028*/
\r
612 __IO uint32_t DAC1PATH; /*!<DAC1 Higher Pattern Register Offset 0x002C*/
\r
613 }DAC_GLOBAL_TypeDef;
\r
615 #define DAC_BASE ((uint32_t)0x48018000U)
\r
616 #define DAC_GLOBAL_BASE (0x0000U)
\r
617 /***************************************************************************/
\r
618 /* Peripheral Declaration */
\r
619 /***************************************************************************/
\r
620 #define DAC ((DAC_GLOBAL_TypeDef*)(DAC_BASE + DAC_GLOBAL_BASE))
\r
622 /***************************************************************************/
\r
624 /***************************************************************************/
\r
630 __I uint32_t OVRSTAT; /*!<GPDMA Overrun Status Offset 0x0000*/
\r
631 __O uint32_t OVRCLR; /*!<GPDMA Overrun Clear Offset 0x0004*/
\r
632 __IO uint32_t SRSEL0; /*!<GPDMA Service Request Selection 0 Offset 0x0008*/
\r
633 __IO uint32_t SRSEL1; /*!<GPDMA Service Request Selection 1 Offset 0x000C*/
\r
634 __IO uint32_t LNEN; /*!<GPDMA Line Enable Offset 0x0010*/
\r
635 }DLR_GLOBAL_TypeDef;
\r
637 #define DLR_BASE ((uint32_t)0x50004900U)
\r
638 #define DLR_GLOBAL_BASE (0x0000U)
\r
639 /***************************************************************************/
\r
640 /* Peripheral Declaration */
\r
641 /***************************************************************************/
\r
642 #define DLR ((DLR_GLOBAL_TypeDef*)(DLR_BASE + DLR_GLOBAL_BASE))
\r
644 /***************************************************************************/
\r
646 /***************************************************************************/
\r
649 *Channel Related registers
\r
652 __IO uint32_t SAR; /*!<Source Address Register for Channel 0 Offset 0x0000*/
\r
653 __I uint32_t RESERVED1;
\r
654 __IO uint32_t DAR; /*!<Destination Address Register for Channel 0 Offset 0x0008*/
\r
655 __I uint32_t RESERVED2[3];
\r
656 __IO uint32_t CTLL; /*!<Control Register for Channel 0 Low Word Offset 0x0018*/
\r
657 __IO uint32_t CTLH; /*!<Control Register for Channel 0 High Word Offset 0x001C*/
\r
658 __I uint32_t RESERVED3[8];
\r
659 __IO uint32_t CFGL; /*!<Configuration Register for Channel 0 Low Word Offset 0x0040*/
\r
660 __IO uint32_t CFGH; /*!<Configuration Register for Channel 0 High Word Offset 0x0044*/
\r
661 }GPDMA1_CH_TypeDef;
\r
664 *GPDMA1 Global registers
\r
667 __IO uint32_t RAWTFR; /*!<Raw IntTfr Status Offset 0x02C0*/
\r
668 __I uint32_t RESERVED1;
\r
669 __IO uint32_t RAWBLOCK; /*!<Raw IntBlock Status Offset 0x02C8*/
\r
670 __I uint32_t RESERVED2;
\r
671 __IO uint32_t RAWSRCTRAN; /*!<Raw IntSrcTran Status Offset 0x02D0*/
\r
672 __I uint32_t RESERVED3;
\r
673 __IO uint32_t RAWDSTTRAN; /*!<Raw IntBlock Status Offset 0x02D8*/
\r
674 __I uint32_t RESERVED4;
\r
675 __IO uint32_t RAWERR; /*!<Raw IntErr Status Offset 0x02E0*/
\r
676 __I uint32_t RESERVED5;
\r
677 __I uint32_t STATUSTFR; /*!<IntTfr Status Offset 0x02E8*/
\r
678 __I uint32_t RESERVED6;
\r
679 __I uint32_t STATUSBLOCK; /*!<IntBlock Status Offset 0x02F0*/
\r
680 __I uint32_t RESERVED7;
\r
681 __I uint32_t STATUSSRCTRAN; /*!<IntSrcTran Status Offset 0x02F8*/
\r
682 __I uint32_t RESERVED8;
\r
683 __I uint32_t STATUSDSTTRAN; /*!<IntBlock Status Offset 0x0300*/
\r
684 __I uint32_t RESERVED9;
\r
685 __I uint32_t STATUSERR; /*!<IntErr Status Offset 0x0308*/
\r
686 __I uint32_t RESERVED10;
\r
687 __IO uint32_t MASKTFR; /*!<Mask for Raw IntTfr Status Offset 0x0310*/
\r
688 __I uint32_t RESERVED11;
\r
689 __IO uint32_t MASKBLOCK; /*!<Mask for Raw IntBlock Status Offset 0x0318*/
\r
690 __I uint32_t RESERVED12;
\r
691 __IO uint32_t MASKSRCTRAN; /*!<Mask for Raw IntSrcTran Status Offset 0x0320*/
\r
692 __I uint32_t RESERVED13;
\r
693 __IO uint32_t MASKDSTTRAN; /*!<Mask for Raw IntBlock Status Offset 0x0328*/
\r
694 __I uint32_t RESERVED14;
\r
695 __IO uint32_t MASKERR; /*!<Mask for Raw IntErr Status Offset 0x0330*/
\r
696 __I uint32_t RESERVED15;
\r
697 __O uint32_t CLEARTFR; /*!<IntTfr Status Offset 0x0338*/
\r
698 __I uint32_t RESERVED16;
\r
699 __O uint32_t CLEARBLOCK; /*!<IntBlock Status Offset 0x0340*/
\r
700 __I uint32_t RESERVED17;
\r
701 __O uint32_t CLEARSRCTRAN; /*!<IntSrcTran Status Offset 0x0348*/
\r
702 __I uint32_t RESERVED18;
\r
703 __O uint32_t CLEARDSTTRAN; /*!<IntBlock Status Offset 0x0350*/
\r
704 __I uint32_t RESERVED19;
\r
705 __O uint32_t CLEARERR; /*!<IntErr Status Offset 0x0358*/
\r
706 __I uint32_t RESERVED20;
\r
707 __I uint32_t STATUSINT; /*!<Combined Interrupt Status Register Offset 0x0360*/
\r
708 __I uint32_t RESERVED21;
\r
709 __IO uint32_t REQSRCREG; /*!<Source Software Transaction Request Register Offset 0x0368*/
\r
710 __I uint32_t RESERVED22;
\r
711 __IO uint32_t REQDSTREG; /*!<Destination Software Transaction Request Register Offset 0x0370*/
\r
712 __I uint32_t RESERVED23;
\r
713 __IO uint32_t SGLREQSRCREG; /*!<Single Source Transaction Request Register Offset 0x0378*/
\r
714 __I uint32_t RESERVED24;
\r
715 __IO uint32_t SGLREQDSTREG; /*!<Single Destination Transaction Request Register Offset 0x0380*/
\r
716 __I uint32_t RESERVED25;
\r
717 __IO uint32_t LSTSRCREG; /*!<Last Source Transaction Request Register Offset 0x0388*/
\r
718 __I uint32_t RESERVED26;
\r
719 __IO uint32_t LSTDSTREG; /*!<Last Destination Transaction Request Register Offset 0x0390*/
\r
720 __I uint32_t RESERVED27;
\r
721 __IO uint32_t DMACFGREG; /*!<GPDMA Configuration Register Offset 0x0398*/
\r
722 __I uint32_t RESERVED28;
\r
723 __IO uint32_t CHENREG; /*!<GPDMA Channel Enable Register Offset 0x03A0*/
\r
724 __I uint32_t RESERVED29;
\r
725 __I uint32_t ID; /*!<GPDMA1 ID Register Offset 0x03A8*/
\r
726 __I uint32_t RESERVED30[19];
\r
727 __I uint32_t TYPE; /*!<GPDMA Component Type Offset 0x03F8*/
\r
728 __I uint32_t VERSION; /*!<DMA Component Version Offset 0x03FC*/
\r
729 }GPDMA1_GLOBAL_TypeDef;
\r
731 #define GPDMA1_BASE ((uint32_t)0x50018000U)
\r
732 #define GPDMA1_CH0_BASE (0x0000U)
\r
733 #define GPDMA1_CH1_BASE (0x0058U)
\r
734 #define GPDMA1_CH2_BASE (0x00B0U)
\r
735 #define GPDMA1_CH3_BASE (0x0108U)
\r
736 #define GPDMA1_GLOBAL_BASE (0x02C0U)
\r
737 /***************************************************************************/
\r
738 /* Peripheral Declaration */
\r
739 /***************************************************************************/
\r
740 #define GPDMA1_CH0 ((GPDMA1_CH_TypeDef*)(GPDMA1_BASE + GPDMA1_CH0_BASE))
\r
741 #define GPDMA1_CH1 ((GPDMA1_CH_TypeDef*)(GPDMA1_BASE + GPDMA1_CH1_BASE))
\r
742 #define GPDMA1_CH2 ((GPDMA1_CH_TypeDef*)(GPDMA1_BASE + GPDMA1_CH2_BASE))
\r
743 #define GPDMA1_CH3 ((GPDMA1_CH_TypeDef*)(GPDMA1_BASE + GPDMA1_CH3_BASE))
\r
744 #define GPDMA1 ((GPDMA1_GLOBAL_TypeDef*)(GPDMA1_BASE + GPDMA1_GLOBAL_BASE))
\r
746 /***************************************************************************/
\r
748 /***************************************************************************/
\r
751 *Channel Related registers
\r
754 __IO uint32_t SAR; /*!<Source Address Register for Channel 0 Offset 0x0000*/
\r
755 __I uint32_t RESERVED1;
\r
756 __IO uint32_t DAR; /*!<Destination Address Register for Channel 0 Offset 0x0008*/
\r
757 __I uint32_t RESERVED2;
\r
758 __IO uint32_t LLP; /*!<Linked List Pointer Register for Channel 0 Offset 0x0010*/
\r
759 __I uint32_t RESERVED3;
\r
760 __IO uint32_t CTLL; /*!<Control Register for Channel 0 Low Word Offset 0x0018*/
\r
761 __IO uint32_t CTLH; /*!<Control Register for Channel 0 High Word Offset 0x001C*/
\r
762 __IO uint32_t SSTAT; /*!<Source Status Register for Channel 0 Offset 0x0020*/
\r
763 __I uint32_t RESERVED4;
\r
764 __IO uint32_t DSTAT; /*!<Destination Status Register for Channel 0 Offset 0x0028*/
\r
765 __I uint32_t RESERVED5;
\r
766 __IO uint32_t SSTATAR; /*!<Source Status Address Register for Channel 0 Offset 0x0030*/
\r
767 __I uint32_t RESERVED6;
\r
768 __IO uint32_t DSTATAR; /*!<Destination Status Address Register for Channel 0 Offset 0x0038*/
\r
769 __I uint32_t RESERVED7;
\r
770 __IO uint32_t CFGL; /*!<Configuration Register for Channel 0 Low Word Offset 0x0040*/
\r
771 __IO uint32_t CFGH; /*!<Configuration Register for Channel 0 High Word Offset 0x0044*/
\r
772 __IO uint32_t SGR; /*!<Source Gather Register for Channel 0 Offset 0x0048*/
\r
773 __I uint32_t RESERVED8;
\r
774 __IO uint32_t DSR; /*!<Destination Scatter Register for Channel 0 Offset 0x0050*/
\r
775 }GPDMA0_CH_TypeDef;
\r
778 *GPDMA0 Global registers
\r
781 __IO uint32_t RAWTFR; /*!<Raw IntTfr Status Offset 0x02C0*/
\r
782 __I uint32_t RESERVED1;
\r
783 __IO uint32_t RAWBLOCK; /*!<Raw IntBlock Status Offset 0x02C8*/
\r
784 __I uint32_t RESERVED2;
\r
785 __IO uint32_t RAWSRCTRAN; /*!<Raw IntSrcTran Status Offset 0x02D0*/
\r
786 __I uint32_t RESERVED3;
\r
787 __IO uint32_t RAWDSTTRAN; /*!<Raw IntBlock Status Offset 0x02D8*/
\r
788 __I uint32_t RESERVED4;
\r
789 __IO uint32_t RAWERR; /*!<Raw IntErr Status Offset 0x02E0*/
\r
790 __I uint32_t RESERVED5;
\r
791 __I uint32_t STATUSTFR; /*!<IntTfr Status Offset 0x02E8*/
\r
792 __I uint32_t RESERVED6;
\r
793 __I uint32_t STATUSBLOCK; /*!<IntBlock Status Offset 0x02F0*/
\r
794 __I uint32_t RESERVED7;
\r
795 __I uint32_t STATUSSRCTRAN; /*!<IntSrcTran Status Offset 0x02F8*/
\r
796 __I uint32_t RESERVED8;
\r
797 __I uint32_t STATUSDSTTRAN; /*!<IntBlock Status Offset 0x0300*/
\r
798 __I uint32_t RESERVED9;
\r
799 __I uint32_t STATUSERR; /*!<IntErr Status Offset 0x0308*/
\r
800 __I uint32_t RESERVED10;
\r
801 __IO uint32_t MASKTFR; /*!<Mask for Raw IntTfr Status Offset 0x0310*/
\r
802 __I uint32_t RESERVED11;
\r
803 __IO uint32_t MASKBLOCK; /*!<Mask for Raw IntBlock Status Offset 0x0318*/
\r
804 __I uint32_t RESERVED12;
\r
805 __IO uint32_t MASKSRCTRAN; /*!<Mask for Raw IntSrcTran Status Offset 0x0320*/
\r
806 __I uint32_t RESERVED13;
\r
807 __IO uint32_t MASKDSTTRAN; /*!<Mask for Raw IntBlock Status Offset 0x0328*/
\r
808 __I uint32_t RESERVED14;
\r
809 __IO uint32_t MASKERR; /*!<Mask for Raw IntErr Status Offset 0x0330*/
\r
810 __I uint32_t RESERVED15;
\r
811 __O uint32_t CLEARTFR; /*!<IntTfr Status Offset 0x0338*/
\r
812 __I uint32_t RESERVED16;
\r
813 __O uint32_t CLEARBLOCK; /*!<IntBlock Status Offset 0x0340*/
\r
814 __I uint32_t RESERVED17;
\r
815 __O uint32_t CLEARSRCTRAN; /*!<IntSrcTran Status Offset 0x0348*/
\r
816 __I uint32_t RESERVED18;
\r
817 __O uint32_t CLEARDSTTRAN; /*!<IntBlock Status Offset 0x0350*/
\r
818 __I uint32_t RESERVED19;
\r
819 __O uint32_t CLEARERR; /*!<IntErr Status Offset 0x0358*/
\r
820 __I uint32_t RESERVED20;
\r
821 __I uint32_t STATUSINT; /*!<Combined Interrupt Status Register Offset 0x0360*/
\r
822 __I uint32_t RESERVED21;
\r
823 __IO uint32_t REQSRCREG; /*!<Source Software Transaction Request Register Offset 0x0368*/
\r
824 __I uint32_t RESERVED22;
\r
825 __IO uint32_t REQDSTREG; /*!<Destination Software Transaction Request Register Offset 0x0370*/
\r
826 __I uint32_t RESERVED23;
\r
827 __IO uint32_t SGLREQSRCREG; /*!<Single Source Transaction Request Register Offset 0x0378*/
\r
828 __I uint32_t RESERVED24;
\r
829 __IO uint32_t SGLREQDSTREG; /*!<Single Destination Transaction Request Register Offset 0x0380*/
\r
830 __I uint32_t RESERVED25;
\r
831 __IO uint32_t LSTSRCREG; /*!<Last Source Transaction Request Register Offset 0x0388*/
\r
832 __I uint32_t RESERVED26;
\r
833 __IO uint32_t LSTDSTREG; /*!<Last Destination Transaction Request Register Offset 0x0390*/
\r
834 __I uint32_t RESERVED27;
\r
835 __IO uint32_t DMACFGREG; /*!<GPDMA Configuration Register Offset 0x0398*/
\r
836 __I uint32_t RESERVED28;
\r
837 __IO uint32_t CHENREG; /*!<GPDMA Channel Enable Register Offset 0x03A0*/
\r
838 __I uint32_t RESERVED29;
\r
839 __I uint32_t ID; /*!<GPDMA0 ID Register Offset 0x03A8*/
\r
840 __I uint32_t RESERVED30[19];
\r
841 __I uint32_t TYPE; /*!<GPDMA Component Type Offset 0x03F8*/
\r
842 __I uint32_t VERSION; /*!<DMA Component Version Offset 0x03FC*/
\r
843 }GPDMA0_GLOBAL_TypeDef;
\r
845 #define GPDMA0_BASE ((uint32_t)0x50014000U)
\r
846 #define GPDMA0_CH0_BASE (0x0000U)
\r
847 #define GPDMA0_CH1_BASE (0x0058U)
\r
848 #define GPDMA0_CH2_BASE (0x00B0U)
\r
849 #define GPDMA0_CH3_BASE (0x0108U)
\r
850 #define GPDMA0_CH4_BASE (0x0160U)
\r
851 #define GPDMA0_CH5_BASE (0x01B8U)
\r
852 #define GPDMA0_CH6_BASE (0x0210U)
\r
853 #define GPDMA0_CH7_BASE (0x0268U)
\r
854 #define GPDMA0_GLOBAL_BASE (0x02C0U)
\r
855 /***************************************************************************/
\r
856 /* Peripheral Declaration */
\r
857 /***************************************************************************/
\r
858 #define GPDMA0_CH0 ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH0_BASE))
\r
859 #define GPDMA0_CH1 ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH1_BASE))
\r
860 #define GPDMA0_CH2 ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH2_BASE))
\r
861 #define GPDMA0_CH3 ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH3_BASE))
\r
862 #define GPDMA0_CH4 ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH4_BASE))
\r
863 #define GPDMA0_CH5 ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH5_BASE))
\r
864 #define GPDMA0_CH6 ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH6_BASE))
\r
865 #define GPDMA0_CH7 ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH7_BASE))
\r
866 #define GPDMA0 ((GPDMA0_GLOBAL_TypeDef*)(GPDMA0_BASE + GPDMA0_GLOBAL_BASE))
\r
868 /***************************************************************************/
\r
870 /***************************************************************************/
\r
873 *DSD Global Registers
\r
876 __IO uint32_t CLC; /*!<Clock Control Register Offset 0x0000*/
\r
877 __I uint32_t RESERVED1;
\r
878 __I uint32_t ID; /*!<Module Identification Register Offset 0x0008*/
\r
879 __I uint32_t RESERVED2[7];
\r
880 __IO uint32_t OCS; /*!<OCDS Control and Status Register Offset 0x0028*/
\r
881 __I uint32_t RESERVED3[21];
\r
882 __IO uint32_t GLOBCFG; /*!<Global Configuration Register Offset 0x0080*/
\r
883 __I uint32_t RESERVED4;
\r
884 __IO uint32_t GLOBRC; /*!<Global Run Control Register Offset 0x0088*/
\r
885 __I uint32_t RESERVED5[5];
\r
886 __IO uint32_t CGCFG; /*!<Carrier Generator Configuration Register Offset 0x00A0*/
\r
887 __I uint32_t RESERVED6[15];
\r
888 __IO uint32_t EVFLAG; /*!<Event Flag Register Offset 0x00E0*/
\r
889 __O uint32_t EVFLAGCLR; /*!<Event Flag Clear Register Offset 0x00E4*/
\r
890 }DSD_GLOBAL_TypeDef;
\r
893 *DSD CHANNEL Registers
\r
896 __IO uint32_t MODCFG; /*!<Modulator Configuration Register 0 Offset 0x0100*/
\r
897 __I uint32_t RESERVED1;
\r
898 __IO uint32_t DICFG; /*!<Demodulator Input Configuration Register 0 Offset 0x0108*/
\r
899 __I uint32_t RESERVED2[2];
\r
900 __IO uint32_t FCFGC; /*!<Filter Configuration Register 0, Main Comb Filter Offset 0x0114*/
\r
901 __IO uint32_t FCFGA; /*!<Filter Configuration Register 0, Auxiliary Filter Offset 0x0118*/
\r
902 __I uint32_t RESERVED3;
\r
903 __IO uint32_t IWCTR; /*!<Integration Window Control Register 0 Offset 0x0120*/
\r
904 __I uint32_t RESERVED4;
\r
905 __IO uint32_t BOUNDSEL; /*!<Boundary Select Register 0 Offset 0x0128*/
\r
906 __I uint32_t RESERVED5;
\r
907 __I uint32_t RESM; /*!<Result Register 0 Main Filter Offset 0x0130*/
\r
908 __I uint32_t RESERVED6;
\r
909 __IO uint32_t OFFM; /*!<Offset Register 0 Main Filter Offset 0x0138*/
\r
910 __I uint32_t RESERVED7;
\r
911 __I uint32_t RESA; /*!<Result Register 0 Auxiliary Filter Offset 0x0140*/
\r
912 __I uint32_t RESERVED8[3];
\r
913 __I uint32_t TSTMP; /*!<Time-Stamp Register 0 Offset 0x0150*/
\r
914 __I uint32_t RESERVED9[19];
\r
915 __IO uint32_t CGSYNC; /*!<Carrier Generator Synchronization Register 0 Offset 0x01A0*/
\r
916 __I uint32_t RESERVED10;
\r
917 __IO uint32_t RECTCFG; /*!<Rectification Configuration Register 0 Offset 0x01A8*/
\r
920 #define DSD_BASE ((uint32_t)0x40008000U)
\r
921 #define DSD_GLOBAL_BASE (0x0000U)
\r
922 #define DSD_CH0_BASE (0x0100U)
\r
923 #define DSD_CH1_BASE (0x0200U)
\r
924 #define DSD_CH2_BASE (0x0300U)
\r
925 #define DSD_CH3_BASE (0x0400U)
\r
926 /***************************************************************************/
\r
927 /* Peripheral Declaration */
\r
928 /***************************************************************************/
\r
929 #define DSD ((DSD_GLOBAL_TypeDef*)(DSD_BASE + DSD_GLOBAL_BASE))
\r
930 #define DSD_CH0 ((DSD_CH_TypeDef*)(DSD_BASE + DSD_CH0_BASE))
\r
931 #define DSD_CH1 ((DSD_CH_TypeDef*)(DSD_BASE + DSD_CH1_BASE))
\r
932 #define DSD_CH2 ((DSD_CH_TypeDef*)(DSD_BASE + DSD_CH2_BASE))
\r
933 #define DSD_CH3 ((DSD_CH_TypeDef*)(DSD_BASE + DSD_CH3_BASE))
\r
935 /***************************************************************************/
\r
937 /***************************************************************************/
\r
940 *Cortex M4 - Data Watchpoint and Trace
\r
942 typedef struct { /*!< DWT Structure */
\r
943 __IO uint32_t DWT_CTRL; /*!< Use the DWT Control Register to enable the DWT unit. */
\r
944 __IO uint32_t DWT_CYCCNT; /*!< The DWT_CYCCNT register characteristics are:Purpose Shows or sets the value of the processor cycle counter, CYCCNT.Usage constraints The DWT unit suspends CYCCNT counting when the processor is in Debug state.Configurations Implemented only when DWT_CTRL.NOCYCCNT is RAZ, see Control register, DWT_CTRL on page C1-879.When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this register is UNK/SBZP.For more information see CYCCNT cycle counter and related timers on page C1-871. */
\r
945 __IO uint32_t DWT_CPICNT; /*!< The DWT_CPICNT register characteristics are:Purpose Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls.Usage constraints The counter initializes to 0 when software enables its counter overflow event by setting the DWT_CTRL.CPIEVTENA bit to 1.Configurations Implemented only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL on page C1-879.If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not include the profiling counters, this re */
\r
946 __IO uint32_t DWT_EXCCNT; /*!< The DWT_EXCCNT register characteristics are:Purpose Counts the total cycles spent in exception processingUsage constraints The counter initializes to 0 when software enables its counter overflow event by setting the DWT_CTRL.EXCEVTENA bit to 1.Configurations Implemented only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL on page C1-879.If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not include the profiling counters, this register is UNK/SBZP.For more information see Pr */
\r
947 __IO uint32_t DWT_SLEEPCNT; /*!< The DWT_SLEEPCNT register characteristics are:Purpose Counts the total number of cycles that the processor is sleeping.Usage constraints The counter initializes to 0 when software enables its counter overflow event by setting the DWT_CTRL.SLEEPEVTENA bit to 1.Configurations Implemented only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL on page C1-879.If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not include the profiling counters, this register is UNK/SBZP.ARM recomme */
\r
948 __IO uint32_t DWT_LSUCNT; /*!< The DWT_LSUCNT register characteristics are:Purpose Increments on the additional cycles required to execute all load or store instructionsUsage constraints The counter initializes to 0 when software enables its counter overflow event by setting the DWT_CTRL.LSUEVTENA bit to 1.Configurations Implemented only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL on page C1-879.If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not include the profiling counters, this register is UNK */
\r
949 __IO uint32_t DWT_FOLDCNT; /*!< The DWT_FOLDCNT register characteristics are:Purpose Increments on each instruction that takes 0 cycles.Usage constraints The counter initializes to 0 when software enables its counter overflow event by setting the DWT_CTRL.FOLDEVTENA bit to 1. If an implementation includes profiling counters but does not support instruction folding, this counter can be RAZ/WI.Configurations Implemented only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL on page C1-879.If DWT_CTRL.NOPRFCNT is RAO, indicating */
\r
950 __I uint32_t DWT_PCSR; /*!< The DWT_PCSR characteristics are:Purpose Samples the current value of the program counter.Usage constraints There are no usage constraints.NoteBit [0] of any sampled value is RAZ and does not reflect instruction set state as it does in a PC sample on the ARMv7-A and ARMv7-R architecture profiles.Configurations An optional feature. Register is RAZ/WI if not implemented.For more information see Program counter sampling support on page C1-877. */
\r
951 __IO uint32_t DWT_COMP0; /*!< The DWT_COMP0 register characteristics are:Purpose Provides a reference value for use by comparator 0.Usage constraints The operation of comparator 0 depends also on the registers DWT_MASK0 and DWT_FUNCTION0, see Comparator Mask registers, DWT_MASKn on page C1-892 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP defines the number of implemented DWT_COMPn registers */
\r
952 __IO uint32_t DWT_MASK0; /*!< The DWT_MASK0 register characteristics are:Purpose Provides the size of the ignore mask applied to the access address for address range matching by comparator 0.Usage constraints The operation of comparator 0 depends also on the registers DWT_COMP0 and DWT_FUNCTION0, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP */
\r
953 __IO uint32_t DWT_FUNCTION0; /*!< The DWT_FUNCTION0 register characteristics are:Purpose Controls the operation of comparator 0.Usage constraints The operation of comparator 0 depends also on the registers DWT_COMP0 and DWT_MASK0, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Mask registers, DWT_MASKn on page C1-892.Reading this register clears some fields to zero. See the field descriptions in Table C1-39 on page C1-894 for more information, and for the usage constraints of individual fields.Configurations Implemented */
\r
954 __I uint32_t RESERVED0;
\r
955 __IO uint32_t DWT_COMP1; /*!< The DWT_COMP1 register characteristics are:Purpose Provides a reference value for use by comparator n.Usage constraints The operation of comparator 1 depends also on the registers DWT_MASK1 and DWT_FUNCTION1, see Comparator Mask registers, DWT_MASKn on page C1-892 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP defines the number of implemented DWT_COMPn registers */
\r
956 __IO uint32_t DWT_MASK1; /*!< The DWT_MASK1 register characteristics are:Purpose Provides the size of the ignore mask applied to the access address for address range matching by comparator 1.Usage constraints The operation of comparator 1 depends also on the registers DWT_COMP1 and DWT_FUNCTION1, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP */
\r
957 __IO uint32_t DWT_FUNCTION1; /*!< The DWT_FUNCTION1 register characteristics are:Purpose Controls the operation of comparator 1.Usage constraints The operation of comparator 1 depends also on the registers DWT_COMP1 and DWT_MASK1, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Mask registers, DWT_MASKn on page C1-892.Reading this register clears some fields to zero. See the field descriptions in Table C1-39 on page C1-894 for more information, and for the usage constraints of individual fields.Configurations Implemented */
\r
958 __I uint32_t RESERVED1;
\r
959 __IO uint32_t DWT_COMP2; /*!< The DWT_COMP2 register characteristics are:Purpose Provides a reference value for use by comparator n.Usage constraints The operation of comparator n depends also on the registers DWT_MASK2 and DWT_FUNCTION2, see Comparator Mask registers, DWT_MASKn on page C1-892 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP defines the number of implemented DWT_COMPn registers */
\r
960 __IO uint32_t DWT_MASK2; /*!< The DWT_MASK2 register characteristics are:Purpose Provides the size of the ignore mask applied to the access address for address range matching by comparator 2.Usage constraints The operation of comparator 2 depends also on the registers DWT_COMP2 and DWT_FUNCTION2, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP */
\r
961 __IO uint32_t DWT_FUNCTION2; /*!< The DWT_FUNCTION2 register characteristics are:Purpose Controls the operation of comparator 2.Usage constraints The operation of comparator 2 depends also on the registers DWT_COMP2 and DWT_MASK2, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Mask registers, DWT_MASKn on page C1-892.Reading this register clears some fields to zero. See the field descriptions in Table C1-39 on page C1-894 for more information, and for the usage constraints of individual fields.Configurations Implemented */
\r
962 __I uint32_t RESERVED2;
\r
963 __IO uint32_t DWT_COMP3; /*!< The DWT_COMP3 register characteristics are:Purpose Provides a reference value for use by comparator n.Usage constraints The operation of comparator 3 depends also on the registers DWT_MASK3 and DWT_FUNCTION3, see Comparator Mask registers, DWT_MASKn on page C1-892 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP defines the number of implemented DWT_COMPn registers */
\r
964 __IO uint32_t DWT_MASK3; /*!< The DWT_MASK3 register characteristics are:Purpose Provides the size of the ignore mask applied to the access address for address range matching by comparator 3.Usage constraints The operation of comparator 3 depends also on the registers DWT_COMP3 and DWT_FUNCTION3, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Function registers, DWT_FUNCTIONn on page C1-893.Configurations Implemented only when DWT_CTRL.NUMCOMP is nonzero, see Control register, DWT_CTRL on page C1-879.DWT_CTRL.NUMCOMP */
\r
965 __IO uint32_t DWT_FUNCTION3; /*!< The DWT_FUNCTION3 register characteristics are:Purpose Controls the operation of comparator 3.Usage constraints The operation of comparator 3 depends also on the registers DWT_COMP3 and DWT_MASK3, see Comparator registers, DWT_COMPn on page C1-891 and Comparator Mask registers, DWT_MASKn on page C1-892.Reading this register clears some fields to zero. See the field descriptions in Table C1-39 on page C1-894 for more information, and for the usage constraints of individual fields.Configurations Implemented */
\r
966 __I uint32_t RESERVED3[989];
\r
967 __I uint32_t DWTPID4; /*!< Peripheral identification register4 */
\r
968 __I uint32_t DWTPID5; /*!< Peripheral identification register5 */
\r
969 __I uint32_t DWTPID6; /*!< Peripheral identification register6 */
\r
970 __I uint32_t DWTPID7; /*!< Peripheral identification register7 */
\r
971 __I uint32_t DWTPID0; /*!< Peripheral identification register0 */
\r
972 __I uint32_t DWTPID1; /*!< Peripheral identification register1 */
\r
973 __I uint32_t DWTPID2; /*!< Peripheral identification register2 */
\r
974 __I uint32_t DWTPID3; /*!< Peripheral identification register3 */
\r
975 __I uint32_t DWTCID0; /*!< Component identification register0 */
\r
976 __I uint32_t DWTCID1; /*!< Component identification register1 */
\r
977 __I uint32_t DWTCID2; /*!< Component identification register2 */
\r
978 __I uint32_t DWTCID3; /*!< Component identification register3 */
\r
981 #define DWT_BASE ((uint32_t)0xE0001000U)
\r
982 #define DWT_GLOBAL_BASE (0x0000U)
\r
983 /***************************************************************************/
\r
984 /* Peripheral Declaration */
\r
985 /***************************************************************************/
\r
986 #define DWT ((DWT_Type *)(DWT_BASE + DWT_GLOBAL_BASE))
\r
988 /***************************************************************************/
\r
990 /***************************************************************************/
\r
993 *EBU GLOBAL registers
\r
996 __IO uint32_t CLC; /*!<EBU Clock Control Register Offset 0x0000*/
\r
997 __IO uint32_t MODCON; /*!<EBU Configuration Register Offset 0x0004*/
\r
998 __I uint32_t ID; /*!<EBU Module Identification Register Offset 0x0008*/
\r
999 __IO uint32_t USERCON; /*!<EBU Test/Control Configuration Register Offset 0x000C*/
\r
1000 }EBU_GLOBAL_TypeDef;
\r
1003 *EBU chipselect registers
\r
1006 __IO uint32_t ADDRSEL; /*!<EBU Address Select Register 0 Offset 0x0018*/
\r
1007 __I uint32_t RESERVED1[3];
\r
1008 __IO uint32_t BUSRCON; /*!<EBU Bus Configuration Register Offset 0x0028*/
\r
1009 __IO uint32_t BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset 0x002C*/
\r
1010 __IO uint32_t BUSWCON; /*!<EBU Bus Write Configuration Register Offset 0x0030*/
\r
1011 __IO uint32_t BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset 0x0034*/
\r
1015 __IO uint32_t ADDRSEL; /*!<EBU Address Select Register 0 Offset 0x001C*/
\r
1016 __I uint32_t RESERVED1[6];
\r
1017 __IO uint32_t BUSRCON; /*!<EBU Bus Configuration Register Offset 0x0038*/
\r
1018 __IO uint32_t BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset*/
\r
1019 __IO uint32_t BUSWCON; /*!<EBU Bus Write Configuration Register Offset*/
\r
1020 __IO uint32_t BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset*/
\r
1024 __IO uint32_t ADDRSEL; /*!<EBU Address Select Register 0 Offset 0x0020*/
\r
1025 __I uint32_t RESERVED1[9];
\r
1026 __IO uint32_t BUSRCON; /*!<EBU Bus Configuration Register Offset 0x0048*/
\r
1027 __IO uint32_t BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset*/
\r
1028 __IO uint32_t BUSWCON; /*!<EBU Bus Write Configuration Register Offset*/
\r
1029 __IO uint32_t BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset*/
\r
1033 __IO uint32_t ADDRSEL; /*!<EBU Address Select Register 0 Offset 0x0024*/
\r
1034 __I uint32_t RESERVED1[12];
\r
1035 __IO uint32_t BUSRCON; /*!<EBU Bus Configuration Register Offset 0x0058*/
\r
1036 __IO uint32_t BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset*/
\r
1037 __IO uint32_t BUSWCON; /*!<EBU Bus Write Configuration Register Offset*/
\r
1038 __IO uint32_t BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset*/
\r
1042 *EBU SDRAM registers
\r
1045 __IO uint32_t SDRMCON; /*!<EBU SDRAM Control Register Offset 0x0068*/
\r
1046 __IO uint32_t SDRMOD; /*!<EBU SDRAM Mode Register Offset 0x006C*/
\r
1047 __IO uint32_t SDRMREF; /*!<EBU SDRAM Refresh Control Register Offset 0x0070*/
\r
1048 __I uint32_t SDRSTAT; /*!<EBU SDRAM Status Register Offset 0x0074*/
\r
1049 }EBU_SDRAM_TypeDef;
\r
1051 #define EBU_BASE ((uint32_t)0x58008000U)
\r
1052 #define EBU_GLOBAL_BASE (0x0000U)
\r
1053 #define EBU_CS0_BASE (0x0018U)
\r
1054 #define EBU_CS1_BASE (0x001CU)
\r
1055 #define EBU_CS2_BASE (0x0020U)
\r
1056 #define EBU_CS3_BASE (0x0024U)
\r
1057 #define EBU_SDRAM_BASE (0x0068U)
\r
1059 /***************************************************************************/
\r
1060 /* Peripheral Declaration */
\r
1061 /***************************************************************************/
\r
1062 #define EBU ((EBU_GLOBAL_TypeDef*)(EBU_BASE + EBU_GLOBAL_BASE))
\r
1063 #define EBU_CS0 ((EBU_CS0_TypeDef*)(EBU_BASE + EBU_CS0_BASE))
\r
1064 #define EBU_CS1 ((EBU_CS1_TypeDef*)(EBU_BASE + EBU_CS1_BASE))
\r
1065 #define EBU_CS2 ((EBU_CS2_TypeDef*)(EBU_BASE + EBU_CS2_BASE))
\r
1066 #define EBU_CS3 ((EBU_CS3_TypeDef*)(EBU_BASE + EBU_CS3_BASE))
\r
1067 #define EBU_SDRAM ((EBU_SDRAM_TypeDef*)(EBU_BASE + EBU_SDRAM_BASE))
\r
1069 /***************************************************************************/
\r
1071 /***************************************************************************/
\r
1077 __IO uint32_t EXISEL; /*!<Event Input Select Register 0 Offset 0x0000*/
\r
1078 __I uint32_t RESERVED1[3];
\r
1079 __IO uint32_t EXICON[4]; /*!<Event Input Control 0 Register Offset 0x0010*/
\r
1080 __IO uint32_t EXOCON[4]; /*!<Event Output Trigger Control 0 Register Offset 0x0020*/
\r
1081 }ERU_GLOBAL_TypeDef;
\r
1083 #define ERU0_BASE ((uint32_t)0x48018000U)
\r
1084 #define ERU1_BASE ((uint32_t)0x40044000U)
\r
1085 #define ERU_GLOBAL_BASE (0x0000U)
\r
1086 /***************************************************************************/
\r
1087 /* Peripheral Declaration */
\r
1088 /***************************************************************************/
\r
1089 #define ERU0 ((ERU_GLOBAL_TypeDef*)(ERU0_BASE + ERU_GLOBAL_BASE))
\r
1090 #define ERU1 ((ERU_GLOBAL_TypeDef*)(ERU1_BASE + ERU_GLOBAL_BASE))
\r
1092 /***************************************************************************/
\r
1094 /***************************************************************************/
\r
1100 __IO uint32_t MAC_CONFIGURATION; /*!<Register 0 [MAC Configuration Register] Offset 0x0000*/
\r
1101 __IO uint32_t MAC_FRAME_FILTER; /*!<Register 1 [MAC Frame Filter] Offset 0x0004*/
\r
1102 __IO uint32_t HASH_TABLE_HIGH; /*!<Register 2 [Hash Table High Register] Offset 0x0008*/
\r
1103 __IO uint32_t HASH_TABLE_LOW; /*!<Register 3 [Hash Table Low Register] Offset 0x000C*/
\r
1104 __IO uint32_t GMII_ADDRESS; /*!<Register 4 [MII Address Register) Offset 0x0010*/
\r
1105 __IO uint32_t GMII_DATA; /*!<Register 5 [MII Data Register] Offset 0x0014*/
\r
1106 __IO uint32_t FLOW_CONTROL; /*!<Register 6 [Flow Control Register] Offset 0x0018*/
\r
1107 __IO uint32_t VLAN_TAG; /*!<Register 7 [VLAN Tag Register] Offset 0x001C*/
\r
1108 __I uint32_t VERSION; /*!<Register 8 [Version Register] Offset 0x0020*/
\r
1109 __I uint32_t DEBUG; /*!<Register 9 [Debug Register] Offset 0x0024*/
\r
1110 __IO uint32_t REMOTE_WAKE_UP_FRAME_FILTER; /*!< Offset 0x0028*/
\r
1111 __IO uint32_t PMT_CONTROL_STATUS; /*!<Register 11 [PMT Control and Status Register] Offset 0x002C*/
\r
1112 __I uint32_t RESERVED1[2];
\r
1113 __I uint32_t INTERRUPT_STATUS; /*!<Register 14 [Interrupt Register] Offset 0x0038*/
\r
1114 __IO uint32_t INTERRUPT_MASK; /*!<Register 15 [Interrupt Mask Register] Offset 0x003C*/
\r
1115 __IO uint32_t MAC_ADDRESS0_HIGH; /*!<Register 16 [MAC Address0 High Register] Offset 0x0040*/
\r
1116 __IO uint32_t MAC_ADDRESS0_LOW; /*!<Register 17 [MAC Address0 Low Register] Offset 0x0044*/
\r
1117 __IO uint32_t MAC_ADDRESS1_HIGH; /*!<Register 18 [MAC Address1 High Register] Offset 0x0048*/
\r
1118 __IO uint32_t MAC_ADDRESS1_LOW; /*!<Register 19 [MAC Address1 Low Register] Offset 0x004C*/
\r
1119 __IO uint32_t MAC_ADDRESS2_HIGH; /*!<Register 20 [MAC Address2 High Register] Offset 0x0050*/
\r
1120 __IO uint32_t MAC_ADDRESS2_LOW; /*!<Register 21 [MAC Address2 Low Register] Offset 0x0054*/
\r
1121 __IO uint32_t MAC_ADDRESS3_HIGH; /*!<Register 22 [MAC Address3 High Register] Offset 0x0058*/
\r
1122 __IO uint32_t MAC_ADDRESS3_LOW; /*!<Register 23 [MAC Address3 Low Register] Offset 0x005C*/
\r
1123 __I uint32_t RESERVED2[40];
\r
1124 __IO uint32_t MMC_CONTROL; /*!<Register 64 [MMC Control Register] Offset 0x0100*/
\r
1125 __I uint32_t MMC_RECEIVE_INTERRUPT; /*!<Register 65 [MMC Receive Interrupt Register] Offset 0x0104*/
\r
1126 __I uint32_t MMC_TRANSMIT_INTERRUPT; /*!<Register 66 [MMC Transmit Interrupt Register] Offset 0x0108*/
\r
1127 __IO uint32_t MMC_RECEIVE_INTERRUPT_MASK; /*!< Offset 0x010C*/
\r
1128 __IO uint32_t MMC_TRANSMIT_INTERRUPT_MASK; /*!< Offset 0x0110*/
\r
1129 __I uint32_t TX_OCTET_COUNT_GOOD_BAD; /*!<Register 69 [Transmit Octet Count for Good and Bad Frames] Offset 0x0114*/
\r
1130 __I uint32_t TX_FRAME_COUNT_GOOD_BAD; /*!<Register 70 [Transmit Frame Count for Good and Bad Frames] Offset 0x0118*/
\r
1131 __I uint32_t TX_BROADCAST_FRAMES_GOOD; /*!<Register 71 [Transmit Frame Count for Good Broadcast Frames] Offset 0x011C*/
\r
1132 __I uint32_t TX_MULTICAST_FRAMES_GOOD; /*!<Register 72 [Transmit Frame Count for Good Multicast Frames] Offset 0x0120*/
\r
1133 __I uint32_t TX_64OCTETS_FRAMES_GOOD_BAD; /*!<Register 73 [Transmit Octet Count for Good and Bad 64 Byte Frames] Offset 0x0124*/
\r
1134 __I uint32_t TX_65TO127OCTETS_FRAMES_GOOD_BAD; /*!<Register 74 [Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames] Offset 0x0128*/
\r
1135 __I uint32_t TX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!<Register 75 [Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames] Offset 0x012C*/
\r
1136 __I uint32_t TX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!<Register 76 [Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames] Offset 0x0130*/
\r
1137 __I uint32_t TX_512TO1023OCTETS_FRAMES_GOOD_BAD; /*!<Register 77 [Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames] Offset 0x0134*/
\r
1138 __I uint32_t TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD; /*!<Register 78 [Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames] Offset 0x0138*/
\r
1139 __I uint32_t TX_UNICAST_FRAMES_GOOD_BAD; /*!<Register 79 [Transmit Frame Count for Good and Bad Unicast Frames] Offset 0x013C*/
\r
1140 __I uint32_t TX_MULTICAST_FRAMES_GOOD_BAD; /*!<Register 80 [Transmit Frame Count for Good and Bad Multicast Frames] Offset 0x0140*/
\r
1141 __I uint32_t TX_BROADCAST_FRAMES_GOOD_BAD; /*!<Register 81 [Transmit Frame Count for Good and Bad Broadcast Frames] Offset 0x0144*/
\r
1142 __I uint32_t TX_UNDERFLOW_ERROR_FRAMES; /*!<Register 82 [Transmit Frame Count for Underflow Error Frames] Offset 0x0148*/
\r
1143 __I uint32_t TX_SINGLE_COLLISION_GOOD_FRAMES; /*!<Register 83 [Transmit Frame Count for Frames Transmitted after Single Collision] Offset 0x014C*/
\r
1144 __I uint32_t TX_MULTIPLE_COLLISION_GOOD_FRAMES; /*!<Register 84 [Transmit Frame Count for Frames Transmitted after Multiple Collision] Offset 0x0150*/
\r
1145 __I uint32_t TX_DEFERRED_FRAMES; /*!< Offset 0x0154*/
\r
1146 __I uint32_t TX_LATE_COLLISION_FRAMES; /*!<Register 86 [Transmit Frame Count for Late Collision Error Frames] Offset 0x0158*/
\r
1147 __I uint32_t TX_EXCESSIVE_COLLISION_FRAMES; /*!<Register 87 [Transmit Frame Count for Excessive Collision Error Frames] Offset 0x015C*/
\r
1148 __I uint32_t TX_CARRIER_ERROR_FRAMES; /*!<Register 88 [Transmit Frame Count for Carrier Sense Error Frames] Offset 0x0160*/
\r
1149 __I uint32_t TX_OCTET_COUNT_GOOD; /*!< Offset 0x0164*/
\r
1150 __I uint32_t TX_FRAME_COUNT_GOOD; /*!< Offset 0x0168*/
\r
1151 __I uint32_t TX_EXCESSIVE_DEFERRAL_ERROR; /*!<Register 91 [Transmit Frame Count for Excessive Deferral Error Frames] Offset 0x016C*/
\r
1152 __I uint32_t TX_PAUSE_FRAMES; /*!<Register 92 [Transmit Frame Count for Good PAUSE Frames] Offset 0x0170*/
\r
1153 __I uint32_t TX_VLAN_FRAMES_GOOD; /*!<Register 93 [Transmit Frame Count for Good VLAN Frames] Offset 0x0174*/
\r
1154 __I uint32_t TX_OSIZE_FRAMES_GOOD; /*!<Register 94 [Transmit Frame Count for Good Oversize Frames] Offset 0x0178*/
\r
1155 __I uint32_t RESERVED3;
\r
1156 __I uint32_t RX_FRAMES_COUNT_GOOD_BAD; /*!<Register 96 [Receive Frame Count for Good and Bad Frames] Offset 0x0180*/
\r
1157 __I uint32_t RX_OCTET_COUNT_GOOD_BAD; /*!<Register 97 [Receive Octet Count for Good and Bad Frames] Offset 0x0184*/
\r
1158 __I uint32_t RX_OCTET_COUNT_GOOD; /*!< Offset 0x0188*/
\r
1159 __I uint32_t RX_BROADCAST_FRAMES_GOOD; /*!<Register 99 [Receive Frame Count for Good Broadcast Frames] Offset 0x018C*/
\r
1160 __I uint32_t RX_MULTICAST_FRAMES_GOOD; /*!<Register 100 [Receive Frame Count for Good Multicast Frames] Offset 0x0190*/
\r
1161 __I uint32_t RX_CRC_ERROR_FRAMES; /*!<Register 101 [Receive Frame Count for CRC Error Frames] Offset 0x0194*/
\r
1162 __I uint32_t RX_ALIGNMENT_ERROR_FRAMES; /*!<Register 102 [Receive Frame Count for Alignment Error Frames] Offset 0x0198*/
\r
1163 __I uint32_t RX_RUNT_ERROR_FRAMES; /*!<Register 103 [Receive Frame Count for Runt Error Frames] Offset 0x019C*/
\r
1164 __I uint32_t RX_JABBER_ERROR_FRAMES; /*!<Register 104 [Receive Frame Count for Jabber Error Frames] Offset 0x01A0*/
\r
1165 __I uint32_t RX_UNDERSIZE_FRAMES_GOOD; /*!<Register 105 [Receive Frame Count for Undersize Frames] Offset 0x01A4*/
\r
1166 __I uint32_t RX_OVERSIZE_FRAMES_GOOD; /*!< Offset 0x01A8*/
\r
1167 __I uint32_t RX_64OCTETS_FRAMES_GOOD_BAD; /*!<Register 107 [Receive Frame Count for Good and Bad 64 Byte Frames] Offset 0x01AC*/
\r
1168 __I uint32_t RX_65TO127OCTETS_FRAMES_GOOD_BAD; /*!<Register 108 [Receive Frame Count for Good and Bad 65 to 127 Bytes Frames] Offset 0x01B0*/
\r
1169 __I uint32_t RX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!<Register 109 [Receive Frame Count for Good and Bad 128 to 255 Bytes Frames] Offset 0x01B4*/
\r
1170 __I uint32_t RX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!<Register 110 [Receive Frame Count for Good and Bad 256 to 511 Bytes Frames] Offset 0x01B8*/
\r
1171 __I uint32_t RX_512TO1023OCTETS_FRAMES_GOOD_BAD; /*!<Register 111 [Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames] Offset 0x01BC*/
\r
1172 __I uint32_t RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD; /*!<Register 112 [Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames] Offset 0x01C0*/
\r
1173 __I uint32_t RX_UNICAST_FRAMES_GOOD; /*!<Register 113 [Receive Frame Count for Good Unicast Frames] Offset 0x01C4*/
\r
1174 __I uint32_t RX_LENGTH_ERROR_FRAMES; /*!<Register 114 [Receive Frame Count for Length Error Frames] Offset 0x01C8*/
\r
1175 __I uint32_t RX_OUT_OF_RANGE_TYPE_FRAMES; /*!<Register 115 [Receive Frame Count for Out of Range Frames] Offset 0x01CC*/
\r
1176 __I uint32_t RX_PAUSE_FRAMES; /*!<Register 116 [Receive Frame Count for PAUSE Frames] Offset 0x01D0*/
\r
1177 __I uint32_t RX_FIFO_OVERFLOW_FRAMES; /*!<Register 117 [Receive Frame Count for FIFO Overflow Frames] Offset 0x01D4*/
\r
1178 __I uint32_t RX_VLAN_FRAMES_GOOD_BAD; /*!<Register 118 [Receive Frame Count for Good and Bad VLAN Frames] Offset 0x01D8*/
\r
1179 __I uint32_t RX_WATCHDOG_ERROR_FRAMES; /*!<Register 119 [Receive Frame Count for Watchdog Error Frames] Offset 0x01DC*/
\r
1180 __I uint32_t RX_RECEIVE_ERROR_FRAMES; /*!<Register 120 [Receive Frame Count for Receive Error Frames] Offset 0x01E0*/
\r
1181 __I uint32_t RX_CONTROL_FRAMES_GOOD; /*!<Register 121 [Receive Frame Count for Good Control Frames Frames] Offset 0x01E4*/
\r
1182 __I uint32_t RESERVED4[6];
\r
1183 __IO uint32_t MMC_IPC_RECEIVE_INTERRUPT_MASK; /*!<Register 128 [MMC Receive Checksum Offload Interrupt Mask Register] Offset 0x0200*/
\r
1184 __I uint32_t RESERVED5;
\r
1185 __I uint32_t MMC_IPC_RECEIVE_INTERRUPT; /*!<Register 130 [MMC Receive Checksum Offload Interrupt Register] Offset 0x0208*/
\r
1186 __I uint32_t RESERVED6;
\r
1187 __I uint32_t RXIPV4_GOOD_FRAMES; /*!< Offset 0x0210*/
\r
1188 __I uint32_t RXIPV4_HEADER_ERROR_FRAMES; /*!<Register 133 [Receive IPV4 Header Error Frame Counter Register] Offset 0x0214*/
\r
1189 __I uint32_t RXIPV4_NO_PAYLOAD_FRAMES; /*!<Register 134 [Receive IPV4 No Payload Frame Counter Register] Offset 0x0218*/
\r
1190 __I uint32_t RXIPV4_FRAGMENTED_FRAMES; /*!<Register 135 [Receive IPV4 Fragmented Frame Counter Register] Offset 0x021C*/
\r
1191 __I uint32_t RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES; /*!<Register 136 [Receive IPV4 UDP Checksum Disabled Frame Counter Register] Offset 0x0220*/
\r
1192 __I uint32_t RXIPV6_GOOD_FRAMES; /*!< Offset 0x0224*/
\r
1193 __I uint32_t RXIPV6_HEADER_ERROR_FRAMES; /*!<Register 138 [Receive IPV6 Header Error Frame Counter Register] Offset 0x0228*/
\r
1194 __I uint32_t RXIPV6_NO_PAYLOAD_FRAMES; /*!<Register 139 [Receive IPV6 No Payload Frame Counter Register] Offset 0x022C*/
\r
1195 __I uint32_t RXUDP_GOOD_FRAMES; /*!< Offset 0x0230*/
\r
1196 __I uint32_t RXUDP_ERROR_FRAMES; /*!< Offset 0x0234*/
\r
1197 __I uint32_t RXTCP_GOOD_FRAMES; /*!< Offset 0x0238*/
\r
1198 __I uint32_t RXTCP_ERROR_FRAMES; /*!< Offset 0x023C*/
\r
1199 __I uint32_t RXICMP_GOOD_FRAMES; /*!< Offset 0x0240*/
\r
1200 __I uint32_t RXICMP_ERROR_FRAMES; /*!< Offset 0x0244*/
\r
1201 __I uint32_t RESERVED7[2];
\r
1202 __I uint32_t RXIPV4_GOOD_OCTETS; /*!< Offset 0x0250*/
\r
1203 __I uint32_t RXIPV4_HEADER_ERROR_OCTETS; /*!<Register 149 [Receive IPV4 Header Error Octet Counter Register] Offset 0x0254*/
\r
1204 __I uint32_t RXIPV4_NO_PAYLOAD_OCTETS; /*!<Register 150 [Receive IPV4 No Payload Octet Counter Register] Offset 0x0258*/
\r
1205 __I uint32_t RXIPV4_FRAGMENTED_OCTETS; /*!<Register 151 [Receive IPV4 Fragmented Octet Counter Register] Offset 0x025C*/
\r
1206 __I uint32_t RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS; /*!<Register 152 [Receive IPV4 Fragmented Octet Counter Register] Offset 0x0260*/
\r
1207 __I uint32_t RXIPV6_GOOD_OCTETS; /*!< Offset 0x0264*/
\r
1208 __I uint32_t RXIPV6_HEADER_ERROR_OCTETS; /*!<Register 154 [Receive IPV6 Header Error Octet Counter Register] Offset 0x0268*/
\r
1209 __I uint32_t RXIPV6_NO_PAYLOAD_OCTETS; /*!<Register 155 [Receive IPV6 No Payload Octet Counter Register] Offset 0x026C*/
\r
1210 __I uint32_t RXUDP_GOOD_OCTETS; /*!< Offset 0x0270*/
\r
1211 __I uint32_t RXUDP_ERROR_OCTETS; /*!< Offset 0x0274*/
\r
1212 __I uint32_t RXTCP_GOOD_OCTETS; /*!< Offset 0x0278*/
\r
1213 __I uint32_t RXTCP_ERROR_OCTETS; /*!< Offset 0x027C*/
\r
1214 __I uint32_t RXICMP_GOOD_OCTETS; /*!< Offset 0x0280*/
\r
1215 __I uint32_t RXICMP_ERROR_OCTETS; /*!< Offset 0x0284*/
\r
1216 __I uint32_t RESERVED8[286];
\r
1217 __IO uint32_t TIMESTAMP_CONTROL; /*!<Register 448 [Timestamp Control Register] Offset 0x0700*/
\r
1218 __IO uint32_t SUB_SECOND_INCREMENT; /*!<Register 449 [Sub-Second Increment Register] Offset 0x0704*/
\r
1219 __I uint32_t SYSTEM_TIME_SECONDS; /*!<Register 450 [System Time - Seconds Register] Offset 0x0708*/
\r
1220 __I uint32_t SYSTEM_TIME_NANOSECONDS; /*!< Offset 0x070C*/
\r
1221 __IO uint32_t SYSTEM_TIME_SECONDS_UPDATE; /*!<Register 452 [System Time - Seconds Update Register] Offset 0x0710*/
\r
1222 __IO uint32_t SYSTEM_TIME_NANOSECONDS_UPDATE; /*!< Offset 0x0714*/
\r
1223 __IO uint32_t TIMESTAMP_ADDEND; /*!<Register 454 [Timestamp Addend Register] Offset 0x0718*/
\r
1224 __IO uint32_t TARGET_TIME_SECONDS; /*!<Register 455 [Target Time Seconds Register] Offset 0x071C*/
\r
1225 __IO uint32_t TARGET_TIME_NANOSECONDS; /*!< Offset 0x0720*/
\r
1226 __IO uint32_t SYSTEM_TIME_HIGHER_WORD_SECONDS; /*!<Register 457 [System Time - Higher Word Seconds Register] Offset 0x0724*/
\r
1227 __I uint32_t TIMESTAMP_STATUS; /*!<Register 458 [Timestamp Status Register] Offset 0x0728*/
\r
1228 __IO uint32_t PPS_CONTROL; /*!<Register 459 [PPS Control Register] Offset 0x072C*/
\r
1229 __I uint32_t RESERVED9[564];
\r
1230 __IO uint32_t BUS_MODE; /*!<Register 0 [Bus Mode Register] Offset 0x1000*/
\r
1231 __IO uint32_t TRANSMIT_POLL_DEMAND; /*!<Register 1 [Transmit Poll Demand Register] Offset 0x1004*/
\r
1232 __IO uint32_t RECEIVE_POLL_DEMAND; /*!< Offset 0x1008*/
\r
1233 __IO uint32_t RECEIVE_DESCRIPTOR_LIST_ADDRESS; /*!< Offset 0x100C*/
\r
1234 __IO uint32_t TRANSMIT_DESCRIPTOR_LIST_ADDRESS; /*!< Offset 0x1010*/
\r
1235 __IO uint32_t STATUS; /*!< Offset 0x1014*/
\r
1236 __IO uint32_t OPERATION_MODE; /*!<Register 6 [Operation Mode Register] Offset 0x1018*/
\r
1237 __IO uint32_t INTERRUPT_ENABLE; /*!<Register 7 [Interrupt Enable Register] Offset 0x101C*/
\r
1238 __I uint32_t MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER; /*!< Offset 0x1020*/
\r
1239 __IO uint32_t RECEIVE_INTERRUPT_WATCHDOG_TIMER; /*!< Offset 0x1024*/
\r
1240 __I uint32_t RESERVED10;
\r
1241 __I uint32_t AHB_STATUS; /*!<Register 11 [AHB Status Register] Offset 0x102C*/
\r
1242 __I uint32_t RESERVED11[6];
\r
1243 __I uint32_t CURRENT_HOST_TRANSMIT_DESCRIPTOR; /*!< Offset 0x1048*/
\r
1244 __I uint32_t CURRENT_HOST_RECEIVE_DESCRIPTOR; /*!< Offset 0x104C*/
\r
1245 __I uint32_t CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS; /*!<Register 20 [Current Host Transmit Buffer Address Register] Offset 0x1050*/
\r
1246 __I uint32_t CURRENT_HOST_RECEIVE_BUFFER_ADDRESS; /*!<Register 21 [Current Host Receive Buffer Address Register] Offset 0x1054*/
\r
1247 __IO uint32_t HW_FEATURE; /*!<Register 22 [HW Feature Register] Offset 0x1058*/
\r
1248 }ETH_GLOBAL_TypeDef;
\r
1250 #define ETH0_BASE ((uint32_t)0x5000C000U)
\r
1251 #define ETH_GLOBAL_BASE (0x0000U)
\r
1253 /***************************************************************************/
\r
1255 /***************************************************************************/
\r
1258 *Ethernet I/O Control Register
\r
1261 __IO uint32_t CON; /*!<Ethernet 0 Port Control Register Offset 0x0000*/
\r
1262 }ETH0_CON_GLOBAL_TypeDef;
\r
1264 #define ETH0_CON_BASE ((uint32_t)0x50004040U)
\r
1265 #define ETH0_CON_GLOBAL_BASE (0x0000U)
\r
1266 /***************************************************************************/
\r
1267 /* Peripheral Declaration */
\r
1268 /***************************************************************************/
\r
1269 #define ETH0_CON ((ETH0_CON_GLOBAL_TypeDef*)(ETH0_CON_BASE + ETH0_CON_GLOBAL_BASE))
\r
1270 #define ETH0 ((ETH_GLOBAL_TypeDef*)(ETH0_BASE + ETH_GLOBAL_BASE))
\r
1272 /***************************************************************************/
\r
1274 /***************************************************************************/
\r
1277 *Cortex M4 - Embedded Trace Macrocell
\r
1279 typedef struct { /*!< ETM Structure */
\r
1280 __IO uint32_t ETMCR; /*!< The ETMCR characteristics are:Purpose Controls general operation of the ETM, such as whether tracing is enabled.Configurations This register is only available if the processor is configured to use the ETM. */
\r
1281 __I uint32_t ETMCCR; /*!< The ETM Configuration Code Register characteristics are:Purpose Enables software to read the implementation-specific configuration of the ETM.Configurations This register is only available if the processor is configured to use the ETM. */
\r
1282 __IO uint32_t ETMTRIGGER; /*!< The Trigger Event Register defines the event that controls the trigger. It is: register 0x02, at offset 0x08 in a memory-mapped implementation a write-only register, although in architecture versions 3.1 and later it is read/write when bit [11] ofthe Configuration Code Extension Register is set, see Configuration Code Extension Register,ETMv3.1 and later on page 3-76. */
\r
1283 __I uint32_t RESERVED0;
\r
1284 __IO uint32_t ETMSR; /*!< The ETM Status Register provides information about the current status of the trace and trigger logic. It is: register 0x04, at offset 0x10 in a memory-mapped implementation a read/write register */
\r
1285 __I uint32_t ETMSCR; /*!< The ETMSCR characteristics are:Purpose Shows the ETM features supported by the implementation of the ETM macrocell.Configurations This register is only available if the processor is configured to use the ETM. */
\r
1286 __I uint32_t RESERVED1[2];
\r
1287 __IO uint32_t ETMTEEVR; /*!< The TraceEnable Event Register defines the TraceEnable enabling event. It is: register 0x08, at offset 0x20 in a memory-mapped implementation a write-only register, although in architecture versions 3.1 and later it is read/write when bit [11] of the Configuration Code Extension Register is set, see Configuration Code Extension Register, ETMv3.1 and later on page 3-76. */
\r
1288 __IO uint32_t ETMTECR1; /*!< The ETMTECR1 characteristics are:Purpose Enables the start/stop logic used for trace enable.Configurations This register is only available if the processor is configured to use the ETM. */
\r
1289 __IO uint32_t ETMFFLR; /*!< The FIFOFULL Level Register holds the level below which the FIFO is considered full, although its function varies for different ETM architectures. From ETMv3.0 the value in this register also controls the point at which data trace suppression occurs.The FIFOFULL Level Register is: register 0x0B, at offset 0x2C in a memory-mapped implementation a read/write register in ETM architecture versions 2.0 and later. */
\r
1290 __I uint32_t RESERVED2[69];
\r
1291 __IO uint32_t ETMCNTRLDVR1; /*!< A Counter Reload Value Register specifies the starting value of the associated counter. The counter is automatically loaded with this value when this register is programmed and when the ETM Programming bit is set. It is then reloaded with this value whenever the counter reload event, specified by the Counter Reload Event Register, is active. The Counter Reload Value Registers are: registers 0x50 to 0x53, at offsets 0x140, 0x144, 0x148, and 0x14C in a memory-mapped implementation write-only registers, altho */
\r
1292 __I uint32_t RESERVED3[39];
\r
1293 __I uint32_t ETMSYNCFR; /*!< The ETMSYNCFR characteristics are:Purpose Holds the trace synchronization frequency value.From ETMv3.5, this value must be set to a value greater than the size of the FIFO, or to zero. Values greater than zero but less than the FIFO size are still not permitted.A value of zero disables periodic synchronization based on the synchronization frequency counter. This does not affect other sources of synchronization, such as external requests from a CoreSight system. */
\r
1294 __I uint32_t ETMIDR; /*!< The ETMIDR characteristics are:Purpose Holds the ETM architecture variant, and defines the programmers model for the ETM.Configurations This register is only available if the processor is configured to use the ETM. */
\r
1295 __I uint32_t ETMCCER; /*!< The ETMCCER characteristics are:Purpose Holds ETM configuration information additional to that in the ETMCCR.See Configuration Code Register, ETMCCR on page 10-14.Configurations This register is only available if the processor is configured to use the ETM. */
\r
1296 __I uint32_t RESERVED4;
\r
1297 __IO uint32_t ETMTESSEICR; /*!< The Trace Start/Stop EmbeddedICE Control Register specifies the EmbeddedICE watchpoint comparator inputs that are used as trace start and stop resources. It is: register 0x7C, at offset 0x1F0 in a memory-mapped implementation a write-only register, that is read/write when bit [11] of the Configuration Code Extension Register is set, see Configuration Code Extension Register, ETMv3.1 and later on page 3-76. */
\r
1298 __I uint32_t RESERVED5;
\r
1299 __IO uint32_t ETMTSEVR; /*!< The ETMTSEVR characteristics are:Purpose Defines an event that requests the insertion of a timestamp into the trace stream. */
\r
1300 __I uint32_t RESERVED6;
\r
1301 __IO uint32_t ETMTRACEIDR; /*!< The ETMTRACEIDR characteristics are:Purpose Defines the 7-bit Trace ID, for output to the trace bus.This register is used in systems where multiple trace sources are present and tracing simultaneously. For example, where an ETM outputs trace onto the AMBA version 3 Advanced Trace Bus (ATB), a unique ID is required for each trace source so that the trace can be uniquely identified as coming from a particular trace source. For more information about the AMBA version 3 ATB, see the CoreSight Architecture Spec */
\r
1302 __I uint32_t RESERVED7;
\r
1303 __I uint32_t ETMIDR2; /*!< The ETMIDR2 characteristics are:Purpose Provides an extension to the ETM ID register, ETMIDR. */
\r
1304 __I uint32_t RESERVED8[66];
\r
1305 __I uint32_t ETMPDSR; /*!< The ETMPDSR characteristics are:Purpose Indicates the power-down status of the ETM.Configurations This register is only available if the processor is configured to use an ETM. */
\r
1306 __I uint32_t RESERVED9[754];
\r
1307 __I uint32_t ITMISCIN; /*!< The ITMISCIN characteristics are:Purpose Integration test.Configurations This register is only available if the processor is configured to use the ETM. */
\r
1308 __I uint32_t RESERVED10;
\r
1309 __IO uint32_t ITTRIGOUT; /*!< The ITMISCIN characteristics are:Purpose Integration test.Usage constraints You must set bit [0] of ETMITCTRL to use this register.Configurations This register is only available if the processor is configured to use the ETM. */
\r
1310 __I uint32_t RESERVED11;
\r
1311 __I uint32_t ETM_ITATBCTR2; /*!< The ETM_ITATBCTR2 characteristics are:Purpose Integration test.Usage constraints You must set bit [0] of ETMITCTRL to use this register.Configurations This register is only available if the processor is configured to use the ETM. */
\r
1312 __I uint32_t RESERVED12;
\r
1313 __IO uint32_t ETM_ITATBCTR0; /*!< The Integration Test ATB Control (ETM_ITATBCTR0) characteristics are:Purpose Integration test.Usage constraints You must set bit [0] of ETMITCTRL to use this register.Configurations This register is only available if the processor is configured to use the ETM. */
\r
1314 __I uint32_t RESERVED13;
\r
1315 __IO uint32_t ETMITCTRL; /*!< The Integration Mode Control Register (ITCTRL) is used to enable topology detection or to check integration testing. It is: register 0x3C0, at offset 0xF00 in a memory-mapped implementation */
\r
1316 __I uint32_t RESERVED14[39];
\r
1317 __IO uint32_t ETMCLAIMSET; /*!< The Claim Tag Set Register (CLAIMSET) is used to set bits in the claim tag and find the number of bits supported by the claim tag. It is: register 0x3E8, at offset 0xFA0 in a memory-mapped implementation */
\r
1318 __IO uint32_t ETMCLAIMCLR; /*!< The Claim Tag Clear Register (CLAIMCLR) is used to clear bits in the claim tag to 0, and to find the current value of the claim tag. It is: register 0x3E9, at offset 0xFA4 in a memory-mapped implementation */
\r
1319 __I uint32_t RESERVED15[2];
\r
1320 __IO uint32_t ETMLAR; /*!< The Lock Access Register (LAR or LOCKACCESS) is used to lock and unlock access to all other ETM registers. It is: register 0x3EC, at offset 0xFB0 in a memory-mapped implementation */
\r
1321 __I uint32_t ETMLSR; /*!< The Lock Status Register (LSR or LOCKSTATUS) has two uses: If you read this register from any interface, you can check bit [0] to find out whether the lock registers are implemented for the interface you are using. If you read this register from an interface for which lock registers are implemented, you can check bit [1] to find out whether the registers are currently locked.The Lock Status Register is: register 0x3ED, at offset 0xFB4 in a memory-mapped implementation */
\r
1322 __I uint32_t ETMAUTHSTATUS; /*!< The Authentication Status Register (AUTHSTATUS) reports the level of tracing currently permitted by the authentication signals provided to the ETM. It is: register 0x3EE, at offset 0xFB8 in a memory-mapped implementation */
\r
1323 __I uint32_t RESERVED16[4];
\r
1324 __I uint32_t ETMDEVTYPE; /*!< The Device Type Register (DEVTYPE) returns the CoreSight device type of the component. It is: register 0x3F3, at offset 0xFCC in a memory-mapped implementation present in all CoreSight components. */
\r
1325 __I uint32_t ETMPIDR4; /*!< The Peripheral ID4 Register holds peripheral identification information. */
\r
1326 __I uint32_t ETMPIDR5; /*!< Peripheral Identification register5. See ARM Embedded TraceMacrocell Architecture Specification */
\r
1327 __I uint32_t ETMPIDR6; /*!< Peripheral Identification register6. See ARM Embedded TraceMacrocell Architecture Specification */
\r
1328 __I uint32_t ETMPIDR7; /*!< Peripheral Identification register7. See ARM Embedded TraceMacrocell Architecture Specification */
\r
1329 __I uint32_t ETMPIDR0; /*!< The Peripheral ID0 Register holds peripheral identification information. */
\r
1330 __I uint32_t ETMPIDR1; /*!< The Peripheral ID1 Register holds peripheral identification information. */
\r
1331 __I uint32_t ETMPIDR2; /*!< The Peripheral ID2 Register holds peripheral identification information. */
\r
1332 __I uint32_t ETMPIDR3; /*!< The Peripheral ID3 Register holds peripheral identification information. */
\r
1333 __I uint32_t ETMCIDR0; /*!< The Component ID0 Register holds byte 0 of the CoreSight preamble information. */
\r
1334 __I uint32_t ETMCIDR1; /*!< The Component ID1 Register holds byte 1 of the CoreSight preamble information. */
\r
1335 __I uint32_t ETMCIDR2; /*!< The Component ID2 Register holds byte 2 of the CoreSight preamble information. */
\r
1336 __I uint32_t ETMCIDR3; /*!< The Component ID3 Register holds byte 3 of the CoreSight preamble information. */
\r
1339 #define ETM_BASE ((uint32_t)0xE0041000U)
\r
1340 #define ETM_GLOBAL_BASE (0x0000U)
\r
1341 /***************************************************************************/
\r
1342 /* Peripheral Declaration */
\r
1343 /***************************************************************************/
\r
1344 #define ETM ((ETM_Type *)(ETM_BASE + ETM_GLOBAL_BASE))
\r
1346 /***************************************************************************/
\r
1348 /***************************************************************************/
\r
1354 __IO uint32_t CLC; /*!<Clock Control Register Offset 0x0000*/
\r
1355 __I uint32_t RESERVED1;
\r
1356 __I uint32_t ID; /*!<Module Identification Register Offset 0x0008*/
\r
1357 }FCE_GLOBAL_TypeDef;
\r
1360 *Generic CRC Engine registers
\r
1363 __IO uint32_t IR; /*!<Input Register 0 Offset 0x0020*/
\r
1364 __I uint32_t RES; /*!<CRC Result Register 0 Offset 0x0024*/
\r
1365 __IO uint32_t CFG; /*!<CRC Configuration Register 0 Offset 0x0028*/
\r
1366 __IO uint32_t STS; /*!<CRC Status Register 0 Offset 0x002C*/
\r
1367 __IO uint32_t LENGTH; /*!<CRC Length Register 0 Offset 0x0030*/
\r
1368 __IO uint32_t CHECK; /*!<CRC Check Register 0 Offset 0x0034*/
\r
1369 __IO uint32_t CRC; /*!<CRC Register 0 Offset 0x0038*/
\r
1370 __IO uint32_t CTR; /*!<CRC Test Register 0 Offset 0x003C*/
\r
1373 #define FCE_BASE ((uint32_t)0x50020000U)
\r
1374 #define FCE_GLOBAL_BASE (0x0000U)
\r
1375 #define FCE_KE0_BASE (0x0020U)
\r
1376 #define FCE_KE1_BASE (0x0040U)
\r
1377 #define FCE_KE2_BASE (0x0060U)
\r
1378 #define FCE_KE3_BASE (0x0080U)
\r
1379 /***************************************************************************/
\r
1380 /* Peripheral Declaration */
\r
1381 /***************************************************************************/
\r
1382 #define FCE ((FCE_GLOBAL_TypeDef*)(FCE_BASE + FCE_GLOBAL_BASE))
\r
1383 #define FCE_KE0 ((FCE_KE_TypeDef*)(FCE_BASE + FCE_KE0_BASE))
\r
1384 #define FCE_KE1 ((FCE_KE_TypeDef*)(FCE_BASE + FCE_KE1_BASE))
\r
1385 #define FCE_KE2 ((FCE_KE_TypeDef*)(FCE_BASE + FCE_KE2_BASE))
\r
1386 #define FCE_KE3 ((FCE_KE_TypeDef*)(FCE_BASE + FCE_KE3_BASE))
\r
1388 /***************************************************************************/
\r
1390 /***************************************************************************/
\r
1393 *FLASH0 GLOBAL registers
\r
1396 __I uint32_t ID; /*!<Flash Module Identification Register Offset 0x1008*/
\r
1397 __I uint32_t RESERVED1;
\r
1398 __I uint32_t FSR; /*!<Flash Status Register Offset 0x1010*/
\r
1399 __IO uint32_t FCON; /*!<Flash Configuration Register Offset 0x1014*/
\r
1400 __IO uint32_t MARP; /*!<Margin Control Register PFLASH Offset 0x1018*/
\r
1401 __I uint32_t RESERVED2;
\r
1402 __I uint32_t PROCON0; /*!<Flash Protection Configuration Register User 0 Offset 0x1020*/
\r
1403 __I uint32_t PROCON1; /*!<Flash Protection Configuration Register User 1 Offset 0x1024*/
\r
1404 __I uint32_t PROCON2; /*!<Flash Protection Configuration Register User 2 Offset 0x1028*/
\r
1405 }FLASH0_GLOBAL_TypeDef;
\r
1407 #define FLASH0_BASE ((uint32_t)0x58001000U)
\r
1408 #define FLASH0_GLOBAL_BASE (0x1008U)
\r
1409 /***************************************************************************/
\r
1410 /* Peripheral Declaration */
\r
1411 /***************************************************************************/
\r
1412 #define FLASH0 ((FLASH0_GLOBAL_TypeDef*)(FLASH0_BASE + FLASH0_GLOBAL_BASE))
\r
1414 /***************************************************************************/
\r
1416 /***************************************************************************/
\r
1419 *Cortex M4 - Flash Patch and Breakpoint
\r
1421 typedef struct { /*!< FPB Structure */
\r
1422 __IO uint32_t FP_CTRL; /*!< The FP_CTRL Register characteristics are:Purpose Provides FPB implementation information, and the global enable for the FPB unit.If implemented: The instruction address comparators start at FP_COMP0. This means the last instruction address comparator is FP_COMPn, where n = (NUM_CODE-1). The maximum number of instruction address comparators is 127. The literal address comparators start at FP_COMPm, where m=NUM_CODE. This means the last literal address comparator is at FP_COMPp, where p=(NUM_CODE+NUM_LIT-1). */
\r
1423 __IO uint32_t FP_REMAP; /*!< The FP_REMAP register characteristics are:Purpose Indicates whether the implementation supports flash patch remap, and if it does, holds the SRAM address for remap.The remap base address must be aligned to the number of words required to support the implemented comparators, that is to (NUM_CODE+NUM_LIT) words, with a minimum alignment of 8 words. Because remap is into the SRAM memory region, 0x20000000-0x3FFFFFFF, bits [31:29] of the remap address are 0b001. */
\r
1424 __IO uint32_t FP_COMP0; /*!< The FP_COMP0 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */
\r
1425 __IO uint32_t FP_COMP1; /*!< The FP_COMP1 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */
\r
1426 __IO uint32_t FP_COMP2; /*!< The FP_COMP2 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */
\r
1427 __IO uint32_t FP_COMP3; /*!< The FP_COMP3 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */
\r
1428 __IO uint32_t FP_COMP4; /*!< The FP_COMP4 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */
\r
1429 __IO uint32_t FP_COMP5; /*!< The FP_COMP5 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */
\r
1430 __IO uint32_t FP_COMP6; /*!< The FP_COMP6 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */
\r
1431 __IO uint32_t FP_COMP7; /*!< The FP_COMP7 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */
\r
1432 __I uint32_t RESERVED0[1002];
\r
1433 __I uint32_t FPBPID4; /*!< Peripheral identification register4 */
\r
1434 __I uint32_t FPBPID5; /*!< Peripheral identification register5 */
\r
1435 __I uint32_t FPBPID6; /*!< Peripheral identification register6 */
\r
1436 __I uint32_t FPBPID7; /*!< Peripheral identification register7 */
\r
1437 __I uint32_t FPBPID0; /*!< Peripheral identification register0 */
\r
1438 __I uint32_t FPBPID1; /*!< Peripheral identification register1 */
\r
1439 __I uint32_t FPBPID2; /*!< Peripheral identification register2 */
\r
1440 __I uint32_t FPBPID3; /*!< Peripheral identification register3 */
\r
1441 __I uint32_t FPBCID0; /*!< Component identification register0 */
\r
1442 __I uint32_t FPBCID1; /*!< Component identification register1 */
\r
1443 __I uint32_t FPBCID2; /*!< Component identification register2 */
\r
1444 __I uint32_t FPBCID3; /*!< Component identification register3 */
\r
1447 #define FPB_BASE ((uint32_t)0xE0002000U)
\r
1448 #define FPB_GLOBAL_BASE (0x0000U)
\r
1449 /***************************************************************************/
\r
1450 /* Peripheral Declaration */
\r
1451 /***************************************************************************/
\r
1452 #define FPB ((FPB_Type *)(FPB_BASE + FPB_GLOBAL_BASE))
\r
1454 /***************************************************************************/
\r
1456 /***************************************************************************/
\r
1459 *LEDTS0 KERNEL registers
\r
1462 __I uint32_t ID; /*!<Module Identification Register Offset 0x0000*/
\r
1463 __IO uint32_t GLOBCTL; /*!<Global Control Register Offset 0x0004*/
\r
1464 __IO uint32_t FNCTL; /*!<Function Control Register Offset 0x0008*/
\r
1465 __IO uint32_t EVFR; /*!<Event Flag Register Offset 0x000C*/
\r
1466 __IO uint32_t TSVAL; /*!<Touch-sense TS-Counter Value Offset 0x0010*/
\r
1467 __IO uint32_t LINE0; /*!<Line Pattern Register 0 Offset 0x0014*/
\r
1468 __IO uint32_t LINE1; /*!<Line Pattern Register 1 Offset 0x0018*/
\r
1469 __IO uint32_t LDCMP0; /*!<LED Compare Register 0 Offset 0x001C*/
\r
1470 __IO uint32_t LDCMP1; /*!<LED Compare Register 1 Offset 0x0020*/
\r
1471 __IO uint32_t TSCMP0; /*!<Touch-sense Compare Register 0 Offset 0x0024*/
\r
1472 __IO uint32_t TSCMP1; /*!<Touch-sense Compare Register 1 Offset 0x0028*/
\r
1473 }LEDTS0_GLOBAL_TypeDef;
\r
1475 #define LEDTS0_BASE ((uint32_t)0x48010000U)
\r
1476 #define LEDTS0_GLOBAL_BASE (0x0000U)
\r
1477 /***************************************************************************/
\r
1478 /* Peripheral Declaration */
\r
1479 /***************************************************************************/
\r
1480 #define LEDTS0 ((LEDTS0_GLOBAL_TypeDef*)(LEDTS0_BASE + LEDTS0_GLOBAL_BASE))
\r
1482 /***************************************************************************/
\r
1484 /***************************************************************************/
\r
1487 *Peripheral Bridge Status and Write Error Address registers
\r
1490 __IO uint32_t STS; /*!<Peripheral Bridge Status Register Offset 0x0000*/
\r
1491 __I uint32_t WADDR; /*!<PBA Write Error Address Register Offset 0x0004*/
\r
1492 }PBA_GLOBAL_TypeDef;
\r
1494 #define PBA0_BASE ((uint32_t)0x40000000U)
\r
1495 #define PBA1_BASE ((uint32_t)0x48000000U)
\r
1496 #define PBA_GLOBAL_BASE (0x0000U)
\r
1497 /***************************************************************************/
\r
1498 /* Peripheral Declaration */
\r
1499 /***************************************************************************/
\r
1500 #define PBA0 ((PBA_GLOBAL_TypeDef*)(PBA0_BASE + PBA_GLOBAL_BASE))
\r
1501 #define PBA1 ((PBA_GLOBAL_TypeDef*)(PBA1_BASE + PBA_GLOBAL_BASE))
\r
1503 /***************************************************************************/
\r
1505 /***************************************************************************/
\r
1511 __I uint32_t ID; /*!<PMU0 Identification Register Offset 0x0508*/
\r
1512 }PMU0_GLOBAL_TypeDef;
\r
1514 #define PMU0_BASE ((uint32_t)0x58000000U)
\r
1515 #define PMU0_GLOBAL_BASE (0x0508U)
\r
1516 /***************************************************************************/
\r
1517 /* Peripheral Declaration */
\r
1518 /***************************************************************************/
\r
1519 #define PMU0 ((PMU0_GLOBAL_TypeDef*)(PMU0_BASE + PMU0_GLOBAL_BASE))
\r
1521 // ------------------------------------------------------------------------------------------------
\r
1522 // ----- PORT0 -----
\r
1523 // ------------------------------------------------------------------------------------------------
\r
1527 * @brief Port 0 (PORT0)
\r
1530 typedef struct { /*!< PORT0 Structure */
\r
1531 __IO uint32_t OUT; /*!< Port 0 Output Register */
\r
1532 __O uint32_t OMR; /*!< Port 0 Output Modification Register */
\r
1533 __I uint32_t RESERVED0[2];
\r
1534 __IO uint32_t IOCR0; /*!< Port 0 Input/Output Control Register 0 */
\r
1535 __IO uint32_t IOCR4; /*!< Port 0 Input/Output Control Register 4 */
\r
1536 __IO uint32_t IOCR8; /*!< Port 0 Input/Output Control Register 8 */
\r
1537 __IO uint32_t IOCR12; /*!< Port 0 Input/Output Control Register 12 */
\r
1538 __I uint32_t RESERVED1;
\r
1539 __I uint32_t IN; /*!< Port 0 Input Register */
\r
1540 __I uint32_t RESERVED2[6];
\r
1541 __IO uint32_t PDR0; /*!< Port 0 Pad Driver Mode 0 Register */
\r
1542 __IO uint32_t PDR1; /*!< Port 0 Pad Driver Mode 1 Register */
\r
1543 __I uint32_t RESERVED3[6];
\r
1544 __I uint32_t PDISC; /*!< Port 0 Pin Function Decision Control Register */
\r
1545 __I uint32_t RESERVED4[3];
\r
1546 __IO uint32_t PPS; /*!< Port 0 Pin Power Save Register */
\r
1547 __IO uint32_t HWSEL; /*!< Port 0 Pin Hardware Select Register */
\r
1551 // ------------------------------------------------------------------------------------------------
\r
1552 // ----- PORT1 -----
\r
1553 // ------------------------------------------------------------------------------------------------
\r
1557 * @brief Port 1 (PORT1)
\r
1560 typedef struct { /*!< PORT1 Structure */
\r
1561 __IO uint32_t OUT; /*!< Port 1 Output Register */
\r
1562 __O uint32_t OMR; /*!< Port 1 Output Modification Register */
\r
1563 __I uint32_t RESERVED0[2];
\r
1564 __IO uint32_t IOCR0; /*!< Port 1 Input/Output Control Register 0 */
\r
1565 __IO uint32_t IOCR4; /*!< Port 1 Input/Output Control Register 4 */
\r
1566 __IO uint32_t IOCR8; /*!< Port 1 Input/Output Control Register 8 */
\r
1567 __IO uint32_t IOCR12; /*!< Port 1 Input/Output Control Register 12 */
\r
1568 __I uint32_t RESERVED1;
\r
1569 __I uint32_t IN; /*!< Port 1 Input Register */
\r
1570 __I uint32_t RESERVED2[6];
\r
1571 __IO uint32_t PDR0; /*!< Port 1 Pad Driver Mode 0 Register */
\r
1572 __IO uint32_t PDR1; /*!< Port 1 Pad Driver Mode 1 Register */
\r
1573 __I uint32_t RESERVED3[6];
\r
1574 __I uint32_t PDISC; /*!< Port 1 Pin Function Decision Control Register */
\r
1575 __I uint32_t RESERVED4[3];
\r
1576 __IO uint32_t PPS; /*!< Port 1 Pin Power Save Register */
\r
1577 __IO uint32_t HWSEL; /*!< Port 1 Pin Hardware Select Register */
\r
1581 // ------------------------------------------------------------------------------------------------
\r
1582 // ----- PORT2 -----
\r
1583 // ------------------------------------------------------------------------------------------------
\r
1587 * @brief Port 2 (PORT2)
\r
1590 typedef struct { /*!< PORT2 Structure */
\r
1591 __IO uint32_t OUT; /*!< Port 2 Output Register */
\r
1592 __O uint32_t OMR; /*!< Port 2 Output Modification Register */
\r
1593 __I uint32_t RESERVED0[2];
\r
1594 __IO uint32_t IOCR0; /*!< Port 2 Input/Output Control Register 0 */
\r
1595 __IO uint32_t IOCR4; /*!< Port 2 Input/Output Control Register 4 */
\r
1596 __IO uint32_t IOCR8; /*!< Port 2 Input/Output Control Register 8 */
\r
1597 __IO uint32_t IOCR12; /*!< Port 2 Input/Output Control Register 12 */
\r
1598 __I uint32_t RESERVED1;
\r
1599 __I uint32_t IN; /*!< Port 2 Input Register */
\r
1600 __I uint32_t RESERVED2[6];
\r
1601 __IO uint32_t PDR0; /*!< Port 2 Pad Driver Mode 0 Register */
\r
1602 __IO uint32_t PDR1; /*!< Port 2 Pad Driver Mode 1 Register */
\r
1603 __I uint32_t RESERVED3[6];
\r
1604 __I uint32_t PDISC; /*!< Port 2 Pin Function Decision Control Register */
\r
1605 __I uint32_t RESERVED4[3];
\r
1606 __IO uint32_t PPS; /*!< Port 2 Pin Power Save Register */
\r
1607 __IO uint32_t HWSEL; /*!< Port 2 Pin Hardware Select Register */
\r
1611 // ------------------------------------------------------------------------------------------------
\r
1612 // ----- PORT3 -----
\r
1613 // ------------------------------------------------------------------------------------------------
\r
1617 * @brief Port 3 (PORT3)
\r
1620 typedef struct { /*!< PORT3 Structure */
\r
1621 __IO uint32_t OUT; /*!< Port 3 Output Register */
\r
1622 __O uint32_t OMR; /*!< Port 3 Output Modification Register */
\r
1623 __I uint32_t RESERVED0[2];
\r
1624 __IO uint32_t IOCR0; /*!< Port 3 Input/Output Control Register 0 */
\r
1625 __IO uint32_t IOCR4; /*!< Port 3 Input/Output Control Register 4 */
\r
1626 __IO uint32_t IOCR8; /*!< Port 3 Input/Output Control Register 8 */
\r
1627 __IO uint32_t IOCR12; /*!< Port 3 Input/Output Control Register 12 */
\r
1628 __I uint32_t RESERVED1;
\r
1629 __I uint32_t IN; /*!< Port 3 Input Register */
\r
1630 __I uint32_t RESERVED2[6];
\r
1631 __IO uint32_t PDR0; /*!< Port 3 Pad Driver Mode 0 Register */
\r
1632 __IO uint32_t PDR1; /*!< Port 3 Pad Driver Mode 1 Register */
\r
1633 __I uint32_t RESERVED3[6];
\r
1634 __I uint32_t PDISC; /*!< Port 3 Pin Function Decision Control Register */
\r
1635 __I uint32_t RESERVED4[3];
\r
1636 __IO uint32_t PPS; /*!< Port 3 Pin Power Save Register */
\r
1637 __IO uint32_t HWSEL; /*!< Port 3 Pin Hardware Select Register */
\r
1641 // ------------------------------------------------------------------------------------------------
\r
1642 // ----- PORT4 -----
\r
1643 // ------------------------------------------------------------------------------------------------
\r
1647 * @brief Port 4 (PORT4)
\r
1650 typedef struct { /*!< PORT4 Structure */
\r
1651 __IO uint32_t OUT; /*!< Port 4 Output Register */
\r
1652 __O uint32_t OMR; /*!< Port 4 Output Modification Register */
\r
1653 __I uint32_t RESERVED0[2];
\r
1654 __IO uint32_t IOCR0; /*!< Port 4 Input/Output Control Register 0 */
\r
1655 __IO uint32_t IOCR4; /*!< Port 4 Input/Output Control Register 4 */
\r
1656 __I uint32_t RESERVED1[3];
\r
1657 __I uint32_t IN; /*!< Port 4 Input Register */
\r
1658 __I uint32_t RESERVED2[6];
\r
1659 __IO uint32_t PDR0; /*!< Port 4 Pad Driver Mode 0 Register */
\r
1660 __I uint32_t RESERVED3[7];
\r
1661 __I uint32_t PDISC; /*!< Port 4 Pin Function Decision Control Register */
\r
1662 __I uint32_t RESERVED4[3];
\r
1663 __IO uint32_t PPS; /*!< Port 4 Pin Power Save Register */
\r
1664 __IO uint32_t HWSEL; /*!< Port 4 Pin Hardware Select Register */
\r
1668 // ------------------------------------------------------------------------------------------------
\r
1669 // ----- PORT5 -----
\r
1670 // ------------------------------------------------------------------------------------------------
\r
1674 * @brief Port 5 (PORT5)
\r
1677 typedef struct { /*!< PORT5 Structure */
\r
1678 __IO uint32_t OUT; /*!< Port 5 Output Register */
\r
1679 __O uint32_t OMR; /*!< Port 5 Output Modification Register */
\r
1680 __I uint32_t RESERVED0[2];
\r
1681 __IO uint32_t IOCR0; /*!< Port 5 Input/Output Control Register 0 */
\r
1682 __IO uint32_t IOCR4; /*!< Port 5 Input/Output Control Register 4 */
\r
1683 __IO uint32_t IOCR8; /*!< Port 5 Input/Output Control Register 8 */
\r
1684 __I uint32_t RESERVED1[2];
\r
1685 __I uint32_t IN; /*!< Port 5 Input Register */
\r
1686 __I uint32_t RESERVED2[6];
\r
1687 __IO uint32_t PDR0; /*!< Port 5 Pad Driver Mode 0 Register */
\r
1688 __IO uint32_t PDR1; /*!< Port 5 Pad Driver Mode 1 Register */
\r
1689 __I uint32_t RESERVED3[6];
\r
1690 __I uint32_t PDISC; /*!< Port 5 Pin Function Decision Control Register */
\r
1691 __I uint32_t RESERVED4[3];
\r
1692 __IO uint32_t PPS; /*!< Port 5 Pin Power Save Register */
\r
1693 __IO uint32_t HWSEL; /*!< Port 5 Pin Hardware Select Register */
\r
1697 // ------------------------------------------------------------------------------------------------
\r
1698 // ----- PORT6 -----
\r
1699 // ------------------------------------------------------------------------------------------------
\r
1703 * @brief Port 6 (PORT6)
\r
1706 typedef struct { /*!< PORT6 Structure */
\r
1707 __IO uint32_t OUT; /*!< Port 6 Output Register */
\r
1708 __O uint32_t OMR; /*!< Port 6 Output Modification Register */
\r
1709 __I uint32_t RESERVED0[2];
\r
1710 __IO uint32_t IOCR0; /*!< Port 6 Input/Output Control Register 0 */
\r
1711 __IO uint32_t IOCR4; /*!< Port 6 Input/Output Control Register 4 */
\r
1712 __I uint32_t RESERVED1[3];
\r
1713 __I uint32_t IN; /*!< Port 6 Input Register */
\r
1714 __I uint32_t RESERVED2[6];
\r
1715 __IO uint32_t PDR0; /*!< Port 6 Pad Driver Mode 0 Register */
\r
1716 __I uint32_t RESERVED3[7];
\r
1717 __I uint32_t PDISC; /*!< Port 6 Pin Function Decision Control Register */
\r
1718 __I uint32_t RESERVED4[3];
\r
1719 __IO uint32_t PPS; /*!< Port 6 Pin Power Save Register */
\r
1720 __IO uint32_t HWSEL; /*!< Port 6 Pin Hardware Select Register */
\r
1724 // ------------------------------------------------------------------------------------------------
\r
1725 // ----- PORT14 -----
\r
1726 // ------------------------------------------------------------------------------------------------
\r
1730 * @brief Port 14 (PORT14)
\r
1733 typedef struct { /*!< PORT14 Structure */
\r
1734 __IO uint32_t OUT; /*!< Port 14 Output Register */
\r
1735 __O uint32_t OMR; /*!< Port 14 Output Modification Register */
\r
1736 __I uint32_t RESERVED0[2];
\r
1737 __IO uint32_t IOCR0; /*!< Port 14 Input/Output Control Register 0 */
\r
1738 __IO uint32_t IOCR4; /*!< Port 14 Input/Output Control Register 4 */
\r
1739 __IO uint32_t IOCR8; /*!< Port 14 Input/Output Control Register 8 */
\r
1740 __IO uint32_t IOCR12; /*!< Port 14 Input/Output Control Register 12 */
\r
1741 __I uint32_t RESERVED1;
\r
1742 __I uint32_t IN; /*!< Port 14 Input Register */
\r
1743 __I uint32_t RESERVED2[14];
\r
1744 __IO uint32_t PDISC; /*!< Port 14 Pin Function Decision Control Register */
\r
1745 __I uint32_t RESERVED3[3];
\r
1746 __IO uint32_t PPS; /*!< Port 14 Pin Power Save Register */
\r
1747 __IO uint32_t HWSEL; /*!< Port 14 Pin Hardware Select Register */
\r
1751 // ------------------------------------------------------------------------------------------------
\r
1752 // ----- PORT15 -----
\r
1753 // ------------------------------------------------------------------------------------------------
\r
1757 * @brief Port 15 (PORT15)
\r
1760 typedef struct { /*!< PORT15 Structure */
\r
1761 __IO uint32_t OUT; /*!< Port 15 Output Register */
\r
1762 __O uint32_t OMR; /*!< Port 15 Output Modification Register */
\r
1763 __I uint32_t RESERVED0[2];
\r
1764 __IO uint32_t IOCR0; /*!< Port 15 Input/Output Control Register 0 */
\r
1765 __IO uint32_t IOCR4; /*!< Port 15 Input/Output Control Register 4 */
\r
1766 __IO uint32_t IOCR8; /*!< Port 15 Input/Output Control Register 8 */
\r
1767 __IO uint32_t IOCR12; /*!< Port 15 Input/Output Control Register 12 */
\r
1768 __I uint32_t RESERVED1;
\r
1769 __I uint32_t IN; /*!< Port 15 Input Register */
\r
1770 __I uint32_t RESERVED2[14];
\r
1771 __IO uint32_t PDISC; /*!< Port 15 Pin Function Decision Control Register */
\r
1772 __I uint32_t RESERVED3[3];
\r
1773 __IO uint32_t PPS; /*!< Port 15 Pin Power Save Register */
\r
1774 __IO uint32_t HWSEL; /*!< Port 15 Pin Hardware Select Register */
\r
1777 #define PORT0_BASE 0x48028000
\r
1778 #define PORT1_BASE 0x48028100
\r
1779 #define PORT2_BASE 0x48028200
\r
1780 #define PORT3_BASE 0x48028300
\r
1781 #define PORT4_BASE 0x48028400
\r
1782 #define PORT5_BASE 0x48028500
\r
1783 #define PORT6_BASE 0x48028600
\r
1784 #define PORT14_BASE 0x48028E00
\r
1785 #define PORT15_BASE 0x48028F00
\r
1787 #define PORT0 ((PORT0_Type *) PORT0_BASE)
\r
1788 #define PORT1 ((PORT1_Type *) PORT1_BASE)
\r
1789 #define PORT2 ((PORT2_Type *) PORT2_BASE)
\r
1790 #define PORT3 ((PORT3_Type *) PORT3_BASE)
\r
1791 #define PORT4 ((PORT4_Type *) PORT4_BASE)
\r
1792 #define PORT5 ((PORT5_Type *) PORT5_BASE)
\r
1793 #define PORT6 ((PORT6_Type *) PORT6_BASE)
\r
1794 #define PORT14 ((PORT14_Type *) PORT14_BASE)
\r
1795 #define PORT15 ((PORT15_Type *) PORT15_BASE)
\r
1798 /***************************************************************************/
\r
1800 /***************************************************************************/
\r
1803 *Position Interface
\r
1806 __IO uint32_t PCONF; /*!<Architectural Overview configuration Offset 0x0000*/
\r
1807 __IO uint32_t PSUS; /*!<Architectural Overview Suspend Config Offset 0x0004*/
\r
1808 __O uint32_t PRUNS; /*!<Architectural Overview Run Bit Set Offset 0x0008*/
\r
1809 __O uint32_t PRUNC; /*!<Architectural Overview Run Bit Clear Offset 0x000C*/
\r
1810 __I uint32_t PRUN; /*!<Architectural Overview Run Bit Status Offset 0x0010*/
\r
1811 __I uint32_t RESERVED1[3];
\r
1812 __I uint32_t MIDR; /*!<Module Identification register Offset 0x0020*/
\r
1813 __I uint32_t RESERVED2[3];
\r
1814 __I uint32_t HALP; /*!<Hall Sensor Patterns Offset 0x0030*/
\r
1815 __IO uint32_t HALPS; /*!<Hall Sensor Shadow Patterns Offset 0x0034*/
\r
1816 __I uint32_t RESERVED3[2];
\r
1817 __I uint32_t MCM; /*!<Multi Channel Pattern Offset 0x0040*/
\r
1818 __IO uint32_t MCSM; /*!<Multi Channel Shadow Pattern Offset 0x0044*/
\r
1819 __O uint32_t MCMS; /*!<Multi Channel Pattern Control set Offset 0x0048*/
\r
1820 __O uint32_t MCMC; /*!<Multi Channel Pattern Control clear Offset 0x004C*/
\r
1821 __I uint32_t MCMF; /*!<Multi Channel Pattern Control flag Offset 0x0050*/
\r
1822 __I uint32_t RESERVED4[3];
\r
1823 __IO uint32_t QDC; /*!<Quadrature Decoder Control Offset 0x0060*/
\r
1824 __I uint32_t RESERVED5[3];
\r
1825 __I uint32_t PFLG; /*!<Architectural Overview Interrupt Flags Offset 0x0070*/
\r
1826 __IO uint32_t PFLGE; /*!<Architectural Overview Interrupt Enable Offset 0x0074*/
\r
1827 __O uint32_t SPFLG; /*!<Architectural Overview Interrupt Set Offset 0x0078*/
\r
1828 __O uint32_t RPFLG; /*!<Architectural Overview Interrupt Clear Offset 0x007C*/
\r
1829 }POSIF_GLOBAL_TypeDef;
\r
1831 #define POSIF0_BASE ((uint32_t)0x40028000U)
\r
1832 #define POSIF1_BASE ((uint32_t)0x4002C000U)
\r
1833 #define POSIF_GLOBAL_BASE (0x0000U)
\r
1834 /***************************************************************************/
\r
1835 /* Peripheral Declaration */
\r
1836 /***************************************************************************/
\r
1837 #define POSIF0 ((POSIF_GLOBAL_TypeDef*)(POSIF0_BASE + POSIF_GLOBAL_BASE))
\r
1838 #define POSIF1 ((POSIF_GLOBAL_TypeDef*)(POSIF1_BASE + POSIF_GLOBAL_BASE))
\r
1840 // ------------------------------------------------------------------------------------------------
\r
1841 // ----- PPB -----
\r
1842 // ------------------------------------------------------------------------------------------------
\r
1846 * @brief Cortex-M4 Private Peripheral Block (PPB)
\r
1849 typedef struct { /*!< (@ 0xE000E000) PPB Structure */
\r
1850 __I uint32_t RESERVED0[2];
\r
1851 __IO uint32_t ACTLR; /*!< (@ 0xE000E008) Auxiliary Control Register */
\r
1852 __I uint32_t RESERVED1;
\r
1853 __IO uint32_t SYST_CSR; /*!< (@ 0xE000E010) SysTick Control and Status Register */
\r
1854 __IO uint32_t SYST_RVR; /*!< (@ 0xE000E014) SysTick Reload Value Register */
\r
1855 __IO uint32_t SYST_CVR; /*!< (@ 0xE000E018) SysTick Current Value Register */
\r
1856 __IO uint32_t SYST_CALIB; /*!< (@ 0xE000E01C) SysTick Calibration Value Register r */
\r
1857 __I uint32_t RESERVED2[56];
\r
1858 __IO uint32_t NVIC_ISER0; /*!< (@ 0xE000E100) Interrupt Set-enable Register 0 */
\r
1859 __IO uint32_t NVIC_ISER1; /*!< (@ 0xE000E104) Interrupt Set-enable Register 1 */
\r
1860 __IO uint32_t NVIC_ISER2; /*!< (@ 0xE000E108) Interrupt Set-enable Register 2 */
\r
1861 __IO uint32_t NVIC_ISER3; /*!< (@ 0xE000E10C) Interrupt Set-enable Register 3 */
\r
1862 __I uint32_t RESERVED3[28];
\r
1863 __IO uint32_t NVIC_ISCER0; /*!< (@ 0xE000E180) Interrupt Clear-enable Register 0 */
\r
1864 __IO uint32_t NVIC_ISCER1; /*!< (@ 0xE000E184) Interrupt Clear-enable Register 1 */
\r
1865 __IO uint32_t NVIC_ISCER2; /*!< (@ 0xE000E188) Interrupt Clear-enable Register 2 */
\r
1866 __IO uint32_t NVIC_ISCER3; /*!< (@ 0xE000E18C) Interrupt Clear-enable Register 3 */
\r
1867 __I uint32_t RESERVED4[28];
\r
1868 __IO uint32_t NVIC_ISSPR0; /*!< (@ 0xE000E200) Interrupt Set-pending Register 0 */
\r
1869 __IO uint32_t NVIC_ISSPR1; /*!< (@ 0xE000E204) Interrupt Set-pending Register 1 */
\r
1870 __IO uint32_t NVIC_ISSPR2; /*!< (@ 0xE000E208) Interrupt Set-pending Register 2 */
\r
1871 __IO uint32_t NVIC_ISSPR3; /*!< (@ 0xE000E20C) Interrupt Set-pending Register 3 */
\r
1872 __I uint32_t RESERVED5[28];
\r
1873 __IO uint32_t NVIC_ICPR0; /*!< (@ 0xE000E280) Interrupt Clear-pending Register 0 */
\r
1874 __IO uint32_t NVIC_ICPR1; /*!< (@ 0xE000E284) Interrupt Clear-pending Register 1 */
\r
1875 __IO uint32_t NVIC_ICPR2; /*!< (@ 0xE000E288) Interrupt Clear-pending Register 2 */
\r
1876 __IO uint32_t NVIC_ICPR3; /*!< (@ 0xE000E28C) Interrupt Clear-pending Register 3 */
\r
1877 __I uint32_t RESERVED6[28];
\r
1878 __IO uint32_t NVIC_IABR0; /*!< (@ 0xE000E300) Interrupt Active Bit Register 0 */
\r
1879 __IO uint32_t NVIC_IABR1; /*!< (@ 0xE000E304) Interrupt Active Bit Register 1 */
\r
1880 __IO uint32_t NVIC_IABR2; /*!< (@ 0xE000E308) Interrupt Active Bit Register 2 */
\r
1881 __IO uint32_t NVIC_IABR3; /*!< (@ 0xE000E30C) Interrupt Active Bit Register 3 */
\r
1882 __I uint32_t RESERVED7[60];
\r
1883 __IO uint32_t NVIC_IPR0; /*!< (@ 0xE000E400) Interrupt Priority Register 0 */
\r
1884 __IO uint32_t NVIC_IPR1; /*!< (@ 0xE000E404) Interrupt Priority Register 1 */
\r
1885 __IO uint32_t NVIC_IPR2; /*!< (@ 0xE000E408) Interrupt Priority Register 2 */
\r
1886 __IO uint32_t NVIC_IPR3; /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */
\r
1887 __IO uint32_t NVIC_IPR4; /*!< (@ 0xE000E410) Interrupt Priority Register 4 */
\r
1888 __IO uint32_t NVIC_IPR5; /*!< (@ 0xE000E414) Interrupt Priority Register 5 */
\r
1889 __IO uint32_t NVIC_IPR6; /*!< (@ 0xE000E418) Interrupt Priority Register 6 */
\r
1890 __IO uint32_t NVIC_IPR7; /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */
\r
1891 __IO uint32_t NVIC_IPR8; /*!< (@ 0xE000E420) Interrupt Priority Register 8 */
\r
1892 __IO uint32_t NVIC_IPR9; /*!< (@ 0xE000E424) Interrupt Priority Register 9 */
\r
1893 __IO uint32_t NVIC_IPR10; /*!< (@ 0xE000E428) Interrupt Priority Register 10 */
\r
1894 __IO uint32_t NVIC_IPR11; /*!< (@ 0xE000E42C) Interrupt Priority Register 11 */
\r
1895 __IO uint32_t NVIC_IPR12; /*!< (@ 0xE000E430) Interrupt Priority Register 12 */
\r
1896 __IO uint32_t NVIC_IPR13; /*!< (@ 0xE000E434) Interrupt Priority Register 13 */
\r
1897 __IO uint32_t NVIC_IPR14; /*!< (@ 0xE000E438) Interrupt Priority Register 14 */
\r
1898 __IO uint32_t NVIC_IPR15; /*!< (@ 0xE000E43C) Interrupt Priority Register 15 */
\r
1899 __IO uint32_t NVIC_IPR16; /*!< (@ 0xE000E440) Interrupt Priority Register 16 */
\r
1900 __IO uint32_t NVIC_IPR17; /*!< (@ 0xE000E444) Interrupt Priority Register 17 */
\r
1901 __IO uint32_t NVIC_IPR18; /*!< (@ 0xE000E448) Interrupt Priority Register 18 */
\r
1902 __IO uint32_t NVIC_IPR19; /*!< (@ 0xE000E44C) Interrupt Priority Register 19 */
\r
1903 __IO uint32_t NVIC_IPR20; /*!< (@ 0xE000E450) Interrupt Priority Register 20 */
\r
1904 __IO uint32_t NVIC_IPR21; /*!< (@ 0xE000E454) Interrupt Priority Register 21 */
\r
1905 __IO uint32_t NVIC_IPR22; /*!< (@ 0xE000E458) Interrupt Priority Register 22 */
\r
1906 __IO uint32_t NVIC_IPR23; /*!< (@ 0xE000E45C) Interrupt Priority Register 23 */
\r
1907 __IO uint32_t NVIC_IPR24; /*!< (@ 0xE000E460) Interrupt Priority Register 24 */
\r
1908 __IO uint32_t NVIC_IPR25; /*!< (@ 0xE000E464) Interrupt Priority Register 25 */
\r
1909 __IO uint32_t NVIC_IPR26; /*!< (@ 0xE000E468) Interrupt Priority Register 26 */
\r
1910 __IO uint32_t NVIC_IPR27; /*!< (@ 0xE000E46C) Interrupt Priority Register 27 */
\r
1911 __I uint32_t RESERVED8[548];
\r
1912 __I uint32_t CPUID; /*!< (@ 0xE000ED00) CPUID Base Register */
\r
1913 __IO uint32_t ICSR; /*!< (@ 0xE000ED04) Interrupt Control and State Register */
\r
1914 __IO uint32_t VTOR; /*!< (@ 0xE000ED08) Vector Table Offset Register */
\r
1915 __IO uint32_t AIRCR; /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */
\r
1916 __IO uint32_t SCR; /*!< (@ 0xE000ED10) System Control Register */
\r
1917 __IO uint32_t CCR; /*!< (@ 0xE000ED14) Configuration and Control Register */
\r
1918 __IO uint32_t SHPR1; /*!< (@ 0xE000ED18) System Handler Priority Register 1 */
\r
1919 __IO uint32_t SHPR2; /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */
\r
1920 __IO uint32_t SHPR3; /*!< (@ 0xE000ED20) System Handler Priority Register 3 */
\r
1921 __IO uint32_t SHCSR; /*!< (@ 0xE000ED24) System Handler Control and State Register */
\r
1922 __IO uint32_t CFSR; /*!< (@ 0xE000ED28) Configurable Fault Status Register */
\r
1923 __IO uint32_t HFSR; /*!< (@ 0xE000ED2C) HardFault Status Register */
\r
1924 __I uint32_t RESERVED9;
\r
1925 __IO uint32_t MMFAR; /*!< (@ 0xE000ED34) MemManage Fault Address Register */
\r
1926 __IO uint32_t BFAR; /*!< (@ 0xE000ED38) BusFault Address Register */
\r
1927 __IO uint32_t AFSR; /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register */
\r
1928 __I uint32_t RESERVED10[18];
\r
1929 __IO uint32_t CPACR; /*!< (@ 0xE000ED88) Coprocessor Access Control Register */
\r
1930 __I uint32_t RESERVED11;
\r
1931 __I uint32_t MPU_TYPE; /*!< (@ 0xE000ED90) MPU Type Register */
\r
1932 __IO uint32_t MPU_CTRL; /*!< (@ 0xE000ED94) MPU Control Register */
\r
1933 __IO uint32_t MPU_RNR; /*!< (@ 0xE000ED98) MPU Region Number Register */
\r
1934 __IO uint32_t MPU_RBAR; /*!< (@ 0xE000ED9C) MPU Region Base Address Register */
\r
1935 __IO uint32_t MPU_RASR; /*!< (@ 0xE000EDA0) MPU Region Attribute and Size Register */
\r
1936 __IO uint32_t MPU_RBAR_A1; /*!< (@ 0xE000EDA4) MPU Region Base Address Register A1 */
\r
1937 __IO uint32_t MPU_RASR_A1; /*!< (@ 0xE000EDA8) MPU Region Attribute and Size Register A1 */
\r
1938 __IO uint32_t MPU_RBAR_A2; /*!< (@ 0xE000EDAC) MPU Region Base Address Register A2 */
\r
1939 __IO uint32_t MPU_RASR_A2; /*!< (@ 0xE000EDB0) MPU Region Attribute and Size Register A2 */
\r
1940 __IO uint32_t MPU_RBAR_A3; /*!< (@ 0xE000EDB4) MPU Region Base Address Register A3 */
\r
1941 __IO uint32_t MPU_RASR_A3; /*!< (@ 0xE000EDB8) MPU Region Attribute and Size Register A3 */
\r
1942 __I uint32_t RESERVED12[81];
\r
1943 __O uint32_t STIR; /*!< (@ 0xE000EF00) Software Trigger Interrupt Register */
\r
1944 __I uint32_t RESERVED13[12];
\r
1945 __IO uint32_t FPCCR; /*!< (@ 0xE000EF34) Floating-point Context Control Register */
\r
1946 __IO uint32_t FPCAR; /*!< (@ 0xE000EF38) Floating-point Context Address Register */
\r
1947 __IO uint32_t FPDSCR; /*!< (@ 0xE000EF3C) Floating-point Default Status Control Register */
\r
1950 #define PPB_BASE 0xE000E000
\r
1951 #define PPB ((PPB_Type *) PPB_BASE)
\r
1954 /***************************************************************************/
\r
1956 /***************************************************************************/
\r
1962 __IO uint32_t PCON; /*!<Prefetch Configuration Register Offset 0x0000*/
\r
1963 }PREF_GLOBAL_TypeDef;
\r
1965 #define PREF_BASE ((uint32_t)0x58004000U)
\r
1966 #define PREF_GLOBAL_BASE (0x0000U)
\r
1967 /***************************************************************************/
\r
1968 /* Peripheral Declaration */
\r
1969 /***************************************************************************/
\r
1970 #define PREF ((PREF_GLOBAL_TypeDef*)(PREF_BASE + PREF_GLOBAL_BASE))
\r
1972 /***************************************************************************/
\r
1974 /***************************************************************************/
\r
1977 *RTC Kernel registers
\r
1980 __I uint32_t ID; /*!<RTC ID Register Offset 0x0000*/
\r
1981 __IO uint32_t CTR; /*!<RTC Control Register Offset 0x0004*/
\r
1982 __I uint32_t RAWSTAT; /*!<RTC Raw Service Request Register Offset 0x0008*/
\r
1983 __I uint32_t STSSR; /*!<RTC Service Request Status Register Offset 0x000C*/
\r
1984 __IO uint32_t MSKSR; /*!<RTC Service Request Mask Register Offset 0x0010*/
\r
1985 __O uint32_t CLRSR; /*!<RTC Clear Service Request Register Offset 0x0014*/
\r
1986 __IO uint32_t ATIM0; /*!<RTC Alarm Time Register 0 Offset 0x0018*/
\r
1987 __IO uint32_t ATIM1; /*!<RTC Alarm Time Register 1 Offset 0x001C*/
\r
1988 __IO uint32_t TIM0; /*!<RTC Time Register 0 Offset 0x0020*/
\r
1989 __IO uint32_t TIM1; /*!<RTC Time Register 1 Offset 0x0024*/
\r
1990 }RTC_GLOBAL_TypeDef;
\r
1992 #define RTC_BASE ((uint32_t)0x50004A00U)
\r
1993 #define RTC_GLOBAL_BASE (0x0000U)
\r
1994 /***************************************************************************/
\r
1995 /* Peripheral Declaration */
\r
1996 /***************************************************************************/
\r
1997 #define RTC ((RTC_GLOBAL_TypeDef*)(RTC_BASE + RTC_GLOBAL_BASE))
\r
1999 /***************************************************************************/
\r
2001 /***************************************************************************/
\r
2004 *SCU CCU PLL registers
\r
2007 __I uint32_t PLLSTAT; /*!<PLL Status Register Offset 0x0710*/
\r
2008 __IO uint32_t PLLCON0; /*!<PLL Configuration 0 Register Offset 0x0714*/
\r
2009 __IO uint32_t PLLCON1; /*!<PLL Configuration 1 Register Offset 0x0718*/
\r
2010 __IO uint32_t PLLCON2; /*!<PLL Configuration 2 Register Offset 0x071C*/
\r
2011 __I uint32_t USBPLLSTAT; /*!<USB PLL Status Register Offset 0x0720*/
\r
2012 __IO uint32_t USBPLLCON; /*!<USB PLL Configuration Register Offset 0x0724*/
\r
2013 __I uint32_t RESERVED1[4];
\r
2014 __I uint32_t CLKMXSTAT; /*!<Clock Multiplexing Status Register Offset 0x0738*/
\r
2018 *SCU CCU OSC registers
\r
2021 __I uint32_t OSCHPSTAT; /*!<OSC_HP Status Register Offset 0x0700*/
\r
2022 __IO uint32_t OSCHPCTRL; /*!<OSC_HP Control Register Offset 0x0704*/
\r
2026 *SCU CCU Clock Control registers
\r
2029 __I uint32_t CLKSTAT; /*!<Clock Status Register Offset 0x0600*/
\r
2030 __O uint32_t CLKSET; /*!<CLK Set Register Offset 0x0604*/
\r
2031 __O uint32_t CLKCLR; /*!<CLK Clear Register Offset 0x0608*/
\r
2032 __IO uint32_t SYSCLKCR; /*!<System Clock Control Register Offset 0x060C*/
\r
2033 __IO uint32_t CPUCLKCR; /*!<CPU Clock Control Register Offset 0x0610*/
\r
2034 __IO uint32_t PBCLKCR; /*!<Peripheral Bus Clock Control Register Offset 0x0614*/
\r
2035 __IO uint32_t USBCLKCR; /*!<USB Clock Control Register Offset 0x0618*/
\r
2036 __IO uint32_t EBUCLKCR; /*!<EBU Clock Control Register Offset 0x061C*/
\r
2037 __IO uint32_t CCUCLKCR; /*!<CCU Clock Control Register Offset 0x0620*/
\r
2038 __IO uint32_t WDTCLKCR; /*!<WDT Clock Control Register Offset 0x0624*/
\r
2039 __IO uint32_t EXTCLKCR; /*!<External Clock Control Offset 0x0628*/
\r
2040 __I uint32_t RESERVED1;
\r
2041 __IO uint32_t SLEEPCR; /*!<Sleep Control Register Offset 0x0630*/
\r
2042 __IO uint32_t DSLEEPCR; /*!<Deep Sleep Control Register Offset 0x0634*/
\r
2045 #define SCU_BASE ((uint32_t)0x50004000U)
\r
2046 #define SCU_PLL_BASE (0x0710U)
\r
2047 #define SCU_OSC_BASE (0x0700U)
\r
2048 #define SCU_CLK_BASE (0x0600U)
\r
2049 /***************************************************************************/
\r
2050 /* Peripheral Declaration */
\r
2051 /***************************************************************************/
\r
2052 #define SCU_PLL ((SCU_PLL_TypeDef*)(SCU_BASE + SCU_PLL_BASE))
\r
2053 #define SCU_OSC ((SCU_OSC_TypeDef*)(SCU_BASE + SCU_OSC_BASE))
\r
2054 #define SCU_CLK ((SCU_CLK_TypeDef*)(SCU_BASE + SCU_CLK_BASE))
\r
2056 /***************************************************************************/
\r
2058 /***************************************************************************/
\r
2061 *SCU GCU CONTROL registers
\r
2064 __I uint32_t ID; /*!<SCU Module ID Register Offset 0x0000*/
\r
2065 __I uint32_t IDCHIP; /*!<Chip ID Register Offset 0x0004*/
\r
2066 __I uint32_t IDMANUF; /*!<Manufactory ID Register Offset 0x0008*/
\r
2067 __I uint32_t RESERVED1;
\r
2068 __IO uint32_t STCON; /*!<Startup Configuration Register Offset 0x0010*/
\r
2069 __I uint32_t RESERVED2[6];
\r
2070 __IO uint32_t GPR[2]; /*!< General Purpose Register 0 Offset 0x002C*/
\r
2071 __I uint32_t RESERVED3[6];
\r
2072 __IO uint32_t CCUCON; /*!<CCU Control Register Offset 0x004C*/
\r
2073 __I uint32_t RESERVED4[15];
\r
2074 __IO uint32_t DTSCON; /*!<Die Temperature Sensor Control Register Offset 0x008C*/
\r
2075 __I uint32_t DTSSTAT; /*!<Die Temperature Sensor Status Register Offset 0x0090*/
\r
2076 __I uint32_t RESERVED5[2];
\r
2077 __IO uint32_t SDMMCDEL; /*!<SD-MMC Delay Control Register Offset 0x009C*/
\r
2078 __IO uint32_t GORCEN[2]; /*!<Out of Range Comparator Enable Register 0 Offset 0x00A0*/
\r
2079 __I uint32_t RESERVED6[7];
\r
2080 __I uint32_t MIRRSTS; /*!<Mirror Update Status Register Offset 0x00C4*/
\r
2081 __IO uint32_t RMACR; /*!<Retention Memory Access Control Register Offset 0x00C8*/
\r
2082 __IO uint32_t RMDATA; /*!<Retention Memory Access Data Register Offset 0x00CC*/
\r
2083 }SCU_GENERAL_TypeDef;
\r
2086 *SCU GCU PARITY registers
\r
2089 __IO uint32_t PEEN; /*!<Parity Error Enable Register Offset 0x013C*/
\r
2090 __IO uint32_t MCHKCON; /*!<Memory Checking Control Register Offset 0x0140*/
\r
2091 __IO uint32_t PETE; /*!<Parity Error Trap Enable Register Offset 0x0144*/
\r
2092 __IO uint32_t PERSTEN; /*!<Parity Error Reset Enable Register Offset 0x0148*/
\r
2093 __I uint32_t RESERVED1;
\r
2094 __IO uint32_t PEFLAG; /*!<Parity Error Flag Register Offset 0x0150*/
\r
2095 __IO uint32_t PMTPR; /*!<Parity Memory Test Pattern Register Offset 0x0154*/
\r
2096 __IO uint32_t PMTSR; /*!<Parity Memory Test Select Register Offset 0x0158*/
\r
2097 }SCU_PARITY_TypeDef;
\r
2100 *SCU GCU INTERRUPT registers
\r
2103 __I uint32_t SRSTAT; /*!<SCU Service Request Status Offset 0x0074*/
\r
2104 __I uint32_t SRRAW; /*!<SCU Raw Service Request Status Offset 0x0078*/
\r
2105 __IO uint32_t SRMSK; /*!<SCU Service Request Mask Offset 0x007C*/
\r
2106 __O uint32_t SRCLR; /*!<SCU Service Request Clear Offset 0x0080*/
\r
2107 __O uint32_t SRSET; /*!<SCU Service Request Set Offset 0x0084*/
\r
2108 __IO uint32_t NMIREQEN; /*!<SCU Service Request Mask Offset 0x0088*/
\r
2109 }SCU_INTERRUPT_TypeDef;
\r
2112 *SCU TRAP registers
\r
2115 __I uint32_t TRAPSTAT; /*!<Trap Status Register Offset 0x0160*/
\r
2116 __I uint32_t TRAPRAW; /*!<Trap Raw Status Register Offset 0x0164*/
\r
2117 __IO uint32_t TRAPDIS; /*!<Trap Disable Register Offset 0x0168*/
\r
2118 __O uint32_t TRAPCLR; /*!<Trap Clear Register Offset 0x016C*/
\r
2119 __O uint32_t TRAPSET; /*!<Trap Set Register Offset 0x0170*/
\r
2120 }SCU_TRAP_TypeDef;
\r
2122 #define SCU_BASE ((uint32_t)0x50004000U)
\r
2123 #define SCU_GENERAL_BASE (0x0000U)
\r
2124 #define SCU_PARITY_BASE (0x013CU)
\r
2125 #define SCU_INTERRUPT_BASE (0x0074U)
\r
2126 #define SCU_TRAP_BASE (0x0160U)
\r
2127 /***************************************************************************/
\r
2128 /* Peripheral Declaration */
\r
2129 /***************************************************************************/
\r
2130 #define SCU_GENERAL ((SCU_GENERAL_TypeDef*)(SCU_BASE + SCU_GENERAL_BASE))
\r
2131 #define SCU_PARITY ((SCU_PARITY_TypeDef*)(SCU_BASE + SCU_PARITY_BASE))
\r
2132 #define SCU_INTERRUPT ((SCU_INTERRUPT_TypeDef*)(SCU_BASE + SCU_INTERRUPT_BASE))
\r
2133 #define SCU_TRAP ((SCU_TRAP_TypeDef*)(SCU_BASE + SCU_TRAP_BASE))
\r
2135 /***************************************************************************/
\r
2137 /***************************************************************************/
\r
2140 *SCU HIBERNATE registers
\r
2143 __I uint32_t HDSTAT; /*!<Hibernate Domain Control & Status Register Offset 0x0300*/
\r
2144 __O uint32_t HDCLR; /*!<Hibernate Domain Status Clear Register Offset 0x0304*/
\r
2145 __O uint32_t HDSET; /*!<Hibernate Domain Status Set Register Offset 0x0308*/
\r
2146 __IO uint32_t HDCR; /*!<Hibernate Domain Configuration Register Offset 0x030C*/
\r
2147 __I uint32_t RESERVED1;
\r
2148 __IO uint32_t OSCSICTRL; /*!<OSC_SI Control Register Offset 0x0314*/
\r
2149 __I uint32_t OSCULSTAT; /*!<OSC_ULP Status Register Offset 0x0318*/
\r
2150 __IO uint32_t OSCULCTRL; /*!<OSC_ULP Control Register Offset 0x031C*/
\r
2151 }SCU_HIBERNATE_TypeDef;
\r
2153 #define SCU_BASE ((uint32_t)0x50004000U)
\r
2154 #define SCU_HIBERNATE_BASE (0x0300U)
\r
2155 /***************************************************************************/
\r
2156 /* Peripheral Declaration */
\r
2157 /***************************************************************************/
\r
2158 #define SCU_HIBERNATE ((SCU_HIBERNATE_TypeDef*)(SCU_BASE + SCU_HIBERNATE_BASE))
\r
2160 /***************************************************************************/
\r
2162 /***************************************************************************/
\r
2165 *SCU PWRCTRL registers
\r
2168 __I uint32_t PWRSTAT; /*!<PCU Status Register Offset 0x0200*/
\r
2169 __O uint32_t PWRSET; /*!<PCU Set Control Register Offset 0x0204*/
\r
2170 __O uint32_t PWRCLR; /*!<PCU Clear Control Register Offset 0x0208*/
\r
2171 __I uint32_t RESERVED1;
\r
2172 __I uint32_t EVRSTAT; /*!<EVR Status Register Offset 0x0210*/
\r
2173 __I uint32_t EVRVADCSTAT; /*!<EVR VADC Status Register Offset 0x0214*/
\r
2174 __I uint32_t RESERVED2[5];
\r
2175 __IO uint32_t PWRMON; /*!< Power Monitor Control Offset 0x022C*/
\r
2176 }SCU_POWER_TypeDef;
\r
2178 #define SCU_BASE ((uint32_t)0x50004000U)
\r
2179 #define SCU_POWER_BASE (0x0200U)
\r
2180 /***************************************************************************/
\r
2181 /* Peripheral Declaration */
\r
2182 /***************************************************************************/
\r
2183 #define SCU_POWER ((SCU_POWER_TypeDef*)(SCU_BASE + SCU_POWER_BASE))
\r
2185 /***************************************************************************/
\r
2187 /***************************************************************************/
\r
2190 *SCU RESET CONTROL registers
\r
2193 __I uint32_t RSTSTAT; /*!<RCU Reset Status Offset 0x0400*/
\r
2194 __O uint32_t RSTSET; /*!<RCU Reset Set Register Offset 0x0404*/
\r
2195 __O uint32_t RSTCLR; /*!<RCU Reset Clear Register Offset 0x0408*/
\r
2196 __I uint32_t PRSTAT0; /*!<RCU Peripheral 0 Reset Status Offset 0x040C*/
\r
2197 __O uint32_t PRSET0; /*!<RCU Peripheral 0 Reset Set Offset 0x0410*/
\r
2198 __O uint32_t PRCLR0; /*!<RCU Peripheral 0 Reset Clear Offset 0x0414*/
\r
2199 __I uint32_t PRSTAT1; /*!<RCU Peripheral 1 Reset Status Offset 0x0418*/
\r
2200 __O uint32_t PRSET1; /*!<RCU Peripheral 1 Reset Set Offset 0x041C*/
\r
2201 __O uint32_t PRCLR1; /*!<RCU Peripheral 1 Reset Clear Offset 0x0420*/
\r
2202 __I uint32_t PRSTAT2; /*!<RCU Peripheral 2 Reset Status Offset 0x0424*/
\r
2203 __O uint32_t PRSET2; /*!<RCU Peripheral 2 Reset Set Offset 0x0428*/
\r
2204 __O uint32_t PRCLR2; /*!<RCU Peripheral 2 Reset Clear Offset 0x042C*/
\r
2205 __I uint32_t PRSTAT3; /*!<RCU Peripheral 3 Reset Status Offset 0x0430*/
\r
2206 __O uint32_t PRSET3; /*!<RCU Peripheral 3 Reset Set Offset 0x0434*/
\r
2207 __O uint32_t PRCLR3; /*!<RCU Peripheral 3 Reset Clear Offset 0x0438*/
\r
2208 }SCU_RESET_TypeDef;
\r
2210 #define SCU_BASE ((uint32_t)0x50004000U)
\r
2211 #define SCU_RESET_BASE (0x0400U)
\r
2212 /***************************************************************************/
\r
2213 /* Peripheral Declaration */
\r
2214 /***************************************************************************/
\r
2215 #define SCU_RESET ((SCU_RESET_TypeDef*)(SCU_BASE + SCU_RESET_BASE))
\r
2217 /***************************************************************************/
\r
2219 /***************************************************************************/
\r
2225 __IO uint16_t BLOCK_SIZE; /*!<Block Size Register Offset 0x0004*/
\r
2226 __IO uint16_t BLOCK_COUNT; /*!<Block Count Register Offset 0x0006*/
\r
2227 __IO uint32_t ARGUMENT1; /*!<Argument1 Register Offset 0x0008*/
\r
2228 __IO uint16_t TRANSFER_MODE; /*!<Transfer Mode Register Offset 0x000C*/
\r
2229 __IO uint16_t COMMAND; /*!<Command Register Offset 0x000E*/
\r
2230 __I uint32_t RESPONSE0; /*!<Response 0 Register Offset 0x0010*/
\r
2231 __I uint32_t RESPONSE2; /*!<Response 2 Register Offset 0x0014*/
\r
2232 __I uint32_t RESPONSE4; /*!<Response 4 Register Offset 0x0018*/
\r
2233 __I uint32_t RESPONSE6; /*!<Response 6 Register Offset 0x001C*/
\r
2234 __IO uint32_t DATA_BUFFER; /*!<Data Buffer Register Offset 0x0020*/
\r
2235 __I uint32_t PRESENT_STATE; /*!<Present State Register Offset 0x0024*/
\r
2236 __IO uint8_t HOST_CTRL; /*!<Host Control Register Offset 0x0028*/
\r
2237 __IO uint8_t POWER_CTRL; /*!<Power Control Register Offset 0x0029*/
\r
2238 __IO uint8_t BLOCK_GAP_CTRL; /*!<Block Gap Control Register Offset 0x002A*/
\r
2239 __IO uint8_t WAKEUP_CTRL; /*!<Wake-up Control Register Offset 0x002B*/
\r
2240 __IO uint16_t CLOCK_CTRL; /*!<Clock Control Register Offset 0x002C*/
\r
2241 __IO uint8_t TIMEOUT_CTRL; /*!<Timeout Control Register Offset 0x002E*/
\r
2242 __IO uint8_t SW_RESET; /*!<Software Reset Register Offset 0x002F*/
\r
2243 __IO uint16_t INT_STATUS_NORM; /*!<Normal Interrupt Status Register Offset 0x0030*/
\r
2244 __IO uint16_t INT_STATUS_ERR; /*!<Error Interrupt Status Register Offset 0x0032*/
\r
2245 __IO uint16_t EN_INT_STATUS_NORM; /*!<Normal Interrupt Status Enable Register Offset 0x0034*/
\r
2246 __IO uint16_t EN_INT_STATUS_ERR; /*!<Error Interrupt Status Enable Register Offset 0x0036*/
\r
2247 __IO uint16_t EN_INT_SIGNAL_NORM; /*!<Normal Interrupt Signal Enable Register Offset 0x0038*/
\r
2248 __IO uint16_t EN_INT_SIGNAL_ERR; /*!<Error Interrupt Signal Enable Register Offset 0x003A*/
\r
2249 __I uint16_t ACMD_ERR_STATUS; /*!<Auto CMD Error Status Register Offset 0x003C*/
\r
2250 __I uint16_t RESERVED0;
\r
2251 __I uint32_t RESERVED1[4];
\r
2252 __O uint16_t FORCE_EVENT_ACMD_ERR_STATUS; /*!<Force Event Register for Auto CMD Error Status Offset 0x0050*/
\r
2253 __O uint16_t FORCE_EVENT_ERR_STATUS; /*!<Force Event Register for Error Interrupt Status Offset 0x0052*/
\r
2254 __I uint32_t RESERVED2;
\r
2255 __I uint32_t RESERVED3[7];
\r
2256 __O uint32_t DEBUG_SEL; /*!<Debug Selection Register Offset 0x0074*/
\r
2257 __I uint32_t RESERVED4[30];
\r
2258 __IO uint32_t SPI; /*!<SPI Interrupt Support Register Offset 0x00F0*/
\r
2259 __I uint32_t RESERVED5[2];
\r
2260 __I uint16_t SLOT_INT_STATUS; /*!<Slot Interrupt Status Register Offset 0x00FC*/
\r
2261 }SDMMC_GLOBAL_TypeDef;
\r
2263 #define SDMMC_BASE ((uint32_t)0x4801C000U)
\r
2264 #define SDMMC_GLOBAL_BASE (0x0004U)
\r
2265 /***************************************************************************/
\r
2266 /* Peripheral Declaration */
\r
2267 /***************************************************************************/
\r
2268 #define SDMMC ((SDMMC_GLOBAL_TypeDef*)(SDMMC_BASE + SDMMC_GLOBAL_BASE))
\r
2270 /***************************************************************************/
\r
2272 /***************************************************************************/
\r
2275 *Cortex M4 - Trace Port Interface Unit
\r
2277 typedef struct { /*!< TPIU Structure */
\r
2278 __I uint32_t TPIU_SSPSR; /*!< The TPIU_SSPSR characteristics are:Purpose Indicates the supported parallel trace port sizes.If TPIU_TYPE.PTINVALID is RAO, this register is UNK. For more information see TPIU Type register, TPIU_TYPE on page C1-902. */
\r
2279 __IO uint32_t TPIU_CSPSR; /*!< The TPIU_CSPSR characteristics are:Purpose Defines the width of the current parallel trace port.Usage constraints Has the same format as the TPIU_SSPSR, but: only one bit is set to 1, all others must be zero the effect of writing a value with more than one bit set to 1 is UNPREDICTABLE the effect of a write to an unsupported bit is UNPREDICTABLE.If TPIU_TYPE.PTINVALID is RAO, this register is UNK/SBZP. For more information see TPIU Type register, TPIU_TYPE on page C1-902.Attributes See Table C1-40 on page */
\r
2280 __I uint32_t RESERVED0[2];
\r
2281 __IO uint32_t TPIU_ACPR; /*!< The TPIU_ACPR characteristics are:Purpose Scales the baud rate of the asynchronous output. */
\r
2282 __I uint32_t RESERVED1[55];
\r
2283 __IO uint32_t TPIU_SPPR; /*!< The TPIU_SPPR characteristics are:Purpose Selects the protocol used for trace output.Usage constraints If a debugger changes the register value while the TPIU is transmitting data, the effect on the output stream is UNPREDICTABLE and the required recovery process is IMPLEMENTATION DEFINED. Bits [11:9] of the TPIU_TYPE register define the trace output protocols supported by the implementation, see TPIU Type register, TPIU_TYPE on page C1-902. The effect of selecting an unsupported mode is UNPREDICTABLE. */
\r
2284 __I uint32_t RESERVED2[131];
\r
2285 __I uint32_t TPIU_FFSR; /*!< The TPIU_FFSR characteristics are:Purpose Indicates the status of the TPIU formatter. */
\r
2286 __IO uint32_t TPIU_FFCR; /*!< The TPIU_FFCR characteristics are:Purpose Controls the TPIU formatter.When one of the two SWO modes is selected, bit [1] of TPIU_FFCR enables the formatter to be bypassed. If the formatter is bypassed, only the ITM and DWT trace source passes through.The TPIU accepts and discards data from the ETM. This function is can be used to connect a device containing an ETM to a trace capture device that is only able to capture SWO data.Enabling or disabling the formatter causes momentary data corruption.NoteIf TPIU */
\r
2287 __I uint32_t TPIU_FSCR; /*!< The global synchronization trigger is generated by the Program Counter (PC) Sampler block. This means that there is no synchronization counter in the TPIU */
\r
2288 __I uint32_t RESERVED3[759];
\r
2289 __I uint32_t TRIGGER; /*!< The TRIGGER characteristics are:Purpose Integration test of the TRIGGER input. */
\r
2290 __I uint32_t FIFO_Data0; /*!< The Integration ETM Data characteristics are:Purpose Trace data integration testing.Usage constraints You must set bit [1] of TPIU_ITCTRL to use this register. See Integration Mode Control, TPIU_ITCTRL on page 11-11. */
\r
2291 __I uint32_t ITATBCTR2; /*!< The ITATBCTR2 characteristics are:Purpose Integration test.Usage constraints You must set bit [0] of TPIU_ITCTRL to use this register. See Integration Mode Control, TPIU_ITCTRL on page 11-11. */
\r
2292 __I uint32_t RESERVED4;
\r
2293 __I uint32_t ITATBCTR0; /*!< The ITATBCTR0 characteristics are:Purpose Integration test. */
\r
2294 __I uint32_t FIFO_Data1; /*!< The Integration ITM Data characteristics are:Purpose Trace data integration testing.Usage constraints You must set bit [1] of TPIU_ITCTRL to use this register. See Integration Mode Control, TPIU_ITCTRL on page 11-11. */
\r
2295 __IO uint32_t ITCTRL; /*!< The TPIU_ITCTRL characteristics are:Purpose Specifies normal or integration mode for the TPIU. */
\r
2296 __I uint32_t RESERVED5[39];
\r
2297 __IO uint32_t CLAIMSET; /*!< This register forms one half of the Claim Tag value. This location enables individual bits to be set, write, and returns the number of bits that can be set, read.Read Each bit is considered separately:0 = this claim tag bit is not implemented1 = this claim tag bit is implemented.Write Each bit is considered separately:0 = no effect1 = set this bit in the claim tag. */
\r
2298 __IO uint32_t CLAIMCLR; /*!< This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read.The width (n) of this register can be determined from reading the Claim Tag Set Register.Read Current Claim Tag ValueWrite Each bit is considered separately:0 = no effect1 = clear this bit in the claim tag. */
\r
2299 __I uint32_t RESERVED6[8];
\r
2300 __I uint32_t DEVID; /*!< The TPIU_DEVID characteristics are:Purpose Indicates the functions provided by the TPIU for use in topology detection. */
\r
2301 __I uint32_t DEVTYPE; /*!< The Device Type Identifier Register is read-only. It provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information.The TPIU_DEVTYPE characteristics are:Purpose Indicates the type of functionality the component supports.Attributes The Device Type reads as 0x11 and indicates this device is a trace sink and specifically a TPIU */
\r
2302 __I uint32_t TPIUPID4; /*!< Peripheral identification register4 */
\r
2303 __I uint32_t TPIUPID5; /*!< Peripheral identification register5 */
\r
2304 __I uint32_t TPIUPID6; /*!< Peripheral identification register6 */
\r
2305 __I uint32_t TPIUPID7; /*!< Peripheral identification register7 */
\r
2306 __I uint32_t TPIUPID0; /*!< Peripheral identification register0 */
\r
2307 __I uint32_t TPIUPID1; /*!< Peripheral identification register1 */
\r
2308 __I uint32_t TPIUPID2; /*!< Peripheral identification register2 */
\r
2309 __I uint32_t TPIUPID3; /*!< Peripheral identification register3 */
\r
2310 __I uint32_t TPIUCID0; /*!< Component identification register0 */
\r
2311 __I uint32_t TPIUCID1; /*!< Component identification register1 */
\r
2312 __I uint32_t TPIUCID2; /*!< Component identification register2 */
\r
2313 __I uint32_t TPIUCID3; /*!< Component identification register3 */
\r
2316 #define TPIU_BASE ((uint32_t)0xE0040000U)
\r
2317 #define TPIU_GLOBAL_BASE (0x0000U)
\r
2318 /***************************************************************************/
\r
2319 /* Peripheral Declaration */
\r
2320 /***************************************************************************/
\r
2321 #define TPIU ((TPIU_Type *)(TPIU_BASE + TPIU_GLOBAL_BASE))
\r
2323 /***************************************************************************/
\r
2325 /***************************************************************************/
\r
2328 *CONTROL registers
\r
2331 __IO uint32_t GOTGCTL; /*!<Control and Status Register Offset 0x0000*/
\r
2332 __IO uint32_t GOTGINT; /*!<OTG Interrupt Register Offset 0x0004*/
\r
2333 __IO uint32_t GAHBCFG; /*!<AHB Configuration Register Offset 0x0008*/
\r
2334 __IO uint32_t GUSBCFG; /*!<USB Configuration Register Offset 0x000C*/
\r
2335 __IO uint32_t GRSTCTL; /*!<Reset Register Offset 0x0010*/
\r
2338 __IO uint32_t GINTSTS_HOSTMODE; /*!<Interrupt Register [Host Mode] Offset 0x0014*/
\r
2339 __IO uint32_t GINTSTS_DEVICEMODE; /*!<Interrupt Register [Device Mode] Offset 0x0014*/
\r
2343 __IO uint32_t GINTMSK_HOSTMODE; /*!<Interrupt Mask Register [Host Mode] Offset 0x0018*/
\r
2344 __IO uint32_t GINTMSK_DEVICEMODE; /*!<Interrupt Mask Register [Device Mode] Offset 0x0018*/
\r
2348 __I uint32_t GRXSTSR_HOSTMODE; /*!<Receive Status Debug Read Register [Host Mode] Offset 0x001C*/
\r
2349 __I uint32_t GRXSTSR_DEVICEMODE; /*!<Receive Status Debug Read Register [Device Mode] Offset 0x001C*/
\r
2353 __I uint32_t GRXSTSP_HOSTMODE; /*!<Receive Status Read and Pop Register [Host Mode] Offset 0x0020*/
\r
2354 __I uint32_t GRXSTSP_DEVICEMODE; /*!<Receive Status Read and Pop Register [Device Mode] Offset 0x0020*/
\r
2356 __IO uint32_t GRXFSIZ; /*!<Receive FIFO Size Register Offset 0x0024*/
\r
2359 __IO uint32_t GNPTXFSIZ_HOSTMODE; /*!<Non-Periodic Transmit FIFO Size Register [Host Mode] Offset 0x0028*/
\r
2360 __IO uint32_t GNPTXFSIZ_DEVICEMODE; /*!<Non-Periodic Transmit FIFO Size Register [Device Mode] Offset 0x0028*/
\r
2362 __I uint32_t GNPTXSTS; /*!<Non-Periodic Transmit FIFO/Queue Status Register Offset 0x002C*/
\r
2363 __I uint32_t RESERVED1[3];
\r
2364 __IO uint32_t GUID; /*!<User ID Register Offset 0x003C*/
\r
2365 __I uint32_t RESERVED2[7];
\r
2366 __IO uint32_t GDFIFOCFG; /*!<Global DFIFO Software Config Register Offset 0x005C*/
\r
2367 __I uint32_t RESERVED3[40];
\r
2368 __IO uint32_t HPTXFSIZ; /*!<Host Periodic Transmit FIFO Size Register Offset 0x0100*/
\r
2369 __IO uint32_t DIEPTXF1; /*!<Device IN Endpoint Transmit FIFO Size Register Offset 0x0104*/
\r
2370 __IO uint32_t DIEPTXF2; /*!<Device IN Endpoint Transmit FIFO Size Register Offset 0x0108*/
\r
2371 __IO uint32_t DIEPTXF3; /*!<Device IN Endpoint Transmit FIFO Size Register Offset 0x010C*/
\r
2372 __IO uint32_t DIEPTXF4; /*!<Device IN Endpoint Transmit FIFO Size Register Offset 0x0110*/
\r
2373 __IO uint32_t DIEPTXF5; /*!<Device IN Endpoint Transmit FIFO Size Register Offset 0x0114*/
\r
2374 __IO uint32_t DIEPTXF6; /*!<Device IN Endpoint Transmit FIFO Size Register Offset 0x0118*/
\r
2375 __I uint32_t RESERVED4[185];
\r
2376 __IO uint32_t HCFG; /*!<Host Configuration Register Offset 0x0400*/
\r
2377 __IO uint32_t HFIR; /*!<Host Frame Interval Register Offset 0x0404*/
\r
2378 __IO uint32_t HFNUM; /*!<Host Frame Number/Frame Time Remaining Register Offset 0x0408*/
\r
2379 __I uint32_t RESERVED5;
\r
2380 __IO uint32_t HPTXSTS; /*!<Host Periodic Transmit FIFO/ Queue Status Register Offset 0x0410*/
\r
2381 __I uint32_t HAINT; /*!<Host All Channels Interrupt Register Offset 0x0414*/
\r
2382 __IO uint32_t HAINTMSK; /*!<Host All Channels Interrupt Mask Register Offset 0x0418*/
\r
2383 __IO uint32_t HFLBADDR; /*!<Host Frame List Base Address Register Offset 0x041C*/
\r
2384 __I uint32_t RESERVED6[8];
\r
2385 __IO uint32_t HPRT; /*!<Host Port Control and Status Register Offset 0x0440*/
\r
2386 __I uint32_t RESERVED7[239];
\r
2387 __IO uint32_t DCFG; /*!<Device Configuration Register Offset 0x0800*/
\r
2388 __IO uint32_t DCTL; /*!<Device Control Register Offset 0x0804*/
\r
2389 __I uint32_t DSTS; /*!<Device Status Register Offset 0x0808*/
\r
2390 __I uint32_t RESERVED8;
\r
2391 __IO uint32_t DIEPMSK; /*!<Device IN Endpoint Common Interrupt Mask Register Offset 0x0810*/
\r
2392 __IO uint32_t DOEPMSK; /*!<Device OUT Endpoint Common Interrupt Mask Register Offset 0x0814*/
\r
2393 __I uint32_t DAINT; /*!<Device All Endpoints Interrupt Register Offset 0x0818*/
\r
2394 __IO uint32_t DAINTMSK; /*!<Device All Endpoints Interrupt Mask Register Offset 0x081C*/
\r
2395 __I uint32_t RESERVED9[2];
\r
2396 __IO uint32_t DVBUSDIS; /*!<Device VBUS Discharge Time Register Offset 0x0828*/
\r
2397 __IO uint32_t DVBUSPULSE; /*!<Device VBUS Pulsing Time Register Offset 0x082C*/
\r
2398 __I uint32_t RESERVED10;
\r
2399 __IO uint32_t DIEPEMPMSK; /*!<Device IN Endpoint FIFO Empty Interrupt Mask Register Offset 0x0834*/
\r
2400 __I uint32_t RESERVED11[370];
\r
2401 __IO uint32_t PCGCCTL; /*!<Power and Clock Gating Control Register Offset 0x0E00*/
\r
2402 }USB0_GLOBAL_TypeDef;
\r
2405 *ENDPOINT-0 registers
\r
2408 __IO uint32_t DIEPCTL0; /*!<Device Control IN Endpoint 0 Control Register Offset 0x0900*/
\r
2409 __I uint32_t RESERVED1;
\r
2410 __IO uint32_t DIEPINT0; /*!<Device Endpoint-0 Interrupt Register Offset 0x0908*/
\r
2411 __I uint32_t RESERVED2;
\r
2412 __IO uint32_t DIEPTSIZ0; /*!<Device IN Endpoint 0 Transfer Size Register Offset 0x0910*/
\r
2413 __IO uint32_t DIEPDMA0; /*!<Device Endpoint-0 DMA Address Register Offset 0x0914*/
\r
2414 __I uint32_t DTXFSTS0; /*!<Device IN Endpoint Transmit FIFO Status Register Offset 0x0918*/
\r
2415 __I uint32_t DIEPDMAB0; /*!<Device Endpoint-0 DMA Buffer Address Register Offset 0x091C*/
\r
2416 __I uint32_t RESERVED3[120];
\r
2417 __IO uint32_t DOEPCTL0; /*!<Device Control OUT Endpoint 0 Control Register Offset 0x0B00*/
\r
2418 __I uint32_t RESERVED4;
\r
2419 __IO uint32_t DOEPINT0; /*!<Device Endpoint-0 Interrupt Register Offset 0x0B08*/
\r
2420 __I uint32_t RESERVED5;
\r
2421 __IO uint32_t DOEPTSIZ0; /*!<Device OUT Endpoint 0 Transfer Size Register Offset 0x0B10*/
\r
2422 __IO uint32_t DOEPDMA0; /*!<Device Endpoint-0 DMA Address Register Offset 0x0B14*/
\r
2423 __I uint32_t RESERVED6;
\r
2424 __I uint32_t DOEPDMAB0; /*!<Device Endpoint-0 DMA Buffer Address Register Offset 0x0B1C*/
\r
2425 }USB0_EP0_TypeDef;
\r
2428 *ENDPOINTx registers
\r
2433 __IO uint32_t DIEPCTL_INTBULK; /*!<Device Endpoint-1 Control Register [Interrupt/Bulk Endpoint] Offset 0x0920*/
\r
2434 __IO uint32_t DIEPCTL_ISOCONT; /*!<Device Endpoint-1 Control Register [Isochronous/Control Endpoint] Offset 0x0920*/
\r
2436 __I uint32_t RESERVED1;
\r
2437 __IO uint32_t DIEPINT; /*!<Device Endpoint-1 Interrupt Register Offset 0x0928*/
\r
2438 __I uint32_t RESERVED2;
\r
2439 __IO uint32_t DIEPTSIZ; /*!<Device Endpoint-1 Transfer Size Register Offset 0x0930*/
\r
2440 __IO uint32_t DIEPDMA; /*!<Device Endpoint-1 DMA Address Register Offset 0x0934*/
\r
2441 __I uint32_t DTXFSTS; /*!<Device IN Endpoint Transmit FIFO Status Register Offset 0x0938*/
\r
2442 __I uint32_t DIEPDMAB; /*!<Device Endpoint-1 DMA Buffer Address Register Offset 0x093C*/
\r
2443 __I uint32_t RESERVED3[120];
\r
2446 __IO uint32_t DOEPCTL_INTBULK; /*!<Device Endpoint-1 Control Register [Interrupt/Bulk Endpoint] Offset 0x0B20*/
\r
2447 __IO uint32_t DOEPCTL_ISOCONT; /*!<Device Endpoint-1 Control Register [Isochronous/Control Endpoint] Offset 0x0B20*/
\r
2449 __I uint32_t RESERVED4;
\r
2450 __IO uint32_t DOEPINT; /*!<Device Endpoint-1 Interrupt Register Offset 0x0B28*/
\r
2451 __I uint32_t RESERVED5;
\r
2454 __IO uint32_t DOEPTSIZ_ISO; /*!<Device Endpoint-1 Transfer Size Register [Isochronous OUT Endpoint] Offset 0x0B30*/
\r
2455 __IO uint32_t DOEPTSIZ_CONTROL; /*!<Device Endpoint-1 Transfer Size Register [Control OUT Endpoint] Offset 0x0B30*/
\r
2457 __IO uint32_t DOEPDMA; /*!<Device Endpoint-1 DMA Address Register Offset 0x0B34*/
\r
2458 __I uint32_t RESERVED6;
\r
2459 __I uint32_t DOEPDMAB; /*!<Device Endpoint-1 DMA Buffer Address Register Offset 0x0B3C*/
\r
2463 *CHANNEL registers
\r
2466 __IO uint32_t HCCHAR; /*!<Host Channel-0 Characteristics Register Offset 0x0500*/
\r
2467 __I uint32_t RESERVED1;
\r
2468 __IO uint32_t HCINT; /*!<Host Channel-0 Interrupt Register Offset 0x0508*/
\r
2469 __IO uint32_t HCINTMSK; /*!<Host Channel-0 Interrupt Mask Register Offset 0x050C*/
\r
2472 __IO uint32_t HCTSIZ_SCATGATHER; /*!<Host Channel-0 Transfer Size Register [Scatter/Gather DMA Mode] Offset 0x0510*/
\r
2473 __IO uint32_t HCTSIZ_BUFFERMODE; /*!<Host Channel-0 Transfer Size Register [Buffer DMA Mode] Offset 0x0510*/
\r
2477 __IO uint32_t HCDMA_SCATGATHER; /*!<Host Channel-0 DMA Address Register [Scatter/Gather DMA Mode] Offset 0x0514*/
\r
2478 __IO uint32_t HCDMA_BUFFERMODE; /*!<Host Channel-0 DMA Address Register [Buffer DMA Mode] Offset 0x0514*/
\r
2480 __I uint32_t RESERVED2;
\r
2481 __I uint32_t HCDMAB; /*!<Host Channel-0 DMA Buffer Address Register Offset 0x051C*/
\r
2484 #define USB0_BASE ((uint32_t)0x50040000U)
\r
2485 #define USB0_GLOBAL_BASE (0x0000U)
\r
2486 #define USB0_EP0_BASE (0x0900U)
\r
2487 #define USB0_EP1_BASE (0x0920U)
\r
2488 #define USB0_EP2_BASE (0x0940U)
\r
2489 #define USB0_EP3_BASE (0x0960U)
\r
2490 #define USB0_EP4_BASE (0x0980U)
\r
2491 #define USB0_EP5_BASE (0x09A0U)
\r
2492 #define USB0_EP6_BASE (0x09C0U)
\r
2493 #define USB0_CH0_BASE (0x0500U)
\r
2494 #define USB0_CH1_BASE (0x0520U)
\r
2495 #define USB0_CH2_BASE (0x0540U)
\r
2496 #define USB0_CH3_BASE (0x0560U)
\r
2497 #define USB0_CH4_BASE (0x0580U)
\r
2498 #define USB0_CH5_BASE (0x05A0U)
\r
2499 #define USB0_CH6_BASE (0x05C0U)
\r
2500 #define USB0_CH7_BASE (0x05E0U)
\r
2501 #define USB0_CH8_BASE (0x0600U)
\r
2502 #define USB0_CH9_BASE (0x0620U)
\r
2503 #define USB0_CH10_BASE (0x0640U)
\r
2504 #define USB0_CH11_BASE (0x0660U)
\r
2505 #define USB0_CH12_BASE (0x0680U)
\r
2506 #define USB0_CH13_BASE (0x06A0U)
\r
2507 /***************************************************************************/
\r
2508 /* Peripheral Declaration */
\r
2509 /***************************************************************************/
\r
2510 #define USB0 ((USB0_GLOBAL_TypeDef*)(USB0_BASE + USB0_GLOBAL_BASE))
\r
2511 #define USB0_EP0 ((USB0_EP0_TypeDef*)(USB0_BASE + USB0_EP0_BASE))
\r
2512 #define USB0_EP1 ((USB0_EP_TypeDef*)(USB0_BASE + USB0_EP1_BASE))
\r
2513 #define USB0_EP2 ((USB0_EP_TypeDef*)(USB0_BASE + USB0_EP2_BASE))
\r
2514 #define USB0_EP3 ((USB0_EP_TypeDef*)(USB0_BASE + USB0_EP3_BASE))
\r
2515 #define USB0_EP4 ((USB0_EP_TypeDef*)(USB0_BASE + USB0_EP4_BASE))
\r
2516 #define USB0_EP5 ((USB0_EP_TypeDef*)(USB0_BASE + USB0_EP5_BASE))
\r
2517 #define USB0_EP6 ((USB0_EP_TypeDef*)(USB0_BASE + USB0_EP6_BASE))
\r
2518 #define USB0_CH0 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH0_BASE))
\r
2519 #define USB0_CH1 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH1_BASE))
\r
2520 #define USB0_CH2 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH2_BASE))
\r
2521 #define USB0_CH3 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH3_BASE))
\r
2522 #define USB0_CH4 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH4_BASE))
\r
2523 #define USB0_CH5 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH5_BASE))
\r
2524 #define USB0_CH6 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH6_BASE))
\r
2525 #define USB0_CH7 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH7_BASE))
\r
2526 #define USB0_CH8 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH8_BASE))
\r
2527 #define USB0_CH9 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH9_BASE))
\r
2528 #define USB0_CH10 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH10_BASE))
\r
2529 #define USB0_CH11 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH11_BASE))
\r
2530 #define USB0_CH12 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH12_BASE))
\r
2531 #define USB0_CH13 ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH13_BASE))
\r
2533 /***************************************************************************/
\r
2535 /***************************************************************************/
\r
2538 *Module wide registers
\r
2541 __I uint32_t RESERVED1[2];
\r
2542 __I uint32_t ID; /*!<Module Identification Register Offset 0x0008*/
\r
2543 }USIC_GLOBAL_TypeDef;
\r
2546 *Channel Related registers
\r
2549 __I uint32_t CCFG; /*!<Channel Configuration Register Offset 0x0004*/
\r
2550 __I uint32_t RESERVED1;
\r
2551 __IO uint16_t KSCFG; /*!<Kernel State Configuration Register Offset 0x000C*/
\r
2552 __I uint16_t RESERVED2;
\r
2553 __IO uint32_t FDR; /*!<Fractional Divider Register Offset 0x0010*/
\r
2554 __IO uint32_t BRG; /*!<Baud Rate Generator Register Offset 0x0014*/
\r
2555 __IO uint32_t INPR; /*!<Interrupt Node Pointer Register Offset 0x0018*/
\r
2556 __IO uint32_t DX0CR; /*!<Input Control Register 0 Offset 0x001C*/
\r
2557 __IO uint32_t DX1CR; /*!<Input Control Register 1 Offset 0x0020*/
\r
2558 __IO uint32_t DX2CR; /*!<Input Control Register 2 Offset 0x0024*/
\r
2559 __IO uint32_t DX3CR; /*!<Input Control Register 3 Offset 0x0028*/
\r
2560 __IO uint32_t DX4CR; /*!<Input Control Register 4 Offset 0x002C*/
\r
2561 __IO uint32_t DX5CR; /*!<Input Control Register 5 Offset 0x0030*/
\r
2562 __IO uint32_t SCTR; /*!<Shift Control Register Offset 0x0034*/
\r
2563 __IO uint32_t TCSR; /*!<Transmit Control/Status Register Offset 0x0038*/
\r
2566 __IO uint32_t PCR_ASCMode; /*!<Protocol Control Register [ASC Mode] Offset 0x003C*/
\r
2567 __IO uint32_t PCR_SSCMode; /*!<Protocol Control Register [SSC Mode] Offset 0x003C*/
\r
2568 __IO uint32_t PCR_IISMode; /*!<Protocol Control Register [IIS Mode] Offset 0x003C*/
\r
2569 __IO uint32_t PCR_IICMode; /*!<Protocol Control Register [IIC Mode] Offset 0x003C*/
\r
2571 __IO uint32_t CCR; /*!<Channel Control Register Offset 0x0040*/
\r
2572 __IO uint32_t CMTR; /*!<Capture Mode Timer Register Offset 0x0044*/
\r
2575 __IO uint32_t PSR_ASCMode; /*!<Protocol Status Register [ASC Mode] Offset 0x0048*/
\r
2576 __IO uint32_t PSR_SSCMode; /*!<Protocol Status Register [SSC Mode] Offset 0x0048*/
\r
2577 __IO uint32_t PSR_IISMode; /*!<Protocol Status Register [IIS Mode] Offset 0x0048*/
\r
2578 __IO uint32_t PSR_IICMode; /*!<Protocol Status Register [IIC Mode] Offset 0x0048*/
\r
2580 __O uint32_t PSCR; /*!<Protocol Status Clear Register Offset 0x004C*/
\r
2581 __I uint32_t RBUFSR; /*!<Receiver Buffer Status Register Offset 0x0050*/
\r
2582 __I uint32_t RBUF; /*!<Receiver Buffer Register Offset 0x0054*/
\r
2583 __I uint32_t RBUFD; /*!<Receiver Buffer Register for Debugger Offset 0x0058*/
\r
2584 __I uint32_t RBUF0; /*!<Receiver Buffer Register 0 Offset 0x005C*/
\r
2585 __I uint32_t RBUF1; /*!<Receiver Buffer Register 1 Offset 0x0060*/
\r
2586 __I uint32_t RBUF01SR; /*!<Receiver Buffer 01 Status Register Offset 0x0064*/
\r
2587 __O uint32_t FMR; /*!<Flag Modification Register Offset 0x0068*/
\r
2588 __I uint32_t RESERVED3[5];
\r
2589 __IO uint32_t TBUF[32]; /*!<Transmit Buffer Input Location 00 Offset 0x0080*/
\r
2590 __IO uint32_t BYP; /*!<Bypass Data Register Offset 0x0100*/
\r
2591 __IO uint32_t BYPCR; /*!<Bypass Control Register Offset 0x0104*/
\r
2592 __IO uint32_t TBCTR; /*!<Transmitter Buffer Control Register Offset 0x0108*/
\r
2593 __IO uint32_t RBCTR; /*!<Receiver Buffer Control Register Offset 0x010C*/
\r
2594 __I uint32_t TRBPTR; /*!<Transmit/Receive Buffer Pointer Register Offset 0x0110*/
\r
2595 __IO uint32_t TRBSR; /*!<Transmit/Receive Buffer Status Register Offset 0x0114*/
\r
2596 __O uint32_t TRBSCR; /*!<Transmit/Receive Buffer Status Clear Register Offset 0x0118*/
\r
2597 __I uint32_t OUTR; /*!<Receiver Buffer Output Register Offset 0x011C*/
\r
2598 __I uint32_t OUTDR; /*!<Receiver Buffer Output Register L for Debugger Offset 0x0120*/
\r
2599 __I uint32_t RESERVED4[23];
\r
2600 __O uint32_t IN[32]; /*!<Transmit FIFO Buffer Input Location 00 Offset 0x0180*/
\r
2603 #define USIC0_BASE ((uint32_t)0x40030000U)
\r
2604 #define USIC1_BASE ((uint32_t)0x48020000U)
\r
2605 #define USIC2_BASE ((uint32_t)0x48024000U)
\r
2606 #define USIC_GLOBAL_BASE (0x0000U)
\r
2607 #define USIC0_CH0_BASE (0x0004U)
\r
2608 #define USIC0_CH1_BASE (0x0204U)
\r
2609 /***************************************************************************/
\r
2610 /* Peripheral Declaration */
\r
2611 /***************************************************************************/
\r
2612 #define USIC0 ((USIC_GLOBAL_TypeDef*)(USIC0_BASE + USIC_GLOBAL_BASE))
\r
2613 #define USIC0_CH0 ((USIC_CH_TypeDef*)(USIC0_BASE + USIC0_CH0_BASE))
\r
2614 #define USIC0_CH1 ((USIC_CH_TypeDef*)(USIC0_BASE + USIC0_CH1_BASE))
\r
2615 #define USIC1 ((USIC_GLOBAL_TypeDef*)(USIC1_BASE + USIC_GLOBAL_BASE))
\r
2616 #define USIC1_CH0 ((USIC_CH_TypeDef*)(USIC1_BASE + USIC0_CH0_BASE))
\r
2617 #define USIC1_CH1 ((USIC_CH_TypeDef*)(USIC1_BASE + USIC0_CH1_BASE))
\r
2618 #define USIC2 ((USIC_GLOBAL_TypeDef*)(USIC2_BASE + USIC_GLOBAL_BASE))
\r
2619 #define USIC2_CH0 ((USIC_CH_TypeDef*)(USIC2_BASE + USIC0_CH0_BASE))
\r
2620 #define USIC2_CH1 ((USIC_CH_TypeDef*)(USIC2_BASE + USIC0_CH1_BASE))
\r
2622 /***************************************************************************/
\r
2624 /***************************************************************************/
\r
2627 *ADC Group registers
\r
2630 __IO uint32_t ARBCFG; /*!<Arbitration Configuration Register, Group 0 Offset 0x0480*/
\r
2631 __IO uint32_t ARBPR; /*!<Arbitration Priority Register, Group 0 Offset 0x0484*/
\r
2632 __IO uint32_t CHASS; /*!<Channel Assignment Register, Group 0 Offset 0x0488*/
\r
2633 __I uint32_t RESERVED1[5];
\r
2634 __IO uint32_t ICLASS[2]; /*!<Input Class Register , Group 0 Offset 0x04A0*/
\r
2635 __I uint32_t RESERVED2[2];
\r
2636 __IO uint32_t ALIAS; /*!<Alias Register, Group 0 Offset 0x04B0*/
\r
2637 __I uint32_t RESERVED3;
\r
2638 __IO uint32_t BOUND; /*!<Boundary Select Register, Group 0 Offset 0x04B8*/
\r
2639 __I uint32_t RESERVED4;
\r
2640 __IO uint32_t SYNCTR; /*!<Synchronization Control Register, Group 0 Offset 0x04C0*/
\r
2641 __I uint32_t RESERVED5;
\r
2642 __IO uint32_t BFL; /*!<Boundary Flag Register, Group 0 Offset 0x04C8*/
\r
2643 __I uint32_t RESERVED6[13];
\r
2644 __IO uint32_t QCTRL0; /*!<Queue 0 Source Control Register, Group 0 Offset 0x0500*/
\r
2645 __IO uint32_t QMR0; /*!<Queue 0 Mode Register, Group 0 Offset 0x0504*/
\r
2646 __I uint32_t QSR0; /*!<Queue 0 Status Register, Group 0 Offset 0x0508*/
\r
2647 __I uint32_t Q0R0; /*!<Queue 0 Register 0, Group 0 Offset 0x050C*/
\r
2650 __I uint32_t QBUR0; /*!<Queue 0 Backup Register, Group 0 Offset 0x0510*/
\r
2651 __O uint32_t QINR0; /*!<Queue 0 Input Register, Group 0 Offset 0x0510*/
\r
2653 __I uint32_t RESERVED7[3];
\r
2654 __IO uint32_t ASCTRL; /*!<Autoscan Source Control Register, Group 0 Offset 0x0520*/
\r
2655 __IO uint32_t ASMR; /*!<Autoscan Source Mode Register, Group 0 Offset 0x0524*/
\r
2656 __IO uint32_t ASSEL; /*!<Autoscan Source Channel Select Register, Group 0 Offset 0x0528*/
\r
2657 __IO uint32_t ASPND; /*!<Autoscan Source Pending Register, Group 0 Offset 0x052C*/
\r
2658 __I uint32_t RESERVED8[20];
\r
2659 __IO uint32_t CEFLAG; /*!<Channel Event Flag Register, Group 0 Offset 0x0580*/
\r
2660 __IO uint32_t REFLAG; /*!<Result Event Flag Register, Group 0 Offset 0x0584*/
\r
2661 __IO uint32_t SEFLAG; /*!<Source Event Flag Register, Group 0 Offset 0x0588*/
\r
2662 __I uint32_t RESERVED9;
\r
2663 __O uint32_t CEFCLR; /*!<Channel Event Flag Clear Register, Group 0 Offset 0x0590*/
\r
2664 __O uint32_t REFCLR; /*!<Result Event Flag Clear Register, Group 0 Offset 0x0594*/
\r
2665 __O uint32_t SEFCLR; /*!<Source Event Flag Clear Register, Group 0 Offset 0x0598*/
\r
2666 __I uint32_t RESERVED10;
\r
2667 __IO uint32_t CEVNP0; /*!<Channel Event Node Pointer Register 0, Group 0 Offset 0x05A0*/
\r
2668 __I uint32_t RESERVED11[3];
\r
2669 __IO uint32_t REVNP0; /*!<Result Event Node Pointer Register 0, Group 0 Offset 0x05B0*/
\r
2670 __IO uint32_t REVNP1; /*!<Result Event Node Pointer Register 1, Group 0 Offset 0x05B4*/
\r
2671 __I uint32_t RESERVED12[2];
\r
2672 __IO uint32_t SEVNP; /*!<Source Event Node Pointer Register, Group 0 Offset 0x05C0*/
\r
2673 __I uint32_t RESERVED13;
\r
2674 __O uint32_t SRACT; /*!<Service Request Software Activation Trigger, Group 0 Offset 0x05C8*/
\r
2675 __I uint32_t RESERVED14[9];
\r
2676 __IO uint32_t EMUXCTR; /*!<E0ternal Multiplexer Control Register, Group x Offset 0x05F0*/
\r
2677 __I uint32_t RESERVED15;
\r
2678 __IO uint32_t VFR; /*!<Valid Flag Register, Group 0 Offset 0x05F8*/
\r
2679 __I uint32_t RESERVED16;
\r
2680 __IO uint32_t CHCTR[8]; /*!<Group 0, Channel 0 Ctrl. Reg. Offset 0x0600*/
\r
2681 __I uint32_t RESERVED17[24];
\r
2682 __IO uint32_t RCR[16]; /*!<Group 0 Result Control Reg. 0 Offset 0x0680*/
\r
2683 __I uint32_t RESERVED18[16];
\r
2684 __IO uint32_t RES[16]; /*!<Group 0 Result Register 0 Offset 0x0700*/
\r
2685 __I uint32_t RESERVED19[16];
\r
2686 __I uint32_t RESD[16]; /*!<Group 0 Result Reg. 0, Debug Offset 0x0780*/
\r
2690 *ADC global registers
\r
2693 __IO uint32_t CLC; /*!<Clock Control Register Offset 0x0000*/
\r
2694 __I uint32_t RESERVED1;
\r
2695 __I uint32_t ID; /*!<Module Identification Register Offset 0x0008*/
\r
2696 __I uint32_t RESERVED2[7];
\r
2697 __IO uint32_t OCS; /*!<OCDS Control and Status Register Offset 0x0028*/
\r
2698 __I uint32_t RESERVED3[21];
\r
2699 __IO uint32_t GLOBCFG; /*!<Global Configuration Register Offset 0x0080*/
\r
2700 __I uint32_t RESERVED4[7];
\r
2701 __IO uint32_t GLOBICLASS[2]; /*!<Input Class Register 0, Global Offset 0x00A0*/
\r
2702 __I uint32_t RESERVED5[4];
\r
2703 __IO uint32_t GLOBBOUND; /*!<Global Boundary Select Register Offset 0x00B8*/
\r
2704 __I uint32_t RESERVED6[9];
\r
2705 __IO uint32_t GLOBEFLAG; /*!<Global Event Flag Register Offset 0x00E0*/
\r
2706 __I uint32_t RESERVED7[23];
\r
2707 __IO uint32_t GLOBEVNP; /*!<Global Event Node Pointer Register Offset 0x0140*/
\r
2708 __I uint32_t RESERVED8[7];
\r
2709 __IO uint32_t GLOBTF; /*!<Global Test Functions Register Offset 0x0160*/
\r
2710 __I uint32_t RESERVED9[7];
\r
2711 __IO uint32_t BRSSEL[4]; /*!<Background Request Source Channel Select Register, Group 0 Offset 0x0180*/
\r
2712 __I uint32_t RESERVED10[12];
\r
2713 __IO uint32_t BRSPND[4]; /*!<Background Request Source Pending Register, Group 0 Offset 0x01C0*/
\r
2714 __I uint32_t RESERVED11[12];
\r
2715 __IO uint32_t BRSCTRL; /*!<Background Request Source Control Register Offset 0x0200*/
\r
2716 __IO uint32_t BRSMR; /*!<Background Request Source Mode Register Offset 0x0204*/
\r
2717 __I uint32_t RESERVED12[30];
\r
2718 __IO uint32_t GLOBRCR; /*!<Global Result Control Register Offset 0x0280*/
\r
2719 __I uint32_t RESERVED13[31];
\r
2720 __IO uint32_t GLOBRES; /*!<Global Result Register Offset 0x0300*/
\r
2721 __I uint32_t RESERVED14[31];
\r
2722 __IO uint32_t GLOBRESD; /*!<Global Result Register, Debug Offset 0x0380*/
\r
2723 __I uint32_t RESERVED15[27];
\r
2724 __IO uint32_t EMUXSEL; /*!<External Multiplexer Select Register Offset 0x03F0*/
\r
2725 }VADC_GLOBAL_TypeDef;
\r
2727 #define VADC_BASE ((uint32_t)0x40004000U)
\r
2728 #define VADC_G0_BASE (0x0480U)
\r
2729 #define VADC_G1_BASE (0x0880U)
\r
2730 #define VADC_G2_BASE (0x0C80U)
\r
2731 #define VADC_G3_BASE (0x1080U)
\r
2732 #define VADC_GLOBAL_BASE (0x0000U)
\r
2733 /***************************************************************************/
\r
2734 /* Peripheral Declaration */
\r
2735 /***************************************************************************/
\r
2736 #define VADC_G0 ((VADC_G_TypeDef*)(VADC_BASE + VADC_G0_BASE))
\r
2737 #define VADC_G1 ((VADC_G_TypeDef*)(VADC_BASE + VADC_G1_BASE))
\r
2738 #define VADC_G2 ((VADC_G_TypeDef*)(VADC_BASE + VADC_G2_BASE))
\r
2739 #define VADC_G3 ((VADC_G_TypeDef*)(VADC_BASE + VADC_G3_BASE))
\r
2740 #define VADC ((VADC_GLOBAL_TypeDef*)(VADC_BASE + VADC_GLOBAL_BASE))
\r
2742 /***************************************************************************/
\r
2744 /***************************************************************************/
\r
2747 *WDT Kernel registers
\r
2750 __I uint32_t ID; /*!<WDT ID Register Offset 0x0000*/
\r
2751 __IO uint32_t CTR; /*!<WDT Control Register Offset 0x0004*/
\r
2752 __O uint32_t SRV; /*!<WDT Service Register Offset 0x0008*/
\r
2753 __I uint32_t TIM; /*!<WDT Timer Register Offset 0x000C*/
\r
2754 __IO uint32_t WLB; /*!<WDT Window Lower Bound Register Offset 0x0010*/
\r
2755 __IO uint32_t WUB; /*!<WDT Window Upper Bound Register Offset 0x0014*/
\r
2756 __I uint32_t WDTSTS; /*!<WDT Status Register Offset 0x0018*/
\r
2757 __O uint32_t WDTCLR; /*!<WDT Clear Register Offset 0x001C*/
\r
2758 }WDT_GLOBAL_TypeDef;
\r
2760 #define WDT_BASE ((uint32_t)0x50008000U)
\r
2761 #define WDT_GLOBAL_BASE (0x0000U)
\r
2762 /***************************************************************************/
\r
2763 /* Peripheral Declaration */
\r
2764 /***************************************************************************/
\r
2765 #define WDT ((WDT_GLOBAL_TypeDef*)(WDT_BASE + WDT_GLOBAL_BASE))
\r
2768 /************************** Bit Fileds *************************************/
\r
2769 /***************************************************************************/
\r
2772 /*** CAN Bit Fileds *******************/
\r
2773 /***************************************************************************/
\r
2776 /* CAN_CLC = CAN Clock Control Register*/
\r
2777 #define CAN_CLC_DISR_Pos (0U)
\r
2778 #define CAN_CLC_DISR_Msk (0x00000001U << CAN_CLC_DISR_Pos)
\r
2780 #define CAN_CLC_DISS_Pos (1U)
\r
2781 #define CAN_CLC_DISS_Msk (0x00000001U << CAN_CLC_DISS_Pos)
\r
2783 #define CAN_CLC_EDIS_Pos (3U)
\r
2784 #define CAN_CLC_EDIS_Msk (0x00000001U << CAN_CLC_EDIS_Pos)
\r
2786 #define CAN_CLC_SBWE_Pos (4U)
\r
2787 #define CAN_CLC_SBWE_Msk (0x00000001U << CAN_CLC_SBWE_Pos)
\r
2789 /* CAN_ID = Module Identification Register*/
\r
2790 #define CAN_ID_MOD_REV_Pos (0U)
\r
2791 #define CAN_ID_MOD_REV_Msk (0x000000FFU << CAN_ID_MOD_REV_Pos)
\r
2793 #define CAN_ID_MOD_TYPE_Pos (8U)
\r
2794 #define CAN_ID_MOD_TYPE_Msk (0x000000FFU << CAN_ID_MOD_TYPE_Pos)
\r
2796 #define CAN_ID_MOD_NUMBER_Pos (16U)
\r
2797 #define CAN_ID_MOD_NUMBER_Msk (0x0000FFFFU << CAN_ID_MOD_NUMBER_Pos)
\r
2799 /* CAN_FDR = CAN Fractional Divider Register*/
\r
2800 #define CAN_FDR_STEP_Pos (0U)
\r
2801 #define CAN_FDR_STEP_Msk (0x000003FFU << CAN_FDR_STEP_Pos)
\r
2803 #define CAN_FDR_SM_Pos (11U)
\r
2804 #define CAN_FDR_SM_Msk (0x00000001U << CAN_FDR_SM_Pos)
\r
2806 #define CAN_FDR_SC_Pos (12U)
\r
2807 #define CAN_FDR_SC_Msk (0x00000003U << CAN_FDR_SC_Pos)
\r
2809 #define CAN_FDR_DM_Pos (14U)
\r
2810 #define CAN_FDR_DM_Msk (0x00000003U << CAN_FDR_DM_Pos)
\r
2812 #define CAN_FDR_RESULT_Pos (16U)
\r
2813 #define CAN_FDR_RESULT_Msk (0x000003FFU << CAN_FDR_RESULT_Pos)
\r
2815 #define CAN_FDR_SUSACK_Pos (28U)
\r
2816 #define CAN_FDR_SUSACK_Msk (0x00000001U << CAN_FDR_SUSACK_Pos)
\r
2818 #define CAN_FDR_SUSREQ_Pos (29U)
\r
2819 #define CAN_FDR_SUSREQ_Msk (0x00000001U << CAN_FDR_SUSREQ_Pos)
\r
2821 #define CAN_FDR_ENHW_Pos (30U)
\r
2822 #define CAN_FDR_ENHW_Msk (0x00000001U << CAN_FDR_ENHW_Pos)
\r
2824 #define CAN_FDR_DISCLK_Pos (31U)
\r
2825 #define CAN_FDR_DISCLK_Msk (0x00000001U << CAN_FDR_DISCLK_Pos)
\r
2827 /* CAN_LIST = List Register 0*/
\r
2828 #define CAN_LIST_BEGIN_Pos (0U)
\r
2829 #define CAN_LIST_BEGIN_Msk (0x000000FFU << CAN_LIST_BEGIN_Pos)
\r
2831 #define CAN_LIST_END_Pos (8U)
\r
2832 #define CAN_LIST_END_Msk (0x000000FFU << CAN_LIST_END_Pos)
\r
2834 #define CAN_LIST_SIZE_Pos (16U)
\r
2835 #define CAN_LIST_SIZE_Msk (0x000000FFU << CAN_LIST_SIZE_Pos)
\r
2837 #define CAN_LIST_EMPTY_Pos (24U)
\r
2838 #define CAN_LIST_EMPTY_Msk (0x00000001U << CAN_LIST_EMPTY_Pos)
\r
2840 /* CAN_MSPND = Message Pending Register 0*/
\r
2841 #define CAN_MSPND_PND_Pos (0U)
\r
2842 #define CAN_MSPND_PND_Msk (0xFFFFFFFFU << CAN_MSPND_PND_Pos)
\r
2844 /* CAN_MSID = Message Index Register 0*/
\r
2845 #define CAN_MSID_INDEX_Pos (0U)
\r
2846 #define CAN_MSID_INDEX_Msk (0x0000003FU << CAN_MSID_INDEX_Pos)
\r
2848 /* CAN_MSIMASK = Message Index Mask Register*/
\r
2849 #define CAN_MSIMASK_IM_Pos (0U)
\r
2850 #define CAN_MSIMASK_IM_Msk (0xFFFFFFFFU << CAN_MSIMASK_IM_Pos)
\r
2852 /* CAN_PANCTR = Panel Control Register*/
\r
2853 #define CAN_PANCTR_PANCMD_Pos (0U)
\r
2854 #define CAN_PANCTR_PANCMD_Msk (0x000000FFU << CAN_PANCTR_PANCMD_Pos)
\r
2856 #define CAN_PANCTR_BUSY_Pos (8U)
\r
2857 #define CAN_PANCTR_BUSY_Msk (0x00000001U << CAN_PANCTR_BUSY_Pos)
\r
2859 #define CAN_PANCTR_RBUSY_Pos (9U)
\r
2860 #define CAN_PANCTR_RBUSY_Msk (0x00000001U << CAN_PANCTR_RBUSY_Pos)
\r
2862 #define CAN_PANCTR_PANAR1_Pos (16U)
\r
2863 #define CAN_PANCTR_PANAR1_Msk (0x000000FFU << CAN_PANCTR_PANAR1_Pos)
\r
2865 #define CAN_PANCTR_PANAR2_Pos (24U)
\r
2866 #define CAN_PANCTR_PANAR2_Msk (0x000000FFU << CAN_PANCTR_PANAR2_Pos)
\r
2868 /* CAN_MCR = Module Control Register*/
\r
2869 #define CAN_MCR_MPSEL_Pos (12U)
\r
2870 #define CAN_MCR_MPSEL_Msk (0x0000000FU << CAN_MCR_MPSEL_Pos)
\r
2872 /* CAN_MITR = Module Interrupt Trigger Register*/
\r
2873 #define CAN_MITR_IT_Pos (0U)
\r
2874 #define CAN_MITR_IT_Msk (0x000000FFU << CAN_MITR_IT_Pos)
\r
2876 /* CAN_NODE_NCRx = Node x Control Register*/
\r
2877 #define CAN_NODE_NCR_INIT_Pos (0U)
\r
2878 #define CAN_NODE_NCR_INIT_Msk (0x00000001U << CAN_NODE_NCR_INIT_Pos)
\r
2880 #define CAN_NODE_NCR_TRIE_Pos (1U)
\r
2881 #define CAN_NODE_NCR_TRIE_Msk (0x00000001U << CAN_NODE_NCR_TRIE_Pos)
\r
2883 #define CAN_NODE_NCR_LECIE_Pos (2U)
\r
2884 #define CAN_NODE_NCR_LECIE_Msk (0x00000001U << CAN_NODE_NCR_LECIE_Pos)
\r
2886 #define CAN_NODE_NCR_ALIE_Pos (3U)
\r
2887 #define CAN_NODE_NCR_ALIE_Msk (0x00000001U << CAN_NODE_NCR_ALIE_Pos)
\r
2889 #define CAN_NODE_NCR_CANDIS_Pos (4U)
\r
2890 #define CAN_NODE_NCR_CANDIS_Msk (0x00000001U << CAN_NODE_NCR_CANDIS_Pos)
\r
2892 #define CAN_NODE_NCR_CCE_Pos (6U)
\r
2893 #define CAN_NODE_NCR_CCE_Msk (0x00000001U << CAN_NODE_NCR_CCE_Pos)
\r
2895 #define CAN_NODE_NCR_CALM_Pos (7U)
\r
2896 #define CAN_NODE_NCR_CALM_Msk (0x00000001U << CAN_NODE_NCR_CALM_Pos)
\r
2898 #define CAN_NODE_NCR_SUSEN_Pos (8U)
\r
2899 #define CAN_NODE_NCR_SUSEN_Msk (0x00000001U << CAN_NODE_NCR_SUSEN_Pos)
\r
2901 /* CAN_NODE_NSRx = Node x Status Register*/
\r
2902 #define CAN_NODE_NSR_LEC_Pos (0U)
\r
2903 #define CAN_NODE_NSR_LEC_Msk (0x00000007U << CAN_NODE_NSR_LEC_Pos)
\r
2905 #define CAN_NODE_NSR_TXOK_Pos (3U)
\r
2906 #define CAN_NODE_NSR_TXOK_Msk (0x00000001U << CAN_NODE_NSR_TXOK_Pos)
\r
2908 #define CAN_NODE_NSR_RXOK_Pos (4U)
\r
2909 #define CAN_NODE_NSR_RXOK_Msk (0x00000001U << CAN_NODE_NSR_RXOK_Pos)
\r
2911 #define CAN_NODE_NSR_ALERT_Pos (5U)
\r
2912 #define CAN_NODE_NSR_ALERT_Msk (0x00000001U << CAN_NODE_NSR_ALERT_Pos)
\r
2914 #define CAN_NODE_NSR_EWRN_Pos (6U)
\r
2915 #define CAN_NODE_NSR_EWRN_Msk (0x00000001U << CAN_NODE_NSR_EWRN_Pos)
\r
2917 #define CAN_NODE_NSR_BOFF_Pos (7U)
\r
2918 #define CAN_NODE_NSR_BOFF_Msk (0x00000001U << CAN_NODE_NSR_BOFF_Pos)
\r
2920 #define CAN_NODE_NSR_LLE_Pos (8U)
\r
2921 #define CAN_NODE_NSR_LLE_Msk (0x00000001U << CAN_NODE_NSR_LLE_Pos)
\r
2923 #define CAN_NODE_NSR_LOE_Pos (9U)
\r
2924 #define CAN_NODE_NSR_LOE_Msk (0x00000001U << CAN_NODE_NSR_LOE_Pos)
\r
2926 #define CAN_NODE_NSR_SUSACK_Pos (10U)
\r
2927 #define CAN_NODE_NSR_SUSACK_Msk (0x00000001U << CAN_NODE_NSR_SUSACK_Pos)
\r
2929 /* CAN_NODE_NIPRx = Node x Interrupt Pointer Register*/
\r
2930 #define CAN_NODE_NIPR_ALINP_Pos (0U)
\r
2931 #define CAN_NODE_NIPR_ALINP_Msk (0x00000007U << CAN_NODE_NIPR_ALINP_Pos)
\r
2933 #define CAN_NODE_NIPR_LECINP_Pos (4U)
\r
2934 #define CAN_NODE_NIPR_LECINP_Msk (0x00000007U << CAN_NODE_NIPR_LECINP_Pos)
\r
2936 #define CAN_NODE_NIPR_TRINP_Pos (8U)
\r
2937 #define CAN_NODE_NIPR_TRINP_Msk (0x00000007U << CAN_NODE_NIPR_TRINP_Pos)
\r
2939 #define CAN_NODE_NIPR_CFCINP_Pos (12U)
\r
2940 #define CAN_NODE_NIPR_CFCINP_Msk (0x00000007U << CAN_NODE_NIPR_CFCINP_Pos)
\r
2942 /* CAN_NODE_NPCRx = Node x Port Control Register*/
\r
2943 #define CAN_NODE_NPCR_RXSEL_Pos (0U)
\r
2944 #define CAN_NODE_NPCR_RXSEL_Msk (0x00000007U << CAN_NODE_NPCR_RXSEL_Pos)
\r
2946 #define CAN_NODE_NPCR_LBM_Pos (8U)
\r
2947 #define CAN_NODE_NPCR_LBM_Msk (0x00000001U << CAN_NODE_NPCR_LBM_Pos)
\r
2949 /* CAN_NODE_NBTRx = Node x Bit Timing Register*/
\r
2950 #define CAN_NODE_NBTR_BRP_Pos (0U)
\r
2951 #define CAN_NODE_NBTR_BRP_Msk (0x0000003FU << CAN_NODE_NBTR_BRP_Pos)
\r
2953 #define CAN_NODE_NBTR_SJW_Pos (6U)
\r
2954 #define CAN_NODE_NBTR_SJW_Msk (0x00000003U << CAN_NODE_NBTR_SJW_Pos)
\r
2956 #define CAN_NODE_NBTR_TSEG1_Pos (8U)
\r
2957 #define CAN_NODE_NBTR_TSEG1_Msk (0x0000000FU << CAN_NODE_NBTR_TSEG1_Pos)
\r
2959 #define CAN_NODE_NBTR_TSEG2_Pos (12U)
\r
2960 #define CAN_NODE_NBTR_TSEG2_Msk (0x00000007U << CAN_NODE_NBTR_TSEG2_Pos)
\r
2962 #define CAN_NODE_NBTR_DIV8_Pos (15U)
\r
2963 #define CAN_NODE_NBTR_DIV8_Msk (0x00000001U << CAN_NODE_NBTR_DIV8_Pos)
\r
2965 /* CAN_NODE_NECNTx = Node x Error Counter Register*/
\r
2966 #define CAN_NODE_NECNT_REC_Pos (0U)
\r
2967 #define CAN_NODE_NECNT_REC_Msk (0x000000FFU << CAN_NODE_NECNT_REC_Pos)
\r
2969 #define CAN_NODE_NECNT_TEC_Pos (8U)
\r
2970 #define CAN_NODE_NECNT_TEC_Msk (0x000000FFU << CAN_NODE_NECNT_TEC_Pos)
\r
2972 #define CAN_NODE_NECNT_EWRNLVL_Pos (16U)
\r
2973 #define CAN_NODE_NECNT_EWRNLVL_Msk (0x000000FFU << CAN_NODE_NECNT_EWRNLVL_Pos)
\r
2975 #define CAN_NODE_NECNT_LETD_Pos (24U)
\r
2976 #define CAN_NODE_NECNT_LETD_Msk (0x00000001U << CAN_NODE_NECNT_LETD_Pos)
\r
2978 #define CAN_NODE_NECNT_LEINC_Pos (25U)
\r
2979 #define CAN_NODE_NECNT_LEINC_Msk (0x00000001U << CAN_NODE_NECNT_LEINC_Pos)
\r
2981 /* CAN_NODE_NFCRx = Node x Frame Counter Register*/
\r
2982 #define CAN_NODE_NFCR_CFC_Pos (0U)
\r
2983 #define CAN_NODE_NFCR_CFC_Msk (0x0000FFFFU << CAN_NODE_NFCR_CFC_Pos)
\r
2985 #define CAN_NODE_NFCR_CFSEL_Pos (16U)
\r
2986 #define CAN_NODE_NFCR_CFSEL_Msk (0x00000007U << CAN_NODE_NFCR_CFSEL_Pos)
\r
2988 #define CAN_NODE_NFCR_CFMOD_Pos (19U)
\r
2989 #define CAN_NODE_NFCR_CFMOD_Msk (0x00000003U << CAN_NODE_NFCR_CFMOD_Pos)
\r
2991 #define CAN_NODE_NFCR_CFCIE_Pos (22U)
\r
2992 #define CAN_NODE_NFCR_CFCIE_Msk (0x00000001U << CAN_NODE_NFCR_CFCIE_Pos)
\r
2994 #define CAN_NODE_NFCR_CFCOV_Pos (23U)
\r
2995 #define CAN_NODE_NFCR_CFCOV_Msk (0x00000001U << CAN_NODE_NFCR_CFCOV_Pos)
\r
2997 /* CAN_MO_MOFCRx = Message Object x Function Control Register*/
\r
2998 #define CAN_MO_MOFCR_MMC_Pos (0U)
\r
2999 #define CAN_MO_MOFCR_MMC_Msk (0x0000000FU << CAN_MO_MOFCR_MMC_Pos)
\r
3001 #define CAN_MO_MOFCR_GDFS_Pos (8U)
\r
3002 #define CAN_MO_MOFCR_GDFS_Msk (0x00000001U << CAN_MO_MOFCR_GDFS_Pos)
\r
3004 #define CAN_MO_MOFCR_IDC_Pos (9U)
\r
3005 #define CAN_MO_MOFCR_IDC_Msk (0x00000001U << CAN_MO_MOFCR_IDC_Pos)
\r
3007 #define CAN_MO_MOFCR_DLCC_Pos (10U)
\r
3008 #define CAN_MO_MOFCR_DLCC_Msk (0x00000001U << CAN_MO_MOFCR_DLCC_Pos)
\r
3010 #define CAN_MO_MOFCR_DATC_Pos (11U)
\r
3011 #define CAN_MO_MOFCR_DATC_Msk (0x00000001U << CAN_MO_MOFCR_DATC_Pos)
\r
3013 #define CAN_MO_MOFCR_RXIE_Pos (16U)
\r
3014 #define CAN_MO_MOFCR_RXIE_Msk (0x00000001U << CAN_MO_MOFCR_RXIE_Pos)
\r
3016 #define CAN_MO_MOFCR_TXIE_Pos (17U)
\r
3017 #define CAN_MO_MOFCR_TXIE_Msk (0x00000001U << CAN_MO_MOFCR_TXIE_Pos)
\r
3019 #define CAN_MO_MOFCR_OVIE_Pos (18U)
\r
3020 #define CAN_MO_MOFCR_OVIE_Msk (0x00000001U << CAN_MO_MOFCR_OVIE_Pos)
\r
3022 #define CAN_MO_MOFCR_FRREN_Pos (20U)
\r
3023 #define CAN_MO_MOFCR_FRREN_Msk (0x00000001U << CAN_MO_MOFCR_FRREN_Pos)
\r
3025 #define CAN_MO_MOFCR_RMM_Pos (21U)
\r
3026 #define CAN_MO_MOFCR_RMM_Msk (0x00000001U << CAN_MO_MOFCR_RMM_Pos)
\r
3028 #define CAN_MO_MOFCR_SDT_Pos (22U)
\r
3029 #define CAN_MO_MOFCR_SDT_Msk (0x00000001U << CAN_MO_MOFCR_SDT_Pos)
\r
3031 #define CAN_MO_MOFCR_STT_Pos (23U)
\r
3032 #define CAN_MO_MOFCR_STT_Msk (0x00000001U << CAN_MO_MOFCR_STT_Pos)
\r
3034 #define CAN_MO_MOFCR_DLC_Pos (24U)
\r
3035 #define CAN_MO_MOFCR_DLC_Msk (0x0000000FU << CAN_MO_MOFCR_DLC_Pos)
\r
3037 /* CAN_MO_MOFGPRx = Message Object x FIFO/Gateway Pointer Register*/
\r
3038 #define CAN_MO_MOFGPR_BOT_Pos (0U)
\r
3039 #define CAN_MO_MOFGPR_BOT_Msk (0x000000FFU << CAN_MO_MOFGPR_BOT_Pos)
\r
3041 #define CAN_MO_MOFGPR_TOP_Pos (8U)
\r
3042 #define CAN_MO_MOFGPR_TOP_Msk (0x000000FFU << CAN_MO_MOFGPR_TOP_Pos)
\r
3044 #define CAN_MO_MOFGPR_CUR_Pos (16U)
\r
3045 #define CAN_MO_MOFGPR_CUR_Msk (0x000000FFU << CAN_MO_MOFGPR_CUR_Pos)
\r
3047 #define CAN_MO_MOFGPR_SEL_Pos (24U)
\r
3048 #define CAN_MO_MOFGPR_SEL_Msk (0x000000FFU << CAN_MO_MOFGPR_SEL_Pos)
\r
3050 /* CAN_MO_MOIPRx = Message Object x Interrupt Pointer Register*/
\r
3051 #define CAN_MO_MOIPR_RXINP_Pos (0U)
\r
3052 #define CAN_MO_MOIPR_RXINP_Msk (0x00000007U << CAN_MO_MOIPR_RXINP_Pos)
\r
3054 #define CAN_MO_MOIPR_TXINP_Pos (4U)
\r
3055 #define CAN_MO_MOIPR_TXINP_Msk (0x00000007U << CAN_MO_MOIPR_TXINP_Pos)
\r
3057 #define CAN_MO_MOIPR_MPN_Pos (8U)
\r
3058 #define CAN_MO_MOIPR_MPN_Msk (0x000000FFU << CAN_MO_MOIPR_MPN_Pos)
\r
3060 #define CAN_MO_MOIPR_CFCVAL_Pos (16U)
\r
3061 #define CAN_MO_MOIPR_CFCVAL_Msk (0x0000FFFFU << CAN_MO_MOIPR_CFCVAL_Pos)
\r
3063 /* CAN_MO_MOAMRx = Message Object x Acceptance Mask Register*/
\r
3064 #define CAN_MO_MOAMR_AM_Pos (0U)
\r
3065 #define CAN_MO_MOAMR_AM_Msk (0x1FFFFFFFU << CAN_MO_MOAMR_AM_Pos)
\r
3067 #define CAN_MO_MOAMR_MIDE_Pos (29U)
\r
3068 #define CAN_MO_MOAMR_MIDE_Msk (0x00000001U << CAN_MO_MOAMR_MIDE_Pos)
\r
3070 /* CAN_MO_MODATALx = Message Object x Data Register Low*/
\r
3071 #define CAN_MO_MODATAL_DB0_Pos (0U)
\r
3072 #define CAN_MO_MODATAL_DB0_Msk (0x000000FFU << CAN_MO_MODATAL_DB0_Pos)
\r
3074 #define CAN_MO_MODATAL_DB1_Pos (8U)
\r
3075 #define CAN_MO_MODATAL_DB1_Msk (0x000000FFU << CAN_MO_MODATAL_DB1_Pos)
\r
3077 #define CAN_MO_MODATAL_DB2_Pos (16U)
\r
3078 #define CAN_MO_MODATAL_DB2_Msk (0x000000FFU << CAN_MO_MODATAL_DB2_Pos)
\r
3080 #define CAN_MO_MODATAL_DB3_Pos (24U)
\r
3081 #define CAN_MO_MODATAL_DB3_Msk (0x000000FFU << CAN_MO_MODATAL_DB3_Pos)
\r
3083 /* CAN_MO_MODATAHx = Message Object x Data Register High*/
\r
3084 #define CAN_MO_MODATAH_DB4_Pos (0U)
\r
3085 #define CAN_MO_MODATAH_DB4_Msk (0x000000FFU << CAN_MO_MODATAH_DB4_Pos)
\r
3087 #define CAN_MO_MODATAH_DB5_Pos (8U)
\r
3088 #define CAN_MO_MODATAH_DB5_Msk (0x000000FFU << CAN_MO_MODATAH_DB5_Pos)
\r
3090 #define CAN_MO_MODATAH_DB6_Pos (16U)
\r
3091 #define CAN_MO_MODATAH_DB6_Msk (0x000000FFU << CAN_MO_MODATAH_DB6_Pos)
\r
3093 #define CAN_MO_MODATAH_DB7_Pos (24U)
\r
3094 #define CAN_MO_MODATAH_DB7_Msk (0x000000FFU << CAN_MO_MODATAH_DB7_Pos)
\r
3096 /* CAN_MO_MOARx = Message Object x Arbitration Register*/
\r
3097 #define CAN_MO_MOAR_ID_Pos (0U)
\r
3098 #define CAN_MO_MOAR_ID_Msk (0x1FFFFFFFU << CAN_MO_MOAR_ID_Pos)
\r
3100 #define CAN_MO_MOAR_IDE_Pos (29U)
\r
3101 #define CAN_MO_MOAR_IDE_Msk (0x00000001U << CAN_MO_MOAR_IDE_Pos)
\r
3103 #define CAN_MO_MOAR_PRI_Pos (30U)
\r
3104 #define CAN_MO_MOAR_PRI_Msk (0x00000003U << CAN_MO_MOAR_PRI_Pos)
\r
3106 /* CAN_MO_MOCTRx = Message Object x Control Register*/
\r
3107 #define CAN_MO_MOCTR_RESRXPND_Pos (0U)
\r
3108 #define CAN_MO_MOCTR_RESRXPND_Msk (0x00000001U << CAN_MO_MOCTR_RESRXPND_Pos)
\r
3110 #define CAN_MO_MOCTR_SETRXPND_Pos (16U)
\r
3111 #define CAN_MO_MOCTR_SETRXPND_Msk (0x00000001U << CAN_MO_MOCTR_SETRXPND_Pos)
\r
3113 #define CAN_MO_MOCTR_RESTXPND_Pos (1U)
\r
3114 #define CAN_MO_MOCTR_RESTXPND_Msk (0x00000001U << CAN_MO_MOCTR_RESTXPND_Pos)
\r
3116 #define CAN_MO_MOCTR_SETTXPND_Pos (17U)
\r
3117 #define CAN_MO_MOCTR_SETTXPND_Msk (0x00000001U << CAN_MO_MOCTR_SETTXPND_Pos)
\r
3119 #define CAN_MO_MOCTR_RESRXUPD_Pos (2U)
\r
3120 #define CAN_MO_MOCTR_RESRXUPD_Msk (0x00000001U << CAN_MO_MOCTR_RESRXUPD_Pos)
\r
3122 #define CAN_MO_MOCTR_SETRXUPD_Pos (18U)
\r
3123 #define CAN_MO_MOCTR_SETRXUPD_Msk (0x00000001U << CAN_MO_MOCTR_SETRXUPD_Pos)
\r
3125 #define CAN_MO_MOCTR_RESNEWDAT_Pos (3U)
\r
3126 #define CAN_MO_MOCTR_RESNEWDAT_Msk (0x00000001U << CAN_MO_MOCTR_RESNEWDAT_Pos)
\r
3128 #define CAN_MO_MOCTR_SETNEWDAT_Pos (19U)
\r
3129 #define CAN_MO_MOCTR_SETNEWDAT_Msk (0x00000001U << CAN_MO_MOCTR_SETNEWDAT_Pos)
\r
3131 #define CAN_MO_MOCTR_RESMSGLST_Pos (4U)
\r
3132 #define CAN_MO_MOCTR_RESMSGLST_Msk (0x00000001U << CAN_MO_MOCTR_RESMSGLST_Pos)
\r
3134 #define CAN_MO_MOCTR_SETMSGLST_Pos (20U)
\r
3135 #define CAN_MO_MOCTR_SETMSGLST_Msk (0x00000001U << CAN_MO_MOCTR_SETMSGLST_Pos)
\r
3137 #define CAN_MO_MOCTR_RESMSGVAL_Pos (5U)
\r
3138 #define CAN_MO_MOCTR_RESMSGVAL_Msk (0x00000001U << CAN_MO_MOCTR_RESMSGVAL_Pos)
\r
3140 #define CAN_MO_MOCTR_SETMSGVAL_Pos (21U)
\r
3141 #define CAN_MO_MOCTR_SETMSGVAL_Msk (0x00000001U << CAN_MO_MOCTR_SETMSGVAL_Pos)
\r
3143 #define CAN_MO_MOCTR_RESRTSEL_Pos (6U)
\r
3144 #define CAN_MO_MOCTR_RESRTSEL_Msk (0x00000001U << CAN_MO_MOCTR_RESRTSEL_Pos)
\r
3146 #define CAN_MO_MOCTR_SETRTSEL_Pos (22U)
\r
3147 #define CAN_MO_MOCTR_SETRTSEL_Msk (0x00000001U << CAN_MO_MOCTR_SETRTSEL_Pos)
\r
3149 #define CAN_MO_MOCTR_RESRXEN_Pos (7U)
\r
3150 #define CAN_MO_MOCTR_RESRXEN_Msk (0x00000001U << CAN_MO_MOCTR_RESRXEN_Pos)
\r
3152 #define CAN_MO_MOCTR_SETRXEN_Pos (23U)
\r
3153 #define CAN_MO_MOCTR_SETRXEN_Msk (0x00000001U << CAN_MO_MOCTR_SETRXEN_Pos)
\r
3155 #define CAN_MO_MOCTR_RESTXRQ_Pos (8U)
\r
3156 #define CAN_MO_MOCTR_RESTXRQ_Msk (0x00000001U << CAN_MO_MOCTR_RESTXRQ_Pos)
\r
3158 #define CAN_MO_MOCTR_SETTXRQ_Pos (24U)
\r
3159 #define CAN_MO_MOCTR_SETTXRQ_Msk (0x00000001U << CAN_MO_MOCTR_SETTXRQ_Pos)
\r
3161 #define CAN_MO_MOCTR_RESTXEN0_Pos (9U)
\r
3162 #define CAN_MO_MOCTR_RESTXEN0_Msk (0x00000001U << CAN_MO_MOCTR_RESTXEN0_Pos)
\r
3164 #define CAN_MO_MOCTR_SETTXEN0_Pos (25U)
\r
3165 #define CAN_MO_MOCTR_SETTXEN0_Msk (0x00000001U << CAN_MO_MOCTR_SETTXEN0_Pos)
\r
3167 #define CAN_MO_MOCTR_RESTXEN1_Pos (10U)
\r
3168 #define CAN_MO_MOCTR_RESTXEN1_Msk (0x00000001U << CAN_MO_MOCTR_RESTXEN1_Pos)
\r
3170 #define CAN_MO_MOCTR_SETTXEN1_Pos (26U)
\r
3171 #define CAN_MO_MOCTR_SETTXEN1_Msk (0x00000001U << CAN_MO_MOCTR_SETTXEN1_Pos)
\r
3173 #define CAN_MO_MOCTR_RESDIR_Pos (11U)
\r
3174 #define CAN_MO_MOCTR_RESDIR_Msk (0x00000001U << CAN_MO_MOCTR_RESDIR_Pos)
\r
3176 #define CAN_MO_MOCTR_SETDIR_Pos (27U)
\r
3177 #define CAN_MO_MOCTR_SETDIR_Msk (0x00000001U << CAN_MO_MOCTR_SETDIR_Pos)
\r
3179 /* CAN_MO_MOSTATx = Message Object x Status Register*/
\r
3180 #define CAN_MO_MOSTAT_RXPND_Pos (0U)
\r
3181 #define CAN_MO_MOSTAT_RXPND_Msk (0x00000001U << CAN_MO_MOSTAT_RXPND_Pos)
\r
3183 #define CAN_MO_MOSTAT_TXPND_Pos (1U)
\r
3184 #define CAN_MO_MOSTAT_TXPND_Msk (0x00000001U << CAN_MO_MOSTAT_TXPND_Pos)
\r
3186 #define CAN_MO_MOSTAT_RXUPD_Pos (2U)
\r
3187 #define CAN_MO_MOSTAT_RXUPD_Msk (0x00000001U << CAN_MO_MOSTAT_RXUPD_Pos)
\r
3189 #define CAN_MO_MOSTAT_NEWDAT_Pos (3U)
\r
3190 #define CAN_MO_MOSTAT_NEWDAT_Msk (0x00000001U << CAN_MO_MOSTAT_NEWDAT_Pos)
\r
3192 #define CAN_MO_MOSTAT_MSGLST_Pos (4U)
\r
3193 #define CAN_MO_MOSTAT_MSGLST_Msk (0x00000001U << CAN_MO_MOSTAT_MSGLST_Pos)
\r
3195 #define CAN_MO_MOSTAT_MSGVAL_Pos (5U)
\r
3196 #define CAN_MO_MOSTAT_MSGVAL_Msk (0x00000001U << CAN_MO_MOSTAT_MSGVAL_Pos)
\r
3198 #define CAN_MO_MOSTAT_RTSEL_Pos (6U)
\r
3199 #define CAN_MO_MOSTAT_RTSEL_Msk (0x00000001U << CAN_MO_MOSTAT_RTSEL_Pos)
\r
3201 #define CAN_MO_MOSTAT_RXEN_Pos (7U)
\r
3202 #define CAN_MO_MOSTAT_RXEN_Msk (0x00000001U << CAN_MO_MOSTAT_RXEN_Pos)
\r
3204 #define CAN_MO_MOSTAT_TXRQ_Pos (8U)
\r
3205 #define CAN_MO_MOSTAT_TXRQ_Msk (0x00000001U << CAN_MO_MOSTAT_TXRQ_Pos)
\r
3207 #define CAN_MO_MOSTAT_TXEN0_Pos (9U)
\r
3208 #define CAN_MO_MOSTAT_TXEN0_Msk (0x00000001U << CAN_MO_MOSTAT_TXEN0_Pos)
\r
3210 #define CAN_MO_MOSTAT_TXEN1_Pos (10U)
\r
3211 #define CAN_MO_MOSTAT_TXEN1_Msk (0x00000001U << CAN_MO_MOSTAT_TXEN1_Pos)
\r
3213 #define CAN_MO_MOSTAT_DIR_Pos (11U)
\r
3214 #define CAN_MO_MOSTAT_DIR_Msk (0x00000001U << CAN_MO_MOSTAT_DIR_Pos)
\r
3216 #define CAN_MO_MOSTAT_LIST_Pos (12U)
\r
3217 #define CAN_MO_MOSTAT_LIST_Msk (0x0000000FU << CAN_MO_MOSTAT_LIST_Pos)
\r
3219 #define CAN_MO_MOSTAT_PPREV_Pos (16U)
\r
3220 #define CAN_MO_MOSTAT_PPREV_Msk (0x000000FFU << CAN_MO_MOSTAT_PPREV_Pos)
\r
3222 #define CAN_MO_MOSTAT_PNEXT_Pos (24U)
\r
3223 #define CAN_MO_MOSTAT_PNEXT_Msk (0x000000FFU << CAN_MO_MOSTAT_PNEXT_Pos)
\r
3227 /*** CCU4x Bit Fileds *******************/
\r
3228 /***************************************************************************/
\r
3231 /* CCU4_GCTRL = Global Control Register*/
\r
3232 #define CCU4_GCTRL_PRBC_Pos (0U)
\r
3233 #define CCU4_GCTRL_PRBC_Msk (0x00000007U << CCU4_GCTRL_PRBC_Pos)
\r
3235 #define CCU4_GCTRL_PCIS_Pos (4U)
\r
3236 #define CCU4_GCTRL_PCIS_Msk (0x00000003U << CCU4_GCTRL_PCIS_Pos)
\r
3238 #define CCU4_GCTRL_SUSCFG_Pos (8U)
\r
3239 #define CCU4_GCTRL_SUSCFG_Msk (0x00000003U << CCU4_GCTRL_SUSCFG_Pos)
\r
3241 #define CCU4_GCTRL_MSE0_Pos (10U)
\r
3242 #define CCU4_GCTRL_MSE0_Msk (0x00000001U << CCU4_GCTRL_MSE0_Pos)
\r
3244 #define CCU4_GCTRL_MSE1_Pos (11U)
\r
3245 #define CCU4_GCTRL_MSE1_Msk (0x00000001U << CCU4_GCTRL_MSE1_Pos)
\r
3247 #define CCU4_GCTRL_MSE2_Pos (12U)
\r
3248 #define CCU4_GCTRL_MSE2_Msk (0x00000001U << CCU4_GCTRL_MSE2_Pos)
\r
3250 #define CCU4_GCTRL_MSE3_Pos (13U)
\r
3251 #define CCU4_GCTRL_MSE3_Msk (0x00000001U << CCU4_GCTRL_MSE3_Pos)
\r
3253 #define CCU4_GCTRL_MSDE_Pos (14U)
\r
3254 #define CCU4_GCTRL_MSDE_Msk (0x00000003U << CCU4_GCTRL_MSDE_Pos)
\r
3256 /* CCU4_GSTAT = Global Status Register*/
\r
3257 #define CCU4_GSTAT_S0I_Pos (0U)
\r
3258 #define CCU4_GSTAT_S0I_Msk (0x00000001U << CCU4_GSTAT_S0I_Pos)
\r
3260 #define CCU4_GSTAT_S1I_Pos (1U)
\r
3261 #define CCU4_GSTAT_S1I_Msk (0x00000001U << CCU4_GSTAT_S1I_Pos)
\r
3263 #define CCU4_GSTAT_S2I_Pos (2U)
\r
3264 #define CCU4_GSTAT_S2I_Msk (0x00000001U << CCU4_GSTAT_S2I_Pos)
\r
3266 #define CCU4_GSTAT_S3I_Pos (3U)
\r
3267 #define CCU4_GSTAT_S3I_Msk (0x00000001U << CCU4_GSTAT_S3I_Pos)
\r
3269 #define CCU4_GSTAT_PRB_Pos (8U)
\r
3270 #define CCU4_GSTAT_PRB_Msk (0x00000001U << CCU4_GSTAT_PRB_Pos)
\r
3272 /* CCU4_GIDLS = Global Idle Set*/
\r
3273 #define CCU4_GIDLS_SS0I_Pos (0U)
\r
3274 #define CCU4_GIDLS_SS0I_Msk (0x00000001U << CCU4_GIDLS_SS0I_Pos)
\r
3276 #define CCU4_GIDLS_SS1I_Pos (1U)
\r
3277 #define CCU4_GIDLS_SS1I_Msk (0x00000001U << CCU4_GIDLS_SS1I_Pos)
\r
3279 #define CCU4_GIDLS_SS2I_Pos (2U)
\r
3280 #define CCU4_GIDLS_SS2I_Msk (0x00000001U << CCU4_GIDLS_SS2I_Pos)
\r
3282 #define CCU4_GIDLS_SS3I_Pos (3U)
\r
3283 #define CCU4_GIDLS_SS3I_Msk (0x00000001U << CCU4_GIDLS_SS3I_Pos)
\r
3285 #define CCU4_GIDLS_CPRB_Pos (8U)
\r
3286 #define CCU4_GIDLS_CPRB_Msk (0x00000001U << CCU4_GIDLS_CPRB_Pos)
\r
3288 #define CCU4_GIDLS_PSIC_Pos (9U)
\r
3289 #define CCU4_GIDLS_PSIC_Msk (0x00000001U << CCU4_GIDLS_PSIC_Pos)
\r
3291 /* CCU4_GIDLC = Global Idle Clear*/
\r
3292 #define CCU4_GIDLC_CS0I_Pos (0U)
\r
3293 #define CCU4_GIDLC_CS0I_Msk (0x00000001U << CCU4_GIDLC_CS0I_Pos)
\r
3295 #define CCU4_GIDLC_CS1I_Pos (1U)
\r
3296 #define CCU4_GIDLC_CS1I_Msk (0x00000001U << CCU4_GIDLC_CS1I_Pos)
\r
3298 #define CCU4_GIDLC_CS2I_Pos (2U)
\r
3299 #define CCU4_GIDLC_CS2I_Msk (0x00000001U << CCU4_GIDLC_CS2I_Pos)
\r
3301 #define CCU4_GIDLC_CS3I_Pos (3U)
\r
3302 #define CCU4_GIDLC_CS3I_Msk (0x00000001U << CCU4_GIDLC_CS3I_Pos)
\r
3304 #define CCU4_GIDLC_SPRB_Pos (8U)
\r
3305 #define CCU4_GIDLC_SPRB_Msk (0x00000001U << CCU4_GIDLC_SPRB_Pos)
\r
3307 /* CCU4_GCSS = Global Channel Set*/
\r
3308 #define CCU4_GCSS_S0SE_Pos (0U)
\r
3309 #define CCU4_GCSS_S0SE_Msk (0x00000001U << CCU4_GCSS_S0SE_Pos)
\r
3311 #define CCU4_GCSS_S0DSE_Pos (1U)
\r
3312 #define CCU4_GCSS_S0DSE_Msk (0x00000001U << CCU4_GCSS_S0DSE_Pos)
\r
3314 #define CCU4_GCSS_S0PSE_Pos (2U)
\r
3315 #define CCU4_GCSS_S0PSE_Msk (0x00000001U << CCU4_GCSS_S0PSE_Pos)
\r
3317 #define CCU4_GCSS_S1SE_Pos (4U)
\r
3318 #define CCU4_GCSS_S1SE_Msk (0x00000001U << CCU4_GCSS_S1SE_Pos)
\r
3320 #define CCU4_GCSS_S1DSE_Pos (5U)
\r
3321 #define CCU4_GCSS_S1DSE_Msk (0x00000001U << CCU4_GCSS_S1DSE_Pos)
\r
3323 #define CCU4_GCSS_S1PSE_Pos (6U)
\r
3324 #define CCU4_GCSS_S1PSE_Msk (0x00000001U << CCU4_GCSS_S1PSE_Pos)
\r
3326 #define CCU4_GCSS_S2SE_Pos (8U)
\r
3327 #define CCU4_GCSS_S2SE_Msk (0x00000001U << CCU4_GCSS_S2SE_Pos)
\r
3329 #define CCU4_GCSS_S2DSE_Pos (9U)
\r
3330 #define CCU4_GCSS_S2DSE_Msk (0x00000001U << CCU4_GCSS_S2DSE_Pos)
\r
3332 #define CCU4_GCSS_S2PSE_Pos (10U)
\r
3333 #define CCU4_GCSS_S2PSE_Msk (0x00000001U << CCU4_GCSS_S2PSE_Pos)
\r
3335 #define CCU4_GCSS_S3SE_Pos (12U)
\r
3336 #define CCU4_GCSS_S3SE_Msk (0x00000001U << CCU4_GCSS_S3SE_Pos)
\r
3338 #define CCU4_GCSS_S3DSE_Pos (13U)
\r
3339 #define CCU4_GCSS_S3DSE_Msk (0x00000001U << CCU4_GCSS_S3DSE_Pos)
\r
3341 #define CCU4_GCSS_S3PSE_Pos (14U)
\r
3342 #define CCU4_GCSS_S3PSE_Msk (0x00000001U << CCU4_GCSS_S3PSE_Pos)
\r
3344 #define CCU4_GCSS_S0STS_Pos (16U)
\r
3345 #define CCU4_GCSS_S0STS_Msk (0x00000001U << CCU4_GCSS_S0STS_Pos)
\r
3347 #define CCU4_GCSS_S1STS_Pos (17U)
\r
3348 #define CCU4_GCSS_S1STS_Msk (0x00000001U << CCU4_GCSS_S1STS_Pos)
\r
3350 #define CCU4_GCSS_S2STS_Pos (18U)
\r
3351 #define CCU4_GCSS_S2STS_Msk (0x00000001U << CCU4_GCSS_S2STS_Pos)
\r
3353 #define CCU4_GCSS_S3STS_Pos (19U)
\r
3354 #define CCU4_GCSS_S3STS_Msk (0x00000001U << CCU4_GCSS_S3STS_Pos)
\r
3356 /* CCU4_GCSC = Global Channel Clear*/
\r
3357 #define CCU4_GCSC_S0SC_Pos (0U)
\r
3358 #define CCU4_GCSC_S0SC_Msk (0x00000001U << CCU4_GCSC_S0SC_Pos)
\r
3360 #define CCU4_GCSC_S0DSC_Pos (1U)
\r
3361 #define CCU4_GCSC_S0DSC_Msk (0x00000001U << CCU4_GCSC_S0DSC_Pos)
\r
3363 #define CCU4_GCSC_S0PSC_Pos (2U)
\r
3364 #define CCU4_GCSC_S0PSC_Msk (0x00000001U << CCU4_GCSC_S0PSC_Pos)
\r
3366 #define CCU4_GCSC_S1SC_Pos (4U)
\r
3367 #define CCU4_GCSC_S1SC_Msk (0x00000001U << CCU4_GCSC_S1SC_Pos)
\r
3369 #define CCU4_GCSC_S1DSC_Pos (5U)
\r
3370 #define CCU4_GCSC_S1DSC_Msk (0x00000001U << CCU4_GCSC_S1DSC_Pos)
\r
3372 #define CCU4_GCSC_S1PSC_Pos (6U)
\r
3373 #define CCU4_GCSC_S1PSC_Msk (0x00000001U << CCU4_GCSC_S1PSC_Pos)
\r
3375 #define CCU4_GCSC_S2SC_Pos (8U)
\r
3376 #define CCU4_GCSC_S2SC_Msk (0x00000001U << CCU4_GCSC_S2SC_Pos)
\r
3378 #define CCU4_GCSC_S2DSC_Pos (9U)
\r
3379 #define CCU4_GCSC_S2DSC_Msk (0x00000001U << CCU4_GCSC_S2DSC_Pos)
\r
3381 #define CCU4_GCSC_S2PSC_Pos (10U)
\r
3382 #define CCU4_GCSC_S2PSC_Msk (0x00000001U << CCU4_GCSC_S2PSC_Pos)
\r
3384 #define CCU4_GCSC_S3SC_Pos (12U)
\r
3385 #define CCU4_GCSC_S3SC_Msk (0x00000001U << CCU4_GCSC_S3SC_Pos)
\r
3387 #define CCU4_GCSC_S3DSC_Pos (13U)
\r
3388 #define CCU4_GCSC_S3DSC_Msk (0x00000001U << CCU4_GCSC_S3DSC_Pos)
\r
3390 #define CCU4_GCSC_S3PSC_Pos (14U)
\r
3391 #define CCU4_GCSC_S3PSC_Msk (0x00000001U << CCU4_GCSC_S3PSC_Pos)
\r
3393 #define CCU4_GCSC_S0STC_Pos (16U)
\r
3394 #define CCU4_GCSC_S0STC_Msk (0x00000001U << CCU4_GCSC_S0STC_Pos)
\r
3396 #define CCU4_GCSC_S1STC_Pos (17U)
\r
3397 #define CCU4_GCSC_S1STC_Msk (0x00000001U << CCU4_GCSC_S1STC_Pos)
\r
3399 #define CCU4_GCSC_S2STC_Pos (18U)
\r
3400 #define CCU4_GCSC_S2STC_Msk (0x00000001U << CCU4_GCSC_S2STC_Pos)
\r
3402 #define CCU4_GCSC_S3STC_Pos (19U)
\r
3403 #define CCU4_GCSC_S3STC_Msk (0x00000001U << CCU4_GCSC_S3STC_Pos)
\r
3405 /* CCU4_GCST = Global Channel Status*/
\r
3406 #define CCU4_GCST_S0SS_Pos (0U)
\r
3407 #define CCU4_GCST_S0SS_Msk (0x00000001U << CCU4_GCST_S0SS_Pos)
\r
3409 #define CCU4_GCST_S0DSS_Pos (1U)
\r
3410 #define CCU4_GCST_S0DSS_Msk (0x00000001U << CCU4_GCST_S0DSS_Pos)
\r
3412 #define CCU4_GCST_S0PSS_Pos (2U)
\r
3413 #define CCU4_GCST_S0PSS_Msk (0x00000001U << CCU4_GCST_S0PSS_Pos)
\r
3415 #define CCU4_GCST_S1SS_Pos (4U)
\r
3416 #define CCU4_GCST_S1SS_Msk (0x00000001U << CCU4_GCST_S1SS_Pos)
\r
3418 #define CCU4_GCST_S1DSS_Pos (5U)
\r
3419 #define CCU4_GCST_S1DSS_Msk (0x00000001U << CCU4_GCST_S1DSS_Pos)
\r
3421 #define CCU4_GCST_S1PSS_Pos (6U)
\r
3422 #define CCU4_GCST_S1PSS_Msk (0x00000001U << CCU4_GCST_S1PSS_Pos)
\r
3424 #define CCU4_GCST_S2SS_Pos (8U)
\r
3425 #define CCU4_GCST_S2SS_Msk (0x00000001U << CCU4_GCST_S2SS_Pos)
\r
3427 #define CCU4_GCST_S2DSS_Pos (9U)
\r
3428 #define CCU4_GCST_S2DSS_Msk (0x00000001U << CCU4_GCST_S2DSS_Pos)
\r
3430 #define CCU4_GCST_S2PSS_Pos (10U)
\r
3431 #define CCU4_GCST_S2PSS_Msk (0x00000001U << CCU4_GCST_S2PSS_Pos)
\r
3433 #define CCU4_GCST_S3SS_Pos (12U)
\r
3434 #define CCU4_GCST_S3SS_Msk (0x00000001U << CCU4_GCST_S3SS_Pos)
\r
3436 #define CCU4_GCST_S3DSS_Pos (13U)
\r
3437 #define CCU4_GCST_S3DSS_Msk (0x00000001U << CCU4_GCST_S3DSS_Pos)
\r
3439 #define CCU4_GCST_S3PSS_Pos (14U)
\r
3440 #define CCU4_GCST_S3PSS_Msk (0x00000001U << CCU4_GCST_S3PSS_Pos)
\r
3442 #define CCU4_GCST_CC40ST_Pos (16U)
\r
3443 #define CCU4_GCST_CC40ST_Msk (0x00000001U << CCU4_GCST_CC40ST_Pos)
\r
3445 #define CCU4_GCST_CC41ST_Pos (17U)
\r
3446 #define CCU4_GCST_CC41ST_Msk (0x00000001U << CCU4_GCST_CC41ST_Pos)
\r
3448 #define CCU4_GCST_CC42ST_Pos (18U)
\r
3449 #define CCU4_GCST_CC42ST_Msk (0x00000001U << CCU4_GCST_CC42ST_Pos)
\r
3451 #define CCU4_GCST_CC43ST_Pos (19U)
\r
3452 #define CCU4_GCST_CC43ST_Msk (0x00000001U << CCU4_GCST_CC43ST_Pos)
\r
3454 /* CCU4_ECRD = Extended Capture Mode Read*/
\r
3455 #define CCU4_ECRD_CAPV_Pos (0U)
\r
3456 #define CCU4_ECRD_CAPV_Msk (0x0000FFFFU << CCU4_ECRD_CAPV_Pos)
\r
3458 #define CCU4_ECRD_FPCV_Pos (16U)
\r
3459 #define CCU4_ECRD_FPCV_Msk (0x0000000FU << CCU4_ECRD_FPCV_Pos)
\r
3461 #define CCU4_ECRD_SPTR_Pos (20U)
\r
3462 #define CCU4_ECRD_SPTR_Msk (0x00000003U << CCU4_ECRD_SPTR_Pos)
\r
3464 #define CCU4_ECRD_VPTR_Pos (22U)
\r
3465 #define CCU4_ECRD_VPTR_Msk (0x00000003U << CCU4_ECRD_VPTR_Pos)
\r
3467 #define CCU4_ECRD_FFL_Pos (24U)
\r
3468 #define CCU4_ECRD_FFL_Msk (0x00000001U << CCU4_ECRD_FFL_Pos)
\r
3470 /* CCU4_MIDR = Module Identification*/
\r
3471 #define CCU4_MIDR_MODR_Pos (0U)
\r
3472 #define CCU4_MIDR_MODR_Msk (0x000000FFU << CCU4_MIDR_MODR_Pos)
\r
3474 #define CCU4_MIDR_MODT_Pos (8U)
\r
3475 #define CCU4_MIDR_MODT_Msk (0x000000FFU << CCU4_MIDR_MODT_Pos)
\r
3477 #define CCU4_MIDR_MODN_Pos (16U)
\r
3478 #define CCU4_MIDR_MODN_Msk (0x0000FFFFU << CCU4_MIDR_MODN_Pos)
\r
3480 /* CCU4_CC4_INS = Input Selector Configuration*/
\r
3481 #define CCU4_CC4_INS_EV0IS_Pos (0U)
\r
3482 #define CCU4_CC4_INS_EV0IS_Msk (0x0000000FU << CCU4_CC4_INS_EV0IS_Pos)
\r
3484 #define CCU4_CC4_INS_EV1IS_Pos (4U)
\r
3485 #define CCU4_CC4_INS_EV1IS_Msk (0x0000000FU << CCU4_CC4_INS_EV1IS_Pos)
\r
3487 #define CCU4_CC4_INS_EV2S_Pos (8U)
\r
3488 #define CCU4_CC4_INS_EV2S_Msk (0x0000000FU << CCU4_CC4_INS_EV2S_Pos)
\r
3490 #define CCU4_CC4_INS_EV0EM_Pos (16U)
\r
3491 #define CCU4_CC4_INS_EV0EM_Msk (0x00000003U << CCU4_CC4_INS_EV0EM_Pos)
\r
3493 #define CCU4_CC4_INS_EV1EM_Pos (18U)
\r
3494 #define CCU4_CC4_INS_EV1EM_Msk (0x00000003U << CCU4_CC4_INS_EV1EM_Pos)
\r
3496 #define CCU4_CC4_INS_EV2EM_Pos (20U)
\r
3497 #define CCU4_CC4_INS_EV2EM_Msk (0x00000003U << CCU4_CC4_INS_EV2EM_Pos)
\r
3499 #define CCU4_CC4_INS_EV0LM_Pos (22U)
\r
3500 #define CCU4_CC4_INS_EV0LM_Msk (0x00000001U << CCU4_CC4_INS_EV0LM_Pos)
\r
3502 #define CCU4_CC4_INS_EV1LM_Pos (23U)
\r
3503 #define CCU4_CC4_INS_EV1LM_Msk (0x00000001U << CCU4_CC4_INS_EV1LM_Pos)
\r
3505 #define CCU4_CC4_INS_EV2LM_Pos (24U)
\r
3506 #define CCU4_CC4_INS_EV2LM_Msk (0x00000001U << CCU4_CC4_INS_EV2LM_Pos)
\r
3508 #define CCU4_CC4_INS_LPF0M_Pos (25U)
\r
3509 #define CCU4_CC4_INS_LPF0M_Msk (0x00000003U << CCU4_CC4_INS_LPF0M_Pos)
\r
3511 #define CCU4_CC4_INS_LPF1M_Pos (27U)
\r
3512 #define CCU4_CC4_INS_LPF1M_Msk (0x00000003U << CCU4_CC4_INS_LPF1M_Pos)
\r
3514 #define CCU4_CC4_INS_LPF2M_Pos (29U)
\r
3515 #define CCU4_CC4_INS_LPF2M_Msk (0x00000003U << CCU4_CC4_INS_LPF2M_Pos)
\r
3517 /* CCU4_CC4_CMC = Connection Matrix Control*/
\r
3518 #define CCU4_CC4_CMC_STRTS_Pos (0U)
\r
3519 #define CCU4_CC4_CMC_STRTS_Msk (0x00000003U << CCU4_CC4_CMC_STRTS_Pos)
\r
3521 #define CCU4_CC4_CMC_ENDS_Pos (2U)
\r
3522 #define CCU4_CC4_CMC_ENDS_Msk (0x00000003U << CCU4_CC4_CMC_ENDS_Pos)
\r
3524 #define CCU4_CC4_CMC_CAP0S_Pos (4U)
\r
3525 #define CCU4_CC4_CMC_CAP0S_Msk (0x00000003U << CCU4_CC4_CMC_CAP0S_Pos)
\r
3527 #define CCU4_CC4_CMC_CAP1S_Pos (6U)
\r
3528 #define CCU4_CC4_CMC_CAP1S_Msk (0x00000003U << CCU4_CC4_CMC_CAP1S_Pos)
\r
3530 #define CCU4_CC4_CMC_GATES_Pos (8U)
\r
3531 #define CCU4_CC4_CMC_GATES_Msk (0x00000003U << CCU4_CC4_CMC_GATES_Pos)
\r
3533 #define CCU4_CC4_CMC_UDS_Pos (10U)
\r
3534 #define CCU4_CC4_CMC_UDS_Msk (0x00000003U << CCU4_CC4_CMC_UDS_Pos)
\r
3536 #define CCU4_CC4_CMC_LDS_Pos (12U)
\r
3537 #define CCU4_CC4_CMC_LDS_Msk (0x00000003U << CCU4_CC4_CMC_LDS_Pos)
\r
3539 #define CCU4_CC4_CMC_CNTS_Pos (14U)
\r
3540 #define CCU4_CC4_CMC_CNTS_Msk (0x00000003U << CCU4_CC4_CMC_CNTS_Pos)
\r
3542 #define CCU4_CC4_CMC_OFS_Pos (16U)
\r
3543 #define CCU4_CC4_CMC_OFS_Msk (0x00000001U << CCU4_CC4_CMC_OFS_Pos)
\r
3545 #define CCU4_CC4_CMC_TS_Pos (17U)
\r
3546 #define CCU4_CC4_CMC_TS_Msk (0x00000001U << CCU4_CC4_CMC_TS_Pos)
\r
3548 #define CCU4_CC4_CMC_MOS_Pos (18U)
\r
3549 #define CCU4_CC4_CMC_MOS_Msk (0x00000003U << CCU4_CC4_CMC_MOS_Pos)
\r
3551 #define CCU4_CC4_CMC_TCE_Pos (20U)
\r
3552 #define CCU4_CC4_CMC_TCE_Msk (0x00000001U << CCU4_CC4_CMC_TCE_Pos)
\r
3554 /* CCU4_CC4_TCST = Slice Timer Status*/
\r
3555 #define CCU4_CC4_TCST_TRB_Pos (0U)
\r
3556 #define CCU4_CC4_TCST_TRB_Msk (0x00000001U << CCU4_CC4_TCST_TRB_Pos)
\r
3558 #define CCU4_CC4_TCST_CDIR_Pos (1U)
\r
3559 #define CCU4_CC4_TCST_CDIR_Msk (0x00000001U << CCU4_CC4_TCST_CDIR_Pos)
\r
3561 /* CCU4_CC4_TCSET = Slice Timer Run Set*/
\r
3562 #define CCU4_CC4_TCSET_TRBS_Pos (0U)
\r
3563 #define CCU4_CC4_TCSET_TRBS_Msk (0x00000001U << CCU4_CC4_TCSET_TRBS_Pos)
\r
3565 /* CCU4_CC4_TCCLR = Slice Timer Clear*/
\r
3566 #define CCU4_CC4_TCCLR_TRBC_Pos (0U)
\r
3567 #define CCU4_CC4_TCCLR_TRBC_Msk (0x00000001U << CCU4_CC4_TCCLR_TRBC_Pos)
\r
3569 #define CCU4_CC4_TCCLR_TCC_Pos (1U)
\r
3570 #define CCU4_CC4_TCCLR_TCC_Msk (0x00000001U << CCU4_CC4_TCCLR_TCC_Pos)
\r
3572 #define CCU4_CC4_TCCLR_DITC_Pos (2U)
\r
3573 #define CCU4_CC4_TCCLR_DITC_Msk (0x00000001U << CCU4_CC4_TCCLR_DITC_Pos)
\r
3575 /* CCU4_CC4_TC = Slice Timer Control*/
\r
3576 #define CCU4_CC4_TC_TCM_Pos (0U)
\r
3577 #define CCU4_CC4_TC_TCM_Msk (0x00000001U << CCU4_CC4_TC_TCM_Pos)
\r
3579 #define CCU4_CC4_TC_TSSM_Pos (1U)
\r
3580 #define CCU4_CC4_TC_TSSM_Msk (0x00000001U << CCU4_CC4_TC_TSSM_Pos)
\r
3582 #define CCU4_CC4_TC_CLST_Pos (2U)
\r
3583 #define CCU4_CC4_TC_CLST_Msk (0x00000001U << CCU4_CC4_TC_CLST_Pos)
\r
3585 #define CCU4_CC4_TC_CMOD_Pos (3U)
\r
3586 #define CCU4_CC4_TC_CMOD_Msk (0x00000001U << CCU4_CC4_TC_CMOD_Pos)
\r
3588 #define CCU4_CC4_TC_ECM_Pos (4U)
\r
3589 #define CCU4_CC4_TC_ECM_Msk (0x00000001U << CCU4_CC4_TC_ECM_Pos)
\r
3591 #define CCU4_CC4_TC_CAPC_Pos (5U)
\r
3592 #define CCU4_CC4_TC_CAPC_Msk (0x00000003U << CCU4_CC4_TC_CAPC_Pos)
\r
3594 #define CCU4_CC4_TC_ENDM_Pos (8U)
\r
3595 #define CCU4_CC4_TC_ENDM_Msk (0x00000003U << CCU4_CC4_TC_ENDM_Pos)
\r
3597 #define CCU4_CC4_TC_STRM_Pos (10U)
\r
3598 #define CCU4_CC4_TC_STRM_Msk (0x00000001U << CCU4_CC4_TC_STRM_Pos)
\r
3600 #define CCU4_CC4_TC_SCE_Pos (11U)
\r
3601 #define CCU4_CC4_TC_SCE_Msk (0x00000001U << CCU4_CC4_TC_SCE_Pos)
\r
3603 #define CCU4_CC4_TC_CCS_Pos (12U)
\r
3604 #define CCU4_CC4_TC_CCS_Msk (0x00000001U << CCU4_CC4_TC_CCS_Pos)
\r
3606 #define CCU4_CC4_TC_DITHE_Pos (13U)
\r
3607 #define CCU4_CC4_TC_DITHE_Msk (0x00000003U << CCU4_CC4_TC_DITHE_Pos)
\r
3609 #define CCU4_CC4_TC_DIM_Pos (15U)
\r
3610 #define CCU4_CC4_TC_DIM_Msk (0x00000001U << CCU4_CC4_TC_DIM_Pos)
\r
3612 #define CCU4_CC4_TC_FPE_Pos (16U)
\r
3613 #define CCU4_CC4_TC_FPE_Msk (0x00000001U << CCU4_CC4_TC_FPE_Pos)
\r
3615 #define CCU4_CC4_TC_TRAPE_Pos (17U)
\r
3616 #define CCU4_CC4_TC_TRAPE_Msk (0x00000001U << CCU4_CC4_TC_TRAPE_Pos)
\r
3618 #define CCU4_CC4_TC_TRPSE_Pos (21U)
\r
3619 #define CCU4_CC4_TC_TRPSE_Msk (0x00000001U << CCU4_CC4_TC_TRPSE_Pos)
\r
3621 #define CCU4_CC4_TC_TRPSW_Pos (22U)
\r
3622 #define CCU4_CC4_TC_TRPSW_Msk (0x00000001U << CCU4_CC4_TC_TRPSW_Pos)
\r
3624 #define CCU4_CC4_TC_EMS_Pos (23U)
\r
3625 #define CCU4_CC4_TC_EMS_Msk (0x00000001U << CCU4_CC4_TC_EMS_Pos)
\r
3627 #define CCU4_CC4_TC_EMT_Pos (24U)
\r
3628 #define CCU4_CC4_TC_EMT_Msk (0x00000001U << CCU4_CC4_TC_EMT_Pos)
\r
3630 #define CCU4_CC4_TC_MCME_Pos (25U)
\r
3631 #define CCU4_CC4_TC_MCME_Msk (0x00000001U << CCU4_CC4_TC_MCME_Pos)
\r
3633 /* CCU4_CC4_PSL = Passive Level Config*/
\r
3634 #define CCU4_CC4_PSL_PSL_Pos (0U)
\r
3635 #define CCU4_CC4_PSL_PSL_Msk (0x00000001U << CCU4_CC4_PSL_PSL_Pos)
\r
3637 /* CCU4_CC4_DIT = Dither Config*/
\r
3638 #define CCU4_CC4_DIT_DCV_Pos (0U)
\r
3639 #define CCU4_CC4_DIT_DCV_Msk (0x0000000FU << CCU4_CC4_DIT_DCV_Pos)
\r
3641 #define CCU4_CC4_DIT_DCNT_Pos (8U)
\r
3642 #define CCU4_CC4_DIT_DCNT_Msk (0x0000000FU << CCU4_CC4_DIT_DCNT_Pos)
\r
3644 /* CCU4_CC4_DITS = Dither Shadow Register*/
\r
3645 #define CCU4_CC4_DITS_DCVS_Pos (0U)
\r
3646 #define CCU4_CC4_DITS_DCVS_Msk (0x0000000FU << CCU4_CC4_DITS_DCVS_Pos)
\r
3648 /* CCU4_CC4_PSC = Prescaler Control*/
\r
3649 #define CCU4_CC4_PSC_PSIV_Pos (0U)
\r
3650 #define CCU4_CC4_PSC_PSIV_Msk (0x0000000FU << CCU4_CC4_PSC_PSIV_Pos)
\r
3652 /* CCU4_CC4_FPC = Floating Prescaler Control*/
\r
3653 #define CCU4_CC4_FPC_PCMP_Pos (0U)
\r
3654 #define CCU4_CC4_FPC_PCMP_Msk (0x0000000FU << CCU4_CC4_FPC_PCMP_Pos)
\r
3656 #define CCU4_CC4_FPC_PVAL_Pos (8U)
\r
3657 #define CCU4_CC4_FPC_PVAL_Msk (0x0000000FU << CCU4_CC4_FPC_PVAL_Pos)
\r
3659 /* CCU4_CC4_FPCS = Floating Prescaler Shadow*/
\r
3660 #define CCU4_CC4_FPCS_PCMP_Pos (0U)
\r
3661 #define CCU4_CC4_FPCS_PCMP_Msk (0x0000000FU << CCU4_CC4_FPCS_PCMP_Pos)
\r
3663 /* CCU4_CC4_PR = Timer Period Value*/
\r
3664 #define CCU4_CC4_PR_PR_Pos (0U)
\r
3665 #define CCU4_CC4_PR_PR_Msk (0x0000FFFFU << CCU4_CC4_PR_PR_Pos)
\r
3667 /* CCU4_CC4_PRS = Timer Shadow Period Value*/
\r
3668 #define CCU4_CC4_PRS_PRS_Pos (0U)
\r
3669 #define CCU4_CC4_PRS_PRS_Msk (0x0000FFFFU << CCU4_CC4_PRS_PRS_Pos)
\r
3671 /* CCU4_CC4_CR = Timer Compare Value*/
\r
3672 #define CCU4_CC4_CR_CR_Pos (0U)
\r
3673 #define CCU4_CC4_CR_CR_Msk (0x0000FFFFU << CCU4_CC4_CR_CR_Pos)
\r
3675 /* CCU4_CC4_CRS = Timer Shadow Compare Value*/
\r
3676 #define CCU4_CC4_CRS_CRS_Pos (0U)
\r
3677 #define CCU4_CC4_CRS_CRS_Msk (0x0000FFFFU << CCU4_CC4_CRS_CRS_Pos)
\r
3679 /* CCU4_CC4_TIMER = Timer Value*/
\r
3680 #define CCU4_CC4_TIMER_TVAL_Pos (0U)
\r
3681 #define CCU4_CC4_TIMER_TVAL_Msk (0x0000FFFFU << CCU4_CC4_TIMER_TVAL_Pos)
\r
3683 /* CCU4_CC4_C0V = Capture Register 0*/
\r
3684 #define CCU4_CC4_CV_CAPTV_Pos (0U)
\r
3685 #define CCU4_CC4_CV_CAPTV_Msk (0x0000FFFFU << CCU4_CC4_CV_CAPTV_Pos)
\r
3687 #define CCU4_CC4_CV_FPCV_Pos (16U)
\r
3688 #define CCU4_CC4_CV_FPCV_Msk (0x0000000FU << CCU4_CC4_CV_FPCV_Pos)
\r
3690 #define CCU4_CC4_CV_FFL_Pos (20U)
\r
3691 #define CCU4_CC4_CV_FFL_Msk (0x00000001U << CCU4_CC4_CV_FFL_Pos)
\r
3693 /* CCU4_CC4_INTS = Interrupt Status*/
\r
3694 #define CCU4_CC4_INTS_PMUS_Pos (0U)
\r
3695 #define CCU4_CC4_INTS_PMUS_Msk (0x00000001U << CCU4_CC4_INTS_PMUS_Pos)
\r
3697 #define CCU4_CC4_INTS_OMDS_Pos (1U)
\r
3698 #define CCU4_CC4_INTS_OMDS_Msk (0x00000001U << CCU4_CC4_INTS_OMDS_Pos)
\r
3700 #define CCU4_CC4_INTS_CMUS_Pos (2U)
\r
3701 #define CCU4_CC4_INTS_CMUS_Msk (0x00000001U << CCU4_CC4_INTS_CMUS_Pos)
\r
3703 #define CCU4_CC4_INTS_CMDS_Pos (3U)
\r
3704 #define CCU4_CC4_INTS_CMDS_Msk (0x00000001U << CCU4_CC4_INTS_CMDS_Pos)
\r
3706 #define CCU4_CC4_INTS_E0AS_Pos (8U)
\r
3707 #define CCU4_CC4_INTS_E0AS_Msk (0x00000001U << CCU4_CC4_INTS_E0AS_Pos)
\r
3709 #define CCU4_CC4_INTS_E1AS_Pos (9U)
\r
3710 #define CCU4_CC4_INTS_E1AS_Msk (0x00000001U << CCU4_CC4_INTS_E1AS_Pos)
\r
3712 #define CCU4_CC4_INTS_E2AS_Pos (10U)
\r
3713 #define CCU4_CC4_INTS_E2AS_Msk (0x00000001U << CCU4_CC4_INTS_E2AS_Pos)
\r
3715 #define CCU4_CC4_INTS_TRPF_Pos (11U)
\r
3716 #define CCU4_CC4_INTS_TRPF_Msk (0x00000001U << CCU4_CC4_INTS_TRPF_Pos)
\r
3718 /* CCU4_CC4_INTE = Interrupt Enable Control*/
\r
3719 #define CCU4_CC4_INTE_PME_Pos (0U)
\r
3720 #define CCU4_CC4_INTE_PME_Msk (0x00000001U << CCU4_CC4_INTE_PME_Pos)
\r
3722 #define CCU4_CC4_INTE_OME_Pos (1U)
\r
3723 #define CCU4_CC4_INTE_OME_Msk (0x00000001U << CCU4_CC4_INTE_OME_Pos)
\r
3725 #define CCU4_CC4_INTE_CMUE_Pos (2U)
\r
3726 #define CCU4_CC4_INTE_CMUE_Msk (0x00000001U << CCU4_CC4_INTE_CMUE_Pos)
\r
3728 #define CCU4_CC4_INTE_CMDE_Pos (3U)
\r
3729 #define CCU4_CC4_INTE_CMDE_Msk (0x00000001U << CCU4_CC4_INTE_CMDE_Pos)
\r
3731 #define CCU4_CC4_INTE_E0AE_Pos (8U)
\r
3732 #define CCU4_CC4_INTE_E0AE_Msk (0x00000001U << CCU4_CC4_INTE_E0AE_Pos)
\r
3734 #define CCU4_CC4_INTE_E1AE_Pos (9U)
\r
3735 #define CCU4_CC4_INTE_E1AE_Msk (0x00000001U << CCU4_CC4_INTE_E1AE_Pos)
\r
3737 #define CCU4_CC4_INTE_E2AE_Pos (10U)
\r
3738 #define CCU4_CC4_INTE_E2AE_Msk (0x00000001U << CCU4_CC4_INTE_E2AE_Pos)
\r
3740 /* CCU4_CC4_SRS = Service Request Selector*/
\r
3741 #define CCU4_CC4_SRS_POSR_Pos (0U)
\r
3742 #define CCU4_CC4_SRS_POSR_Msk (0x00000003U << CCU4_CC4_SRS_POSR_Pos)
\r
3744 #define CCU4_CC4_SRS_CMSR_Pos (2U)
\r
3745 #define CCU4_CC4_SRS_CMSR_Msk (0x00000003U << CCU4_CC4_SRS_CMSR_Pos)
\r
3747 #define CCU4_CC4_SRS_E0SR_Pos (8U)
\r
3748 #define CCU4_CC4_SRS_E0SR_Msk (0x00000003U << CCU4_CC4_SRS_E0SR_Pos)
\r
3750 #define CCU4_CC4_SRS_E1SR_Pos (10U)
\r
3751 #define CCU4_CC4_SRS_E1SR_Msk (0x00000003U << CCU4_CC4_SRS_E1SR_Pos)
\r
3753 #define CCU4_CC4_SRS_E2SR_Pos (12U)
\r
3754 #define CCU4_CC4_SRS_E2SR_Msk (0x00000003U << CCU4_CC4_SRS_E2SR_Pos)
\r
3756 /* CCU4_CC4_SWS = Interrupt Status Set*/
\r
3757 #define CCU4_CC4_SWS_SPM_Pos (0U)
\r
3758 #define CCU4_CC4_SWS_SPM_Msk (0x00000001U << CCU4_CC4_SWS_SPM_Pos)
\r
3760 #define CCU4_CC4_SWS_SOM_Pos (1U)
\r
3761 #define CCU4_CC4_SWS_SOM_Msk (0x00000001U << CCU4_CC4_SWS_SOM_Pos)
\r
3763 #define CCU4_CC4_SWS_SCMU_Pos (2U)
\r
3764 #define CCU4_CC4_SWS_SCMU_Msk (0x00000001U << CCU4_CC4_SWS_SCMU_Pos)
\r
3766 #define CCU4_CC4_SWS_SCMD_Pos (3U)
\r
3767 #define CCU4_CC4_SWS_SCMD_Msk (0x00000001U << CCU4_CC4_SWS_SCMD_Pos)
\r
3769 #define CCU4_CC4_SWS_SE0A_Pos (8U)
\r
3770 #define CCU4_CC4_SWS_SE0A_Msk (0x00000001U << CCU4_CC4_SWS_SE0A_Pos)
\r
3772 #define CCU4_CC4_SWS_SE1A_Pos (9U)
\r
3773 #define CCU4_CC4_SWS_SE1A_Msk (0x00000001U << CCU4_CC4_SWS_SE1A_Pos)
\r
3775 #define CCU4_CC4_SWS_SE2A_Pos (10U)
\r
3776 #define CCU4_CC4_SWS_SE2A_Msk (0x00000001U << CCU4_CC4_SWS_SE2A_Pos)
\r
3778 #define CCU4_CC4_SWS_STRPF_Pos (11U)
\r
3779 #define CCU4_CC4_SWS_STRPF_Msk (0x00000001U << CCU4_CC4_SWS_STRPF_Pos)
\r
3781 /* CCU4_CC4_SWR = Interrupt Status Clear*/
\r
3782 #define CCU4_CC4_SWR_RPM_Pos (0U)
\r
3783 #define CCU4_CC4_SWR_RPM_Msk (0x00000001U << CCU4_CC4_SWR_RPM_Pos)
\r
3785 #define CCU4_CC4_SWR_ROM_Pos (1U)
\r
3786 #define CCU4_CC4_SWR_ROM_Msk (0x00000001U << CCU4_CC4_SWR_ROM_Pos)
\r
3788 #define CCU4_CC4_SWR_RCMU_Pos (2U)
\r
3789 #define CCU4_CC4_SWR_RCMU_Msk (0x00000001U << CCU4_CC4_SWR_RCMU_Pos)
\r
3791 #define CCU4_CC4_SWR_RCMD_Pos (3U)
\r
3792 #define CCU4_CC4_SWR_RCMD_Msk (0x00000001U << CCU4_CC4_SWR_RCMD_Pos)
\r
3794 #define CCU4_CC4_SWR_RE0A_Pos (8U)
\r
3795 #define CCU4_CC4_SWR_RE0A_Msk (0x00000001U << CCU4_CC4_SWR_RE0A_Pos)
\r
3797 #define CCU4_CC4_SWR_RE1A_Pos (9U)
\r
3798 #define CCU4_CC4_SWR_RE1A_Msk (0x00000001U << CCU4_CC4_SWR_RE1A_Pos)
\r
3800 #define CCU4_CC4_SWR_RE2A_Pos (10U)
\r
3801 #define CCU4_CC4_SWR_RE2A_Msk (0x00000001U << CCU4_CC4_SWR_RE2A_Pos)
\r
3803 #define CCU4_CC4_SWR_RTRPF_Pos (11U)
\r
3804 #define CCU4_CC4_SWR_RTRPF_Msk (0x00000001U << CCU4_CC4_SWR_RTRPF_Pos)
\r
3808 /*** CCU8x Bit Fileds *******************/
\r
3809 /***************************************************************************/
\r
3812 /* CCU8_GCTRL = Global Control Register*/
\r
3813 #define CCU8_GCTRL_PRBC_Pos (0U)
\r
3814 #define CCU8_GCTRL_PRBC_Msk (0x00000007U << CCU8_GCTRL_PRBC_Pos)
\r
3816 #define CCU8_GCTRL_PCIS_Pos (4U)
\r
3817 #define CCU8_GCTRL_PCIS_Msk (0x00000003U << CCU8_GCTRL_PCIS_Pos)
\r
3819 #define CCU8_GCTRL_SUSCFG_Pos (8U)
\r
3820 #define CCU8_GCTRL_SUSCFG_Msk (0x00000003U << CCU8_GCTRL_SUSCFG_Pos)
\r
3822 #define CCU8_GCTRL_MSE0_Pos (10U)
\r
3823 #define CCU8_GCTRL_MSE0_Msk (0x00000001U << CCU8_GCTRL_MSE0_Pos)
\r
3825 #define CCU8_GCTRL_MSE1_Pos (11U)
\r
3826 #define CCU8_GCTRL_MSE1_Msk (0x00000001U << CCU8_GCTRL_MSE1_Pos)
\r
3828 #define CCU8_GCTRL_MSE2_Pos (12U)
\r
3829 #define CCU8_GCTRL_MSE2_Msk (0x00000001U << CCU8_GCTRL_MSE2_Pos)
\r
3831 #define CCU8_GCTRL_MSE3_Pos (13U)
\r
3832 #define CCU8_GCTRL_MSE3_Msk (0x00000001U << CCU8_GCTRL_MSE3_Pos)
\r
3834 #define CCU8_GCTRL_MSDE_Pos (14U)
\r
3835 #define CCU8_GCTRL_MSDE_Msk (0x00000003U << CCU8_GCTRL_MSDE_Pos)
\r
3837 /* CCU8_GSTAT = Global Status Register*/
\r
3838 #define CCU8_GSTAT_S0I_Pos (0U)
\r
3839 #define CCU8_GSTAT_S0I_Msk (0x00000001U << CCU8_GSTAT_S0I_Pos)
\r
3841 #define CCU8_GSTAT_S1I_Pos (1U)
\r
3842 #define CCU8_GSTAT_S1I_Msk (0x00000001U << CCU8_GSTAT_S1I_Pos)
\r
3844 #define CCU8_GSTAT_S2I_Pos (2U)
\r
3845 #define CCU8_GSTAT_S2I_Msk (0x00000001U << CCU8_GSTAT_S2I_Pos)
\r
3847 #define CCU8_GSTAT_S3I_Pos (3U)
\r
3848 #define CCU8_GSTAT_S3I_Msk (0x00000001U << CCU8_GSTAT_S3I_Pos)
\r
3850 #define CCU8_GSTAT_PRB_Pos (8U)
\r
3851 #define CCU8_GSTAT_PRB_Msk (0x00000001U << CCU8_GSTAT_PRB_Pos)
\r
3853 #define CCU8_GSTAT_PCRB_Pos (10U)
\r
3854 #define CCU8_GSTAT_PCRB_Msk (0x00000001U << CCU8_GSTAT_PCRB_Pos)
\r
3856 /* CCU8_GIDLS = Global Idle Set*/
\r
3857 #define CCU8_GIDLS_SS0I_Pos (0U)
\r
3858 #define CCU8_GIDLS_SS0I_Msk (0x00000001U << CCU8_GIDLS_SS0I_Pos)
\r
3860 #define CCU8_GIDLS_SS1I_Pos (1U)
\r
3861 #define CCU8_GIDLS_SS1I_Msk (0x00000001U << CCU8_GIDLS_SS1I_Pos)
\r
3863 #define CCU8_GIDLS_SS2I_Pos (2U)
\r
3864 #define CCU8_GIDLS_SS2I_Msk (0x00000001U << CCU8_GIDLS_SS2I_Pos)
\r
3866 #define CCU8_GIDLS_SS3I_Pos (3U)
\r
3867 #define CCU8_GIDLS_SS3I_Msk (0x00000001U << CCU8_GIDLS_SS3I_Pos)
\r
3869 #define CCU8_GIDLS_CPRB_Pos (8U)
\r
3870 #define CCU8_GIDLS_CPRB_Msk (0x00000001U << CCU8_GIDLS_CPRB_Pos)
\r
3872 #define CCU8_GIDLS_PSIC_Pos (9U)
\r
3873 #define CCU8_GIDLS_PSIC_Msk (0x00000001U << CCU8_GIDLS_PSIC_Pos)
\r
3875 #define CCU8_GIDLS_CPCH_Pos (10U)
\r
3876 #define CCU8_GIDLS_CPCH_Msk (0x00000001U << CCU8_GIDLS_CPCH_Pos)
\r
3878 /* CCU8_GIDLC = Global Idle Clear*/
\r
3879 #define CCU8_GIDLC_CS0I_Pos (0U)
\r
3880 #define CCU8_GIDLC_CS0I_Msk (0x00000001U << CCU8_GIDLC_CS0I_Pos)
\r
3882 #define CCU8_GIDLC_CS1I_Pos (1U)
\r
3883 #define CCU8_GIDLC_CS1I_Msk (0x00000001U << CCU8_GIDLC_CS1I_Pos)
\r
3885 #define CCU8_GIDLC_CS2I_Pos (2U)
\r
3886 #define CCU8_GIDLC_CS2I_Msk (0x00000001U << CCU8_GIDLC_CS2I_Pos)
\r
3888 #define CCU8_GIDLC_CS3I_Pos (3U)
\r
3889 #define CCU8_GIDLC_CS3I_Msk (0x00000001U << CCU8_GIDLC_CS3I_Pos)
\r
3891 #define CCU8_GIDLC_SPRB_Pos (8U)
\r
3892 #define CCU8_GIDLC_SPRB_Msk (0x00000001U << CCU8_GIDLC_SPRB_Pos)
\r
3894 #define CCU8_GIDLC_SPCH_Pos (10U)
\r
3895 #define CCU8_GIDLC_SPCH_Msk (0x00000001U << CCU8_GIDLC_SPCH_Pos)
\r
3897 /* CCU8_GCSS = Global Channel Set*/
\r
3898 #define CCU8_GCSS_S0SE_Pos (0U)
\r
3899 #define CCU8_GCSS_S0SE_Msk (0x00000001U << CCU8_GCSS_S0SE_Pos)
\r
3901 #define CCU8_GCSS_S0DSE_Pos (1U)
\r
3902 #define CCU8_GCSS_S0DSE_Msk (0x00000001U << CCU8_GCSS_S0DSE_Pos)
\r
3904 #define CCU8_GCSS_S0PSE_Pos (2U)
\r
3905 #define CCU8_GCSS_S0PSE_Msk (0x00000001U << CCU8_GCSS_S0PSE_Pos)
\r
3907 #define CCU8_GCSS_S1SE_Pos (4U)
\r
3908 #define CCU8_GCSS_S1SE_Msk (0x00000001U << CCU8_GCSS_S1SE_Pos)
\r
3910 #define CCU8_GCSS_S1DSE_Pos (5U)
\r
3911 #define CCU8_GCSS_S1DSE_Msk (0x00000001U << CCU8_GCSS_S1DSE_Pos)
\r
3913 #define CCU8_GCSS_S1PSE_Pos (6U)
\r
3914 #define CCU8_GCSS_S1PSE_Msk (0x00000001U << CCU8_GCSS_S1PSE_Pos)
\r
3916 #define CCU8_GCSS_S2SE_Pos (8U)
\r
3917 #define CCU8_GCSS_S2SE_Msk (0x00000001U << CCU8_GCSS_S2SE_Pos)
\r
3919 #define CCU8_GCSS_S2DSE_Pos (9U)
\r
3920 #define CCU8_GCSS_S2DSE_Msk (0x00000001U << CCU8_GCSS_S2DSE_Pos)
\r
3922 #define CCU8_GCSS_S2PSE_Pos (10U)
\r
3923 #define CCU8_GCSS_S2PSE_Msk (0x00000001U << CCU8_GCSS_S2PSE_Pos)
\r
3925 #define CCU8_GCSS_S3SE_Pos (12U)
\r
3926 #define CCU8_GCSS_S3SE_Msk (0x00000001U << CCU8_GCSS_S3SE_Pos)
\r
3928 #define CCU8_GCSS_S3DSE_Pos (13U)
\r
3929 #define CCU8_GCSS_S3DSE_Msk (0x00000001U << CCU8_GCSS_S3DSE_Pos)
\r
3931 #define CCU8_GCSS_S3PSE_Pos (14U)
\r
3932 #define CCU8_GCSS_S3PSE_Msk (0x00000001U << CCU8_GCSS_S3PSE_Pos)
\r
3934 #define CCU8_GCSS_S0ST1S_Pos (16U)
\r
3935 #define CCU8_GCSS_S0ST1S_Msk (0x00000001U << CCU8_GCSS_S0ST1S_Pos)
\r
3937 #define CCU8_GCSS_S1ST1S_Pos (17U)
\r
3938 #define CCU8_GCSS_S1ST1S_Msk (0x00000001U << CCU8_GCSS_S1ST1S_Pos)
\r
3940 #define CCU8_GCSS_S2ST1S_Pos (18U)
\r
3941 #define CCU8_GCSS_S2ST1S_Msk (0x00000001U << CCU8_GCSS_S2ST1S_Pos)
\r
3943 #define CCU8_GCSS_S3ST1S_Pos (19U)
\r
3944 #define CCU8_GCSS_S3ST1S_Msk (0x00000001U << CCU8_GCSS_S3ST1S_Pos)
\r
3946 #define CCU8_GCSS_S0ST2S_Pos (20U)
\r
3947 #define CCU8_GCSS_S0ST2S_Msk (0x00000001U << CCU8_GCSS_S0ST2S_Pos)
\r
3949 #define CCU8_GCSS_S1ST2S_Pos (21U)
\r
3950 #define CCU8_GCSS_S1ST2S_Msk (0x00000001U << CCU8_GCSS_S1ST2S_Pos)
\r
3952 #define CCU8_GCSS_S2ST2S_Pos (22U)
\r
3953 #define CCU8_GCSS_S2ST2S_Msk (0x00000001U << CCU8_GCSS_S2ST2S_Pos)
\r
3955 #define CCU8_GCSS_S3ST2S_Pos (23U)
\r
3956 #define CCU8_GCSS_S3ST2S_Msk (0x00000001U << CCU8_GCSS_S3ST2S_Pos)
\r
3958 /* CCU8_GCSC = Global Channel Clear*/
\r
3959 #define CCU8_GCSC_S0SC_Pos (0U)
\r
3960 #define CCU8_GCSC_S0SC_Msk (0x00000001U << CCU8_GCSC_S0SC_Pos)
\r
3962 #define CCU8_GCSC_S0DSC_Pos (1U)
\r
3963 #define CCU8_GCSC_S0DSC_Msk (0x00000001U << CCU8_GCSC_S0DSC_Pos)
\r
3965 #define CCU8_GCSC_S0PSC_Pos (2U)
\r
3966 #define CCU8_GCSC_S0PSC_Msk (0x00000001U << CCU8_GCSC_S0PSC_Pos)
\r
3968 #define CCU8_GCSC_S1SC_Pos (4U)
\r
3969 #define CCU8_GCSC_S1SC_Msk (0x00000001U << CCU8_GCSC_S1SC_Pos)
\r
3971 #define CCU8_GCSC_S1DSC_Pos (5U)
\r
3972 #define CCU8_GCSC_S1DSC_Msk (0x00000001U << CCU8_GCSC_S1DSC_Pos)
\r
3974 #define CCU8_GCSC_S1PSC_Pos (6U)
\r
3975 #define CCU8_GCSC_S1PSC_Msk (0x00000001U << CCU8_GCSC_S1PSC_Pos)
\r
3977 #define CCU8_GCSC_S2SC_Pos (8U)
\r
3978 #define CCU8_GCSC_S2SC_Msk (0x00000001U << CCU8_GCSC_S2SC_Pos)
\r
3980 #define CCU8_GCSC_S2DSC_Pos (9U)
\r
3981 #define CCU8_GCSC_S2DSC_Msk (0x00000001U << CCU8_GCSC_S2DSC_Pos)
\r
3983 #define CCU8_GCSC_S2PSC_Pos (10U)
\r
3984 #define CCU8_GCSC_S2PSC_Msk (0x00000001U << CCU8_GCSC_S2PSC_Pos)
\r
3986 #define CCU8_GCSC_S3SC_Pos (12U)
\r
3987 #define CCU8_GCSC_S3SC_Msk (0x00000001U << CCU8_GCSC_S3SC_Pos)
\r
3989 #define CCU8_GCSC_S3DSC_Pos (13U)
\r
3990 #define CCU8_GCSC_S3DSC_Msk (0x00000001U << CCU8_GCSC_S3DSC_Pos)
\r
3992 #define CCU8_GCSC_S3PSC_Pos (14U)
\r
3993 #define CCU8_GCSC_S3PSC_Msk (0x00000001U << CCU8_GCSC_S3PSC_Pos)
\r
3995 #define CCU8_GCSC_S0ST1C_Pos (16U)
\r
3996 #define CCU8_GCSC_S0ST1C_Msk (0x00000001U << CCU8_GCSC_S0ST1C_Pos)
\r
3998 #define CCU8_GCSC_S1ST1C_Pos (17U)
\r
3999 #define CCU8_GCSC_S1ST1C_Msk (0x00000001U << CCU8_GCSC_S1ST1C_Pos)
\r
4001 #define CCU8_GCSC_S2ST1C_Pos (18U)
\r
4002 #define CCU8_GCSC_S2ST1C_Msk (0x00000001U << CCU8_GCSC_S2ST1C_Pos)
\r
4004 #define CCU8_GCSC_S3ST1C_Pos (19U)
\r
4005 #define CCU8_GCSC_S3ST1C_Msk (0x00000001U << CCU8_GCSC_S3ST1C_Pos)
\r
4007 #define CCU8_GCSC_S0ST2C_Pos (20U)
\r
4008 #define CCU8_GCSC_S0ST2C_Msk (0x00000001U << CCU8_GCSC_S0ST2C_Pos)
\r
4010 #define CCU8_GCSC_S1ST2C_Pos (21U)
\r
4011 #define CCU8_GCSC_S1ST2C_Msk (0x00000001U << CCU8_GCSC_S1ST2C_Pos)
\r
4013 #define CCU8_GCSC_S2ST2C_Pos (22U)
\r
4014 #define CCU8_GCSC_S2ST2C_Msk (0x00000001U << CCU8_GCSC_S2ST2C_Pos)
\r
4016 #define CCU8_GCSC_S3ST2C_Pos (23U)
\r
4017 #define CCU8_GCSC_S3ST2C_Msk (0x00000001U << CCU8_GCSC_S3ST2C_Pos)
\r
4019 /* CCU8_GCST = Global Channel status*/
\r
4020 #define CCU8_GCST_S0SS_Pos (0U)
\r
4021 #define CCU8_GCST_S0SS_Msk (0x00000001U << CCU8_GCST_S0SS_Pos)
\r
4023 #define CCU8_GCST_S0DSS_Pos (1U)
\r
4024 #define CCU8_GCST_S0DSS_Msk (0x00000001U << CCU8_GCST_S0DSS_Pos)
\r
4026 #define CCU8_GCST_S0PSS_Pos (2U)
\r
4027 #define CCU8_GCST_S0PSS_Msk (0x00000001U << CCU8_GCST_S0PSS_Pos)
\r
4029 #define CCU8_GCST_S1SS_Pos (4U)
\r
4030 #define CCU8_GCST_S1SS_Msk (0x00000001U << CCU8_GCST_S1SS_Pos)
\r
4032 #define CCU8_GCST_S1DSS_Pos (5U)
\r
4033 #define CCU8_GCST_S1DSS_Msk (0x00000001U << CCU8_GCST_S1DSS_Pos)
\r
4035 #define CCU8_GCST_S1PSS_Pos (6U)
\r
4036 #define CCU8_GCST_S1PSS_Msk (0x00000001U << CCU8_GCST_S1PSS_Pos)
\r
4038 #define CCU8_GCST_S2SS_Pos (8U)
\r
4039 #define CCU8_GCST_S2SS_Msk (0x00000001U << CCU8_GCST_S2SS_Pos)
\r
4041 #define CCU8_GCST_S2DSS_Pos (9U)
\r
4042 #define CCU8_GCST_S2DSS_Msk (0x00000001U << CCU8_GCST_S2DSS_Pos)
\r
4044 #define CCU8_GCST_S2PSS_Pos (10U)
\r
4045 #define CCU8_GCST_S2PSS_Msk (0x00000001U << CCU8_GCST_S2PSS_Pos)
\r
4047 #define CCU8_GCST_S3SS_Pos (12U)
\r
4048 #define CCU8_GCST_S3SS_Msk (0x00000001U << CCU8_GCST_S3SS_Pos)
\r
4050 #define CCU8_GCST_S3DSS_Pos (13U)
\r
4051 #define CCU8_GCST_S3DSS_Msk (0x00000001U << CCU8_GCST_S3DSS_Pos)
\r
4053 #define CCU8_GCST_S3PSS_Pos (14U)
\r
4054 #define CCU8_GCST_S3PSS_Msk (0x00000001U << CCU8_GCST_S3PSS_Pos)
\r
4056 #define CCU8_GCST_CC80ST1_Pos (16U)
\r
4057 #define CCU8_GCST_CC80ST1_Msk (0x00000001U << CCU8_GCST_CC80ST1_Pos)
\r
4059 #define CCU8_GCST_CC81ST1_Pos (17U)
\r
4060 #define CCU8_GCST_CC81ST1_Msk (0x00000001U << CCU8_GCST_CC81ST1_Pos)
\r
4062 #define CCU8_GCST_CC82ST1_Pos (18U)
\r
4063 #define CCU8_GCST_CC82ST1_Msk (0x00000001U << CCU8_GCST_CC82ST1_Pos)
\r
4065 #define CCU8_GCST_CC83ST1_Pos (19U)
\r
4066 #define CCU8_GCST_CC83ST1_Msk (0x00000001U << CCU8_GCST_CC83ST1_Pos)
\r
4068 #define CCU8_GCST_CC80ST2_Pos (20U)
\r
4069 #define CCU8_GCST_CC80ST2_Msk (0x00000001U << CCU8_GCST_CC80ST2_Pos)
\r
4071 #define CCU8_GCST_CC81ST2_Pos (21U)
\r
4072 #define CCU8_GCST_CC81ST2_Msk (0x00000001U << CCU8_GCST_CC81ST2_Pos)
\r
4074 #define CCU8_GCST_CC82ST2_Pos (22U)
\r
4075 #define CCU8_GCST_CC82ST2_Msk (0x00000001U << CCU8_GCST_CC82ST2_Pos)
\r
4077 #define CCU8_GCST_CC83ST2_Pos (23U)
\r
4078 #define CCU8_GCST_CC83ST2_Msk (0x00000001U << CCU8_GCST_CC83ST2_Pos)
\r
4080 /* CCU8_GPCHK = Parity Checker Configuration*/
\r
4081 #define CCU8_GPCHK_PASE_Pos (0U)
\r
4082 #define CCU8_GPCHK_PASE_Msk (0x00000001U << CCU8_GPCHK_PASE_Pos)
\r
4084 #define CCU8_GPCHK_PACS_Pos (1U)
\r
4085 #define CCU8_GPCHK_PACS_Msk (0x00000003U << CCU8_GPCHK_PACS_Pos)
\r
4087 #define CCU8_GPCHK_PISEL_Pos (3U)
\r
4088 #define CCU8_GPCHK_PISEL_Msk (0x00000003U << CCU8_GPCHK_PISEL_Pos)
\r
4090 #define CCU8_GPCHK_PCDS_Pos (5U)
\r
4091 #define CCU8_GPCHK_PCDS_Msk (0x00000003U << CCU8_GPCHK_PCDS_Pos)
\r
4093 #define CCU8_GPCHK_PCTS_Pos (7U)
\r
4094 #define CCU8_GPCHK_PCTS_Msk (0x00000001U << CCU8_GPCHK_PCTS_Pos)
\r
4096 #define CCU8_GPCHK_PCST_Pos (15U)
\r
4097 #define CCU8_GPCHK_PCST_Msk (0x00000001U << CCU8_GPCHK_PCST_Pos)
\r
4099 #define CCU8_GPCHK_PCSEL0_Pos (16U)
\r
4100 #define CCU8_GPCHK_PCSEL0_Msk (0x0000000FU << CCU8_GPCHK_PCSEL0_Pos)
\r
4102 #define CCU8_GPCHK_PCSEL1_Pos (20U)
\r
4103 #define CCU8_GPCHK_PCSEL1_Msk (0x0000000FU << CCU8_GPCHK_PCSEL1_Pos)
\r
4105 #define CCU8_GPCHK_PCSEL2_Pos (24U)
\r
4106 #define CCU8_GPCHK_PCSEL2_Msk (0x0000000FU << CCU8_GPCHK_PCSEL2_Pos)
\r
4108 #define CCU8_GPCHK_PCSEL3_Pos (28U)
\r
4109 #define CCU8_GPCHK_PCSEL3_Msk (0x0000000FU << CCU8_GPCHK_PCSEL3_Pos)
\r
4111 /* CCU8_ECRD = Extended Capture Mode Read*/
\r
4112 #define CCU8_ECRD_CAPV_Pos (0U)
\r
4113 #define CCU8_ECRD_CAPV_Msk (0x0000FFFFU << CCU8_ECRD_CAPV_Pos)
\r
4115 #define CCU8_ECRD_FPCV_Pos (16U)
\r
4116 #define CCU8_ECRD_FPCV_Msk (0x0000000FU << CCU8_ECRD_FPCV_Pos)
\r
4118 #define CCU8_ECRD_SPTR_Pos (20U)
\r
4119 #define CCU8_ECRD_SPTR_Msk (0x00000003U << CCU8_ECRD_SPTR_Pos)
\r
4121 #define CCU8_ECRD_VPTR_Pos (22U)
\r
4122 #define CCU8_ECRD_VPTR_Msk (0x00000003U << CCU8_ECRD_VPTR_Pos)
\r
4124 #define CCU8_ECRD_FFL_Pos (24U)
\r
4125 #define CCU8_ECRD_FFL_Msk (0x00000001U << CCU8_ECRD_FFL_Pos)
\r
4127 /* CCU8_MIDR = Module Identification*/
\r
4128 #define CCU8_MIDR_MODR_Pos (0U)
\r
4129 #define CCU8_MIDR_MODR_Msk (0x000000FFU << CCU8_MIDR_MODR_Pos)
\r
4131 #define CCU8_MIDR_MODT_Pos (8U)
\r
4132 #define CCU8_MIDR_MODT_Msk (0x000000FFU << CCU8_MIDR_MODT_Pos)
\r
4134 #define CCU8_MIDR_MODN_Pos (16U)
\r
4135 #define CCU8_MIDR_MODN_Msk (0x0000FFFFU << CCU8_MIDR_MODN_Pos)
\r
4137 /* CCU8_CC8_INS = Input Selector Configuration*/
\r
4138 #define CCU8_CC8_INS_EV0IS_Pos (0U)
\r
4139 #define CCU8_CC8_INS_EV0IS_Msk (0x0000000FU << CCU8_CC8_INS_EV0IS_Pos)
\r
4141 #define CCU8_CC8_INS_EV1IS_Pos (4U)
\r
4142 #define CCU8_CC8_INS_EV1IS_Msk (0x0000000FU << CCU8_CC8_INS_EV1IS_Pos)
\r
4144 #define CCU8_CC8_INS_EV2S_Pos (8U)
\r
4145 #define CCU8_CC8_INS_EV2S_Msk (0x0000000FU << CCU8_CC8_INS_EV2S_Pos)
\r
4147 #define CCU8_CC8_INS_EV0EM_Pos (16U)
\r
4148 #define CCU8_CC8_INS_EV0EM_Msk (0x00000003U << CCU8_CC8_INS_EV0EM_Pos)
\r
4150 #define CCU8_CC8_INS_EV1EM_Pos (18U)
\r
4151 #define CCU8_CC8_INS_EV1EM_Msk (0x00000003U << CCU8_CC8_INS_EV1EM_Pos)
\r
4153 #define CCU8_CC8_INS_EV2EM_Pos (20U)
\r
4154 #define CCU8_CC8_INS_EV2EM_Msk (0x00000003U << CCU8_CC8_INS_EV2EM_Pos)
\r
4156 #define CCU8_CC8_INS_EV0LM_Pos (22U)
\r
4157 #define CCU8_CC8_INS_EV0LM_Msk (0x00000001U << CCU8_CC8_INS_EV0LM_Pos)
\r
4159 #define CCU8_CC8_INS_EV1LM_Pos (23U)
\r
4160 #define CCU8_CC8_INS_EV1LM_Msk (0x00000001U << CCU8_CC8_INS_EV1LM_Pos)
\r
4162 #define CCU8_CC8_INS_EV2LM_Pos (24U)
\r
4163 #define CCU8_CC8_INS_EV2LM_Msk (0x00000001U << CCU8_CC8_INS_EV2LM_Pos)
\r
4165 #define CCU8_CC8_INS_LPF0M_Pos (25U)
\r
4166 #define CCU8_CC8_INS_LPF0M_Msk (0x00000003U << CCU8_CC8_INS_LPF0M_Pos)
\r
4168 #define CCU8_CC8_INS_LPF1M_Pos (27U)
\r
4169 #define CCU8_CC8_INS_LPF1M_Msk (0x00000003U << CCU8_CC8_INS_LPF1M_Pos)
\r
4171 #define CCU8_CC8_INS_LPF2M_Pos (29U)
\r
4172 #define CCU8_CC8_INS_LPF2M_Msk (0x00000003U << CCU8_CC8_INS_LPF2M_Pos)
\r
4174 /* CCU8_CC8_CMC = Connection Matrix Control*/
\r
4175 #define CCU8_CC8_CMC_STRTS_Pos (0U)
\r
4176 #define CCU8_CC8_CMC_STRTS_Msk (0x00000003U << CCU8_CC8_CMC_STRTS_Pos)
\r
4178 #define CCU8_CC8_CMC_ENDS_Pos (2U)
\r
4179 #define CCU8_CC8_CMC_ENDS_Msk (0x00000003U << CCU8_CC8_CMC_ENDS_Pos)
\r
4181 #define CCU8_CC8_CMC_CAP0S_Pos (4U)
\r
4182 #define CCU8_CC8_CMC_CAP0S_Msk (0x00000003U << CCU8_CC8_CMC_CAP0S_Pos)
\r
4184 #define CCU8_CC8_CMC_CAP1S_Pos (6U)
\r
4185 #define CCU8_CC8_CMC_CAP1S_Msk (0x00000003U << CCU8_CC8_CMC_CAP1S_Pos)
\r
4187 #define CCU8_CC8_CMC_GATES_Pos (8U)
\r
4188 #define CCU8_CC8_CMC_GATES_Msk (0x00000003U << CCU8_CC8_CMC_GATES_Pos)
\r
4190 #define CCU8_CC8_CMC_UDS_Pos (10U)
\r
4191 #define CCU8_CC8_CMC_UDS_Msk (0x00000003U << CCU8_CC8_CMC_UDS_Pos)
\r
4193 #define CCU8_CC8_CMC_LDS_Pos (12U)
\r
4194 #define CCU8_CC8_CMC_LDS_Msk (0x00000003U << CCU8_CC8_CMC_LDS_Pos)
\r
4196 #define CCU8_CC8_CMC_CNTS_Pos (14U)
\r
4197 #define CCU8_CC8_CMC_CNTS_Msk (0x00000003U << CCU8_CC8_CMC_CNTS_Pos)
\r
4199 #define CCU8_CC8_CMC_OFS_Pos (16U)
\r
4200 #define CCU8_CC8_CMC_OFS_Msk (0x00000001U << CCU8_CC8_CMC_OFS_Pos)
\r
4202 #define CCU8_CC8_CMC_TS_Pos (17U)
\r
4203 #define CCU8_CC8_CMC_TS_Msk (0x00000001U << CCU8_CC8_CMC_TS_Pos)
\r
4205 #define CCU8_CC8_CMC_MOS_Pos (18U)
\r
4206 #define CCU8_CC8_CMC_MOS_Msk (0x00000003U << CCU8_CC8_CMC_MOS_Pos)
\r
4208 #define CCU8_CC8_CMC_TCE_Pos (20U)
\r
4209 #define CCU8_CC8_CMC_TCE_Msk (0x00000001U << CCU8_CC8_CMC_TCE_Pos)
\r
4211 /* CCU8_CC8_TCST = Slice Timer Status*/
\r
4212 #define CCU8_CC8_TCST_TRB_Pos (0U)
\r
4213 #define CCU8_CC8_TCST_TRB_Msk (0x00000001U << CCU8_CC8_TCST_TRB_Pos)
\r
4215 #define CCU8_CC8_TCST_CDIR_Pos (1U)
\r
4216 #define CCU8_CC8_TCST_CDIR_Msk (0x00000001U << CCU8_CC8_TCST_CDIR_Pos)
\r
4218 #define CCU8_CC8_TCST_DTR1_Pos (3U)
\r
4219 #define CCU8_CC8_TCST_DTR1_Msk (0x00000001U << CCU8_CC8_TCST_DTR1_Pos)
\r
4221 #define CCU8_CC8_TCST_DTR2_Pos (4U)
\r
4222 #define CCU8_CC8_TCST_DTR2_Msk (0x00000001U << CCU8_CC8_TCST_DTR2_Pos)
\r
4224 /* CCU8_CC8_TCSET = Slice Timer Run Set*/
\r
4225 #define CCU8_CC8_TCSET_TRBS_Pos (0U)
\r
4226 #define CCU8_CC8_TCSET_TRBS_Msk (0x00000001U << CCU8_CC8_TCSET_TRBS_Pos)
\r
4228 /* CCU8_CC8_TCCLR = Slice Timer Clear*/
\r
4229 #define CCU8_CC8_TCCLR_TRBC_Pos (0U)
\r
4230 #define CCU8_CC8_TCCLR_TRBC_Msk (0x00000001U << CCU8_CC8_TCCLR_TRBC_Pos)
\r
4232 #define CCU8_CC8_TCCLR_TCC_Pos (1U)
\r
4233 #define CCU8_CC8_TCCLR_TCC_Msk (0x00000001U << CCU8_CC8_TCCLR_TCC_Pos)
\r
4235 #define CCU8_CC8_TCCLR_DITC_Pos (2U)
\r
4236 #define CCU8_CC8_TCCLR_DITC_Msk (0x00000001U << CCU8_CC8_TCCLR_DITC_Pos)
\r
4238 #define CCU8_CC8_TCCLR_DTC1C_Pos (3U)
\r
4239 #define CCU8_CC8_TCCLR_DTC1C_Msk (0x00000001U << CCU8_CC8_TCCLR_DTC1C_Pos)
\r
4241 #define CCU8_CC8_TCCLR_DTC2C_Pos (4U)
\r
4242 #define CCU8_CC8_TCCLR_DTC2C_Msk (0x00000001U << CCU8_CC8_TCCLR_DTC2C_Pos)
\r
4244 /* CCU8_CC8_TC = Slice Timer Control*/
\r
4245 #define CCU8_CC8_TC_TCM_Pos (0U)
\r
4246 #define CCU8_CC8_TC_TCM_Msk (0x00000001U << CCU8_CC8_TC_TCM_Pos)
\r
4248 #define CCU8_CC8_TC_TSSM_Pos (1U)
\r
4249 #define CCU8_CC8_TC_TSSM_Msk (0x00000001U << CCU8_CC8_TC_TSSM_Pos)
\r
4251 #define CCU8_CC8_TC_CLST_Pos (2U)
\r
4252 #define CCU8_CC8_TC_CLST_Msk (0x00000001U << CCU8_CC8_TC_CLST_Pos)
\r
4254 #define CCU8_CC8_TC_CMOD_Pos (3U)
\r
4255 #define CCU8_CC8_TC_CMOD_Msk (0x00000001U << CCU8_CC8_TC_CMOD_Pos)
\r
4257 #define CCU8_CC8_TC_ECM_Pos (4U)
\r
4258 #define CCU8_CC8_TC_ECM_Msk (0x00000001U << CCU8_CC8_TC_ECM_Pos)
\r
4260 #define CCU8_CC8_TC_CAPC_Pos (5U)
\r
4261 #define CCU8_CC8_TC_CAPC_Msk (0x00000003U << CCU8_CC8_TC_CAPC_Pos)
\r
4263 #define CCU8_CC8_TC_TLS_Pos (7U)
\r
4264 #define CCU8_CC8_TC_TLS_Msk (0x00000001U << CCU8_CC8_TC_TLS_Pos)
\r
4266 #define CCU8_CC8_TC_ENDM_Pos (8U)
\r
4267 #define CCU8_CC8_TC_ENDM_Msk (0x00000003U << CCU8_CC8_TC_ENDM_Pos)
\r
4269 #define CCU8_CC8_TC_STRM_Pos (10U)
\r
4270 #define CCU8_CC8_TC_STRM_Msk (0x00000001U << CCU8_CC8_TC_STRM_Pos)
\r
4272 #define CCU8_CC8_TC_SCE_Pos (11U)
\r
4273 #define CCU8_CC8_TC_SCE_Msk (0x00000001U << CCU8_CC8_TC_SCE_Pos)
\r
4275 #define CCU8_CC8_TC_CCS_Pos (12U)
\r
4276 #define CCU8_CC8_TC_CCS_Msk (0x00000001U << CCU8_CC8_TC_CCS_Pos)
\r
4278 #define CCU8_CC8_TC_DITHE_Pos (13U)
\r
4279 #define CCU8_CC8_TC_DITHE_Msk (0x00000003U << CCU8_CC8_TC_DITHE_Pos)
\r
4281 #define CCU8_CC8_TC_DIM_Pos (15U)
\r
4282 #define CCU8_CC8_TC_DIM_Msk (0x00000001U << CCU8_CC8_TC_DIM_Pos)
\r
4284 #define CCU8_CC8_TC_FPE_Pos (16U)
\r
4285 #define CCU8_CC8_TC_FPE_Msk (0x00000001U << CCU8_CC8_TC_FPE_Pos)
\r
4287 #define CCU8_CC8_TC_TRAPE0_Pos (17U)
\r
4288 #define CCU8_CC8_TC_TRAPE0_Msk (0x00000001U << CCU8_CC8_TC_TRAPE0_Pos)
\r
4290 #define CCU8_CC8_TC_TRAPE1_Pos (18U)
\r
4291 #define CCU8_CC8_TC_TRAPE1_Msk (0x00000001U << CCU8_CC8_TC_TRAPE1_Pos)
\r
4293 #define CCU8_CC8_TC_TRAPE2_Pos (19U)
\r
4294 #define CCU8_CC8_TC_TRAPE2_Msk (0x00000001U << CCU8_CC8_TC_TRAPE2_Pos)
\r
4296 #define CCU8_CC8_TC_TRAPE3_Pos (20U)
\r
4297 #define CCU8_CC8_TC_TRAPE3_Msk (0x00000001U << CCU8_CC8_TC_TRAPE3_Pos)
\r
4299 #define CCU8_CC8_TC_TRPSE_Pos (21U)
\r
4300 #define CCU8_CC8_TC_TRPSE_Msk (0x00000001U << CCU8_CC8_TC_TRPSE_Pos)
\r
4302 #define CCU8_CC8_TC_TRPSW_Pos (22U)
\r
4303 #define CCU8_CC8_TC_TRPSW_Msk (0x00000001U << CCU8_CC8_TC_TRPSW_Pos)
\r
4305 #define CCU8_CC8_TC_EMS_Pos (23U)
\r
4306 #define CCU8_CC8_TC_EMS_Msk (0x00000001U << CCU8_CC8_TC_EMS_Pos)
\r
4308 #define CCU8_CC8_TC_EMT_Pos (24U)
\r
4309 #define CCU8_CC8_TC_EMT_Msk (0x00000001U << CCU8_CC8_TC_EMT_Pos)
\r
4311 #define CCU8_CC8_TC_MCME1_Pos (25U)
\r
4312 #define CCU8_CC8_TC_MCME1_Msk (0x00000001U << CCU8_CC8_TC_MCME1_Pos)
\r
4314 #define CCU8_CC8_TC_MCME2_Pos (26U)
\r
4315 #define CCU8_CC8_TC_MCME2_Msk (0x00000001U << CCU8_CC8_TC_MCME2_Pos)
\r
4317 #define CCU8_CC8_TC_EME_Pos (27U)
\r
4318 #define CCU8_CC8_TC_EME_Msk (0x00000003U << CCU8_CC8_TC_EME_Pos)
\r
4320 #define CCU8_CC8_TC_STOS_Pos (29U)
\r
4321 #define CCU8_CC8_TC_STOS_Msk (0x00000003U << CCU8_CC8_TC_STOS_Pos)
\r
4323 /* CCU8_CC8_PSL = Passive Level Config*/
\r
4324 #define CCU8_CC8_PSL_PSL11_Pos (0U)
\r
4325 #define CCU8_CC8_PSL_PSL11_Msk (0x00000001U << CCU8_CC8_PSL_PSL11_Pos)
\r
4327 #define CCU8_CC8_PSL_PSL12_Pos (1U)
\r
4328 #define CCU8_CC8_PSL_PSL12_Msk (0x00000001U << CCU8_CC8_PSL_PSL12_Pos)
\r
4330 #define CCU8_CC8_PSL_PSL21_Pos (2U)
\r
4331 #define CCU8_CC8_PSL_PSL21_Msk (0x00000001U << CCU8_CC8_PSL_PSL21_Pos)
\r
4333 #define CCU8_CC8_PSL_PSL22_Pos (3U)
\r
4334 #define CCU8_CC8_PSL_PSL22_Msk (0x00000001U << CCU8_CC8_PSL_PSL22_Pos)
\r
4336 /* CCU8_CC8_DIT = Dither Config*/
\r
4337 #define CCU8_CC8_DIT_DCV_Pos (0U)
\r
4338 #define CCU8_CC8_DIT_DCV_Msk (0x0000000FU << CCU8_CC8_DIT_DCV_Pos)
\r
4340 #define CCU8_CC8_DIT_DCNT_Pos (8U)
\r
4341 #define CCU8_CC8_DIT_DCNT_Msk (0x0000000FU << CCU8_CC8_DIT_DCNT_Pos)
\r
4343 /* CCU8_CC8_DITS = Dither Shadow Register*/
\r
4344 #define CCU8_CC8_DITS_DCVS_Pos (0U)
\r
4345 #define CCU8_CC8_DITS_DCVS_Msk (0x0000000FU << CCU8_CC8_DITS_DCVS_Pos)
\r
4347 /* CCU8_CC8_PSC = Prescaler Control*/
\r
4348 #define CCU8_CC8_PSC_PSIV_Pos (0U)
\r
4349 #define CCU8_CC8_PSC_PSIV_Msk (0x0000000FU << CCU8_CC8_PSC_PSIV_Pos)
\r
4351 /* CCU8_CC8_FPC = Floating Prescaler Control*/
\r
4352 #define CCU8_CC8_FPC_PCMP_Pos (0U)
\r
4353 #define CCU8_CC8_FPC_PCMP_Msk (0x0000000FU << CCU8_CC8_FPC_PCMP_Pos)
\r
4355 #define CCU8_CC8_FPC_PVAL_Pos (8U)
\r
4356 #define CCU8_CC8_FPC_PVAL_Msk (0x0000000FU << CCU8_CC8_FPC_PVAL_Pos)
\r
4358 /* CCU8_CC8_FPCS = Floating Prescaler Shadow*/
\r
4359 #define CCU8_CC8_FPCS_PCMP_Pos (0U)
\r
4360 #define CCU8_CC8_FPCS_PCMP_Msk (0x0000000FU << CCU8_CC8_FPCS_PCMP_Pos)
\r
4362 /* CCU8_CC8_PR = Timer Period Value*/
\r
4363 #define CCU8_CC8_PR_PR_Pos (0U)
\r
4364 #define CCU8_CC8_PR_PR_Msk (0x0000FFFFU << CCU8_CC8_PR_PR_Pos)
\r
4366 /* CCU8_CC8_PRS = Timer Shadow Period Value*/
\r
4367 #define CCU8_CC8_PRS_PRS_Pos (0U)
\r
4368 #define CCU8_CC8_PRS_PRS_Msk (0x0000FFFFU << CCU8_CC8_PRS_PRS_Pos)
\r
4370 /* CCU8_CC8_CR1 = Channel 1 Compare Value*/
\r
4371 #define CCU8_CC8_CR1_CR1_Pos (0U)
\r
4372 #define CCU8_CC8_CR1_CR1_Msk (0x0000FFFFU << CCU8_CC8_CR1_CR1_Pos)
\r
4374 /* CCU8_CC8_CR1S = Channel 1 Compare Shadow Value*/
\r
4375 #define CCU8_CC8_CR1S_CR1S_Pos (0U)
\r
4376 #define CCU8_CC8_CR1S_CR1S_Msk (0x0000FFFFU << CCU8_CC8_CR1S_CR1S_Pos)
\r
4378 /* CCU8_CC8_CR2 = Channel 2 Compare Value*/
\r
4379 #define CCU8_CC8_CR2_CR2_Pos (0U)
\r
4380 #define CCU8_CC8_CR2_CR2_Msk (0x0000FFFFU << CCU8_CC8_CR2_CR2_Pos)
\r
4382 /* CCU8_CC8_CR2S = Channel 2 Compare Shadow Value*/
\r
4383 #define CCU8_CC8_CR2S_CR2S_Pos (0U)
\r
4384 #define CCU8_CC8_CR2S_CR2S_Msk (0x0000FFFFU << CCU8_CC8_CR2S_CR2S_Pos)
\r
4386 /* CCU8_CC8_CHC = Channel Control*/
\r
4387 #define CCU8_CC8_CHC_ASE_Pos (0U)
\r
4388 #define CCU8_CC8_CHC_ASE_Msk (0x00000001U << CCU8_CC8_CHC_ASE_Pos)
\r
4390 #define CCU8_CC8_CHC_OCS1_Pos (1U)
\r
4391 #define CCU8_CC8_CHC_OCS1_Msk (0x00000001U << CCU8_CC8_CHC_OCS1_Pos)
\r
4393 #define CCU8_CC8_CHC_OCS2_Pos (2U)
\r
4394 #define CCU8_CC8_CHC_OCS2_Msk (0x00000001U << CCU8_CC8_CHC_OCS2_Pos)
\r
4396 #define CCU8_CC8_CHC_OCS3_Pos (3U)
\r
4397 #define CCU8_CC8_CHC_OCS3_Msk (0x00000001U << CCU8_CC8_CHC_OCS3_Pos)
\r
4399 #define CCU8_CC8_CHC_OCS4_Pos (4U)
\r
4400 #define CCU8_CC8_CHC_OCS4_Msk (0x00000001U << CCU8_CC8_CHC_OCS4_Pos)
\r
4402 /* CCU8_CC8_DTC = Dead Time Control*/
\r
4403 #define CCU8_CC8_DTC_DTE1_Pos (0U)
\r
4404 #define CCU8_CC8_DTC_DTE1_Msk (0x00000001U << CCU8_CC8_DTC_DTE1_Pos)
\r
4406 #define CCU8_CC8_DTC_DTE2_Pos (1U)
\r
4407 #define CCU8_CC8_DTC_DTE2_Msk (0x00000001U << CCU8_CC8_DTC_DTE2_Pos)
\r
4409 #define CCU8_CC8_DTC_DCEN1_Pos (2U)
\r
4410 #define CCU8_CC8_DTC_DCEN1_Msk (0x00000001U << CCU8_CC8_DTC_DCEN1_Pos)
\r
4412 #define CCU8_CC8_DTC_DCEN2_Pos (3U)
\r
4413 #define CCU8_CC8_DTC_DCEN2_Msk (0x00000001U << CCU8_CC8_DTC_DCEN2_Pos)
\r
4415 #define CCU8_CC8_DTC_DCEN3_Pos (4U)
\r
4416 #define CCU8_CC8_DTC_DCEN3_Msk (0x00000001U << CCU8_CC8_DTC_DCEN3_Pos)
\r
4418 #define CCU8_CC8_DTC_DCEN4_Pos (5U)
\r
4419 #define CCU8_CC8_DTC_DCEN4_Msk (0x00000001U << CCU8_CC8_DTC_DCEN4_Pos)
\r
4421 #define CCU8_CC8_DTC_DTCC_Pos (6U)
\r
4422 #define CCU8_CC8_DTC_DTCC_Msk (0x00000003U << CCU8_CC8_DTC_DTCC_Pos)
\r
4424 /* CCU8_CC8_DC1R = Channel 1 Dead Time Values*/
\r
4425 #define CCU8_CC8_DC1R_DT1R_Pos (0U)
\r
4426 #define CCU8_CC8_DC1R_DT1R_Msk (0x000000FFU << CCU8_CC8_DC1R_DT1R_Pos)
\r
4428 #define CCU8_CC8_DC1R_DT1F_Pos (8U)
\r
4429 #define CCU8_CC8_DC1R_DT1F_Msk (0x000000FFU << CCU8_CC8_DC1R_DT1F_Pos)
\r
4431 /* CCU8_CC8_DC2R = Channel 2 Dead Time Values*/
\r
4432 #define CCU8_CC8_DC2R_DT2R_Pos (0U)
\r
4433 #define CCU8_CC8_DC2R_DT2R_Msk (0x000000FFU << CCU8_CC8_DC2R_DT2R_Pos)
\r
4435 #define CCU8_CC8_DC2R_DT2F_Pos (8U)
\r
4436 #define CCU8_CC8_DC2R_DT2F_Msk (0x000000FFU << CCU8_CC8_DC2R_DT2F_Pos)
\r
4438 /* CCU8_CC8_TIMER = Timer Value*/
\r
4439 #define CCU8_CC8_TIMER_TVAL_Pos (0U)
\r
4440 #define CCU8_CC8_TIMER_TVAL_Msk (0x0000FFFFU << CCU8_CC8_TIMER_TVAL_Pos)
\r
4442 /* CCU8_CC8_C0V = Capture Register 0*/
\r
4443 #define CCU8_CC8_CV_CAPTV_Pos (0U)
\r
4444 #define CCU8_CC8_CV_CAPTV_Msk (0x0000FFFFU << CCU8_CC8_CV_CAPTV_Pos)
\r
4446 #define CCU8_CC8_CV_FPCV_Pos (16U)
\r
4447 #define CCU8_CC8_CV_FPCV_Msk (0x0000000FU << CCU8_CC8_CV_FPCV_Pos)
\r
4449 #define CCU8_CC8_CV_FFL_Pos (20U)
\r
4450 #define CCU8_CC8_CV_FFL_Msk (0x00000001U << CCU8_CC8_CV_FFL_Pos)
\r
4452 /* CCU8_CC8_INTS = Interrupt Status*/
\r
4453 #define CCU8_CC8_INTS_PMUS_Pos (0U)
\r
4454 #define CCU8_CC8_INTS_PMUS_Msk (0x00000001U << CCU8_CC8_INTS_PMUS_Pos)
\r
4456 #define CCU8_CC8_INTS_OMDS_Pos (1U)
\r
4457 #define CCU8_CC8_INTS_OMDS_Msk (0x00000001U << CCU8_CC8_INTS_OMDS_Pos)
\r
4459 #define CCU8_CC8_INTS_CMU1S_Pos (2U)
\r
4460 #define CCU8_CC8_INTS_CMU1S_Msk (0x00000001U << CCU8_CC8_INTS_CMU1S_Pos)
\r
4462 #define CCU8_CC8_INTS_CMD1S_Pos (3U)
\r
4463 #define CCU8_CC8_INTS_CMD1S_Msk (0x00000001U << CCU8_CC8_INTS_CMD1S_Pos)
\r
4465 #define CCU8_CC8_INTS_CMU2S_Pos (4U)
\r
4466 #define CCU8_CC8_INTS_CMU2S_Msk (0x00000001U << CCU8_CC8_INTS_CMU2S_Pos)
\r
4468 #define CCU8_CC8_INTS_CMD2S_Pos (5U)
\r
4469 #define CCU8_CC8_INTS_CMD2S_Msk (0x00000001U << CCU8_CC8_INTS_CMD2S_Pos)
\r
4471 #define CCU8_CC8_INTS_E0AS_Pos (8U)
\r
4472 #define CCU8_CC8_INTS_E0AS_Msk (0x00000001U << CCU8_CC8_INTS_E0AS_Pos)
\r
4474 #define CCU8_CC8_INTS_E1AS_Pos (9U)
\r
4475 #define CCU8_CC8_INTS_E1AS_Msk (0x00000001U << CCU8_CC8_INTS_E1AS_Pos)
\r
4477 #define CCU8_CC8_INTS_E2AS_Pos (10U)
\r
4478 #define CCU8_CC8_INTS_E2AS_Msk (0x00000001U << CCU8_CC8_INTS_E2AS_Pos)
\r
4480 #define CCU8_CC8_INTS_TRPF_Pos (11U)
\r
4481 #define CCU8_CC8_INTS_TRPF_Msk (0x00000001U << CCU8_CC8_INTS_TRPF_Pos)
\r
4483 /* CCU8_CC8_INTE = Interrupt Enable Control*/
\r
4484 #define CCU8_CC8_INTE_PME_Pos (0U)
\r
4485 #define CCU8_CC8_INTE_PME_Msk (0x00000001U << CCU8_CC8_INTE_PME_Pos)
\r
4487 #define CCU8_CC8_INTE_OME_Pos (1U)
\r
4488 #define CCU8_CC8_INTE_OME_Msk (0x00000001U << CCU8_CC8_INTE_OME_Pos)
\r
4490 #define CCU8_CC8_INTE_CMU1E_Pos (2U)
\r
4491 #define CCU8_CC8_INTE_CMU1E_Msk (0x00000001U << CCU8_CC8_INTE_CMU1E_Pos)
\r
4493 #define CCU8_CC8_INTE_CMD1E_Pos (3U)
\r
4494 #define CCU8_CC8_INTE_CMD1E_Msk (0x00000001U << CCU8_CC8_INTE_CMD1E_Pos)
\r
4496 #define CCU8_CC8_INTE_CMU2E_Pos (4U)
\r
4497 #define CCU8_CC8_INTE_CMU2E_Msk (0x00000001U << CCU8_CC8_INTE_CMU2E_Pos)
\r
4499 #define CCU8_CC8_INTE_CMD2E_Pos (5U)
\r
4500 #define CCU8_CC8_INTE_CMD2E_Msk (0x00000001U << CCU8_CC8_INTE_CMD2E_Pos)
\r
4502 #define CCU8_CC8_INTE_E0AE_Pos (8U)
\r
4503 #define CCU8_CC8_INTE_E0AE_Msk (0x00000001U << CCU8_CC8_INTE_E0AE_Pos)
\r
4505 #define CCU8_CC8_INTE_E1AE_Pos (9U)
\r
4506 #define CCU8_CC8_INTE_E1AE_Msk (0x00000001U << CCU8_CC8_INTE_E1AE_Pos)
\r
4508 #define CCU8_CC8_INTE_E2AE_Pos (10U)
\r
4509 #define CCU8_CC8_INTE_E2AE_Msk (0x00000001U << CCU8_CC8_INTE_E2AE_Pos)
\r
4511 /* CCU8_CC8_SRS = Service Request Selector*/
\r
4512 #define CCU8_CC8_SRS_POSR_Pos (0U)
\r
4513 #define CCU8_CC8_SRS_POSR_Msk (0x00000003U << CCU8_CC8_SRS_POSR_Pos)
\r
4515 #define CCU8_CC8_SRS_CM1SR_Pos (2U)
\r
4516 #define CCU8_CC8_SRS_CM1SR_Msk (0x00000003U << CCU8_CC8_SRS_CM1SR_Pos)
\r
4518 #define CCU8_CC8_SRS_CM2SR_Pos (4U)
\r
4519 #define CCU8_CC8_SRS_CM2SR_Msk (0x00000003U << CCU8_CC8_SRS_CM2SR_Pos)
\r
4521 #define CCU8_CC8_SRS_E0SR_Pos (8U)
\r
4522 #define CCU8_CC8_SRS_E0SR_Msk (0x00000003U << CCU8_CC8_SRS_E0SR_Pos)
\r
4524 #define CCU8_CC8_SRS_E1SR_Pos (10U)
\r
4525 #define CCU8_CC8_SRS_E1SR_Msk (0x00000003U << CCU8_CC8_SRS_E1SR_Pos)
\r
4527 #define CCU8_CC8_SRS_E2SR_Pos (12U)
\r
4528 #define CCU8_CC8_SRS_E2SR_Msk (0x00000003U << CCU8_CC8_SRS_E2SR_Pos)
\r
4530 /* CCU8_CC8_SWS = Interrupt Status Set*/
\r
4531 #define CCU8_CC8_SWS_SPM_Pos (0U)
\r
4532 #define CCU8_CC8_SWS_SPM_Msk (0x00000001U << CCU8_CC8_SWS_SPM_Pos)
\r
4534 #define CCU8_CC8_SWS_SOM_Pos (1U)
\r
4535 #define CCU8_CC8_SWS_SOM_Msk (0x00000001U << CCU8_CC8_SWS_SOM_Pos)
\r
4537 #define CCU8_CC8_SWS_SCM1U_Pos (2U)
\r
4538 #define CCU8_CC8_SWS_SCM1U_Msk (0x00000001U << CCU8_CC8_SWS_SCM1U_Pos)
\r
4540 #define CCU8_CC8_SWS_SCM1D_Pos (3U)
\r
4541 #define CCU8_CC8_SWS_SCM1D_Msk (0x00000001U << CCU8_CC8_SWS_SCM1D_Pos)
\r
4543 #define CCU8_CC8_SWS_SCM2U_Pos (4U)
\r
4544 #define CCU8_CC8_SWS_SCM2U_Msk (0x00000001U << CCU8_CC8_SWS_SCM2U_Pos)
\r
4546 #define CCU8_CC8_SWS_SCM2D_Pos (5U)
\r
4547 #define CCU8_CC8_SWS_SCM2D_Msk (0x00000001U << CCU8_CC8_SWS_SCM2D_Pos)
\r
4549 #define CCU8_CC8_SWS_SE0A_Pos (8U)
\r
4550 #define CCU8_CC8_SWS_SE0A_Msk (0x00000001U << CCU8_CC8_SWS_SE0A_Pos)
\r
4552 #define CCU8_CC8_SWS_SE1A_Pos (9U)
\r
4553 #define CCU8_CC8_SWS_SE1A_Msk (0x00000001U << CCU8_CC8_SWS_SE1A_Pos)
\r
4555 #define CCU8_CC8_SWS_SE2A_Pos (10U)
\r
4556 #define CCU8_CC8_SWS_SE2A_Msk (0x00000001U << CCU8_CC8_SWS_SE2A_Pos)
\r
4558 #define CCU8_CC8_SWS_STRPF_Pos (11U)
\r
4559 #define CCU8_CC8_SWS_STRPF_Msk (0x00000001U << CCU8_CC8_SWS_STRPF_Pos)
\r
4561 /* CCU8_CC8_SWR = Interrupt Status Clear*/
\r
4562 #define CCU8_CC8_SWR_RPM_Pos (0U)
\r
4563 #define CCU8_CC8_SWR_RPM_Msk (0x00000001U << CCU8_CC8_SWR_RPM_Pos)
\r
4565 #define CCU8_CC8_SWR_ROM_Pos (1U)
\r
4566 #define CCU8_CC8_SWR_ROM_Msk (0x00000001U << CCU8_CC8_SWR_ROM_Pos)
\r
4568 #define CCU8_CC8_SWR_RCM1U_Pos (2U)
\r
4569 #define CCU8_CC8_SWR_RCM1U_Msk (0x00000001U << CCU8_CC8_SWR_RCM1U_Pos)
\r
4571 #define CCU8_CC8_SWR_RCM1D_Pos (3U)
\r
4572 #define CCU8_CC8_SWR_RCM1D_Msk (0x00000001U << CCU8_CC8_SWR_RCM1D_Pos)
\r
4574 #define CCU8_CC8_SWR_RCM2U_Pos (4U)
\r
4575 #define CCU8_CC8_SWR_RCM2U_Msk (0x00000001U << CCU8_CC8_SWR_RCM2U_Pos)
\r
4577 #define CCU8_CC8_SWR_RCM2D_Pos (5U)
\r
4578 #define CCU8_CC8_SWR_RCM2D_Msk (0x00000001U << CCU8_CC8_SWR_RCM2D_Pos)
\r
4580 #define CCU8_CC8_SWR_RE0A_Pos (8U)
\r
4581 #define CCU8_CC8_SWR_RE0A_Msk (0x00000001U << CCU8_CC8_SWR_RE0A_Pos)
\r
4583 #define CCU8_CC8_SWR_RE1A_Pos (9U)
\r
4584 #define CCU8_CC8_SWR_RE1A_Msk (0x00000001U << CCU8_CC8_SWR_RE1A_Pos)
\r
4586 #define CCU8_CC8_SWR_RE2A_Pos (10U)
\r
4587 #define CCU8_CC8_SWR_RE2A_Msk (0x00000001U << CCU8_CC8_SWR_RE2A_Pos)
\r
4589 #define CCU8_CC8_SWR_RTRPF_Pos (11U)
\r
4590 #define CCU8_CC8_SWR_RTRPF_Msk (0x00000001U << CCU8_CC8_SWR_RTRPF_Pos)
\r
4594 /*** DAC Bit Fileds *******************/
\r
4595 /***************************************************************************/
\r
4598 /* DAC_ID = Module Identification Register*/
\r
4599 #define DAC_ID_MODR_Pos (0U)
\r
4600 #define DAC_ID_MODR_Msk (0x000000FFU << DAC_ID_MODR_Pos)
\r
4602 #define DAC_ID_MODT_Pos (8U)
\r
4603 #define DAC_ID_MODT_Msk (0x000000FFU << DAC_ID_MODT_Pos)
\r
4605 #define DAC_ID_MODN_Pos (16U)
\r
4606 #define DAC_ID_MODN_Msk (0x0000FFFFU << DAC_ID_MODN_Pos)
\r
4608 /* DAC_DAC0CFG0 = DAC0 Configuration Register 0*/
\r
4609 #define DAC_DAC0CFG0_FREQ_Pos (0U)
\r
4610 #define DAC_DAC0CFG0_FREQ_Msk (0x000FFFFFU << DAC_DAC0CFG0_FREQ_Pos)
\r
4612 #define DAC_DAC0CFG0_MODE_Pos (20U)
\r
4613 #define DAC_DAC0CFG0_MODE_Msk (0x00000007U << DAC_DAC0CFG0_MODE_Pos)
\r
4615 #define DAC_DAC0CFG0_SIGN_Pos (23U)
\r
4616 #define DAC_DAC0CFG0_SIGN_Msk (0x00000001U << DAC_DAC0CFG0_SIGN_Pos)
\r
4618 #define DAC_DAC0CFG0_FIFOIND_Pos (24U)
\r
4619 #define DAC_DAC0CFG0_FIFOIND_Msk (0x00000003U << DAC_DAC0CFG0_FIFOIND_Pos)
\r
4621 #define DAC_DAC0CFG0_FIFOEMP_Pos (26U)
\r
4622 #define DAC_DAC0CFG0_FIFOEMP_Msk (0x00000001U << DAC_DAC0CFG0_FIFOEMP_Pos)
\r
4624 #define DAC_DAC0CFG0_FIFOFUL_Pos (27U)
\r
4625 #define DAC_DAC0CFG0_FIFOFUL_Msk (0x00000001U << DAC_DAC0CFG0_FIFOFUL_Pos)
\r
4627 #define DAC_DAC0CFG0_SIGNEN_Pos (29U)
\r
4628 #define DAC_DAC0CFG0_SIGNEN_Msk (0x00000001U << DAC_DAC0CFG0_SIGNEN_Pos)
\r
4630 #define DAC_DAC0CFG0_SREN_Pos (30U)
\r
4631 #define DAC_DAC0CFG0_SREN_Msk (0x00000001U << DAC_DAC0CFG0_SREN_Pos)
\r
4633 #define DAC_DAC0CFG0_RUN_Pos (31U)
\r
4634 #define DAC_DAC0CFG0_RUN_Msk (0x00000001U << DAC_DAC0CFG0_RUN_Pos)
\r
4636 /* DAC_DAC0CFG1 = DAC0 Configuration Register 1*/
\r
4637 #define DAC_DAC0CFG1_SCALE_Pos (0U)
\r
4638 #define DAC_DAC0CFG1_SCALE_Msk (0x00000007U << DAC_DAC0CFG1_SCALE_Pos)
\r
4640 #define DAC_DAC0CFG1_MULDIV_Pos (3U)
\r
4641 #define DAC_DAC0CFG1_MULDIV_Msk (0x00000001U << DAC_DAC0CFG1_MULDIV_Pos)
\r
4643 #define DAC_DAC0CFG1_OFFS_Pos (4U)
\r
4644 #define DAC_DAC0CFG1_OFFS_Msk (0x000000FFU << DAC_DAC0CFG1_OFFS_Pos)
\r
4646 #define DAC_DAC0CFG1_TRIGSEL_Pos (12U)
\r
4647 #define DAC_DAC0CFG1_TRIGSEL_Msk (0x00000007U << DAC_DAC0CFG1_TRIGSEL_Pos)
\r
4649 #define DAC_DAC0CFG1_DATMOD_Pos (15U)
\r
4650 #define DAC_DAC0CFG1_DATMOD_Msk (0x00000001U << DAC_DAC0CFG1_DATMOD_Pos)
\r
4652 #define DAC_DAC0CFG1_SWTRIG_Pos (16U)
\r
4653 #define DAC_DAC0CFG1_SWTRIG_Msk (0x00000001U << DAC_DAC0CFG1_SWTRIG_Pos)
\r
4655 #define DAC_DAC0CFG1_TRIGMOD_Pos (17U)
\r
4656 #define DAC_DAC0CFG1_TRIGMOD_Msk (0x00000003U << DAC_DAC0CFG1_TRIGMOD_Pos)
\r
4658 #define DAC_DAC0CFG1_ANACFG_Pos (19U)
\r
4659 #define DAC_DAC0CFG1_ANACFG_Msk (0x0000001FU << DAC_DAC0CFG1_ANACFG_Pos)
\r
4661 #define DAC_DAC0CFG1_ANAEN_Pos (24U)
\r
4662 #define DAC_DAC0CFG1_ANAEN_Msk (0x00000001U << DAC_DAC0CFG1_ANAEN_Pos)
\r
4664 #define DAC_DAC0CFG1_REFCFGL_Pos (28U)
\r
4665 #define DAC_DAC0CFG1_REFCFGL_Msk (0x0000000FU << DAC_DAC0CFG1_REFCFGL_Pos)
\r
4667 /* DAC_DAC1CFG0 = DAC1 Configuration Register 0*/
\r
4668 #define DAC_DAC1CFG0_FREQ_Pos (0U)
\r
4669 #define DAC_DAC1CFG0_FREQ_Msk (0x000FFFFFU << DAC_DAC1CFG0_FREQ_Pos)
\r
4671 #define DAC_DAC1CFG0_MODE_Pos (20U)
\r
4672 #define DAC_DAC1CFG0_MODE_Msk (0x00000007U << DAC_DAC1CFG0_MODE_Pos)
\r
4674 #define DAC_DAC1CFG0_SIGN_Pos (23U)
\r
4675 #define DAC_DAC1CFG0_SIGN_Msk (0x00000001U << DAC_DAC1CFG0_SIGN_Pos)
\r
4677 #define DAC_DAC1CFG0_FIFOIND_Pos (24U)
\r
4678 #define DAC_DAC1CFG0_FIFOIND_Msk (0x00000003U << DAC_DAC1CFG0_FIFOIND_Pos)
\r
4680 #define DAC_DAC1CFG0_FIFOEMP_Pos (26U)
\r
4681 #define DAC_DAC1CFG0_FIFOEMP_Msk (0x00000001U << DAC_DAC1CFG0_FIFOEMP_Pos)
\r
4683 #define DAC_DAC1CFG0_FIFOFUL_Pos (27U)
\r
4684 #define DAC_DAC1CFG0_FIFOFUL_Msk (0x00000001U << DAC_DAC1CFG0_FIFOFUL_Pos)
\r
4686 #define DAC_DAC1CFG0_SIGNEN_Pos (29U)
\r
4687 #define DAC_DAC1CFG0_SIGNEN_Msk (0x00000001U << DAC_DAC1CFG0_SIGNEN_Pos)
\r
4689 #define DAC_DAC1CFG0_SREN_Pos (30U)
\r
4690 #define DAC_DAC1CFG0_SREN_Msk (0x00000001U << DAC_DAC1CFG0_SREN_Pos)
\r
4692 #define DAC_DAC1CFG0_RUN_Pos (31U)
\r
4693 #define DAC_DAC1CFG0_RUN_Msk (0x00000001U << DAC_DAC1CFG0_RUN_Pos)
\r
4695 /* DAC_DAC1CFG1 = DAC1 Configuration Register 1*/
\r
4696 #define DAC_DAC1CFG1_SCALE_Pos (0U)
\r
4697 #define DAC_DAC1CFG1_SCALE_Msk (0x00000007U << DAC_DAC1CFG1_SCALE_Pos)
\r
4699 #define DAC_DAC1CFG1_MULDIV_Pos (3U)
\r
4700 #define DAC_DAC1CFG1_MULDIV_Msk (0x00000001U << DAC_DAC1CFG1_MULDIV_Pos)
\r
4702 #define DAC_DAC1CFG1_OFFS_Pos (4U)
\r
4703 #define DAC_DAC1CFG1_OFFS_Msk (0x000000FFU << DAC_DAC1CFG1_OFFS_Pos)
\r
4705 #define DAC_DAC1CFG1_TRIGSEL_Pos (12U)
\r
4706 #define DAC_DAC1CFG1_TRIGSEL_Msk (0x00000007U << DAC_DAC1CFG1_TRIGSEL_Pos)
\r
4708 #define DAC_DAC1CFG1_SWTRIG_Pos (16U)
\r
4709 #define DAC_DAC1CFG1_SWTRIG_Msk (0x00000001U << DAC_DAC1CFG1_SWTRIG_Pos)
\r
4711 #define DAC_DAC1CFG1_TRIGMOD_Pos (17U)
\r
4712 #define DAC_DAC1CFG1_TRIGMOD_Msk (0x00000003U << DAC_DAC1CFG1_TRIGMOD_Pos)
\r
4714 #define DAC_DAC1CFG1_ANACFG_Pos (19U)
\r
4715 #define DAC_DAC1CFG1_ANACFG_Msk (0x0000001FU << DAC_DAC1CFG1_ANACFG_Pos)
\r
4717 #define DAC_DAC1CFG1_ANAEN_Pos (24U)
\r
4718 #define DAC_DAC1CFG1_ANAEN_Msk (0x00000001U << DAC_DAC1CFG1_ANAEN_Pos)
\r
4720 #define DAC_DAC1CFG1_REFCFGH_Pos (28U)
\r
4721 #define DAC_DAC1CFG1_REFCFGH_Msk (0x0000000FU << DAC_DAC1CFG1_REFCFGH_Pos)
\r
4723 /* DAC_DAC0DATA = DAC0 Data Register*/
\r
4724 #define DAC_DAC0DATA_DATA0_Pos (0U)
\r
4725 #define DAC_DAC0DATA_DATA0_Msk (0x00000FFFU << DAC_DAC0DATA_DATA0_Pos)
\r
4727 /* DAC_DAC1DATA = DAC1 Data Register*/
\r
4728 #define DAC_DAC1DATA_DATA1_Pos (0U)
\r
4729 #define DAC_DAC1DATA_DATA1_Msk (0x00000FFFU << DAC_DAC1DATA_DATA1_Pos)
\r
4731 /* DAC_DAC01DATA = DAC01 Data Register*/
\r
4732 #define DAC_DAC01DATA_DATA0_Pos (0U)
\r
4733 #define DAC_DAC01DATA_DATA0_Msk (0x00000FFFU << DAC_DAC01DATA_DATA0_Pos)
\r
4735 #define DAC_DAC01DATA_DATA1_Pos (16U)
\r
4736 #define DAC_DAC01DATA_DATA1_Msk (0x00000FFFU << DAC_DAC01DATA_DATA1_Pos)
\r
4738 /* DAC_DAC0PATL = DAC0 Lower Pattern Register*/
\r
4739 #define DAC_DAC0PATL_PAT0_Pos (0U)
\r
4740 #define DAC_DAC0PATL_PAT0_Msk (0x0000001FU << DAC_DAC0PATL_PAT0_Pos)
\r
4742 #define DAC_DAC0PATL_PAT1_Pos (5U)
\r
4743 #define DAC_DAC0PATL_PAT1_Msk (0x0000001FU << DAC_DAC0PATL_PAT1_Pos)
\r
4745 #define DAC_DAC0PATL_PAT2_Pos (10U)
\r
4746 #define DAC_DAC0PATL_PAT2_Msk (0x0000001FU << DAC_DAC0PATL_PAT2_Pos)
\r
4748 #define DAC_DAC0PATL_PAT3_Pos (15U)
\r
4749 #define DAC_DAC0PATL_PAT3_Msk (0x0000001FU << DAC_DAC0PATL_PAT3_Pos)
\r
4751 #define DAC_DAC0PATL_PAT4_Pos (20U)
\r
4752 #define DAC_DAC0PATL_PAT4_Msk (0x0000001FU << DAC_DAC0PATL_PAT4_Pos)
\r
4754 #define DAC_DAC0PATL_PAT5_Pos (25U)
\r
4755 #define DAC_DAC0PATL_PAT5_Msk (0x0000001FU << DAC_DAC0PATL_PAT5_Pos)
\r
4757 /* DAC_DAC0PATH = DAC0 Higher Pattern Register*/
\r
4758 #define DAC_DAC0PATH_PAT6_Pos (0U)
\r
4759 #define DAC_DAC0PATH_PAT6_Msk (0x0000001FU << DAC_DAC0PATH_PAT6_Pos)
\r
4761 #define DAC_DAC0PATH_PAT7_Pos (5U)
\r
4762 #define DAC_DAC0PATH_PAT7_Msk (0x0000001FU << DAC_DAC0PATH_PAT7_Pos)
\r
4764 #define DAC_DAC0PATH_PAT8_Pos (10U)
\r
4765 #define DAC_DAC0PATH_PAT8_Msk (0x0000001FU << DAC_DAC0PATH_PAT8_Pos)
\r
4767 /* DAC_DAC1PATL = DAC1 Lower Pattern Register*/
\r
4768 #define DAC_DAC1PATL_PAT0_Pos (0U)
\r
4769 #define DAC_DAC1PATL_PAT0_Msk (0x0000001FU << DAC_DAC1PATL_PAT0_Pos)
\r
4771 #define DAC_DAC1PATL_PAT1_Pos (5U)
\r
4772 #define DAC_DAC1PATL_PAT1_Msk (0x0000001FU << DAC_DAC1PATL_PAT1_Pos)
\r
4774 #define DAC_DAC1PATL_PAT2_Pos (10U)
\r
4775 #define DAC_DAC1PATL_PAT2_Msk (0x0000001FU << DAC_DAC1PATL_PAT2_Pos)
\r
4777 #define DAC_DAC1PATL_PAT3_Pos (15U)
\r
4778 #define DAC_DAC1PATL_PAT3_Msk (0x0000001FU << DAC_DAC1PATL_PAT3_Pos)
\r
4780 #define DAC_DAC1PATL_PAT4_Pos (20U)
\r
4781 #define DAC_DAC1PATL_PAT4_Msk (0x0000001FU << DAC_DAC1PATL_PAT4_Pos)
\r
4783 #define DAC_DAC1PATL_PAT5_Pos (25U)
\r
4784 #define DAC_DAC1PATL_PAT5_Msk (0x0000001FU << DAC_DAC1PATL_PAT5_Pos)
\r
4786 /* DAC_DAC1PATH = DAC1 Higher Pattern Register*/
\r
4787 #define DAC_DAC1PATH_PAT6_Pos (0U)
\r
4788 #define DAC_DAC1PATH_PAT6_Msk (0x0000001FU << DAC_DAC1PATH_PAT6_Pos)
\r
4790 #define DAC_DAC1PATH_PAT7_Pos (5U)
\r
4791 #define DAC_DAC1PATH_PAT7_Msk (0x0000001FU << DAC_DAC1PATH_PAT7_Pos)
\r
4793 #define DAC_DAC1PATH_PAT8_Pos (10U)
\r
4794 #define DAC_DAC1PATH_PAT8_Msk (0x0000001FU << DAC_DAC1PATH_PAT8_Pos)
\r
4798 /*** DLR Bit Fileds *******************/
\r
4799 /***************************************************************************/
\r
4802 /* DLR_OVRSTAT = GPDMA Overrun Status*/
\r
4803 #define DLR_OVRSTAT_LN0_Pos (0U)
\r
4804 #define DLR_OVRSTAT_LN0_Msk (0x00000001U << DLR_OVRSTAT_LN0_Pos)
\r
4806 #define DLR_OVRSTAT_LN1_Pos (1U)
\r
4807 #define DLR_OVRSTAT_LN1_Msk (0x00000001U << DLR_OVRSTAT_LN1_Pos)
\r
4809 #define DLR_OVRSTAT_LN2_Pos (2U)
\r
4810 #define DLR_OVRSTAT_LN2_Msk (0x00000001U << DLR_OVRSTAT_LN2_Pos)
\r
4812 #define DLR_OVRSTAT_LN3_Pos (3U)
\r
4813 #define DLR_OVRSTAT_LN3_Msk (0x00000001U << DLR_OVRSTAT_LN3_Pos)
\r
4815 #define DLR_OVRSTAT_LN4_Pos (4U)
\r
4816 #define DLR_OVRSTAT_LN4_Msk (0x00000001U << DLR_OVRSTAT_LN4_Pos)
\r
4818 #define DLR_OVRSTAT_LN5_Pos (5U)
\r
4819 #define DLR_OVRSTAT_LN5_Msk (0x00000001U << DLR_OVRSTAT_LN5_Pos)
\r
4821 #define DLR_OVRSTAT_LN6_Pos (6U)
\r
4822 #define DLR_OVRSTAT_LN6_Msk (0x00000001U << DLR_OVRSTAT_LN6_Pos)
\r
4824 #define DLR_OVRSTAT_LN7_Pos (7U)
\r
4825 #define DLR_OVRSTAT_LN7_Msk (0x00000001U << DLR_OVRSTAT_LN7_Pos)
\r
4827 #define DLR_OVRSTAT_LN8_Pos (8U)
\r
4828 #define DLR_OVRSTAT_LN8_Msk (0x00000001U << DLR_OVRSTAT_LN8_Pos)
\r
4830 #define DLR_OVRSTAT_LN9_Pos (9U)
\r
4831 #define DLR_OVRSTAT_LN9_Msk (0x00000001U << DLR_OVRSTAT_LN9_Pos)
\r
4833 #define DLR_OVRSTAT_LN10_Pos (10U)
\r
4834 #define DLR_OVRSTAT_LN10_Msk (0x00000001U << DLR_OVRSTAT_LN10_Pos)
\r
4836 #define DLR_OVRSTAT_LN11_Pos (11U)
\r
4837 #define DLR_OVRSTAT_LN11_Msk (0x00000001U << DLR_OVRSTAT_LN11_Pos)
\r
4839 /* DLR_OVRCLR = GPDMA Overrun Clear*/
\r
4840 #define DLR_OVRCLR_LN0_Pos (0U)
\r
4841 #define DLR_OVRCLR_LN0_Msk (0x00000001U << DLR_OVRCLR_LN0_Pos)
\r
4843 #define DLR_OVRCLR_LN1_Pos (1U)
\r
4844 #define DLR_OVRCLR_LN1_Msk (0x00000001U << DLR_OVRCLR_LN1_Pos)
\r
4846 #define DLR_OVRCLR_LN2_Pos (2U)
\r
4847 #define DLR_OVRCLR_LN2_Msk (0x00000001U << DLR_OVRCLR_LN2_Pos)
\r
4849 #define DLR_OVRCLR_LN3_Pos (3U)
\r
4850 #define DLR_OVRCLR_LN3_Msk (0x00000001U << DLR_OVRCLR_LN3_Pos)
\r
4852 #define DLR_OVRCLR_LN4_Pos (4U)
\r
4853 #define DLR_OVRCLR_LN4_Msk (0x00000001U << DLR_OVRCLR_LN4_Pos)
\r
4855 #define DLR_OVRCLR_LN5_Pos (5U)
\r
4856 #define DLR_OVRCLR_LN5_Msk (0x00000001U << DLR_OVRCLR_LN5_Pos)
\r
4858 #define DLR_OVRCLR_LN6_Pos (6U)
\r
4859 #define DLR_OVRCLR_LN6_Msk (0x00000001U << DLR_OVRCLR_LN6_Pos)
\r
4861 #define DLR_OVRCLR_LN7_Pos (7U)
\r
4862 #define DLR_OVRCLR_LN7_Msk (0x00000001U << DLR_OVRCLR_LN7_Pos)
\r
4864 #define DLR_OVRCLR_LN8_Pos (8U)
\r
4865 #define DLR_OVRCLR_LN8_Msk (0x00000001U << DLR_OVRCLR_LN8_Pos)
\r
4867 #define DLR_OVRCLR_LN9_Pos (9U)
\r
4868 #define DLR_OVRCLR_LN9_Msk (0x00000001U << DLR_OVRCLR_LN9_Pos)
\r
4870 #define DLR_OVRCLR_LN10_Pos (10U)
\r
4871 #define DLR_OVRCLR_LN10_Msk (0x00000001U << DLR_OVRCLR_LN10_Pos)
\r
4873 #define DLR_OVRCLR_LN11_Pos (11U)
\r
4874 #define DLR_OVRCLR_LN11_Msk (0x00000001U << DLR_OVRCLR_LN11_Pos)
\r
4876 /* DLR_SRSEL0 = GPDMA Service Request Selection 0*/
\r
4877 #define DLR_SRSEL0_RS0_Pos (0U)
\r
4878 #define DLR_SRSEL0_RS0_Msk (0x0000000FU << DLR_SRSEL0_RS0_Pos)
\r
4880 #define DLR_SRSEL0_RS1_Pos (4U)
\r
4881 #define DLR_SRSEL0_RS1_Msk (0x0000000FU << DLR_SRSEL0_RS1_Pos)
\r
4883 #define DLR_SRSEL0_RS2_Pos (8U)
\r
4884 #define DLR_SRSEL0_RS2_Msk (0x0000000FU << DLR_SRSEL0_RS2_Pos)
\r
4886 #define DLR_SRSEL0_RS3_Pos (12U)
\r
4887 #define DLR_SRSEL0_RS3_Msk (0x0000000FU << DLR_SRSEL0_RS3_Pos)
\r
4889 #define DLR_SRSEL0_RS4_Pos (16U)
\r
4890 #define DLR_SRSEL0_RS4_Msk (0x0000000FU << DLR_SRSEL0_RS4_Pos)
\r
4892 #define DLR_SRSEL0_RS5_Pos (20U)
\r
4893 #define DLR_SRSEL0_RS5_Msk (0x0000000FU << DLR_SRSEL0_RS5_Pos)
\r
4895 #define DLR_SRSEL0_RS6_Pos (24U)
\r
4896 #define DLR_SRSEL0_RS6_Msk (0x0000000FU << DLR_SRSEL0_RS6_Pos)
\r
4898 #define DLR_SRSEL0_RS7_Pos (28U)
\r
4899 #define DLR_SRSEL0_RS7_Msk (0x0000000FU << DLR_SRSEL0_RS7_Pos)
\r
4901 /* DLR_SRSEL1 = GPDMA Service Request Selection 1*/
\r
4902 #define DLR_SRSEL1_RS8_Pos (0U)
\r
4903 #define DLR_SRSEL1_RS8_Msk (0x0000000FU << DLR_SRSEL1_RS8_Pos)
\r
4905 #define DLR_SRSEL1_RS9_Pos (4U)
\r
4906 #define DLR_SRSEL1_RS9_Msk (0x0000000FU << DLR_SRSEL1_RS9_Pos)
\r
4908 #define DLR_SRSEL1_RS10_Pos (8U)
\r
4909 #define DLR_SRSEL1_RS10_Msk (0x0000000FU << DLR_SRSEL1_RS10_Pos)
\r
4911 #define DLR_SRSEL1_RS11_Pos (12U)
\r
4912 #define DLR_SRSEL1_RS11_Msk (0x0000000FU << DLR_SRSEL1_RS11_Pos)
\r
4914 /* DLR_LNEN = GPDMA Line Enable*/
\r
4915 #define DLR_LNEN_LN0_Pos (0U)
\r
4916 #define DLR_LNEN_LN0_Msk (0x00000001U << DLR_LNEN_LN0_Pos)
\r
4918 #define DLR_LNEN_LN1_Pos (1U)
\r
4919 #define DLR_LNEN_LN1_Msk (0x00000001U << DLR_LNEN_LN1_Pos)
\r
4921 #define DLR_LNEN_LN2_Pos (2U)
\r
4922 #define DLR_LNEN_LN2_Msk (0x00000001U << DLR_LNEN_LN2_Pos)
\r
4924 #define DLR_LNEN_LN3_Pos (3U)
\r
4925 #define DLR_LNEN_LN3_Msk (0x00000001U << DLR_LNEN_LN3_Pos)
\r
4927 #define DLR_LNEN_LN4_Pos (4U)
\r
4928 #define DLR_LNEN_LN4_Msk (0x00000001U << DLR_LNEN_LN4_Pos)
\r
4930 #define DLR_LNEN_LN5_Pos (5U)
\r
4931 #define DLR_LNEN_LN5_Msk (0x00000001U << DLR_LNEN_LN5_Pos)
\r
4933 #define DLR_LNEN_LN6_Pos (6U)
\r
4934 #define DLR_LNEN_LN6_Msk (0x00000001U << DLR_LNEN_LN6_Pos)
\r
4936 #define DLR_LNEN_LN7_Pos (7U)
\r
4937 #define DLR_LNEN_LN7_Msk (0x00000001U << DLR_LNEN_LN7_Pos)
\r
4939 #define DLR_LNEN_LN8_Pos (8U)
\r
4940 #define DLR_LNEN_LN8_Msk (0x00000001U << DLR_LNEN_LN8_Pos)
\r
4942 #define DLR_LNEN_LN9_Pos (9U)
\r
4943 #define DLR_LNEN_LN9_Msk (0x00000001U << DLR_LNEN_LN9_Pos)
\r
4945 #define DLR_LNEN_LN10_Pos (10U)
\r
4946 #define DLR_LNEN_LN10_Msk (0x00000001U << DLR_LNEN_LN10_Pos)
\r
4948 #define DLR_LNEN_LN11_Pos (11U)
\r
4949 #define DLR_LNEN_LN11_Msk (0x00000001U << DLR_LNEN_LN11_Pos)
\r
4953 /*** GPDMA1 Bit Fileds *******************/
\r
4954 /***************************************************************************/
\r
4957 /* GPDMA1_SARx = Source Address Register for Channel 0*/
\r
4958 #define GPDMA1_SAR_SAR_Pos (0U)
\r
4959 #define GPDMA1_SAR_SAR_Msk (0xFFFFFFFFU << GPDMA1_SAR_SAR_Pos)
\r
4961 /* GPDMA1_DARx = Destination Address Register for Channel 0*/
\r
4962 #define GPDMA1_DAR_DAR_Pos (0U)
\r
4963 #define GPDMA1_DAR_DAR_Msk (0xFFFFFFFFU << GPDMA1_DAR_DAR_Pos)
\r
4965 /* GPDMA1_CH_CTLL = Control Register for Channel x Low Word*/
\r
4966 #define GPDMA1_CH_CTLL_TT_FC_Pos (20U)
\r
4967 #define GPDMA1_CH_CTLL_TT_FC_Msk (0x00000007U << GPDMA1_CH_CTLL_TT_FC_Pos)
\r
4969 #define GPDMA1_CH_CTLL_SRC_MSIZE_Pos (14U)
\r
4970 #define GPDMA1_CH_CTLL_SRC_MSIZE_Msk (0x00000007U << GPDMA1_CH_CTLL_SRC_MSIZE_Pos)
\r
4972 #define GPDMA1_CH_CTLL_DEST_MSIZE_Pos (11U)
\r
4973 #define GPDMA1_CH_CTLL_DEST_MSIZE_Msk (0x00000007U << GPDMA1_CH_CTLL_DEST_MSIZE_Pos)
\r
4975 #define GPDMA1_CH_CTLL_SINC_Pos (9U)
\r
4976 #define GPDMA1_CH_CTLL_SINC_Msk (0x00000003U << GPDMA1_CH_CTLL_SINC_Pos)
\r
4978 #define GPDMA1_CH_CTLL_DINC_Pos (7U)
\r
4979 #define GPDMA1_CH_CTLL_DINC_Msk (0x00000003U << GPDMA1_CH_CTLL_DINC_Pos)
\r
4981 #define GPDMA1_CH_CTLL_SRC_TR_WIDTH_Pos (4U)
\r
4982 #define GPDMA1_CH_CTLL_SRC_TR_WIDTH_Msk (0x00000007U << GPDMA1_CH_CTLL_SRC_TR_WIDTH_Pos)
\r
4984 #define GPDMA1_CH_CTLL_DST_TR_WIDTH_Pos (1U)
\r
4985 #define GPDMA1_CH_CTLL_DST_TR_WIDTH_Msk (0x00000007U << GPDMA1_CH_CTLL_DST_TR_WIDTH_Pos)
\r
4987 #define GPDMA1_CH_CTLL_INT_EN_Pos (0U)
\r
4988 #define GPDMA1_CH_CTLL_INT_EN_Msk (0x00000001U << GPDMA1_CH_CTLL_INT_EN_Pos)
\r
4990 /* GPDMA1_CH_CTLH = Control Register for Channel x High Word*/
\r
4991 #define GPDMA1_CH_CTLH_DONE_Pos (12U)
\r
4992 #define GPDMA1_CH_CTLH_DONE_Msk (0x00000001U << GPDMA1_CH_CTLH_DONE_Pos)
\r
4994 #define GPDMA1_CH_CTLH_BLOCK_TS_Pos (0U)
\r
4995 #define GPDMA1_CH_CTLH_BLOCK_TS_Msk (0x00000FFFU << GPDMA1_CH_CTLH_BLOCK_TS_Pos)
\r
4997 /* GPDMA1_CH_CFGL = Configuration Register for Channel x Low Word*/
\r
4998 #define GPDMA1_CH_CFGL_MAX_ABRST_Pos (20U)
\r
4999 #define GPDMA1_CH_CFGL_MAX_ABRST_Msk (0x000003FFU << GPDMA1_CH_CFGL_MAX_ABRST_Pos)
\r
5001 #define GPDMA1_CH_CFGL_SRC_HS_POL_Pos (19U)
\r
5002 #define GPDMA1_CH_CFGL_SRC_HS_POL_Msk (0x00000001U << GPDMA1_CH_CFGL_SRC_HS_POL_Pos)
\r
5004 #define GPDMA1_CH_CFGL_DST_HS_POL_Pos (18U)
\r
5005 #define GPDMA1_CH_CFGL_DST_HS_POL_Msk (0x00000001U << GPDMA1_CH_CFGL_DST_HS_POL_Pos)
\r
5007 #define GPDMA1_CH_CFGL_LOCK_B_Pos (17U)
\r
5008 #define GPDMA1_CH_CFGL_LOCK_B_Msk (0x00000001U << GPDMA1_CH_CFGL_LOCK_B_Pos)
\r
5010 #define GPDMA1_CH_CFGL_LOCK_CH_Pos (16U)
\r
5011 #define GPDMA1_CH_CFGL_LOCK_CH_Msk (0x00000001U << GPDMA1_CH_CFGL_LOCK_CH_Pos)
\r
5013 #define GPDMA1_CH_CFGL_LOCK_B_L_Pos (14U)
\r
5014 #define GPDMA1_CH_CFGL_LOCK_B_L_Msk (0x00000003U << GPDMA1_CH_CFGL_LOCK_B_L_Pos)
\r
5016 #define GPDMA1_CH_CFGL_LOCK_CH_L_Pos (12U)
\r
5017 #define GPDMA1_CH_CFGL_LOCK_CH_L_Msk (0x00000003U << GPDMA1_CH_CFGL_LOCK_CH_L_Pos)
\r
5019 #define GPDMA1_CH_CFGL_HS_SEL_SRC_Pos (11U)
\r
5020 #define GPDMA1_CH_CFGL_HS_SEL_SRC_Msk (0x00000001U << GPDMA1_CH_CFGL_HS_SEL_SRC_Pos)
\r
5022 #define GPDMA1_CH_CFGL_HS_SEL_DST_Pos (10U)
\r
5023 #define GPDMA1_CH_CFGL_HS_SEL_DST_Msk (0x00000001U << GPDMA1_CH_CFGL_HS_SEL_DST_Pos)
\r
5025 #define GPDMA1_CH_CFGL_FIFO_EMPTY_Pos (9U)
\r
5026 #define GPDMA1_CH_CFGL_FIFO_EMPTY_Msk (0x00000001U << GPDMA1_CH_CFGL_FIFO_EMPTY_Pos)
\r
5028 #define GPDMA1_CH_CFGL_CH_SUSP_Pos (8U)
\r
5029 #define GPDMA1_CH_CFGL_CH_SUSP_Msk (0x00000001U << GPDMA1_CH_CFGL_CH_SUSP_Pos)
\r
5031 #define GPDMA1_CH_CFGL_CH_PRIOR_Pos (5U)
\r
5032 #define GPDMA1_CH_CFGL_CH_PRIOR_Msk (0x00000007U << GPDMA1_CH_CFGL_CH_PRIOR_Pos)
\r
5034 /* GPDMA1_CH_CFGH = Configuration Register for Channel x High Word*/
\r
5035 #define GPDMA1_CH_CFGH_DEST_PER_Pos (11U)
\r
5036 #define GPDMA1_CH_CFGH_DEST_PER_Msk (0x0000000FU << GPDMA1_CH_CFGH_DEST_PER_Pos)
\r
5038 #define GPDMA1_CH_CFGH_SRC_PER_Pos (7U)
\r
5039 #define GPDMA1_CH_CFGH_SRC_PER_Msk (0x0000000FU << GPDMA1_CH_CFGH_SRC_PER_Pos)
\r
5041 #define GPDMA1_CH_CFGH_PROTCTL_Pos (2U)
\r
5042 #define GPDMA1_CH_CFGH_PROTCTL_Msk (0x00000007U << GPDMA1_CH_CFGH_PROTCTL_Pos)
\r
5044 #define GPDMA1_CH_CFGH_FIFO_MODE_Pos (1U)
\r
5045 #define GPDMA1_CH_CFGH_FIFO_MODE_Msk (0x00000001U << GPDMA1_CH_CFGH_FIFO_MODE_Pos)
\r
5047 #define GPDMA1_CH_CFGH_FCMODE_Pos (0U)
\r
5048 #define GPDMA1_CH_CFGH_FCMODE_Msk (0x00000001U << GPDMA1_CH_CFGH_FCMODE_Pos)
\r
5050 /* GPDMA1_RAWTFR = Raw IntTfr Status*/
\r
5051 #define GPDMA1_RAWTFR_CH0_Pos (0U)
\r
5052 #define GPDMA1_RAWTFR_CH0_Msk (0x00000001U << GPDMA1_RAWTFR_CH0_Pos)
\r
5054 #define GPDMA1_RAWTFR_CH1_Pos (1U)
\r
5055 #define GPDMA1_RAWTFR_CH1_Msk (0x00000001U << GPDMA1_RAWTFR_CH1_Pos)
\r
5057 #define GPDMA1_RAWTFR_CH2_Pos (2U)
\r
5058 #define GPDMA1_RAWTFR_CH2_Msk (0x00000001U << GPDMA1_RAWTFR_CH2_Pos)
\r
5060 #define GPDMA1_RAWTFR_CH3_Pos (3U)
\r
5061 #define GPDMA1_RAWTFR_CH3_Msk (0x00000001U << GPDMA1_RAWTFR_CH3_Pos)
\r
5063 /* GPDMA1_RAWBLOCK = Raw IntBlock Status*/
\r
5064 #define GPDMA1_RAWBLOCK_CH0_Pos (0U)
\r
5065 #define GPDMA1_RAWBLOCK_CH0_Msk (0x00000001U << GPDMA1_RAWBLOCK_CH0_Pos)
\r
5067 #define GPDMA1_RAWBLOCK_CH1_Pos (1U)
\r
5068 #define GPDMA1_RAWBLOCK_CH1_Msk (0x00000001U << GPDMA1_RAWBLOCK_CH1_Pos)
\r
5070 #define GPDMA1_RAWBLOCK_CH2_Pos (2U)
\r
5071 #define GPDMA1_RAWBLOCK_CH2_Msk (0x00000001U << GPDMA1_RAWBLOCK_CH2_Pos)
\r
5073 #define GPDMA1_RAWBLOCK_CH3_Pos (3U)
\r
5074 #define GPDMA1_RAWBLOCK_CH3_Msk (0x00000001U << GPDMA1_RAWBLOCK_CH3_Pos)
\r
5076 /* GPDMA1_RAWSRCTRAN = Raw IntSrcTran Status*/
\r
5077 #define GPDMA1_RAWSRCTRAN_CH0_Pos (0U)
\r
5078 #define GPDMA1_RAWSRCTRAN_CH0_Msk (0x00000001U << GPDMA1_RAWSRCTRAN_CH0_Pos)
\r
5080 #define GPDMA1_RAWSRCTRAN_CH1_Pos (1U)
\r
5081 #define GPDMA1_RAWSRCTRAN_CH1_Msk (0x00000001U << GPDMA1_RAWSRCTRAN_CH1_Pos)
\r
5083 #define GPDMA1_RAWSRCTRAN_CH2_Pos (2U)
\r
5084 #define GPDMA1_RAWSRCTRAN_CH2_Msk (0x00000001U << GPDMA1_RAWSRCTRAN_CH2_Pos)
\r
5086 #define GPDMA1_RAWSRCTRAN_CH3_Pos (3U)
\r
5087 #define GPDMA1_RAWSRCTRAN_CH3_Msk (0x00000001U << GPDMA1_RAWSRCTRAN_CH3_Pos)
\r
5089 /* GPDMA1_RAWDSTTRAN = Raw IntBlock Status*/
\r
5090 #define GPDMA1_RAWDSTTRAN_CH0_Pos (0U)
\r
5091 #define GPDMA1_RAWDSTTRAN_CH0_Msk (0x00000001U << GPDMA1_RAWDSTTRAN_CH0_Pos)
\r
5093 #define GPDMA1_RAWDSTTRAN_CH1_Pos (1U)
\r
5094 #define GPDMA1_RAWDSTTRAN_CH1_Msk (0x00000001U << GPDMA1_RAWDSTTRAN_CH1_Pos)
\r
5096 #define GPDMA1_RAWDSTTRAN_CH2_Pos (2U)
\r
5097 #define GPDMA1_RAWDSTTRAN_CH2_Msk (0x00000001U << GPDMA1_RAWDSTTRAN_CH2_Pos)
\r
5099 #define GPDMA1_RAWDSTTRAN_CH3_Pos (3U)
\r
5100 #define GPDMA1_RAWDSTTRAN_CH3_Msk (0x00000001U << GPDMA1_RAWDSTTRAN_CH3_Pos)
\r
5102 /* GPDMA1_RAWERR = Raw IntErr Status*/
\r
5103 #define GPDMA1_RAWERR_CH0_Pos (0U)
\r
5104 #define GPDMA1_RAWERR_CH0_Msk (0x00000001U << GPDMA1_RAWERR_CH0_Pos)
\r
5106 #define GPDMA1_RAWERR_CH1_Pos (1U)
\r
5107 #define GPDMA1_RAWERR_CH1_Msk (0x00000001U << GPDMA1_RAWERR_CH1_Pos)
\r
5109 #define GPDMA1_RAWERR_CH2_Pos (2U)
\r
5110 #define GPDMA1_RAWERR_CH2_Msk (0x00000001U << GPDMA1_RAWERR_CH2_Pos)
\r
5112 #define GPDMA1_RAWERR_CH3_Pos (3U)
\r
5113 #define GPDMA1_RAWERR_CH3_Msk (0x00000001U << GPDMA1_RAWERR_CH3_Pos)
\r
5115 /* GPDMA1_STATUSTFR = IntTfr Status*/
\r
5116 #define GPDMA1_STATUSTFR_CH0_Pos (0U)
\r
5117 #define GPDMA1_STATUSTFR_CH0_Msk (0x00000001U << GPDMA1_STATUSTFR_CH0_Pos)
\r
5119 #define GPDMA1_STATUSTFR_CH1_Pos (1U)
\r
5120 #define GPDMA1_STATUSTFR_CH1_Msk (0x00000001U << GPDMA1_STATUSTFR_CH1_Pos)
\r
5122 #define GPDMA1_STATUSTFR_CH2_Pos (2U)
\r
5123 #define GPDMA1_STATUSTFR_CH2_Msk (0x00000001U << GPDMA1_STATUSTFR_CH2_Pos)
\r
5125 #define GPDMA1_STATUSTFR_CH3_Pos (3U)
\r
5126 #define GPDMA1_STATUSTFR_CH3_Msk (0x00000001U << GPDMA1_STATUSTFR_CH3_Pos)
\r
5128 /* GPDMA1_STATUSBLOCK = IntBlock Status*/
\r
5129 #define GPDMA1_STATUSBLOCK_CH0_Pos (0U)
\r
5130 #define GPDMA1_STATUSBLOCK_CH0_Msk (0x00000001U << GPDMA1_STATUSBLOCK_CH0_Pos)
\r
5132 #define GPDMA1_STATUSBLOCK_CH1_Pos (1U)
\r
5133 #define GPDMA1_STATUSBLOCK_CH1_Msk (0x00000001U << GPDMA1_STATUSBLOCK_CH1_Pos)
\r
5135 #define GPDMA1_STATUSBLOCK_CH2_Pos (2U)
\r
5136 #define GPDMA1_STATUSBLOCK_CH2_Msk (0x00000001U << GPDMA1_STATUSBLOCK_CH2_Pos)
\r
5138 #define GPDMA1_STATUSBLOCK_CH3_Pos (3U)
\r
5139 #define GPDMA1_STATUSBLOCK_CH3_Msk (0x00000001U << GPDMA1_STATUSBLOCK_CH3_Pos)
\r
5141 /* GPDMA1_STATUSSRCTRAN = IntSrcTran Status*/
\r
5142 #define GPDMA1_STATUSSRCTRAN_CH0_Pos (0U)
\r
5143 #define GPDMA1_STATUSSRCTRAN_CH0_Msk (0x00000001U << GPDMA1_STATUSSRCTRAN_CH0_Pos)
\r
5145 #define GPDMA1_STATUSSRCTRAN_CH1_Pos (1U)
\r
5146 #define GPDMA1_STATUSSRCTRAN_CH1_Msk (0x00000001U << GPDMA1_STATUSSRCTRAN_CH1_Pos)
\r
5148 #define GPDMA1_STATUSSRCTRAN_CH2_Pos (2U)
\r
5149 #define GPDMA1_STATUSSRCTRAN_CH2_Msk (0x00000001U << GPDMA1_STATUSSRCTRAN_CH2_Pos)
\r
5151 #define GPDMA1_STATUSSRCTRAN_CH3_Pos (3U)
\r
5152 #define GPDMA1_STATUSSRCTRAN_CH3_Msk (0x00000001U << GPDMA1_STATUSSRCTRAN_CH3_Pos)
\r
5154 /* GPDMA1_STATUSDSTTRAN = IntBlock Status*/
\r
5155 #define GPDMA1_STATUSDSTTRAN_CH0_Pos (0U)
\r
5156 #define GPDMA1_STATUSDSTTRAN_CH0_Msk (0x00000001U << GPDMA1_STATUSDSTTRAN_CH0_Pos)
\r
5158 #define GPDMA1_STATUSDSTTRAN_CH1_Pos (1U)
\r
5159 #define GPDMA1_STATUSDSTTRAN_CH1_Msk (0x00000001U << GPDMA1_STATUSDSTTRAN_CH1_Pos)
\r
5161 #define GPDMA1_STATUSDSTTRAN_CH2_Pos (2U)
\r
5162 #define GPDMA1_STATUSDSTTRAN_CH2_Msk (0x00000001U << GPDMA1_STATUSDSTTRAN_CH2_Pos)
\r
5164 #define GPDMA1_STATUSDSTTRAN_CH3_Pos (3U)
\r
5165 #define GPDMA1_STATUSDSTTRAN_CH3_Msk (0x00000001U << GPDMA1_STATUSDSTTRAN_CH3_Pos)
\r
5167 /* GPDMA1_STATUSERR = IntErr Status*/
\r
5168 #define GPDMA1_STATUSERR_CH0_Pos (0U)
\r
5169 #define GPDMA1_STATUSERR_CH0_Msk (0x00000001U << GPDMA1_STATUSERR_CH0_Pos)
\r
5171 #define GPDMA1_STATUSERR_CH1_Pos (1U)
\r
5172 #define GPDMA1_STATUSERR_CH1_Msk (0x00000001U << GPDMA1_STATUSERR_CH1_Pos)
\r
5174 #define GPDMA1_STATUSERR_CH2_Pos (2U)
\r
5175 #define GPDMA1_STATUSERR_CH2_Msk (0x00000001U << GPDMA1_STATUSERR_CH2_Pos)
\r
5177 #define GPDMA1_STATUSERR_CH3_Pos (3U)
\r
5178 #define GPDMA1_STATUSERR_CH3_Msk (0x00000001U << GPDMA1_STATUSERR_CH3_Pos)
\r
5180 /* GPDMA1_MASKTFR = Mask for Raw IntTfr Status*/
\r
5181 #define GPDMA1_MASKTFR_WE_CH0_Pos (8U)
\r
5182 #define GPDMA1_MASKTFR_WE_CH0_Msk (0x00000001U << GPDMA1_MASKTFR_WE_CH0_Pos)
\r
5184 #define GPDMA1_MASKTFR_WE_CH1_Pos (9U)
\r
5185 #define GPDMA1_MASKTFR_WE_CH1_Msk (0x00000001U << GPDMA1_MASKTFR_WE_CH1_Pos)
\r
5187 #define GPDMA1_MASKTFR_WE_CH2_Pos (10U)
\r
5188 #define GPDMA1_MASKTFR_WE_CH2_Msk (0x00000001U << GPDMA1_MASKTFR_WE_CH2_Pos)
\r
5190 #define GPDMA1_MASKTFR_WE_CH3_Pos (11U)
\r
5191 #define GPDMA1_MASKTFR_WE_CH3_Msk (0x00000001U << GPDMA1_MASKTFR_WE_CH3_Pos)
\r
5193 #define GPDMA1_MASKTFR_CH0_Pos (0U)
\r
5194 #define GPDMA1_MASKTFR_CH0_Msk (0x00000001U << GPDMA1_MASKTFR_CH0_Pos)
\r
5196 #define GPDMA1_MASKTFR_CH1_Pos (1U)
\r
5197 #define GPDMA1_MASKTFR_CH1_Msk (0x00000001U << GPDMA1_MASKTFR_CH1_Pos)
\r
5199 #define GPDMA1_MASKTFR_CH2_Pos (2U)
\r
5200 #define GPDMA1_MASKTFR_CH2_Msk (0x00000001U << GPDMA1_MASKTFR_CH2_Pos)
\r
5202 #define GPDMA1_MASKTFR_CH3_Pos (3U)
\r
5203 #define GPDMA1_MASKTFR_CH3_Msk (0x00000001U << GPDMA1_MASKTFR_CH3_Pos)
\r
5205 /* GPDMA1_MASKBLOCK = Mask for Raw IntBlock Status*/
\r
5206 #define GPDMA1_MASKBLOCK_WE_CH0_Pos (8U)
\r
5207 #define GPDMA1_MASKBLOCK_WE_CH0_Msk (0x00000001U << GPDMA1_MASKBLOCK_WE_CH0_Pos)
\r
5209 #define GPDMA1_MASKBLOCK_WE_CH1_Pos (9U)
\r
5210 #define GPDMA1_MASKBLOCK_WE_CH1_Msk (0x00000001U << GPDMA1_MASKBLOCK_WE_CH1_Pos)
\r
5212 #define GPDMA1_MASKBLOCK_WE_CH2_Pos (10U)
\r
5213 #define GPDMA1_MASKBLOCK_WE_CH2_Msk (0x00000001U << GPDMA1_MASKBLOCK_WE_CH2_Pos)
\r
5215 #define GPDMA1_MASKBLOCK_WE_CH3_Pos (11U)
\r
5216 #define GPDMA1_MASKBLOCK_WE_CH3_Msk (0x00000001U << GPDMA1_MASKBLOCK_WE_CH3_Pos)
\r
5218 #define GPDMA1_MASKBLOCK_CH0_Pos (0U)
\r
5219 #define GPDMA1_MASKBLOCK_CH0_Msk (0x00000001U << GPDMA1_MASKBLOCK_CH0_Pos)
\r
5221 #define GPDMA1_MASKBLOCK_CH1_Pos (1U)
\r
5222 #define GPDMA1_MASKBLOCK_CH1_Msk (0x00000001U << GPDMA1_MASKBLOCK_CH1_Pos)
\r
5224 #define GPDMA1_MASKBLOCK_CH2_Pos (2U)
\r
5225 #define GPDMA1_MASKBLOCK_CH2_Msk (0x00000001U << GPDMA1_MASKBLOCK_CH2_Pos)
\r
5227 #define GPDMA1_MASKBLOCK_CH3_Pos (3U)
\r
5228 #define GPDMA1_MASKBLOCK_CH3_Msk (0x00000001U << GPDMA1_MASKBLOCK_CH3_Pos)
\r
5230 /* GPDMA1_MASKSRCTRAN = Mask for Raw IntSrcTran Status*/
\r
5231 #define GPDMA1_MASKSRCTRAN_WE_CH0_Pos (8U)
\r
5232 #define GPDMA1_MASKSRCTRAN_WE_CH0_Msk (0x00000001U << GPDMA1_MASKSRCTRAN_WE_CH0_Pos)
\r
5234 #define GPDMA1_MASKSRCTRAN_WE_CH1_Pos (9U)
\r
5235 #define GPDMA1_MASKSRCTRAN_WE_CH1_Msk (0x00000001U << GPDMA1_MASKSRCTRAN_WE_CH1_Pos)
\r
5237 #define GPDMA1_MASKSRCTRAN_WE_CH2_Pos (10U)
\r
5238 #define GPDMA1_MASKSRCTRAN_WE_CH2_Msk (0x00000001U << GPDMA1_MASKSRCTRAN_WE_CH2_Pos)
\r
5240 #define GPDMA1_MASKSRCTRAN_WE_CH3_Pos (11U)
\r
5241 #define GPDMA1_MASKSRCTRAN_WE_CH3_Msk (0x00000001U << GPDMA1_MASKSRCTRAN_WE_CH3_Pos)
\r
5243 #define GPDMA1_MASKSRCTRAN_CH0_Pos (0U)
\r
5244 #define GPDMA1_MASKSRCTRAN_CH0_Msk (0x00000001U << GPDMA1_MASKSRCTRAN_CH0_Pos)
\r
5246 #define GPDMA1_MASKSRCTRAN_CH1_Pos (1U)
\r
5247 #define GPDMA1_MASKSRCTRAN_CH1_Msk (0x00000001U << GPDMA1_MASKSRCTRAN_CH1_Pos)
\r
5249 #define GPDMA1_MASKSRCTRAN_CH2_Pos (2U)
\r
5250 #define GPDMA1_MASKSRCTRAN_CH2_Msk (0x00000001U << GPDMA1_MASKSRCTRAN_CH2_Pos)
\r
5252 #define GPDMA1_MASKSRCTRAN_CH3_Pos (3U)
\r
5253 #define GPDMA1_MASKSRCTRAN_CH3_Msk (0x00000001U << GPDMA1_MASKSRCTRAN_CH3_Pos)
\r
5255 /* GPDMA1_MASKDSTTRAN = Mask for Raw IntBlock Status*/
\r
5256 #define GPDMA1_MASKDSTTRAN_WE_CH0_Pos (8U)
\r
5257 #define GPDMA1_MASKDSTTRAN_WE_CH0_Msk (0x00000001U << GPDMA1_MASKDSTTRAN_WE_CH0_Pos)
\r
5259 #define GPDMA1_MASKDSTTRAN_WE_CH1_Pos (9U)
\r
5260 #define GPDMA1_MASKDSTTRAN_WE_CH1_Msk (0x00000001U << GPDMA1_MASKDSTTRAN_WE_CH1_Pos)
\r
5262 #define GPDMA1_MASKDSTTRAN_WE_CH2_Pos (10U)
\r
5263 #define GPDMA1_MASKDSTTRAN_WE_CH2_Msk (0x00000001U << GPDMA1_MASKDSTTRAN_WE_CH2_Pos)
\r
5265 #define GPDMA1_MASKDSTTRAN_WE_CH3_Pos (11U)
\r
5266 #define GPDMA1_MASKDSTTRAN_WE_CH3_Msk (0x00000001U << GPDMA1_MASKDSTTRAN_WE_CH3_Pos)
\r
5268 #define GPDMA1_MASKDSTTRAN_CH0_Pos (0U)
\r
5269 #define GPDMA1_MASKDSTTRAN_CH0_Msk (0x00000001U << GPDMA1_MASKDSTTRAN_CH0_Pos)
\r
5271 #define GPDMA1_MASKDSTTRAN_CH1_Pos (1U)
\r
5272 #define GPDMA1_MASKDSTTRAN_CH1_Msk (0x00000001U << GPDMA1_MASKDSTTRAN_CH1_Pos)
\r
5274 #define GPDMA1_MASKDSTTRAN_CH2_Pos (2U)
\r
5275 #define GPDMA1_MASKDSTTRAN_CH2_Msk (0x00000001U << GPDMA1_MASKDSTTRAN_CH2_Pos)
\r
5277 #define GPDMA1_MASKDSTTRAN_CH3_Pos (3U)
\r
5278 #define GPDMA1_MASKDSTTRAN_CH3_Msk (0x00000001U << GPDMA1_MASKDSTTRAN_CH3_Pos)
\r
5280 /* GPDMA1_MASKERR = Mask for Raw IntErr Status*/
\r
5281 #define GPDMA1_MASKERR_WE_CH0_Pos (8U)
\r
5282 #define GPDMA1_MASKERR_WE_CH0_Msk (0x00000001U << GPDMA1_MASKERR_WE_CH0_Pos)
\r
5284 #define GPDMA1_MASKERR_WE_CH1_Pos (9U)
\r
5285 #define GPDMA1_MASKERR_WE_CH1_Msk (0x00000001U << GPDMA1_MASKERR_WE_CH1_Pos)
\r
5287 #define GPDMA1_MASKERR_WE_CH2_Pos (10U)
\r
5288 #define GPDMA1_MASKERR_WE_CH2_Msk (0x00000001U << GPDMA1_MASKERR_WE_CH2_Pos)
\r
5290 #define GPDMA1_MASKERR_WE_CH3_Pos (11U)
\r
5291 #define GPDMA1_MASKERR_WE_CH3_Msk (0x00000001U << GPDMA1_MASKERR_WE_CH3_Pos)
\r
5293 #define GPDMA1_MASKERR_CH0_Pos (0U)
\r
5294 #define GPDMA1_MASKERR_CH0_Msk (0x00000001U << GPDMA1_MASKERR_CH0_Pos)
\r
5296 #define GPDMA1_MASKERR_CH1_Pos (1U)
\r
5297 #define GPDMA1_MASKERR_CH1_Msk (0x00000001U << GPDMA1_MASKERR_CH1_Pos)
\r
5299 #define GPDMA1_MASKERR_CH2_Pos (2U)
\r
5300 #define GPDMA1_MASKERR_CH2_Msk (0x00000001U << GPDMA1_MASKERR_CH2_Pos)
\r
5302 #define GPDMA1_MASKERR_CH3_Pos (3U)
\r
5303 #define GPDMA1_MASKERR_CH3_Msk (0x00000001U << GPDMA1_MASKERR_CH3_Pos)
\r
5305 /* GPDMA1_CLEARTFR = IntTfr Status*/
\r
5306 #define GPDMA1_CLEARTFR_CH0_Pos (0U)
\r
5307 #define GPDMA1_CLEARTFR_CH0_Msk (0x00000001U << GPDMA1_CLEARTFR_CH0_Pos)
\r
5309 #define GPDMA1_CLEARTFR_CH1_Pos (1U)
\r
5310 #define GPDMA1_CLEARTFR_CH1_Msk (0x00000001U << GPDMA1_CLEARTFR_CH1_Pos)
\r
5312 #define GPDMA1_CLEARTFR_CH2_Pos (2U)
\r
5313 #define GPDMA1_CLEARTFR_CH2_Msk (0x00000001U << GPDMA1_CLEARTFR_CH2_Pos)
\r
5315 #define GPDMA1_CLEARTFR_CH3_Pos (3U)
\r
5316 #define GPDMA1_CLEARTFR_CH3_Msk (0x00000001U << GPDMA1_CLEARTFR_CH3_Pos)
\r
5318 /* GPDMA1_CLEARBLOCK = IntBlock Status*/
\r
5319 #define GPDMA1_CLEARBLOCK_CH0_Pos (0U)
\r
5320 #define GPDMA1_CLEARBLOCK_CH0_Msk (0x00000001U << GPDMA1_CLEARBLOCK_CH0_Pos)
\r
5322 #define GPDMA1_CLEARBLOCK_CH1_Pos (1U)
\r
5323 #define GPDMA1_CLEARBLOCK_CH1_Msk (0x00000001U << GPDMA1_CLEARBLOCK_CH1_Pos)
\r
5325 #define GPDMA1_CLEARBLOCK_CH2_Pos (2U)
\r
5326 #define GPDMA1_CLEARBLOCK_CH2_Msk (0x00000001U << GPDMA1_CLEARBLOCK_CH2_Pos)
\r
5328 #define GPDMA1_CLEARBLOCK_CH3_Pos (3U)
\r
5329 #define GPDMA1_CLEARBLOCK_CH3_Msk (0x00000001U << GPDMA1_CLEARBLOCK_CH3_Pos)
\r
5331 /* GPDMA1_CLEARSRCTRAN = IntSrcTran Status*/
\r
5332 #define GPDMA1_CLEARSRCTRAN_CH0_Pos (0U)
\r
5333 #define GPDMA1_CLEARSRCTRAN_CH0_Msk (0x00000001U << GPDMA1_CLEARSRCTRAN_CH0_Pos)
\r
5335 #define GPDMA1_CLEARSRCTRAN_CH1_Pos (1U)
\r
5336 #define GPDMA1_CLEARSRCTRAN_CH1_Msk (0x00000001U << GPDMA1_CLEARSRCTRAN_CH1_Pos)
\r
5338 #define GPDMA1_CLEARSRCTRAN_CH2_Pos (2U)
\r
5339 #define GPDMA1_CLEARSRCTRAN_CH2_Msk (0x00000001U << GPDMA1_CLEARSRCTRAN_CH2_Pos)
\r
5341 #define GPDMA1_CLEARSRCTRAN_CH3_Pos (3U)
\r
5342 #define GPDMA1_CLEARSRCTRAN_CH3_Msk (0x00000001U << GPDMA1_CLEARSRCTRAN_CH3_Pos)
\r
5344 /* GPDMA1_CLEARDSTTRAN = IntBlock Status*/
\r
5345 #define GPDMA1_CLEARDSTTRAN_CH0_Pos (0U)
\r
5346 #define GPDMA1_CLEARDSTTRAN_CH0_Msk (0x00000001U << GPDMA1_CLEARDSTTRAN_CH0_Pos)
\r
5348 #define GPDMA1_CLEARDSTTRAN_CH1_Pos (1U)
\r
5349 #define GPDMA1_CLEARDSTTRAN_CH1_Msk (0x00000001U << GPDMA1_CLEARDSTTRAN_CH1_Pos)
\r
5351 #define GPDMA1_CLEARDSTTRAN_CH2_Pos (2U)
\r
5352 #define GPDMA1_CLEARDSTTRAN_CH2_Msk (0x00000001U << GPDMA1_CLEARDSTTRAN_CH2_Pos)
\r
5354 #define GPDMA1_CLEARDSTTRAN_CH3_Pos (3U)
\r
5355 #define GPDMA1_CLEARDSTTRAN_CH3_Msk (0x00000001U << GPDMA1_CLEARDSTTRAN_CH3_Pos)
\r
5357 /* GPDMA1_CLEARERR = IntErr Status*/
\r
5358 #define GPDMA1_CLEARERR_CH0_Pos (0U)
\r
5359 #define GPDMA1_CLEARERR_CH0_Msk (0x00000001U << GPDMA1_CLEARERR_CH0_Pos)
\r
5361 #define GPDMA1_CLEARERR_CH1_Pos (1U)
\r
5362 #define GPDMA1_CLEARERR_CH1_Msk (0x00000001U << GPDMA1_CLEARERR_CH1_Pos)
\r
5364 #define GPDMA1_CLEARERR_CH2_Pos (2U)
\r
5365 #define GPDMA1_CLEARERR_CH2_Msk (0x00000001U << GPDMA1_CLEARERR_CH2_Pos)
\r
5367 #define GPDMA1_CLEARERR_CH3_Pos (3U)
\r
5368 #define GPDMA1_CLEARERR_CH3_Msk (0x00000001U << GPDMA1_CLEARERR_CH3_Pos)
\r
5370 /* GPDMA1_STATUSINT = Combined Interrupt Status Register*/
\r
5371 #define GPDMA1_STATUSINT_ERR_Pos (4U)
\r
5372 #define GPDMA1_STATUSINT_ERR_Msk (0x00000001U << GPDMA1_STATUSINT_ERR_Pos)
\r
5374 #define GPDMA1_STATUSINT_DSTT_Pos (3U)
\r
5375 #define GPDMA1_STATUSINT_DSTT_Msk (0x00000001U << GPDMA1_STATUSINT_DSTT_Pos)
\r
5377 #define GPDMA1_STATUSINT_SRCT_Pos (2U)
\r
5378 #define GPDMA1_STATUSINT_SRCT_Msk (0x00000001U << GPDMA1_STATUSINT_SRCT_Pos)
\r
5380 #define GPDMA1_STATUSINT_BLOCK_Pos (1U)
\r
5381 #define GPDMA1_STATUSINT_BLOCK_Msk (0x00000001U << GPDMA1_STATUSINT_BLOCK_Pos)
\r
5383 #define GPDMA1_STATUSINT_TFR_Pos (0U)
\r
5384 #define GPDMA1_STATUSINT_TFR_Msk (0x00000001U << GPDMA1_STATUSINT_TFR_Pos)
\r
5386 /* GPDMA1_REQSRCREG = Source Software Transaction Request Register*/
\r
5387 #define GPDMA1_REQSRCREG_WE_CH0_Pos (8U)
\r
5388 #define GPDMA1_REQSRCREG_WE_CH0_Msk (0x00000001U << GPDMA1_REQSRCREG_WE_CH0_Pos)
\r
5390 #define GPDMA1_REQSRCREG_WE_CH1_Pos (9U)
\r
5391 #define GPDMA1_REQSRCREG_WE_CH1_Msk (0x00000001U << GPDMA1_REQSRCREG_WE_CH1_Pos)
\r
5393 #define GPDMA1_REQSRCREG_WE_CH2_Pos (10U)
\r
5394 #define GPDMA1_REQSRCREG_WE_CH2_Msk (0x00000001U << GPDMA1_REQSRCREG_WE_CH2_Pos)
\r
5396 #define GPDMA1_REQSRCREG_WE_CH3_Pos (11U)
\r
5397 #define GPDMA1_REQSRCREG_WE_CH3_Msk (0x00000001U << GPDMA1_REQSRCREG_WE_CH3_Pos)
\r
5399 #define GPDMA1_REQSRCREG_CH0_Pos (0U)
\r
5400 #define GPDMA1_REQSRCREG_CH0_Msk (0x00000001U << GPDMA1_REQSRCREG_CH0_Pos)
\r
5402 #define GPDMA1_REQSRCREG_CH1_Pos (1U)
\r
5403 #define GPDMA1_REQSRCREG_CH1_Msk (0x00000001U << GPDMA1_REQSRCREG_CH1_Pos)
\r
5405 #define GPDMA1_REQSRCREG_CH2_Pos (2U)
\r
5406 #define GPDMA1_REQSRCREG_CH2_Msk (0x00000001U << GPDMA1_REQSRCREG_CH2_Pos)
\r
5408 #define GPDMA1_REQSRCREG_CH3_Pos (3U)
\r
5409 #define GPDMA1_REQSRCREG_CH3_Msk (0x00000001U << GPDMA1_REQSRCREG_CH3_Pos)
\r
5411 /* GPDMA1_REQDSTREG = Destination Software Transaction Request Register*/
\r
5412 #define GPDMA1_REQDSTREG_WE_CH0_Pos (8U)
\r
5413 #define GPDMA1_REQDSTREG_WE_CH0_Msk (0x00000001U << GPDMA1_REQDSTREG_WE_CH0_Pos)
\r
5415 #define GPDMA1_REQDSTREG_WE_CH1_Pos (9U)
\r
5416 #define GPDMA1_REQDSTREG_WE_CH1_Msk (0x00000001U << GPDMA1_REQDSTREG_WE_CH1_Pos)
\r
5418 #define GPDMA1_REQDSTREG_WE_CH2_Pos (10U)
\r
5419 #define GPDMA1_REQDSTREG_WE_CH2_Msk (0x00000001U << GPDMA1_REQDSTREG_WE_CH2_Pos)
\r
5421 #define GPDMA1_REQDSTREG_WE_CH3_Pos (11U)
\r
5422 #define GPDMA1_REQDSTREG_WE_CH3_Msk (0x00000001U << GPDMA1_REQDSTREG_WE_CH3_Pos)
\r
5424 #define GPDMA1_REQDSTREG_CH0_Pos (0U)
\r
5425 #define GPDMA1_REQDSTREG_CH0_Msk (0x00000001U << GPDMA1_REQDSTREG_CH0_Pos)
\r
5427 #define GPDMA1_REQDSTREG_CH1_Pos (1U)
\r
5428 #define GPDMA1_REQDSTREG_CH1_Msk (0x00000001U << GPDMA1_REQDSTREG_CH1_Pos)
\r
5430 #define GPDMA1_REQDSTREG_CH2_Pos (2U)
\r
5431 #define GPDMA1_REQDSTREG_CH2_Msk (0x00000001U << GPDMA1_REQDSTREG_CH2_Pos)
\r
5433 #define GPDMA1_REQDSTREG_CH3_Pos (3U)
\r
5434 #define GPDMA1_REQDSTREG_CH3_Msk (0x00000001U << GPDMA1_REQDSTREG_CH3_Pos)
\r
5436 /* GPDMA1_SGLREQSRCREG = Single Source Transaction Request Register*/
\r
5437 #define GPDMA1_SGLREQSRCREG_WE_CH0_Pos (8U)
\r
5438 #define GPDMA1_SGLREQSRCREG_WE_CH0_Msk (0x00000001U << GPDMA1_SGLREQSRCREG_WE_CH0_Pos)
\r
5440 #define GPDMA1_SGLREQSRCREG_WE_CH1_Pos (9U)
\r
5441 #define GPDMA1_SGLREQSRCREG_WE_CH1_Msk (0x00000001U << GPDMA1_SGLREQSRCREG_WE_CH1_Pos)
\r
5443 #define GPDMA1_SGLREQSRCREG_WE_CH2_Pos (10U)
\r
5444 #define GPDMA1_SGLREQSRCREG_WE_CH2_Msk (0x00000001U << GPDMA1_SGLREQSRCREG_WE_CH2_Pos)
\r
5446 #define GPDMA1_SGLREQSRCREG_WE_CH3_Pos (11U)
\r
5447 #define GPDMA1_SGLREQSRCREG_WE_CH3_Msk (0x00000001U << GPDMA1_SGLREQSRCREG_WE_CH3_Pos)
\r
5449 #define GPDMA1_SGLREQSRCREG_CH0_Pos (0U)
\r
5450 #define GPDMA1_SGLREQSRCREG_CH0_Msk (0x00000001U << GPDMA1_SGLREQSRCREG_CH0_Pos)
\r
5452 #define GPDMA1_SGLREQSRCREG_CH1_Pos (1U)
\r
5453 #define GPDMA1_SGLREQSRCREG_CH1_Msk (0x00000001U << GPDMA1_SGLREQSRCREG_CH1_Pos)
\r
5455 #define GPDMA1_SGLREQSRCREG_CH2_Pos (2U)
\r
5456 #define GPDMA1_SGLREQSRCREG_CH2_Msk (0x00000001U << GPDMA1_SGLREQSRCREG_CH2_Pos)
\r
5458 #define GPDMA1_SGLREQSRCREG_CH3_Pos (3U)
\r
5459 #define GPDMA1_SGLREQSRCREG_CH3_Msk (0x00000001U << GPDMA1_SGLREQSRCREG_CH3_Pos)
\r
5461 /* GPDMA1_SGLREQDSTREG = Single Destination Transaction Request Register*/
\r
5462 #define GPDMA1_SGLREQDSTREG_WE_CH0_Pos (8U)
\r
5463 #define GPDMA1_SGLREQDSTREG_WE_CH0_Msk (0x00000001U << GPDMA1_SGLREQDSTREG_WE_CH0_Pos)
\r
5465 #define GPDMA1_SGLREQDSTREG_WE_CH1_Pos (9U)
\r
5466 #define GPDMA1_SGLREQDSTREG_WE_CH1_Msk (0x00000001U << GPDMA1_SGLREQDSTREG_WE_CH1_Pos)
\r
5468 #define GPDMA1_SGLREQDSTREG_WE_CH2_Pos (10U)
\r
5469 #define GPDMA1_SGLREQDSTREG_WE_CH2_Msk (0x00000001U << GPDMA1_SGLREQDSTREG_WE_CH2_Pos)
\r
5471 #define GPDMA1_SGLREQDSTREG_WE_CH3_Pos (11U)
\r
5472 #define GPDMA1_SGLREQDSTREG_WE_CH3_Msk (0x00000001U << GPDMA1_SGLREQDSTREG_WE_CH3_Pos)
\r
5474 #define GPDMA1_SGLREQDSTREG_CH0_Pos (0U)
\r
5475 #define GPDMA1_SGLREQDSTREG_CH0_Msk (0x00000001U << GPDMA1_SGLREQDSTREG_CH0_Pos)
\r
5477 #define GPDMA1_SGLREQDSTREG_CH1_Pos (1U)
\r
5478 #define GPDMA1_SGLREQDSTREG_CH1_Msk (0x00000001U << GPDMA1_SGLREQDSTREG_CH1_Pos)
\r
5480 #define GPDMA1_SGLREQDSTREG_CH2_Pos (2U)
\r
5481 #define GPDMA1_SGLREQDSTREG_CH2_Msk (0x00000001U << GPDMA1_SGLREQDSTREG_CH2_Pos)
\r
5483 #define GPDMA1_SGLREQDSTREG_CH3_Pos (3U)
\r
5484 #define GPDMA1_SGLREQDSTREG_CH3_Msk (0x00000001U << GPDMA1_SGLREQDSTREG_CH3_Pos)
\r
5486 /* GPDMA1_LSTSRCREG = Last Source Transaction Request Register*/
\r
5487 #define GPDMA1_LSTSRCREG_WE_CH0_Pos (8U)
\r
5488 #define GPDMA1_LSTSRCREG_WE_CH0_Msk (0x00000001U << GPDMA1_LSTSRCREG_WE_CH0_Pos)
\r
5490 #define GPDMA1_LSTSRCREG_WE_CH1_Pos (9U)
\r
5491 #define GPDMA1_LSTSRCREG_WE_CH1_Msk (0x00000001U << GPDMA1_LSTSRCREG_WE_CH1_Pos)
\r
5493 #define GPDMA1_LSTSRCREG_WE_CH2_Pos (10U)
\r
5494 #define GPDMA1_LSTSRCREG_WE_CH2_Msk (0x00000001U << GPDMA1_LSTSRCREG_WE_CH2_Pos)
\r
5496 #define GPDMA1_LSTSRCREG_WE_CH3_Pos (11U)
\r
5497 #define GPDMA1_LSTSRCREG_WE_CH3_Msk (0x00000001U << GPDMA1_LSTSRCREG_WE_CH3_Pos)
\r
5499 #define GPDMA1_LSTSRCREG_CH0_Pos (0U)
\r
5500 #define GPDMA1_LSTSRCREG_CH0_Msk (0x00000001U << GPDMA1_LSTSRCREG_CH0_Pos)
\r
5502 #define GPDMA1_LSTSRCREG_CH1_Pos (1U)
\r
5503 #define GPDMA1_LSTSRCREG_CH1_Msk (0x00000001U << GPDMA1_LSTSRCREG_CH1_Pos)
\r
5505 #define GPDMA1_LSTSRCREG_CH2_Pos (2U)
\r
5506 #define GPDMA1_LSTSRCREG_CH2_Msk (0x00000001U << GPDMA1_LSTSRCREG_CH2_Pos)
\r
5508 #define GPDMA1_LSTSRCREG_CH3_Pos (3U)
\r
5509 #define GPDMA1_LSTSRCREG_CH3_Msk (0x00000001U << GPDMA1_LSTSRCREG_CH3_Pos)
\r
5511 /* GPDMA1_LSTDSTREG = Last Destination Transaction Request Register*/
\r
5512 #define GPDMA1_LSTDSTREG_WE_CH0_Pos (8U)
\r
5513 #define GPDMA1_LSTDSTREG_WE_CH0_Msk (0x00000001U << GPDMA1_LSTDSTREG_WE_CH0_Pos)
\r
5515 #define GPDMA1_LSTDSTREG_WE_CH1_Pos (9U)
\r
5516 #define GPDMA1_LSTDSTREG_WE_CH1_Msk (0x00000001U << GPDMA1_LSTDSTREG_WE_CH1_Pos)
\r
5518 #define GPDMA1_LSTDSTREG_WE_CH2_Pos (10U)
\r
5519 #define GPDMA1_LSTDSTREG_WE_CH2_Msk (0x00000001U << GPDMA1_LSTDSTREG_WE_CH2_Pos)
\r
5521 #define GPDMA1_LSTDSTREG_WE_CH3_Pos (11U)
\r
5522 #define GPDMA1_LSTDSTREG_WE_CH3_Msk (0x00000001U << GPDMA1_LSTDSTREG_WE_CH3_Pos)
\r
5524 #define GPDMA1_LSTDSTREG_CH0_Pos (0U)
\r
5525 #define GPDMA1_LSTDSTREG_CH0_Msk (0x00000001U << GPDMA1_LSTDSTREG_CH0_Pos)
\r
5527 #define GPDMA1_LSTDSTREG_CH1_Pos (1U)
\r
5528 #define GPDMA1_LSTDSTREG_CH1_Msk (0x00000001U << GPDMA1_LSTDSTREG_CH1_Pos)
\r
5530 #define GPDMA1_LSTDSTREG_CH2_Pos (2U)
\r
5531 #define GPDMA1_LSTDSTREG_CH2_Msk (0x00000001U << GPDMA1_LSTDSTREG_CH2_Pos)
\r
5533 #define GPDMA1_LSTDSTREG_CH3_Pos (3U)
\r
5534 #define GPDMA1_LSTDSTREG_CH3_Msk (0x00000001U << GPDMA1_LSTDSTREG_CH3_Pos)
\r
5536 /* GPDMA1_DMACFGREG = GPDMA Configuration Register*/
\r
5537 #define GPDMA1_DMACFGREG_DMA_EN_Pos (0U)
\r
5538 #define GPDMA1_DMACFGREG_DMA_EN_Msk (0x00000001U << GPDMA1_DMACFGREG_DMA_EN_Pos)
\r
5540 /* GPDMA1_CHENREG = GPDMA Channel Enable Register*/
\r
5541 #define GPDMA1_CHENREG_WE_CH_Pos (8U)
\r
5542 #define GPDMA1_CHENREG_WE_CH_Msk (0x0000000FU << GPDMA1_CHENREG_WE_CH_Pos)
\r
5544 #define GPDMA1_CHENREG_CH_Pos (0U)
\r
5545 #define GPDMA1_CHENREG_CH_Msk (0x0000000FU << GPDMA1_CHENREG_CH_Pos)
\r
5547 /* GPDMA1_ID = GPDMA1 ID Register*/
\r
5548 #define GPDMA1_ID_VALUE_Pos (0U)
\r
5549 #define GPDMA1_ID_VALUE_Msk (0xFFFFFFFFU << GPDMA1_ID_VALUE_Pos)
\r
5551 /* GPDMA1_TYPE = GPDMA Component Type*/
\r
5552 #define GPDMA1_TYPE_VALUE_Pos (0U)
\r
5553 #define GPDMA1_TYPE_VALUE_Msk (0xFFFFFFFFU << GPDMA1_TYPE_VALUE_Pos)
\r
5555 /* GPDMA1_VERSION = DMA Component Version*/
\r
5556 #define GPDMA1_VERSION_VALUE_Pos (0U)
\r
5557 #define GPDMA1_VERSION_VALUE_Msk (0xFFFFFFFFU << GPDMA1_VERSION_VALUE_Pos)
\r
5561 /*** GPDMA0 Bit Fileds *******************/
\r
5562 /***************************************************************************/
\r
5565 /* GPDMA0_CH_SARx = Source Address Register for Channel 0*/
\r
5566 #define GPDMA0_CH_SAR_SAR_Pos (0U)
\r
5567 #define GPDMA0_CH_SAR_SAR_Msk (0xFFFFFFFFU << GPDMA0_CH_SAR_SAR_Pos)
\r
5569 /* GPDMA0_CH_DARx = Destination Address Register for Channel 0*/
\r
5570 #define GPDMA0_CH_DAR_DAR_Pos (0U)
\r
5571 #define GPDMA0_CH_DAR_DAR_Msk (0xFFFFFFFFU << GPDMA0_CH_DAR_DAR_Pos)
\r
5573 /* GPDMA0_CH_LLPx = Linked List Pointer Register for Channel 0*/
\r
5574 #define GPDMA0_CH_LLP_LOC_Pos (2U)
\r
5575 #define GPDMA0_CH_LLP_LOC_Msk (0x3FFFFFFFU << GPDMA0_CH_LLP_LOC_Pos)
\r
5577 /* GPDMA0_CH_CTLL = Control Register for Channel x Low Word*/
\r
5578 #define GPDMA0_CH_CTLL_LLP_SRC_EN_Pos (28U)
\r
5579 #define GPDMA0_CH_CTLL_LLP_SRC_EN_Msk (0x00000001U << GPDMA0_CH_CTLL_LLP_SRC_EN_Pos)
\r
5581 #define GPDMA0_CH_CTLL_LLP_DST_EN_Pos (27U)
\r
5582 #define GPDMA0_CH_CTLL_LLP_DST_EN_Msk (0x00000001U << GPDMA0_CH_CTLL_LLP_DST_EN_Pos)
\r
5584 #define GPDMA0_CH_CTLL_TT_FC_Pos (20U)
\r
5585 #define GPDMA0_CH_CTLL_TT_FC_Msk (0x00000007U << GPDMA0_CH_CTLL_TT_FC_Pos)
\r
5587 #define GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos (18U)
\r
5588 #define GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk (0x00000001U << GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos)
\r
5590 #define GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos (17U)
\r
5591 #define GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk (0x00000001U << GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos)
\r
5593 #define GPDMA0_CH_CTLL_SRC_MSIZE_Pos (14U)
\r
5594 #define GPDMA0_CH_CTLL_SRC_MSIZE_Msk (0x00000007U << GPDMA0_CH_CTLL_SRC_MSIZE_Pos)
\r
5596 #define GPDMA0_CH_CTLL_DEST_MSIZE_Pos (11U)
\r
5597 #define GPDMA0_CH_CTLL_DEST_MSIZE_Msk (0x00000007U << GPDMA0_CH_CTLL_DEST_MSIZE_Pos)
\r
5599 #define GPDMA0_CH_CTLL_SINC_Pos (9U)
\r
5600 #define GPDMA0_CH_CTLL_SINC_Msk (0x00000003U << GPDMA0_CH_CTLL_SINC_Pos)
\r
5602 #define GPDMA0_CH_CTLL_DINC_Pos (7U)
\r
5603 #define GPDMA0_CH_CTLL_DINC_Msk (0x00000003U << GPDMA0_CH_CTLL_DINC_Pos)
\r
5605 #define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos (4U)
\r
5606 #define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Msk (0x00000007U << GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos)
\r
5608 #define GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos (1U)
\r
5609 #define GPDMA0_CH_CTLL_DST_TR_WIDTH_Msk (0x00000007U << GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos)
\r
5611 #define GPDMA0_CH_CTLL_INT_EN_Pos (0U)
\r
5612 #define GPDMA0_CH_CTLL_INT_EN_Msk (0x00000001U << GPDMA0_CH_CTLL_INT_EN_Pos)
\r
5614 /* GPDMA0_CH_CTLH = Control Register for Channel x High Word*/
\r
5615 #define GPDMA0_CH_CTLH_DONE_Pos (12U)
\r
5616 #define GPDMA0_CH_CTLH_DONE_Msk (0x00000001U << GPDMA0_CH_CTLH_DONE_Pos)
\r
5618 #define GPDMA0_CH_CTLH_BLOCK_TS_Pos (0U)
\r
5619 #define GPDMA0_CH_CTLH_BLOCK_TS_Msk (0x00000FFFU << GPDMA0_CH_CTLH_BLOCK_TS_Pos)
\r
5621 /* GPDMA0_CH_SSTATx = Source Status Register for Channel 0*/
\r
5622 #define GPDMA0_CH_SSTAT_SSTAT_Pos (0U)
\r
5623 #define GPDMA0_CH_SSTAT_SSTAT_Msk (0xFFFFFFFFU << GPDMA0_CH_SSTAT_SSTAT_Pos)
\r
5625 /* GPDMA0_CH_DSTATx = Destination Status Register for Channel 0*/
\r
5626 #define GPDMA0_CH_DSTAT_DSTAT_Pos (0U)
\r
5627 #define GPDMA0_CH_DSTAT_DSTAT_Msk (0xFFFFFFFFU << GPDMA0_CH_DSTAT_DSTAT_Pos)
\r
5629 /* GPDMA0_CH_SSTATARx = Source Status Address Register for Channel 0*/
\r
5630 #define GPDMA0_CH_SSTATAR_SSTATAR_Pos (0U)
\r
5631 #define GPDMA0_CH_SSTATAR_SSTATAR_Msk (0xFFFFFFFFU << GPDMA0_CH_SSTATAR_SSTATAR_Pos)
\r
5633 /* GPDMA0_CH_DSTATARx = Destination Status Address Register for Channel 0*/
\r
5634 #define GPDMA0_CH_DSTATAR_DSTATAR_Pos (0U)
\r
5635 #define GPDMA0_CH_DSTATAR_DSTATAR_Msk (0xFFFFFFFFU << GPDMA0_CH_DSTATAR_DSTATAR_Pos)
\r
5637 /* GPDMA0_CH_CFGL = Configuration Register for Channel x Low Word*/
\r
5638 #define GPDMA0_CH_CFGL_RELOAD_DST_Pos (31U)
\r
5639 #define GPDMA0_CH_CFGL_RELOAD_DST_Msk (0x00000001U << GPDMA0_CH_CFGL_RELOAD_DST_Pos)
\r
5641 #define GPDMA0_CH_CFGL_RELOAD_SRC_Pos (30U)
\r
5642 #define GPDMA0_CH_CFGL_RELOAD_SRC_Msk (0x00000001U << GPDMA0_CH_CFGL_RELOAD_SRC_Pos)
\r
5644 #define GPDMA0_CH_CFGL_MAX_ABRST_Pos (20U)
\r
5645 #define GPDMA0_CH_CFGL_MAX_ABRST_Msk (0x000003FFU << GPDMA0_CH_CFGL_MAX_ABRST_Pos)
\r
5647 #define GPDMA0_CH_CFGL_SRC_HS_POL_Pos (19U)
\r
5648 #define GPDMA0_CH_CFGL_SRC_HS_POL_Msk (0x00000001U << GPDMA0_CH_CFGL_SRC_HS_POL_Pos)
\r
5650 #define GPDMA0_CH_CFGL_DST_HS_POL_Pos (18U)
\r
5651 #define GPDMA0_CH_CFGL_DST_HS_POL_Msk (0x00000001U << GPDMA0_CH_CFGL_DST_HS_POL_Pos)
\r
5653 #define GPDMA0_CH_CFGL_LOCK_B_Pos (17U)
\r
5654 #define GPDMA0_CH_CFGL_LOCK_B_Msk (0x00000001U << GPDMA0_CH_CFGL_LOCK_B_Pos)
\r
5656 #define GPDMA0_CH_CFGL_LOCK_CH_Pos (16U)
\r
5657 #define GPDMA0_CH_CFGL_LOCK_CH_Msk (0x00000001U << GPDMA0_CH_CFGL_LOCK_CH_Pos)
\r
5659 #define GPDMA0_CH_CFGL_LOCK_B_L_Pos (14U)
\r
5660 #define GPDMA0_CH_CFGL_LOCK_B_L_Msk (0x00000003U << GPDMA0_CH_CFGL_LOCK_B_L_Pos)
\r
5662 #define GPDMA0_CH_CFGL_LOCK_CH_L_Pos (12U)
\r
5663 #define GPDMA0_CH_CFGL_LOCK_CH_L_Msk (0x00000003U << GPDMA0_CH_CFGL_LOCK_CH_L_Pos)
\r
5665 #define GPDMA0_CH_CFGL_HS_SEL_SRC_Pos (11U)
\r
5666 #define GPDMA0_CH_CFGL_HS_SEL_SRC_Msk (0x00000001U << GPDMA0_CH_CFGL_HS_SEL_SRC_Pos)
\r
5668 #define GPDMA0_CH_CFGL_HS_SEL_DST_Pos (10U)
\r
5669 #define GPDMA0_CH_CFGL_HS_SEL_DST_Msk (0x00000001U << GPDMA0_CH_CFGL_HS_SEL_DST_Pos)
\r
5671 #define GPDMA0_CH_CFGL_FIFO_EMPTY_Pos (9U)
\r
5672 #define GPDMA0_CH_CFGL_FIFO_EMPTY_Msk (0x00000001U << GPDMA0_CH_CFGL_FIFO_EMPTY_Pos)
\r
5674 #define GPDMA0_CH_CFGL_CH_SUSP_Pos (8U)
\r
5675 #define GPDMA0_CH_CFGL_CH_SUSP_Msk (0x00000001U << GPDMA0_CH_CFGL_CH_SUSP_Pos)
\r
5677 #define GPDMA0_CH_CFGL_CH_PRIOR_Pos (5U)
\r
5678 #define GPDMA0_CH_CFGL_CH_PRIOR_Msk (0x00000007U << GPDMA0_CH_CFGL_CH_PRIOR_Pos)
\r
5680 /* GPDMA0_CH_CFGH = Configuration Register for Channel x High Word*/
\r
5681 #define GPDMA0_CH_CFGH_DEST_PER_Pos (11U)
\r
5682 #define GPDMA0_CH_CFGH_DEST_PER_Msk (0x0000000FU << GPDMA0_CH_CFGH_DEST_PER_Pos)
\r
5684 #define GPDMA0_CH_CFGH_SRC_PER_Pos (7U)
\r
5685 #define GPDMA0_CH_CFGH_SRC_PER_Msk (0x0000000FU << GPDMA0_CH_CFGH_SRC_PER_Pos)
\r
5687 #define GPDMA0_CH_CFGH_SS_UPD_EN_Pos (6U)
\r
5688 #define GPDMA0_CH_CFGH_SS_UPD_EN_Msk (0x00000001U << GPDMA0_CH_CFGH_SS_UPD_EN_Pos)
\r
5690 #define GPDMA0_CH_CFGH_DS_UPD_EN_Pos (5U)
\r
5691 #define GPDMA0_CH_CFGH_DS_UPD_EN_Msk (0x00000001U << GPDMA0_CH_CFGH_DS_UPD_EN_Pos)
\r
5693 #define GPDMA0_CH_CFGH_PROTCTL_Pos (2U)
\r
5694 #define GPDMA0_CH_CFGH_PROTCTL_Msk (0x00000007U << GPDMA0_CH_CFGH_PROTCTL_Pos)
\r
5696 #define GPDMA0_CH_CFGH_FIFO_MODE_Pos (1U)
\r
5697 #define GPDMA0_CH_CFGH_FIFO_MODE_Msk (0x00000001U << GPDMA0_CH_CFGH_FIFO_MODE_Pos)
\r
5699 #define GPDMA0_CH_CFGH_FCMODE_Pos (0U)
\r
5700 #define GPDMA0_CH_CFGH_FCMODE_Msk (0x00000001U << GPDMA0_CH_CFGH_FCMODE_Pos)
\r
5702 /* GPDMA0_CH_SGRx = Source Gather Register for Channel 0*/
\r
5703 #define GPDMA0_CH_SGR_SGC_Pos (20U)
\r
5704 #define GPDMA0_CH_SGR_SGC_Msk (0x00000FFFU << GPDMA0_CH_SGR_SGC_Pos)
\r
5706 #define GPDMA0_CH_SGR_SGI_Pos (0U)
\r
5707 #define GPDMA0_CH_SGR_SGI_Msk (0x000FFFFFU << GPDMA0_CH_SGR_SGI_Pos)
\r
5709 /* GPDMA0_CH_DSRx = Destination Scatter Register for Channel 0*/
\r
5710 #define GPDMA0_CH_DSR_DSC_Pos (20U)
\r
5711 #define GPDMA0_CH_DSR_DSC_Msk (0x00000FFFU << GPDMA0_CH_DSR_DSC_Pos)
\r
5713 #define GPDMA0_CH_DSR_DSI_Pos (0U)
\r
5714 #define GPDMA0_CH_DSR_DSI_Msk (0x000FFFFFU << GPDMA0_CH_DSR_DSI_Pos)
\r
5716 /* GPDMA0_RAWTFR = Raw IntTfr Status*/
\r
5717 #define GPDMA0_RAWTFR_CH0_Pos (0U)
\r
5718 #define GPDMA0_RAWTFR_CH0_Msk (0x00000001U << GPDMA0_RAWTFR_CH0_Pos)
\r
5720 #define GPDMA0_RAWTFR_CH1_Pos (1U)
\r
5721 #define GPDMA0_RAWTFR_CH1_Msk (0x00000001U << GPDMA0_RAWTFR_CH1_Pos)
\r
5723 #define GPDMA0_RAWTFR_CH2_Pos (2U)
\r
5724 #define GPDMA0_RAWTFR_CH2_Msk (0x00000001U << GPDMA0_RAWTFR_CH2_Pos)
\r
5726 #define GPDMA0_RAWTFR_CH3_Pos (3U)
\r
5727 #define GPDMA0_RAWTFR_CH3_Msk (0x00000001U << GPDMA0_RAWTFR_CH3_Pos)
\r
5729 #define GPDMA0_RAWTFR_CH4_Pos (4U)
\r
5730 #define GPDMA0_RAWTFR_CH4_Msk (0x00000001U << GPDMA0_RAWTFR_CH4_Pos)
\r
5732 #define GPDMA0_RAWTFR_CH5_Pos (5U)
\r
5733 #define GPDMA0_RAWTFR_CH5_Msk (0x00000001U << GPDMA0_RAWTFR_CH5_Pos)
\r
5735 #define GPDMA0_RAWTFR_CH6_Pos (6U)
\r
5736 #define GPDMA0_RAWTFR_CH6_Msk (0x00000001U << GPDMA0_RAWTFR_CH6_Pos)
\r
5738 #define GPDMA0_RAWTFR_CH7_Pos (7U)
\r
5739 #define GPDMA0_RAWTFR_CH7_Msk (0x00000001U << GPDMA0_RAWTFR_CH7_Pos)
\r
5741 /* GPDMA0_RAWBLOCK = Raw IntBlock Status*/
\r
5742 #define GPDMA0_RAWBLOCK_CH0_Pos (0U)
\r
5743 #define GPDMA0_RAWBLOCK_CH0_Msk (0x00000001U << GPDMA0_RAWBLOCK_CH0_Pos)
\r
5745 #define GPDMA0_RAWBLOCK_CH1_Pos (1U)
\r
5746 #define GPDMA0_RAWBLOCK_CH1_Msk (0x00000001U << GPDMA0_RAWBLOCK_CH1_Pos)
\r
5748 #define GPDMA0_RAWBLOCK_CH2_Pos (2U)
\r
5749 #define GPDMA0_RAWBLOCK_CH2_Msk (0x00000001U << GPDMA0_RAWBLOCK_CH2_Pos)
\r
5751 #define GPDMA0_RAWBLOCK_CH3_Pos (3U)
\r
5752 #define GPDMA0_RAWBLOCK_CH3_Msk (0x00000001U << GPDMA0_RAWBLOCK_CH3_Pos)
\r
5754 #define GPDMA0_RAWBLOCK_CH4_Pos (4U)
\r
5755 #define GPDMA0_RAWBLOCK_CH4_Msk (0x00000001U << GPDMA0_RAWBLOCK_CH4_Pos)
\r
5757 #define GPDMA0_RAWBLOCK_CH5_Pos (5U)
\r
5758 #define GPDMA0_RAWBLOCK_CH5_Msk (0x00000001U << GPDMA0_RAWBLOCK_CH5_Pos)
\r
5760 #define GPDMA0_RAWBLOCK_CH6_Pos (6U)
\r
5761 #define GPDMA0_RAWBLOCK_CH6_Msk (0x00000001U << GPDMA0_RAWBLOCK_CH6_Pos)
\r
5763 #define GPDMA0_RAWBLOCK_CH7_Pos (7U)
\r
5764 #define GPDMA0_RAWBLOCK_CH7_Msk (0x00000001U << GPDMA0_RAWBLOCK_CH7_Pos)
\r
5766 /* GPDMA0_RAWSRCTRAN = Raw IntSrcTran Status*/
\r
5767 #define GPDMA0_RAWSRCTRAN_CH0_Pos (0U)
\r
5768 #define GPDMA0_RAWSRCTRAN_CH0_Msk (0x00000001U << GPDMA0_RAWSRCTRAN_CH0_Pos)
\r
5770 #define GPDMA0_RAWSRCTRAN_CH1_Pos (1U)
\r
5771 #define GPDMA0_RAWSRCTRAN_CH1_Msk (0x00000001U << GPDMA0_RAWSRCTRAN_CH1_Pos)
\r
5773 #define GPDMA0_RAWSRCTRAN_CH2_Pos (2U)
\r
5774 #define GPDMA0_RAWSRCTRAN_CH2_Msk (0x00000001U << GPDMA0_RAWSRCTRAN_CH2_Pos)
\r
5776 #define GPDMA0_RAWSRCTRAN_CH3_Pos (3U)
\r
5777 #define GPDMA0_RAWSRCTRAN_CH3_Msk (0x00000001U << GPDMA0_RAWSRCTRAN_CH3_Pos)
\r
5779 #define GPDMA0_RAWSRCTRAN_CH4_Pos (4U)
\r
5780 #define GPDMA0_RAWSRCTRAN_CH4_Msk (0x00000001U << GPDMA0_RAWSRCTRAN_CH4_Pos)
\r
5782 #define GPDMA0_RAWSRCTRAN_CH5_Pos (5U)
\r
5783 #define GPDMA0_RAWSRCTRAN_CH5_Msk (0x00000001U << GPDMA0_RAWSRCTRAN_CH5_Pos)
\r
5785 #define GPDMA0_RAWSRCTRAN_CH6_Pos (6U)
\r
5786 #define GPDMA0_RAWSRCTRAN_CH6_Msk (0x00000001U << GPDMA0_RAWSRCTRAN_CH6_Pos)
\r
5788 #define GPDMA0_RAWSRCTRAN_CH7_Pos (7U)
\r
5789 #define GPDMA0_RAWSRCTRAN_CH7_Msk (0x00000001U << GPDMA0_RAWSRCTRAN_CH7_Pos)
\r
5791 /* GPDMA0_RAWDSTTRAN = Raw IntBlock Status*/
\r
5792 #define GPDMA0_RAWDSTTRAN_CH0_Pos (0U)
\r
5793 #define GPDMA0_RAWDSTTRAN_CH0_Msk (0x00000001U << GPDMA0_RAWDSTTRAN_CH0_Pos)
\r
5795 #define GPDMA0_RAWDSTTRAN_CH1_Pos (1U)
\r
5796 #define GPDMA0_RAWDSTTRAN_CH1_Msk (0x00000001U << GPDMA0_RAWDSTTRAN_CH1_Pos)
\r
5798 #define GPDMA0_RAWDSTTRAN_CH2_Pos (2U)
\r
5799 #define GPDMA0_RAWDSTTRAN_CH2_Msk (0x00000001U << GPDMA0_RAWDSTTRAN_CH2_Pos)
\r
5801 #define GPDMA0_RAWDSTTRAN_CH3_Pos (3U)
\r
5802 #define GPDMA0_RAWDSTTRAN_CH3_Msk (0x00000001U << GPDMA0_RAWDSTTRAN_CH3_Pos)
\r
5804 #define GPDMA0_RAWDSTTRAN_CH4_Pos (4U)
\r
5805 #define GPDMA0_RAWDSTTRAN_CH4_Msk (0x00000001U << GPDMA0_RAWDSTTRAN_CH4_Pos)
\r
5807 #define GPDMA0_RAWDSTTRAN_CH5_Pos (5U)
\r
5808 #define GPDMA0_RAWDSTTRAN_CH5_Msk (0x00000001U << GPDMA0_RAWDSTTRAN_CH5_Pos)
\r
5810 #define GPDMA0_RAWDSTTRAN_CH6_Pos (6U)
\r
5811 #define GPDMA0_RAWDSTTRAN_CH6_Msk (0x00000001U << GPDMA0_RAWDSTTRAN_CH6_Pos)
\r
5813 #define GPDMA0_RAWDSTTRAN_CH7_Pos (7U)
\r
5814 #define GPDMA0_RAWDSTTRAN_CH7_Msk (0x00000001U << GPDMA0_RAWDSTTRAN_CH7_Pos)
\r
5816 /* GPDMA0_RAWERR = Raw IntErr Status*/
\r
5817 #define GPDMA0_RAWERR_CH0_Pos (0U)
\r
5818 #define GPDMA0_RAWERR_CH0_Msk (0x00000001U << GPDMA0_RAWERR_CH0_Pos)
\r
5820 #define GPDMA0_RAWERR_CH1_Pos (1U)
\r
5821 #define GPDMA0_RAWERR_CH1_Msk (0x00000001U << GPDMA0_RAWERR_CH1_Pos)
\r
5823 #define GPDMA0_RAWERR_CH2_Pos (2U)
\r
5824 #define GPDMA0_RAWERR_CH2_Msk (0x00000001U << GPDMA0_RAWERR_CH2_Pos)
\r
5826 #define GPDMA0_RAWERR_CH3_Pos (3U)
\r
5827 #define GPDMA0_RAWERR_CH3_Msk (0x00000001U << GPDMA0_RAWERR_CH3_Pos)
\r
5829 #define GPDMA0_RAWERR_CH4_Pos (4U)
\r
5830 #define GPDMA0_RAWERR_CH4_Msk (0x00000001U << GPDMA0_RAWERR_CH4_Pos)
\r
5832 #define GPDMA0_RAWERR_CH5_Pos (5U)
\r
5833 #define GPDMA0_RAWERR_CH5_Msk (0x00000001U << GPDMA0_RAWERR_CH5_Pos)
\r
5835 #define GPDMA0_RAWERR_CH6_Pos (6U)
\r
5836 #define GPDMA0_RAWERR_CH6_Msk (0x00000001U << GPDMA0_RAWERR_CH6_Pos)
\r
5838 #define GPDMA0_RAWERR_CH7_Pos (7U)
\r
5839 #define GPDMA0_RAWERR_CH7_Msk (0x00000001U << GPDMA0_RAWERR_CH7_Pos)
\r
5841 /* GPDMA0_STATUSTFR = IntTfr Status*/
\r
5842 #define GPDMA0_STATUSTFR_CH0_Pos (0U)
\r
5843 #define GPDMA0_STATUSTFR_CH0_Msk (0x00000001U << GPDMA0_STATUSTFR_CH0_Pos)
\r
5845 #define GPDMA0_STATUSTFR_CH1_Pos (1U)
\r
5846 #define GPDMA0_STATUSTFR_CH1_Msk (0x00000001U << GPDMA0_STATUSTFR_CH1_Pos)
\r
5848 #define GPDMA0_STATUSTFR_CH2_Pos (2U)
\r
5849 #define GPDMA0_STATUSTFR_CH2_Msk (0x00000001U << GPDMA0_STATUSTFR_CH2_Pos)
\r
5851 #define GPDMA0_STATUSTFR_CH3_Pos (3U)
\r
5852 #define GPDMA0_STATUSTFR_CH3_Msk (0x00000001U << GPDMA0_STATUSTFR_CH3_Pos)
\r
5854 #define GPDMA0_STATUSTFR_CH4_Pos (4U)
\r
5855 #define GPDMA0_STATUSTFR_CH4_Msk (0x00000001U << GPDMA0_STATUSTFR_CH4_Pos)
\r
5857 #define GPDMA0_STATUSTFR_CH5_Pos (5U)
\r
5858 #define GPDMA0_STATUSTFR_CH5_Msk (0x00000001U << GPDMA0_STATUSTFR_CH5_Pos)
\r
5860 #define GPDMA0_STATUSTFR_CH6_Pos (6U)
\r
5861 #define GPDMA0_STATUSTFR_CH6_Msk (0x00000001U << GPDMA0_STATUSTFR_CH6_Pos)
\r
5863 #define GPDMA0_STATUSTFR_CH7_Pos (7U)
\r
5864 #define GPDMA0_STATUSTFR_CH7_Msk (0x00000001U << GPDMA0_STATUSTFR_CH7_Pos)
\r
5866 /* GPDMA0_STATUSBLOCK = IntBlock Status*/
\r
5867 #define GPDMA0_STATUSBLOCK_CH0_Pos (0U)
\r
5868 #define GPDMA0_STATUSBLOCK_CH0_Msk (0x00000001U << GPDMA0_STATUSBLOCK_CH0_Pos)
\r
5870 #define GPDMA0_STATUSBLOCK_CH1_Pos (1U)
\r
5871 #define GPDMA0_STATUSBLOCK_CH1_Msk (0x00000001U << GPDMA0_STATUSBLOCK_CH1_Pos)
\r
5873 #define GPDMA0_STATUSBLOCK_CH2_Pos (2U)
\r
5874 #define GPDMA0_STATUSBLOCK_CH2_Msk (0x00000001U << GPDMA0_STATUSBLOCK_CH2_Pos)
\r
5876 #define GPDMA0_STATUSBLOCK_CH3_Pos (3U)
\r
5877 #define GPDMA0_STATUSBLOCK_CH3_Msk (0x00000001U << GPDMA0_STATUSBLOCK_CH3_Pos)
\r
5879 #define GPDMA0_STATUSBLOCK_CH4_Pos (4U)
\r
5880 #define GPDMA0_STATUSBLOCK_CH4_Msk (0x00000001U << GPDMA0_STATUSBLOCK_CH4_Pos)
\r
5882 #define GPDMA0_STATUSBLOCK_CH5_Pos (5U)
\r
5883 #define GPDMA0_STATUSBLOCK_CH5_Msk (0x00000001U << GPDMA0_STATUSBLOCK_CH5_Pos)
\r
5885 #define GPDMA0_STATUSBLOCK_CH6_Pos (6U)
\r
5886 #define GPDMA0_STATUSBLOCK_CH6_Msk (0x00000001U << GPDMA0_STATUSBLOCK_CH6_Pos)
\r
5888 #define GPDMA0_STATUSBLOCK_CH7_Pos (7U)
\r
5889 #define GPDMA0_STATUSBLOCK_CH7_Msk (0x00000001U << GPDMA0_STATUSBLOCK_CH7_Pos)
\r
5891 /* GPDMA0_STATUSSRCTRAN = IntSrcTran Status*/
\r
5892 #define GPDMA0_STATUSSRCTRAN_CH0_Pos (0U)
\r
5893 #define GPDMA0_STATUSSRCTRAN_CH0_Msk (0x00000001U << GPDMA0_STATUSSRCTRAN_CH0_Pos)
\r
5895 #define GPDMA0_STATUSSRCTRAN_CH1_Pos (1U)
\r
5896 #define GPDMA0_STATUSSRCTRAN_CH1_Msk (0x00000001U << GPDMA0_STATUSSRCTRAN_CH1_Pos)
\r
5898 #define GPDMA0_STATUSSRCTRAN_CH2_Pos (2U)
\r
5899 #define GPDMA0_STATUSSRCTRAN_CH2_Msk (0x00000001U << GPDMA0_STATUSSRCTRAN_CH2_Pos)
\r
5901 #define GPDMA0_STATUSSRCTRAN_CH3_Pos (3U)
\r
5902 #define GPDMA0_STATUSSRCTRAN_CH3_Msk (0x00000001U << GPDMA0_STATUSSRCTRAN_CH3_Pos)
\r
5904 #define GPDMA0_STATUSSRCTRAN_CH4_Pos (4U)
\r
5905 #define GPDMA0_STATUSSRCTRAN_CH4_Msk (0x00000001U << GPDMA0_STATUSSRCTRAN_CH4_Pos)
\r
5907 #define GPDMA0_STATUSSRCTRAN_CH5_Pos (5U)
\r
5908 #define GPDMA0_STATUSSRCTRAN_CH5_Msk (0x00000001U << GPDMA0_STATUSSRCTRAN_CH5_Pos)
\r
5910 #define GPDMA0_STATUSSRCTRAN_CH6_Pos (6U)
\r
5911 #define GPDMA0_STATUSSRCTRAN_CH6_Msk (0x00000001U << GPDMA0_STATUSSRCTRAN_CH6_Pos)
\r
5913 #define GPDMA0_STATUSSRCTRAN_CH7_Pos (7U)
\r
5914 #define GPDMA0_STATUSSRCTRAN_CH7_Msk (0x00000001U << GPDMA0_STATUSSRCTRAN_CH7_Pos)
\r
5916 /* GPDMA0_STATUSDSTTRAN = IntBlock Status*/
\r
5917 #define GPDMA0_STATUSDSTTRAN_CH0_Pos (0U)
\r
5918 #define GPDMA0_STATUSDSTTRAN_CH0_Msk (0x00000001U << GPDMA0_STATUSDSTTRAN_CH0_Pos)
\r
5920 #define GPDMA0_STATUSDSTTRAN_CH1_Pos (1U)
\r
5921 #define GPDMA0_STATUSDSTTRAN_CH1_Msk (0x00000001U << GPDMA0_STATUSDSTTRAN_CH1_Pos)
\r
5923 #define GPDMA0_STATUSDSTTRAN_CH2_Pos (2U)
\r
5924 #define GPDMA0_STATUSDSTTRAN_CH2_Msk (0x00000001U << GPDMA0_STATUSDSTTRAN_CH2_Pos)
\r
5926 #define GPDMA0_STATUSDSTTRAN_CH3_Pos (3U)
\r
5927 #define GPDMA0_STATUSDSTTRAN_CH3_Msk (0x00000001U << GPDMA0_STATUSDSTTRAN_CH3_Pos)
\r
5929 #define GPDMA0_STATUSDSTTRAN_CH4_Pos (4U)
\r
5930 #define GPDMA0_STATUSDSTTRAN_CH4_Msk (0x00000001U << GPDMA0_STATUSDSTTRAN_CH4_Pos)
\r
5932 #define GPDMA0_STATUSDSTTRAN_CH5_Pos (5U)
\r
5933 #define GPDMA0_STATUSDSTTRAN_CH5_Msk (0x00000001U << GPDMA0_STATUSDSTTRAN_CH5_Pos)
\r
5935 #define GPDMA0_STATUSDSTTRAN_CH6_Pos (6U)
\r
5936 #define GPDMA0_STATUSDSTTRAN_CH6_Msk (0x00000001U << GPDMA0_STATUSDSTTRAN_CH6_Pos)
\r
5938 #define GPDMA0_STATUSDSTTRAN_CH7_Pos (7U)
\r
5939 #define GPDMA0_STATUSDSTTRAN_CH7_Msk (0x00000001U << GPDMA0_STATUSDSTTRAN_CH7_Pos)
\r
5941 /* GPDMA0_STATUSERR = IntErr Status*/
\r
5942 #define GPDMA0_STATUSERR_CH0_Pos (0U)
\r
5943 #define GPDMA0_STATUSERR_CH0_Msk (0x00000001U << GPDMA0_STATUSERR_CH0_Pos)
\r
5945 #define GPDMA0_STATUSERR_CH1_Pos (1U)
\r
5946 #define GPDMA0_STATUSERR_CH1_Msk (0x00000001U << GPDMA0_STATUSERR_CH1_Pos)
\r
5948 #define GPDMA0_STATUSERR_CH2_Pos (2U)
\r
5949 #define GPDMA0_STATUSERR_CH2_Msk (0x00000001U << GPDMA0_STATUSERR_CH2_Pos)
\r
5951 #define GPDMA0_STATUSERR_CH3_Pos (3U)
\r
5952 #define GPDMA0_STATUSERR_CH3_Msk (0x00000001U << GPDMA0_STATUSERR_CH3_Pos)
\r
5954 #define GPDMA0_STATUSERR_CH4_Pos (4U)
\r
5955 #define GPDMA0_STATUSERR_CH4_Msk (0x00000001U << GPDMA0_STATUSERR_CH4_Pos)
\r
5957 #define GPDMA0_STATUSERR_CH5_Pos (5U)
\r
5958 #define GPDMA0_STATUSERR_CH5_Msk (0x00000001U << GPDMA0_STATUSERR_CH5_Pos)
\r
5960 #define GPDMA0_STATUSERR_CH6_Pos (6U)
\r
5961 #define GPDMA0_STATUSERR_CH6_Msk (0x00000001U << GPDMA0_STATUSERR_CH6_Pos)
\r
5963 #define GPDMA0_STATUSERR_CH7_Pos (7U)
\r
5964 #define GPDMA0_STATUSERR_CH7_Msk (0x00000001U << GPDMA0_STATUSERR_CH7_Pos)
\r
5966 /* GPDMA0_MASKTFR = Mask for Raw IntTfr Status*/
\r
5967 #define GPDMA0_MASKTFR_WE_CH0_Pos (8U)
\r
5968 #define GPDMA0_MASKTFR_WE_CH0_Msk (0x00000001U << GPDMA0_MASKTFR_WE_CH0_Pos)
\r
5970 #define GPDMA0_MASKTFR_WE_CH1_Pos (9U)
\r
5971 #define GPDMA0_MASKTFR_WE_CH1_Msk (0x00000001U << GPDMA0_MASKTFR_WE_CH1_Pos)
\r
5973 #define GPDMA0_MASKTFR_WE_CH2_Pos (10U)
\r
5974 #define GPDMA0_MASKTFR_WE_CH2_Msk (0x00000001U << GPDMA0_MASKTFR_WE_CH2_Pos)
\r
5976 #define GPDMA0_MASKTFR_WE_CH3_Pos (11U)
\r
5977 #define GPDMA0_MASKTFR_WE_CH3_Msk (0x00000001U << GPDMA0_MASKTFR_WE_CH3_Pos)
\r
5979 #define GPDMA0_MASKTFR_WE_CH4_Pos (12U)
\r
5980 #define GPDMA0_MASKTFR_WE_CH4_Msk (0x00000001U << GPDMA0_MASKTFR_WE_CH4_Pos)
\r
5982 #define GPDMA0_MASKTFR_WE_CH5_Pos (13U)
\r
5983 #define GPDMA0_MASKTFR_WE_CH5_Msk (0x00000001U << GPDMA0_MASKTFR_WE_CH5_Pos)
\r
5985 #define GPDMA0_MASKTFR_WE_CH6_Pos (14U)
\r
5986 #define GPDMA0_MASKTFR_WE_CH6_Msk (0x00000001U << GPDMA0_MASKTFR_WE_CH6_Pos)
\r
5988 #define GPDMA0_MASKTFR_WE_CH7_Pos (15U)
\r
5989 #define GPDMA0_MASKTFR_WE_CH7_Msk (0x00000001U << GPDMA0_MASKTFR_WE_CH7_Pos)
\r
5991 #define GPDMA0_MASKTFR_CH0_Pos (0U)
\r
5992 #define GPDMA0_MASKTFR_CH0_Msk (0x00000001U << GPDMA0_MASKTFR_CH0_Pos)
\r
5994 #define GPDMA0_MASKTFR_CH1_Pos (1U)
\r
5995 #define GPDMA0_MASKTFR_CH1_Msk (0x00000001U << GPDMA0_MASKTFR_CH1_Pos)
\r
5997 #define GPDMA0_MASKTFR_CH2_Pos (2U)
\r
5998 #define GPDMA0_MASKTFR_CH2_Msk (0x00000001U << GPDMA0_MASKTFR_CH2_Pos)
\r
6000 #define GPDMA0_MASKTFR_CH3_Pos (3U)
\r
6001 #define GPDMA0_MASKTFR_CH3_Msk (0x00000001U << GPDMA0_MASKTFR_CH3_Pos)
\r
6003 #define GPDMA0_MASKTFR_CH4_Pos (4U)
\r
6004 #define GPDMA0_MASKTFR_CH4_Msk (0x00000001U << GPDMA0_MASKTFR_CH4_Pos)
\r
6006 #define GPDMA0_MASKTFR_CH5_Pos (5U)
\r
6007 #define GPDMA0_MASKTFR_CH5_Msk (0x00000001U << GPDMA0_MASKTFR_CH5_Pos)
\r
6009 #define GPDMA0_MASKTFR_CH6_Pos (6U)
\r
6010 #define GPDMA0_MASKTFR_CH6_Msk (0x00000001U << GPDMA0_MASKTFR_CH6_Pos)
\r
6012 #define GPDMA0_MASKTFR_CH7_Pos (7U)
\r
6013 #define GPDMA0_MASKTFR_CH7_Msk (0x00000001U << GPDMA0_MASKTFR_CH7_Pos)
\r
6015 /* GPDMA0_MASKBLOCK = Mask for Raw IntBlock Status*/
\r
6016 #define GPDMA0_MASKBLOCK_WE_CH0_Pos (8U)
\r
6017 #define GPDMA0_MASKBLOCK_WE_CH0_Msk (0x00000001U << GPDMA0_MASKBLOCK_WE_CH0_Pos)
\r
6019 #define GPDMA0_MASKBLOCK_WE_CH1_Pos (9U)
\r
6020 #define GPDMA0_MASKBLOCK_WE_CH1_Msk (0x00000001U << GPDMA0_MASKBLOCK_WE_CH1_Pos)
\r
6022 #define GPDMA0_MASKBLOCK_WE_CH2_Pos (10U)
\r
6023 #define GPDMA0_MASKBLOCK_WE_CH2_Msk (0x00000001U << GPDMA0_MASKBLOCK_WE_CH2_Pos)
\r
6025 #define GPDMA0_MASKBLOCK_WE_CH3_Pos (11U)
\r
6026 #define GPDMA0_MASKBLOCK_WE_CH3_Msk (0x00000001U << GPDMA0_MASKBLOCK_WE_CH3_Pos)
\r
6028 #define GPDMA0_MASKBLOCK_WE_CH4_Pos (12U)
\r
6029 #define GPDMA0_MASKBLOCK_WE_CH4_Msk (0x00000001U << GPDMA0_MASKBLOCK_WE_CH4_Pos)
\r
6031 #define GPDMA0_MASKBLOCK_WE_CH5_Pos (13U)
\r
6032 #define GPDMA0_MASKBLOCK_WE_CH5_Msk (0x00000001U << GPDMA0_MASKBLOCK_WE_CH5_Pos)
\r
6034 #define GPDMA0_MASKBLOCK_WE_CH6_Pos (14U)
\r
6035 #define GPDMA0_MASKBLOCK_WE_CH6_Msk (0x00000001U << GPDMA0_MASKBLOCK_WE_CH6_Pos)
\r
6037 #define GPDMA0_MASKBLOCK_WE_CH7_Pos (15U)
\r
6038 #define GPDMA0_MASKBLOCK_WE_CH7_Msk (0x00000001U << GPDMA0_MASKBLOCK_WE_CH7_Pos)
\r
6040 #define GPDMA0_MASKBLOCK_CH0_Pos (0U)
\r
6041 #define GPDMA0_MASKBLOCK_CH0_Msk (0x00000001U << GPDMA0_MASKBLOCK_CH0_Pos)
\r
6043 #define GPDMA0_MASKBLOCK_CH1_Pos (1U)
\r
6044 #define GPDMA0_MASKBLOCK_CH1_Msk (0x00000001U << GPDMA0_MASKBLOCK_CH1_Pos)
\r
6046 #define GPDMA0_MASKBLOCK_CH2_Pos (2U)
\r
6047 #define GPDMA0_MASKBLOCK_CH2_Msk (0x00000001U << GPDMA0_MASKBLOCK_CH2_Pos)
\r
6049 #define GPDMA0_MASKBLOCK_CH3_Pos (3U)
\r
6050 #define GPDMA0_MASKBLOCK_CH3_Msk (0x00000001U << GPDMA0_MASKBLOCK_CH3_Pos)
\r
6052 #define GPDMA0_MASKBLOCK_CH4_Pos (4U)
\r
6053 #define GPDMA0_MASKBLOCK_CH4_Msk (0x00000001U << GPDMA0_MASKBLOCK_CH4_Pos)
\r
6055 #define GPDMA0_MASKBLOCK_CH5_Pos (5U)
\r
6056 #define GPDMA0_MASKBLOCK_CH5_Msk (0x00000001U << GPDMA0_MASKBLOCK_CH5_Pos)
\r
6058 #define GPDMA0_MASKBLOCK_CH6_Pos (6U)
\r
6059 #define GPDMA0_MASKBLOCK_CH6_Msk (0x00000001U << GPDMA0_MASKBLOCK_CH6_Pos)
\r
6061 #define GPDMA0_MASKBLOCK_CH7_Pos (7U)
\r
6062 #define GPDMA0_MASKBLOCK_CH7_Msk (0x00000001U << GPDMA0_MASKBLOCK_CH7_Pos)
\r
6064 /* GPDMA0_MASKSRCTRAN = Mask for Raw IntSrcTran Status*/
\r
6065 #define GPDMA0_MASKSRCTRAN_WE_CH0_Pos (8U)
\r
6066 #define GPDMA0_MASKSRCTRAN_WE_CH0_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_WE_CH0_Pos)
\r
6068 #define GPDMA0_MASKSRCTRAN_WE_CH1_Pos (9U)
\r
6069 #define GPDMA0_MASKSRCTRAN_WE_CH1_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_WE_CH1_Pos)
\r
6071 #define GPDMA0_MASKSRCTRAN_WE_CH2_Pos (10U)
\r
6072 #define GPDMA0_MASKSRCTRAN_WE_CH2_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_WE_CH2_Pos)
\r
6074 #define GPDMA0_MASKSRCTRAN_WE_CH3_Pos (11U)
\r
6075 #define GPDMA0_MASKSRCTRAN_WE_CH3_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_WE_CH3_Pos)
\r
6077 #define GPDMA0_MASKSRCTRAN_WE_CH4_Pos (12U)
\r
6078 #define GPDMA0_MASKSRCTRAN_WE_CH4_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_WE_CH4_Pos)
\r
6080 #define GPDMA0_MASKSRCTRAN_WE_CH5_Pos (13U)
\r
6081 #define GPDMA0_MASKSRCTRAN_WE_CH5_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_WE_CH5_Pos)
\r
6083 #define GPDMA0_MASKSRCTRAN_WE_CH6_Pos (14U)
\r
6084 #define GPDMA0_MASKSRCTRAN_WE_CH6_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_WE_CH6_Pos)
\r
6086 #define GPDMA0_MASKSRCTRAN_WE_CH7_Pos (15U)
\r
6087 #define GPDMA0_MASKSRCTRAN_WE_CH7_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_WE_CH7_Pos)
\r
6089 #define GPDMA0_MASKSRCTRAN_CH0_Pos (0U)
\r
6090 #define GPDMA0_MASKSRCTRAN_CH0_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_CH0_Pos)
\r
6092 #define GPDMA0_MASKSRCTRAN_CH1_Pos (1U)
\r
6093 #define GPDMA0_MASKSRCTRAN_CH1_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_CH1_Pos)
\r
6095 #define GPDMA0_MASKSRCTRAN_CH2_Pos (2U)
\r
6096 #define GPDMA0_MASKSRCTRAN_CH2_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_CH2_Pos)
\r
6098 #define GPDMA0_MASKSRCTRAN_CH3_Pos (3U)
\r
6099 #define GPDMA0_MASKSRCTRAN_CH3_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_CH3_Pos)
\r
6101 #define GPDMA0_MASKSRCTRAN_CH4_Pos (4U)
\r
6102 #define GPDMA0_MASKSRCTRAN_CH4_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_CH4_Pos)
\r
6104 #define GPDMA0_MASKSRCTRAN_CH5_Pos (5U)
\r
6105 #define GPDMA0_MASKSRCTRAN_CH5_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_CH5_Pos)
\r
6107 #define GPDMA0_MASKSRCTRAN_CH6_Pos (6U)
\r
6108 #define GPDMA0_MASKSRCTRAN_CH6_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_CH6_Pos)
\r
6110 #define GPDMA0_MASKSRCTRAN_CH7_Pos (7U)
\r
6111 #define GPDMA0_MASKSRCTRAN_CH7_Msk (0x00000001U << GPDMA0_MASKSRCTRAN_CH7_Pos)
\r
6113 /* GPDMA0_MASKDSTTRAN = Mask for Raw IntBlock Status*/
\r
6114 #define GPDMA0_MASKDSTTRAN_WE_CH0_Pos (8U)
\r
6115 #define GPDMA0_MASKDSTTRAN_WE_CH0_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_WE_CH0_Pos)
\r
6117 #define GPDMA0_MASKDSTTRAN_WE_CH1_Pos (9U)
\r
6118 #define GPDMA0_MASKDSTTRAN_WE_CH1_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_WE_CH1_Pos)
\r
6120 #define GPDMA0_MASKDSTTRAN_WE_CH2_Pos (10U)
\r
6121 #define GPDMA0_MASKDSTTRAN_WE_CH2_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_WE_CH2_Pos)
\r
6123 #define GPDMA0_MASKDSTTRAN_WE_CH3_Pos (11U)
\r
6124 #define GPDMA0_MASKDSTTRAN_WE_CH3_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_WE_CH3_Pos)
\r
6126 #define GPDMA0_MASKDSTTRAN_WE_CH4_Pos (12U)
\r
6127 #define GPDMA0_MASKDSTTRAN_WE_CH4_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_WE_CH4_Pos)
\r
6129 #define GPDMA0_MASKDSTTRAN_WE_CH5_Pos (13U)
\r
6130 #define GPDMA0_MASKDSTTRAN_WE_CH5_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_WE_CH5_Pos)
\r
6132 #define GPDMA0_MASKDSTTRAN_WE_CH6_Pos (14U)
\r
6133 #define GPDMA0_MASKDSTTRAN_WE_CH6_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_WE_CH6_Pos)
\r
6135 #define GPDMA0_MASKDSTTRAN_WE_CH7_Pos (15U)
\r
6136 #define GPDMA0_MASKDSTTRAN_WE_CH7_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_WE_CH7_Pos)
\r
6138 #define GPDMA0_MASKDSTTRAN_CH0_Pos (0U)
\r
6139 #define GPDMA0_MASKDSTTRAN_CH0_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_CH0_Pos)
\r
6141 #define GPDMA0_MASKDSTTRAN_CH1_Pos (1U)
\r
6142 #define GPDMA0_MASKDSTTRAN_CH1_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_CH1_Pos)
\r
6144 #define GPDMA0_MASKDSTTRAN_CH2_Pos (2U)
\r
6145 #define GPDMA0_MASKDSTTRAN_CH2_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_CH2_Pos)
\r
6147 #define GPDMA0_MASKDSTTRAN_CH3_Pos (3U)
\r
6148 #define GPDMA0_MASKDSTTRAN_CH3_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_CH3_Pos)
\r
6150 #define GPDMA0_MASKDSTTRAN_CH4_Pos (4U)
\r
6151 #define GPDMA0_MASKDSTTRAN_CH4_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_CH4_Pos)
\r
6153 #define GPDMA0_MASKDSTTRAN_CH5_Pos (5U)
\r
6154 #define GPDMA0_MASKDSTTRAN_CH5_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_CH5_Pos)
\r
6156 #define GPDMA0_MASKDSTTRAN_CH6_Pos (6U)
\r
6157 #define GPDMA0_MASKDSTTRAN_CH6_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_CH6_Pos)
\r
6159 #define GPDMA0_MASKDSTTRAN_CH7_Pos (7U)
\r
6160 #define GPDMA0_MASKDSTTRAN_CH7_Msk (0x00000001U << GPDMA0_MASKDSTTRAN_CH7_Pos)
\r
6162 /* GPDMA0_MASKERR = Mask for Raw IntErr Status*/
\r
6163 #define GPDMA0_MASKERR_WE_CH0_Pos (8U)
\r
6164 #define GPDMA0_MASKERR_WE_CH0_Msk (0x00000001U << GPDMA0_MASKERR_WE_CH0_Pos)
\r
6166 #define GPDMA0_MASKERR_WE_CH1_Pos (9U)
\r
6167 #define GPDMA0_MASKERR_WE_CH1_Msk (0x00000001U << GPDMA0_MASKERR_WE_CH1_Pos)
\r
6169 #define GPDMA0_MASKERR_WE_CH2_Pos (10U)
\r
6170 #define GPDMA0_MASKERR_WE_CH2_Msk (0x00000001U << GPDMA0_MASKERR_WE_CH2_Pos)
\r
6172 #define GPDMA0_MASKERR_WE_CH3_Pos (11U)
\r
6173 #define GPDMA0_MASKERR_WE_CH3_Msk (0x00000001U << GPDMA0_MASKERR_WE_CH3_Pos)
\r
6175 #define GPDMA0_MASKERR_WE_CH4_Pos (12U)
\r
6176 #define GPDMA0_MASKERR_WE_CH4_Msk (0x00000001U << GPDMA0_MASKERR_WE_CH4_Pos)
\r
6178 #define GPDMA0_MASKERR_WE_CH5_Pos (13U)
\r
6179 #define GPDMA0_MASKERR_WE_CH5_Msk (0x00000001U << GPDMA0_MASKERR_WE_CH5_Pos)
\r
6181 #define GPDMA0_MASKERR_WE_CH6_Pos (14U)
\r
6182 #define GPDMA0_MASKERR_WE_CH6_Msk (0x00000001U << GPDMA0_MASKERR_WE_CH6_Pos)
\r
6184 #define GPDMA0_MASKERR_WE_CH7_Pos (15U)
\r
6185 #define GPDMA0_MASKERR_WE_CH7_Msk (0x00000001U << GPDMA0_MASKERR_WE_CH7_Pos)
\r
6187 #define GPDMA0_MASKERR_CH0_Pos (0U)
\r
6188 #define GPDMA0_MASKERR_CH0_Msk (0x00000001U << GPDMA0_MASKERR_CH0_Pos)
\r
6190 #define GPDMA0_MASKERR_CH1_Pos (1U)
\r
6191 #define GPDMA0_MASKERR_CH1_Msk (0x00000001U << GPDMA0_MASKERR_CH1_Pos)
\r
6193 #define GPDMA0_MASKERR_CH2_Pos (2U)
\r
6194 #define GPDMA0_MASKERR_CH2_Msk (0x00000001U << GPDMA0_MASKERR_CH2_Pos)
\r
6196 #define GPDMA0_MASKERR_CH3_Pos (3U)
\r
6197 #define GPDMA0_MASKERR_CH3_Msk (0x00000001U << GPDMA0_MASKERR_CH3_Pos)
\r
6199 #define GPDMA0_MASKERR_CH4_Pos (4U)
\r
6200 #define GPDMA0_MASKERR_CH4_Msk (0x00000001U << GPDMA0_MASKERR_CH4_Pos)
\r
6202 #define GPDMA0_MASKERR_CH5_Pos (5U)
\r
6203 #define GPDMA0_MASKERR_CH5_Msk (0x00000001U << GPDMA0_MASKERR_CH5_Pos)
\r
6205 #define GPDMA0_MASKERR_CH6_Pos (6U)
\r
6206 #define GPDMA0_MASKERR_CH6_Msk (0x00000001U << GPDMA0_MASKERR_CH6_Pos)
\r
6208 #define GPDMA0_MASKERR_CH7_Pos (7U)
\r
6209 #define GPDMA0_MASKERR_CH7_Msk (0x00000001U << GPDMA0_MASKERR_CH7_Pos)
\r
6211 /* GPDMA0_CLEARTFR = IntTfr Status*/
\r
6212 #define GPDMA0_CLEARTFR_CH0_Pos (0U)
\r
6213 #define GPDMA0_CLEARTFR_CH0_Msk (0x00000001U << GPDMA0_CLEARTFR_CH0_Pos)
\r
6215 #define GPDMA0_CLEARTFR_CH1_Pos (1U)
\r
6216 #define GPDMA0_CLEARTFR_CH1_Msk (0x00000001U << GPDMA0_CLEARTFR_CH1_Pos)
\r
6218 #define GPDMA0_CLEARTFR_CH2_Pos (2U)
\r
6219 #define GPDMA0_CLEARTFR_CH2_Msk (0x00000001U << GPDMA0_CLEARTFR_CH2_Pos)
\r
6221 #define GPDMA0_CLEARTFR_CH3_Pos (3U)
\r
6222 #define GPDMA0_CLEARTFR_CH3_Msk (0x00000001U << GPDMA0_CLEARTFR_CH3_Pos)
\r
6224 #define GPDMA0_CLEARTFR_CH4_Pos (4U)
\r
6225 #define GPDMA0_CLEARTFR_CH4_Msk (0x00000001U << GPDMA0_CLEARTFR_CH4_Pos)
\r
6227 #define GPDMA0_CLEARTFR_CH5_Pos (5U)
\r
6228 #define GPDMA0_CLEARTFR_CH5_Msk (0x00000001U << GPDMA0_CLEARTFR_CH5_Pos)
\r
6230 #define GPDMA0_CLEARTFR_CH6_Pos (6U)
\r
6231 #define GPDMA0_CLEARTFR_CH6_Msk (0x00000001U << GPDMA0_CLEARTFR_CH6_Pos)
\r
6233 #define GPDMA0_CLEARTFR_CH7_Pos (7U)
\r
6234 #define GPDMA0_CLEARTFR_CH7_Msk (0x00000001U << GPDMA0_CLEARTFR_CH7_Pos)
\r
6236 /* GPDMA0_CLEARBLOCK = IntBlock Status*/
\r
6237 #define GPDMA0_CLEARBLOCK_CH0_Pos (0U)
\r
6238 #define GPDMA0_CLEARBLOCK_CH0_Msk (0x00000001U << GPDMA0_CLEARBLOCK_CH0_Pos)
\r
6240 #define GPDMA0_CLEARBLOCK_CH1_Pos (1U)
\r
6241 #define GPDMA0_CLEARBLOCK_CH1_Msk (0x00000001U << GPDMA0_CLEARBLOCK_CH1_Pos)
\r
6243 #define GPDMA0_CLEARBLOCK_CH2_Pos (2U)
\r
6244 #define GPDMA0_CLEARBLOCK_CH2_Msk (0x00000001U << GPDMA0_CLEARBLOCK_CH2_Pos)
\r
6246 #define GPDMA0_CLEARBLOCK_CH3_Pos (3U)
\r
6247 #define GPDMA0_CLEARBLOCK_CH3_Msk (0x00000001U << GPDMA0_CLEARBLOCK_CH3_Pos)
\r
6249 #define GPDMA0_CLEARBLOCK_CH4_Pos (4U)
\r
6250 #define GPDMA0_CLEARBLOCK_CH4_Msk (0x00000001U << GPDMA0_CLEARBLOCK_CH4_Pos)
\r
6252 #define GPDMA0_CLEARBLOCK_CH5_Pos (5U)
\r
6253 #define GPDMA0_CLEARBLOCK_CH5_Msk (0x00000001U << GPDMA0_CLEARBLOCK_CH5_Pos)
\r
6255 #define GPDMA0_CLEARBLOCK_CH6_Pos (6U)
\r
6256 #define GPDMA0_CLEARBLOCK_CH6_Msk (0x00000001U << GPDMA0_CLEARBLOCK_CH6_Pos)
\r
6258 #define GPDMA0_CLEARBLOCK_CH7_Pos (7U)
\r
6259 #define GPDMA0_CLEARBLOCK_CH7_Msk (0x00000001U << GPDMA0_CLEARBLOCK_CH7_Pos)
\r
6261 /* GPDMA0_CLEARSRCTRAN = IntSrcTran Status*/
\r
6262 #define GPDMA0_CLEARSRCTRAN_CH0_Pos (0U)
\r
6263 #define GPDMA0_CLEARSRCTRAN_CH0_Msk (0x00000001U << GPDMA0_CLEARSRCTRAN_CH0_Pos)
\r
6265 #define GPDMA0_CLEARSRCTRAN_CH1_Pos (1U)
\r
6266 #define GPDMA0_CLEARSRCTRAN_CH1_Msk (0x00000001U << GPDMA0_CLEARSRCTRAN_CH1_Pos)
\r
6268 #define GPDMA0_CLEARSRCTRAN_CH2_Pos (2U)
\r
6269 #define GPDMA0_CLEARSRCTRAN_CH2_Msk (0x00000001U << GPDMA0_CLEARSRCTRAN_CH2_Pos)
\r
6271 #define GPDMA0_CLEARSRCTRAN_CH3_Pos (3U)
\r
6272 #define GPDMA0_CLEARSRCTRAN_CH3_Msk (0x00000001U << GPDMA0_CLEARSRCTRAN_CH3_Pos)
\r
6274 #define GPDMA0_CLEARSRCTRAN_CH4_Pos (4U)
\r
6275 #define GPDMA0_CLEARSRCTRAN_CH4_Msk (0x00000001U << GPDMA0_CLEARSRCTRAN_CH4_Pos)
\r
6277 #define GPDMA0_CLEARSRCTRAN_CH5_Pos (5U)
\r
6278 #define GPDMA0_CLEARSRCTRAN_CH5_Msk (0x00000001U << GPDMA0_CLEARSRCTRAN_CH5_Pos)
\r
6280 #define GPDMA0_CLEARSRCTRAN_CH6_Pos (6U)
\r
6281 #define GPDMA0_CLEARSRCTRAN_CH6_Msk (0x00000001U << GPDMA0_CLEARSRCTRAN_CH6_Pos)
\r
6283 #define GPDMA0_CLEARSRCTRAN_CH7_Pos (7U)
\r
6284 #define GPDMA0_CLEARSRCTRAN_CH7_Msk (0x00000001U << GPDMA0_CLEARSRCTRAN_CH7_Pos)
\r
6286 /* GPDMA0_CLEARDSTTRAN = IntBlock Status*/
\r
6287 #define GPDMA0_CLEARDSTTRAN_CH0_Pos (0U)
\r
6288 #define GPDMA0_CLEARDSTTRAN_CH0_Msk (0x00000001U << GPDMA0_CLEARDSTTRAN_CH0_Pos)
\r
6290 #define GPDMA0_CLEARDSTTRAN_CH1_Pos (1U)
\r
6291 #define GPDMA0_CLEARDSTTRAN_CH1_Msk (0x00000001U << GPDMA0_CLEARDSTTRAN_CH1_Pos)
\r
6293 #define GPDMA0_CLEARDSTTRAN_CH2_Pos (2U)
\r
6294 #define GPDMA0_CLEARDSTTRAN_CH2_Msk (0x00000001U << GPDMA0_CLEARDSTTRAN_CH2_Pos)
\r
6296 #define GPDMA0_CLEARDSTTRAN_CH3_Pos (3U)
\r
6297 #define GPDMA0_CLEARDSTTRAN_CH3_Msk (0x00000001U << GPDMA0_CLEARDSTTRAN_CH3_Pos)
\r
6299 #define GPDMA0_CLEARDSTTRAN_CH4_Pos (4U)
\r
6300 #define GPDMA0_CLEARDSTTRAN_CH4_Msk (0x00000001U << GPDMA0_CLEARDSTTRAN_CH4_Pos)
\r
6302 #define GPDMA0_CLEARDSTTRAN_CH5_Pos (5U)
\r
6303 #define GPDMA0_CLEARDSTTRAN_CH5_Msk (0x00000001U << GPDMA0_CLEARDSTTRAN_CH5_Pos)
\r
6305 #define GPDMA0_CLEARDSTTRAN_CH6_Pos (6U)
\r
6306 #define GPDMA0_CLEARDSTTRAN_CH6_Msk (0x00000001U << GPDMA0_CLEARDSTTRAN_CH6_Pos)
\r
6308 #define GPDMA0_CLEARDSTTRAN_CH7_Pos (7U)
\r
6309 #define GPDMA0_CLEARDSTTRAN_CH7_Msk (0x00000001U << GPDMA0_CLEARDSTTRAN_CH7_Pos)
\r
6311 /* GPDMA0_CLEARERR = IntErr Status*/
\r
6312 #define GPDMA0_CLEARERR_CH0_Pos (0U)
\r
6313 #define GPDMA0_CLEARERR_CH0_Msk (0x00000001U << GPDMA0_CLEARERR_CH0_Pos)
\r
6315 #define GPDMA0_CLEARERR_CH1_Pos (1U)
\r
6316 #define GPDMA0_CLEARERR_CH1_Msk (0x00000001U << GPDMA0_CLEARERR_CH1_Pos)
\r
6318 #define GPDMA0_CLEARERR_CH2_Pos (2U)
\r
6319 #define GPDMA0_CLEARERR_CH2_Msk (0x00000001U << GPDMA0_CLEARERR_CH2_Pos)
\r
6321 #define GPDMA0_CLEARERR_CH3_Pos (3U)
\r
6322 #define GPDMA0_CLEARERR_CH3_Msk (0x00000001U << GPDMA0_CLEARERR_CH3_Pos)
\r
6324 #define GPDMA0_CLEARERR_CH4_Pos (4U)
\r
6325 #define GPDMA0_CLEARERR_CH4_Msk (0x00000001U << GPDMA0_CLEARERR_CH4_Pos)
\r
6327 #define GPDMA0_CLEARERR_CH5_Pos (5U)
\r
6328 #define GPDMA0_CLEARERR_CH5_Msk (0x00000001U << GPDMA0_CLEARERR_CH5_Pos)
\r
6330 #define GPDMA0_CLEARERR_CH6_Pos (6U)
\r
6331 #define GPDMA0_CLEARERR_CH6_Msk (0x00000001U << GPDMA0_CLEARERR_CH6_Pos)
\r
6333 #define GPDMA0_CLEARERR_CH7_Pos (7U)
\r
6334 #define GPDMA0_CLEARERR_CH7_Msk (0x00000001U << GPDMA0_CLEARERR_CH7_Pos)
\r
6336 /* GPDMA0_STATUSINT = Combined Interrupt Status Register*/
\r
6337 #define GPDMA0_STATUSINT_ERR_Pos (4U)
\r
6338 #define GPDMA0_STATUSINT_ERR_Msk (0x00000001U << GPDMA0_STATUSINT_ERR_Pos)
\r
6340 #define GPDMA0_STATUSINT_DSTT_Pos (3U)
\r
6341 #define GPDMA0_STATUSINT_DSTT_Msk (0x00000001U << GPDMA0_STATUSINT_DSTT_Pos)
\r
6343 #define GPDMA0_STATUSINT_SRCT_Pos (2U)
\r
6344 #define GPDMA0_STATUSINT_SRCT_Msk (0x00000001U << GPDMA0_STATUSINT_SRCT_Pos)
\r
6346 #define GPDMA0_STATUSINT_BLOCK_Pos (1U)
\r
6347 #define GPDMA0_STATUSINT_BLOCK_Msk (0x00000001U << GPDMA0_STATUSINT_BLOCK_Pos)
\r
6349 #define GPDMA0_STATUSINT_TFR_Pos (0U)
\r
6350 #define GPDMA0_STATUSINT_TFR_Msk (0x00000001U << GPDMA0_STATUSINT_TFR_Pos)
\r
6352 /* GPDMA0_REQSRCREG = Source Software Transaction Request Register*/
\r
6353 #define GPDMA0_REQSRCREG_WE_CH0_Pos (8U)
\r
6354 #define GPDMA0_REQSRCREG_WE_CH0_Msk (0x00000001U << GPDMA0_REQSRCREG_WE_CH0_Pos)
\r
6356 #define GPDMA0_REQSRCREG_WE_CH1_Pos (9U)
\r
6357 #define GPDMA0_REQSRCREG_WE_CH1_Msk (0x00000001U << GPDMA0_REQSRCREG_WE_CH1_Pos)
\r
6359 #define GPDMA0_REQSRCREG_WE_CH2_Pos (10U)
\r
6360 #define GPDMA0_REQSRCREG_WE_CH2_Msk (0x00000001U << GPDMA0_REQSRCREG_WE_CH2_Pos)
\r
6362 #define GPDMA0_REQSRCREG_WE_CH3_Pos (11U)
\r
6363 #define GPDMA0_REQSRCREG_WE_CH3_Msk (0x00000001U << GPDMA0_REQSRCREG_WE_CH3_Pos)
\r
6365 #define GPDMA0_REQSRCREG_WE_CH4_Pos (12U)
\r
6366 #define GPDMA0_REQSRCREG_WE_CH4_Msk (0x00000001U << GPDMA0_REQSRCREG_WE_CH4_Pos)
\r
6368 #define GPDMA0_REQSRCREG_WE_CH5_Pos (13U)
\r
6369 #define GPDMA0_REQSRCREG_WE_CH5_Msk (0x00000001U << GPDMA0_REQSRCREG_WE_CH5_Pos)
\r
6371 #define GPDMA0_REQSRCREG_WE_CH6_Pos (14U)
\r
6372 #define GPDMA0_REQSRCREG_WE_CH6_Msk (0x00000001U << GPDMA0_REQSRCREG_WE_CH6_Pos)
\r
6374 #define GPDMA0_REQSRCREG_WE_CH7_Pos (15U)
\r
6375 #define GPDMA0_REQSRCREG_WE_CH7_Msk (0x00000001U << GPDMA0_REQSRCREG_WE_CH7_Pos)
\r
6377 #define GPDMA0_REQSRCREG_CH0_Pos (0U)
\r
6378 #define GPDMA0_REQSRCREG_CH0_Msk (0x00000001U << GPDMA0_REQSRCREG_CH0_Pos)
\r
6380 #define GPDMA0_REQSRCREG_CH1_Pos (1U)
\r
6381 #define GPDMA0_REQSRCREG_CH1_Msk (0x00000001U << GPDMA0_REQSRCREG_CH1_Pos)
\r
6383 #define GPDMA0_REQSRCREG_CH2_Pos (2U)
\r
6384 #define GPDMA0_REQSRCREG_CH2_Msk (0x00000001U << GPDMA0_REQSRCREG_CH2_Pos)
\r
6386 #define GPDMA0_REQSRCREG_CH3_Pos (3U)
\r
6387 #define GPDMA0_REQSRCREG_CH3_Msk (0x00000001U << GPDMA0_REQSRCREG_CH3_Pos)
\r
6389 #define GPDMA0_REQSRCREG_CH4_Pos (4U)
\r
6390 #define GPDMA0_REQSRCREG_CH4_Msk (0x00000001U << GPDMA0_REQSRCREG_CH4_Pos)
\r
6392 #define GPDMA0_REQSRCREG_CH5_Pos (5U)
\r
6393 #define GPDMA0_REQSRCREG_CH5_Msk (0x00000001U << GPDMA0_REQSRCREG_CH5_Pos)
\r
6395 #define GPDMA0_REQSRCREG_CH6_Pos (6U)
\r
6396 #define GPDMA0_REQSRCREG_CH6_Msk (0x00000001U << GPDMA0_REQSRCREG_CH6_Pos)
\r
6398 #define GPDMA0_REQSRCREG_CH7_Pos (7U)
\r
6399 #define GPDMA0_REQSRCREG_CH7_Msk (0x00000001U << GPDMA0_REQSRCREG_CH7_Pos)
\r
6401 /* GPDMA0_REQDSTREG = Destination Software Transaction Request Register*/
\r
6402 #define GPDMA0_REQDSTREG_WE_CH0_Pos (8U)
\r
6403 #define GPDMA0_REQDSTREG_WE_CH0_Msk (0x00000001U << GPDMA0_REQDSTREG_WE_CH0_Pos)
\r
6405 #define GPDMA0_REQDSTREG_WE_CH1_Pos (9U)
\r
6406 #define GPDMA0_REQDSTREG_WE_CH1_Msk (0x00000001U << GPDMA0_REQDSTREG_WE_CH1_Pos)
\r
6408 #define GPDMA0_REQDSTREG_WE_CH2_Pos (10U)
\r
6409 #define GPDMA0_REQDSTREG_WE_CH2_Msk (0x00000001U << GPDMA0_REQDSTREG_WE_CH2_Pos)
\r
6411 #define GPDMA0_REQDSTREG_WE_CH3_Pos (11U)
\r
6412 #define GPDMA0_REQDSTREG_WE_CH3_Msk (0x00000001U << GPDMA0_REQDSTREG_WE_CH3_Pos)
\r
6414 #define GPDMA0_REQDSTREG_WE_CH4_Pos (12U)
\r
6415 #define GPDMA0_REQDSTREG_WE_CH4_Msk (0x00000001U << GPDMA0_REQDSTREG_WE_CH4_Pos)
\r
6417 #define GPDMA0_REQDSTREG_WE_CH5_Pos (13U)
\r
6418 #define GPDMA0_REQDSTREG_WE_CH5_Msk (0x00000001U << GPDMA0_REQDSTREG_WE_CH5_Pos)
\r
6420 #define GPDMA0_REQDSTREG_WE_CH6_Pos (14U)
\r
6421 #define GPDMA0_REQDSTREG_WE_CH6_Msk (0x00000001U << GPDMA0_REQDSTREG_WE_CH6_Pos)
\r
6423 #define GPDMA0_REQDSTREG_WE_CH7_Pos (15U)
\r
6424 #define GPDMA0_REQDSTREG_WE_CH7_Msk (0x00000001U << GPDMA0_REQDSTREG_WE_CH7_Pos)
\r
6426 #define GPDMA0_REQDSTREG_CH0_Pos (0U)
\r
6427 #define GPDMA0_REQDSTREG_CH0_Msk (0x00000001U << GPDMA0_REQDSTREG_CH0_Pos)
\r
6429 #define GPDMA0_REQDSTREG_CH1_Pos (1U)
\r
6430 #define GPDMA0_REQDSTREG_CH1_Msk (0x00000001U << GPDMA0_REQDSTREG_CH1_Pos)
\r
6432 #define GPDMA0_REQDSTREG_CH2_Pos (2U)
\r
6433 #define GPDMA0_REQDSTREG_CH2_Msk (0x00000001U << GPDMA0_REQDSTREG_CH2_Pos)
\r
6435 #define GPDMA0_REQDSTREG_CH3_Pos (3U)
\r
6436 #define GPDMA0_REQDSTREG_CH3_Msk (0x00000001U << GPDMA0_REQDSTREG_CH3_Pos)
\r
6438 #define GPDMA0_REQDSTREG_CH4_Pos (4U)
\r
6439 #define GPDMA0_REQDSTREG_CH4_Msk (0x00000001U << GPDMA0_REQDSTREG_CH4_Pos)
\r
6441 #define GPDMA0_REQDSTREG_CH5_Pos (5U)
\r
6442 #define GPDMA0_REQDSTREG_CH5_Msk (0x00000001U << GPDMA0_REQDSTREG_CH5_Pos)
\r
6444 #define GPDMA0_REQDSTREG_CH6_Pos (6U)
\r
6445 #define GPDMA0_REQDSTREG_CH6_Msk (0x00000001U << GPDMA0_REQDSTREG_CH6_Pos)
\r
6447 #define GPDMA0_REQDSTREG_CH7_Pos (7U)
\r
6448 #define GPDMA0_REQDSTREG_CH7_Msk (0x00000001U << GPDMA0_REQDSTREG_CH7_Pos)
\r
6450 /* GPDMA0_SGLREQSRCREG = Single Source Transaction Request Register*/
\r
6451 #define GPDMA0_SGLREQSRCREG_WE_CH0_Pos (8U)
\r
6452 #define GPDMA0_SGLREQSRCREG_WE_CH0_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_WE_CH0_Pos)
\r
6454 #define GPDMA0_SGLREQSRCREG_WE_CH1_Pos (9U)
\r
6455 #define GPDMA0_SGLREQSRCREG_WE_CH1_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_WE_CH1_Pos)
\r
6457 #define GPDMA0_SGLREQSRCREG_WE_CH2_Pos (10U)
\r
6458 #define GPDMA0_SGLREQSRCREG_WE_CH2_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_WE_CH2_Pos)
\r
6460 #define GPDMA0_SGLREQSRCREG_WE_CH3_Pos (11U)
\r
6461 #define GPDMA0_SGLREQSRCREG_WE_CH3_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_WE_CH3_Pos)
\r
6463 #define GPDMA0_SGLREQSRCREG_WE_CH4_Pos (12U)
\r
6464 #define GPDMA0_SGLREQSRCREG_WE_CH4_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_WE_CH4_Pos)
\r
6466 #define GPDMA0_SGLREQSRCREG_WE_CH5_Pos (13U)
\r
6467 #define GPDMA0_SGLREQSRCREG_WE_CH5_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_WE_CH5_Pos)
\r
6469 #define GPDMA0_SGLREQSRCREG_WE_CH6_Pos (14U)
\r
6470 #define GPDMA0_SGLREQSRCREG_WE_CH6_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_WE_CH6_Pos)
\r
6472 #define GPDMA0_SGLREQSRCREG_WE_CH7_Pos (15U)
\r
6473 #define GPDMA0_SGLREQSRCREG_WE_CH7_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_WE_CH7_Pos)
\r
6475 #define GPDMA0_SGLREQSRCREG_CH0_Pos (0U)
\r
6476 #define GPDMA0_SGLREQSRCREG_CH0_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_CH0_Pos)
\r
6478 #define GPDMA0_SGLREQSRCREG_CH1_Pos (1U)
\r
6479 #define GPDMA0_SGLREQSRCREG_CH1_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_CH1_Pos)
\r
6481 #define GPDMA0_SGLREQSRCREG_CH2_Pos (2U)
\r
6482 #define GPDMA0_SGLREQSRCREG_CH2_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_CH2_Pos)
\r
6484 #define GPDMA0_SGLREQSRCREG_CH3_Pos (3U)
\r
6485 #define GPDMA0_SGLREQSRCREG_CH3_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_CH3_Pos)
\r
6487 #define GPDMA0_SGLREQSRCREG_CH4_Pos (4U)
\r
6488 #define GPDMA0_SGLREQSRCREG_CH4_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_CH4_Pos)
\r
6490 #define GPDMA0_SGLREQSRCREG_CH5_Pos (5U)
\r
6491 #define GPDMA0_SGLREQSRCREG_CH5_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_CH5_Pos)
\r
6493 #define GPDMA0_SGLREQSRCREG_CH6_Pos (6U)
\r
6494 #define GPDMA0_SGLREQSRCREG_CH6_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_CH6_Pos)
\r
6496 #define GPDMA0_SGLREQSRCREG_CH7_Pos (7U)
\r
6497 #define GPDMA0_SGLREQSRCREG_CH7_Msk (0x00000001U << GPDMA0_SGLREQSRCREG_CH7_Pos)
\r
6499 /* GPDMA0_SGLREQDSTREG = Single Destination Transaction Request Register*/
\r
6500 #define GPDMA0_SGLREQDSTREG_WE_CH0_Pos (8U)
\r
6501 #define GPDMA0_SGLREQDSTREG_WE_CH0_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_WE_CH0_Pos)
\r
6503 #define GPDMA0_SGLREQDSTREG_WE_CH1_Pos (9U)
\r
6504 #define GPDMA0_SGLREQDSTREG_WE_CH1_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_WE_CH1_Pos)
\r
6506 #define GPDMA0_SGLREQDSTREG_WE_CH2_Pos (10U)
\r
6507 #define GPDMA0_SGLREQDSTREG_WE_CH2_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_WE_CH2_Pos)
\r
6509 #define GPDMA0_SGLREQDSTREG_WE_CH3_Pos (11U)
\r
6510 #define GPDMA0_SGLREQDSTREG_WE_CH3_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_WE_CH3_Pos)
\r
6512 #define GPDMA0_SGLREQDSTREG_WE_CH4_Pos (12U)
\r
6513 #define GPDMA0_SGLREQDSTREG_WE_CH4_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_WE_CH4_Pos)
\r
6515 #define GPDMA0_SGLREQDSTREG_WE_CH5_Pos (13U)
\r
6516 #define GPDMA0_SGLREQDSTREG_WE_CH5_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_WE_CH5_Pos)
\r
6518 #define GPDMA0_SGLREQDSTREG_WE_CH6_Pos (14U)
\r
6519 #define GPDMA0_SGLREQDSTREG_WE_CH6_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_WE_CH6_Pos)
\r
6521 #define GPDMA0_SGLREQDSTREG_WE_CH7_Pos (15U)
\r
6522 #define GPDMA0_SGLREQDSTREG_WE_CH7_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_WE_CH7_Pos)
\r
6524 #define GPDMA0_SGLREQDSTREG_CH0_Pos (0U)
\r
6525 #define GPDMA0_SGLREQDSTREG_CH0_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_CH0_Pos)
\r
6527 #define GPDMA0_SGLREQDSTREG_CH1_Pos (1U)
\r
6528 #define GPDMA0_SGLREQDSTREG_CH1_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_CH1_Pos)
\r
6530 #define GPDMA0_SGLREQDSTREG_CH2_Pos (2U)
\r
6531 #define GPDMA0_SGLREQDSTREG_CH2_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_CH2_Pos)
\r
6533 #define GPDMA0_SGLREQDSTREG_CH3_Pos (3U)
\r
6534 #define GPDMA0_SGLREQDSTREG_CH3_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_CH3_Pos)
\r
6536 #define GPDMA0_SGLREQDSTREG_CH4_Pos (4U)
\r
6537 #define GPDMA0_SGLREQDSTREG_CH4_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_CH4_Pos)
\r
6539 #define GPDMA0_SGLREQDSTREG_CH5_Pos (5U)
\r
6540 #define GPDMA0_SGLREQDSTREG_CH5_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_CH5_Pos)
\r
6542 #define GPDMA0_SGLREQDSTREG_CH6_Pos (6U)
\r
6543 #define GPDMA0_SGLREQDSTREG_CH6_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_CH6_Pos)
\r
6545 #define GPDMA0_SGLREQDSTREG_CH7_Pos (7U)
\r
6546 #define GPDMA0_SGLREQDSTREG_CH7_Msk (0x00000001U << GPDMA0_SGLREQDSTREG_CH7_Pos)
\r
6548 /* GPDMA0_LSTSRCREG = Last Source Transaction Request Register*/
\r
6549 #define GPDMA0_LSTSRCREG_WE_CH0_Pos (8U)
\r
6550 #define GPDMA0_LSTSRCREG_WE_CH0_Msk (0x00000001U << GPDMA0_LSTSRCREG_WE_CH0_Pos)
\r
6552 #define GPDMA0_LSTSRCREG_WE_CH1_Pos (9U)
\r
6553 #define GPDMA0_LSTSRCREG_WE_CH1_Msk (0x00000001U << GPDMA0_LSTSRCREG_WE_CH1_Pos)
\r
6555 #define GPDMA0_LSTSRCREG_WE_CH2_Pos (10U)
\r
6556 #define GPDMA0_LSTSRCREG_WE_CH2_Msk (0x00000001U << GPDMA0_LSTSRCREG_WE_CH2_Pos)
\r
6558 #define GPDMA0_LSTSRCREG_WE_CH3_Pos (11U)
\r
6559 #define GPDMA0_LSTSRCREG_WE_CH3_Msk (0x00000001U << GPDMA0_LSTSRCREG_WE_CH3_Pos)
\r
6561 #define GPDMA0_LSTSRCREG_WE_CH4_Pos (12U)
\r
6562 #define GPDMA0_LSTSRCREG_WE_CH4_Msk (0x00000001U << GPDMA0_LSTSRCREG_WE_CH4_Pos)
\r
6564 #define GPDMA0_LSTSRCREG_WE_CH5_Pos (13U)
\r
6565 #define GPDMA0_LSTSRCREG_WE_CH5_Msk (0x00000001U << GPDMA0_LSTSRCREG_WE_CH5_Pos)
\r
6567 #define GPDMA0_LSTSRCREG_WE_CH6_Pos (14U)
\r
6568 #define GPDMA0_LSTSRCREG_WE_CH6_Msk (0x00000001U << GPDMA0_LSTSRCREG_WE_CH6_Pos)
\r
6570 #define GPDMA0_LSTSRCREG_WE_CH7_Pos (15U)
\r
6571 #define GPDMA0_LSTSRCREG_WE_CH7_Msk (0x00000001U << GPDMA0_LSTSRCREG_WE_CH7_Pos)
\r
6573 #define GPDMA0_LSTSRCREG_CH0_Pos (0U)
\r
6574 #define GPDMA0_LSTSRCREG_CH0_Msk (0x00000001U << GPDMA0_LSTSRCREG_CH0_Pos)
\r
6576 #define GPDMA0_LSTSRCREG_CH1_Pos (1U)
\r
6577 #define GPDMA0_LSTSRCREG_CH1_Msk (0x00000001U << GPDMA0_LSTSRCREG_CH1_Pos)
\r
6579 #define GPDMA0_LSTSRCREG_CH2_Pos (2U)
\r
6580 #define GPDMA0_LSTSRCREG_CH2_Msk (0x00000001U << GPDMA0_LSTSRCREG_CH2_Pos)
\r
6582 #define GPDMA0_LSTSRCREG_CH3_Pos (3U)
\r
6583 #define GPDMA0_LSTSRCREG_CH3_Msk (0x00000001U << GPDMA0_LSTSRCREG_CH3_Pos)
\r
6585 #define GPDMA0_LSTSRCREG_CH4_Pos (4U)
\r
6586 #define GPDMA0_LSTSRCREG_CH4_Msk (0x00000001U << GPDMA0_LSTSRCREG_CH4_Pos)
\r
6588 #define GPDMA0_LSTSRCREG_CH5_Pos (5U)
\r
6589 #define GPDMA0_LSTSRCREG_CH5_Msk (0x00000001U << GPDMA0_LSTSRCREG_CH5_Pos)
\r
6591 #define GPDMA0_LSTSRCREG_CH6_Pos (6U)
\r
6592 #define GPDMA0_LSTSRCREG_CH6_Msk (0x00000001U << GPDMA0_LSTSRCREG_CH6_Pos)
\r
6594 #define GPDMA0_LSTSRCREG_CH7_Pos (7U)
\r
6595 #define GPDMA0_LSTSRCREG_CH7_Msk (0x00000001U << GPDMA0_LSTSRCREG_CH7_Pos)
\r
6597 /* GPDMA0_LSTDSTREG = Last Destination Transaction Request Register*/
\r
6598 #define GPDMA0_LSTDSTREG_WE_CH0_Pos (8U)
\r
6599 #define GPDMA0_LSTDSTREG_WE_CH0_Msk (0x00000001U << GPDMA0_LSTDSTREG_WE_CH0_Pos)
\r
6601 #define GPDMA0_LSTDSTREG_WE_CH1_Pos (9U)
\r
6602 #define GPDMA0_LSTDSTREG_WE_CH1_Msk (0x00000001U << GPDMA0_LSTDSTREG_WE_CH1_Pos)
\r
6604 #define GPDMA0_LSTDSTREG_WE_CH2_Pos (10U)
\r
6605 #define GPDMA0_LSTDSTREG_WE_CH2_Msk (0x00000001U << GPDMA0_LSTDSTREG_WE_CH2_Pos)
\r
6607 #define GPDMA0_LSTDSTREG_WE_CH3_Pos (11U)
\r
6608 #define GPDMA0_LSTDSTREG_WE_CH3_Msk (0x00000001U << GPDMA0_LSTDSTREG_WE_CH3_Pos)
\r
6610 #define GPDMA0_LSTDSTREG_WE_CH4_Pos (12U)
\r
6611 #define GPDMA0_LSTDSTREG_WE_CH4_Msk (0x00000001U << GPDMA0_LSTDSTREG_WE_CH4_Pos)
\r
6613 #define GPDMA0_LSTDSTREG_WE_CH5_Pos (13U)
\r
6614 #define GPDMA0_LSTDSTREG_WE_CH5_Msk (0x00000001U << GPDMA0_LSTDSTREG_WE_CH5_Pos)
\r
6616 #define GPDMA0_LSTDSTREG_WE_CH6_Pos (14U)
\r
6617 #define GPDMA0_LSTDSTREG_WE_CH6_Msk (0x00000001U << GPDMA0_LSTDSTREG_WE_CH6_Pos)
\r
6619 #define GPDMA0_LSTDSTREG_WE_CH7_Pos (15U)
\r
6620 #define GPDMA0_LSTDSTREG_WE_CH7_Msk (0x00000001U << GPDMA0_LSTDSTREG_WE_CH7_Pos)
\r
6622 #define GPDMA0_LSTDSTREG_CH0_Pos (0U)
\r
6623 #define GPDMA0_LSTDSTREG_CH0_Msk (0x00000001U << GPDMA0_LSTDSTREG_CH0_Pos)
\r
6625 #define GPDMA0_LSTDSTREG_CH1_Pos (1U)
\r
6626 #define GPDMA0_LSTDSTREG_CH1_Msk (0x00000001U << GPDMA0_LSTDSTREG_CH1_Pos)
\r
6628 #define GPDMA0_LSTDSTREG_CH2_Pos (2U)
\r
6629 #define GPDMA0_LSTDSTREG_CH2_Msk (0x00000001U << GPDMA0_LSTDSTREG_CH2_Pos)
\r
6631 #define GPDMA0_LSTDSTREG_CH3_Pos (3U)
\r
6632 #define GPDMA0_LSTDSTREG_CH3_Msk (0x00000001U << GPDMA0_LSTDSTREG_CH3_Pos)
\r
6634 #define GPDMA0_LSTDSTREG_CH4_Pos (4U)
\r
6635 #define GPDMA0_LSTDSTREG_CH4_Msk (0x00000001U << GPDMA0_LSTDSTREG_CH4_Pos)
\r
6637 #define GPDMA0_LSTDSTREG_CH5_Pos (5U)
\r
6638 #define GPDMA0_LSTDSTREG_CH5_Msk (0x00000001U << GPDMA0_LSTDSTREG_CH5_Pos)
\r
6640 #define GPDMA0_LSTDSTREG_CH6_Pos (6U)
\r
6641 #define GPDMA0_LSTDSTREG_CH6_Msk (0x00000001U << GPDMA0_LSTDSTREG_CH6_Pos)
\r
6643 #define GPDMA0_LSTDSTREG_CH7_Pos (7U)
\r
6644 #define GPDMA0_LSTDSTREG_CH7_Msk (0x00000001U << GPDMA0_LSTDSTREG_CH7_Pos)
\r
6646 /* GPDMA0_DMACFGREG = GPDMA Configuration Register*/
\r
6647 #define GPDMA0_DMACFGREG_DMA_EN_Pos (0U)
\r
6648 #define GPDMA0_DMACFGREG_DMA_EN_Msk (0x00000001U << GPDMA0_DMACFGREG_DMA_EN_Pos)
\r
6650 /* GPDMA0_CHENREG = GPDMA Channel Enable Register*/
\r
6651 #define GPDMA0_CHENREG_WE_CH_Pos (8U)
\r
6652 #define GPDMA0_CHENREG_WE_CH_Msk (0x000000FFU << GPDMA0_CHENREG_WE_CH_Pos)
\r
6654 #define GPDMA0_CHENREG_CH_Pos (0U)
\r
6655 #define GPDMA0_CHENREG_CH_Msk (0x000000FFU << GPDMA0_CHENREG_CH_Pos)
\r
6657 /* GPDMA0_ID = GPDMA0 ID Register*/
\r
6658 #define GPDMA0_ID_VALUE_Pos (0U)
\r
6659 #define GPDMA0_ID_VALUE_Msk (0xFFFFFFFFU << GPDMA0_ID_VALUE_Pos)
\r
6661 /* GPDMA0_TYPE = GPDMA Component Type*/
\r
6662 #define GPDMA0_TYPE_VALUE_Pos (0U)
\r
6663 #define GPDMA0_TYPE_VALUE_Msk (0xFFFFFFFFU << GPDMA0_TYPE_VALUE_Pos)
\r
6665 /* GPDMA0_VERSION = DMA Component Version*/
\r
6666 #define GPDMA0_VERSION_VALUE_Pos (0U)
\r
6667 #define GPDMA0_VERSION_VALUE_Msk (0xFFFFFFFFU << GPDMA0_VERSION_VALUE_Pos)
\r
6671 /*** DSD Bit Fileds *******************/
\r
6672 /***************************************************************************/
\r
6675 /* DSD_CLC = Clock Control Register*/
\r
6676 #define DSD_CLC_DISR_Pos (0U)
\r
6677 #define DSD_CLC_DISR_Msk (0x00000001U << DSD_CLC_DISR_Pos)
\r
6679 #define DSD_CLC_DISS_Pos (1U)
\r
6680 #define DSD_CLC_DISS_Msk (0x00000001U << DSD_CLC_DISS_Pos)
\r
6682 #define DSD_CLC_EDIS_Pos (3U)
\r
6683 #define DSD_CLC_EDIS_Msk (0x00000001U << DSD_CLC_EDIS_Pos)
\r
6685 /* DSD_ID = Module Identification Register*/
\r
6686 #define DSD_ID_MOD_REV_Pos (0U)
\r
6687 #define DSD_ID_MOD_REV_Msk (0x000000FFU << DSD_ID_MOD_REV_Pos)
\r
6689 #define DSD_ID_MOD_TYPE_Pos (8U)
\r
6690 #define DSD_ID_MOD_TYPE_Msk (0x000000FFU << DSD_ID_MOD_TYPE_Pos)
\r
6692 #define DSD_ID_MOD_NUMBER_Pos (16U)
\r
6693 #define DSD_ID_MOD_NUMBER_Msk (0x0000FFFFU << DSD_ID_MOD_NUMBER_Pos)
\r
6695 /* DSD_OCS = OCDS Control and Status Register*/
\r
6696 #define DSD_OCS_SUS_Pos (24U)
\r
6697 #define DSD_OCS_SUS_Msk (0x0000000FU << DSD_OCS_SUS_Pos)
\r
6699 #define DSD_OCS_SUS_P_Pos (28U)
\r
6700 #define DSD_OCS_SUS_P_Msk (0x00000001U << DSD_OCS_SUS_P_Pos)
\r
6702 #define DSD_OCS_SUSSTA_Pos (29U)
\r
6703 #define DSD_OCS_SUSSTA_Msk (0x00000001U << DSD_OCS_SUSSTA_Pos)
\r
6705 /* DSD_GLOBCFG = Global Configuration Register*/
\r
6706 #define DSD_GLOBCFG_MCSEL_Pos (0U)
\r
6707 #define DSD_GLOBCFG_MCSEL_Msk (0x00000007U << DSD_GLOBCFG_MCSEL_Pos)
\r
6709 /* DSD_GLOBRC = Global Run Control Register*/
\r
6710 #define DSD_GLOBRC_CHRUN_Pos (0U)
\r
6711 #define DSD_GLOBRC_CHRUN_Msk (0x0000000FU << DSD_GLOBRC_CHRUN_Pos)
\r
6713 /* DSD_CGCFG = Carrier Generator Configuration Register*/
\r
6714 #define DSD_CGCFG_CGMOD_Pos (0U)
\r
6715 #define DSD_CGCFG_CGMOD_Msk (0x00000003U << DSD_CGCFG_CGMOD_Pos)
\r
6717 #define DSD_CGCFG_BREV_Pos (2U)
\r
6718 #define DSD_CGCFG_BREV_Msk (0x00000001U << DSD_CGCFG_BREV_Pos)
\r
6720 #define DSD_CGCFG_SIGPOL_Pos (3U)
\r
6721 #define DSD_CGCFG_SIGPOL_Msk (0x00000001U << DSD_CGCFG_SIGPOL_Pos)
\r
6723 #define DSD_CGCFG_DIVCG_Pos (4U)
\r
6724 #define DSD_CGCFG_DIVCG_Msk (0x0000000FU << DSD_CGCFG_DIVCG_Pos)
\r
6726 #define DSD_CGCFG_RUN_Pos (15U)
\r
6727 #define DSD_CGCFG_RUN_Msk (0x00000001U << DSD_CGCFG_RUN_Pos)
\r
6729 #define DSD_CGCFG_BITCOUNT_Pos (16U)
\r
6730 #define DSD_CGCFG_BITCOUNT_Msk (0x0000001FU << DSD_CGCFG_BITCOUNT_Pos)
\r
6732 #define DSD_CGCFG_STEPCOUNT_Pos (24U)
\r
6733 #define DSD_CGCFG_STEPCOUNT_Msk (0x0000000FU << DSD_CGCFG_STEPCOUNT_Pos)
\r
6735 #define DSD_CGCFG_STEPS_Pos (28U)
\r
6736 #define DSD_CGCFG_STEPS_Msk (0x00000001U << DSD_CGCFG_STEPS_Pos)
\r
6738 #define DSD_CGCFG_STEPD_Pos (29U)
\r
6739 #define DSD_CGCFG_STEPD_Msk (0x00000001U << DSD_CGCFG_STEPD_Pos)
\r
6741 #define DSD_CGCFG_SGNCG_Pos (30U)
\r
6742 #define DSD_CGCFG_SGNCG_Msk (0x00000001U << DSD_CGCFG_SGNCG_Pos)
\r
6744 /* DSD_EVFLAG = Event Flag Register*/
\r
6745 #define DSD_EVFLAG_RESEV0_Pos (0U)
\r
6746 #define DSD_EVFLAG_RESEV0_Msk (0x00000001U << DSD_EVFLAG_RESEV0_Pos)
\r
6748 #define DSD_EVFLAG_RESEV1_Pos (1U)
\r
6749 #define DSD_EVFLAG_RESEV1_Msk (0x00000001U << DSD_EVFLAG_RESEV1_Pos)
\r
6751 #define DSD_EVFLAG_RESEV2_Pos (2U)
\r
6752 #define DSD_EVFLAG_RESEV2_Msk (0x00000001U << DSD_EVFLAG_RESEV2_Pos)
\r
6754 #define DSD_EVFLAG_RESEV3_Pos (3U)
\r
6755 #define DSD_EVFLAG_RESEV3_Msk (0x00000001U << DSD_EVFLAG_RESEV3_Pos)
\r
6757 #define DSD_EVFLAG_ALEV0_Pos (16U)
\r
6758 #define DSD_EVFLAG_ALEV0_Msk (0x00000001U << DSD_EVFLAG_ALEV0_Pos)
\r
6760 #define DSD_EVFLAG_ALEV1_Pos (17U)
\r
6761 #define DSD_EVFLAG_ALEV1_Msk (0x00000001U << DSD_EVFLAG_ALEV1_Pos)
\r
6763 #define DSD_EVFLAG_ALEV2_Pos (18U)
\r
6764 #define DSD_EVFLAG_ALEV2_Msk (0x00000001U << DSD_EVFLAG_ALEV2_Pos)
\r
6766 #define DSD_EVFLAG_ALEV3_Pos (19U)
\r
6767 #define DSD_EVFLAG_ALEV3_Msk (0x00000001U << DSD_EVFLAG_ALEV3_Pos)
\r
6769 #define DSD_EVFLAG_ALEV4_Pos (20U)
\r
6770 #define DSD_EVFLAG_ALEV4_Msk (0x00000001U << DSD_EVFLAG_ALEV4_Pos)
\r
6772 #define DSD_EVFLAG_ALEV5_Pos (21U)
\r
6773 #define DSD_EVFLAG_ALEV5_Msk (0x00000001U << DSD_EVFLAG_ALEV5_Pos)
\r
6775 #define DSD_EVFLAG_ALEV6_Pos (22U)
\r
6776 #define DSD_EVFLAG_ALEV6_Msk (0x00000001U << DSD_EVFLAG_ALEV6_Pos)
\r
6778 #define DSD_EVFLAG_ALEV7_Pos (23U)
\r
6779 #define DSD_EVFLAG_ALEV7_Msk (0x00000001U << DSD_EVFLAG_ALEV7_Pos)
\r
6781 #define DSD_EVFLAG_ALEV8_Pos (24U)
\r
6782 #define DSD_EVFLAG_ALEV8_Msk (0x00000001U << DSD_EVFLAG_ALEV8_Pos)
\r
6784 #define DSD_EVFLAG_ALEV9_Pos (25U)
\r
6785 #define DSD_EVFLAG_ALEV9_Msk (0x00000001U << DSD_EVFLAG_ALEV9_Pos)
\r
6787 /* DSD_EVFLAGCLR = Event Flag Clear Register*/
\r
6788 #define DSD_EVFLAGCLR_RESEC0_Pos (0U)
\r
6789 #define DSD_EVFLAGCLR_RESEC0_Msk (0x00000001U << DSD_EVFLAGCLR_RESEC0_Pos)
\r
6791 #define DSD_EVFLAGCLR_RESEC1_Pos (1U)
\r
6792 #define DSD_EVFLAGCLR_RESEC1_Msk (0x00000001U << DSD_EVFLAGCLR_RESEC1_Pos)
\r
6794 #define DSD_EVFLAGCLR_RESEC2_Pos (2U)
\r
6795 #define DSD_EVFLAGCLR_RESEC2_Msk (0x00000001U << DSD_EVFLAGCLR_RESEC2_Pos)
\r
6797 #define DSD_EVFLAGCLR_RESEC3_Pos (3U)
\r
6798 #define DSD_EVFLAGCLR_RESEC3_Msk (0x00000001U << DSD_EVFLAGCLR_RESEC3_Pos)
\r
6800 #define DSD_EVFLAGCLR_ALEC0_Pos (16U)
\r
6801 #define DSD_EVFLAGCLR_ALEC0_Msk (0x00000001U << DSD_EVFLAGCLR_ALEC0_Pos)
\r
6803 #define DSD_EVFLAGCLR_ALEC1_Pos (17U)
\r
6804 #define DSD_EVFLAGCLR_ALEC1_Msk (0x00000001U << DSD_EVFLAGCLR_ALEC1_Pos)
\r
6806 #define DSD_EVFLAGCLR_ALEC2_Pos (18U)
\r
6807 #define DSD_EVFLAGCLR_ALEC2_Msk (0x00000001U << DSD_EVFLAGCLR_ALEC2_Pos)
\r
6809 #define DSD_EVFLAGCLR_ALEC3_Pos (19U)
\r
6810 #define DSD_EVFLAGCLR_ALEC3_Msk (0x00000001U << DSD_EVFLAGCLR_ALEC3_Pos)
\r
6812 /* DSD_CH_MODCFGx = Modulator Configuration Register 0*/
\r
6813 #define DSD_CH_MODCFG_DIVM_Pos (16U)
\r
6814 #define DSD_CH_MODCFG_DIVM_Msk (0x0000000FU << DSD_CH_MODCFG_DIVM_Pos)
\r
6816 #define DSD_CH_MODCFG_DWC_Pos (23U)
\r
6817 #define DSD_CH_MODCFG_DWC_Msk (0x00000001U << DSD_CH_MODCFG_DWC_Pos)
\r
6819 /* DSD_CH_DICFGx = Demodulator Input Configuration Register 0*/
\r
6820 #define DSD_CH_DICFG_DSRC_Pos (0U)
\r
6821 #define DSD_CH_DICFG_DSRC_Msk (0x0000000FU << DSD_CH_DICFG_DSRC_Pos)
\r
6823 #define DSD_CH_DICFG_DSWC_Pos (7U)
\r
6824 #define DSD_CH_DICFG_DSWC_Msk (0x00000001U << DSD_CH_DICFG_DSWC_Pos)
\r
6826 #define DSD_CH_DICFG_ITRMODE_Pos (8U)
\r
6827 #define DSD_CH_DICFG_ITRMODE_Msk (0x00000003U << DSD_CH_DICFG_ITRMODE_Pos)
\r
6829 #define DSD_CH_DICFG_TSTRMODE_Pos (10U)
\r
6830 #define DSD_CH_DICFG_TSTRMODE_Msk (0x00000003U << DSD_CH_DICFG_TSTRMODE_Pos)
\r
6832 #define DSD_CH_DICFG_TRSEL_Pos (12U)
\r
6833 #define DSD_CH_DICFG_TRSEL_Msk (0x00000007U << DSD_CH_DICFG_TRSEL_Pos)
\r
6835 #define DSD_CH_DICFG_TRWC_Pos (15U)
\r
6836 #define DSD_CH_DICFG_TRWC_Msk (0x00000001U << DSD_CH_DICFG_TRWC_Pos)
\r
6838 #define DSD_CH_DICFG_CSRC_Pos (16U)
\r
6839 #define DSD_CH_DICFG_CSRC_Msk (0x0000000FU << DSD_CH_DICFG_CSRC_Pos)
\r
6841 #define DSD_CH_DICFG_STROBE_Pos (20U)
\r
6842 #define DSD_CH_DICFG_STROBE_Msk (0x0000000FU << DSD_CH_DICFG_STROBE_Pos)
\r
6844 #define DSD_CH_DICFG_SCWC_Pos (31U)
\r
6845 #define DSD_CH_DICFG_SCWC_Msk (0x00000001U << DSD_CH_DICFG_SCWC_Pos)
\r
6847 /* DSD_CH_FCFGCx = Filter Configuration Register 0, Main Comb Filter*/
\r
6848 #define DSD_CH_FCFGC_CFMDF_Pos (0U)
\r
6849 #define DSD_CH_FCFGC_CFMDF_Msk (0x000000FFU << DSD_CH_FCFGC_CFMDF_Pos)
\r
6851 #define DSD_CH_FCFGC_CFMC_Pos (8U)
\r
6852 #define DSD_CH_FCFGC_CFMC_Msk (0x00000003U << DSD_CH_FCFGC_CFMC_Pos)
\r
6854 #define DSD_CH_FCFGC_CFEN_Pos (10U)
\r
6855 #define DSD_CH_FCFGC_CFEN_Msk (0x00000001U << DSD_CH_FCFGC_CFEN_Pos)
\r
6857 #define DSD_CH_FCFGC_SRGM_Pos (14U)
\r
6858 #define DSD_CH_FCFGC_SRGM_Msk (0x00000003U << DSD_CH_FCFGC_SRGM_Pos)
\r
6860 #define DSD_CH_FCFGC_CFMSV_Pos (16U)
\r
6861 #define DSD_CH_FCFGC_CFMSV_Msk (0x000000FFU << DSD_CH_FCFGC_CFMSV_Pos)
\r
6863 #define DSD_CH_FCFGC_CFMDCNT_Pos (24U)
\r
6864 #define DSD_CH_FCFGC_CFMDCNT_Msk (0x000000FFU << DSD_CH_FCFGC_CFMDCNT_Pos)
\r
6866 /* DSD_CH_FCFGAx = Filter Configuration Register 0, Auxiliary Filter*/
\r
6867 #define DSD_CH_FCFGA_CFADF_Pos (0U)
\r
6868 #define DSD_CH_FCFGA_CFADF_Msk (0x000000FFU << DSD_CH_FCFGA_CFADF_Pos)
\r
6870 #define DSD_CH_FCFGA_CFAC_Pos (8U)
\r
6871 #define DSD_CH_FCFGA_CFAC_Msk (0x00000003U << DSD_CH_FCFGA_CFAC_Pos)
\r
6873 #define DSD_CH_FCFGA_SRGA_Pos (10U)
\r
6874 #define DSD_CH_FCFGA_SRGA_Msk (0x00000003U << DSD_CH_FCFGA_SRGA_Pos)
\r
6876 #define DSD_CH_FCFGA_ESEL_Pos (12U)
\r
6877 #define DSD_CH_FCFGA_ESEL_Msk (0x00000003U << DSD_CH_FCFGA_ESEL_Pos)
\r
6879 #define DSD_CH_FCFGA_EGT_Pos (14U)
\r
6880 #define DSD_CH_FCFGA_EGT_Msk (0x00000001U << DSD_CH_FCFGA_EGT_Pos)
\r
6882 #define DSD_CH_FCFGA_CFADCNT_Pos (24U)
\r
6883 #define DSD_CH_FCFGA_CFADCNT_Msk (0x000000FFU << DSD_CH_FCFGA_CFADCNT_Pos)
\r
6885 /* DSD_CH_IWCTRx = Integration Window Control Register 0*/
\r
6886 #define DSD_CH_IWCTR_NVALCNT_Pos (0U)
\r
6887 #define DSD_CH_IWCTR_NVALCNT_Msk (0x0000003FU << DSD_CH_IWCTR_NVALCNT_Pos)
\r
6889 #define DSD_CH_IWCTR_INTEN_Pos (7U)
\r
6890 #define DSD_CH_IWCTR_INTEN_Msk (0x00000001U << DSD_CH_IWCTR_INTEN_Pos)
\r
6892 #define DSD_CH_IWCTR_REPCNT_Pos (8U)
\r
6893 #define DSD_CH_IWCTR_REPCNT_Msk (0x0000000FU << DSD_CH_IWCTR_REPCNT_Pos)
\r
6895 #define DSD_CH_IWCTR_REPVAL_Pos (12U)
\r
6896 #define DSD_CH_IWCTR_REPVAL_Msk (0x0000000FU << DSD_CH_IWCTR_REPVAL_Pos)
\r
6898 #define DSD_CH_IWCTR_NVALDIS_Pos (16U)
\r
6899 #define DSD_CH_IWCTR_NVALDIS_Msk (0x0000003FU << DSD_CH_IWCTR_NVALDIS_Pos)
\r
6901 #define DSD_CH_IWCTR_IWS_Pos (23U)
\r
6902 #define DSD_CH_IWCTR_IWS_Msk (0x00000001U << DSD_CH_IWCTR_IWS_Pos)
\r
6904 #define DSD_CH_IWCTR_NVALINT_Pos (24U)
\r
6905 #define DSD_CH_IWCTR_NVALINT_Msk (0x0000003FU << DSD_CH_IWCTR_NVALINT_Pos)
\r
6907 /* DSD_CH_BOUNDSELx = Boundary Select Register 0*/
\r
6908 #define DSD_CH_BOUNDSEL_BOUNDARYL_Pos (0U)
\r
6909 #define DSD_CH_BOUNDSEL_BOUNDARYL_Msk (0x0000FFFFU << DSD_CH_BOUNDSEL_BOUNDARYL_Pos)
\r
6911 #define DSD_CH_BOUNDSEL_BOUNDARYU_Pos (16U)
\r
6912 #define DSD_CH_BOUNDSEL_BOUNDARYU_Msk (0x0000FFFFU << DSD_CH_BOUNDSEL_BOUNDARYU_Pos)
\r
6914 /* DSD_CH_RESMx = Result Register x Main Filter*/
\r
6915 #define DSD_CH_RESM_RESULT_Pos (0U)
\r
6916 #define DSD_CH_RESM_RESULT_Msk (0x0000FFFFU << DSD_CH_RESM_RESULT_Pos)
\r
6918 /* DSD_CH_OFFMx = Offset Register x Main Filter*/
\r
6919 #define DSD_CH_OFFM_OFFSET_Pos (0U)
\r
6920 #define DSD_CH_OFFM_OFFSET_Msk (0x0000FFFFU << DSD_CH_OFFM_OFFSET_Pos)
\r
6922 /* DSD_CH_RESAx = Result Register x Auxiliary Filter*/
\r
6923 #define DSD_CH_RESA_RESULT_Pos (0U)
\r
6924 #define DSD_CH_RESA_RESULT_Msk (0x0000FFFFU << DSD_CH_RESA_RESULT_Pos)
\r
6926 /* DSD_CH_TSTMPx = Time-Stamp Register 0*/
\r
6927 #define DSD_CH_TSTMP_RESULT_Pos (0U)
\r
6928 #define DSD_CH_TSTMP_RESULT_Msk (0x0000FFFFU << DSD_CH_TSTMP_RESULT_Pos)
\r
6930 #define DSD_CH_TSTMP_CFMDCNT_Pos (16U)
\r
6931 #define DSD_CH_TSTMP_CFMDCNT_Msk (0x000000FFU << DSD_CH_TSTMP_CFMDCNT_Pos)
\r
6933 #define DSD_CH_TSTMP_NVALCNT_Pos (24U)
\r
6934 #define DSD_CH_TSTMP_NVALCNT_Msk (0x0000003FU << DSD_CH_TSTMP_NVALCNT_Pos)
\r
6936 /* DSD_CH_CGSYNCx = Carrier Generator Synchronization Register 0*/
\r
6937 #define DSD_CH_CGSYNC_SDCOUNT_Pos (0U)
\r
6938 #define DSD_CH_CGSYNC_SDCOUNT_Msk (0x000000FFU << DSD_CH_CGSYNC_SDCOUNT_Pos)
\r
6940 #define DSD_CH_CGSYNC_SDCAP_Pos (8U)
\r
6941 #define DSD_CH_CGSYNC_SDCAP_Msk (0x000000FFU << DSD_CH_CGSYNC_SDCAP_Pos)
\r
6943 #define DSD_CH_CGSYNC_SDPOS_Pos (16U)
\r
6944 #define DSD_CH_CGSYNC_SDPOS_Msk (0x000000FFU << DSD_CH_CGSYNC_SDPOS_Pos)
\r
6946 #define DSD_CH_CGSYNC_SDNEG_Pos (24U)
\r
6947 #define DSD_CH_CGSYNC_SDNEG_Msk (0x000000FFU << DSD_CH_CGSYNC_SDNEG_Pos)
\r
6949 /* DSD_CH_RECTCFGx = Rectification Configuration Register 0*/
\r
6950 #define DSD_CH_RECTCFG_RFEN_Pos (0U)
\r
6951 #define DSD_CH_RECTCFG_RFEN_Msk (0x00000001U << DSD_CH_RECTCFG_RFEN_Pos)
\r
6953 #define DSD_CH_RECTCFG_SSRC_Pos (4U)
\r
6954 #define DSD_CH_RECTCFG_SSRC_Msk (0x00000003U << DSD_CH_RECTCFG_SSRC_Pos)
\r
6956 #define DSD_CH_RECTCFG_SDVAL_Pos (15U)
\r
6957 #define DSD_CH_RECTCFG_SDVAL_Msk (0x00000001U << DSD_CH_RECTCFG_SDVAL_Pos)
\r
6959 #define DSD_CH_RECTCFG_SGNCS_Pos (30U)
\r
6960 #define DSD_CH_RECTCFG_SGNCS_Msk (0x00000001U << DSD_CH_RECTCFG_SGNCS_Pos)
\r
6962 #define DSD_CH_RECTCFG_SGND_Pos (31U)
\r
6963 #define DSD_CH_RECTCFG_SGND_Msk (0x00000001U << DSD_CH_RECTCFG_SGND_Pos)
\r
6967 // -------------------------------------- DWT_DWT_CTRL ------------------------------------------
\r
6968 #define DWT_DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT DWT_CTRL: CYCCNTENA Position */
\r
6969 #define DWT_DWT_CTRL_CYCCNTENA_Msk (0x01UL << DWT_DWT_CTRL_CYCCNTENA_Pos) /*!< DWT DWT_CTRL: CYCCNTENA Mask */
\r
6970 #define DWT_DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT DWT_CTRL: POSTPRESET Position */
\r
6971 #define DWT_DWT_CTRL_POSTPRESET_Msk (0x0fUL << DWT_DWT_CTRL_POSTPRESET_Pos) /*!< DWT DWT_CTRL: POSTPRESET Mask */
\r
6972 #define DWT_DWT_CTRL_POSTINIT_Pos 5 /*!< DWT DWT_CTRL: POSTINIT Position */
\r
6973 #define DWT_DWT_CTRL_POSTINIT_Msk (0x0fUL << DWT_DWT_CTRL_POSTINIT_Pos) /*!< DWT DWT_CTRL: POSTINIT Mask */
\r
6974 #define DWT_DWT_CTRL_CYCTAP_Pos 9 /*!< DWT DWT_CTRL: CYCTAP Position */
\r
6975 #define DWT_DWT_CTRL_CYCTAP_Msk (0x01UL << DWT_DWT_CTRL_CYCTAP_Pos) /*!< DWT DWT_CTRL: CYCTAP Mask */
\r
6976 #define DWT_DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT DWT_CTRL: SYNCTAP Position */
\r
6977 #define DWT_DWT_CTRL_SYNCTAP_Msk (0x03UL << DWT_DWT_CTRL_SYNCTAP_Pos) /*!< DWT DWT_CTRL: SYNCTAP Mask */
\r
6978 #define DWT_DWT_CTRL_PCSAMPLEENA_Pos 12 /*!< DWT DWT_CTRL: PCSAMPLEENA Position */
\r
6979 #define DWT_DWT_CTRL_PCSAMPLEENA_Msk (0x01UL << DWT_DWT_CTRL_PCSAMPLEENA_Pos) /*!< DWT DWT_CTRL: PCSAMPLEENA Mask */
\r
6980 #define DWT_DWT_CTRL_Reserved_Pos 13 /*!< DWT DWT_CTRL: Reserved Position */
\r
6981 #define DWT_DWT_CTRL_Reserved_Msk (0x07UL << DWT_DWT_CTRL_Reserved_Pos) /*!< DWT DWT_CTRL: Reserved Mask */
\r
6982 #define DWT_DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT DWT_CTRL: EXCTRCENA Position */
\r
6983 #define DWT_DWT_CTRL_EXCTRCENA_Msk (0x01UL << DWT_DWT_CTRL_EXCTRCENA_Pos) /*!< DWT DWT_CTRL: EXCTRCENA Mask */
\r
6984 #define DWT_DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT DWT_CTRL: CPIEVTENA Position */
\r
6985 #define DWT_DWT_CTRL_CPIEVTENA_Msk (0x01UL << DWT_DWT_CTRL_CPIEVTENA_Pos) /*!< DWT DWT_CTRL: CPIEVTENA Mask */
\r
6986 #define DWT_DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT DWT_CTRL: EXCEVTENA Position */
\r
6987 #define DWT_DWT_CTRL_EXCEVTENA_Msk (0x01UL << DWT_DWT_CTRL_EXCEVTENA_Pos) /*!< DWT DWT_CTRL: EXCEVTENA Mask */
\r
6988 #define DWT_DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT DWT_CTRL: SLEEPEVTENA Position */
\r
6989 #define DWT_DWT_CTRL_SLEEPEVTENA_Msk (0x01UL << DWT_DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT DWT_CTRL: SLEEPEVTENA Mask */
\r
6990 #define DWT_DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT DWT_CTRL: LSUEVTENA Position */
\r
6991 #define DWT_DWT_CTRL_LSUEVTENA_Msk (0x01UL << DWT_DWT_CTRL_LSUEVTENA_Pos) /*!< DWT DWT_CTRL: LSUEVTENA Mask */
\r
6992 #define DWT_DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT DWT_CTRL: FOLDEVTENA Position */
\r
6993 #define DWT_DWT_CTRL_FOLDEVTENA_Msk (0x01UL << DWT_DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT DWT_CTRL: FOLDEVTENA Mask */
\r
6994 #define DWT_DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT DWT_CTRL: CYCEVTENA Position */
\r
6995 #define DWT_DWT_CTRL_CYCEVTENA_Msk (0x01UL << DWT_DWT_CTRL_CYCEVTENA_Pos) /*!< DWT DWT_CTRL: CYCEVTENA Mask */
\r
6996 #define DWT_DWT_CTRL_Reserved1_Pos 23 /*!< DWT DWT_CTRL: Reserved1 Position */
\r
6997 #define DWT_DWT_CTRL_Reserved1_Msk (0x01UL << DWT_DWT_CTRL_Reserved1_Pos) /*!< DWT DWT_CTRL: Reserved1 Mask */
\r
6998 #define DWT_DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT DWT_CTRL: NOPRFCNT Position */
\r
6999 #define DWT_DWT_CTRL_NOPRFCNT_Msk (0x01UL << DWT_DWT_CTRL_NOPRFCNT_Pos) /*!< DWT DWT_CTRL: NOPRFCNT Mask */
\r
7000 #define DWT_DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT DWT_CTRL: NOCYCCNT Position */
\r
7001 #define DWT_DWT_CTRL_NOCYCCNT_Msk (0x01UL << DWT_DWT_CTRL_NOCYCCNT_Pos) /*!< DWT DWT_CTRL: NOCYCCNT Mask */
\r
7002 #define DWT_DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT DWT_CTRL: NOEXTTRIG Position */
\r
7003 #define DWT_DWT_CTRL_NOEXTTRIG_Msk (0x01UL << DWT_DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT DWT_CTRL: NOEXTTRIG Mask */
\r
7004 #define DWT_DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT DWT_CTRL: NOTRCPKT Position */
\r
7005 #define DWT_DWT_CTRL_NOTRCPKT_Msk (0x01UL << DWT_DWT_CTRL_NOTRCPKT_Pos) /*!< DWT DWT_CTRL: NOTRCPKT Mask */
\r
7006 #define DWT_DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT DWT_CTRL: NUMCOMP Position */
\r
7007 #define DWT_DWT_CTRL_NUMCOMP_Msk (0x0fUL << DWT_DWT_CTRL_NUMCOMP_Pos) /*!< DWT DWT_CTRL: NUMCOMP Mask */
\r
7009 // ------------------------------------- DWT_DWT_CYCCNT -----------------------------------------
\r
7010 #define DWT_DWT_CYCCNT_CYCCNT_Pos 0 /*!< DWT DWT_CYCCNT: CYCCNT Position */
\r
7011 #define DWT_DWT_CYCCNT_CYCCNT_Msk (0xffffffffUL << DWT_DWT_CYCCNT_CYCCNT_Pos) /*!< DWT DWT_CYCCNT: CYCCNT Mask */
\r
7013 // ------------------------------------- DWT_DWT_CPICNT -----------------------------------------
\r
7014 #define DWT_DWT_CPICNT_CPICNT_Pos 0 /*!< DWT DWT_CPICNT: CPICNT Position */
\r
7015 #define DWT_DWT_CPICNT_CPICNT_Msk (0x000000ffUL << DWT_DWT_CPICNT_CPICNT_Pos) /*!< DWT DWT_CPICNT: CPICNT Mask */
\r
7016 #define DWT_DWT_CPICNT_Reserved_Pos 8 /*!< DWT DWT_CPICNT: Reserved Position */
\r
7017 #define DWT_DWT_CPICNT_Reserved_Msk (0x00ffffffUL << DWT_DWT_CPICNT_Reserved_Pos) /*!< DWT DWT_CPICNT: Reserved Mask */
\r
7019 // ------------------------------------- DWT_DWT_EXCCNT -----------------------------------------
\r
7020 #define DWT_DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT DWT_EXCCNT: EXCCNT Position */
\r
7021 #define DWT_DWT_EXCCNT_EXCCNT_Msk (0x000000ffUL << DWT_DWT_EXCCNT_EXCCNT_Pos) /*!< DWT DWT_EXCCNT: EXCCNT Mask */
\r
7022 #define DWT_DWT_EXCCNT_Reserved_Pos 8 /*!< DWT DWT_EXCCNT: Reserved Position */
\r
7023 #define DWT_DWT_EXCCNT_Reserved_Msk (0x00ffffffUL << DWT_DWT_EXCCNT_Reserved_Pos) /*!< DWT DWT_EXCCNT: Reserved Mask */
\r
7025 // ------------------------------------ DWT_DWT_SLEEPCNT ----------------------------------------
\r
7026 #define DWT_DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT DWT_SLEEPCNT: SLEEPCNT Position */
\r
7027 #define DWT_DWT_SLEEPCNT_SLEEPCNT_Msk (0x000000ffUL << DWT_DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT DWT_SLEEPCNT: SLEEPCNT Mask */
\r
7028 #define DWT_DWT_SLEEPCNT_Reserved_Pos 8 /*!< DWT DWT_SLEEPCNT: Reserved Position */
\r
7029 #define DWT_DWT_SLEEPCNT_Reserved_Msk (0x00ffffffUL << DWT_DWT_SLEEPCNT_Reserved_Pos) /*!< DWT DWT_SLEEPCNT: Reserved Mask */
\r
7031 // ------------------------------------- DWT_DWT_LSUCNT -----------------------------------------
\r
7032 #define DWT_DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT DWT_LSUCNT: LSUCNT Position */
\r
7033 #define DWT_DWT_LSUCNT_LSUCNT_Msk (0x000000ffUL << DWT_DWT_LSUCNT_LSUCNT_Pos) /*!< DWT DWT_LSUCNT: LSUCNT Mask */
\r
7034 #define DWT_DWT_LSUCNT_Reserved_Pos 8 /*!< DWT DWT_LSUCNT: Reserved Position */
\r
7035 #define DWT_DWT_LSUCNT_Reserved_Msk (0x00ffffffUL << DWT_DWT_LSUCNT_Reserved_Pos) /*!< DWT DWT_LSUCNT: Reserved Mask */
\r
7037 // ------------------------------------- DWT_DWT_FOLDCNT ----------------------------------------
\r
7038 #define DWT_DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT DWT_FOLDCNT: FOLDCNT Position */
\r
7039 #define DWT_DWT_FOLDCNT_FOLDCNT_Msk (0x000000ffUL << DWT_DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT DWT_FOLDCNT: FOLDCNT Mask */
\r
7040 #define DWT_DWT_FOLDCNT_Reserved_Pos 8 /*!< DWT DWT_FOLDCNT: Reserved Position */
\r
7041 #define DWT_DWT_FOLDCNT_Reserved_Msk (0x00ffffffUL << DWT_DWT_FOLDCNT_Reserved_Pos) /*!< DWT DWT_FOLDCNT: Reserved Mask */
\r
7043 // -------------------------------------- DWT_DWT_PCSR ------------------------------------------
\r
7044 #define DWT_DWT_PCSR_EIASAMPLE_Pos 0 /*!< DWT DWT_PCSR: EIASAMPLE Position */
\r
7045 #define DWT_DWT_PCSR_EIASAMPLE_Msk (0xffffffffUL << DWT_DWT_PCSR_EIASAMPLE_Pos) /*!< DWT DWT_PCSR: EIASAMPLE Mask */
\r
7047 // -------------------------------------- DWT_DWT_COMP0 -----------------------------------------
\r
7048 #define DWT_DWT_COMP0_COMP_Pos 0 /*!< DWT DWT_COMP0: COMP Position */
\r
7049 #define DWT_DWT_COMP0_COMP_Msk (0xffffffffUL << DWT_DWT_COMP0_COMP_Pos) /*!< DWT DWT_COMP0: COMP Mask */
\r
7051 // -------------------------------------- DWT_DWT_MASK0 -----------------------------------------
\r
7052 #define DWT_DWT_MASK0_MASK_Pos 0 /*!< DWT DWT_MASK0: MASK Position */
\r
7053 #define DWT_DWT_MASK0_MASK_Msk (0x1fUL << DWT_DWT_MASK0_MASK_Pos) /*!< DWT DWT_MASK0: MASK Mask */
\r
7054 #define DWT_DWT_MASK0_Reserved_Pos 5 /*!< DWT DWT_MASK0: Reserved Position */
\r
7055 #define DWT_DWT_MASK0_Reserved_Msk (0x07ffffffUL << DWT_DWT_MASK0_Reserved_Pos) /*!< DWT DWT_MASK0: Reserved Mask */
\r
7057 // ------------------------------------ DWT_DWT_FUNCTION0 ---------------------------------------
\r
7058 #define DWT_DWT_FUNCTION0_FUNCTION_Pos 0 /*!< DWT DWT_FUNCTION0: FUNCTION Position */
\r
7059 #define DWT_DWT_FUNCTION0_FUNCTION_Msk (0x0fUL << DWT_DWT_FUNCTION0_FUNCTION_Pos) /*!< DWT DWT_FUNCTION0: FUNCTION Mask */
\r
7060 #define DWT_DWT_FUNCTION0_Reserved_Pos 4 /*!< DWT DWT_FUNCTION0: Reserved Position */
\r
7061 #define DWT_DWT_FUNCTION0_Reserved_Msk (0x01UL << DWT_DWT_FUNCTION0_Reserved_Pos) /*!< DWT DWT_FUNCTION0: Reserved Mask */
\r
7062 #define DWT_DWT_FUNCTION0_EMITRANGE_Pos 5 /*!< DWT DWT_FUNCTION0: EMITRANGE Position */
\r
7063 #define DWT_DWT_FUNCTION0_EMITRANGE_Msk (0x01UL << DWT_DWT_FUNCTION0_EMITRANGE_Pos) /*!< DWT DWT_FUNCTION0: EMITRANGE Mask */
\r
7064 #define DWT_DWT_FUNCTION0_Reserved1_Pos 6 /*!< DWT DWT_FUNCTION0: Reserved1 Position */
\r
7065 #define DWT_DWT_FUNCTION0_Reserved1_Msk (0x01UL << DWT_DWT_FUNCTION0_Reserved1_Pos) /*!< DWT DWT_FUNCTION0: Reserved1 Mask */
\r
7066 #define DWT_DWT_FUNCTION0_CYCMATCH_Pos 7 /*!< DWT DWT_FUNCTION0: CYCMATCH Position */
\r
7067 #define DWT_DWT_FUNCTION0_CYCMATCH_Msk (0x01UL << DWT_DWT_FUNCTION0_CYCMATCH_Pos) /*!< DWT DWT_FUNCTION0: CYCMATCH Mask */
\r
7068 #define DWT_DWT_FUNCTION0_DATAVMATCH_Pos 8 /*!< DWT DWT_FUNCTION0: DATAVMATCH Position */
\r
7069 #define DWT_DWT_FUNCTION0_DATAVMATCH_Msk (0x01UL << DWT_DWT_FUNCTION0_DATAVMATCH_Pos) /*!< DWT DWT_FUNCTION0: DATAVMATCH Mask */
\r
7070 #define DWT_DWT_FUNCTION0_LNK1ENA_Pos 9 /*!< DWT DWT_FUNCTION0: LNK1ENA Position */
\r
7071 #define DWT_DWT_FUNCTION0_LNK1ENA_Msk (0x01UL << DWT_DWT_FUNCTION0_LNK1ENA_Pos) /*!< DWT DWT_FUNCTION0: LNK1ENA Mask */
\r
7072 #define DWT_DWT_FUNCTION0_DATAVSIZE_Pos 10 /*!< DWT DWT_FUNCTION0: DATAVSIZE Position */
\r
7073 #define DWT_DWT_FUNCTION0_DATAVSIZE_Msk (0x03UL << DWT_DWT_FUNCTION0_DATAVSIZE_Pos) /*!< DWT DWT_FUNCTION0: DATAVSIZE Mask */
\r
7074 #define DWT_DWT_FUNCTION0_DATAVADDR0_Pos 12 /*!< DWT DWT_FUNCTION0: DATAVADDR0 Position */
\r
7075 #define DWT_DWT_FUNCTION0_DATAVADDR0_Msk (0x0fUL << DWT_DWT_FUNCTION0_DATAVADDR0_Pos) /*!< DWT DWT_FUNCTION0: DATAVADDR0 Mask */
\r
7076 #define DWT_DWT_FUNCTION0_DATAVADDR1_Pos 16 /*!< DWT DWT_FUNCTION0: DATAVADDR1 Position */
\r
7077 #define DWT_DWT_FUNCTION0_DATAVADDR1_Msk (0x0fUL << DWT_DWT_FUNCTION0_DATAVADDR1_Pos) /*!< DWT DWT_FUNCTION0: DATAVADDR1 Mask */
\r
7078 #define DWT_DWT_FUNCTION0_Reserved2_Pos 20 /*!< DWT DWT_FUNCTION0: Reserved2 Position */
\r
7079 #define DWT_DWT_FUNCTION0_Reserved2_Msk (0x0fUL << DWT_DWT_FUNCTION0_Reserved2_Pos) /*!< DWT DWT_FUNCTION0: Reserved2 Mask */
\r
7080 #define DWT_DWT_FUNCTION0_MATCHED_Pos 24 /*!< DWT DWT_FUNCTION0: MATCHED Position */
\r
7081 #define DWT_DWT_FUNCTION0_MATCHED_Msk (0x01UL << DWT_DWT_FUNCTION0_MATCHED_Pos) /*!< DWT DWT_FUNCTION0: MATCHED Mask */
\r
7082 #define DWT_DWT_FUNCTION0_Reserved3_Pos 25 /*!< DWT DWT_FUNCTION0: Reserved3 Position */
\r
7083 #define DWT_DWT_FUNCTION0_Reserved3_Msk (0x7fUL << DWT_DWT_FUNCTION0_Reserved3_Pos) /*!< DWT DWT_FUNCTION0: Reserved3 Mask */
\r
7085 // -------------------------------------- DWT_DWT_COMP1 -----------------------------------------
\r
7086 #define DWT_DWT_COMP1_COMP_Pos 0 /*!< DWT DWT_COMP1: COMP Position */
\r
7087 #define DWT_DWT_COMP1_COMP_Msk (0xffffffffUL << DWT_DWT_COMP1_COMP_Pos) /*!< DWT DWT_COMP1: COMP Mask */
\r
7089 // -------------------------------------- DWT_DWT_MASK1 -----------------------------------------
\r
7090 #define DWT_DWT_MASK1_MASK_Pos 0 /*!< DWT DWT_MASK1: MASK Position */
\r
7091 #define DWT_DWT_MASK1_MASK_Msk (0x1fUL << DWT_DWT_MASK1_MASK_Pos) /*!< DWT DWT_MASK1: MASK Mask */
\r
7092 #define DWT_DWT_MASK1_Reserved_Pos 5 /*!< DWT DWT_MASK1: Reserved Position */
\r
7093 #define DWT_DWT_MASK1_Reserved_Msk (0x07ffffffUL << DWT_DWT_MASK1_Reserved_Pos) /*!< DWT DWT_MASK1: Reserved Mask */
\r
7095 // ------------------------------------ DWT_DWT_FUNCTION1 ---------------------------------------
\r
7096 #define DWT_DWT_FUNCTION1_FUNCTION_Pos 0 /*!< DWT DWT_FUNCTION1: FUNCTION Position */
\r
7097 #define DWT_DWT_FUNCTION1_FUNCTION_Msk (0x0fUL << DWT_DWT_FUNCTION1_FUNCTION_Pos) /*!< DWT DWT_FUNCTION1: FUNCTION Mask */
\r
7098 #define DWT_DWT_FUNCTION1_Reserved_Pos 4 /*!< DWT DWT_FUNCTION1: Reserved Position */
\r
7099 #define DWT_DWT_FUNCTION1_Reserved_Msk (0x01UL << DWT_DWT_FUNCTION1_Reserved_Pos) /*!< DWT DWT_FUNCTION1: Reserved Mask */
\r
7100 #define DWT_DWT_FUNCTION1_EMITRANGE_Pos 5 /*!< DWT DWT_FUNCTION1: EMITRANGE Position */
\r
7101 #define DWT_DWT_FUNCTION1_EMITRANGE_Msk (0x01UL << DWT_DWT_FUNCTION1_EMITRANGE_Pos) /*!< DWT DWT_FUNCTION1: EMITRANGE Mask */
\r
7102 #define DWT_DWT_FUNCTION1_Reserved1_Pos 6 /*!< DWT DWT_FUNCTION1: Reserved1 Position */
\r
7103 #define DWT_DWT_FUNCTION1_Reserved1_Msk (0x03UL << DWT_DWT_FUNCTION1_Reserved1_Pos) /*!< DWT DWT_FUNCTION1: Reserved1 Mask */
\r
7104 #define DWT_DWT_FUNCTION1_DATAVMATCH_Pos 8 /*!< DWT DWT_FUNCTION1: DATAVMATCH Position */
\r
7105 #define DWT_DWT_FUNCTION1_DATAVMATCH_Msk (0x01UL << DWT_DWT_FUNCTION1_DATAVMATCH_Pos) /*!< DWT DWT_FUNCTION1: DATAVMATCH Mask */
\r
7106 #define DWT_DWT_FUNCTION1_LNK1ENA_Pos 9 /*!< DWT DWT_FUNCTION1: LNK1ENA Position */
\r
7107 #define DWT_DWT_FUNCTION1_LNK1ENA_Msk (0x01UL << DWT_DWT_FUNCTION1_LNK1ENA_Pos) /*!< DWT DWT_FUNCTION1: LNK1ENA Mask */
\r
7108 #define DWT_DWT_FUNCTION1_DATAVSIZE_Pos 10 /*!< DWT DWT_FUNCTION1: DATAVSIZE Position */
\r
7109 #define DWT_DWT_FUNCTION1_DATAVSIZE_Msk (0x03UL << DWT_DWT_FUNCTION1_DATAVSIZE_Pos) /*!< DWT DWT_FUNCTION1: DATAVSIZE Mask */
\r
7110 #define DWT_DWT_FUNCTION1_DATAVADDR0_Pos 12 /*!< DWT DWT_FUNCTION1: DATAVADDR0 Position */
\r
7111 #define DWT_DWT_FUNCTION1_DATAVADDR0_Msk (0x0fUL << DWT_DWT_FUNCTION1_DATAVADDR0_Pos) /*!< DWT DWT_FUNCTION1: DATAVADDR0 Mask */
\r
7112 #define DWT_DWT_FUNCTION1_DATAVADDR1_Pos 16 /*!< DWT DWT_FUNCTION1: DATAVADDR1 Position */
\r
7113 #define DWT_DWT_FUNCTION1_DATAVADDR1_Msk (0x0fUL << DWT_DWT_FUNCTION1_DATAVADDR1_Pos) /*!< DWT DWT_FUNCTION1: DATAVADDR1 Mask */
\r
7114 #define DWT_DWT_FUNCTION1_Reserved2_Pos 20 /*!< DWT DWT_FUNCTION1: Reserved2 Position */
\r
7115 #define DWT_DWT_FUNCTION1_Reserved2_Msk (0x0fUL << DWT_DWT_FUNCTION1_Reserved2_Pos) /*!< DWT DWT_FUNCTION1: Reserved2 Mask */
\r
7116 #define DWT_DWT_FUNCTION1_MATCHED_Pos 24 /*!< DWT DWT_FUNCTION1: MATCHED Position */
\r
7117 #define DWT_DWT_FUNCTION1_MATCHED_Msk (0x01UL << DWT_DWT_FUNCTION1_MATCHED_Pos) /*!< DWT DWT_FUNCTION1: MATCHED Mask */
\r
7118 #define DWT_DWT_FUNCTION1_Reserved3_Pos 25 /*!< DWT DWT_FUNCTION1: Reserved3 Position */
\r
7119 #define DWT_DWT_FUNCTION1_Reserved3_Msk (0x7fUL << DWT_DWT_FUNCTION1_Reserved3_Pos) /*!< DWT DWT_FUNCTION1: Reserved3 Mask */
\r
7121 // -------------------------------------- DWT_DWT_COMP2 -----------------------------------------
\r
7122 #define DWT_DWT_COMP2_COMP_Pos 0 /*!< DWT DWT_COMP2: COMP Position */
\r
7123 #define DWT_DWT_COMP2_COMP_Msk (0xffffffffUL << DWT_DWT_COMP2_COMP_Pos) /*!< DWT DWT_COMP2: COMP Mask */
\r
7125 // -------------------------------------- DWT_DWT_MASK2 -----------------------------------------
\r
7126 #define DWT_DWT_MASK2_MASK_Pos 0 /*!< DWT DWT_MASK2: MASK Position */
\r
7127 #define DWT_DWT_MASK2_MASK_Msk (0x1fUL << DWT_DWT_MASK2_MASK_Pos) /*!< DWT DWT_MASK2: MASK Mask */
\r
7128 #define DWT_DWT_MASK2_Reserved_Pos 5 /*!< DWT DWT_MASK2: Reserved Position */
\r
7129 #define DWT_DWT_MASK2_Reserved_Msk (0x07ffffffUL << DWT_DWT_MASK2_Reserved_Pos) /*!< DWT DWT_MASK2: Reserved Mask */
\r
7131 // ------------------------------------ DWT_DWT_FUNCTION2 ---------------------------------------
\r
7132 #define DWT_DWT_FUNCTION2_FUNCTION_Pos 0 /*!< DWT DWT_FUNCTION2: FUNCTION Position */
\r
7133 #define DWT_DWT_FUNCTION2_FUNCTION_Msk (0x0fUL << DWT_DWT_FUNCTION2_FUNCTION_Pos) /*!< DWT DWT_FUNCTION2: FUNCTION Mask */
\r
7134 #define DWT_DWT_FUNCTION2_Reserved_Pos 4 /*!< DWT DWT_FUNCTION2: Reserved Position */
\r
7135 #define DWT_DWT_FUNCTION2_Reserved_Msk (0x01UL << DWT_DWT_FUNCTION2_Reserved_Pos) /*!< DWT DWT_FUNCTION2: Reserved Mask */
\r
7136 #define DWT_DWT_FUNCTION2_EMITRANGE_Pos 5 /*!< DWT DWT_FUNCTION2: EMITRANGE Position */
\r
7137 #define DWT_DWT_FUNCTION2_EMITRANGE_Msk (0x01UL << DWT_DWT_FUNCTION2_EMITRANGE_Pos) /*!< DWT DWT_FUNCTION2: EMITRANGE Mask */
\r
7138 #define DWT_DWT_FUNCTION2_Reserved1_Pos 6 /*!< DWT DWT_FUNCTION2: Reserved1 Position */
\r
7139 #define DWT_DWT_FUNCTION2_Reserved1_Msk (0x03UL << DWT_DWT_FUNCTION2_Reserved1_Pos) /*!< DWT DWT_FUNCTION2: Reserved1 Mask */
\r
7140 #define DWT_DWT_FUNCTION2_DATAVMATCH_Pos 8 /*!< DWT DWT_FUNCTION2: DATAVMATCH Position */
\r
7141 #define DWT_DWT_FUNCTION2_DATAVMATCH_Msk (0x01UL << DWT_DWT_FUNCTION2_DATAVMATCH_Pos) /*!< DWT DWT_FUNCTION2: DATAVMATCH Mask */
\r
7142 #define DWT_DWT_FUNCTION2_LNK1ENA_Pos 9 /*!< DWT DWT_FUNCTION2: LNK1ENA Position */
\r
7143 #define DWT_DWT_FUNCTION2_LNK1ENA_Msk (0x01UL << DWT_DWT_FUNCTION2_LNK1ENA_Pos) /*!< DWT DWT_FUNCTION2: LNK1ENA Mask */
\r
7144 #define DWT_DWT_FUNCTION2_DATAVSIZE_Pos 10 /*!< DWT DWT_FUNCTION2: DATAVSIZE Position */
\r
7145 #define DWT_DWT_FUNCTION2_DATAVSIZE_Msk (0x03UL << DWT_DWT_FUNCTION2_DATAVSIZE_Pos) /*!< DWT DWT_FUNCTION2: DATAVSIZE Mask */
\r
7146 #define DWT_DWT_FUNCTION2_DATAVADDR0_Pos 12 /*!< DWT DWT_FUNCTION2: DATAVADDR0 Position */
\r
7147 #define DWT_DWT_FUNCTION2_DATAVADDR0_Msk (0x0fUL << DWT_DWT_FUNCTION2_DATAVADDR0_Pos) /*!< DWT DWT_FUNCTION2: DATAVADDR0 Mask */
\r
7148 #define DWT_DWT_FUNCTION2_DATAVADDR1_Pos 16 /*!< DWT DWT_FUNCTION2: DATAVADDR1 Position */
\r
7149 #define DWT_DWT_FUNCTION2_DATAVADDR1_Msk (0x0fUL << DWT_DWT_FUNCTION2_DATAVADDR1_Pos) /*!< DWT DWT_FUNCTION2: DATAVADDR1 Mask */
\r
7150 #define DWT_DWT_FUNCTION2_Reserved2_Pos 20 /*!< DWT DWT_FUNCTION2: Reserved2 Position */
\r
7151 #define DWT_DWT_FUNCTION2_Reserved2_Msk (0x0fUL << DWT_DWT_FUNCTION2_Reserved2_Pos) /*!< DWT DWT_FUNCTION2: Reserved2 Mask */
\r
7152 #define DWT_DWT_FUNCTION2_MATCHED_Pos 24 /*!< DWT DWT_FUNCTION2: MATCHED Position */
\r
7153 #define DWT_DWT_FUNCTION2_MATCHED_Msk (0x01UL << DWT_DWT_FUNCTION2_MATCHED_Pos) /*!< DWT DWT_FUNCTION2: MATCHED Mask */
\r
7154 #define DWT_DWT_FUNCTION2_Reserved3_Pos 25 /*!< DWT DWT_FUNCTION2: Reserved3 Position */
\r
7155 #define DWT_DWT_FUNCTION2_Reserved3_Msk (0x7fUL << DWT_DWT_FUNCTION2_Reserved3_Pos) /*!< DWT DWT_FUNCTION2: Reserved3 Mask */
\r
7157 // -------------------------------------- DWT_DWT_COMP3 -----------------------------------------
\r
7158 #define DWT_DWT_COMP3_COMP_Pos 0 /*!< DWT DWT_COMP3: COMP Position */
\r
7159 #define DWT_DWT_COMP3_COMP_Msk (0xffffffffUL << DWT_DWT_COMP3_COMP_Pos) /*!< DWT DWT_COMP3: COMP Mask */
\r
7161 // -------------------------------------- DWT_DWT_MASK3 -----------------------------------------
\r
7162 #define DWT_DWT_MASK3_MASK_Pos 0 /*!< DWT DWT_MASK3: MASK Position */
\r
7163 #define DWT_DWT_MASK3_MASK_Msk (0x1fUL << DWT_DWT_MASK3_MASK_Pos) /*!< DWT DWT_MASK3: MASK Mask */
\r
7164 #define DWT_DWT_MASK3_Reserved_Pos 5 /*!< DWT DWT_MASK3: Reserved Position */
\r
7165 #define DWT_DWT_MASK3_Reserved_Msk (0x07ffffffUL << DWT_DWT_MASK3_Reserved_Pos) /*!< DWT DWT_MASK3: Reserved Mask */
\r
7167 // ------------------------------------ DWT_DWT_FUNCTION3 ---------------------------------------
\r
7168 #define DWT_DWT_FUNCTION3_FUNCTION_Pos 0 /*!< DWT DWT_FUNCTION3: FUNCTION Position */
\r
7169 #define DWT_DWT_FUNCTION3_FUNCTION_Msk (0x0fUL << DWT_DWT_FUNCTION3_FUNCTION_Pos) /*!< DWT DWT_FUNCTION3: FUNCTION Mask */
\r
7170 #define DWT_DWT_FUNCTION3_Reserved_Pos 4 /*!< DWT DWT_FUNCTION3: Reserved Position */
\r
7171 #define DWT_DWT_FUNCTION3_Reserved_Msk (0x01UL << DWT_DWT_FUNCTION3_Reserved_Pos) /*!< DWT DWT_FUNCTION3: Reserved Mask */
\r
7172 #define DWT_DWT_FUNCTION3_EMITRANGE_Pos 5 /*!< DWT DWT_FUNCTION3: EMITRANGE Position */
\r
7173 #define DWT_DWT_FUNCTION3_EMITRANGE_Msk (0x01UL << DWT_DWT_FUNCTION3_EMITRANGE_Pos) /*!< DWT DWT_FUNCTION3: EMITRANGE Mask */
\r
7174 #define DWT_DWT_FUNCTION3_Reserved1_Pos 6 /*!< DWT DWT_FUNCTION3: Reserved1 Position */
\r
7175 #define DWT_DWT_FUNCTION3_Reserved1_Msk (0x03UL << DWT_DWT_FUNCTION3_Reserved1_Pos) /*!< DWT DWT_FUNCTION3: Reserved1 Mask */
\r
7176 #define DWT_DWT_FUNCTION3_DATAVMATCH_Pos 8 /*!< DWT DWT_FUNCTION3: DATAVMATCH Position */
\r
7177 #define DWT_DWT_FUNCTION3_DATAVMATCH_Msk (0x01UL << DWT_DWT_FUNCTION3_DATAVMATCH_Pos) /*!< DWT DWT_FUNCTION3: DATAVMATCH Mask */
\r
7178 #define DWT_DWT_FUNCTION3_LNK1ENA_Pos 9 /*!< DWT DWT_FUNCTION3: LNK1ENA Position */
\r
7179 #define DWT_DWT_FUNCTION3_LNK1ENA_Msk (0x01UL << DWT_DWT_FUNCTION3_LNK1ENA_Pos) /*!< DWT DWT_FUNCTION3: LNK1ENA Mask */
\r
7180 #define DWT_DWT_FUNCTION3_DATAVSIZE_Pos 10 /*!< DWT DWT_FUNCTION3: DATAVSIZE Position */
\r
7181 #define DWT_DWT_FUNCTION3_DATAVSIZE_Msk (0x03UL << DWT_DWT_FUNCTION3_DATAVSIZE_Pos) /*!< DWT DWT_FUNCTION3: DATAVSIZE Mask */
\r
7182 #define DWT_DWT_FUNCTION3_DATAVADDR0_Pos 12 /*!< DWT DWT_FUNCTION3: DATAVADDR0 Position */
\r
7183 #define DWT_DWT_FUNCTION3_DATAVADDR0_Msk (0x0fUL << DWT_DWT_FUNCTION3_DATAVADDR0_Pos) /*!< DWT DWT_FUNCTION3: DATAVADDR0 Mask */
\r
7184 #define DWT_DWT_FUNCTION3_DATAVADDR1_Pos 16 /*!< DWT DWT_FUNCTION3: DATAVADDR1 Position */
\r
7185 #define DWT_DWT_FUNCTION3_DATAVADDR1_Msk (0x0fUL << DWT_DWT_FUNCTION3_DATAVADDR1_Pos) /*!< DWT DWT_FUNCTION3: DATAVADDR1 Mask */
\r
7186 #define DWT_DWT_FUNCTION3_Reserved2_Pos 20 /*!< DWT DWT_FUNCTION3: Reserved2 Position */
\r
7187 #define DWT_DWT_FUNCTION3_Reserved2_Msk (0x0fUL << DWT_DWT_FUNCTION3_Reserved2_Pos) /*!< DWT DWT_FUNCTION3: Reserved2 Mask */
\r
7188 #define DWT_DWT_FUNCTION3_MATCHED_Pos 24 /*!< DWT DWT_FUNCTION3: MATCHED Position */
\r
7189 #define DWT_DWT_FUNCTION3_MATCHED_Msk (0x01UL << DWT_DWT_FUNCTION3_MATCHED_Pos) /*!< DWT DWT_FUNCTION3: MATCHED Mask */
\r
7190 #define DWT_DWT_FUNCTION3_Reserved3_Pos 25 /*!< DWT DWT_FUNCTION3: Reserved3 Position */
\r
7191 #define DWT_DWT_FUNCTION3_Reserved3_Msk (0x7fUL << DWT_DWT_FUNCTION3_Reserved3_Pos) /*!< DWT DWT_FUNCTION3: Reserved3 Mask */
\r
7193 // --------------------------------------- DWT_DWTPID4 ------------------------------------------
\r
7194 #define DWT_DWTPID4_PID4_Pos 0 /*!< DWT DWTPID4: PID4 Position */
\r
7195 #define DWT_DWTPID4_PID4_Msk (0xffffffffUL << DWT_DWTPID4_PID4_Pos) /*!< DWT DWTPID4: PID4 Mask */
\r
7197 // --------------------------------------- DWT_DWTPID5 ------------------------------------------
\r
7198 #define DWT_DWTPID5_PID5_Pos 0 /*!< DWT DWTPID5: PID5 Position */
\r
7199 #define DWT_DWTPID5_PID5_Msk (0xffffffffUL << DWT_DWTPID5_PID5_Pos) /*!< DWT DWTPID5: PID5 Mask */
\r
7201 // --------------------------------------- DWT_DWTPID6 ------------------------------------------
\r
7202 #define DWT_DWTPID6_PID6_Pos 0 /*!< DWT DWTPID6: PID6 Position */
\r
7203 #define DWT_DWTPID6_PID6_Msk (0xffffffffUL << DWT_DWTPID6_PID6_Pos) /*!< DWT DWTPID6: PID6 Mask */
\r
7205 // --------------------------------------- DWT_DWTPID7 ------------------------------------------
\r
7206 #define DWT_DWTPID7_PID7_Pos 0 /*!< DWT DWTPID7: PID7 Position */
\r
7207 #define DWT_DWTPID7_PID7_Msk (0xffffffffUL << DWT_DWTPID7_PID7_Pos) /*!< DWT DWTPID7: PID7 Mask */
\r
7209 // --------------------------------------- DWT_DWTPID0 ------------------------------------------
\r
7210 #define DWT_DWTPID0_PID0_Pos 0 /*!< DWT DWTPID0: PID0 Position */
\r
7211 #define DWT_DWTPID0_PID0_Msk (0xffffffffUL << DWT_DWTPID0_PID0_Pos) /*!< DWT DWTPID0: PID0 Mask */
\r
7213 // --------------------------------------- DWT_DWTPID1 ------------------------------------------
\r
7214 #define DWT_DWTPID1_PID1_Pos 0 /*!< DWT DWTPID1: PID1 Position */
\r
7215 #define DWT_DWTPID1_PID1_Msk (0xffffffffUL << DWT_DWTPID1_PID1_Pos) /*!< DWT DWTPID1: PID1 Mask */
\r
7217 // --------------------------------------- DWT_DWTPID2 ------------------------------------------
\r
7218 #define DWT_DWTPID2_PID2_Pos 0 /*!< DWT DWTPID2: PID2 Position */
\r
7219 #define DWT_DWTPID2_PID2_Msk (0xffffffffUL << DWT_DWTPID2_PID2_Pos) /*!< DWT DWTPID2: PID2 Mask */
\r
7221 // --------------------------------------- DWT_DWTPID3 ------------------------------------------
\r
7222 #define DWT_DWTPID3_PID3_Pos 0 /*!< DWT DWTPID3: PID3 Position */
\r
7223 #define DWT_DWTPID3_PID3_Msk (0xffffffffUL << DWT_DWTPID3_PID3_Pos) /*!< DWT DWTPID3: PID3 Mask */
\r
7225 // --------------------------------------- DWT_DWTCID0 ------------------------------------------
\r
7226 #define DWT_DWTCID0_CID0_Pos 0 /*!< DWT DWTCID0: CID0 Position */
\r
7227 #define DWT_DWTCID0_CID0_Msk (0xffffffffUL << DWT_DWTCID0_CID0_Pos) /*!< DWT DWTCID0: CID0 Mask */
\r
7229 // --------------------------------------- DWT_DWTCID1 ------------------------------------------
\r
7230 #define DWT_DWTCID1_CID1_Pos 0 /*!< DWT DWTCID1: CID1 Position */
\r
7231 #define DWT_DWTCID1_CID1_Msk (0xffffffffUL << DWT_DWTCID1_CID1_Pos) /*!< DWT DWTCID1: CID1 Mask */
\r
7233 // --------------------------------------- DWT_DWTCID2 ------------------------------------------
\r
7234 #define DWT_DWTCID2_CID2_Pos 0 /*!< DWT DWTCID2: CID2 Position */
\r
7235 #define DWT_DWTCID2_CID2_Msk (0xffffffffUL << DWT_DWTCID2_CID2_Pos) /*!< DWT DWTCID2: CID2 Mask */
\r
7237 // --------------------------------------- DWT_DWTCID3 ------------------------------------------
\r
7238 #define DWT_DWTCID3_CID3_Pos 0 /*!< DWT DWTCID3: CID3 Position */
\r
7239 #define DWT_DWTCID3_CID3_Msk (0xffffffffUL << DWT_DWTCID3_CID3_Pos) /*!< DWT DWTCID3: CID3 Mask */
\r
7243 /*** EBU Bit Fileds *******************/
\r
7244 /***************************************************************************/
\r
7247 /* EBU_CLC = EBU Clock Control Register*/
\r
7248 #define EBU_CLC_DISR_Pos (0U)
\r
7249 #define EBU_CLC_DISR_Msk (0x00000001U << EBU_CLC_DISR_Pos)
\r
7251 #define EBU_CLC_DISS_Pos (1U)
\r
7252 #define EBU_CLC_DISS_Msk (0x00000001U << EBU_CLC_DISS_Pos)
\r
7254 #define EBU_CLC_SYNC_Pos (16U)
\r
7255 #define EBU_CLC_SYNC_Msk (0x00000001U << EBU_CLC_SYNC_Pos)
\r
7257 #define EBU_CLC_DIV2_Pos (17U)
\r
7258 #define EBU_CLC_DIV2_Msk (0x00000001U << EBU_CLC_DIV2_Pos)
\r
7260 #define EBU_CLC_EBUDIV_Pos (18U)
\r
7261 #define EBU_CLC_EBUDIV_Msk (0x00000003U << EBU_CLC_EBUDIV_Pos)
\r
7263 #define EBU_CLC_SYNCACK_Pos (20U)
\r
7264 #define EBU_CLC_SYNCACK_Msk (0x00000001U << EBU_CLC_SYNCACK_Pos)
\r
7266 #define EBU_CLC_DIV2ACK_Pos (21U)
\r
7267 #define EBU_CLC_DIV2ACK_Msk (0x00000001U << EBU_CLC_DIV2ACK_Pos)
\r
7269 #define EBU_CLC_EBUDIVACK_Pos (22U)
\r
7270 #define EBU_CLC_EBUDIVACK_Msk (0x00000003U << EBU_CLC_EBUDIVACK_Pos)
\r
7272 /* EBU_MODCON = EBU Configuration Register*/
\r
7273 #define EBU_MODCON_STS_Pos (0U)
\r
7274 #define EBU_MODCON_STS_Msk (0x00000001U << EBU_MODCON_STS_Pos)
\r
7276 #define EBU_MODCON_LCKABRT_Pos (1U)
\r
7277 #define EBU_MODCON_LCKABRT_Msk (0x00000001U << EBU_MODCON_LCKABRT_Pos)
\r
7279 #define EBU_MODCON_SDTRI_Pos (2U)
\r
7280 #define EBU_MODCON_SDTRI_Msk (0x00000001U << EBU_MODCON_SDTRI_Pos)
\r
7282 #define EBU_MODCON_EXTLOCK_Pos (4U)
\r
7283 #define EBU_MODCON_EXTLOCK_Msk (0x00000001U << EBU_MODCON_EXTLOCK_Pos)
\r
7285 #define EBU_MODCON_ARBSYNC_Pos (5U)
\r
7286 #define EBU_MODCON_ARBSYNC_Msk (0x00000001U << EBU_MODCON_ARBSYNC_Pos)
\r
7288 #define EBU_MODCON_ARBMODE_Pos (6U)
\r
7289 #define EBU_MODCON_ARBMODE_Msk (0x00000003U << EBU_MODCON_ARBMODE_Pos)
\r
7291 #define EBU_MODCON_TIMEOUTC_Pos (8U)
\r
7292 #define EBU_MODCON_TIMEOUTC_Msk (0x000000FFU << EBU_MODCON_TIMEOUTC_Pos)
\r
7294 #define EBU_MODCON_LOCKTIMEOUT_Pos (16U)
\r
7295 #define EBU_MODCON_LOCKTIMEOUT_Msk (0x000000FFU << EBU_MODCON_LOCKTIMEOUT_Pos)
\r
7297 #define EBU_MODCON_GLOBALCS_Pos (24U)
\r
7298 #define EBU_MODCON_GLOBALCS_Msk (0x0000000FU << EBU_MODCON_GLOBALCS_Pos)
\r
7300 #define EBU_MODCON_ACCSINH_Pos (28U)
\r
7301 #define EBU_MODCON_ACCSINH_Msk (0x00000001U << EBU_MODCON_ACCSINH_Pos)
\r
7303 #define EBU_MODCON_ACCSINHACK_Pos (29U)
\r
7304 #define EBU_MODCON_ACCSINHACK_Msk (0x00000001U << EBU_MODCON_ACCSINHACK_Pos)
\r
7306 #define EBU_MODCON_ALE_Pos (31U)
\r
7307 #define EBU_MODCON_ALE_Msk (0x00000001U << EBU_MODCON_ALE_Pos)
\r
7309 /* EBU_ID = EBU Module Identification Register*/
\r
7310 #define EBU_ID_MOD_REV_Pos (0U)
\r
7311 #define EBU_ID_MOD_REV_Msk (0x000000FFU << EBU_ID_MOD_REV_Pos)
\r
7313 #define EBU_ID_MOD_TYPE_Pos (8U)
\r
7314 #define EBU_ID_MOD_TYPE_Msk (0x000000FFU << EBU_ID_MOD_TYPE_Pos)
\r
7316 #define EBU_ID_MOD_NUMBER_Pos (16U)
\r
7317 #define EBU_ID_MOD_NUMBER_Msk (0x0000FFFFU << EBU_ID_MOD_NUMBER_Pos)
\r
7319 /* EBU_USERCON = EBU Test/Control Configuration Register*/
\r
7320 #define EBU_USERCON_DIP_Pos (0U)
\r
7321 #define EBU_USERCON_DIP_Msk (0x00000001U << EBU_USERCON_DIP_Pos)
\r
7323 #define EBU_USERCON_ADDIO_Pos (16U)
\r
7324 #define EBU_USERCON_ADDIO_Msk (0x000001FFU << EBU_USERCON_ADDIO_Pos)
\r
7326 #define EBU_USERCON_ADVIO_Pos (25U)
\r
7327 #define EBU_USERCON_ADVIO_Msk (0x00000001U << EBU_USERCON_ADVIO_Pos)
\r
7329 /* EBU_CS_ADDRSELx = EBU Address Select Register 0*/
\r
7330 #define EBU_CS_ADDRSEL_REGENAB_Pos (0U)
\r
7331 #define EBU_CS_ADDRSEL_REGENAB_Msk (0x00000001U << EBU_CS_ADDRSEL_REGENAB_Pos)
\r
7333 #define EBU_CS_ADDRSEL_ALTENAB_Pos (1U)
\r
7334 #define EBU_CS_ADDRSEL_ALTENAB_Msk (0x00000001U << EBU_CS_ADDRSEL_ALTENAB_Pos)
\r
7336 #define EBU_CS_ADDRSEL_WPROT_Pos (2U)
\r
7337 #define EBU_CS_ADDRSEL_WPROT_Msk (0x00000001U << EBU_CS_ADDRSEL_WPROT_Pos)
\r
7339 /* EBU_CS_BUSRCONx = EBU Bus Configuration Register*/
\r
7340 #define EBU_CS_BUSRCON_FETBLEN_Pos (0U)
\r
7341 #define EBU_CS_BUSRCON_FETBLEN_Msk (0x00000007U << EBU_CS_BUSRCON_FETBLEN_Pos)
\r
7343 #define EBU_CS_BUSRCON_FBBMSEL_Pos (3U)
\r
7344 #define EBU_CS_BUSRCON_FBBMSEL_Msk (0x00000001U << EBU_CS_BUSRCON_FBBMSEL_Pos)
\r
7346 #define EBU_CS_BUSRCON_BFSSS_Pos (4U)
\r
7347 #define EBU_CS_BUSRCON_BFSSS_Msk (0x00000001U << EBU_CS_BUSRCON_BFSSS_Pos)
\r
7349 #define EBU_CS_BUSRCON_FDBKEN_Pos (5U)
\r
7350 #define EBU_CS_BUSRCON_FDBKEN_Msk (0x00000001U << EBU_CS_BUSRCON_FDBKEN_Pos)
\r
7352 #define EBU_CS_BUSRCON_BFCMSEL_Pos (6U)
\r
7353 #define EBU_CS_BUSRCON_BFCMSEL_Msk (0x00000001U << EBU_CS_BUSRCON_BFCMSEL_Pos)
\r
7355 #define EBU_CS_BUSRCON_NAA_Pos (7U)
\r
7356 #define EBU_CS_BUSRCON_NAA_Msk (0x00000001U << EBU_CS_BUSRCON_NAA_Pos)
\r
7358 #define EBU_CS_BUSRCON_ECSE_Pos (16U)
\r
7359 #define EBU_CS_BUSRCON_ECSE_Msk (0x00000001U << EBU_CS_BUSRCON_ECSE_Pos)
\r
7361 #define EBU_CS_BUSRCON_EBSE_Pos (17U)
\r
7362 #define EBU_CS_BUSRCON_EBSE_Msk (0x00000001U << EBU_CS_BUSRCON_EBSE_Pos)
\r
7364 #define EBU_CS_BUSRCON_DBA_Pos (18U)
\r
7365 #define EBU_CS_BUSRCON_DBA_Msk (0x00000001U << EBU_CS_BUSRCON_DBA_Pos)
\r
7367 #define EBU_CS_BUSRCON_WAITINV_Pos (19U)
\r
7368 #define EBU_CS_BUSRCON_WAITINV_Msk (0x00000001U << EBU_CS_BUSRCON_WAITINV_Pos)
\r
7370 #define EBU_CS_BUSRCON_BCGEN_Pos (20U)
\r
7371 #define EBU_CS_BUSRCON_BCGEN_Msk (0x00000003U << EBU_CS_BUSRCON_BCGEN_Pos)
\r
7373 #define EBU_CS_BUSRCON_PORTW_Pos (22U)
\r
7374 #define EBU_CS_BUSRCON_PORTW_Msk (0x00000003U << EBU_CS_BUSRCON_PORTW_Pos)
\r
7376 #define EBU_CS_BUSRCON_WAIT_Pos (24U)
\r
7377 #define EBU_CS_BUSRCON_WAIT_Msk (0x00000003U << EBU_CS_BUSRCON_WAIT_Pos)
\r
7379 #define EBU_CS_BUSRCON_AAP_Pos (26U)
\r
7380 #define EBU_CS_BUSRCON_AAP_Msk (0x00000001U << EBU_CS_BUSRCON_AAP_Pos)
\r
7382 #define EBU_CS_BUSRCON_AGEN_Pos (28U)
\r
7383 #define EBU_CS_BUSRCON_AGEN_Msk (0x0000000FU << EBU_CS_BUSRCON_AGEN_Pos)
\r
7385 /* EBU_CS_BUSRAPx = EBU Bus Read Access Parameter Register*/
\r
7386 #define EBU_CS_BUSRAP_RDDTACS_Pos (0U)
\r
7387 #define EBU_CS_BUSRAP_RDDTACS_Msk (0x0000000FU << EBU_CS_BUSRAP_RDDTACS_Pos)
\r
7389 #define EBU_CS_BUSRAP_RDRECOVC_Pos (4U)
\r
7390 #define EBU_CS_BUSRAP_RDRECOVC_Msk (0x00000007U << EBU_CS_BUSRAP_RDRECOVC_Pos)
\r
7392 #define EBU_CS_BUSRAP_WAITRDC_Pos (7U)
\r
7393 #define EBU_CS_BUSRAP_WAITRDC_Msk (0x0000001FU << EBU_CS_BUSRAP_WAITRDC_Pos)
\r
7395 #define EBU_CS_BUSRAP_DATAC_Pos (12U)
\r
7396 #define EBU_CS_BUSRAP_DATAC_Msk (0x0000000FU << EBU_CS_BUSRAP_DATAC_Pos)
\r
7398 #define EBU_CS_BUSRAP_EXTCLOCK_Pos (16U)
\r
7399 #define EBU_CS_BUSRAP_EXTCLOCK_Msk (0x00000003U << EBU_CS_BUSRAP_EXTCLOCK_Pos)
\r
7401 #define EBU_CS_BUSRAP_EXTDATA_Pos (18U)
\r
7402 #define EBU_CS_BUSRAP_EXTDATA_Msk (0x00000003U << EBU_CS_BUSRAP_EXTDATA_Pos)
\r
7404 #define EBU_CS_BUSRAP_CMDDELAY_Pos (20U)
\r
7405 #define EBU_CS_BUSRAP_CMDDELAY_Msk (0x0000000FU << EBU_CS_BUSRAP_CMDDELAY_Pos)
\r
7407 #define EBU_CS_BUSRAP_AHOLDC_Pos (24U)
\r
7408 #define EBU_CS_BUSRAP_AHOLDC_Msk (0x0000000FU << EBU_CS_BUSRAP_AHOLDC_Pos)
\r
7410 #define EBU_CS_BUSRAP_ADDRC_Pos (28U)
\r
7411 #define EBU_CS_BUSRAP_ADDRC_Msk (0x0000000FU << EBU_CS_BUSRAP_ADDRC_Pos)
\r
7413 /* EBU_CS_BUSWCONx = EBU Bus Write Configuration Register*/
\r
7414 #define EBU_CS_BUSWCON_FETBLEN_Pos (0U)
\r
7415 #define EBU_CS_BUSWCON_FETBLEN_Msk (0x00000007U << EBU_CS_BUSWCON_FETBLEN_Pos)
\r
7417 #define EBU_CS_BUSWCON_FBBMSEL_Pos (3U)
\r
7418 #define EBU_CS_BUSWCON_FBBMSEL_Msk (0x00000001U << EBU_CS_BUSWCON_FBBMSEL_Pos)
\r
7420 #define EBU_CS_BUSWCON_NAA_Pos (7U)
\r
7421 #define EBU_CS_BUSWCON_NAA_Msk (0x00000001U << EBU_CS_BUSWCON_NAA_Pos)
\r
7423 #define EBU_CS_BUSWCON_ECSE_Pos (16U)
\r
7424 #define EBU_CS_BUSWCON_ECSE_Msk (0x00000001U << EBU_CS_BUSWCON_ECSE_Pos)
\r
7426 #define EBU_CS_BUSWCON_EBSE_Pos (17U)
\r
7427 #define EBU_CS_BUSWCON_EBSE_Msk (0x00000001U << EBU_CS_BUSWCON_EBSE_Pos)
\r
7429 #define EBU_CS_BUSWCON_WAITINV_Pos (19U)
\r
7430 #define EBU_CS_BUSWCON_WAITINV_Msk (0x00000001U << EBU_CS_BUSWCON_WAITINV_Pos)
\r
7432 #define EBU_CS_BUSWCON_BCGEN_Pos (20U)
\r
7433 #define EBU_CS_BUSWCON_BCGEN_Msk (0x00000003U << EBU_CS_BUSWCON_BCGEN_Pos)
\r
7435 #define EBU_CS_BUSWCON_PORTW_Pos (22U)
\r
7436 #define EBU_CS_BUSWCON_PORTW_Msk (0x00000003U << EBU_CS_BUSWCON_PORTW_Pos)
\r
7438 #define EBU_CS_BUSWCON_WAIT_Pos (24U)
\r
7439 #define EBU_CS_BUSWCON_WAIT_Msk (0x00000003U << EBU_CS_BUSWCON_WAIT_Pos)
\r
7441 #define EBU_CS_BUSWCON_AAP_Pos (26U)
\r
7442 #define EBU_CS_BUSWCON_AAP_Msk (0x00000001U << EBU_CS_BUSWCON_AAP_Pos)
\r
7444 #define EBU_CS_BUSWCON_LOCKCS_Pos (27U)
\r
7445 #define EBU_CS_BUSWCON_LOCKCS_Msk (0x00000001U << EBU_CS_BUSWCON_LOCKCS_Pos)
\r
7447 #define EBU_CS_BUSWCON_AGEN_Pos (28U)
\r
7448 #define EBU_CS_BUSWCON_AGEN_Msk (0x0000000FU << EBU_CS_BUSWCON_AGEN_Pos)
\r
7450 /* EBU_CS_BUSWAPx = EBU Bus Write Access Parameter Register*/
\r
7451 #define EBU_CS_BUSWAP_WRDTACS_Pos (0U)
\r
7452 #define EBU_CS_BUSWAP_WRDTACS_Msk (0x0000000FU << EBU_CS_BUSWAP_WRDTACS_Pos)
\r
7454 #define EBU_CS_BUSWAP_WRRECOVC_Pos (4U)
\r
7455 #define EBU_CS_BUSWAP_WRRECOVC_Msk (0x00000007U << EBU_CS_BUSWAP_WRRECOVC_Pos)
\r
7457 #define EBU_CS_BUSWAP_WAITWRC_Pos (7U)
\r
7458 #define EBU_CS_BUSWAP_WAITWRC_Msk (0x0000001FU << EBU_CS_BUSWAP_WAITWRC_Pos)
\r
7460 #define EBU_CS_BUSWAP_DATAC_Pos (12U)
\r
7461 #define EBU_CS_BUSWAP_DATAC_Msk (0x0000000FU << EBU_CS_BUSWAP_DATAC_Pos)
\r
7463 #define EBU_CS_BUSWAP_EXTCLOCK_Pos (16U)
\r
7464 #define EBU_CS_BUSWAP_EXTCLOCK_Msk (0x00000003U << EBU_CS_BUSWAP_EXTCLOCK_Pos)
\r
7466 #define EBU_CS_BUSWAP_EXTDATA_Pos (18U)
\r
7467 #define EBU_CS_BUSWAP_EXTDATA_Msk (0x00000003U << EBU_CS_BUSWAP_EXTDATA_Pos)
\r
7469 #define EBU_CS_BUSWAP_CMDDELAY_Pos (20U)
\r
7470 #define EBU_CS_BUSWAP_CMDDELAY_Msk (0x0000000FU << EBU_CS_BUSWAP_CMDDELAY_Pos)
\r
7472 #define EBU_CS_BUSWAP_AHOLDC_Pos (24U)
\r
7473 #define EBU_CS_BUSWAP_AHOLDC_Msk (0x0000000FU << EBU_CS_BUSWAP_AHOLDC_Pos)
\r
7475 #define EBU_CS_BUSWAP_ADDRC_Pos (28U)
\r
7476 #define EBU_CS_BUSWAP_ADDRC_Msk (0x0000000FU << EBU_CS_BUSWAP_ADDRC_Pos)
\r
7478 /* EBU_SDRAM_SDRMCON = EBU SDRAM Control Register*/
\r
7479 #define EBU_SDRAM_SDRMCON_SDCMSEL_Pos (31U)
\r
7480 #define EBU_SDRAM_SDRMCON_SDCMSEL_Msk (0x00000001U << EBU_SDRAM_SDRMCON_SDCMSEL_Pos)
\r
7482 #define EBU_SDRAM_SDRMCON_PWR_MODE_Pos (29U)
\r
7483 #define EBU_SDRAM_SDRMCON_PWR_MODE_Msk (0x00000003U << EBU_SDRAM_SDRMCON_PWR_MODE_Pos)
\r
7485 #define EBU_SDRAM_SDRMCON_CLKDIS_Pos (28U)
\r
7486 #define EBU_SDRAM_SDRMCON_CLKDIS_Msk (0x00000001U << EBU_SDRAM_SDRMCON_CLKDIS_Pos)
\r
7488 #define EBU_SDRAM_SDRMCON_CRCE_Pos (25U)
\r
7489 #define EBU_SDRAM_SDRMCON_CRCE_Msk (0x00000007U << EBU_SDRAM_SDRMCON_CRCE_Pos)
\r
7491 #define EBU_SDRAM_SDRMCON_BANKM_Pos (22U)
\r
7492 #define EBU_SDRAM_SDRMCON_BANKM_Msk (0x00000007U << EBU_SDRAM_SDRMCON_BANKM_Pos)
\r
7494 #define EBU_SDRAM_SDRMCON_ROWM_Pos (19U)
\r
7495 #define EBU_SDRAM_SDRMCON_ROWM_Msk (0x00000007U << EBU_SDRAM_SDRMCON_ROWM_Pos)
\r
7497 #define EBU_SDRAM_SDRMCON_CRC_Pos (16U)
\r
7498 #define EBU_SDRAM_SDRMCON_CRC_Msk (0x00000007U << EBU_SDRAM_SDRMCON_CRC_Pos)
\r
7500 #define EBU_SDRAM_SDRMCON_CRCD_Pos (14U)
\r
7501 #define EBU_SDRAM_SDRMCON_CRCD_Msk (0x00000003U << EBU_SDRAM_SDRMCON_CRCD_Pos)
\r
7503 #define EBU_SDRAM_SDRMCON_AWIDTH_Pos (12U)
\r
7504 #define EBU_SDRAM_SDRMCON_AWIDTH_Msk (0x00000003U << EBU_SDRAM_SDRMCON_AWIDTH_Pos)
\r
7506 #define EBU_SDRAM_SDRMCON_CRP_Pos (10U)
\r
7507 #define EBU_SDRAM_SDRMCON_CRP_Msk (0x00000003U << EBU_SDRAM_SDRMCON_CRP_Pos)
\r
7509 #define EBU_SDRAM_SDRMCON_CRSC_Pos (8U)
\r
7510 #define EBU_SDRAM_SDRMCON_CRSC_Msk (0x00000003U << EBU_SDRAM_SDRMCON_CRSC_Pos)
\r
7512 #define EBU_SDRAM_SDRMCON_CRFSH_Pos (4U)
\r
7513 #define EBU_SDRAM_SDRMCON_CRFSH_Msk (0x0000000FU << EBU_SDRAM_SDRMCON_CRFSH_Pos)
\r
7515 #define EBU_SDRAM_SDRMCON_CRAS_Pos (0U)
\r
7516 #define EBU_SDRAM_SDRMCON_CRAS_Msk (0x0000000FU << EBU_SDRAM_SDRMCON_CRAS_Pos)
\r
7518 /* EBU_SDRAM_SDRMOD = EBU SDRAM Mode Register*/
\r
7519 #define EBU_SDRAM_SDRMOD_XBA_Pos (28U)
\r
7520 #define EBU_SDRAM_SDRMOD_XBA_Msk (0x0000000FU << EBU_SDRAM_SDRMOD_XBA_Pos)
\r
7522 #define EBU_SDRAM_SDRMOD_XOPM_Pos (16U)
\r
7523 #define EBU_SDRAM_SDRMOD_XOPM_Msk (0x00000FFFU << EBU_SDRAM_SDRMOD_XOPM_Pos)
\r
7525 #define EBU_SDRAM_SDRMOD_COLDSTART_Pos (15U)
\r
7526 #define EBU_SDRAM_SDRMOD_COLDSTART_Msk (0x00000001U << EBU_SDRAM_SDRMOD_COLDSTART_Pos)
\r
7528 #define EBU_SDRAM_SDRMOD_OPMODE_Pos (7U)
\r
7529 #define EBU_SDRAM_SDRMOD_OPMODE_Msk (0x0000007FU << EBU_SDRAM_SDRMOD_OPMODE_Pos)
\r
7531 #define EBU_SDRAM_SDRMOD_CASLAT_Pos (4U)
\r
7532 #define EBU_SDRAM_SDRMOD_CASLAT_Msk (0x00000007U << EBU_SDRAM_SDRMOD_CASLAT_Pos)
\r
7534 #define EBU_SDRAM_SDRMOD_BTYP_Pos (3U)
\r
7535 #define EBU_SDRAM_SDRMOD_BTYP_Msk (0x00000001U << EBU_SDRAM_SDRMOD_BTYP_Pos)
\r
7537 #define EBU_SDRAM_SDRMOD_BURSTL_Pos (0U)
\r
7538 #define EBU_SDRAM_SDRMOD_BURSTL_Msk (0x00000007U << EBU_SDRAM_SDRMOD_BURSTL_Pos)
\r
7540 /* EBU_SDRAM_SDRMREF = EBU SDRAM Refresh Control Register*/
\r
7541 #define EBU_SDRAM_SDRMREF_RES_DLY_Pos (25U)
\r
7542 #define EBU_SDRAM_SDRMREF_RES_DLY_Msk (0x00000007U << EBU_SDRAM_SDRMREF_RES_DLY_Pos)
\r
7544 #define EBU_SDRAM_SDRMREF_ARFSH_Pos (24U)
\r
7545 #define EBU_SDRAM_SDRMREF_ARFSH_Msk (0x00000001U << EBU_SDRAM_SDRMREF_ARFSH_Pos)
\r
7547 #define EBU_SDRAM_SDRMREF_SELFREX_DLY_Pos (16U)
\r
7548 #define EBU_SDRAM_SDRMREF_SELFREX_DLY_Msk (0x000000FFU << EBU_SDRAM_SDRMREF_SELFREX_DLY_Pos)
\r
7550 #define EBU_SDRAM_SDRMREF_ERFSHC_Pos (14U)
\r
7551 #define EBU_SDRAM_SDRMREF_ERFSHC_Msk (0x00000003U << EBU_SDRAM_SDRMREF_ERFSHC_Pos)
\r
7553 #define EBU_SDRAM_SDRMREF_AUTOSELFR_Pos (13U)
\r
7554 #define EBU_SDRAM_SDRMREF_AUTOSELFR_Msk (0x00000001U << EBU_SDRAM_SDRMREF_AUTOSELFR_Pos)
\r
7556 #define EBU_SDRAM_SDRMREF_SELFREN_Pos (12U)
\r
7557 #define EBU_SDRAM_SDRMREF_SELFREN_Msk (0x00000001U << EBU_SDRAM_SDRMREF_SELFREN_Pos)
\r
7559 #define EBU_SDRAM_SDRMREF_SELFRENST_Pos (11U)
\r
7560 #define EBU_SDRAM_SDRMREF_SELFRENST_Msk (0x00000001U << EBU_SDRAM_SDRMREF_SELFRENST_Pos)
\r
7562 #define EBU_SDRAM_SDRMREF_SELFREX_Pos (10U)
\r
7563 #define EBU_SDRAM_SDRMREF_SELFREX_Msk (0x00000001U << EBU_SDRAM_SDRMREF_SELFREX_Pos)
\r
7565 #define EBU_SDRAM_SDRMREF_SELFREXST_Pos (9U)
\r
7566 #define EBU_SDRAM_SDRMREF_SELFREXST_Msk (0x00000001U << EBU_SDRAM_SDRMREF_SELFREXST_Pos)
\r
7568 #define EBU_SDRAM_SDRMREF_REFRESHR_Pos (6U)
\r
7569 #define EBU_SDRAM_SDRMREF_REFRESHR_Msk (0x00000007U << EBU_SDRAM_SDRMREF_REFRESHR_Pos)
\r
7571 #define EBU_SDRAM_SDRMREF_REFRESHC_Pos (0U)
\r
7572 #define EBU_SDRAM_SDRMREF_REFRESHC_Msk (0x0000003FU << EBU_SDRAM_SDRMREF_REFRESHC_Pos)
\r
7574 /* EBU_SDRAM_SDRSTAT = EBU SDRAM Status Register*/
\r
7575 #define EBU_SDRAM_SDRSTAT_SDERR_Pos (2U)
\r
7576 #define EBU_SDRAM_SDRSTAT_SDERR_Msk (0x00000001U << EBU_SDRAM_SDRSTAT_SDERR_Pos)
\r
7578 #define EBU_SDRAM_SDRSTAT_SDRMBUSY_Pos (1U)
\r
7579 #define EBU_SDRAM_SDRSTAT_SDRMBUSY_Msk (0x00000001U << EBU_SDRAM_SDRSTAT_SDRMBUSY_Pos)
\r
7581 #define EBU_SDRAM_SDRSTAT_REFERR_Pos (0U)
\r
7582 #define EBU_SDRAM_SDRSTAT_REFERR_Msk (0x00000001U << EBU_SDRAM_SDRSTAT_REFERR_Pos)
\r
7586 /*** ERUx Bit Fileds *******************/
\r
7587 /***************************************************************************/
\r
7590 /* ERU_EXISEL = Event Input Select Register 0*/
\r
7591 #define ERU_EXISEL_EXS0A_Pos (0U)
\r
7592 #define ERU_EXISEL_EXS0A_Msk (0x00000003U << ERU_EXISEL_EXS0A_Pos)
\r
7594 #define ERU_EXISEL_EXS0B_Pos (2U)
\r
7595 #define ERU_EXISEL_EXS0B_Msk (0x00000003U << ERU_EXISEL_EXS0B_Pos)
\r
7597 #define ERU_EXISEL_EXS1A_Pos (4U)
\r
7598 #define ERU_EXISEL_EXS1A_Msk (0x00000003U << ERU_EXISEL_EXS1A_Pos)
\r
7600 #define ERU_EXISEL_EXS1B_Pos (6U)
\r
7601 #define ERU_EXISEL_EXS1B_Msk (0x00000003U << ERU_EXISEL_EXS1B_Pos)
\r
7603 #define ERU_EXISEL_EXS2A_Pos (8U)
\r
7604 #define ERU_EXISEL_EXS2A_Msk (0x00000003U << ERU_EXISEL_EXS2A_Pos)
\r
7606 #define ERU_EXISEL_EXS2B_Pos (10U)
\r
7607 #define ERU_EXISEL_EXS2B_Msk (0x00000003U << ERU_EXISEL_EXS2B_Pos)
\r
7609 #define ERU_EXISEL_EXS3A_Pos (12U)
\r
7610 #define ERU_EXISEL_EXS3A_Msk (0x00000003U << ERU_EXISEL_EXS3A_Pos)
\r
7612 #define ERU_EXISEL_EXS3B_Pos (14U)
\r
7613 #define ERU_EXISEL_EXS3B_Msk (0x00000003U << ERU_EXISEL_EXS3B_Pos)
\r
7615 /* ERU_EXICON0 = Event Input Control x Register*/
\r
7616 #define ERU_EXICON_PE_Pos (0U)
\r
7617 #define ERU_EXICON_PE_Msk (0x00000001U << ERU_EXICON_PE_Pos)
\r
7619 #define ERU_EXICON_LD_Pos (1U)
\r
7620 #define ERU_EXICON_LD_Msk (0x00000001U << ERU_EXICON_LD_Pos)
\r
7622 #define ERU_EXICON_RE_Pos (2U)
\r
7623 #define ERU_EXICON_RE_Msk (0x00000001U << ERU_EXICON_RE_Pos)
\r
7625 #define ERU_EXICON_FE_Pos (3U)
\r
7626 #define ERU_EXICON_FE_Msk (0x00000001U << ERU_EXICON_FE_Pos)
\r
7628 #define ERU_EXICON_OCS_Pos (4U)
\r
7629 #define ERU_EXICON_OCS_Msk (0x00000007U << ERU_EXICON_OCS_Pos)
\r
7631 #define ERU_EXICON_FL_Pos (7U)
\r
7632 #define ERU_EXICON_FL_Msk (0x00000001U << ERU_EXICON_FL_Pos)
\r
7634 #define ERU_EXICON_SS_Pos (8U)
\r
7635 #define ERU_EXICON_SS_Msk (0x00000003U << ERU_EXICON_SS_Pos)
\r
7637 #define ERU_EXICON_NA_Pos (10U)
\r
7638 #define ERU_EXICON_NA_Msk (0x00000001U << ERU_EXICON_NA_Pos)
\r
7640 #define ERU_EXICON_NB_Pos (11U)
\r
7641 #define ERU_EXICON_NB_Msk (0x00000001U << ERU_EXICON_NB_Pos)
\r
7644 /* ERU_EXOCON0 = Event Output Trigger Control x Register*/
\r
7645 #define ERU_EXOCON_ISS_Pos (0U)
\r
7646 #define ERU_EXOCON_ISS_Msk (0x00000003U << ERU_EXOCON_ISS_Pos)
\r
7648 #define ERU_EXOCON_GEEN_Pos (2U)
\r
7649 #define ERU_EXOCON_GEEN_Msk (0x00000001U << ERU_EXOCON_GEEN_Pos)
\r
7651 #define ERU_EXOCON_PDR_Pos (3U)
\r
7652 #define ERU_EXOCON_PDR_Msk (0x00000001U << ERU_EXOCON_PDR_Pos)
\r
7654 #define ERU_EXOCON_GP_Pos (4U)
\r
7655 #define ERU_EXOCON_GP_Msk (0x00000003U << ERU_EXOCON_GP_Pos)
\r
7657 #define ERU_EXOCON_IPEN0_Pos (12U)
\r
7658 #define ERU_EXOCON_IPEN0_Msk (0x00000001U << ERU_EXOCON_IPEN0_Pos)
\r
7660 #define ERU_EXOCON_IPEN1_Pos (13U)
\r
7661 #define ERU_EXOCON_IPEN1_Msk (0x00000001U << ERU_EXOCON_IPEN1_Pos)
\r
7663 #define ERU_EXOCON_IPEN2_Pos (14U)
\r
7664 #define ERU_EXOCON_IPEN2_Msk (0x00000001U << ERU_EXOCON_IPEN2_Pos)
\r
7666 #define ERU_EXOCON_IPEN3_Pos (15U)
\r
7667 #define ERU_EXOCON_IPEN3_Msk (0x00000001U << ERU_EXOCON_IPEN3_Pos)
\r
7670 /*** ETHx Bit Fileds *******************/
\r
7671 /***************************************************************************/
\r
7674 /* ETH_MAC_CONFIGURATION = Register x [MAC Configuration Register]*/
\r
7675 #define ETH_MAC_CONFIGURATION_PRELEN_Pos (0U)
\r
7676 #define ETH_MAC_CONFIGURATION_PRELEN_Msk (0x00000003U << ETH_MAC_CONFIGURATION_PRELEN_Pos)
\r
7678 #define ETH_MAC_CONFIGURATION_RE_Pos (2U)
\r
7679 #define ETH_MAC_CONFIGURATION_RE_Msk (0x00000001U << ETH_MAC_CONFIGURATION_RE_Pos)
\r
7681 #define ETH_MAC_CONFIGURATION_TE_Pos (3U)
\r
7682 #define ETH_MAC_CONFIGURATION_TE_Msk (0x00000001U << ETH_MAC_CONFIGURATION_TE_Pos)
\r
7684 #define ETH_MAC_CONFIGURATION_DC_Pos (4U)
\r
7685 #define ETH_MAC_CONFIGURATION_DC_Msk (0x00000001U << ETH_MAC_CONFIGURATION_DC_Pos)
\r
7687 #define ETH_MAC_CONFIGURATION_BL_Pos (5U)
\r
7688 #define ETH_MAC_CONFIGURATION_BL_Msk (0x00000003U << ETH_MAC_CONFIGURATION_BL_Pos)
\r
7690 #define ETH_MAC_CONFIGURATION_ACS_Pos (7U)
\r
7691 #define ETH_MAC_CONFIGURATION_ACS_Msk (0x00000001U << ETH_MAC_CONFIGURATION_ACS_Pos)
\r
7693 #define ETH_MAC_CONFIGURATION_LUD_Pos (8U)
\r
7694 #define ETH_MAC_CONFIGURATION_LUD_Msk (0x00000001U << ETH_MAC_CONFIGURATION_LUD_Pos)
\r
7696 #define ETH_MAC_CONFIGURATION_DR_Pos (9U)
\r
7697 #define ETH_MAC_CONFIGURATION_DR_Msk (0x00000001U << ETH_MAC_CONFIGURATION_DR_Pos)
\r
7699 #define ETH_MAC_CONFIGURATION_IPC_Pos (10U)
\r
7700 #define ETH_MAC_CONFIGURATION_IPC_Msk (0x00000001U << ETH_MAC_CONFIGURATION_IPC_Pos)
\r
7702 #define ETH_MAC_CONFIGURATION_DM_Pos (11U)
\r
7703 #define ETH_MAC_CONFIGURATION_DM_Msk (0x00000001U << ETH_MAC_CONFIGURATION_DM_Pos)
\r
7705 #define ETH_MAC_CONFIGURATION_LM_Pos (12U)
\r
7706 #define ETH_MAC_CONFIGURATION_LM_Msk (0x00000001U << ETH_MAC_CONFIGURATION_LM_Pos)
\r
7708 #define ETH_MAC_CONFIGURATION_DO_Pos (13U)
\r
7709 #define ETH_MAC_CONFIGURATION_DO_Msk (0x00000001U << ETH_MAC_CONFIGURATION_DO_Pos)
\r
7711 #define ETH_MAC_CONFIGURATION_FES_Pos (14U)
\r
7712 #define ETH_MAC_CONFIGURATION_FES_Msk (0x00000001U << ETH_MAC_CONFIGURATION_FES_Pos)
\r
7714 #define ETH_MAC_CONFIGURATION_Reserved_Pos (15U)
\r
7715 #define ETH_MAC_CONFIGURATION_Reserved_Msk (0x00000001U << ETH_MAC_CONFIGURATION_Reserved_Pos)
\r
7717 #define ETH_MAC_CONFIGURATION_DCRS_Pos (16U)
\r
7718 #define ETH_MAC_CONFIGURATION_DCRS_Msk (0x00000001U << ETH_MAC_CONFIGURATION_DCRS_Pos)
\r
7720 #define ETH_MAC_CONFIGURATION_IFG_Pos (17U)
\r
7721 #define ETH_MAC_CONFIGURATION_IFG_Msk (0x00000007U << ETH_MAC_CONFIGURATION_IFG_Pos)
\r
7723 #define ETH_MAC_CONFIGURATION_JE_Pos (20U)
\r
7724 #define ETH_MAC_CONFIGURATION_JE_Msk (0x00000001U << ETH_MAC_CONFIGURATION_JE_Pos)
\r
7726 #define ETH_MAC_CONFIGURATION_BE_Pos (21U)
\r
7727 #define ETH_MAC_CONFIGURATION_BE_Msk (0x00000001U << ETH_MAC_CONFIGURATION_BE_Pos)
\r
7729 #define ETH_MAC_CONFIGURATION_JD_Pos (22U)
\r
7730 #define ETH_MAC_CONFIGURATION_JD_Msk (0x00000001U << ETH_MAC_CONFIGURATION_JD_Pos)
\r
7732 #define ETH_MAC_CONFIGURATION_WD_Pos (23U)
\r
7733 #define ETH_MAC_CONFIGURATION_WD_Msk (0x00000001U << ETH_MAC_CONFIGURATION_WD_Pos)
\r
7735 #define ETH_MAC_CONFIGURATION_TC_Pos (24U)
\r
7736 #define ETH_MAC_CONFIGURATION_TC_Msk (0x00000001U << ETH_MAC_CONFIGURATION_TC_Pos)
\r
7738 #define ETH_MAC_CONFIGURATION_CST_Pos (25U)
\r
7739 #define ETH_MAC_CONFIGURATION_CST_Msk (0x00000001U << ETH_MAC_CONFIGURATION_CST_Pos)
\r
7741 #define ETH_MAC_CONFIGURATION_Reserved_26_Pos (26U)
\r
7742 #define ETH_MAC_CONFIGURATION_Reserved_26_Msk (0x00000001U << ETH_MAC_CONFIGURATION_Reserved_26_Pos)
\r
7744 #define ETH_MAC_CONFIGURATION_TWOKPE_Pos (27U)
\r
7745 #define ETH_MAC_CONFIGURATION_TWOKPE_Msk (0x00000001U << ETH_MAC_CONFIGURATION_TWOKPE_Pos)
\r
7747 #define ETH_MAC_CONFIGURATION_SARC_Pos (28U)
\r
7748 #define ETH_MAC_CONFIGURATION_SARC_Msk (0x00000007U << ETH_MAC_CONFIGURATION_SARC_Pos)
\r
7750 #define ETH_MAC_CONFIGURATION_Reserved_31_Pos (31U)
\r
7751 #define ETH_MAC_CONFIGURATION_Reserved_31_Msk (0x00000001U << ETH_MAC_CONFIGURATION_Reserved_31_Pos)
\r
7753 /* ETH_MAC_FRAME_FILTER = Register 1 [MAC Frame Filter]*/
\r
7754 #define ETH_MAC_FRAME_FILTER_PR_Pos (0U)
\r
7755 #define ETH_MAC_FRAME_FILTER_PR_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_PR_Pos)
\r
7757 #define ETH_MAC_FRAME_FILTER_HUC_Pos (1U)
\r
7758 #define ETH_MAC_FRAME_FILTER_HUC_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_HUC_Pos)
\r
7760 #define ETH_MAC_FRAME_FILTER_HMC_Pos (2U)
\r
7761 #define ETH_MAC_FRAME_FILTER_HMC_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_HMC_Pos)
\r
7763 #define ETH_MAC_FRAME_FILTER_DAIF_Pos (3U)
\r
7764 #define ETH_MAC_FRAME_FILTER_DAIF_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_DAIF_Pos)
\r
7766 #define ETH_MAC_FRAME_FILTER_PM_Pos (4U)
\r
7767 #define ETH_MAC_FRAME_FILTER_PM_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_PM_Pos)
\r
7769 #define ETH_MAC_FRAME_FILTER_DBF_Pos (5U)
\r
7770 #define ETH_MAC_FRAME_FILTER_DBF_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_DBF_Pos)
\r
7772 #define ETH_MAC_FRAME_FILTER_PCF_Pos (6U)
\r
7773 #define ETH_MAC_FRAME_FILTER_PCF_Msk (0x00000003U << ETH_MAC_FRAME_FILTER_PCF_Pos)
\r
7775 #define ETH_MAC_FRAME_FILTER_SAIF_Pos (8U)
\r
7776 #define ETH_MAC_FRAME_FILTER_SAIF_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_SAIF_Pos)
\r
7778 #define ETH_MAC_FRAME_FILTER_SAF_Pos (9U)
\r
7779 #define ETH_MAC_FRAME_FILTER_SAF_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_SAF_Pos)
\r
7781 #define ETH_MAC_FRAME_FILTER_HPF_Pos (10U)
\r
7782 #define ETH_MAC_FRAME_FILTER_HPF_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_HPF_Pos)
\r
7784 #define ETH_MAC_FRAME_FILTER_Reserved_15_11_Pos (11U)
\r
7785 #define ETH_MAC_FRAME_FILTER_Reserved_15_11_Msk (0x0000001FU << ETH_MAC_FRAME_FILTER_Reserved_15_11_Pos)
\r
7787 #define ETH_MAC_FRAME_FILTER_VTFE_Pos (16U)
\r
7788 #define ETH_MAC_FRAME_FILTER_VTFE_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_VTFE_Pos)
\r
7790 #define ETH_MAC_FRAME_FILTER_Reserved_19_17_Pos (17U)
\r
7791 #define ETH_MAC_FRAME_FILTER_Reserved_19_17_Msk (0x00000007U << ETH_MAC_FRAME_FILTER_Reserved_19_17_Pos)
\r
7793 #define ETH_MAC_FRAME_FILTER_IPFE_Pos (20U)
\r
7794 #define ETH_MAC_FRAME_FILTER_IPFE_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_IPFE_Pos)
\r
7796 #define ETH_MAC_FRAME_FILTER_DNTU_Pos (21U)
\r
7797 #define ETH_MAC_FRAME_FILTER_DNTU_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_DNTU_Pos)
\r
7799 #define ETH_MAC_FRAME_FILTER_Reserved_30_22_Pos (22U)
\r
7800 #define ETH_MAC_FRAME_FILTER_Reserved_30_22_Msk (0x000001FFU << ETH_MAC_FRAME_FILTER_Reserved_30_22_Pos)
\r
7802 #define ETH_MAC_FRAME_FILTER_RA_Pos (31U)
\r
7803 #define ETH_MAC_FRAME_FILTER_RA_Msk (0x00000001U << ETH_MAC_FRAME_FILTER_RA_Pos)
\r
7805 /* ETH_HASH_TABLE_HIGH = Register 2 [Hash Table High Register]*/
\r
7806 #define ETH_HASH_TABLE_HIGH_HTH_Pos (0U)
\r
7807 #define ETH_HASH_TABLE_HIGH_HTH_Msk (0xFFFFFFFFU << ETH_HASH_TABLE_HIGH_HTH_Pos)
\r
7809 /* ETH_HASH_TABLE_LOW = Register 3 [Hash Table Low Register]*/
\r
7810 #define ETH_HASH_TABLE_LOW_HTL_Pos (0U)
\r
7811 #define ETH_HASH_TABLE_LOW_HTL_Msk (0xFFFFFFFFU << ETH_HASH_TABLE_LOW_HTL_Pos)
\r
7813 /* ETH_GMII_ADDRESS = Register 4 [MII Address Register)*/
\r
7814 #define ETH_GMII_ADDRESS_MB_Pos (0U)
\r
7815 #define ETH_GMII_ADDRESS_MB_Msk (0x00000001U << ETH_GMII_ADDRESS_MB_Pos)
\r
7817 #define ETH_GMII_ADDRESS_MW_Pos (1U)
\r
7818 #define ETH_GMII_ADDRESS_MW_Msk (0x00000001U << ETH_GMII_ADDRESS_MW_Pos)
\r
7820 #define ETH_GMII_ADDRESS_CR_Pos (2U)
\r
7821 #define ETH_GMII_ADDRESS_CR_Msk (0x0000000FU << ETH_GMII_ADDRESS_CR_Pos)
\r
7823 #define ETH_GMII_ADDRESS_MR_Pos (6U)
\r
7824 #define ETH_GMII_ADDRESS_MR_Msk (0x0000001FU << ETH_GMII_ADDRESS_MR_Pos)
\r
7826 #define ETH_GMII_ADDRESS_PA_Pos (11U)
\r
7827 #define ETH_GMII_ADDRESS_PA_Msk (0x0000001FU << ETH_GMII_ADDRESS_PA_Pos)
\r
7829 #define ETH_GMII_ADDRESS_Reserved_31_16_Pos (16U)
\r
7830 #define ETH_GMII_ADDRESS_Reserved_31_16_Msk (0x0000FFFFU << ETH_GMII_ADDRESS_Reserved_31_16_Pos)
\r
7832 /* ETH_GMII_DATA = Register 5 [MII Data Register]*/
\r
7833 #define ETH_GMII_DATA_MD_Pos (0U)
\r
7834 #define ETH_GMII_DATA_MD_Msk (0x0000FFFFU << ETH_GMII_DATA_MD_Pos)
\r
7836 #define ETH_GMII_DATA_Reserved_31_16_Pos (16U)
\r
7837 #define ETH_GMII_DATA_Reserved_31_16_Msk (0x0000FFFFU << ETH_GMII_DATA_Reserved_31_16_Pos)
\r
7839 /* ETH_FLOW_CONTROL = Register 6 [Flow Control Register]*/
\r
7840 #define ETH_FLOW_CONTROL_FCA_BPA_Pos (0U)
\r
7841 #define ETH_FLOW_CONTROL_FCA_BPA_Msk (0x00000001U << ETH_FLOW_CONTROL_FCA_BPA_Pos)
\r
7843 #define ETH_FLOW_CONTROL_TFE_Pos (1U)
\r
7844 #define ETH_FLOW_CONTROL_TFE_Msk (0x00000001U << ETH_FLOW_CONTROL_TFE_Pos)
\r
7846 #define ETH_FLOW_CONTROL_RFE_Pos (2U)
\r
7847 #define ETH_FLOW_CONTROL_RFE_Msk (0x00000001U << ETH_FLOW_CONTROL_RFE_Pos)
\r
7849 #define ETH_FLOW_CONTROL_UP_Pos (3U)
\r
7850 #define ETH_FLOW_CONTROL_UP_Msk (0x00000001U << ETH_FLOW_CONTROL_UP_Pos)
\r
7852 #define ETH_FLOW_CONTROL_PLT_Pos (4U)
\r
7853 #define ETH_FLOW_CONTROL_PLT_Msk (0x00000003U << ETH_FLOW_CONTROL_PLT_Pos)
\r
7855 #define ETH_FLOW_CONTROL_Reserved_6_Pos (6U)
\r
7856 #define ETH_FLOW_CONTROL_Reserved_6_Msk (0x00000001U << ETH_FLOW_CONTROL_Reserved_6_Pos)
\r
7858 #define ETH_FLOW_CONTROL_DZPQ_Pos (7U)
\r
7859 #define ETH_FLOW_CONTROL_DZPQ_Msk (0x00000001U << ETH_FLOW_CONTROL_DZPQ_Pos)
\r
7861 #define ETH_FLOW_CONTROL_Reserved_15_8_Pos (8U)
\r
7862 #define ETH_FLOW_CONTROL_Reserved_15_8_Msk (0x000000FFU << ETH_FLOW_CONTROL_Reserved_15_8_Pos)
\r
7864 #define ETH_FLOW_CONTROL_PT_Pos (16U)
\r
7865 #define ETH_FLOW_CONTROL_PT_Msk (0x0000FFFFU << ETH_FLOW_CONTROL_PT_Pos)
\r
7867 /* ETH_VLAN_TAG = Register 7 [VLAN Tag Register]*/
\r
7868 #define ETH_VLAN_TAG_VL_Pos (0U)
\r
7869 #define ETH_VLAN_TAG_VL_Msk (0x0000FFFFU << ETH_VLAN_TAG_VL_Pos)
\r
7871 #define ETH_VLAN_TAG_ETV_Pos (16U)
\r
7872 #define ETH_VLAN_TAG_ETV_Msk (0x00000001U << ETH_VLAN_TAG_ETV_Pos)
\r
7874 #define ETH_VLAN_TAG_VTIM_Pos (17U)
\r
7875 #define ETH_VLAN_TAG_VTIM_Msk (0x00000001U << ETH_VLAN_TAG_VTIM_Pos)
\r
7877 #define ETH_VLAN_TAG_ESVL_Pos (18U)
\r
7878 #define ETH_VLAN_TAG_ESVL_Msk (0x00000001U << ETH_VLAN_TAG_ESVL_Pos)
\r
7880 #define ETH_VLAN_TAG_VTHM_Pos (19U)
\r
7881 #define ETH_VLAN_TAG_VTHM_Msk (0x00000001U << ETH_VLAN_TAG_VTHM_Pos)
\r
7883 #define ETH_VLAN_TAG_Reserved_31_20_Pos (20U)
\r
7884 #define ETH_VLAN_TAG_Reserved_31_20_Msk (0x00000FFFU << ETH_VLAN_TAG_Reserved_31_20_Pos)
\r
7886 /* ETH_VERSION = Register 8 [Version Register]*/
\r
7887 #define ETH_VERSION_SNPSVER_Pos (0U)
\r
7888 #define ETH_VERSION_SNPSVER_Msk (0x000000FFU << ETH_VERSION_SNPSVER_Pos)
\r
7890 #define ETH_VERSION_USERVER_Pos (8U)
\r
7891 #define ETH_VERSION_USERVER_Msk (0x000000FFU << ETH_VERSION_USERVER_Pos)
\r
7893 #define ETH_VERSION_Reserved_31_16_Pos (16U)
\r
7894 #define ETH_VERSION_Reserved_31_16_Msk (0x0000FFFFU << ETH_VERSION_Reserved_31_16_Pos)
\r
7896 /* ETH_DEBUG = Register 9 [Debug Register]*/
\r
7897 #define ETH_DEBUG_RPESTS_Pos (0U)
\r
7898 #define ETH_DEBUG_RPESTS_Msk (0x00000001U << ETH_DEBUG_RPESTS_Pos)
\r
7900 #define ETH_DEBUG_RFCFCSTS_Pos (1U)
\r
7901 #define ETH_DEBUG_RFCFCSTS_Msk (0x00000003U << ETH_DEBUG_RFCFCSTS_Pos)
\r
7903 #define ETH_DEBUG_Reserved_3_Pos (3U)
\r
7904 #define ETH_DEBUG_Reserved_3_Msk (0x00000001U << ETH_DEBUG_Reserved_3_Pos)
\r
7906 #define ETH_DEBUG_RWCSTS_Pos (4U)
\r
7907 #define ETH_DEBUG_RWCSTS_Msk (0x00000001U << ETH_DEBUG_RWCSTS_Pos)
\r
7909 #define ETH_DEBUG_RRCSTS_Pos (5U)
\r
7910 #define ETH_DEBUG_RRCSTS_Msk (0x00000003U << ETH_DEBUG_RRCSTS_Pos)
\r
7912 #define ETH_DEBUG_Reserved_7_Pos (7U)
\r
7913 #define ETH_DEBUG_Reserved_7_Msk (0x00000001U << ETH_DEBUG_Reserved_7_Pos)
\r
7915 #define ETH_DEBUG_RXFSTS_Pos (8U)
\r
7916 #define ETH_DEBUG_RXFSTS_Msk (0x00000003U << ETH_DEBUG_RXFSTS_Pos)
\r
7918 #define ETH_DEBUG_Reserved_15_10_Pos (10U)
\r
7919 #define ETH_DEBUG_Reserved_15_10_Msk (0x0000003FU << ETH_DEBUG_Reserved_15_10_Pos)
\r
7921 #define ETH_DEBUG_TPESTS_Pos (16U)
\r
7922 #define ETH_DEBUG_TPESTS_Msk (0x00000001U << ETH_DEBUG_TPESTS_Pos)
\r
7924 #define ETH_DEBUG_TFCSTS_Pos (17U)
\r
7925 #define ETH_DEBUG_TFCSTS_Msk (0x00000003U << ETH_DEBUG_TFCSTS_Pos)
\r
7927 #define ETH_DEBUG_TXPAUSED_Pos (19U)
\r
7928 #define ETH_DEBUG_TXPAUSED_Msk (0x00000001U << ETH_DEBUG_TXPAUSED_Pos)
\r
7930 #define ETH_DEBUG_TRCSTS_Pos (20U)
\r
7931 #define ETH_DEBUG_TRCSTS_Msk (0x00000003U << ETH_DEBUG_TRCSTS_Pos)
\r
7933 #define ETH_DEBUG_TWCSTS_Pos (22U)
\r
7934 #define ETH_DEBUG_TWCSTS_Msk (0x00000001U << ETH_DEBUG_TWCSTS_Pos)
\r
7936 #define ETH_DEBUG_Reserved_23_Pos (23U)
\r
7937 #define ETH_DEBUG_Reserved_23_Msk (0x00000001U << ETH_DEBUG_Reserved_23_Pos)
\r
7939 #define ETH_DEBUG_TXFSTS_Pos (24U)
\r
7940 #define ETH_DEBUG_TXFSTS_Msk (0x00000001U << ETH_DEBUG_TXFSTS_Pos)
\r
7942 #define ETH_DEBUG_TXSTSFSTS_Pos (25U)
\r
7943 #define ETH_DEBUG_TXSTSFSTS_Msk (0x00000001U << ETH_DEBUG_TXSTSFSTS_Pos)
\r
7945 #define ETH_DEBUG_Reserved_31_26_Pos (26U)
\r
7946 #define ETH_DEBUG_Reserved_31_26_Msk (0x0000003FU << ETH_DEBUG_Reserved_31_26_Pos)
\r
7948 /* ETH_REMOTE_WAKE_UP_FRAME_FILTER = */
\r
7949 #define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos (0U)
\r
7950 #define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Msk (0xFFFFFFFFU << ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos)
\r
7952 /* ETH_PMT_CONTROL_STATUS = Register 11 [PMT Control and Status Register]*/
\r
7953 #define ETH_PMT_CONTROL_STATUS_PWRDWN_Pos (0U)
\r
7954 #define ETH_PMT_CONTROL_STATUS_PWRDWN_Msk (0x00000001U << ETH_PMT_CONTROL_STATUS_PWRDWN_Pos)
\r
7956 #define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos (1U)
\r
7957 #define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Msk (0x00000001U << ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos)
\r
7959 #define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos (2U)
\r
7960 #define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Msk (0x00000001U << ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos)
\r
7962 #define ETH_PMT_CONTROL_STATUS_Reserved_4_3_Pos (3U)
\r
7963 #define ETH_PMT_CONTROL_STATUS_Reserved_4_3_Msk (0x00000003U << ETH_PMT_CONTROL_STATUS_Reserved_4_3_Pos)
\r
7965 #define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos (5U)
\r
7966 #define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Msk (0x00000001U << ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos)
\r
7968 #define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos (6U)
\r
7969 #define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Msk (0x00000001U << ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos)
\r
7971 #define ETH_PMT_CONTROL_STATUS_Reserved_8_7_Pos (7U)
\r
7972 #define ETH_PMT_CONTROL_STATUS_Reserved_8_7_Msk (0x00000003U << ETH_PMT_CONTROL_STATUS_Reserved_8_7_Pos)
\r
7974 #define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos (9U)
\r
7975 #define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Msk (0x00000001U << ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos)
\r
7977 #define ETH_PMT_CONTROL_STATUS_Reserved_30_10_Pos (10U)
\r
7978 #define ETH_PMT_CONTROL_STATUS_Reserved_30_10_Msk (0x001FFFFFU << ETH_PMT_CONTROL_STATUS_Reserved_30_10_Pos)
\r
7980 #define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos (31U)
\r
7981 #define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Msk (0x00000001U << ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos)
\r
7983 /* ETH_INTERRUPT_STATUS = Register 14 [Interrupt Register]*/
\r
7984 #define ETH_INTERRUPT_STATUS_RMIIIS_Pos (0U)
\r
7985 #define ETH_INTERRUPT_STATUS_RMIIIS_Msk (0x00000001U << ETH_INTERRUPT_STATUS_RMIIIS_Pos)
\r
7987 #define ETH_INTERRUPT_STATUS_Reserved_1_Pos (1U)
\r
7988 #define ETH_INTERRUPT_STATUS_Reserved_1_Msk (0x00000001U << ETH_INTERRUPT_STATUS_Reserved_1_Pos)
\r
7990 #define ETH_INTERRUPT_STATUS_Reserved_2_Pos (2U)
\r
7991 #define ETH_INTERRUPT_STATUS_Reserved_2_Msk (0x00000001U << ETH_INTERRUPT_STATUS_Reserved_2_Pos)
\r
7993 #define ETH_INTERRUPT_STATUS_PMTIS_Pos (3U)
\r
7994 #define ETH_INTERRUPT_STATUS_PMTIS_Msk (0x00000001U << ETH_INTERRUPT_STATUS_PMTIS_Pos)
\r
7996 #define ETH_INTERRUPT_STATUS_MMCIS_Pos (4U)
\r
7997 #define ETH_INTERRUPT_STATUS_MMCIS_Msk (0x00000001U << ETH_INTERRUPT_STATUS_MMCIS_Pos)
\r
7999 #define ETH_INTERRUPT_STATUS_MMCRXIS_Pos (5U)
\r
8000 #define ETH_INTERRUPT_STATUS_MMCRXIS_Msk (0x00000001U << ETH_INTERRUPT_STATUS_MMCRXIS_Pos)
\r
8002 #define ETH_INTERRUPT_STATUS_MMCTXIS_Pos (6U)
\r
8003 #define ETH_INTERRUPT_STATUS_MMCTXIS_Msk (0x00000001U << ETH_INTERRUPT_STATUS_MMCTXIS_Pos)
\r
8005 #define ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos (7U)
\r
8006 #define ETH_INTERRUPT_STATUS_MMCRXIPIS_Msk (0x00000001U << ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos)
\r
8008 #define ETH_INTERRUPT_STATUS_Reserved_8_Pos (8U)
\r
8009 #define ETH_INTERRUPT_STATUS_Reserved_8_Msk (0x00000001U << ETH_INTERRUPT_STATUS_Reserved_8_Pos)
\r
8011 #define ETH_INTERRUPT_STATUS_TSIS_Pos (9U)
\r
8012 #define ETH_INTERRUPT_STATUS_TSIS_Msk (0x00000001U << ETH_INTERRUPT_STATUS_TSIS_Pos)
\r
8014 #define ETH_INTERRUPT_STATUS_LPIIS_Pos (10U)
\r
8015 #define ETH_INTERRUPT_STATUS_LPIIS_Msk (0x00000001U << ETH_INTERRUPT_STATUS_LPIIS_Pos)
\r
8017 #define ETH_INTERRUPT_STATUS_Reserved_31_11_Pos (11U)
\r
8018 #define ETH_INTERRUPT_STATUS_Reserved_31_11_Msk (0x001FFFFFU << ETH_INTERRUPT_STATUS_Reserved_31_11_Pos)
\r
8020 /* ETH_INTERRUPT_MASK = Register 15 [Interrupt Mask Register]*/
\r
8021 #define ETH_INTERRUPT_MASK_RMIIIM_Pos (0U)
\r
8022 #define ETH_INTERRUPT_MASK_RMIIIM_Msk (0x00000001U << ETH_INTERRUPT_MASK_RMIIIM_Pos)
\r
8024 #define ETH_INTERRUPT_MASK_Reserved_1_Pos (1U)
\r
8025 #define ETH_INTERRUPT_MASK_Reserved_1_Msk (0x00000001U << ETH_INTERRUPT_MASK_Reserved_1_Pos)
\r
8027 #define ETH_INTERRUPT_MASK_Reserved_2_Pos (2U)
\r
8028 #define ETH_INTERRUPT_MASK_Reserved_2_Msk (0x00000001U << ETH_INTERRUPT_MASK_Reserved_2_Pos)
\r
8030 #define ETH_INTERRUPT_MASK_PMTIM_Pos (3U)
\r
8031 #define ETH_INTERRUPT_MASK_PMTIM_Msk (0x00000001U << ETH_INTERRUPT_MASK_PMTIM_Pos)
\r
8033 #define ETH_INTERRUPT_MASK_Reserved_8_4_Pos (4U)
\r
8034 #define ETH_INTERRUPT_MASK_Reserved_8_4_Msk (0x0000001FU << ETH_INTERRUPT_MASK_Reserved_8_4_Pos)
\r
8036 #define ETH_INTERRUPT_MASK_TSIM_Pos (9U)
\r
8037 #define ETH_INTERRUPT_MASK_TSIM_Msk (0x00000001U << ETH_INTERRUPT_MASK_TSIM_Pos)
\r
8039 #define ETH_INTERRUPT_MASK_LPIIM_Pos (10U)
\r
8040 #define ETH_INTERRUPT_MASK_LPIIM_Msk (0x00000001U << ETH_INTERRUPT_MASK_LPIIM_Pos)
\r
8042 #define ETH_INTERRUPT_MASK_Reserved_31_11_Pos (11U)
\r
8043 #define ETH_INTERRUPT_MASK_Reserved_31_11_Msk (0x001FFFFFU << ETH_INTERRUPT_MASK_Reserved_31_11_Pos)
\r
8045 /* ETH_MAC_ADDRESS0_HIGH = Register 16 [MAC Address0 High Register]*/
\r
8046 #define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos (0U)
\r
8047 #define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Msk (0x0000FFFFU << ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos)
\r
8049 #define ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Pos (16U)
\r
8050 #define ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Msk (0x00007FFFU << ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Pos)
\r
8052 #define ETH_MAC_ADDRESS0_HIGH_AE_Pos (31U)
\r
8053 #define ETH_MAC_ADDRESS0_HIGH_AE_Msk (0x00000001U << ETH_MAC_ADDRESS0_HIGH_AE_Pos)
\r
8055 /* ETH_MAC_ADDRESS0_LOW = Register 17 [MAC Address0 Low Register]*/
\r
8056 #define ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos (0U)
\r
8057 #define ETH_MAC_ADDRESS0_LOW_ADDRLO_Msk (0xFFFFFFFFU << ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos)
\r
8059 /* ETH_MAC_ADDRESS1_HIGH = Register 18 [MAC Address1 High Register]*/
\r
8060 #define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos (0U)
\r
8061 #define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Msk (0x0000FFFFU << ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos)
\r
8063 #define ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Pos (16U)
\r
8064 #define ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Msk (0x000000FFU << ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Pos)
\r
8066 #define ETH_MAC_ADDRESS1_HIGH_MBC_Pos (24U)
\r
8067 #define ETH_MAC_ADDRESS1_HIGH_MBC_Msk (0x0000003FU << ETH_MAC_ADDRESS1_HIGH_MBC_Pos)
\r
8069 #define ETH_MAC_ADDRESS1_HIGH_SA_Pos (30U)
\r
8070 #define ETH_MAC_ADDRESS1_HIGH_SA_Msk (0x00000001U << ETH_MAC_ADDRESS1_HIGH_SA_Pos)
\r
8072 #define ETH_MAC_ADDRESS1_HIGH_AE_Pos (31U)
\r
8073 #define ETH_MAC_ADDRESS1_HIGH_AE_Msk (0x00000001U << ETH_MAC_ADDRESS1_HIGH_AE_Pos)
\r
8075 /* ETH_MAC_ADDRESS1_LOW = Register 19 [MAC Address1 Low Register]*/
\r
8076 #define ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos (0U)
\r
8077 #define ETH_MAC_ADDRESS1_LOW_ADDRLO_Msk (0xFFFFFFFFU << ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos)
\r
8079 /* ETH_MAC_ADDRESS2_HIGH = Register 20 [MAC Address2 High Register]*/
\r
8080 #define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos (0U)
\r
8081 #define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Msk (0x0000FFFFU << ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos)
\r
8083 #define ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Pos (16U)
\r
8084 #define ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Msk (0x000000FFU << ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Pos)
\r
8086 #define ETH_MAC_ADDRESS2_HIGH_MBC_Pos (24U)
\r
8087 #define ETH_MAC_ADDRESS2_HIGH_MBC_Msk (0x0000003FU << ETH_MAC_ADDRESS2_HIGH_MBC_Pos)
\r
8089 #define ETH_MAC_ADDRESS2_HIGH_SA_Pos (30U)
\r
8090 #define ETH_MAC_ADDRESS2_HIGH_SA_Msk (0x00000001U << ETH_MAC_ADDRESS2_HIGH_SA_Pos)
\r
8092 #define ETH_MAC_ADDRESS2_HIGH_AE_Pos (31U)
\r
8093 #define ETH_MAC_ADDRESS2_HIGH_AE_Msk (0x00000001U << ETH_MAC_ADDRESS2_HIGH_AE_Pos)
\r
8095 /* ETH_MAC_ADDRESS2_LOW = Register 21 [MAC Address2 Low Register]*/
\r
8096 #define ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos (0U)
\r
8097 #define ETH_MAC_ADDRESS2_LOW_ADDRLO_Msk (0xFFFFFFFFU << ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos)
\r
8099 /* ETH_MAC_ADDRESS3_HIGH = Register 22 [MAC Address3 High Register]*/
\r
8100 #define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos (0U)
\r
8101 #define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Msk (0x0000FFFFU << ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos)
\r
8103 #define ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Pos (16U)
\r
8104 #define ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Msk (0x000000FFU << ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Pos)
\r
8106 #define ETH_MAC_ADDRESS3_HIGH_MBC_Pos (24U)
\r
8107 #define ETH_MAC_ADDRESS3_HIGH_MBC_Msk (0x0000003FU << ETH_MAC_ADDRESS3_HIGH_MBC_Pos)
\r
8109 #define ETH_MAC_ADDRESS3_HIGH_SA_Pos (30U)
\r
8110 #define ETH_MAC_ADDRESS3_HIGH_SA_Msk (0x00000001U << ETH_MAC_ADDRESS3_HIGH_SA_Pos)
\r
8112 #define ETH_MAC_ADDRESS3_HIGH_AE_Pos (31U)
\r
8113 #define ETH_MAC_ADDRESS3_HIGH_AE_Msk (0x00000001U << ETH_MAC_ADDRESS3_HIGH_AE_Pos)
\r
8115 /* ETH_MAC_ADDRESS3_LOW = Register 23 [MAC Address3 Low Register]*/
\r
8116 #define ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos (0U)
\r
8117 #define ETH_MAC_ADDRESS3_LOW_ADDRLO_Msk (0xFFFFFFFFU << ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos)
\r
8119 /* ETH_MMC_CONTROL = Register 64 [MMC Control Register]*/
\r
8120 #define ETH_MMC_CONTROL_CNTRST_Pos (0U)
\r
8121 #define ETH_MMC_CONTROL_CNTRST_Msk (0x00000001U << ETH_MMC_CONTROL_CNTRST_Pos)
\r
8123 #define ETH_MMC_CONTROL_CNTSTOPRO_Pos (1U)
\r
8124 #define ETH_MMC_CONTROL_CNTSTOPRO_Msk (0x00000001U << ETH_MMC_CONTROL_CNTSTOPRO_Pos)
\r
8126 #define ETH_MMC_CONTROL_RSTONRD_Pos (2U)
\r
8127 #define ETH_MMC_CONTROL_RSTONRD_Msk (0x00000001U << ETH_MMC_CONTROL_RSTONRD_Pos)
\r
8129 #define ETH_MMC_CONTROL_CNTFREEZ_Pos (3U)
\r
8130 #define ETH_MMC_CONTROL_CNTFREEZ_Msk (0x00000001U << ETH_MMC_CONTROL_CNTFREEZ_Pos)
\r
8132 #define ETH_MMC_CONTROL_CNTPRST_Pos (4U)
\r
8133 #define ETH_MMC_CONTROL_CNTPRST_Msk (0x00000001U << ETH_MMC_CONTROL_CNTPRST_Pos)
\r
8135 #define ETH_MMC_CONTROL_CNTPRSTLVL_Pos (5U)
\r
8136 #define ETH_MMC_CONTROL_CNTPRSTLVL_Msk (0x00000001U << ETH_MMC_CONTROL_CNTPRSTLVL_Pos)
\r
8138 #define ETH_MMC_CONTROL_Reserved_7_6_Pos (6U)
\r
8139 #define ETH_MMC_CONTROL_Reserved_7_6_Msk (0x00000003U << ETH_MMC_CONTROL_Reserved_7_6_Pos)
\r
8141 #define ETH_MMC_CONTROL_UCDBC_Pos (8U)
\r
8142 #define ETH_MMC_CONTROL_UCDBC_Msk (0x00000001U << ETH_MMC_CONTROL_UCDBC_Pos)
\r
8144 #define ETH_MMC_CONTROL_Reserved_31_9_Pos (9U)
\r
8145 #define ETH_MMC_CONTROL_Reserved_31_9_Msk (0x007FFFFFU << ETH_MMC_CONTROL_Reserved_31_9_Pos)
\r
8147 /* ETH_MMC_RECEIVE_INTERRUPT = Register 65 [MMC Receive Interrupt Register]*/
\r
8148 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos (0U)
\r
8149 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos)
\r
8151 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos (1U)
\r
8152 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos)
\r
8154 #define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos (2U)
\r
8155 #define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos)
\r
8157 #define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos (3U)
\r
8158 #define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos)
\r
8160 #define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos (4U)
\r
8161 #define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos)
\r
8163 #define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos (5U)
\r
8164 #define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos)
\r
8166 #define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos (6U)
\r
8167 #define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos)
\r
8169 #define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos (7U)
\r
8170 #define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos)
\r
8172 #define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos (8U)
\r
8173 #define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos)
\r
8175 #define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos (9U)
\r
8176 #define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos)
\r
8178 #define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos (10U)
\r
8179 #define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos)
\r
8181 #define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos (11U)
\r
8182 #define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos)
\r
8184 #define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos (12U)
\r
8185 #define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos)
\r
8187 #define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos (13U)
\r
8188 #define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos)
\r
8190 #define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos (14U)
\r
8191 #define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos)
\r
8193 #define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos (15U)
\r
8194 #define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos)
\r
8196 #define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos (16U)
\r
8197 #define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos)
\r
8199 #define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos (17U)
\r
8200 #define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos)
\r
8202 #define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos (18U)
\r
8203 #define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos)
\r
8205 #define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos (19U)
\r
8206 #define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos)
\r
8208 #define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos (20U)
\r
8209 #define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos)
\r
8211 #define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos (21U)
\r
8212 #define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos)
\r
8214 #define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos (22U)
\r
8215 #define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos)
\r
8217 #define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos (23U)
\r
8218 #define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos)
\r
8220 #define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos (24U)
\r
8221 #define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos)
\r
8223 #define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos (25U)
\r
8224 #define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos)
\r
8226 #define ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Pos (26U)
\r
8227 #define ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Msk (0x0000003FU << ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Pos)
\r
8229 /* ETH_MMC_TRANSMIT_INTERRUPT = Register 66 [MMC Transmit Interrupt Register]*/
\r
8230 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos (0U)
\r
8231 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos)
\r
8233 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos (1U)
\r
8234 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos)
\r
8236 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos (2U)
\r
8237 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos)
\r
8239 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos (3U)
\r
8240 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos)
\r
8242 #define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos (4U)
\r
8243 #define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos)
\r
8245 #define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos (5U)
\r
8246 #define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos)
\r
8248 #define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos (6U)
\r
8249 #define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos)
\r
8251 #define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos (7U)
\r
8252 #define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos)
\r
8254 #define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos (8U)
\r
8255 #define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos)
\r
8257 #define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos (9U)
\r
8258 #define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos)
\r
8260 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos (10U)
\r
8261 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos)
\r
8263 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos (11U)
\r
8264 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos)
\r
8266 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos (12U)
\r
8267 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos)
\r
8269 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos (13U)
\r
8270 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos)
\r
8272 #define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos (14U)
\r
8273 #define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos)
\r
8275 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos (15U)
\r
8276 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos)
\r
8278 #define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos (16U)
\r
8279 #define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos)
\r
8281 #define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos (17U)
\r
8282 #define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos)
\r
8284 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos (18U)
\r
8285 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos)
\r
8287 #define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos (19U)
\r
8288 #define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos)
\r
8290 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos (20U)
\r
8291 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos)
\r
8293 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos (21U)
\r
8294 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos)
\r
8296 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos (22U)
\r
8297 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos)
\r
8299 #define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos (23U)
\r
8300 #define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos)
\r
8302 #define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos (24U)
\r
8303 #define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos)
\r
8305 #define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos (25U)
\r
8306 #define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos)
\r
8308 #define ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Pos (26U)
\r
8309 #define ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Msk (0x0000003FU << ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Pos)
\r
8311 /* ETH_MMC_RECEIVE_INTERRUPT_MASK = */
\r
8312 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos (0U)
\r
8313 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos)
\r
8315 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos (1U)
\r
8316 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos)
\r
8318 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos (2U)
\r
8319 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos)
\r
8321 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos (3U)
\r
8322 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos)
\r
8324 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos (4U)
\r
8325 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos)
\r
8327 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos (5U)
\r
8328 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos)
\r
8330 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos (6U)
\r
8331 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos)
\r
8333 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos (7U)
\r
8334 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos)
\r
8336 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos (8U)
\r
8337 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos)
\r
8339 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos (9U)
\r
8340 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos)
\r
8342 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos (10U)
\r
8343 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos)
\r
8345 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos (11U)
\r
8346 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos)
\r
8348 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos (12U)
\r
8349 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos)
\r
8351 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos (13U)
\r
8352 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos)
\r
8354 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos (14U)
\r
8355 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos)
\r
8357 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos (15U)
\r
8358 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos)
\r
8360 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos (16U)
\r
8361 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos)
\r
8363 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos (17U)
\r
8364 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos)
\r
8366 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos (18U)
\r
8367 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos)
\r
8369 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos (19U)
\r
8370 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos)
\r
8372 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos (20U)
\r
8373 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos)
\r
8375 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos (21U)
\r
8376 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos)
\r
8378 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos (22U)
\r
8379 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos)
\r
8381 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos (23U)
\r
8382 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos)
\r
8384 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos (24U)
\r
8385 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos)
\r
8387 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos (25U)
\r
8388 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Msk (0x00000001U << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos)
\r
8390 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Pos (26U)
\r
8391 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Msk (0x0000003FU << ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Pos)
\r
8393 /* ETH_MMC_TRANSMIT_INTERRUPT_MASK = */
\r
8394 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos (0U)
\r
8395 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos)
\r
8397 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos (1U)
\r
8398 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos)
\r
8400 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos (2U)
\r
8401 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos)
\r
8403 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos (3U)
\r
8404 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos)
\r
8406 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos (4U)
\r
8407 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos)
\r
8409 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos (5U)
\r
8410 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos)
\r
8412 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos (6U)
\r
8413 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos)
\r
8415 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos (7U)
\r
8416 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos)
\r
8418 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos (8U)
\r
8419 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos)
\r
8421 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos (9U)
\r
8422 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos)
\r
8424 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos (10U)
\r
8425 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos)
\r
8427 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos (11U)
\r
8428 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos)
\r
8430 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos (12U)
\r
8431 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos)
\r
8433 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos (13U)
\r
8434 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos)
\r
8436 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos (14U)
\r
8437 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos)
\r
8439 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos (15U)
\r
8440 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos)
\r
8442 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos (16U)
\r
8443 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos)
\r
8445 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos (17U)
\r
8446 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos)
\r
8448 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos (18U)
\r
8449 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos)
\r
8451 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos (19U)
\r
8452 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos)
\r
8454 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos (20U)
\r
8455 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos)
\r
8457 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos (21U)
\r
8458 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos)
\r
8460 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos (22U)
\r
8461 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos)
\r
8463 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos (23U)
\r
8464 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos)
\r
8466 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos (24U)
\r
8467 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos)
\r
8469 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos (25U)
\r
8470 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Msk (0x00000001U << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos)
\r
8472 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Pos (26U)
\r
8473 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Msk (0x0000003FU << ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Pos)
\r
8475 /* ETH_TX_OCTET_COUNT_GOOD_BAD = Register 69 [Transmit Octet Count for Good and Bad Frames]*/
\r
8476 #define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos (0U)
\r
8477 #define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Msk (0xFFFFFFFFU << ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos)
\r
8479 /* ETH_TX_FRAME_COUNT_GOOD_BAD = Register 70 [Transmit Frame Count for Good and Bad Frames]*/
\r
8480 #define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos (0U)
\r
8481 #define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Msk (0xFFFFFFFFU << ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos)
\r
8483 /* ETH_TX_BROADCAST_FRAMES_GOOD = Register 71 [Transmit Frame Count for Good Broadcast Frames]*/
\r
8484 #define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos (0U)
\r
8485 #define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Msk (0xFFFFFFFFU << ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos)
\r
8487 /* ETH_TX_MULTICAST_FRAMES_GOOD = Register 72 [Transmit Frame Count for Good Multicast Frames]*/
\r
8488 #define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos (0U)
\r
8489 #define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Msk (0xFFFFFFFFU << ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos)
\r
8491 /* ETH_TX_64OCTETS_FRAMES_GOOD_BAD = Register 73 [Transmit Octet Count for Good and Bad 64 Byte Frames]*/
\r
8492 #define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos (0U)
\r
8493 #define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Msk (0xFFFFFFFFU << ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos)
\r
8495 /* ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD = Register 74 [Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames]*/
\r
8496 #define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos (0U)
\r
8497 #define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Msk (0xFFFFFFFFU << ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos)
\r
8499 /* ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD = Register 75 [Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames]*/
\r
8500 #define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos (0U)
\r
8501 #define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Msk (0xFFFFFFFFU << ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos)
\r
8503 /* ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD = Register 76 [Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames]*/
\r
8504 #define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos (0U)
\r
8505 #define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Msk (0xFFFFFFFFU << ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos)
\r
8507 /* ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD = Register 77 [Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames]*/
\r
8508 #define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos (0U)
\r
8509 #define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Msk (0xFFFFFFFFU << ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos)
\r
8511 /* ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD = Register 78 [Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames]*/
\r
8512 #define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos (0U)
\r
8513 #define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Msk (0xFFFFFFFFU << ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos)
\r
8515 /* ETH_TX_UNICAST_FRAMES_GOOD_BAD = Register 79 [Transmit Frame Count for Good and Bad Unicast Frames]*/
\r
8516 #define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos (0U)
\r
8517 #define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Msk (0xFFFFFFFFU << ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos)
\r
8519 /* ETH_TX_MULTICAST_FRAMES_GOOD_BAD = Register 80 [Transmit Frame Count for Good and Bad Multicast Frames]*/
\r
8520 #define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos (0U)
\r
8521 #define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Msk (0xFFFFFFFFU << ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos)
\r
8523 /* ETH_TX_BROADCAST_FRAMES_GOOD_BAD = Register 81 [Transmit Frame Count for Good and Bad Broadcast Frames]*/
\r
8524 #define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos (0U)
\r
8525 #define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Msk (0xFFFFFFFFU << ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos)
\r
8527 /* ETH_TX_UNDERFLOW_ERROR_FRAMES = Register 82 [Transmit Frame Count for Underflow Error Frames]*/
\r
8528 #define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos (0U)
\r
8529 #define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Msk (0xFFFFFFFFU << ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos)
\r
8531 /* ETH_TX_SINGLE_COLLISION_GOOD_FRAMES = Register 83 [Transmit Frame Count for Frames Transmitted after Single Collision]*/
\r
8532 #define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos (0U)
\r
8533 #define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Msk (0xFFFFFFFFU << ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos)
\r
8535 /* ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES = Register 84 [Transmit Frame Count for Frames Transmitted after Multiple Collision]*/
\r
8536 #define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos (0U)
\r
8537 #define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Msk (0xFFFFFFFFU << ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos)
\r
8539 /* ETH_TX_DEFERRED_FRAMES = */
\r
8540 #define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos (0U)
\r
8541 #define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Msk (0xFFFFFFFFU << ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos)
\r
8543 /* ETH_TX_LATE_COLLISION_FRAMES = Register 86 [Transmit Frame Count for Late Collision Error Frames]*/
\r
8544 #define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos (0U)
\r
8545 #define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Msk (0xFFFFFFFFU << ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos)
\r
8547 /* ETH_TX_EXCESSIVE_COLLISION_FRAMES = Register 87 [Transmit Frame Count for Excessive Collision Error Frames]*/
\r
8548 #define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos (0U)
\r
8549 #define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Msk (0xFFFFFFFFU << ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos)
\r
8551 /* ETH_TX_CARRIER_ERROR_FRAMES = Register 88 [Transmit Frame Count for Carrier Sense Error Frames]*/
\r
8552 #define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos (0U)
\r
8553 #define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Msk (0xFFFFFFFFU << ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos)
\r
8555 /* ETH_TX_OCTET_COUNT_GOOD = */
\r
8556 #define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos (0U)
\r
8557 #define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Msk (0xFFFFFFFFU << ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos)
\r
8559 /* ETH_TX_FRAME_COUNT_GOOD = */
\r
8560 #define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos (0U)
\r
8561 #define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Msk (0xFFFFFFFFU << ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos)
\r
8563 /* ETH_TX_EXCESSIVE_DEFERRAL_ERROR = Register 91 [Transmit Frame Count for Excessive Deferral Error Frames]*/
\r
8564 #define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos (0U)
\r
8565 #define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Msk (0xFFFFFFFFU << ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos)
\r
8567 /* ETH_TX_PAUSE_FRAMES = Register 92 [Transmit Frame Count for Good PAUSE Frames]*/
\r
8568 #define ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos (0U)
\r
8569 #define ETH_TX_PAUSE_FRAMES_TXPAUSE_Msk (0xFFFFFFFFU << ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos)
\r
8571 /* ETH_TX_VLAN_FRAMES_GOOD = Register 93 [Transmit Frame Count for Good VLAN Frames]*/
\r
8572 #define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos (0U)
\r
8573 #define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Msk (0xFFFFFFFFU << ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos)
\r
8575 /* ETH_TX_OSIZE_FRAMES_GOOD = Register 94 [Transmit Frame Count for Good Oversize Frames]*/
\r
8576 #define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos (0U)
\r
8577 #define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Msk (0xFFFFFFFFU << ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos)
\r
8579 /* ETH_RX_FRAMES_COUNT_GOOD_BAD = Register 96 [Receive Frame Count for Good and Bad Frames]*/
\r
8580 #define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos (0U)
\r
8581 #define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Msk (0xFFFFFFFFU << ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos)
\r
8583 /* ETH_RX_OCTET_COUNT_GOOD_BAD = Register 97 [Receive Octet Count for Good and Bad Frames]*/
\r
8584 #define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos (0U)
\r
8585 #define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Msk (0xFFFFFFFFU << ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos)
\r
8587 /* ETH_RX_OCTET_COUNT_GOOD = */
\r
8588 #define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos (0U)
\r
8589 #define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Msk (0xFFFFFFFFU << ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos)
\r
8591 /* ETH_RX_BROADCAST_FRAMES_GOOD = Register 99 [Receive Frame Count for Good Broadcast Frames]*/
\r
8592 #define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos (0U)
\r
8593 #define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Msk (0xFFFFFFFFU << ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos)
\r
8595 /* ETH_RX_MULTICAST_FRAMES_GOOD = Register 100 [Receive Frame Count for Good Multicast Frames]*/
\r
8596 #define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos (0U)
\r
8597 #define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Msk (0xFFFFFFFFU << ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos)
\r
8599 /* ETH_RX_CRC_ERROR_FRAMES = Register 101 [Receive Frame Count for CRC Error Frames]*/
\r
8600 #define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos (0U)
\r
8601 #define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Msk (0xFFFFFFFFU << ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos)
\r
8603 /* ETH_RX_ALIGNMENT_ERROR_FRAMES = Register 102 [Receive Frame Count for Alignment Error Frames]*/
\r
8604 #define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos (0U)
\r
8605 #define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Msk (0xFFFFFFFFU << ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos)
\r
8607 /* ETH_RX_RUNT_ERROR_FRAMES = Register 103 [Receive Frame Count for Runt Error Frames]*/
\r
8608 #define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos (0U)
\r
8609 #define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Msk (0xFFFFFFFFU << ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos)
\r
8611 /* ETH_RX_JABBER_ERROR_FRAMES = Register 104 [Receive Frame Count for Jabber Error Frames]*/
\r
8612 #define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos (0U)
\r
8613 #define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Msk (0xFFFFFFFFU << ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos)
\r
8615 /* ETH_RX_UNDERSIZE_FRAMES_GOOD = Register 105 [Receive Frame Count for Undersize Frames]*/
\r
8616 #define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos (0U)
\r
8617 #define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Msk (0xFFFFFFFFU << ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos)
\r
8619 /* ETH_RX_OVERSIZE_FRAMES_GOOD = */
\r
8620 #define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos (0U)
\r
8621 #define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Msk (0xFFFFFFFFU << ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos)
\r
8623 /* ETH_RX_64OCTETS_FRAMES_GOOD_BAD = Register 107 [Receive Frame Count for Good and Bad 64 Byte Frames]*/
\r
8624 #define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos (0U)
\r
8625 #define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Msk (0xFFFFFFFFU << ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos)
\r
8627 /* ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD = Register 108 [Receive Frame Count for Good and Bad 65 to 127 Bytes Frames]*/
\r
8628 #define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos (0U)
\r
8629 #define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Msk (0xFFFFFFFFU << ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos)
\r
8631 /* ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD = Register 109 [Receive Frame Count for Good and Bad 128 to 255 Bytes Frames]*/
\r
8632 #define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos (0U)
\r
8633 #define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Msk (0xFFFFFFFFU << ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos)
\r
8635 /* ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD = Register 110 [Receive Frame Count for Good and Bad 256 to 511 Bytes Frames]*/
\r
8636 #define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos (0U)
\r
8637 #define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Msk (0xFFFFFFFFU << ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos)
\r
8639 /* ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD = Register 111 [Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames]*/
\r
8640 #define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos (0U)
\r
8641 #define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Msk (0xFFFFFFFFU << ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos)
\r
8643 /* ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD = Register 112 [Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames]*/
\r
8644 #define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos (0U)
\r
8645 #define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Msk (0xFFFFFFFFU << ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos)
\r
8647 /* ETH_RX_UNICAST_FRAMES_GOOD = Register 113 [Receive Frame Count for Good Unicast Frames]*/
\r
8648 #define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos (0U)
\r
8649 #define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Msk (0xFFFFFFFFU << ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos)
\r
8651 /* ETH_RX_LENGTH_ERROR_FRAMES = Register 114 [Receive Frame Count for Length Error Frames]*/
\r
8652 #define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos (0U)
\r
8653 #define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Msk (0xFFFFFFFFU << ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos)
\r
8655 /* ETH_RX_OUT_OF_RANGE_TYPE_FRAMES = Register 115 [Receive Frame Count for Out of Range Frames]*/
\r
8656 #define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos (0U)
\r
8657 #define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Msk (0xFFFFFFFFU << ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos)
\r
8659 /* ETH_RX_PAUSE_FRAMES = Register 116 [Receive Frame Count for PAUSE Frames]*/
\r
8660 #define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos (0U)
\r
8661 #define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Msk (0xFFFFFFFFU << ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos)
\r
8663 /* ETH_RX_FIFO_OVERFLOW_FRAMES = Register 117 [Receive Frame Count for FIFO Overflow Frames]*/
\r
8664 #define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos (0U)
\r
8665 #define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Msk (0xFFFFFFFFU << ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos)
\r
8667 /* ETH_RX_VLAN_FRAMES_GOOD_BAD = Register 118 [Receive Frame Count for Good and Bad VLAN Frames]*/
\r
8668 #define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos (0U)
\r
8669 #define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Msk (0xFFFFFFFFU << ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos)
\r
8671 /* ETH_RX_WATCHDOG_ERROR_FRAMES = Register 119 [Receive Frame Count for Watchdog Error Frames]*/
\r
8672 #define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos (0U)
\r
8673 #define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Msk (0xFFFFFFFFU << ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos)
\r
8675 /* ETH_RX_RECEIVE_ERROR_FRAMES = Register 120 [Receive Frame Count for Receive Error Frames]*/
\r
8676 #define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos (0U)
\r
8677 #define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Msk (0xFFFFFFFFU << ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos)
\r
8679 /* ETH_RX_CONTROL_FRAMES_GOOD = Register 121 [Receive Frame Count for Good Control Frames Frames]*/
\r
8680 #define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos (0U)
\r
8681 #define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Msk (0xFFFFFFFFU << ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos)
\r
8683 /* ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK = Register 128 [MMC Receive Checksum Offload Interrupt Mask Register]*/
\r
8684 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos (0U)
\r
8685 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos)
\r
8687 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos (1U)
\r
8688 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos)
\r
8690 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos (2U)
\r
8691 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos)
\r
8693 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos (3U)
\r
8694 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos)
\r
8696 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos (4U)
\r
8697 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos)
\r
8699 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos (5U)
\r
8700 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos)
\r
8702 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos (6U)
\r
8703 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos)
\r
8705 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos (7U)
\r
8706 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos)
\r
8708 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos (8U)
\r
8709 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos)
\r
8711 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos (9U)
\r
8712 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos)
\r
8714 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos (10U)
\r
8715 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos)
\r
8717 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos (11U)
\r
8718 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos)
\r
8720 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos (12U)
\r
8721 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos)
\r
8723 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos (13U)
\r
8724 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos)
\r
8726 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Pos (14U)
\r
8727 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Msk (0x00000003U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Pos)
\r
8729 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos (16U)
\r
8730 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos)
\r
8732 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos (17U)
\r
8733 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos)
\r
8735 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos (18U)
\r
8736 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos)
\r
8738 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos (19U)
\r
8739 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos)
\r
8741 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos (20U)
\r
8742 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos)
\r
8744 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos (21U)
\r
8745 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos)
\r
8747 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos (22U)
\r
8748 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos)
\r
8750 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos (23U)
\r
8751 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos)
\r
8753 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos (24U)
\r
8754 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos)
\r
8756 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos (25U)
\r
8757 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos)
\r
8759 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos (26U)
\r
8760 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos)
\r
8762 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos (27U)
\r
8763 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos)
\r
8765 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos (28U)
\r
8766 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos)
\r
8768 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos (29U)
\r
8769 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos)
\r
8771 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Pos (30U)
\r
8772 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Msk (0x00000003U << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Pos)
\r
8774 /* ETH_MMC_IPC_RECEIVE_INTERRUPT = Register 130 [MMC Receive Checksum Offload Interrupt Register]*/
\r
8775 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos (0U)
\r
8776 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos)
\r
8778 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos (1U)
\r
8779 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos)
\r
8781 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos (2U)
\r
8782 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos)
\r
8784 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos (3U)
\r
8785 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos)
\r
8787 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos (4U)
\r
8788 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos)
\r
8790 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos (5U)
\r
8791 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos)
\r
8793 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos (6U)
\r
8794 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos)
\r
8796 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos (7U)
\r
8797 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos)
\r
8799 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos (8U)
\r
8800 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos)
\r
8802 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos (9U)
\r
8803 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos)
\r
8805 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos (10U)
\r
8806 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos)
\r
8808 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos (11U)
\r
8809 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos)
\r
8811 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos (12U)
\r
8812 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos)
\r
8814 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos (13U)
\r
8815 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos)
\r
8817 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Pos (14U)
\r
8818 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Msk (0x00000003U << ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Pos)
\r
8820 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos (16U)
\r
8821 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos)
\r
8823 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos (17U)
\r
8824 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos)
\r
8826 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos (18U)
\r
8827 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos)
\r
8829 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos (19U)
\r
8830 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos)
\r
8832 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos (20U)
\r
8833 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos)
\r
8835 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos (21U)
\r
8836 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos)
\r
8838 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos (22U)
\r
8839 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos)
\r
8841 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos (23U)
\r
8842 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos)
\r
8844 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos (24U)
\r
8845 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos)
\r
8847 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos (25U)
\r
8848 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos)
\r
8850 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos (26U)
\r
8851 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos)
\r
8853 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos (27U)
\r
8854 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos)
\r
8856 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos (28U)
\r
8857 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos)
\r
8859 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos (29U)
\r
8860 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Msk (0x00000001U << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos)
\r
8862 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Pos (30U)
\r
8863 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Msk (0x00000003U << ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Pos)
\r
8865 /* ETH_RXIPV4_GOOD_FRAMES = */
\r
8866 #define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos (0U)
\r
8867 #define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Msk (0xFFFFFFFFU << ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos)
\r
8869 /* ETH_RXIPV4_HEADER_ERROR_FRAMES = Register 133 [Receive IPV4 Header Error Frame Counter Register]*/
\r
8870 #define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos (0U)
\r
8871 #define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Msk (0xFFFFFFFFU << ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos)
\r
8873 /* ETH_RXIPV4_NO_PAYLOAD_FRAMES = Register 134 [Receive IPV4 No Payload Frame Counter Register]*/
\r
8874 #define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos (0U)
\r
8875 #define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Msk (0xFFFFFFFFU << ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos)
\r
8877 /* ETH_RXIPV4_FRAGMENTED_FRAMES = Register 135 [Receive IPV4 Fragmented Frame Counter Register]*/
\r
8878 #define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos (0U)
\r
8879 #define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Msk (0xFFFFFFFFU << ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos)
\r
8881 /* ETH_RXIPV4_UDPORT_CHECKSUM_DISABLED_FRAMES = Register 136 [Receive IPV4 UDP Checksum Disabled Frame Counter Register]*/
\r
8882 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos (0U)
\r
8883 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Msk (0xFFFFFFFFU << ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos)
\r
8885 /* ETH_RXIPV6_GOOD_FRAMES = */
\r
8886 #define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos (0U)
\r
8887 #define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Msk (0xFFFFFFFFU << ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos)
\r
8889 /* ETH_RXIPV6_HEADER_ERROR_FRAMES = Register 138 [Receive IPV6 Header Error Frame Counter Register]*/
\r
8890 #define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos (0U)
\r
8891 #define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Msk (0xFFFFFFFFU << ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos)
\r
8893 /* ETH_RXIPV6_NO_PAYLOAD_FRAMES = Register 139 [Receive IPV6 No Payload Frame Counter Register]*/
\r
8894 #define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos (0U)
\r
8895 #define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Msk (0xFFFFFFFFU << ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos)
\r
8897 /* ETH_RXUDPORT_GOOD_FRAMES = */
\r
8898 #define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos (0U)
\r
8899 #define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Msk (0xFFFFFFFFU << ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos)
\r
8901 /* ETH_RXUDPORT_ERROR_FRAMES = */
\r
8902 #define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos (0U)
\r
8903 #define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Msk (0xFFFFFFFFU << ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos)
\r
8905 /* ETH_RXTCPORT_GOOD_FRAMES = */
\r
8906 #define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos (0U)
\r
8907 #define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Msk (0xFFFFFFFFU << ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos)
\r
8909 /* ETH_RXTCPORT_ERROR_FRAMES = */
\r
8910 #define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos (0U)
\r
8911 #define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Msk (0xFFFFFFFFU << ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos)
\r
8913 /* ETH_RXICMP_GOOD_FRAMES = */
\r
8914 #define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos (0U)
\r
8915 #define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Msk (0xFFFFFFFFU << ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos)
\r
8917 /* ETH_RXICMP_ERROR_FRAMES = */
\r
8918 #define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos (0U)
\r
8919 #define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Msk (0xFFFFFFFFU << ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos)
\r
8921 /* ETH_RXIPV4_GOOD_OCTETS = */
\r
8922 #define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos (0U)
\r
8923 #define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Msk (0xFFFFFFFFU << ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos)
\r
8925 /* ETH_RXIPV4_HEADER_ERROR_OCTETS = Register 149 [Receive IPV4 Header Error Octet Counter Register]*/
\r
8926 #define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos (0U)
\r
8927 #define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Msk (0xFFFFFFFFU << ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos)
\r
8929 /* ETH_RXIPV4_NO_PAYLOAD_OCTETS = Register 150 [Receive IPV4 No Payload Octet Counter Register]*/
\r
8930 #define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos (0U)
\r
8931 #define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Msk (0xFFFFFFFFU << ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos)
\r
8933 /* ETH_RXIPV4_FRAGMENTED_OCTETS = Register 151 [Receive IPV4 Fragmented Octet Counter Register]*/
\r
8934 #define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos (0U)
\r
8935 #define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Msk (0xFFFFFFFFU << ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos)
\r
8937 /* ETH_RXIPV4_UDPORT_CHECKSUM_DISABLE_OCTETS = Register 152 [Receive IPV4 Fragmented Octet Counter Register]*/
\r
8938 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos (0U)
\r
8939 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Msk (0xFFFFFFFFU << ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos)
\r
8941 /* ETH_RXIPV6_GOOD_OCTETS = */
\r
8942 #define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos (0U)
\r
8943 #define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Msk (0xFFFFFFFFU << ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos)
\r
8945 /* ETH_RXIPV6_HEADER_ERROR_OCTETS = Register 154 [Receive IPV6 Header Error Octet Counter Register]*/
\r
8946 #define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos (0U)
\r
8947 #define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Msk (0xFFFFFFFFU << ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos)
\r
8949 /* ETH_RXIPV6_NO_PAYLOAD_OCTETS = Register 155 [Receive IPV6 No Payload Octet Counter Register]*/
\r
8950 #define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos (0U)
\r
8951 #define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Msk (0xFFFFFFFFU << ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos)
\r
8953 /* ETH_RXUDPORT_GOOD_OCTETS = */
\r
8954 #define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos (0U)
\r
8955 #define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Msk (0xFFFFFFFFU << ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos)
\r
8957 /* ETH_RXUDPORT_ERROR_OCTETS = */
\r
8958 #define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos (0U)
\r
8959 #define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Msk (0xFFFFFFFFU << ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos)
\r
8961 /* ETH_RXTCPORT_GOOD_OCTETS = */
\r
8962 #define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos (0U)
\r
8963 #define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Msk (0xFFFFFFFFU << ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos)
\r
8965 /* ETH_RXTCPORT_ERROR_OCTETS = */
\r
8966 #define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos (0U)
\r
8967 #define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Msk (0xFFFFFFFFU << ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos)
\r
8969 /* ETH_RXICMP_GOOD_OCTETS = */
\r
8970 #define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos (0U)
\r
8971 #define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Msk (0xFFFFFFFFU << ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos)
\r
8973 /* ETH_RXICMP_ERROR_OCTETS = */
\r
8974 #define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos (0U)
\r
8975 #define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Msk (0xFFFFFFFFU << ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos)
\r
8977 /* ETH_TIMESTAMP_CONTROL = Register 448 [Timestamp Control Register]*/
\r
8978 #define ETH_TIMESTAMP_CONTROL_TSENA_Pos (0U)
\r
8979 #define ETH_TIMESTAMP_CONTROL_TSENA_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSENA_Pos)
\r
8981 #define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos (1U)
\r
8982 #define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos)
\r
8984 #define ETH_TIMESTAMP_CONTROL_TSINIT_Pos (2U)
\r
8985 #define ETH_TIMESTAMP_CONTROL_TSINIT_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSINIT_Pos)
\r
8987 #define ETH_TIMESTAMP_CONTROL_TSUPDT_Pos (3U)
\r
8988 #define ETH_TIMESTAMP_CONTROL_TSUPDT_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSUPDT_Pos)
\r
8990 #define ETH_TIMESTAMP_CONTROL_TSTRIG_Pos (4U)
\r
8991 #define ETH_TIMESTAMP_CONTROL_TSTRIG_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSTRIG_Pos)
\r
8993 #define ETH_TIMESTAMP_CONTROL_TSADDREG_Pos (5U)
\r
8994 #define ETH_TIMESTAMP_CONTROL_TSADDREG_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSADDREG_Pos)
\r
8996 #define ETH_TIMESTAMP_CONTROL_Reserved_7_6_Pos (6U)
\r
8997 #define ETH_TIMESTAMP_CONTROL_Reserved_7_6_Msk (0x00000003U << ETH_TIMESTAMP_CONTROL_Reserved_7_6_Pos)
\r
8999 #define ETH_TIMESTAMP_CONTROL_TSENALL_Pos (8U)
\r
9000 #define ETH_TIMESTAMP_CONTROL_TSENALL_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSENALL_Pos)
\r
9002 #define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos (9U)
\r
9003 #define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos)
\r
9005 #define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos (10U)
\r
9006 #define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos)
\r
9008 #define ETH_TIMESTAMP_CONTROL_TSIPENA_Pos (11U)
\r
9009 #define ETH_TIMESTAMP_CONTROL_TSIPENA_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSIPENA_Pos)
\r
9011 #define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos (12U)
\r
9012 #define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos)
\r
9014 #define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos (13U)
\r
9015 #define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos)
\r
9017 #define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos (14U)
\r
9018 #define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos)
\r
9020 #define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos (15U)
\r
9021 #define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos)
\r
9023 #define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos (16U)
\r
9024 #define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Msk (0x00000003U << ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos)
\r
9026 #define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos (18U)
\r
9027 #define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos)
\r
9029 #define ETH_TIMESTAMP_CONTROL_Reserved_23_19_Pos (19U)
\r
9030 #define ETH_TIMESTAMP_CONTROL_Reserved_23_19_Msk (0x0000001FU << ETH_TIMESTAMP_CONTROL_Reserved_23_19_Pos)
\r
9032 #define ETH_TIMESTAMP_CONTROL_ATSFC_Pos (24U)
\r
9033 #define ETH_TIMESTAMP_CONTROL_ATSFC_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_ATSFC_Pos)
\r
9035 #define ETH_TIMESTAMP_CONTROL_ATSEN0_Pos (25U)
\r
9036 #define ETH_TIMESTAMP_CONTROL_ATSEN0_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_ATSEN0_Pos)
\r
9038 #define ETH_TIMESTAMP_CONTROL_ATSEN1_Pos (26U)
\r
9039 #define ETH_TIMESTAMP_CONTROL_ATSEN1_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_ATSEN1_Pos)
\r
9041 #define ETH_TIMESTAMP_CONTROL_ATSEN2_Pos (27U)
\r
9042 #define ETH_TIMESTAMP_CONTROL_ATSEN2_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_ATSEN2_Pos)
\r
9044 #define ETH_TIMESTAMP_CONTROL_ATSEN3_Pos (28U)
\r
9045 #define ETH_TIMESTAMP_CONTROL_ATSEN3_Msk (0x00000001U << ETH_TIMESTAMP_CONTROL_ATSEN3_Pos)
\r
9047 #define ETH_TIMESTAMP_CONTROL_Reserved_31_29_Pos (29U)
\r
9048 #define ETH_TIMESTAMP_CONTROL_Reserved_31_29_Msk (0x00000007U << ETH_TIMESTAMP_CONTROL_Reserved_31_29_Pos)
\r
9050 /* ETH_SUB_SECOND_INCREMENT = Register 449 [Sub-Second Increment Register]*/
\r
9051 #define ETH_SUB_SECOND_INCREMENT_SSINC_Pos (0U)
\r
9052 #define ETH_SUB_SECOND_INCREMENT_SSINC_Msk (0x000000FFU << ETH_SUB_SECOND_INCREMENT_SSINC_Pos)
\r
9054 #define ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Pos (8U)
\r
9055 #define ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Msk (0x00FFFFFFU << ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Pos)
\r
9057 /* ETH_SYSTEM_TIME_SECONDS = Register 450 [System Time - Seconds Register]*/
\r
9058 #define ETH_SYSTEM_TIME_SECONDS_TSS_Pos (0U)
\r
9059 #define ETH_SYSTEM_TIME_SECONDS_TSS_Msk (0xFFFFFFFFU << ETH_SYSTEM_TIME_SECONDS_TSS_Pos)
\r
9061 /* ETH_SYSTEM_TIME_NANOSECONDS = */
\r
9062 #define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos (0U)
\r
9063 #define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Msk (0x7FFFFFFFU << ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos)
\r
9065 #define ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Pos (31U)
\r
9066 #define ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Msk (0x00000001U << ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Pos)
\r
9068 /* ETH_SYSTEM_TIME_SECONDS_UPDATE = Register 452 [System Time - Seconds Update Register]*/
\r
9069 #define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos (0U)
\r
9070 #define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Msk (0xFFFFFFFFU << ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos)
\r
9072 /* ETH_SYSTEM_TIME_NANOSECONDS_UPDATE = */
\r
9073 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos (0U)
\r
9074 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Msk (0x7FFFFFFFU << ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos)
\r
9076 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos (31U)
\r
9077 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Msk (0x00000001U << ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos)
\r
9079 /* ETH_TIMESTAMP_ADDEND = Register 454 [Timestamp Addend Register]*/
\r
9080 #define ETH_TIMESTAMP_ADDEND_TSAR_Pos (0U)
\r
9081 #define ETH_TIMESTAMP_ADDEND_TSAR_Msk (0xFFFFFFFFU << ETH_TIMESTAMP_ADDEND_TSAR_Pos)
\r
9083 /* ETH_TARGET_TIME_SECONDS = Register 455 [Target Time Seconds Register]*/
\r
9084 #define ETH_TARGET_TIME_SECONDS_TSTR_Pos (0U)
\r
9085 #define ETH_TARGET_TIME_SECONDS_TSTR_Msk (0xFFFFFFFFU << ETH_TARGET_TIME_SECONDS_TSTR_Pos)
\r
9087 /* ETH_TARGET_TIME_NANOSECONDS = */
\r
9088 #define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos (0U)
\r
9089 #define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Msk (0x7FFFFFFFU << ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos)
\r
9091 #define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos (31U)
\r
9092 #define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Msk (0x00000001U << ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos)
\r
9094 /* ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS = Register 457 [System Time - Higher Word Seconds Register]*/
\r
9095 #define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos (0U)
\r
9096 #define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Msk (0x0000FFFFU << ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos)
\r
9098 #define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Pos (16U)
\r
9099 #define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Msk (0x0000FFFFU << ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Pos)
\r
9101 /* ETH_TIMESTAMP_STATUS = Register 458 [Timestamp Status Register]*/
\r
9102 #define ETH_TIMESTAMP_STATUS_TSSOVF_Pos (0U)
\r
9103 #define ETH_TIMESTAMP_STATUS_TSSOVF_Msk (0x00000001U << ETH_TIMESTAMP_STATUS_TSSOVF_Pos)
\r
9105 #define ETH_TIMESTAMP_STATUS_TSTARGT_Pos (1U)
\r
9106 #define ETH_TIMESTAMP_STATUS_TSTARGT_Msk (0x00000001U << ETH_TIMESTAMP_STATUS_TSTARGT_Pos)
\r
9108 #define ETH_TIMESTAMP_STATUS_AUXTSTRIG_Pos (2U)
\r
9109 #define ETH_TIMESTAMP_STATUS_AUXTSTRIG_Msk (0x00000001U << ETH_TIMESTAMP_STATUS_AUXTSTRIG_Pos)
\r
9111 #define ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos (3U)
\r
9112 #define ETH_TIMESTAMP_STATUS_TSTRGTERR_Msk (0x00000001U << ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos)
\r
9114 #define ETH_TIMESTAMP_STATUS_TSTARGT1_Pos (4U)
\r
9115 #define ETH_TIMESTAMP_STATUS_TSTARGT1_Msk (0x00000001U << ETH_TIMESTAMP_STATUS_TSTARGT1_Pos)
\r
9117 #define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos (5U)
\r
9118 #define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Msk (0x00000001U << ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos)
\r
9120 #define ETH_TIMESTAMP_STATUS_TSTARGT2_Pos (6U)
\r
9121 #define ETH_TIMESTAMP_STATUS_TSTARGT2_Msk (0x00000001U << ETH_TIMESTAMP_STATUS_TSTARGT2_Pos)
\r
9123 #define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos (7U)
\r
9124 #define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Msk (0x00000001U << ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos)
\r
9126 #define ETH_TIMESTAMP_STATUS_TSTARGT3_Pos (8U)
\r
9127 #define ETH_TIMESTAMP_STATUS_TSTARGT3_Msk (0x00000001U << ETH_TIMESTAMP_STATUS_TSTARGT3_Pos)
\r
9129 #define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos (9U)
\r
9130 #define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Msk (0x00000001U << ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos)
\r
9132 #define ETH_TIMESTAMP_STATUS_Reserved_15_10_Pos (10U)
\r
9133 #define ETH_TIMESTAMP_STATUS_Reserved_15_10_Msk (0x0000003FU << ETH_TIMESTAMP_STATUS_Reserved_15_10_Pos)
\r
9135 #define ETH_TIMESTAMP_STATUS_ATSSTN_Pos (16U)
\r
9136 #define ETH_TIMESTAMP_STATUS_ATSSTN_Msk (0x0000000FU << ETH_TIMESTAMP_STATUS_ATSSTN_Pos)
\r
9138 #define ETH_TIMESTAMP_STATUS_Reserved_23_20_Pos (20U)
\r
9139 #define ETH_TIMESTAMP_STATUS_Reserved_23_20_Msk (0x0000000FU << ETH_TIMESTAMP_STATUS_Reserved_23_20_Pos)
\r
9141 #define ETH_TIMESTAMP_STATUS_ATSSTM_Pos (24U)
\r
9142 #define ETH_TIMESTAMP_STATUS_ATSSTM_Msk (0x00000001U << ETH_TIMESTAMP_STATUS_ATSSTM_Pos)
\r
9144 #define ETH_TIMESTAMP_STATUS_ATSNS_Pos (25U)
\r
9145 #define ETH_TIMESTAMP_STATUS_ATSNS_Msk (0x0000001FU << ETH_TIMESTAMP_STATUS_ATSNS_Pos)
\r
9147 #define ETH_TIMESTAMP_STATUS_Reserved_31_30_Pos (30U)
\r
9148 #define ETH_TIMESTAMP_STATUS_Reserved_31_30_Msk (0x00000003U << ETH_TIMESTAMP_STATUS_Reserved_31_30_Pos)
\r
9150 /* ETH_PPS_CONTROL = Register 459 [PPS Control Register]*/
\r
9151 #define ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Pos (0U)
\r
9152 #define ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Msk (0x0000000FU << ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Pos)
\r
9154 #define ETH_PPS_CONTROL_PPSEN0_Pos (4U)
\r
9155 #define ETH_PPS_CONTROL_PPSEN0_Msk (0x00000001U << ETH_PPS_CONTROL_PPSEN0_Pos)
\r
9157 #define ETH_PPS_CONTROL_TRGTMODSEL0_Pos (5U)
\r
9158 #define ETH_PPS_CONTROL_TRGTMODSEL0_Msk (0x00000003U << ETH_PPS_CONTROL_TRGTMODSEL0_Pos)
\r
9160 #define ETH_PPS_CONTROL_Reserved_7_Pos (7U)
\r
9161 #define ETH_PPS_CONTROL_Reserved_7_Msk (0x00000001U << ETH_PPS_CONTROL_Reserved_7_Pos)
\r
9163 #define ETH_PPS_CONTROL_PPSCMD1_Pos (8U)
\r
9164 #define ETH_PPS_CONTROL_PPSCMD1_Msk (0x00000007U << ETH_PPS_CONTROL_PPSCMD1_Pos)
\r
9166 #define ETH_PPS_CONTROL_Reserved_12_11_Pos (11U)
\r
9167 #define ETH_PPS_CONTROL_Reserved_12_11_Msk (0x00000003U << ETH_PPS_CONTROL_Reserved_12_11_Pos)
\r
9169 #define ETH_PPS_CONTROL_TRGTMODSEL1_Pos (13U)
\r
9170 #define ETH_PPS_CONTROL_TRGTMODSEL1_Msk (0x00000003U << ETH_PPS_CONTROL_TRGTMODSEL1_Pos)
\r
9172 #define ETH_PPS_CONTROL_Reserved_15_Pos (15U)
\r
9173 #define ETH_PPS_CONTROL_Reserved_15_Msk (0x00000001U << ETH_PPS_CONTROL_Reserved_15_Pos)
\r
9175 #define ETH_PPS_CONTROL_PPSCMD2_Pos (16U)
\r
9176 #define ETH_PPS_CONTROL_PPSCMD2_Msk (0x00000007U << ETH_PPS_CONTROL_PPSCMD2_Pos)
\r
9178 #define ETH_PPS_CONTROL_Reserved_20_19_Pos (19U)
\r
9179 #define ETH_PPS_CONTROL_Reserved_20_19_Msk (0x00000003U << ETH_PPS_CONTROL_Reserved_20_19_Pos)
\r
9181 #define ETH_PPS_CONTROL_TRGTMODSEL2_Pos (21U)
\r
9182 #define ETH_PPS_CONTROL_TRGTMODSEL2_Msk (0x00000003U << ETH_PPS_CONTROL_TRGTMODSEL2_Pos)
\r
9184 #define ETH_PPS_CONTROL_Reserved_23_Pos (23U)
\r
9185 #define ETH_PPS_CONTROL_Reserved_23_Msk (0x00000001U << ETH_PPS_CONTROL_Reserved_23_Pos)
\r
9187 #define ETH_PPS_CONTROL_PPSCMD3_Pos (24U)
\r
9188 #define ETH_PPS_CONTROL_PPSCMD3_Msk (0x00000007U << ETH_PPS_CONTROL_PPSCMD3_Pos)
\r
9190 #define ETH_PPS_CONTROL_Reserved_28_27_Pos (27U)
\r
9191 #define ETH_PPS_CONTROL_Reserved_28_27_Msk (0x00000003U << ETH_PPS_CONTROL_Reserved_28_27_Pos)
\r
9193 #define ETH_PPS_CONTROL_TRGTMODSEL3_Pos (29U)
\r
9194 #define ETH_PPS_CONTROL_TRGTMODSEL3_Msk (0x00000003U << ETH_PPS_CONTROL_TRGTMODSEL3_Pos)
\r
9196 #define ETH_PPS_CONTROL_Reserved_31_Pos (31U)
\r
9197 #define ETH_PPS_CONTROL_Reserved_31_Msk (0x00000001U << ETH_PPS_CONTROL_Reserved_31_Pos)
\r
9199 /* ETH_BUS_MODE = Register x [Bus Mode Register]*/
\r
9200 #define ETH_BUS_MODE_SWR_Pos (0U)
\r
9201 #define ETH_BUS_MODE_SWR_Msk (0x00000001U << ETH_BUS_MODE_SWR_Pos)
\r
9203 #define ETH_BUS_MODE_DA_Pos (1U)
\r
9204 #define ETH_BUS_MODE_DA_Msk (0x00000001U << ETH_BUS_MODE_DA_Pos)
\r
9206 #define ETH_BUS_MODE_DSL_Pos (2U)
\r
9207 #define ETH_BUS_MODE_DSL_Msk (0x0000001FU << ETH_BUS_MODE_DSL_Pos)
\r
9209 #define ETH_BUS_MODE_Reserved_7_Pos (7U)
\r
9210 #define ETH_BUS_MODE_Reserved_7_Msk (0x00000001U << ETH_BUS_MODE_Reserved_7_Pos)
\r
9212 #define ETH_BUS_MODE_PBL_Pos (8U)
\r
9213 #define ETH_BUS_MODE_PBL_Msk (0x0000003FU << ETH_BUS_MODE_PBL_Pos)
\r
9215 #define ETH_BUS_MODE_PR_Pos (14U)
\r
9216 #define ETH_BUS_MODE_PR_Msk (0x00000003U << ETH_BUS_MODE_PR_Pos)
\r
9218 #define ETH_BUS_MODE_FB_Pos (16U)
\r
9219 #define ETH_BUS_MODE_FB_Msk (0x00000001U << ETH_BUS_MODE_FB_Pos)
\r
9221 #define ETH_BUS_MODE_RPBL_Pos (17U)
\r
9222 #define ETH_BUS_MODE_RPBL_Msk (0x0000003FU << ETH_BUS_MODE_RPBL_Pos)
\r
9224 #define ETH_BUS_MODE_USP_Pos (23U)
\r
9225 #define ETH_BUS_MODE_USP_Msk (0x00000001U << ETH_BUS_MODE_USP_Pos)
\r
9227 #define ETH_BUS_MODE_EIGHTxPBL_Pos (24U)
\r
9228 #define ETH_BUS_MODE_EIGHTxPBL_Msk (0x00000001U << ETH_BUS_MODE_EIGHTxPBL_Pos)
\r
9230 #define ETH_BUS_MODE_AAL_Pos (25U)
\r
9231 #define ETH_BUS_MODE_AAL_Msk (0x00000001U << ETH_BUS_MODE_AAL_Pos)
\r
9233 #define ETH_BUS_MODE_MB_Pos (26U)
\r
9234 #define ETH_BUS_MODE_MB_Msk (0x00000001U << ETH_BUS_MODE_MB_Pos)
\r
9236 #define ETH_BUS_MODE_TXPR_Pos (27U)
\r
9237 #define ETH_BUS_MODE_TXPR_Msk (0x00000001U << ETH_BUS_MODE_TXPR_Pos)
\r
9239 #define ETH_BUS_MODE_PRWG_Pos (28U)
\r
9240 #define ETH_BUS_MODE_PRWG_Msk (0x00000003U << ETH_BUS_MODE_PRWG_Pos)
\r
9242 #define ETH_BUS_MODE_Reserved_31_30_Pos (30U)
\r
9243 #define ETH_BUS_MODE_Reserved_31_30_Msk (0x00000003U << ETH_BUS_MODE_Reserved_31_30_Pos)
\r
9245 /* ETH_TRANSMIT_POLL_DEMAND = Register 1 [Transmit Poll Demand Register]*/
\r
9246 #define ETH_TRANSMIT_POLL_DEMAND_TPD_Pos (0U)
\r
9247 #define ETH_TRANSMIT_POLL_DEMAND_TPD_Msk (0xFFFFFFFFU << ETH_TRANSMIT_POLL_DEMAND_TPD_Pos)
\r
9249 /* ETH_RECEIVE_POLL_DEMAND = */
\r
9250 #define ETH_RECEIVE_POLL_DEMAND_RPD_Pos (0U)
\r
9251 #define ETH_RECEIVE_POLL_DEMAND_RPD_Msk (0xFFFFFFFFU << ETH_RECEIVE_POLL_DEMAND_RPD_Pos)
\r
9253 /* ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS = */
\r
9254 #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos (0U)
\r
9255 #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Msk (0x00000003U << ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos)
\r
9257 #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos (2U)
\r
9258 #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Msk (0x3FFFFFFFU << ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos)
\r
9260 /* ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS = */
\r
9261 #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos (0U)
\r
9262 #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Msk (0x00000003U << ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos)
\r
9264 #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos (2U)
\r
9265 #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Msk (0x3FFFFFFFU << ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos)
\r
9267 /* ETH_STATUS = */
\r
9268 #define ETH_STATUS_TI_Pos (0U)
\r
9269 #define ETH_STATUS_TI_Msk (0x00000001U << ETH_STATUS_TI_Pos)
\r
9271 #define ETH_STATUS_TPS_Pos (1U)
\r
9272 #define ETH_STATUS_TPS_Msk (0x00000001U << ETH_STATUS_TPS_Pos)
\r
9274 #define ETH_STATUS_TU_Pos (2U)
\r
9275 #define ETH_STATUS_TU_Msk (0x00000001U << ETH_STATUS_TU_Pos)
\r
9277 #define ETH_STATUS_TJT_Pos (3U)
\r
9278 #define ETH_STATUS_TJT_Msk (0x00000001U << ETH_STATUS_TJT_Pos)
\r
9280 #define ETH_STATUS_OVF_Pos (4U)
\r
9281 #define ETH_STATUS_OVF_Msk (0x00000001U << ETH_STATUS_OVF_Pos)
\r
9283 #define ETH_STATUS_UNF_Pos (5U)
\r
9284 #define ETH_STATUS_UNF_Msk (0x00000001U << ETH_STATUS_UNF_Pos)
\r
9286 #define ETH_STATUS_RI_Pos (6U)
\r
9287 #define ETH_STATUS_RI_Msk (0x00000001U << ETH_STATUS_RI_Pos)
\r
9289 #define ETH_STATUS_RU_Pos (7U)
\r
9290 #define ETH_STATUS_RU_Msk (0x00000001U << ETH_STATUS_RU_Pos)
\r
9292 #define ETH_STATUS_RPS_Pos (8U)
\r
9293 #define ETH_STATUS_RPS_Msk (0x00000001U << ETH_STATUS_RPS_Pos)
\r
9295 #define ETH_STATUS_RWT_Pos (9U)
\r
9296 #define ETH_STATUS_RWT_Msk (0x00000001U << ETH_STATUS_RWT_Pos)
\r
9298 #define ETH_STATUS_ETI_Pos (10U)
\r
9299 #define ETH_STATUS_ETI_Msk (0x00000001U << ETH_STATUS_ETI_Pos)
\r
9301 #define ETH_STATUS_Reserved_12_11_Pos (11U)
\r
9302 #define ETH_STATUS_Reserved_12_11_Msk (0x00000003U << ETH_STATUS_Reserved_12_11_Pos)
\r
9304 #define ETH_STATUS_FBI_Pos (13U)
\r
9305 #define ETH_STATUS_FBI_Msk (0x00000001U << ETH_STATUS_FBI_Pos)
\r
9307 #define ETH_STATUS_ERI_Pos (14U)
\r
9308 #define ETH_STATUS_ERI_Msk (0x00000001U << ETH_STATUS_ERI_Pos)
\r
9310 #define ETH_STATUS_AIS_Pos (15U)
\r
9311 #define ETH_STATUS_AIS_Msk (0x00000001U << ETH_STATUS_AIS_Pos)
\r
9313 #define ETH_STATUS_NIS_Pos (16U)
\r
9314 #define ETH_STATUS_NIS_Msk (0x00000001U << ETH_STATUS_NIS_Pos)
\r
9316 #define ETH_STATUS_RS_Pos (17U)
\r
9317 #define ETH_STATUS_RS_Msk (0x00000007U << ETH_STATUS_RS_Pos)
\r
9319 #define ETH_STATUS_TS_Pos (20U)
\r
9320 #define ETH_STATUS_TS_Msk (0x00000007U << ETH_STATUS_TS_Pos)
\r
9322 #define ETH_STATUS_EB_Pos (23U)
\r
9323 #define ETH_STATUS_EB_Msk (0x00000007U << ETH_STATUS_EB_Pos)
\r
9325 #define ETH_STATUS_MLI_Pos (26U)
\r
9326 #define ETH_STATUS_MLI_Msk (0x00000001U << ETH_STATUS_MLI_Pos)
\r
9328 #define ETH_STATUS_EMI_Pos (27U)
\r
9329 #define ETH_STATUS_EMI_Msk (0x00000001U << ETH_STATUS_EMI_Pos)
\r
9331 #define ETH_STATUS_EPI_Pos (28U)
\r
9332 #define ETH_STATUS_EPI_Msk (0x00000001U << ETH_STATUS_EPI_Pos)
\r
9334 #define ETH_STATUS_TTI_Pos (29U)
\r
9335 #define ETH_STATUS_TTI_Msk (0x00000001U << ETH_STATUS_TTI_Pos)
\r
9337 #define ETH_STATUS_ELPII_Pos (30U)
\r
9338 #define ETH_STATUS_ELPII_Msk (0x00000001U << ETH_STATUS_ELPII_Pos)
\r
9340 #define ETH_STATUS_Reserved_31_Pos (31U)
\r
9341 #define ETH_STATUS_Reserved_31_Msk (0x00000001U << ETH_STATUS_Reserved_31_Pos)
\r
9343 /* ETH_OPERATION_MODE = Register 6 [Operation Mode Register]*/
\r
9344 #define ETH_OPERATION_MODE_Reserved_0_Pos (0U)
\r
9345 #define ETH_OPERATION_MODE_Reserved_0_Msk (0x00000001U << ETH_OPERATION_MODE_Reserved_0_Pos)
\r
9347 #define ETH_OPERATION_MODE_SR_Pos (1U)
\r
9348 #define ETH_OPERATION_MODE_SR_Msk (0x00000001U << ETH_OPERATION_MODE_SR_Pos)
\r
9350 #define ETH_OPERATION_MODE_OSF_Pos (2U)
\r
9351 #define ETH_OPERATION_MODE_OSF_Msk (0x00000001U << ETH_OPERATION_MODE_OSF_Pos)
\r
9353 #define ETH_OPERATION_MODE_RTC_Pos (3U)
\r
9354 #define ETH_OPERATION_MODE_RTC_Msk (0x00000003U << ETH_OPERATION_MODE_RTC_Pos)
\r
9356 #define ETH_OPERATION_MODE_Reserved_5_Pos (5U)
\r
9357 #define ETH_OPERATION_MODE_Reserved_5_Msk (0x00000001U << ETH_OPERATION_MODE_Reserved_5_Pos)
\r
9359 #define ETH_OPERATION_MODE_FUF_Pos (6U)
\r
9360 #define ETH_OPERATION_MODE_FUF_Msk (0x00000001U << ETH_OPERATION_MODE_FUF_Pos)
\r
9362 #define ETH_OPERATION_MODE_FEF_Pos (7U)
\r
9363 #define ETH_OPERATION_MODE_FEF_Msk (0x00000001U << ETH_OPERATION_MODE_FEF_Pos)
\r
9365 #define ETH_OPERATION_MODE_EFC_Pos (8U)
\r
9366 #define ETH_OPERATION_MODE_EFC_Msk (0x00000001U << ETH_OPERATION_MODE_EFC_Pos)
\r
9368 #define ETH_OPERATION_MODE_RFA_Pos (9U)
\r
9369 #define ETH_OPERATION_MODE_RFA_Msk (0x00000003U << ETH_OPERATION_MODE_RFA_Pos)
\r
9371 #define ETH_OPERATION_MODE_RFD_Pos (11U)
\r
9372 #define ETH_OPERATION_MODE_RFD_Msk (0x00000003U << ETH_OPERATION_MODE_RFD_Pos)
\r
9374 #define ETH_OPERATION_MODE_ST_Pos (13U)
\r
9375 #define ETH_OPERATION_MODE_ST_Msk (0x00000001U << ETH_OPERATION_MODE_ST_Pos)
\r
9377 #define ETH_OPERATION_MODE_TTC_Pos (14U)
\r
9378 #define ETH_OPERATION_MODE_TTC_Msk (0x00000007U << ETH_OPERATION_MODE_TTC_Pos)
\r
9380 #define ETH_OPERATION_MODE_Reserved_19_17_Pos (17U)
\r
9381 #define ETH_OPERATION_MODE_Reserved_19_17_Msk (0x00000007U << ETH_OPERATION_MODE_Reserved_19_17_Pos)
\r
9383 #define ETH_OPERATION_MODE_FTF_Pos (20U)
\r
9384 #define ETH_OPERATION_MODE_FTF_Msk (0x00000001U << ETH_OPERATION_MODE_FTF_Pos)
\r
9386 #define ETH_OPERATION_MODE_TSF_Pos (21U)
\r
9387 #define ETH_OPERATION_MODE_TSF_Msk (0x00000001U << ETH_OPERATION_MODE_TSF_Pos)
\r
9389 #define ETH_OPERATION_MODE_RFD2_Pos (22U)
\r
9390 #define ETH_OPERATION_MODE_RFD2_Msk (0x00000001U << ETH_OPERATION_MODE_RFD2_Pos)
\r
9392 #define ETH_OPERATION_MODE_RFA2_Pos (23U)
\r
9393 #define ETH_OPERATION_MODE_RFA2_Msk (0x00000001U << ETH_OPERATION_MODE_RFA2_Pos)
\r
9395 #define ETH_OPERATION_MODE_DFF_Pos (24U)
\r
9396 #define ETH_OPERATION_MODE_DFF_Msk (0x00000001U << ETH_OPERATION_MODE_DFF_Pos)
\r
9398 #define ETH_OPERATION_MODE_RSF_Pos (25U)
\r
9399 #define ETH_OPERATION_MODE_RSF_Msk (0x00000001U << ETH_OPERATION_MODE_RSF_Pos)
\r
9401 #define ETH_OPERATION_MODE_DT_Pos (26U)
\r
9402 #define ETH_OPERATION_MODE_DT_Msk (0x00000001U << ETH_OPERATION_MODE_DT_Pos)
\r
9404 #define ETH_OPERATION_MODE_Reserved_31_27_Pos (27U)
\r
9405 #define ETH_OPERATION_MODE_Reserved_31_27_Msk (0x0000001FU << ETH_OPERATION_MODE_Reserved_31_27_Pos)
\r
9407 /* ETH_INTERRUPT_ENABLE = Register 7 [Interrupt Enable Register]*/
\r
9408 #define ETH_INTERRUPT_ENABLE_TIE_Pos (0U)
\r
9409 #define ETH_INTERRUPT_ENABLE_TIE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_TIE_Pos)
\r
9411 #define ETH_INTERRUPT_ENABLE_TSE_Pos (1U)
\r
9412 #define ETH_INTERRUPT_ENABLE_TSE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_TSE_Pos)
\r
9414 #define ETH_INTERRUPT_ENABLE_TUE_Pos (2U)
\r
9415 #define ETH_INTERRUPT_ENABLE_TUE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_TUE_Pos)
\r
9417 #define ETH_INTERRUPT_ENABLE_TJE_Pos (3U)
\r
9418 #define ETH_INTERRUPT_ENABLE_TJE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_TJE_Pos)
\r
9420 #define ETH_INTERRUPT_ENABLE_OVE_Pos (4U)
\r
9421 #define ETH_INTERRUPT_ENABLE_OVE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_OVE_Pos)
\r
9423 #define ETH_INTERRUPT_ENABLE_UNE_Pos (5U)
\r
9424 #define ETH_INTERRUPT_ENABLE_UNE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_UNE_Pos)
\r
9426 #define ETH_INTERRUPT_ENABLE_RIE_Pos (6U)
\r
9427 #define ETH_INTERRUPT_ENABLE_RIE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_RIE_Pos)
\r
9429 #define ETH_INTERRUPT_ENABLE_RUE_Pos (7U)
\r
9430 #define ETH_INTERRUPT_ENABLE_RUE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_RUE_Pos)
\r
9432 #define ETH_INTERRUPT_ENABLE_RSE_Pos (8U)
\r
9433 #define ETH_INTERRUPT_ENABLE_RSE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_RSE_Pos)
\r
9435 #define ETH_INTERRUPT_ENABLE_RWE_Pos (9U)
\r
9436 #define ETH_INTERRUPT_ENABLE_RWE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_RWE_Pos)
\r
9438 #define ETH_INTERRUPT_ENABLE_ETE_Pos (10U)
\r
9439 #define ETH_INTERRUPT_ENABLE_ETE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_ETE_Pos)
\r
9441 #define ETH_INTERRUPT_ENABLE_Reserved_12_11_Pos (11U)
\r
9442 #define ETH_INTERRUPT_ENABLE_Reserved_12_11_Msk (0x00000003U << ETH_INTERRUPT_ENABLE_Reserved_12_11_Pos)
\r
9444 #define ETH_INTERRUPT_ENABLE_FBE_Pos (13U)
\r
9445 #define ETH_INTERRUPT_ENABLE_FBE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_FBE_Pos)
\r
9447 #define ETH_INTERRUPT_ENABLE_ERE_Pos (14U)
\r
9448 #define ETH_INTERRUPT_ENABLE_ERE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_ERE_Pos)
\r
9450 #define ETH_INTERRUPT_ENABLE_AIE_Pos (15U)
\r
9451 #define ETH_INTERRUPT_ENABLE_AIE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_AIE_Pos)
\r
9453 #define ETH_INTERRUPT_ENABLE_NIE_Pos (16U)
\r
9454 #define ETH_INTERRUPT_ENABLE_NIE_Msk (0x00000001U << ETH_INTERRUPT_ENABLE_NIE_Pos)
\r
9456 #define ETH_INTERRUPT_ENABLE_Reserved_31_17_Pos (17U)
\r
9457 #define ETH_INTERRUPT_ENABLE_Reserved_31_17_Msk (0x00007FFFU << ETH_INTERRUPT_ENABLE_Reserved_31_17_Pos)
\r
9459 /* ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER = */
\r
9460 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos (0U)
\r
9461 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Msk (0x0000FFFFU << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos)
\r
9463 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos (16U)
\r
9464 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Msk (0x00000001U << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos)
\r
9466 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos (17U)
\r
9467 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Msk (0x000007FFU << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos)
\r
9469 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos (28U)
\r
9470 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Msk (0x00000001U << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos)
\r
9472 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Pos (29U)
\r
9473 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Msk (0x00000007U << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Pos)
\r
9475 /* ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER = */
\r
9476 #define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos (0U)
\r
9477 #define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Msk (0x000000FFU << ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos)
\r
9479 #define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Pos (8U)
\r
9480 #define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Msk (0x00FFFFFFU << ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Pos)
\r
9482 /* ETH_AHB_STATUS = Register 11 [AHB Status Register]*/
\r
9483 #define ETH_AHB_STATUS_AHBMS_Pos (0U)
\r
9484 #define ETH_AHB_STATUS_AHBMS_Msk (0x00000001U << ETH_AHB_STATUS_AHBMS_Pos)
\r
9486 #define ETH_AHB_STATUS_Reserved_1_Pos (1U)
\r
9487 #define ETH_AHB_STATUS_Reserved_1_Msk (0x00000001U << ETH_AHB_STATUS_Reserved_1_Pos)
\r
9489 #define ETH_AHB_STATUS_Reserved_31_2_Pos (2U)
\r
9490 #define ETH_AHB_STATUS_Reserved_31_2_Msk (0x3FFFFFFFU << ETH_AHB_STATUS_Reserved_31_2_Pos)
\r
9492 /* ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR = */
\r
9493 #define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos (0U)
\r
9494 #define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Msk (0xFFFFFFFFU << ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos)
\r
9496 /* ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR = */
\r
9497 #define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos (0U)
\r
9498 #define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Msk (0xFFFFFFFFU << ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos)
\r
9500 /* ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS = Register 20 [Current Host Transmit Buffer Address Register]*/
\r
9501 #define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos (0U)
\r
9502 #define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Msk (0xFFFFFFFFU << ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos)
\r
9504 /* ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS = Register 21 [Current Host Receive Buffer Address Register]*/
\r
9505 #define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos (0U)
\r
9506 #define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Msk (0xFFFFFFFFU << ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos)
\r
9508 /* ETH_HW_FEATURE = Register 22 [HW Feature Register]*/
\r
9509 #define ETH_HW_FEATURE_MIISEL_Pos (0U)
\r
9510 #define ETH_HW_FEATURE_MIISEL_Msk (0x00000001U << ETH_HW_FEATURE_MIISEL_Pos)
\r
9512 #define ETH_HW_FEATURE_GMIISEL_Pos (1U)
\r
9513 #define ETH_HW_FEATURE_GMIISEL_Msk (0x00000001U << ETH_HW_FEATURE_GMIISEL_Pos)
\r
9515 #define ETH_HW_FEATURE_HDSEL_Pos (2U)
\r
9516 #define ETH_HW_FEATURE_HDSEL_Msk (0x00000001U << ETH_HW_FEATURE_HDSEL_Pos)
\r
9518 #define ETH_HW_FEATURE_EXTHASHEN_Pos (3U)
\r
9519 #define ETH_HW_FEATURE_EXTHASHEN_Msk (0x00000001U << ETH_HW_FEATURE_EXTHASHEN_Pos)
\r
9521 #define ETH_HW_FEATURE_HASHSEL_Pos (4U)
\r
9522 #define ETH_HW_FEATURE_HASHSEL_Msk (0x00000001U << ETH_HW_FEATURE_HASHSEL_Pos)
\r
9524 #define ETH_HW_FEATURE_ADDMACADRSEL_Pos (5U)
\r
9525 #define ETH_HW_FEATURE_ADDMACADRSEL_Msk (0x00000001U << ETH_HW_FEATURE_ADDMACADRSEL_Pos)
\r
9527 #define ETH_HW_FEATURE_PCSSEL_Pos (6U)
\r
9528 #define ETH_HW_FEATURE_PCSSEL_Msk (0x00000001U << ETH_HW_FEATURE_PCSSEL_Pos)
\r
9530 #define ETH_HW_FEATURE_L3L4FLTREN_Pos (7U)
\r
9531 #define ETH_HW_FEATURE_L3L4FLTREN_Msk (0x00000001U << ETH_HW_FEATURE_L3L4FLTREN_Pos)
\r
9533 #define ETH_HW_FEATURE_SMASEL_Pos (8U)
\r
9534 #define ETH_HW_FEATURE_SMASEL_Msk (0x00000001U << ETH_HW_FEATURE_SMASEL_Pos)
\r
9536 #define ETH_HW_FEATURE_RWKSEL_Pos (9U)
\r
9537 #define ETH_HW_FEATURE_RWKSEL_Msk (0x00000001U << ETH_HW_FEATURE_RWKSEL_Pos)
\r
9539 #define ETH_HW_FEATURE_MGKSEL_Pos (10U)
\r
9540 #define ETH_HW_FEATURE_MGKSEL_Msk (0x00000001U << ETH_HW_FEATURE_MGKSEL_Pos)
\r
9542 #define ETH_HW_FEATURE_MMCSEL_Pos (11U)
\r
9543 #define ETH_HW_FEATURE_MMCSEL_Msk (0x00000001U << ETH_HW_FEATURE_MMCSEL_Pos)
\r
9545 #define ETH_HW_FEATURE_TSVER1SEL_Pos (12U)
\r
9546 #define ETH_HW_FEATURE_TSVER1SEL_Msk (0x00000001U << ETH_HW_FEATURE_TSVER1SEL_Pos)
\r
9548 #define ETH_HW_FEATURE_TSVER2SEL_Pos (13U)
\r
9549 #define ETH_HW_FEATURE_TSVER2SEL_Msk (0x00000001U << ETH_HW_FEATURE_TSVER2SEL_Pos)
\r
9551 #define ETH_HW_FEATURE_EEESEL_Pos (14U)
\r
9552 #define ETH_HW_FEATURE_EEESEL_Msk (0x00000001U << ETH_HW_FEATURE_EEESEL_Pos)
\r
9554 #define ETH_HW_FEATURE_AVSEL_Pos (15U)
\r
9555 #define ETH_HW_FEATURE_AVSEL_Msk (0x00000001U << ETH_HW_FEATURE_AVSEL_Pos)
\r
9557 #define ETH_HW_FEATURE_TXCOESEL_Pos (16U)
\r
9558 #define ETH_HW_FEATURE_TXCOESEL_Msk (0x00000001U << ETH_HW_FEATURE_TXCOESEL_Pos)
\r
9560 #define ETH_HW_FEATURE_RXTYP1COE_Pos (17U)
\r
9561 #define ETH_HW_FEATURE_RXTYP1COE_Msk (0x00000001U << ETH_HW_FEATURE_RXTYP1COE_Pos)
\r
9563 #define ETH_HW_FEATURE_RXTYP2COE_Pos (18U)
\r
9564 #define ETH_HW_FEATURE_RXTYP2COE_Msk (0x00000001U << ETH_HW_FEATURE_RXTYP2COE_Pos)
\r
9566 #define ETH_HW_FEATURE_RXFIFOSIZE_Pos (19U)
\r
9567 #define ETH_HW_FEATURE_RXFIFOSIZE_Msk (0x00000001U << ETH_HW_FEATURE_RXFIFOSIZE_Pos)
\r
9569 #define ETH_HW_FEATURE_RXCHCNT_Pos (20U)
\r
9570 #define ETH_HW_FEATURE_RXCHCNT_Msk (0x00000003U << ETH_HW_FEATURE_RXCHCNT_Pos)
\r
9572 #define ETH_HW_FEATURE_TXCHCNT_Pos (22U)
\r
9573 #define ETH_HW_FEATURE_TXCHCNT_Msk (0x00000003U << ETH_HW_FEATURE_TXCHCNT_Pos)
\r
9575 #define ETH_HW_FEATURE_ENHDESSEL_Pos (24U)
\r
9576 #define ETH_HW_FEATURE_ENHDESSEL_Msk (0x00000001U << ETH_HW_FEATURE_ENHDESSEL_Pos)
\r
9578 #define ETH_HW_FEATURE_INTTSEN_Pos (25U)
\r
9579 #define ETH_HW_FEATURE_INTTSEN_Msk (0x00000001U << ETH_HW_FEATURE_INTTSEN_Pos)
\r
9581 #define ETH_HW_FEATURE_FLEXIPPSEN_Pos (26U)
\r
9582 #define ETH_HW_FEATURE_FLEXIPPSEN_Msk (0x00000001U << ETH_HW_FEATURE_FLEXIPPSEN_Pos)
\r
9584 #define ETH_HW_FEATURE_SAVLANINS_Pos (27U)
\r
9585 #define ETH_HW_FEATURE_SAVLANINS_Msk (0x00000001U << ETH_HW_FEATURE_SAVLANINS_Pos)
\r
9587 #define ETH_HW_FEATURE_ACTPHYIF_Pos (28U)
\r
9588 #define ETH_HW_FEATURE_ACTPHYIF_Msk (0x00000007U << ETH_HW_FEATURE_ACTPHYIF_Pos)
\r
9590 #define ETH_HW_FEATURE_Reserved_31_Pos (31U)
\r
9591 #define ETH_HW_FEATURE_Reserved_31_Msk (0x00000001U << ETH_HW_FEATURE_Reserved_31_Pos)
\r
9595 /*** ETH0_CON Bit Fileds *******************/
\r
9596 /***************************************************************************/
\r
9599 /* ETH0_CON = Ethernet x Port Control Register*/
\r
9600 #define ETH_CON_RXD0_Pos (0U)
\r
9601 #define ETH_CON_RXD0_Msk (0x00000003U << ETH_CON_RXD0_Pos)
\r
9603 #define ETH_CON_RXD1_Pos (2U)
\r
9604 #define ETH_CON_RXD1_Msk (0x00000003U << ETH_CON_RXD1_Pos)
\r
9606 #define ETH_CON_RXD2_Pos (4U)
\r
9607 #define ETH_CON_RXD2_Msk (0x00000003U << ETH_CON_RXD2_Pos)
\r
9609 #define ETH_CON_RXD3_Pos (6U)
\r
9610 #define ETH_CON_RXD3_Msk (0x00000003U << ETH_CON_RXD3_Pos)
\r
9612 #define ETH_CON_CLK_RMII_Pos (8U)
\r
9613 #define ETH_CON_CLK_RMII_Msk (0x00000003U << ETH_CON_CLK_RMII_Pos)
\r
9615 #define ETH_CON_CRS_DV_Pos (10U)
\r
9616 #define ETH_CON_CRS_DV_Msk (0x00000003U << ETH_CON_CRS_DV_Pos)
\r
9618 #define ETH_CON_CRS_Pos (12U)
\r
9619 #define ETH_CON_CRS_Msk (0x00000003U << ETH_CON_CRS_Pos)
\r
9621 #define ETH_CON_RXER_Pos (14U)
\r
9622 #define ETH_CON_RXER_Msk (0x00000003U << ETH_CON_RXER_Pos)
\r
9624 #define ETH_CON_COL_Pos (16U)
\r
9625 #define ETH_CON_COL_Msk (0x00000003U << ETH_CON_COL_Pos)
\r
9627 #define ETH_CON_CLK_TX_Pos (18U)
\r
9628 #define ETH_CON_CLK_TX_Msk (0x00000003U << ETH_CON_CLK_TX_Pos)
\r
9630 #define ETH_CON_MDIO_Pos (22U)
\r
9631 #define ETH_CON_MDIO_Msk (0x00000003U << ETH_CON_MDIO_Pos)
\r
9633 #define ETH_CON_INFSEL_Pos (26U)
\r
9634 #define ETH_CON_INFSEL_Msk (0x00000001U << ETH_CON_INFSEL_Pos)
\r
9638 /*** ETM Bit Fileds *******************/
\r
9639 /***************************************************************************/
\r
9642 // ---------------------------------------- ETM_ETMCR -------------------------------------------
\r
9643 #define ETM_ETMCR_ETM_PowerDown_Pos 0 /*!< ETM ETMCR: ETM_PowerDown Position */
\r
9644 #define ETM_ETMCR_ETM_PowerDown_Msk (0x01UL << ETM_ETMCR_ETM_PowerDown_Pos) /*!< ETM ETMCR: ETM_PowerDown Mask */
\r
9645 #define ETM_ETMCR_Reserved_Pos 1 /*!< ETM ETMCR: Reserved Position */
\r
9646 #define ETM_ETMCR_Reserved_Msk (0x07UL << ETM_ETMCR_Reserved_Pos) /*!< ETM ETMCR: Reserved Mask */
\r
9647 #define ETM_ETMCR_PortSize_2_0_Pos 4 /*!< ETM ETMCR: PortSize_2_0 Position */
\r
9648 #define ETM_ETMCR_PortSize_2_0_Msk (0x07UL << ETM_ETMCR_PortSize_2_0_Pos) /*!< ETM ETMCR: PortSize_2_0 Mask */
\r
9649 #define ETM_ETMCR_StallProcessor_Pos 7 /*!< ETM ETMCR: StallProcessor Position */
\r
9650 #define ETM_ETMCR_StallProcessor_Msk (0x01UL << ETM_ETMCR_StallProcessor_Pos) /*!< ETM ETMCR: StallProcessor Mask */
\r
9651 #define ETM_ETMCR_BranchOutput_Pos 8 /*!< ETM ETMCR: BranchOutput Position */
\r
9652 #define ETM_ETMCR_BranchOutput_Msk (0x01UL << ETM_ETMCR_BranchOutput_Pos) /*!< ETM ETMCR: BranchOutput Mask */
\r
9653 #define ETM_ETMCR_DebugRequestControl_Pos 9 /*!< ETM ETMCR: DebugRequestControl Position */
\r
9654 #define ETM_ETMCR_DebugRequestControl_Msk (0x01UL << ETM_ETMCR_DebugRequestControl_Pos) /*!< ETM ETMCR: DebugRequestControl Mask */
\r
9655 #define ETM_ETMCR_ETM_Programming_Pos 10 /*!< ETM ETMCR: ETM_Programming Position */
\r
9656 #define ETM_ETMCR_ETM_Programming_Msk (0x01UL << ETM_ETMCR_ETM_Programming_Pos) /*!< ETM ETMCR: ETM_Programming Mask */
\r
9657 #define ETM_ETMCR_ETM_PortSelection_Pos 11 /*!< ETM ETMCR: ETM_PortSelection Position */
\r
9658 #define ETM_ETMCR_ETM_PortSelection_Msk (0x01UL << ETM_ETMCR_ETM_PortSelection_Pos) /*!< ETM ETMCR: ETM_PortSelection Mask */
\r
9659 #define ETM_ETMCR_Reserved1_Pos 12 /*!< ETM ETMCR: Reserved1 Position */
\r
9660 #define ETM_ETMCR_Reserved1_Msk (0x01UL << ETM_ETMCR_Reserved1_Pos) /*!< ETM ETMCR: Reserved1 Mask */
\r
9661 #define ETM_ETMCR_PortMode_2_Pos 13 /*!< ETM ETMCR: PortMode_2 Position */
\r
9662 #define ETM_ETMCR_PortMode_2_Msk (0x01UL << ETM_ETMCR_PortMode_2_Pos) /*!< ETM ETMCR: PortMode_2 Mask */
\r
9663 #define ETM_ETMCR_Reserved2_Pos 14 /*!< ETM ETMCR: Reserved2 Position */
\r
9664 #define ETM_ETMCR_Reserved2_Msk (0x03UL << ETM_ETMCR_Reserved2_Pos) /*!< ETM ETMCR: Reserved2 Mask */
\r
9665 #define ETM_ETMCR_PortMode_1_0_Pos 16 /*!< ETM ETMCR: PortMode_1_0 Position */
\r
9666 #define ETM_ETMCR_PortMode_1_0_Msk (0x03UL << ETM_ETMCR_PortMode_1_0_Pos) /*!< ETM ETMCR: PortMode_1_0 Mask */
\r
9667 #define ETM_ETMCR_Reserved3_Pos 18 /*!< ETM ETMCR: Reserved3 Position */
\r
9668 #define ETM_ETMCR_Reserved3_Msk (0x07UL << ETM_ETMCR_Reserved3_Pos) /*!< ETM ETMCR: Reserved3 Mask */
\r
9669 #define ETM_ETMCR_PortSize_3_Pos 21 /*!< ETM ETMCR: PortSize_3 Position */
\r
9670 #define ETM_ETMCR_PortSize_3_Msk (0x01UL << ETM_ETMCR_PortSize_3_Pos) /*!< ETM ETMCR: PortSize_3 Mask */
\r
9671 #define ETM_ETMCR_Reserved4_Pos 22 /*!< ETM ETMCR: Reserved4 Position */
\r
9672 #define ETM_ETMCR_Reserved4_Msk (0x3fUL << ETM_ETMCR_Reserved4_Pos) /*!< ETM ETMCR: Reserved4 Mask */
\r
9673 #define ETM_ETMCR_Timestamp_Pos 28 /*!< ETM ETMCR: Timestamp Position */
\r
9674 #define ETM_ETMCR_Timestamp_Msk (0x01UL << ETM_ETMCR_Timestamp_Pos) /*!< ETM ETMCR: Timestamp Mask */
\r
9675 #define ETM_ETMCR_Reserved5_Pos 29 /*!< ETM ETMCR: Reserved5 Position */
\r
9676 #define ETM_ETMCR_Reserved5_Msk (0x07UL << ETM_ETMCR_Reserved5_Pos) /*!< ETM ETMCR: Reserved5 Mask */
\r
9678 // --------------------------------------- ETM_ETMCCR -------------------------------------------
\r
9679 #define ETM_ETMCCR_NumberOfAddressComparatorPairs_Pos 0 /*!< ETM ETMCCR: NumberOfAddressComparatorPairs Position */
\r
9680 #define ETM_ETMCCR_NumberOfAddressComparatorPairs_Msk (0x0fUL << ETM_ETMCCR_NumberOfAddressComparatorPairs_Pos) /*!< ETM ETMCCR: NumberOfAddressComparatorPairs Mask */
\r
9681 #define ETM_ETMCCR_NumberOfDataValueComparators_Pos 4 /*!< ETM ETMCCR: NumberOfDataValueComparators Position */
\r
9682 #define ETM_ETMCCR_NumberOfDataValueComparators_Msk (0x0fUL << ETM_ETMCCR_NumberOfDataValueComparators_Pos) /*!< ETM ETMCCR: NumberOfDataValueComparators Mask */
\r
9683 #define ETM_ETMCCR_NumberOfMemoryMapDecoders_Pos 8 /*!< ETM ETMCCR: NumberOfMemoryMapDecoders Position */
\r
9684 #define ETM_ETMCCR_NumberOfMemoryMapDecoders_Msk (0x1fUL << ETM_ETMCCR_NumberOfMemoryMapDecoders_Pos) /*!< ETM ETMCCR: NumberOfMemoryMapDecoders Mask */
\r
9685 #define ETM_ETMCCR_NumberOfCounters_Pos 13 /*!< ETM ETMCCR: NumberOfCounters Position */
\r
9686 #define ETM_ETMCCR_NumberOfCounters_Msk (0x07UL << ETM_ETMCCR_NumberOfCounters_Pos) /*!< ETM ETMCCR: NumberOfCounters Mask */
\r
9687 #define ETM_ETMCCR_SequencerPresent_Pos 16 /*!< ETM ETMCCR: SequencerPresent Position */
\r
9688 #define ETM_ETMCCR_SequencerPresent_Msk (0x01UL << ETM_ETMCCR_SequencerPresent_Pos) /*!< ETM ETMCCR: SequencerPresent Mask */
\r
9689 #define ETM_ETMCCR_NumberOfExternalIinputs_Pos 17 /*!< ETM ETMCCR: NumberOfExternalIinputs Position */
\r
9690 #define ETM_ETMCCR_NumberOfExternalIinputs_Msk (0x07UL << ETM_ETMCCR_NumberOfExternalIinputs_Pos) /*!< ETM ETMCCR: NumberOfExternalIinputs Mask */
\r
9691 #define ETM_ETMCCR_NumberOfExternalOutputs_Pos 20 /*!< ETM ETMCCR: NumberOfExternalOutputs Position */
\r
9692 #define ETM_ETMCCR_NumberOfExternalOutputs_Msk (0x07UL << ETM_ETMCCR_NumberOfExternalOutputs_Pos) /*!< ETM ETMCCR: NumberOfExternalOutputs Mask */
\r
9693 #define ETM_ETMCCR_FIFOFULL_LogicPresent_Pos 23 /*!< ETM ETMCCR: FIFOFULL_LogicPresent Position */
\r
9694 #define ETM_ETMCCR_FIFOFULL_LogicPresent_Msk (0x01UL << ETM_ETMCCR_FIFOFULL_LogicPresent_Pos) /*!< ETM ETMCCR: FIFOFULL_LogicPresent Mask */
\r
9695 #define ETM_ETMCCR_NumberOfContextID_Comparators_Pos 24 /*!< ETM ETMCCR: NumberOfContextID_Comparators Position */
\r
9696 #define ETM_ETMCCR_NumberOfContextID_Comparators_Msk (0x03UL << ETM_ETMCCR_NumberOfContextID_Comparators_Pos) /*!< ETM ETMCCR: NumberOfContextID_Comparators Mask */
\r
9697 #define ETM_ETMCCR_TraceStartStopBlockPresent_Pos 26 /*!< ETM ETMCCR: TraceStartStopBlockPresent Position */
\r
9698 #define ETM_ETMCCR_TraceStartStopBlockPresent_Msk (0x01UL << ETM_ETMCCR_TraceStartStopBlockPresent_Pos) /*!< ETM ETMCCR: TraceStartStopBlockPresent Mask */
\r
9699 #define ETM_ETMCCR_CoprocessorAndMemoryAccess_Pos 27 /*!< ETM ETMCCR: CoprocessorAndMemoryAccess Position */
\r
9700 #define ETM_ETMCCR_CoprocessorAndMemoryAccess_Msk (0x01UL << ETM_ETMCCR_CoprocessorAndMemoryAccess_Pos) /*!< ETM ETMCCR: CoprocessorAndMemoryAccess Mask */
\r
9701 #define ETM_ETMCCR_Reserved_Pos 28 /*!< ETM ETMCCR: Reserved Position */
\r
9702 #define ETM_ETMCCR_Reserved_Msk (0x07UL << ETM_ETMCCR_Reserved_Pos) /*!< ETM ETMCCR: Reserved Mask */
\r
9703 #define ETM_ETMCCR_ETM_ID_RegisterPresent_Pos 31 /*!< ETM ETMCCR: ETM_ID_RegisterPresent Position */
\r
9704 #define ETM_ETMCCR_ETM_ID_RegisterPresent_Msk (0x01UL << ETM_ETMCCR_ETM_ID_RegisterPresent_Pos) /*!< ETM ETMCCR: ETM_ID_RegisterPresent Mask */
\r
9706 // ------------------------------------- ETM_ETMTRIGGER -----------------------------------------
\r
9707 #define ETM_ETMTRIGGER_ResourceA_Pos 0 /*!< ETM ETMTRIGGER: ResourceA Position */
\r
9708 #define ETM_ETMTRIGGER_ResourceA_Msk (0x7fUL << ETM_ETMTRIGGER_ResourceA_Pos) /*!< ETM ETMTRIGGER: ResourceA Mask */
\r
9709 #define ETM_ETMTRIGGER_ResourceB_Pos 7 /*!< ETM ETMTRIGGER: ResourceB Position */
\r
9710 #define ETM_ETMTRIGGER_ResourceB_Msk (0x7fUL << ETM_ETMTRIGGER_ResourceB_Pos) /*!< ETM ETMTRIGGER: ResourceB Mask */
\r
9711 #define ETM_ETMTRIGGER_Function_Pos 14 /*!< ETM ETMTRIGGER: Function Position */
\r
9712 #define ETM_ETMTRIGGER_Function_Msk (0x07UL << ETM_ETMTRIGGER_Function_Pos) /*!< ETM ETMTRIGGER: Function Mask */
\r
9713 #define ETM_ETMTRIGGER_Reserved_Pos 17 /*!< ETM ETMTRIGGER: Reserved Position */
\r
9714 #define ETM_ETMTRIGGER_Reserved_Msk (0x00007fffUL << ETM_ETMTRIGGER_Reserved_Pos) /*!< ETM ETMTRIGGER: Reserved Mask */
\r
9716 // ---------------------------------------- ETM_ETMSR -------------------------------------------
\r
9717 #define ETM_ETMSR_UntracedOverflowFlag_Pos 0 /*!< ETM ETMSR: UntracedOverflowFlag Position */
\r
9718 #define ETM_ETMSR_UntracedOverflowFlag_Msk (0x01UL << ETM_ETMSR_UntracedOverflowFlag_Pos) /*!< ETM ETMSR: UntracedOverflowFlag Mask */
\r
9719 #define ETM_ETMSR_Progbit_Pos 1 /*!< ETM ETMSR: Progbit Position */
\r
9720 #define ETM_ETMSR_Progbit_Msk (0x01UL << ETM_ETMSR_Progbit_Pos) /*!< ETM ETMSR: Progbit Mask */
\r
9721 #define ETM_ETMSR_TraceStartStopResourceStatus_Pos 2 /*!< ETM ETMSR: TraceStartStopResourceStatus Position */
\r
9722 #define ETM_ETMSR_TraceStartStopResourceStatus_Msk (0x01UL << ETM_ETMSR_TraceStartStopResourceStatus_Pos) /*!< ETM ETMSR: TraceStartStopResourceStatus Mask */
\r
9723 #define ETM_ETMSR_TriggerFlag_Pos 3 /*!< ETM ETMSR: TriggerFlag Position */
\r
9724 #define ETM_ETMSR_TriggerFlag_Msk (0x01UL << ETM_ETMSR_TriggerFlag_Pos) /*!< ETM ETMSR: TriggerFlag Mask */
\r
9725 #define ETM_ETMSR_Reserved_Pos 4 /*!< ETM ETMSR: Reserved Position */
\r
9726 #define ETM_ETMSR_Reserved_Msk (0x0fffffffUL << ETM_ETMSR_Reserved_Pos) /*!< ETM ETMSR: Reserved Mask */
\r
9728 // --------------------------------------- ETM_ETMSCR -------------------------------------------
\r
9729 #define ETM_ETMSCR_MaximumPortSize_2_0_Pos 0 /*!< ETM ETMSCR: MaximumPortSize_2_0 Position */
\r
9730 #define ETM_ETMSCR_MaximumPortSize_2_0_Msk (0x07UL << ETM_ETMSCR_MaximumPortSize_2_0_Pos) /*!< ETM ETMSCR: MaximumPortSize_2_0 Mask */
\r
9731 #define ETM_ETMSCR_Reserved_Pos 3 /*!< ETM ETMSCR: Reserved Position */
\r
9732 #define ETM_ETMSCR_Reserved_Msk (0x01UL << ETM_ETMSCR_Reserved_Pos) /*!< ETM ETMSCR: Reserved Mask */
\r
9733 #define ETM_ETMSCR_Reserved1_Pos 4 /*!< ETM ETMSCR: Reserved1 Position */
\r
9734 #define ETM_ETMSCR_Reserved1_Msk (0x0fUL << ETM_ETMSCR_Reserved1_Pos) /*!< ETM ETMSCR: Reserved1 Mask */
\r
9735 #define ETM_ETMSCR_FIFOFULL_Supported_Pos 8 /*!< ETM ETMSCR: FIFOFULL_Supported Position */
\r
9736 #define ETM_ETMSCR_FIFOFULL_Supported_Msk (0x01UL << ETM_ETMSCR_FIFOFULL_Supported_Pos) /*!< ETM ETMSCR: FIFOFULL_Supported Mask */
\r
9737 #define ETM_ETMSCR_MaximumPortSize_3_Pos 9 /*!< ETM ETMSCR: MaximumPortSize_3 Position */
\r
9738 #define ETM_ETMSCR_MaximumPortSize_3_Msk (0x01UL << ETM_ETMSCR_MaximumPortSize_3_Pos) /*!< ETM ETMSCR: MaximumPortSize_3 Mask */
\r
9739 #define ETM_ETMSCR_PortSizeSupported_Pos 10 /*!< ETM ETMSCR: PortSizeSupported Position */
\r
9740 #define ETM_ETMSCR_PortSizeSupported_Msk (0x01UL << ETM_ETMSCR_PortSizeSupported_Pos) /*!< ETM ETMSCR: PortSizeSupported Mask */
\r
9741 #define ETM_ETMSCR_PortModeSupported_Pos 11 /*!< ETM ETMSCR: PortModeSupported Position */
\r
9742 #define ETM_ETMSCR_PortModeSupported_Msk (0x01UL << ETM_ETMSCR_PortModeSupported_Pos) /*!< ETM ETMSCR: PortModeSupported Mask */
\r
9743 #define ETM_ETMSCR_N_Minus_1_Pos 12 /*!< ETM ETMSCR: N_Minus_1 Position */
\r
9744 #define ETM_ETMSCR_N_Minus_1_Msk (0x07UL << ETM_ETMSCR_N_Minus_1_Pos) /*!< ETM ETMSCR: N_Minus_1 Mask */
\r
9745 #define ETM_ETMSCR_Reserved2_Pos 15 /*!< ETM ETMSCR: Reserved2 Position */
\r
9746 #define ETM_ETMSCR_Reserved2_Msk (0x03UL << ETM_ETMSCR_Reserved2_Pos) /*!< ETM ETMSCR: Reserved2 Mask */
\r
9747 #define ETM_ETMSCR_NoFetchComparisons_Pos 17 /*!< ETM ETMSCR: NoFetchComparisons Position */
\r
9748 #define ETM_ETMSCR_NoFetchComparisons_Msk (0x01UL << ETM_ETMSCR_NoFetchComparisons_Pos) /*!< ETM ETMSCR: NoFetchComparisons Mask */
\r
9749 #define ETM_ETMSCR_Reserved3_Pos 18 /*!< ETM ETMSCR: Reserved3 Position */
\r
9750 #define ETM_ETMSCR_Reserved3_Msk (0x00003fffUL << ETM_ETMSCR_Reserved3_Pos) /*!< ETM ETMSCR: Reserved3 Mask */
\r
9752 // -------------------------------------- ETM_ETMTEEVR ------------------------------------------
\r
9753 #define ETM_ETMTEEVR_ResourceA_Pos 0 /*!< ETM ETMTEEVR: ResourceA Position */
\r
9754 #define ETM_ETMTEEVR_ResourceA_Msk (0x7fUL << ETM_ETMTEEVR_ResourceA_Pos) /*!< ETM ETMTEEVR: ResourceA Mask */
\r
9755 #define ETM_ETMTEEVR_ResourceB_Pos 7 /*!< ETM ETMTEEVR: ResourceB Position */
\r
9756 #define ETM_ETMTEEVR_ResourceB_Msk (0x7fUL << ETM_ETMTEEVR_ResourceB_Pos) /*!< ETM ETMTEEVR: ResourceB Mask */
\r
9757 #define ETM_ETMTEEVR_Function_Pos 14 /*!< ETM ETMTEEVR: Function Position */
\r
9758 #define ETM_ETMTEEVR_Function_Msk (0x07UL << ETM_ETMTEEVR_Function_Pos) /*!< ETM ETMTEEVR: Function Mask */
\r
9759 #define ETM_ETMTEEVR_Reserved_Pos 17 /*!< ETM ETMTEEVR: Reserved Position */
\r
9760 #define ETM_ETMTEEVR_Reserved_Msk (0x00007fffUL << ETM_ETMTEEVR_Reserved_Pos) /*!< ETM ETMTEEVR: Reserved Mask */
\r
9762 // -------------------------------------- ETM_ETMTECR1 ------------------------------------------
\r
9763 #define ETM_ETMTECR1_Reserved_Pos 0 /*!< ETM ETMTECR1: Reserved Position */
\r
9764 #define ETM_ETMTECR1_Reserved_Msk (0x01ffffffUL << ETM_ETMTECR1_Reserved_Pos) /*!< ETM ETMTECR1: Reserved Mask */
\r
9765 #define ETM_ETMTECR1_TraceStartStopEnable_Pos 25 /*!< ETM ETMTECR1: TraceStartStopEnable Position */
\r
9766 #define ETM_ETMTECR1_TraceStartStopEnable_Msk (0x01UL << ETM_ETMTECR1_TraceStartStopEnable_Pos) /*!< ETM ETMTECR1: TraceStartStopEnable Mask */
\r
9767 #define ETM_ETMTECR1_Reserved1_Pos 26 /*!< ETM ETMTECR1: Reserved1 Position */
\r
9768 #define ETM_ETMTECR1_Reserved1_Msk (0x3fUL << ETM_ETMTECR1_Reserved1_Pos) /*!< ETM ETMTECR1: Reserved1 Mask */
\r
9770 // --------------------------------------- ETM_ETMFFLR ------------------------------------------
\r
9771 #define ETM_ETMFFLR_FIFO_FullLevel_Pos 0 /*!< ETM ETMFFLR: FIFO_FullLevel Position */
\r
9772 #define ETM_ETMFFLR_FIFO_FullLevel_Msk (0x000000ffUL << ETM_ETMFFLR_FIFO_FullLevel_Pos) /*!< ETM ETMFFLR: FIFO_FullLevel Mask */
\r
9773 #define ETM_ETMFFLR_Reserved_Pos 8 /*!< ETM ETMFFLR: Reserved Position */
\r
9774 #define ETM_ETMFFLR_Reserved_Msk (0x00ffffffUL << ETM_ETMFFLR_Reserved_Pos) /*!< ETM ETMFFLR: Reserved Mask */
\r
9776 // ------------------------------------ ETM_ETMCNTRLDVR1 ----------------------------------------
\r
9777 #define ETM_ETMCNTRLDVR1_InitialCount_Pos 0 /*!< ETM ETMCNTRLDVR1: InitialCount Position */
\r
9778 #define ETM_ETMCNTRLDVR1_InitialCount_Msk (0x0000ffffUL << ETM_ETMCNTRLDVR1_InitialCount_Pos) /*!< ETM ETMCNTRLDVR1: InitialCount Mask */
\r
9779 #define ETM_ETMCNTRLDVR1_Reserved_Pos 16 /*!< ETM ETMCNTRLDVR1: Reserved Position */
\r
9780 #define ETM_ETMCNTRLDVR1_Reserved_Msk (0x0000ffffUL << ETM_ETMCNTRLDVR1_Reserved_Pos) /*!< ETM ETMCNTRLDVR1: Reserved Mask */
\r
9782 // -------------------------------------- ETM_ETMSYNCFR -----------------------------------------
\r
9783 #define ETM_ETMSYNCFR_SynchronizationFrequency_Pos 0 /*!< ETM ETMSYNCFR: SynchronizationFrequency Position */
\r
9784 #define ETM_ETMSYNCFR_SynchronizationFrequency_Msk (0x00000fffUL << ETM_ETMSYNCFR_SynchronizationFrequency_Pos)/*!< ETM ETMSYNCFR: SynchronizationFrequency Mask */
\r
9785 #define ETM_ETMSYNCFR_Reserved_Pos 12 /*!< ETM ETMSYNCFR: Reserved Position */
\r
9786 #define ETM_ETMSYNCFR_Reserved_Msk (0x000fffffUL << ETM_ETMSYNCFR_Reserved_Pos) /*!< ETM ETMSYNCFR: Reserved Mask */
\r
9788 // --------------------------------------- ETM_ETMIDR -------------------------------------------
\r
9789 #define ETM_ETMIDR_ImplementationRevision_Pos 0 /*!< ETM ETMIDR: ImplementationRevision Position */
\r
9790 #define ETM_ETMIDR_ImplementationRevision_Msk (0x0fUL << ETM_ETMIDR_ImplementationRevision_Pos) /*!< ETM ETMIDR: ImplementationRevision Mask */
\r
9791 #define ETM_ETMIDR_MinorETM_ArchitectureVersion_Pos 4 /*!< ETM ETMIDR: MinorETM_ArchitectureVersion Position */
\r
9792 #define ETM_ETMIDR_MinorETM_ArchitectureVersion_Msk (0x0fUL << ETM_ETMIDR_MinorETM_ArchitectureVersion_Pos) /*!< ETM ETMIDR: MinorETM_ArchitectureVersion Mask */
\r
9793 #define ETM_ETMIDR_MajorETM_ArchitectureVersion_Pos 8 /*!< ETM ETMIDR: MajorETM_ArchitectureVersion Position */
\r
9794 #define ETM_ETMIDR_MajorETM_ArchitectureVersion_Msk (0x0fUL << ETM_ETMIDR_MajorETM_ArchitectureVersion_Pos) /*!< ETM ETMIDR: MajorETM_ArchitectureVersion Mask */
\r
9795 #define ETM_ETMIDR_ProcessorFamily_Pos 12 /*!< ETM ETMIDR: ProcessorFamily Position */
\r
9796 #define ETM_ETMIDR_ProcessorFamily_Msk (0x0fUL << ETM_ETMIDR_ProcessorFamily_Pos) /*!< ETM ETMIDR: ProcessorFamily Mask */
\r
9797 #define ETM_ETMIDR_LoadPC_First_Pos 16 /*!< ETM ETMIDR: LoadPC_First Position */
\r
9798 #define ETM_ETMIDR_LoadPC_First_Msk (0x01UL << ETM_ETMIDR_LoadPC_First_Pos) /*!< ETM ETMIDR: LoadPC_First Mask */
\r
9799 #define ETM_ETMIDR_Reserved_Pos 17 /*!< ETM ETMIDR: Reserved Position */
\r
9800 #define ETM_ETMIDR_Reserved_Msk (0x01UL << ETM_ETMIDR_Reserved_Pos) /*!< ETM ETMIDR: Reserved Mask */
\r
9801 #define ETM_ETMIDR_Bitfield_32bitThumbInstructionTracing_Pos 18 /*!< ETM ETMIDR: Bitfield_32bitThumbInstructionTracing Position */
\r
9802 #define ETM_ETMIDR_Bitfield_32bitThumbInstructionTracing_Msk (0x01UL << ETM_ETMIDR_Bitfield_32bitThumbInstructionTracing_Pos)/*!< ETM ETMIDR: Bitfield_32bitThumbInstructionTracing Mask */
\r
9803 #define ETM_ETMIDR_SecurityExtensionsSupport_Pos 19 /*!< ETM ETMIDR: SecurityExtensionsSupport Position */
\r
9804 #define ETM_ETMIDR_SecurityExtensionsSupport_Msk (0x01UL << ETM_ETMIDR_SecurityExtensionsSupport_Pos) /*!< ETM ETMIDR: SecurityExtensionsSupport Mask */
\r
9805 #define ETM_ETMIDR_BranchPacketEncoding_Pos 20 /*!< ETM ETMIDR: BranchPacketEncoding Position */
\r
9806 #define ETM_ETMIDR_BranchPacketEncoding_Msk (0x01UL << ETM_ETMIDR_BranchPacketEncoding_Pos) /*!< ETM ETMIDR: BranchPacketEncoding Mask */
\r
9807 #define ETM_ETMIDR_Reserved1_Pos 21 /*!< ETM ETMIDR: Reserved1 Position */
\r
9808 #define ETM_ETMIDR_Reserved1_Msk (0x07UL << ETM_ETMIDR_Reserved1_Pos) /*!< ETM ETMIDR: Reserved1 Mask */
\r
9809 #define ETM_ETMIDR_ImplementerCode_Pos 24 /*!< ETM ETMIDR: ImplementerCode Position */
\r
9810 #define ETM_ETMIDR_ImplementerCode_Msk (0x000000ffUL << ETM_ETMIDR_ImplementerCode_Pos) /*!< ETM ETMIDR: ImplementerCode Mask */
\r
9812 // --------------------------------------- ETM_ETMCCER ------------------------------------------
\r
9813 #define ETM_ETMCCER_ExtendedExternalInputSelectors_Pos 0 /*!< ETM ETMCCER: ExtendedExternalInputSelectors Position */
\r
9814 #define ETM_ETMCCER_ExtendedExternalInputSelectors_Msk (0x07UL << ETM_ETMCCER_ExtendedExternalInputSelectors_Pos)/*!< ETM ETMCCER: ExtendedExternalInputSelectors Mask */
\r
9815 #define ETM_ETMCCER_ExtendedExternalInputBus_Pos 3 /*!< ETM ETMCCER: ExtendedExternalInputBus Position */
\r
9816 #define ETM_ETMCCER_ExtendedExternalInputBus_Msk (0x000000ffUL << ETM_ETMCCER_ExtendedExternalInputBus_Pos)/*!< ETM ETMCCER: ExtendedExternalInputBus Mask */
\r
9817 #define ETM_ETMCCER_ReadableRegisters_Pos 11 /*!< ETM ETMCCER: ReadableRegisters Position */
\r
9818 #define ETM_ETMCCER_ReadableRegisters_Msk (0x01UL << ETM_ETMCCER_ReadableRegisters_Pos) /*!< ETM ETMCCER: ReadableRegisters Mask */
\r
9819 #define ETM_ETMCCER_DataAddressComparisons_Pos 12 /*!< ETM ETMCCER: DataAddressComparisons Position */
\r
9820 #define ETM_ETMCCER_DataAddressComparisons_Msk (0x01UL << ETM_ETMCCER_DataAddressComparisons_Pos) /*!< ETM ETMCCER: DataAddressComparisons Mask */
\r
9821 #define ETM_ETMCCER_InstrumentationResources_Pos 13 /*!< ETM ETMCCER: InstrumentationResources Position */
\r
9822 #define ETM_ETMCCER_InstrumentationResources_Msk (0x07UL << ETM_ETMCCER_InstrumentationResources_Pos) /*!< ETM ETMCCER: InstrumentationResources Mask */
\r
9823 #define ETM_ETMCCER_EmbeddedICE_WatchpointInputs_Pos 16 /*!< ETM ETMCCER: EmbeddedICE_WatchpointInputs Position */
\r
9824 #define ETM_ETMCCER_EmbeddedICE_WatchpointInputs_Msk (0x0fUL << ETM_ETMCCER_EmbeddedICE_WatchpointInputs_Pos) /*!< ETM ETMCCER: EmbeddedICE_WatchpointInputs Mask */
\r
9825 #define ETM_ETMCCER_TraceStartStopBlockUsesEmbeddediceWatchpointInputs_Pos20 /*!< ETM ETMCCER: TraceStartStopBlockUsesEmbeddediceWatchpointInputs Position */
\r
9826 #define ETM_ETMCCER_TraceStartStopBlockUsesEmbeddediceWatchpointInputs_Msk (0x01UL << ETM_ETMCCER_TraceStartStopBlockUsesEmbeddediceWatchpointInputs_Pos)/*!< ETM ETMCCER: TraceStartStopBlockUsesEmbeddediceWatchpointInputs Mask */
\r
9827 #define ETM_ETMCCER_EmbeddediceBehaviorControlImplemented_Pos 21 /*!< ETM ETMCCER: EmbeddediceBehaviorControlImplemented Position */
\r
9828 #define ETM_ETMCCER_EmbeddediceBehaviorControlImplemented_Msk (0x01UL << ETM_ETMCCER_EmbeddediceBehaviorControlImplemented_Pos)/*!< ETM ETMCCER: EmbeddediceBehaviorControlImplemented Mask */
\r
9829 #define ETM_ETMCCER_TimestampingImplemented_Pos 22 /*!< ETM ETMCCER: TimestampingImplemented Position */
\r
9830 #define ETM_ETMCCER_TimestampingImplemented_Msk (0x01UL << ETM_ETMCCER_TimestampingImplemented_Pos) /*!< ETM ETMCCER: TimestampingImplemented Mask */
\r
9831 #define ETM_ETMCCER_Reserved_Pos 23 /*!< ETM ETMCCER: Reserved Position */
\r
9832 #define ETM_ETMCCER_Reserved_Msk (0x0fUL << ETM_ETMCCER_Reserved_Pos) /*!< ETM ETMCCER: Reserved Mask */
\r
9833 #define ETM_ETMCCER_ReducedFunctionCounter_Pos 27 /*!< ETM ETMCCER: ReducedFunctionCounter Position */
\r
9834 #define ETM_ETMCCER_ReducedFunctionCounter_Msk (0x01UL << ETM_ETMCCER_ReducedFunctionCounter_Pos) /*!< ETM ETMCCER: ReducedFunctionCounter Mask */
\r
9835 #define ETM_ETMCCER_TimestampEncoding_Pos 28 /*!< ETM ETMCCER: TimestampEncoding Position */
\r
9836 #define ETM_ETMCCER_TimestampEncoding_Msk (0x01UL << ETM_ETMCCER_TimestampEncoding_Pos) /*!< ETM ETMCCER: TimestampEncoding Mask */
\r
9837 #define ETM_ETMCCER_TimestampSize_Pos 29 /*!< ETM ETMCCER: TimestampSize Position */
\r
9838 #define ETM_ETMCCER_TimestampSize_Msk (0x01UL << ETM_ETMCCER_TimestampSize_Pos) /*!< ETM ETMCCER: TimestampSize Mask */
\r
9839 #define ETM_ETMCCER_Reserved1_Pos 30 /*!< ETM ETMCCER: Reserved1 Position */
\r
9840 #define ETM_ETMCCER_Reserved1_Msk (0x03UL << ETM_ETMCCER_Reserved1_Pos) /*!< ETM ETMCCER: Reserved1 Mask */
\r
9842 // ------------------------------------- ETM_ETMTESSEICR ----------------------------------------
\r
9843 #define ETM_ETMTESSEICR_StartResourceSelect_Pos 0 /*!< ETM ETMTESSEICR: StartResourceSelect Position */
\r
9844 #define ETM_ETMTESSEICR_StartResourceSelect_Msk (0x000000ffUL << ETM_ETMTESSEICR_StartResourceSelect_Pos) /*!< ETM ETMTESSEICR: StartResourceSelect Mask */
\r
9845 #define ETM_ETMTESSEICR_Reserved_Pos 8 /*!< ETM ETMTESSEICR: Reserved Position */
\r
9846 #define ETM_ETMTESSEICR_Reserved_Msk (0x000000ffUL << ETM_ETMTESSEICR_Reserved_Pos) /*!< ETM ETMTESSEICR: Reserved Mask */
\r
9847 #define ETM_ETMTESSEICR_StopResourceSelect_Pos 16 /*!< ETM ETMTESSEICR: StopResourceSelect Position */
\r
9848 #define ETM_ETMTESSEICR_StopResourceSelect_Msk (0x000000ffUL << ETM_ETMTESSEICR_StopResourceSelect_Pos) /*!< ETM ETMTESSEICR: StopResourceSelect Mask */
\r
9849 #define ETM_ETMTESSEICR_Reserved1_Pos 24 /*!< ETM ETMTESSEICR: Reserved1 Position */
\r
9850 #define ETM_ETMTESSEICR_Reserved1_Msk (0x000000ffUL << ETM_ETMTESSEICR_Reserved1_Pos) /*!< ETM ETMTESSEICR: Reserved1 Mask */
\r
9852 // -------------------------------------- ETM_ETMTSEVR ------------------------------------------
\r
9853 #define ETM_ETMTSEVR_ResourceA_Pos 0 /*!< ETM ETMTSEVR: ResourceA Position */
\r
9854 #define ETM_ETMTSEVR_ResourceA_Msk (0x7fUL << ETM_ETMTSEVR_ResourceA_Pos) /*!< ETM ETMTSEVR: ResourceA Mask */
\r
9855 #define ETM_ETMTSEVR_ResourceB_Pos 7 /*!< ETM ETMTSEVR: ResourceB Position */
\r
9856 #define ETM_ETMTSEVR_ResourceB_Msk (0x7fUL << ETM_ETMTSEVR_ResourceB_Pos) /*!< ETM ETMTSEVR: ResourceB Mask */
\r
9857 #define ETM_ETMTSEVR_Function_Pos 14 /*!< ETM ETMTSEVR: Function Position */
\r
9858 #define ETM_ETMTSEVR_Function_Msk (0x07UL << ETM_ETMTSEVR_Function_Pos) /*!< ETM ETMTSEVR: Function Mask */
\r
9859 #define ETM_ETMTSEVR_Reserved_Pos 17 /*!< ETM ETMTSEVR: Reserved Position */
\r
9860 #define ETM_ETMTSEVR_Reserved_Msk (0x00007fffUL << ETM_ETMTSEVR_Reserved_Pos) /*!< ETM ETMTSEVR: Reserved Mask */
\r
9862 // ------------------------------------- ETM_ETMTRACEIDR ----------------------------------------
\r
9863 #define ETM_ETMTRACEIDR_EmbeddedICE_WatchpointInputs_Pos 0 /*!< ETM ETMTRACEIDR: EmbeddedICE_WatchpointInputs Position */
\r
9864 #define ETM_ETMTRACEIDR_EmbeddedICE_WatchpointInputs_Msk (0x7fUL << ETM_ETMTRACEIDR_EmbeddedICE_WatchpointInputs_Pos)/*!< ETM ETMTRACEIDR: EmbeddedICE_WatchpointInputs Mask */
\r
9865 #define ETM_ETMTRACEIDR_Reserved_Pos 7 /*!< ETM ETMTRACEIDR: Reserved Position */
\r
9866 #define ETM_ETMTRACEIDR_Reserved_Msk (0x01ffffffUL << ETM_ETMTRACEIDR_Reserved_Pos) /*!< ETM ETMTRACEIDR: Reserved Mask */
\r
9868 // --------------------------------------- ETM_ETMIDR2 ------------------------------------------
\r
9869 #define ETM_ETMIDR2_RFE_TransferOrder_Pos 0 /*!< ETM ETMIDR2: RFE_TransferOrder Position */
\r
9870 #define ETM_ETMIDR2_RFE_TransferOrder_Msk (0x01UL << ETM_ETMIDR2_RFE_TransferOrder_Pos) /*!< ETM ETMIDR2: RFE_TransferOrder Mask */
\r
9871 #define ETM_ETMIDR2_SWP_TransferOrder_Pos 1 /*!< ETM ETMIDR2: SWP_TransferOrder Position */
\r
9872 #define ETM_ETMIDR2_SWP_TransferOrder_Msk (0x01UL << ETM_ETMIDR2_SWP_TransferOrder_Pos) /*!< ETM ETMIDR2: SWP_TransferOrder Mask */
\r
9873 #define ETM_ETMIDR2_Reserved_Pos 2 /*!< ETM ETMIDR2: Reserved Position */
\r
9874 #define ETM_ETMIDR2_Reserved_Msk (0x3fffffffUL << ETM_ETMIDR2_Reserved_Pos) /*!< ETM ETMIDR2: Reserved Mask */
\r
9876 // --------------------------------------- ETM_ETMPDSR ------------------------------------------
\r
9877 #define ETM_ETMPDSR_ETM_PoweredUp_Pos 0 /*!< ETM ETMPDSR: ETM_PoweredUp Position */
\r
9878 #define ETM_ETMPDSR_ETM_PoweredUp_Msk (0x01UL << ETM_ETMPDSR_ETM_PoweredUp_Pos) /*!< ETM ETMPDSR: ETM_PoweredUp Mask */
\r
9879 #define ETM_ETMPDSR_Reserved_Pos 1 /*!< ETM ETMPDSR: Reserved Position */
\r
9880 #define ETM_ETMPDSR_Reserved_Msk (0x7fffffffUL << ETM_ETMPDSR_Reserved_Pos) /*!< ETM ETMPDSR: Reserved Mask */
\r
9882 // -------------------------------------- ETM_ITMISCIN ------------------------------------------
\r
9883 #define ETM_ITMISCIN_EXTIN_1_0_Pos 0 /*!< ETM ITMISCIN: EXTIN_1_0 Position */
\r
9884 #define ETM_ITMISCIN_EXTIN_1_0_Msk (0x03UL << ETM_ITMISCIN_EXTIN_1_0_Pos) /*!< ETM ITMISCIN: EXTIN_1_0 Mask */
\r
9885 #define ETM_ITMISCIN_Reserved_Pos 2 /*!< ETM ITMISCIN: Reserved Position */
\r
9886 #define ETM_ITMISCIN_Reserved_Msk (0x03UL << ETM_ITMISCIN_Reserved_Pos) /*!< ETM ITMISCIN: Reserved Mask */
\r
9887 #define ETM_ITMISCIN_COREHALT_Pos 4 /*!< ETM ITMISCIN: COREHALT Position */
\r
9888 #define ETM_ITMISCIN_COREHALT_Msk (0x01UL << ETM_ITMISCIN_COREHALT_Pos) /*!< ETM ITMISCIN: COREHALT Mask */
\r
9889 #define ETM_ITMISCIN_Reserved1_Pos 5 /*!< ETM ITMISCIN: Reserved1 Position */
\r
9890 #define ETM_ITMISCIN_Reserved1_Msk (0x07ffffffUL << ETM_ITMISCIN_Reserved1_Pos) /*!< ETM ITMISCIN: Reserved1 Mask */
\r
9892 // -------------------------------------- ETM_ITTRIGOUT -----------------------------------------
\r
9893 #define ETM_ITTRIGOUT_TRIGGER_OutputValue_Pos 0 /*!< ETM ITTRIGOUT: TRIGGER_OutputValue Position */
\r
9894 #define ETM_ITTRIGOUT_TRIGGER_OutputValue_Msk (0x01UL << ETM_ITTRIGOUT_TRIGGER_OutputValue_Pos) /*!< ETM ITTRIGOUT: TRIGGER_OutputValue Mask */
\r
9895 #define ETM_ITTRIGOUT_Reserved_Pos 1 /*!< ETM ITTRIGOUT: Reserved Position */
\r
9896 #define ETM_ITTRIGOUT_Reserved_Msk (0x7fffffffUL << ETM_ITTRIGOUT_Reserved_Pos) /*!< ETM ITTRIGOUT: Reserved Mask */
\r
9898 // ------------------------------------ ETM_ETM_ITATBCTR2 ---------------------------------------
\r
9899 #define ETM_ETM_ITATBCTR2_ATREADYInputValue_Pos 0 /*!< ETM ETM_ITATBCTR2: ATREADYInputValue Position */
\r
9900 #define ETM_ETM_ITATBCTR2_ATREADYInputValue_Msk (0x01UL << ETM_ETM_ITATBCTR2_ATREADYInputValue_Pos) /*!< ETM ETM_ITATBCTR2: ATREADYInputValue Mask */
\r
9901 #define ETM_ETM_ITATBCTR2_Reserved_Pos 1 /*!< ETM ETM_ITATBCTR2: Reserved Position */
\r
9902 #define ETM_ETM_ITATBCTR2_Reserved_Msk (0x7fffffffUL << ETM_ETM_ITATBCTR2_Reserved_Pos) /*!< ETM ETM_ITATBCTR2: Reserved Mask */
\r
9904 // ------------------------------------ ETM_ETM_ITATBCTR0 ---------------------------------------
\r
9905 #define ETM_ETM_ITATBCTR0_ATVALIDOutputValue_Pos 0 /*!< ETM ETM_ITATBCTR0: ATVALIDOutputValue Position */
\r
9906 #define ETM_ETM_ITATBCTR0_ATVALIDOutputValue_Msk (0x01UL << ETM_ETM_ITATBCTR0_ATVALIDOutputValue_Pos) /*!< ETM ETM_ITATBCTR0: ATVALIDOutputValue Mask */
\r
9907 #define ETM_ETM_ITATBCTR0_Reserved_Pos 1 /*!< ETM ETM_ITATBCTR0: Reserved Position */
\r
9908 #define ETM_ETM_ITATBCTR0_Reserved_Msk (0x7fffffffUL << ETM_ETM_ITATBCTR0_Reserved_Pos) /*!< ETM ETM_ITATBCTR0: Reserved Mask */
\r
9910 // -------------------------------------- ETM_ETMITCTRL -----------------------------------------
\r
9911 #define ETM_ETMITCTRL_EnableIntegrationMode_Pos 0 /*!< ETM ETMITCTRL: EnableIntegrationMode Position */
\r
9912 #define ETM_ETMITCTRL_EnableIntegrationMode_Msk (0x01UL << ETM_ETMITCTRL_EnableIntegrationMode_Pos) /*!< ETM ETMITCTRL: EnableIntegrationMode Mask */
\r
9913 #define ETM_ETMITCTRL_Reserved_Pos 1 /*!< ETM ETMITCTRL: Reserved Position */
\r
9914 #define ETM_ETMITCTRL_Reserved_Msk (0x7fffffffUL << ETM_ETMITCTRL_Reserved_Pos) /*!< ETM ETMITCTRL: Reserved Mask */
\r
9916 // ------------------------------------- ETM_ETMCLAIMSET ----------------------------------------
\r
9917 #define ETM_ETMCLAIMSET_ClaimTag_Pos 0 /*!< ETM ETMCLAIMSET: ClaimTag Position */
\r
9918 #define ETM_ETMCLAIMSET_ClaimTag_Msk (0x000000ffUL << ETM_ETMCLAIMSET_ClaimTag_Pos) /*!< ETM ETMCLAIMSET: ClaimTag Mask */
\r
9919 #define ETM_ETMCLAIMSET_Reserved_Pos 8 /*!< ETM ETMCLAIMSET: Reserved Position */
\r
9920 #define ETM_ETMCLAIMSET_Reserved_Msk (0x00ffffffUL << ETM_ETMCLAIMSET_Reserved_Pos) /*!< ETM ETMCLAIMSET: Reserved Mask */
\r
9922 // ------------------------------------- ETM_ETMCLAIMCLR ----------------------------------------
\r
9923 #define ETM_ETMCLAIMCLR_ClaimTag_Pos 0 /*!< ETM ETMCLAIMCLR: ClaimTag Position */
\r
9924 #define ETM_ETMCLAIMCLR_ClaimTag_Msk (0x000000ffUL << ETM_ETMCLAIMCLR_ClaimTag_Pos) /*!< ETM ETMCLAIMCLR: ClaimTag Mask */
\r
9925 #define ETM_ETMCLAIMCLR_Reserved_Pos 8 /*!< ETM ETMCLAIMCLR: Reserved Position */
\r
9926 #define ETM_ETMCLAIMCLR_Reserved_Msk (0x00ffffffUL << ETM_ETMCLAIMCLR_Reserved_Pos) /*!< ETM ETMCLAIMCLR: Reserved Mask */
\r
9928 // --------------------------------------- ETM_ETMLAR -------------------------------------------
\r
9929 #define ETM_ETMLAR_KeyValue_Pos 0 /*!< ETM ETMLAR: KeyValue Position */
\r
9930 #define ETM_ETMLAR_KeyValue_Msk (0xffffffffUL << ETM_ETMLAR_KeyValue_Pos) /*!< ETM ETMLAR: KeyValue Mask */
\r
9932 // --------------------------------------- ETM_ETMLSR -------------------------------------------
\r
9933 #define ETM_ETMLSR_ETM_LockingImplemented_Pos 0 /*!< ETM ETMLSR: ETM_LockingImplemented Position */
\r
9934 #define ETM_ETMLSR_ETM_LockingImplemented_Msk (0x01UL << ETM_ETMLSR_ETM_LockingImplemented_Pos) /*!< ETM ETMLSR: ETM_LockingImplemented Mask */
\r
9935 #define ETM_ETMLSR_ETM_Locked_Pos 1 /*!< ETM ETMLSR: ETM_Locked Position */
\r
9936 #define ETM_ETMLSR_ETM_Locked_Msk (0x01UL << ETM_ETMLSR_ETM_Locked_Pos) /*!< ETM ETMLSR: ETM_Locked Mask */
\r
9937 #define ETM_ETMLSR_ReadsAsZero_Pos 2 /*!< ETM ETMLSR: ReadsAsZero Position */
\r
9938 #define ETM_ETMLSR_ReadsAsZero_Msk (0x01UL << ETM_ETMLSR_ReadsAsZero_Pos) /*!< ETM ETMLSR: ReadsAsZero Mask */
\r
9939 #define ETM_ETMLSR_Reserved_Pos 3 /*!< ETM ETMLSR: Reserved Position */
\r
9940 #define ETM_ETMLSR_Reserved_Msk (0x1fffffffUL << ETM_ETMLSR_Reserved_Pos) /*!< ETM ETMLSR: Reserved Mask */
\r
9942 // ------------------------------------ ETM_ETMAUTHSTATUS ---------------------------------------
\r
9943 #define ETM_ETMAUTHSTATUS_NonsecureInvasiveDebug_Pos 0 /*!< ETM ETMAUTHSTATUS: NonsecureInvasiveDebug Position */
\r
9944 #define ETM_ETMAUTHSTATUS_NonsecureInvasiveDebug_Msk (0x03UL << ETM_ETMAUTHSTATUS_NonsecureInvasiveDebug_Pos) /*!< ETM ETMAUTHSTATUS: NonsecureInvasiveDebug Mask */
\r
9945 #define ETM_ETMAUTHSTATUS_NonsecureNonInvasiveDebug_Pos 2 /*!< ETM ETMAUTHSTATUS: NonsecureNonInvasiveDebug Position */
\r
9946 #define ETM_ETMAUTHSTATUS_NonsecureNonInvasiveDebug_Msk (0x03UL << ETM_ETMAUTHSTATUS_NonsecureNonInvasiveDebug_Pos)/*!< ETM ETMAUTHSTATUS: NonsecureNonInvasiveDebug Mask */
\r
9947 #define ETM_ETMAUTHSTATUS_SecureInvasiveDebug_Pos 4 /*!< ETM ETMAUTHSTATUS: SecureInvasiveDebug Position */
\r
9948 #define ETM_ETMAUTHSTATUS_SecureInvasiveDebug_Msk (0x03UL << ETM_ETMAUTHSTATUS_SecureInvasiveDebug_Pos) /*!< ETM ETMAUTHSTATUS: SecureInvasiveDebug Mask */
\r
9949 #define ETM_ETMAUTHSTATUS_SecureNonInvasiveDebug_Pos 6 /*!< ETM ETMAUTHSTATUS: SecureNonInvasiveDebug Position */
\r
9950 #define ETM_ETMAUTHSTATUS_SecureNonInvasiveDebug_Msk (0x03UL << ETM_ETMAUTHSTATUS_SecureNonInvasiveDebug_Pos) /*!< ETM ETMAUTHSTATUS: SecureNonInvasiveDebug Mask */
\r
9951 #define ETM_ETMAUTHSTATUS_Reserved_Pos 8 /*!< ETM ETMAUTHSTATUS: Reserved Position */
\r
9952 #define ETM_ETMAUTHSTATUS_Reserved_Msk (0x00ffffffUL << ETM_ETMAUTHSTATUS_Reserved_Pos) /*!< ETM ETMAUTHSTATUS: Reserved Mask */
\r
9954 // ------------------------------------- ETM_ETMDEVTYPE -----------------------------------------
\r
9955 #define ETM_ETMDEVTYPE_MainType_Pos 0 /*!< ETM ETMDEVTYPE: MainType Position */
\r
9956 #define ETM_ETMDEVTYPE_MainType_Msk (0x0fUL << ETM_ETMDEVTYPE_MainType_Pos) /*!< ETM ETMDEVTYPE: MainType Mask */
\r
9957 #define ETM_ETMDEVTYPE_SubType_Pos 4 /*!< ETM ETMDEVTYPE: SubType Position */
\r
9958 #define ETM_ETMDEVTYPE_SubType_Msk (0x0fUL << ETM_ETMDEVTYPE_SubType_Pos) /*!< ETM ETMDEVTYPE: SubType Mask */
\r
9959 #define ETM_ETMDEVTYPE_Reserved_Pos 8 /*!< ETM ETMDEVTYPE: Reserved Position */
\r
9960 #define ETM_ETMDEVTYPE_Reserved_Msk (0x00ffffffUL << ETM_ETMDEVTYPE_Reserved_Pos) /*!< ETM ETMDEVTYPE: Reserved Mask */
\r
9962 // -------------------------------------- ETM_ETMPIDR4 ------------------------------------------
\r
9963 #define ETM_ETMPIDR4_JEP106ContinuationCode_Pos 0 /*!< ETM ETMPIDR4: JEP106ContinuationCode Position */
\r
9964 #define ETM_ETMPIDR4_JEP106ContinuationCode_Msk (0x0fUL << ETM_ETMPIDR4_JEP106ContinuationCode_Pos) /*!< ETM ETMPIDR4: JEP106ContinuationCode Mask */
\r
9965 #define ETM_ETMPIDR4_Bitfield_4KBcount_Pos 4 /*!< ETM ETMPIDR4: Bitfield_4KBcount Position */
\r
9966 #define ETM_ETMPIDR4_Bitfield_4KBcount_Msk (0x0fUL << ETM_ETMPIDR4_Bitfield_4KBcount_Pos) /*!< ETM ETMPIDR4: Bitfield_4KBcount Mask */
\r
9967 #define ETM_ETMPIDR4_Reserved_Pos 8 /*!< ETM ETMPIDR4: Reserved Position */
\r
9968 #define ETM_ETMPIDR4_Reserved_Msk (0x00ffffffUL << ETM_ETMPIDR4_Reserved_Pos) /*!< ETM ETMPIDR4: Reserved Mask */
\r
9970 // -------------------------------------- ETM_ETMPIDR5 ------------------------------------------
\r
9971 #define ETM_ETMPIDR5_ReservedForFutureUse_Pos 0 /*!< ETM ETMPIDR5: ReservedForFutureUse Position */
\r
9972 #define ETM_ETMPIDR5_ReservedForFutureUse_Msk (0x000000ffUL << ETM_ETMPIDR5_ReservedForFutureUse_Pos) /*!< ETM ETMPIDR5: ReservedForFutureUse Mask */
\r
9973 #define ETM_ETMPIDR5_Reserved_Pos 8 /*!< ETM ETMPIDR5: Reserved Position */
\r
9974 #define ETM_ETMPIDR5_Reserved_Msk (0x00ffffffUL << ETM_ETMPIDR5_Reserved_Pos) /*!< ETM ETMPIDR5: Reserved Mask */
\r
9976 // -------------------------------------- ETM_ETMPIDR6 ------------------------------------------
\r
9977 #define ETM_ETMPIDR6_ReservedForFutureUse_Pos 0 /*!< ETM ETMPIDR6: ReservedForFutureUse Position */
\r
9978 #define ETM_ETMPIDR6_ReservedForFutureUse_Msk (0x000000ffUL << ETM_ETMPIDR6_ReservedForFutureUse_Pos) /*!< ETM ETMPIDR6: ReservedForFutureUse Mask */
\r
9979 #define ETM_ETMPIDR6_Reserved_Pos 8 /*!< ETM ETMPIDR6: Reserved Position */
\r
9980 #define ETM_ETMPIDR6_Reserved_Msk (0x00ffffffUL << ETM_ETMPIDR6_Reserved_Pos) /*!< ETM ETMPIDR6: Reserved Mask */
\r
9982 // -------------------------------------- ETM_ETMPIDR7 ------------------------------------------
\r
9983 #define ETM_ETMPIDR7_ReservedForFutureUse_Pos 0 /*!< ETM ETMPIDR7: ReservedForFutureUse Position */
\r
9984 #define ETM_ETMPIDR7_ReservedForFutureUse_Msk (0x000000ffUL << ETM_ETMPIDR7_ReservedForFutureUse_Pos) /*!< ETM ETMPIDR7: ReservedForFutureUse Mask */
\r
9985 #define ETM_ETMPIDR7_Reserved_Pos 8 /*!< ETM ETMPIDR7: Reserved Position */
\r
9986 #define ETM_ETMPIDR7_Reserved_Msk (0x00ffffffUL << ETM_ETMPIDR7_Reserved_Pos) /*!< ETM ETMPIDR7: Reserved Mask */
\r
9988 // -------------------------------------- ETM_ETMPIDR0 ------------------------------------------
\r
9989 #define ETM_ETMPIDR0_PartNumber_7_0_Pos 0 /*!< ETM ETMPIDR0: PartNumber_7_0 Position */
\r
9990 #define ETM_ETMPIDR0_PartNumber_7_0_Msk (0x000000ffUL << ETM_ETMPIDR0_PartNumber_7_0_Pos) /*!< ETM ETMPIDR0: PartNumber_7_0 Mask */
\r
9991 #define ETM_ETMPIDR0_Reserved_Pos 8 /*!< ETM ETMPIDR0: Reserved Position */
\r
9992 #define ETM_ETMPIDR0_Reserved_Msk (0x00ffffffUL << ETM_ETMPIDR0_Reserved_Pos) /*!< ETM ETMPIDR0: Reserved Mask */
\r
9994 // -------------------------------------- ETM_ETMPIDR1 ------------------------------------------
\r
9995 #define ETM_ETMPIDR1_PartNumber_11_8_Pos 0 /*!< ETM ETMPIDR1: PartNumber_11_8 Position */
\r
9996 #define ETM_ETMPIDR1_PartNumber_11_8_Msk (0x0fUL << ETM_ETMPIDR1_PartNumber_11_8_Pos) /*!< ETM ETMPIDR1: PartNumber_11_8 Mask */
\r
9997 #define ETM_ETMPIDR1_JEP106IdentityCode_3_0_Pos 4 /*!< ETM ETMPIDR1: JEP106IdentityCode_3_0 Position */
\r
9998 #define ETM_ETMPIDR1_JEP106IdentityCode_3_0_Msk (0x0fUL << ETM_ETMPIDR1_JEP106IdentityCode_3_0_Pos) /*!< ETM ETMPIDR1: JEP106IdentityCode_3_0 Mask */
\r
9999 #define ETM_ETMPIDR1_Reserved_Pos 8 /*!< ETM ETMPIDR1: Reserved Position */
\r
10000 #define ETM_ETMPIDR1_Reserved_Msk (0x00ffffffUL << ETM_ETMPIDR1_Reserved_Pos) /*!< ETM ETMPIDR1: Reserved Mask */
\r
10002 // -------------------------------------- ETM_ETMPIDR2 ------------------------------------------
\r
10003 #define ETM_ETMPIDR2_JEP106IdentityCode_6_4_Pos 0 /*!< ETM ETMPIDR2: JEP106IdentityCode_6_4 Position */
\r
10004 #define ETM_ETMPIDR2_JEP106IdentityCode_6_4_Msk (0x0fUL << ETM_ETMPIDR2_JEP106IdentityCode_6_4_Pos) /*!< ETM ETMPIDR2: JEP106IdentityCode_6_4 Mask */
\r
10005 #define ETM_ETMPIDR2_Always1_Pos 4 /*!< ETM ETMPIDR2: Always1 Position */
\r
10006 #define ETM_ETMPIDR2_Always1_Msk (0x01UL << ETM_ETMPIDR2_Always1_Pos) /*!< ETM ETMPIDR2: Always1 Mask */
\r
10007 #define ETM_ETMPIDR2_Revision_Pos 5 /*!< ETM ETMPIDR2: Revision Position */
\r
10008 #define ETM_ETMPIDR2_Revision_Msk (0x07UL << ETM_ETMPIDR2_Revision_Pos) /*!< ETM ETMPIDR2: Revision Mask */
\r
10009 #define ETM_ETMPIDR2_Reserved_Pos 8 /*!< ETM ETMPIDR2: Reserved Position */
\r
10010 #define ETM_ETMPIDR2_Reserved_Msk (0x00ffffffUL << ETM_ETMPIDR2_Reserved_Pos) /*!< ETM ETMPIDR2: Reserved Mask */
\r
10012 // -------------------------------------- ETM_ETMPIDR3 ------------------------------------------
\r
10013 #define ETM_ETMPIDR3_CustomerModified_Pos 0 /*!< ETM ETMPIDR3: CustomerModified Position */
\r
10014 #define ETM_ETMPIDR3_CustomerModified_Msk (0x0fUL << ETM_ETMPIDR3_CustomerModified_Pos) /*!< ETM ETMPIDR3: CustomerModified Mask */
\r
10015 #define ETM_ETMPIDR3_RevAnd_Pos 4 /*!< ETM ETMPIDR3: RevAnd Position */
\r
10016 #define ETM_ETMPIDR3_RevAnd_Msk (0x0fUL << ETM_ETMPIDR3_RevAnd_Pos) /*!< ETM ETMPIDR3: RevAnd Mask */
\r
10017 #define ETM_ETMPIDR3_Reserved_Pos 8 /*!< ETM ETMPIDR3: Reserved Position */
\r
10018 #define ETM_ETMPIDR3_Reserved_Msk (0x00ffffffUL << ETM_ETMPIDR3_Reserved_Pos) /*!< ETM ETMPIDR3: Reserved Mask */
\r
10020 // -------------------------------------- ETM_ETMCIDR0 ------------------------------------------
\r
10021 #define ETM_ETMCIDR0_CID0_Pos 0 /*!< ETM ETMCIDR0: CID0 Position */
\r
10022 #define ETM_ETMCIDR0_CID0_Msk (0x000000ffUL << ETM_ETMCIDR0_CID0_Pos) /*!< ETM ETMCIDR0: CID0 Mask */
\r
10023 #define ETM_ETMCIDR0_Reserved_Pos 8 /*!< ETM ETMCIDR0: Reserved Position */
\r
10024 #define ETM_ETMCIDR0_Reserved_Msk (0x00ffffffUL << ETM_ETMCIDR0_Reserved_Pos) /*!< ETM ETMCIDR0: Reserved Mask */
\r
10026 // -------------------------------------- ETM_ETMCIDR1 ------------------------------------------
\r
10027 #define ETM_ETMCIDR1_CID1_Pos 0 /*!< ETM ETMCIDR1: CID1 Position */
\r
10028 #define ETM_ETMCIDR1_CID1_Msk (0x000000ffUL << ETM_ETMCIDR1_CID1_Pos) /*!< ETM ETMCIDR1: CID1 Mask */
\r
10029 #define ETM_ETMCIDR1_Reserved_Pos 8 /*!< ETM ETMCIDR1: Reserved Position */
\r
10030 #define ETM_ETMCIDR1_Reserved_Msk (0x00ffffffUL << ETM_ETMCIDR1_Reserved_Pos) /*!< ETM ETMCIDR1: Reserved Mask */
\r
10032 // -------------------------------------- ETM_ETMCIDR2 ------------------------------------------
\r
10033 #define ETM_ETMCIDR2_CID2_Pos 0 /*!< ETM ETMCIDR2: CID2 Position */
\r
10034 #define ETM_ETMCIDR2_CID2_Msk (0x000000ffUL << ETM_ETMCIDR2_CID2_Pos) /*!< ETM ETMCIDR2: CID2 Mask */
\r
10035 #define ETM_ETMCIDR2_Reserved_Pos 8 /*!< ETM ETMCIDR2: Reserved Position */
\r
10036 #define ETM_ETMCIDR2_Reserved_Msk (0x00ffffffUL << ETM_ETMCIDR2_Reserved_Pos) /*!< ETM ETMCIDR2: Reserved Mask */
\r
10038 // -------------------------------------- ETM_ETMCIDR3 ------------------------------------------
\r
10039 #define ETM_ETMCIDR3_CID3_Pos 0 /*!< ETM ETMCIDR3: CID3 Position */
\r
10040 #define ETM_ETMCIDR3_CID3_Msk (0x000000ffUL << ETM_ETMCIDR3_CID3_Pos) /*!< ETM ETMCIDR3: CID3 Mask */
\r
10041 #define ETM_ETMCIDR3_Reserved_Pos 8 /*!< ETM ETMCIDR3: Reserved Position */
\r
10042 #define ETM_ETMCIDR3_Reserved_Msk (0x00ffffffUL << ETM_ETMCIDR3_Reserved_Pos) /*!< ETM ETMCIDR3: Reserved Mask */
\r
10046 /*** FCE Bit Fileds *******************/
\r
10047 /***************************************************************************/
\r
10050 /* FCE_CLC = Clock Control Register*/
\r
10051 #define FCE_CLC_DISR_Pos (0U)
\r
10052 #define FCE_CLC_DISR_Msk (0x00000001U << FCE_CLC_DISR_Pos)
\r
10054 #define FCE_CLC_DISS_Pos (1U)
\r
10055 #define FCE_CLC_DISS_Msk (0x00000001U << FCE_CLC_DISS_Pos)
\r
10057 /* FCE_ID = Module Identification Register*/
\r
10058 #define FCE_ID_MOD_REV_Pos (0U)
\r
10059 #define FCE_ID_MOD_REV_Msk (0x000000FFU << FCE_ID_MOD_REV_Pos)
\r
10061 #define FCE_ID_MOD_TYPE_Pos (8U)
\r
10062 #define FCE_ID_MOD_TYPE_Msk (0x000000FFU << FCE_ID_MOD_TYPE_Pos)
\r
10064 #define FCE_ID_MOD_NUMBER_Pos (16U)
\r
10065 #define FCE_ID_MOD_NUMBER_Msk (0x0000FFFFU << FCE_ID_MOD_NUMBER_Pos)
\r
10067 /* FCE_KE_IRx = Input Register 0*/
\r
10068 #define FCE_KE_IR_IR_Pos (0U)
\r
10069 #define FCE_KE_IR_IR_Msk (0xFFFFFFFFU << FCE_KE_IR_IR_Pos)
\r
10071 /* FCE_KE_RESx = CRC Result Register 0*/
\r
10072 #define FCE_KE_RES_RES_Pos (0U)
\r
10073 #define FCE_KE_RES_RES_Msk (0xFFFFFFFFU << FCE_KE_RES_RES_Pos)
\r
10075 /* FCE_KE_CFGx = CRC Configuration Register 0*/
\r
10076 #define FCE_KE_CFG_CMI_Pos (0U)
\r
10077 #define FCE_KE_CFG_CMI_Msk (0x00000001U << FCE_KE_CFG_CMI_Pos)
\r
10079 #define FCE_KE_CFG_CEI_Pos (1U)
\r
10080 #define FCE_KE_CFG_CEI_Msk (0x00000001U << FCE_KE_CFG_CEI_Pos)
\r
10082 #define FCE_KE_CFG_LEI_Pos (2U)
\r
10083 #define FCE_KE_CFG_LEI_Msk (0x00000001U << FCE_KE_CFG_LEI_Pos)
\r
10085 #define FCE_KE_CFG_BEI_Pos (3U)
\r
10086 #define FCE_KE_CFG_BEI_Msk (0x00000001U << FCE_KE_CFG_BEI_Pos)
\r
10088 #define FCE_KE_CFG_CCE_Pos (4U)
\r
10089 #define FCE_KE_CFG_CCE_Msk (0x00000001U << FCE_KE_CFG_CCE_Pos)
\r
10091 #define FCE_KE_CFG_ALR_Pos (5U)
\r
10092 #define FCE_KE_CFG_ALR_Msk (0x00000001U << FCE_KE_CFG_ALR_Pos)
\r
10094 #define FCE_KE_CFG_REFIN_Pos (8U)
\r
10095 #define FCE_KE_CFG_REFIN_Msk (0x00000001U << FCE_KE_CFG_REFIN_Pos)
\r
10097 #define FCE_KE_CFG_REFOUT_Pos (9U)
\r
10098 #define FCE_KE_CFG_REFOUT_Msk (0x00000001U << FCE_KE_CFG_REFOUT_Pos)
\r
10100 #define FCE_KE_CFG_XSEL_Pos (10U)
\r
10101 #define FCE_KE_CFG_XSEL_Msk (0x00000001U << FCE_KE_CFG_XSEL_Pos)
\r
10103 /* FCE_KE_STSx = CRC Status Register 0*/
\r
10104 #define FCE_KE_STS_CMF_Pos (0U)
\r
10105 #define FCE_KE_STS_CMF_Msk (0x00000001U << FCE_KE_STS_CMF_Pos)
\r
10107 #define FCE_KE_STS_CEF_Pos (1U)
\r
10108 #define FCE_KE_STS_CEF_Msk (0x00000001U << FCE_KE_STS_CEF_Pos)
\r
10110 #define FCE_KE_STS_LEF_Pos (2U)
\r
10111 #define FCE_KE_STS_LEF_Msk (0x00000001U << FCE_KE_STS_LEF_Pos)
\r
10113 #define FCE_KE_STS_BEF_Pos (3U)
\r
10114 #define FCE_KE_STS_BEF_Msk (0x00000001U << FCE_KE_STS_BEF_Pos)
\r
10116 /* FCE_KE_LENGTHx = CRC Length Register 0*/
\r
10117 #define FCE_KE_LENGTH_LENGTH_Pos (0U)
\r
10118 #define FCE_KE_LENGTH_LENGTH_Msk (0x0000FFFFU << FCE_KE_LENGTH_LENGTH_Pos)
\r
10120 /* FCE_KE_CHECKx = CRC Check Register 0*/
\r
10121 #define FCE_KE_CHECK_CHECK_Pos (0U)
\r
10122 #define FCE_KE_CHECK_CHECK_Msk (0xFFFFFFFFU << FCE_KE_CHECK_CHECK_Pos)
\r
10124 /* FCE_KE_CRCx = CRC Register 0*/
\r
10125 #define FCE_KE_CRC_CRC_Pos (0U)
\r
10126 #define FCE_KE_CRC_CRC_Msk (0xFFFFFFFFU << FCE_KE_CRC_CRC_Pos)
\r
10128 /* FCE_KE_CTRx = CRC Test Register 0*/
\r
10129 #define FCE_KE_CTR_FCM_Pos (0U)
\r
10130 #define FCE_KE_CTR_FCM_Msk (0x00000001U << FCE_KE_CTR_FCM_Pos)
\r
10132 #define FCE_KE_CTR_FRM_CFG_Pos (1U)
\r
10133 #define FCE_KE_CTR_FRM_CFG_Msk (0x00000001U << FCE_KE_CTR_FRM_CFG_Pos)
\r
10135 #define FCE_KE_CTR_FRM_CHECK_Pos (2U)
\r
10136 #define FCE_KE_CTR_FRM_CHECK_Msk (0x00000001U << FCE_KE_CTR_FRM_CHECK_Pos)
\r
10140 /*** FLASH0 Bit Fileds *******************/
\r
10141 /***************************************************************************/
\r
10144 /* FLASH_ID = Flash Module Identification Register*/
\r
10145 #define FLASH_ID_MOD_REV_Pos (0U)
\r
10146 #define FLASH_ID_MOD_REV_Msk (0x000000FFU << FLASH_ID_MOD_REV_Pos)
\r
10148 #define FLASH_ID_MOD_TYPE_Pos (8U)
\r
10149 #define FLASH_ID_MOD_TYPE_Msk (0x000000FFU << FLASH_ID_MOD_TYPE_Pos)
\r
10151 #define FLASH_ID_MOD_NUMBER_Pos (16U)
\r
10152 #define FLASH_ID_MOD_NUMBER_Msk (0x0000FFFFU << FLASH_ID_MOD_NUMBER_Pos)
\r
10154 /* FLASH_FSR = Flash Status Register*/
\r
10155 #define FLASH_FSR_PBUSY_Pos (0U)
\r
10156 #define FLASH_FSR_PBUSY_Msk (0x00000001U << FLASH_FSR_PBUSY_Pos)
\r
10158 #define FLASH_FSR_FABUSY_Pos (1U)
\r
10159 #define FLASH_FSR_FABUSY_Msk (0x00000001U << FLASH_FSR_FABUSY_Pos)
\r
10161 #define FLASH_FSR_PROG_Pos (4U)
\r
10162 #define FLASH_FSR_PROG_Msk (0x00000001U << FLASH_FSR_PROG_Pos)
\r
10164 #define FLASH_FSR_ERASE_Pos (5U)
\r
10165 #define FLASH_FSR_ERASE_Msk (0x00000001U << FLASH_FSR_ERASE_Pos)
\r
10167 #define FLASH_FSR_PFPAGE_Pos (6U)
\r
10168 #define FLASH_FSR_PFPAGE_Msk (0x00000001U << FLASH_FSR_PFPAGE_Pos)
\r
10170 #define FLASH_FSR_PFOPER_Pos (8U)
\r
10171 #define FLASH_FSR_PFOPER_Msk (0x00000001U << FLASH_FSR_PFOPER_Pos)
\r
10173 #define FLASH_FSR_SQER_Pos (10U)
\r
10174 #define FLASH_FSR_SQER_Msk (0x00000001U << FLASH_FSR_SQER_Pos)
\r
10176 #define FLASH_FSR_PROER_Pos (11U)
\r
10177 #define FLASH_FSR_PROER_Msk (0x00000001U << FLASH_FSR_PROER_Pos)
\r
10179 #define FLASH_FSR_PFSBER_Pos (12U)
\r
10180 #define FLASH_FSR_PFSBER_Msk (0x00000001U << FLASH_FSR_PFSBER_Pos)
\r
10182 #define FLASH_FSR_PFDBER_Pos (14U)
\r
10183 #define FLASH_FSR_PFDBER_Msk (0x00000001U << FLASH_FSR_PFDBER_Pos)
\r
10185 #define FLASH_FSR_PROIN_Pos (16U)
\r
10186 #define FLASH_FSR_PROIN_Msk (0x00000001U << FLASH_FSR_PROIN_Pos)
\r
10188 #define FLASH_FSR_RPROIN_Pos (18U)
\r
10189 #define FLASH_FSR_RPROIN_Msk (0x00000001U << FLASH_FSR_RPROIN_Pos)
\r
10191 #define FLASH_FSR_RPRODIS_Pos (19U)
\r
10192 #define FLASH_FSR_RPRODIS_Msk (0x00000001U << FLASH_FSR_RPRODIS_Pos)
\r
10194 #define FLASH_FSR_WPROIN0_Pos (21U)
\r
10195 #define FLASH_FSR_WPROIN0_Msk (0x00000001U << FLASH_FSR_WPROIN0_Pos)
\r
10197 #define FLASH_FSR_WPROIN1_Pos (22U)
\r
10198 #define FLASH_FSR_WPROIN1_Msk (0x00000001U << FLASH_FSR_WPROIN1_Pos)
\r
10200 #define FLASH_FSR_WPROIN2_Pos (23U)
\r
10201 #define FLASH_FSR_WPROIN2_Msk (0x00000001U << FLASH_FSR_WPROIN2_Pos)
\r
10203 #define FLASH_FSR_WPRODIS0_Pos (25U)
\r
10204 #define FLASH_FSR_WPRODIS0_Msk (0x00000001U << FLASH_FSR_WPRODIS0_Pos)
\r
10206 #define FLASH_FSR_WPRODIS1_Pos (26U)
\r
10207 #define FLASH_FSR_WPRODIS1_Msk (0x00000001U << FLASH_FSR_WPRODIS1_Pos)
\r
10209 #define FLASH_FSR_SLM_Pos (28U)
\r
10210 #define FLASH_FSR_SLM_Msk (0x00000001U << FLASH_FSR_SLM_Pos)
\r
10212 #define FLASH_FSR_X_Pos (30U)
\r
10213 #define FLASH_FSR_X_Msk (0x00000001U << FLASH_FSR_X_Pos)
\r
10215 #define FLASH_FSR_VER_Pos (31U)
\r
10216 #define FLASH_FSR_VER_Msk (0x00000001U << FLASH_FSR_VER_Pos)
\r
10218 /* FLASH_FCON = Flash Configuration Register*/
\r
10219 #define FLASH_FCON_WSPFLASH_Pos (0U)
\r
10220 #define FLASH_FCON_WSPFLASH_Msk (0x0000000FU << FLASH_FCON_WSPFLASH_Pos)
\r
10222 #define FLASH_FCON_WSECPF_Pos (4U)
\r
10223 #define FLASH_FCON_WSECPF_Msk (0x00000001U << FLASH_FCON_WSECPF_Pos)
\r
10225 #define FLASH_FCON_IDLE_Pos (13U)
\r
10226 #define FLASH_FCON_IDLE_Msk (0x00000001U << FLASH_FCON_IDLE_Pos)
\r
10228 #define FLASH_FCON_ESLDIS_Pos (14U)
\r
10229 #define FLASH_FCON_ESLDIS_Msk (0x00000001U << FLASH_FCON_ESLDIS_Pos)
\r
10231 #define FLASH_FCON_SLEEP_Pos (15U)
\r
10232 #define FLASH_FCON_SLEEP_Msk (0x00000001U << FLASH_FCON_SLEEP_Pos)
\r
10234 #define FLASH_FCON_RPA_Pos (16U)
\r
10235 #define FLASH_FCON_RPA_Msk (0x00000001U << FLASH_FCON_RPA_Pos)
\r
10237 #define FLASH_FCON_DCF_Pos (17U)
\r
10238 #define FLASH_FCON_DCF_Msk (0x00000001U << FLASH_FCON_DCF_Pos)
\r
10240 #define FLASH_FCON_DDF_Pos (18U)
\r
10241 #define FLASH_FCON_DDF_Msk (0x00000001U << FLASH_FCON_DDF_Pos)
\r
10243 #define FLASH_FCON_VOPERM_Pos (24U)
\r
10244 #define FLASH_FCON_VOPERM_Msk (0x00000001U << FLASH_FCON_VOPERM_Pos)
\r
10246 #define FLASH_FCON_SQERM_Pos (25U)
\r
10247 #define FLASH_FCON_SQERM_Msk (0x00000001U << FLASH_FCON_SQERM_Pos)
\r
10249 #define FLASH_FCON_PROERM_Pos (26U)
\r
10250 #define FLASH_FCON_PROERM_Msk (0x00000001U << FLASH_FCON_PROERM_Pos)
\r
10252 #define FLASH_FCON_PFSBERM_Pos (27U)
\r
10253 #define FLASH_FCON_PFSBERM_Msk (0x00000001U << FLASH_FCON_PFSBERM_Pos)
\r
10255 #define FLASH_FCON_PFDBERM_Pos (29U)
\r
10256 #define FLASH_FCON_PFDBERM_Msk (0x00000001U << FLASH_FCON_PFDBERM_Pos)
\r
10258 #define FLASH_FCON_EOBM_Pos (31U)
\r
10259 #define FLASH_FCON_EOBM_Msk (0x00000001U << FLASH_FCON_EOBM_Pos)
\r
10261 /* FLASH_MARP = Margin Control Register PFLASH*/
\r
10262 #define FLASH_MARP_MARGIN_Pos (0U)
\r
10263 #define FLASH_MARP_MARGIN_Msk (0x0000000FU << FLASH_MARP_MARGIN_Pos)
\r
10265 #define FLASH_MARP_TRAPDIS_Pos (15U)
\r
10266 #define FLASH_MARP_TRAPDIS_Msk (0x00000001U << FLASH_MARP_TRAPDIS_Pos)
\r
10268 /* FLASH_PROCON0 = Flash Protection Configuration Register User 0*/
\r
10269 #define FLASH_PROCON0_S0L_Pos (0U)
\r
10270 #define FLASH_PROCON0_S0L_Msk (0x00000001U << FLASH_PROCON0_S0L_Pos)
\r
10272 #define FLASH_PROCON0_S1L_Pos (1U)
\r
10273 #define FLASH_PROCON0_S1L_Msk (0x00000001U << FLASH_PROCON0_S1L_Pos)
\r
10275 #define FLASH_PROCON0_S2L_Pos (2U)
\r
10276 #define FLASH_PROCON0_S2L_Msk (0x00000001U << FLASH_PROCON0_S2L_Pos)
\r
10278 #define FLASH_PROCON0_S3L_Pos (3U)
\r
10279 #define FLASH_PROCON0_S3L_Msk (0x00000001U << FLASH_PROCON0_S3L_Pos)
\r
10281 #define FLASH_PROCON0_S4L_Pos (4U)
\r
10282 #define FLASH_PROCON0_S4L_Msk (0x00000001U << FLASH_PROCON0_S4L_Pos)
\r
10284 #define FLASH_PROCON0_S5L_Pos (5U)
\r
10285 #define FLASH_PROCON0_S5L_Msk (0x00000001U << FLASH_PROCON0_S5L_Pos)
\r
10287 #define FLASH_PROCON0_S6L_Pos (6U)
\r
10288 #define FLASH_PROCON0_S6L_Msk (0x00000001U << FLASH_PROCON0_S6L_Pos)
\r
10290 #define FLASH_PROCON0_S7L_Pos (7U)
\r
10291 #define FLASH_PROCON0_S7L_Msk (0x00000001U << FLASH_PROCON0_S7L_Pos)
\r
10293 #define FLASH_PROCON0_S8L_Pos (8U)
\r
10294 #define FLASH_PROCON0_S8L_Msk (0x00000001U << FLASH_PROCON0_S8L_Pos)
\r
10296 #define FLASH_PROCON0_S9L_Pos (9U)
\r
10297 #define FLASH_PROCON0_S9L_Msk (0x00000001U << FLASH_PROCON0_S9L_Pos)
\r
10299 #define FLASH_PROCON0_S10_S11L_Pos (10U)
\r
10300 #define FLASH_PROCON0_S10_S11L_Msk (0x00000001U << FLASH_PROCON0_S10_S11L_Pos)
\r
10302 #define FLASH_PROCON0_RPRO_Pos (15U)
\r
10303 #define FLASH_PROCON0_RPRO_Msk (0x00000001U << FLASH_PROCON0_RPRO_Pos)
\r
10305 /* FLASH_PROCON1 = Flash Protection Configuration Register User 1*/
\r
10306 #define FLASH_PROCON1_S0L_Pos (0U)
\r
10307 #define FLASH_PROCON1_S0L_Msk (0x00000001U << FLASH_PROCON1_S0L_Pos)
\r
10309 #define FLASH_PROCON1_S1L_Pos (1U)
\r
10310 #define FLASH_PROCON1_S1L_Msk (0x00000001U << FLASH_PROCON1_S1L_Pos)
\r
10312 #define FLASH_PROCON1_S2L_Pos (2U)
\r
10313 #define FLASH_PROCON1_S2L_Msk (0x00000001U << FLASH_PROCON1_S2L_Pos)
\r
10315 #define FLASH_PROCON1_S3L_Pos (3U)
\r
10316 #define FLASH_PROCON1_S3L_Msk (0x00000001U << FLASH_PROCON1_S3L_Pos)
\r
10318 #define FLASH_PROCON1_S4L_Pos (4U)
\r
10319 #define FLASH_PROCON1_S4L_Msk (0x00000001U << FLASH_PROCON1_S4L_Pos)
\r
10321 #define FLASH_PROCON1_S5L_Pos (5U)
\r
10322 #define FLASH_PROCON1_S5L_Msk (0x00000001U << FLASH_PROCON1_S5L_Pos)
\r
10324 #define FLASH_PROCON1_S6L_Pos (6U)
\r
10325 #define FLASH_PROCON1_S6L_Msk (0x00000001U << FLASH_PROCON1_S6L_Pos)
\r
10327 #define FLASH_PROCON1_S7L_Pos (7U)
\r
10328 #define FLASH_PROCON1_S7L_Msk (0x00000001U << FLASH_PROCON1_S7L_Pos)
\r
10330 #define FLASH_PROCON1_S8L_Pos (8U)
\r
10331 #define FLASH_PROCON1_S8L_Msk (0x00000001U << FLASH_PROCON1_S8L_Pos)
\r
10333 #define FLASH_PROCON1_S9L_Pos (9U)
\r
10334 #define FLASH_PROCON1_S9L_Msk (0x00000001U << FLASH_PROCON1_S9L_Pos)
\r
10336 #define FLASH_PROCON1_S10_S11L_Pos (10U)
\r
10337 #define FLASH_PROCON1_S10_S11L_Msk (0x00000001U << FLASH_PROCON1_S10_S11L_Pos)
\r
10339 /* FLASH_PROCON2 = Flash Protection Configuration Register User 2*/
\r
10340 #define FLASH_PROCON2_S0ROM_Pos (0U)
\r
10341 #define FLASH_PROCON2_S0ROM_Msk (0x00000001U << FLASH_PROCON2_S0ROM_Pos)
\r
10343 #define FLASH_PROCON2_S1ROM_Pos (1U)
\r
10344 #define FLASH_PROCON2_S1ROM_Msk (0x00000001U << FLASH_PROCON2_S1ROM_Pos)
\r
10346 #define FLASH_PROCON2_S2ROM_Pos (2U)
\r
10347 #define FLASH_PROCON2_S2ROM_Msk (0x00000001U << FLASH_PROCON2_S2ROM_Pos)
\r
10349 #define FLASH_PROCON2_S3ROM_Pos (3U)
\r
10350 #define FLASH_PROCON2_S3ROM_Msk (0x00000001U << FLASH_PROCON2_S3ROM_Pos)
\r
10352 #define FLASH_PROCON2_S4ROM_Pos (4U)
\r
10353 #define FLASH_PROCON2_S4ROM_Msk (0x00000001U << FLASH_PROCON2_S4ROM_Pos)
\r
10355 #define FLASH_PROCON2_S5ROM_Pos (5U)
\r
10356 #define FLASH_PROCON2_S5ROM_Msk (0x00000001U << FLASH_PROCON2_S5ROM_Pos)
\r
10358 #define FLASH_PROCON2_S6ROM_Pos (6U)
\r
10359 #define FLASH_PROCON2_S6ROM_Msk (0x00000001U << FLASH_PROCON2_S6ROM_Pos)
\r
10361 #define FLASH_PROCON2_S7ROM_Pos (7U)
\r
10362 #define FLASH_PROCON2_S7ROM_Msk (0x00000001U << FLASH_PROCON2_S7ROM_Pos)
\r
10364 #define FLASH_PROCON2_S8ROM_Pos (8U)
\r
10365 #define FLASH_PROCON2_S8ROM_Msk (0x00000001U << FLASH_PROCON2_S8ROM_Pos)
\r
10367 #define FLASH_PROCON2_S9ROM_Pos (9U)
\r
10368 #define FLASH_PROCON2_S9ROM_Msk (0x00000001U << FLASH_PROCON2_S9ROM_Pos)
\r
10370 #define FLASH_PROCON2_S10_S11ROM_Pos (10U)
\r
10371 #define FLASH_PROCON2_S10_S11ROM_Msk (0x00000001U << FLASH_PROCON2_S10_S11ROM_Pos)
\r
10375 /*** FPB Bit Fileds *******************/
\r
10376 /***************************************************************************/
\r
10379 // --------------------------------------- FPB_FP_CTRL ------------------------------------------
\r
10380 #define FPB_FP_CTRL_ENABLE_Pos 0 /*!< FPB FP_CTRL: ENABLE Position */
\r
10381 #define FPB_FP_CTRL_ENABLE_Msk (0x01UL << FPB_FP_CTRL_ENABLE_Pos) /*!< FPB FP_CTRL: ENABLE Mask */
\r
10382 #define FPB_FP_CTRL_KEY_Pos 1 /*!< FPB FP_CTRL: KEY Position */
\r
10383 #define FPB_FP_CTRL_KEY_Msk (0x01UL << FPB_FP_CTRL_KEY_Pos) /*!< FPB FP_CTRL: KEY Mask */
\r
10384 #define FPB_FP_CTRL_Reserved_Pos 2 /*!< FPB FP_CTRL: Reserved Position */
\r
10385 #define FPB_FP_CTRL_Reserved_Msk (0x03UL << FPB_FP_CTRL_Reserved_Pos) /*!< FPB FP_CTRL: Reserved Mask */
\r
10386 #define FPB_FP_CTRL_NUM_CODE_3_0_Pos 4 /*!< FPB FP_CTRL: NUM_CODE_3_0 Position */
\r
10387 #define FPB_FP_CTRL_NUM_CODE_3_0_Msk (0x0fUL << FPB_FP_CTRL_NUM_CODE_3_0_Pos) /*!< FPB FP_CTRL: NUM_CODE_3_0 Mask */
\r
10388 #define FPB_FP_CTRL_NUM_LIT_Pos 8 /*!< FPB FP_CTRL: NUM_LIT Position */
\r
10389 #define FPB_FP_CTRL_NUM_LIT_Msk (0x0fUL << FPB_FP_CTRL_NUM_LIT_Pos) /*!< FPB FP_CTRL: NUM_LIT Mask */
\r
10390 #define FPB_FP_CTRL_NUM_CODE_6_4_Pos 12 /*!< FPB FP_CTRL: NUM_CODE_6_4 Position */
\r
10391 #define FPB_FP_CTRL_NUM_CODE_6_4_Msk (0x07UL << FPB_FP_CTRL_NUM_CODE_6_4_Pos) /*!< FPB FP_CTRL: NUM_CODE_6_4 Mask */
\r
10392 #define FPB_FP_CTRL_Reserved1_Pos 15 /*!< FPB FP_CTRL: Reserved1 Position */
\r
10393 #define FPB_FP_CTRL_Reserved1_Msk (0x0001ffffUL << FPB_FP_CTRL_Reserved1_Pos) /*!< FPB FP_CTRL: Reserved1 Mask */
\r
10395 // -------------------------------------- FPB_FP_REMAP ------------------------------------------
\r
10396 #define FPB_FP_REMAP_Reserved_Pos 0 /*!< FPB FP_REMAP: Reserved Position */
\r
10397 #define FPB_FP_REMAP_Reserved_Msk (0x1fUL << FPB_FP_REMAP_Reserved_Pos) /*!< FPB FP_REMAP: Reserved Mask */
\r
10398 #define FPB_FP_REMAP_REMAP_Pos 5 /*!< FPB FP_REMAP: REMAP Position */
\r
10399 #define FPB_FP_REMAP_REMAP_Msk (0x00ffffffUL << FPB_FP_REMAP_REMAP_Pos) /*!< FPB FP_REMAP: REMAP Mask */
\r
10400 #define FPB_FP_REMAP_RMPSPT_Pos 29 /*!< FPB FP_REMAP: RMPSPT Position */
\r
10401 #define FPB_FP_REMAP_RMPSPT_Msk (0x01UL << FPB_FP_REMAP_RMPSPT_Pos) /*!< FPB FP_REMAP: RMPSPT Mask */
\r
10402 #define FPB_FP_REMAP_Reserved1_Pos 30 /*!< FPB FP_REMAP: Reserved1 Position */
\r
10403 #define FPB_FP_REMAP_Reserved1_Msk (0x03UL << FPB_FP_REMAP_Reserved1_Pos) /*!< FPB FP_REMAP: Reserved1 Mask */
\r
10405 // -------------------------------------- FPB_FP_COMP0 ------------------------------------------
\r
10406 #define FPB_FP_COMP0_ENABLE_Pos 0 /*!< FPB FP_COMP0: ENABLE Position */
\r
10407 #define FPB_FP_COMP0_ENABLE_Msk (0x01UL << FPB_FP_COMP0_ENABLE_Pos) /*!< FPB FP_COMP0: ENABLE Mask */
\r
10408 #define FPB_FP_COMP0_Reserved_Pos 1 /*!< FPB FP_COMP0: Reserved Position */
\r
10409 #define FPB_FP_COMP0_Reserved_Msk (0x01UL << FPB_FP_COMP0_Reserved_Pos) /*!< FPB FP_COMP0: Reserved Mask */
\r
10410 #define FPB_FP_COMP0_COMP_Pos 2 /*!< FPB FP_COMP0: COMP Position */
\r
10411 #define FPB_FP_COMP0_COMP_Msk (0x07ffffffUL << FPB_FP_COMP0_COMP_Pos) /*!< FPB FP_COMP0: COMP Mask */
\r
10412 #define FPB_FP_COMP0_Reserved1_Pos 29 /*!< FPB FP_COMP0: Reserved1 Position */
\r
10413 #define FPB_FP_COMP0_Reserved1_Msk (0x01UL << FPB_FP_COMP0_Reserved1_Pos) /*!< FPB FP_COMP0: Reserved1 Mask */
\r
10414 #define FPB_FP_COMP0_REPLACE_Pos 30 /*!< FPB FP_COMP0: REPLACE Position */
\r
10415 #define FPB_FP_COMP0_REPLACE_Msk (0x03UL << FPB_FP_COMP0_REPLACE_Pos) /*!< FPB FP_COMP0: REPLACE Mask */
\r
10417 // -------------------------------------- FPB_FP_COMP1 ------------------------------------------
\r
10418 #define FPB_FP_COMP1_ENABLE_Pos 0 /*!< FPB FP_COMP1: ENABLE Position */
\r
10419 #define FPB_FP_COMP1_ENABLE_Msk (0x01UL << FPB_FP_COMP1_ENABLE_Pos) /*!< FPB FP_COMP1: ENABLE Mask */
\r
10420 #define FPB_FP_COMP1_Reserved_Pos 1 /*!< FPB FP_COMP1: Reserved Position */
\r
10421 #define FPB_FP_COMP1_Reserved_Msk (0x01UL << FPB_FP_COMP1_Reserved_Pos) /*!< FPB FP_COMP1: Reserved Mask */
\r
10422 #define FPB_FP_COMP1_COMP_Pos 2 /*!< FPB FP_COMP1: COMP Position */
\r
10423 #define FPB_FP_COMP1_COMP_Msk (0x07ffffffUL << FPB_FP_COMP1_COMP_Pos) /*!< FPB FP_COMP1: COMP Mask */
\r
10424 #define FPB_FP_COMP1_Reserved1_Pos 29 /*!< FPB FP_COMP1: Reserved1 Position */
\r
10425 #define FPB_FP_COMP1_Reserved1_Msk (0x01UL << FPB_FP_COMP1_Reserved1_Pos) /*!< FPB FP_COMP1: Reserved1 Mask */
\r
10426 #define FPB_FP_COMP1_REPLACE_Pos 30 /*!< FPB FP_COMP1: REPLACE Position */
\r
10427 #define FPB_FP_COMP1_REPLACE_Msk (0x03UL << FPB_FP_COMP1_REPLACE_Pos) /*!< FPB FP_COMP1: REPLACE Mask */
\r
10429 // -------------------------------------- FPB_FP_COMP2 ------------------------------------------
\r
10430 #define FPB_FP_COMP2_ENABLE_Pos 0 /*!< FPB FP_COMP2: ENABLE Position */
\r
10431 #define FPB_FP_COMP2_ENABLE_Msk (0x01UL << FPB_FP_COMP2_ENABLE_Pos) /*!< FPB FP_COMP2: ENABLE Mask */
\r
10432 #define FPB_FP_COMP2_Reserved_Pos 1 /*!< FPB FP_COMP2: Reserved Position */
\r
10433 #define FPB_FP_COMP2_Reserved_Msk (0x01UL << FPB_FP_COMP2_Reserved_Pos) /*!< FPB FP_COMP2: Reserved Mask */
\r
10434 #define FPB_FP_COMP2_COMP_Pos 2 /*!< FPB FP_COMP2: COMP Position */
\r
10435 #define FPB_FP_COMP2_COMP_Msk (0x07ffffffUL << FPB_FP_COMP2_COMP_Pos) /*!< FPB FP_COMP2: COMP Mask */
\r
10436 #define FPB_FP_COMP2_Reserved1_Pos 29 /*!< FPB FP_COMP2: Reserved1 Position */
\r
10437 #define FPB_FP_COMP2_Reserved1_Msk (0x01UL << FPB_FP_COMP2_Reserved1_Pos) /*!< FPB FP_COMP2: Reserved1 Mask */
\r
10438 #define FPB_FP_COMP2_REPLACE_Pos 30 /*!< FPB FP_COMP2: REPLACE Position */
\r
10439 #define FPB_FP_COMP2_REPLACE_Msk (0x03UL << FPB_FP_COMP2_REPLACE_Pos) /*!< FPB FP_COMP2: REPLACE Mask */
\r
10441 // -------------------------------------- FPB_FP_COMP3 ------------------------------------------
\r
10442 #define FPB_FP_COMP3_ENABLE_Pos 0 /*!< FPB FP_COMP3: ENABLE Position */
\r
10443 #define FPB_FP_COMP3_ENABLE_Msk (0x01UL << FPB_FP_COMP3_ENABLE_Pos) /*!< FPB FP_COMP3: ENABLE Mask */
\r
10444 #define FPB_FP_COMP3_Reserved_Pos 1 /*!< FPB FP_COMP3: Reserved Position */
\r
10445 #define FPB_FP_COMP3_Reserved_Msk (0x01UL << FPB_FP_COMP3_Reserved_Pos) /*!< FPB FP_COMP3: Reserved Mask */
\r
10446 #define FPB_FP_COMP3_COMP_Pos 2 /*!< FPB FP_COMP3: COMP Position */
\r
10447 #define FPB_FP_COMP3_COMP_Msk (0x07ffffffUL << FPB_FP_COMP3_COMP_Pos) /*!< FPB FP_COMP3: COMP Mask */
\r
10448 #define FPB_FP_COMP3_Reserved1_Pos 29 /*!< FPB FP_COMP3: Reserved1 Position */
\r
10449 #define FPB_FP_COMP3_Reserved1_Msk (0x01UL << FPB_FP_COMP3_Reserved1_Pos) /*!< FPB FP_COMP3: Reserved1 Mask */
\r
10450 #define FPB_FP_COMP3_REPLACE_Pos 30 /*!< FPB FP_COMP3: REPLACE Position */
\r
10451 #define FPB_FP_COMP3_REPLACE_Msk (0x03UL << FPB_FP_COMP3_REPLACE_Pos) /*!< FPB FP_COMP3: REPLACE Mask */
\r
10453 // -------------------------------------- FPB_FP_COMP4 ------------------------------------------
\r
10454 #define FPB_FP_COMP4_ENABLE_Pos 0 /*!< FPB FP_COMP4: ENABLE Position */
\r
10455 #define FPB_FP_COMP4_ENABLE_Msk (0x01UL << FPB_FP_COMP4_ENABLE_Pos) /*!< FPB FP_COMP4: ENABLE Mask */
\r
10456 #define FPB_FP_COMP4_Reserved_Pos 1 /*!< FPB FP_COMP4: Reserved Position */
\r
10457 #define FPB_FP_COMP4_Reserved_Msk (0x01UL << FPB_FP_COMP4_Reserved_Pos) /*!< FPB FP_COMP4: Reserved Mask */
\r
10458 #define FPB_FP_COMP4_COMP_Pos 2 /*!< FPB FP_COMP4: COMP Position */
\r
10459 #define FPB_FP_COMP4_COMP_Msk (0x07ffffffUL << FPB_FP_COMP4_COMP_Pos) /*!< FPB FP_COMP4: COMP Mask */
\r
10460 #define FPB_FP_COMP4_Reserved1_Pos 29 /*!< FPB FP_COMP4: Reserved1 Position */
\r
10461 #define FPB_FP_COMP4_Reserved1_Msk (0x01UL << FPB_FP_COMP4_Reserved1_Pos) /*!< FPB FP_COMP4: Reserved1 Mask */
\r
10462 #define FPB_FP_COMP4_REPLACE_Pos 30 /*!< FPB FP_COMP4: REPLACE Position */
\r
10463 #define FPB_FP_COMP4_REPLACE_Msk (0x03UL << FPB_FP_COMP4_REPLACE_Pos) /*!< FPB FP_COMP4: REPLACE Mask */
\r
10465 // -------------------------------------- FPB_FP_COMP5 ------------------------------------------
\r
10466 #define FPB_FP_COMP5_ENABLE_Pos 0 /*!< FPB FP_COMP5: ENABLE Position */
\r
10467 #define FPB_FP_COMP5_ENABLE_Msk (0x01UL << FPB_FP_COMP5_ENABLE_Pos) /*!< FPB FP_COMP5: ENABLE Mask */
\r
10468 #define FPB_FP_COMP5_Reserved_Pos 1 /*!< FPB FP_COMP5: Reserved Position */
\r
10469 #define FPB_FP_COMP5_Reserved_Msk (0x01UL << FPB_FP_COMP5_Reserved_Pos) /*!< FPB FP_COMP5: Reserved Mask */
\r
10470 #define FPB_FP_COMP5_COMP_Pos 2 /*!< FPB FP_COMP5: COMP Position */
\r
10471 #define FPB_FP_COMP5_COMP_Msk (0x07ffffffUL << FPB_FP_COMP5_COMP_Pos) /*!< FPB FP_COMP5: COMP Mask */
\r
10472 #define FPB_FP_COMP5_Reserved1_Pos 29 /*!< FPB FP_COMP5: Reserved1 Position */
\r
10473 #define FPB_FP_COMP5_Reserved1_Msk (0x01UL << FPB_FP_COMP5_Reserved1_Pos) /*!< FPB FP_COMP5: Reserved1 Mask */
\r
10474 #define FPB_FP_COMP5_REPLACE_Pos 30 /*!< FPB FP_COMP5: REPLACE Position */
\r
10475 #define FPB_FP_COMP5_REPLACE_Msk (0x03UL << FPB_FP_COMP5_REPLACE_Pos) /*!< FPB FP_COMP5: REPLACE Mask */
\r
10477 // -------------------------------------- FPB_FP_COMP6 ------------------------------------------
\r
10478 #define FPB_FP_COMP6_ENABLE_Pos 0 /*!< FPB FP_COMP6: ENABLE Position */
\r
10479 #define FPB_FP_COMP6_ENABLE_Msk (0x01UL << FPB_FP_COMP6_ENABLE_Pos) /*!< FPB FP_COMP6: ENABLE Mask */
\r
10480 #define FPB_FP_COMP6_Reserved_Pos 1 /*!< FPB FP_COMP6: Reserved Position */
\r
10481 #define FPB_FP_COMP6_Reserved_Msk (0x01UL << FPB_FP_COMP6_Reserved_Pos) /*!< FPB FP_COMP6: Reserved Mask */
\r
10482 #define FPB_FP_COMP6_COMP_Pos 2 /*!< FPB FP_COMP6: COMP Position */
\r
10483 #define FPB_FP_COMP6_COMP_Msk (0x07ffffffUL << FPB_FP_COMP6_COMP_Pos) /*!< FPB FP_COMP6: COMP Mask */
\r
10484 #define FPB_FP_COMP6_Reserved1_Pos 29 /*!< FPB FP_COMP6: Reserved1 Position */
\r
10485 #define FPB_FP_COMP6_Reserved1_Msk (0x01UL << FPB_FP_COMP6_Reserved1_Pos) /*!< FPB FP_COMP6: Reserved1 Mask */
\r
10486 #define FPB_FP_COMP6_REPLACE_Pos 30 /*!< FPB FP_COMP6: REPLACE Position */
\r
10487 #define FPB_FP_COMP6_REPLACE_Msk (0x03UL << FPB_FP_COMP6_REPLACE_Pos) /*!< FPB FP_COMP6: REPLACE Mask */
\r
10489 // -------------------------------------- FPB_FP_COMP7 ------------------------------------------
\r
10490 #define FPB_FP_COMP7_ENABLE_Pos 0 /*!< FPB FP_COMP7: ENABLE Position */
\r
10491 #define FPB_FP_COMP7_ENABLE_Msk (0x01UL << FPB_FP_COMP7_ENABLE_Pos) /*!< FPB FP_COMP7: ENABLE Mask */
\r
10492 #define FPB_FP_COMP7_Reserved_Pos 1 /*!< FPB FP_COMP7: Reserved Position */
\r
10493 #define FPB_FP_COMP7_Reserved_Msk (0x01UL << FPB_FP_COMP7_Reserved_Pos) /*!< FPB FP_COMP7: Reserved Mask */
\r
10494 #define FPB_FP_COMP7_COMP_Pos 2 /*!< FPB FP_COMP7: COMP Position */
\r
10495 #define FPB_FP_COMP7_COMP_Msk (0x07ffffffUL << FPB_FP_COMP7_COMP_Pos) /*!< FPB FP_COMP7: COMP Mask */
\r
10496 #define FPB_FP_COMP7_Reserved1_Pos 29 /*!< FPB FP_COMP7: Reserved1 Position */
\r
10497 #define FPB_FP_COMP7_Reserved1_Msk (0x01UL << FPB_FP_COMP7_Reserved1_Pos) /*!< FPB FP_COMP7: Reserved1 Mask */
\r
10498 #define FPB_FP_COMP7_REPLACE_Pos 30 /*!< FPB FP_COMP7: REPLACE Position */
\r
10499 #define FPB_FP_COMP7_REPLACE_Msk (0x03UL << FPB_FP_COMP7_REPLACE_Pos) /*!< FPB FP_COMP7: REPLACE Mask */
\r
10501 // --------------------------------------- FPB_FPBPID4 ------------------------------------------
\r
10502 #define FPB_FPBPID4_PID4_Pos 0 /*!< FPB FPBPID4: PID4 Position */
\r
10503 #define FPB_FPBPID4_PID4_Msk (0xffffffffUL << FPB_FPBPID4_PID4_Pos) /*!< FPB FPBPID4: PID4 Mask */
\r
10505 // --------------------------------------- FPB_FPBPID5 ------------------------------------------
\r
10506 #define FPB_FPBPID5_PID5_Pos 0 /*!< FPB FPBPID5: PID5 Position */
\r
10507 #define FPB_FPBPID5_PID5_Msk (0xffffffffUL << FPB_FPBPID5_PID5_Pos) /*!< FPB FPBPID5: PID5 Mask */
\r
10509 // --------------------------------------- FPB_FPBPID6 ------------------------------------------
\r
10510 #define FPB_FPBPID6_PID6_Pos 0 /*!< FPB FPBPID6: PID6 Position */
\r
10511 #define FPB_FPBPID6_PID6_Msk (0xffffffffUL << FPB_FPBPID6_PID6_Pos) /*!< FPB FPBPID6: PID6 Mask */
\r
10513 // --------------------------------------- FPB_FPBPID7 ------------------------------------------
\r
10514 #define FPB_FPBPID7_PID7_Pos 0 /*!< FPB FPBPID7: PID7 Position */
\r
10515 #define FPB_FPBPID7_PID7_Msk (0xffffffffUL << FPB_FPBPID7_PID7_Pos) /*!< FPB FPBPID7: PID7 Mask */
\r
10517 // --------------------------------------- FPB_FPBPID0 ------------------------------------------
\r
10518 #define FPB_FPBPID0_PID0_Pos 0 /*!< FPB FPBPID0: PID0 Position */
\r
10519 #define FPB_FPBPID0_PID0_Msk (0xffffffffUL << FPB_FPBPID0_PID0_Pos) /*!< FPB FPBPID0: PID0 Mask */
\r
10521 // --------------------------------------- FPB_FPBPID1 ------------------------------------------
\r
10522 #define FPB_FPBPID1_PID1_Pos 0 /*!< FPB FPBPID1: PID1 Position */
\r
10523 #define FPB_FPBPID1_PID1_Msk (0xffffffffUL << FPB_FPBPID1_PID1_Pos) /*!< FPB FPBPID1: PID1 Mask */
\r
10525 // --------------------------------------- FPB_FPBPID2 ------------------------------------------
\r
10526 #define FPB_FPBPID2_PID2_Pos 0 /*!< FPB FPBPID2: PID2 Position */
\r
10527 #define FPB_FPBPID2_PID2_Msk (0xffffffffUL << FPB_FPBPID2_PID2_Pos) /*!< FPB FPBPID2: PID2 Mask */
\r
10529 // --------------------------------------- FPB_FPBPID3 ------------------------------------------
\r
10530 #define FPB_FPBPID3_PID3_Pos 0 /*!< FPB FPBPID3: PID3 Position */
\r
10531 #define FPB_FPBPID3_PID3_Msk (0xffffffffUL << FPB_FPBPID3_PID3_Pos) /*!< FPB FPBPID3: PID3 Mask */
\r
10533 // --------------------------------------- FPB_FPBCID0 ------------------------------------------
\r
10534 #define FPB_FPBCID0_CID0_Pos 0 /*!< FPB FPBCID0: CID0 Position */
\r
10535 #define FPB_FPBCID0_CID0_Msk (0xffffffffUL << FPB_FPBCID0_CID0_Pos) /*!< FPB FPBCID0: CID0 Mask */
\r
10537 // --------------------------------------- FPB_FPBCID1 ------------------------------------------
\r
10538 #define FPB_FPBCID1_CID1_Pos 0 /*!< FPB FPBCID1: CID1 Position */
\r
10539 #define FPB_FPBCID1_CID1_Msk (0xffffffffUL << FPB_FPBCID1_CID1_Pos) /*!< FPB FPBCID1: CID1 Mask */
\r
10541 // --------------------------------------- FPB_FPBCID2 ------------------------------------------
\r
10542 #define FPB_FPBCID2_CID2_Pos 0 /*!< FPB FPBCID2: CID2 Position */
\r
10543 #define FPB_FPBCID2_CID2_Msk (0xffffffffUL << FPB_FPBCID2_CID2_Pos) /*!< FPB FPBCID2: CID2 Mask */
\r
10545 // --------------------------------------- FPB_FPBCID3 ------------------------------------------
\r
10546 #define FPB_FPBCID3_CID3_Pos 0 /*!< FPB FPBCID3: CID3 Position */
\r
10547 #define FPB_FPBCID3_CID3_Msk (0xffffffffUL << FPB_FPBCID3_CID3_Pos) /*!< FPB FPBCID3: CID3 Mask */
\r
10551 /*** LEDTS0 Bit Fileds *******************/
\r
10552 /***************************************************************************/
\r
10555 /* LEDTS_ID = Module Identification Register*/
\r
10556 #define LEDTS_ID_MOD_REV_Pos (0U)
\r
10557 #define LEDTS_ID_MOD_REV_Msk (0x000000FFU << LEDTS_ID_MOD_REV_Pos)
\r
10559 #define LEDTS_ID_MOD_TYPE_Pos (8U)
\r
10560 #define LEDTS_ID_MOD_TYPE_Msk (0x000000FFU << LEDTS_ID_MOD_TYPE_Pos)
\r
10562 #define LEDTS_ID_MOD_NUMBER_Pos (16U)
\r
10563 #define LEDTS_ID_MOD_NUMBER_Msk (0x0000FFFFU << LEDTS_ID_MOD_NUMBER_Pos)
\r
10565 /* LEDTS_GLOBCTL = Global Control Register*/
\r
10566 #define LEDTS_GLOBCTL_TS_EN_Pos (0U)
\r
10567 #define LEDTS_GLOBCTL_TS_EN_Msk (0x00000001U << LEDTS_GLOBCTL_TS_EN_Pos)
\r
10569 #define LEDTS_GLOBCTL_LD_EN_Pos (1U)
\r
10570 #define LEDTS_GLOBCTL_LD_EN_Msk (0x00000001U << LEDTS_GLOBCTL_LD_EN_Pos)
\r
10572 #define LEDTS_GLOBCTL_CMTR_Pos (2U)
\r
10573 #define LEDTS_GLOBCTL_CMTR_Msk (0x00000001U << LEDTS_GLOBCTL_CMTR_Pos)
\r
10575 #define LEDTS_GLOBCTL_ENSYNC_Pos (3U)
\r
10576 #define LEDTS_GLOBCTL_ENSYNC_Msk (0x00000001U << LEDTS_GLOBCTL_ENSYNC_Pos)
\r
10578 #define LEDTS_GLOBCTL_SUSCFG_Pos (8U)
\r
10579 #define LEDTS_GLOBCTL_SUSCFG_Msk (0x00000001U << LEDTS_GLOBCTL_SUSCFG_Pos)
\r
10581 #define LEDTS_GLOBCTL_MASKVAL_Pos (9U)
\r
10582 #define LEDTS_GLOBCTL_MASKVAL_Msk (0x00000007U << LEDTS_GLOBCTL_MASKVAL_Pos)
\r
10584 #define LEDTS_GLOBCTL_FENVAL_Pos (12U)
\r
10585 #define LEDTS_GLOBCTL_FENVAL_Msk (0x00000001U << LEDTS_GLOBCTL_FENVAL_Pos)
\r
10587 #define LEDTS_GLOBCTL_ITS_EN_Pos (13U)
\r
10588 #define LEDTS_GLOBCTL_ITS_EN_Msk (0x00000001U << LEDTS_GLOBCTL_ITS_EN_Pos)
\r
10590 #define LEDTS_GLOBCTL_ITF_EN_Pos (14U)
\r
10591 #define LEDTS_GLOBCTL_ITF_EN_Msk (0x00000001U << LEDTS_GLOBCTL_ITF_EN_Pos)
\r
10593 #define LEDTS_GLOBCTL_ITP_EN_Pos (15U)
\r
10594 #define LEDTS_GLOBCTL_ITP_EN_Msk (0x00000001U << LEDTS_GLOBCTL_ITP_EN_Pos)
\r
10596 #define LEDTS_GLOBCTL_CLK_PS_Pos (16U)
\r
10597 #define LEDTS_GLOBCTL_CLK_PS_Msk (0x0000FFFFU << LEDTS_GLOBCTL_CLK_PS_Pos)
\r
10599 /* LEDTS_FNCTL = Function Control Register*/
\r
10600 #define LEDTS_FNCTL_PADT_Pos (0U)
\r
10601 #define LEDTS_FNCTL_PADT_Msk (0x00000007U << LEDTS_FNCTL_PADT_Pos)
\r
10603 #define LEDTS_FNCTL_PADTSW_Pos (3U)
\r
10604 #define LEDTS_FNCTL_PADTSW_Msk (0x00000001U << LEDTS_FNCTL_PADTSW_Pos)
\r
10606 #define LEDTS_FNCTL_EPULL_Pos (4U)
\r
10607 #define LEDTS_FNCTL_EPULL_Msk (0x00000001U << LEDTS_FNCTL_EPULL_Pos)
\r
10609 #define LEDTS_FNCTL_FNCOL_Pos (5U)
\r
10610 #define LEDTS_FNCTL_FNCOL_Msk (0x00000007U << LEDTS_FNCTL_FNCOL_Pos)
\r
10612 #define LEDTS_FNCTL_ACCCNT_Pos (16U)
\r
10613 #define LEDTS_FNCTL_ACCCNT_Msk (0x0000000FU << LEDTS_FNCTL_ACCCNT_Pos)
\r
10615 #define LEDTS_FNCTL_TSCCMP_Pos (20U)
\r
10616 #define LEDTS_FNCTL_TSCCMP_Msk (0x00000001U << LEDTS_FNCTL_TSCCMP_Pos)
\r
10618 #define LEDTS_FNCTL_TSOEXT_Pos (21U)
\r
10619 #define LEDTS_FNCTL_TSOEXT_Msk (0x00000003U << LEDTS_FNCTL_TSOEXT_Pos)
\r
10621 #define LEDTS_FNCTL_TSCTRR_Pos (23U)
\r
10622 #define LEDTS_FNCTL_TSCTRR_Msk (0x00000001U << LEDTS_FNCTL_TSCTRR_Pos)
\r
10624 #define LEDTS_FNCTL_TSCTRSAT_Pos (24U)
\r
10625 #define LEDTS_FNCTL_TSCTRSAT_Msk (0x00000001U << LEDTS_FNCTL_TSCTRSAT_Pos)
\r
10627 #define LEDTS_FNCTL_NR_TSIN_Pos (25U)
\r
10628 #define LEDTS_FNCTL_NR_TSIN_Msk (0x00000007U << LEDTS_FNCTL_NR_TSIN_Pos)
\r
10630 #define LEDTS_FNCTL_COLLEV_Pos (28U)
\r
10631 #define LEDTS_FNCTL_COLLEV_Msk (0x00000001U << LEDTS_FNCTL_COLLEV_Pos)
\r
10633 #define LEDTS_FNCTL_NR_LEDCOL_Pos (29U)
\r
10634 #define LEDTS_FNCTL_NR_LEDCOL_Msk (0x00000007U << LEDTS_FNCTL_NR_LEDCOL_Pos)
\r
10636 /* LEDTS_EVFR = Event Flag Register*/
\r
10637 #define LEDTS_EVFR_TSF_Pos (0U)
\r
10638 #define LEDTS_EVFR_TSF_Msk (0x00000001U << LEDTS_EVFR_TSF_Pos)
\r
10640 #define LEDTS_EVFR_TFF_Pos (1U)
\r
10641 #define LEDTS_EVFR_TFF_Msk (0x00000001U << LEDTS_EVFR_TFF_Pos)
\r
10643 #define LEDTS_EVFR_TPF_Pos (2U)
\r
10644 #define LEDTS_EVFR_TPF_Msk (0x00000001U << LEDTS_EVFR_TPF_Pos)
\r
10646 #define LEDTS_EVFR_TSCTROVF_Pos (3U)
\r
10647 #define LEDTS_EVFR_TSCTROVF_Msk (0x00000001U << LEDTS_EVFR_TSCTROVF_Pos)
\r
10649 #define LEDTS_EVFR_CTSF_Pos (16U)
\r
10650 #define LEDTS_EVFR_CTSF_Msk (0x00000001U << LEDTS_EVFR_CTSF_Pos)
\r
10652 #define LEDTS_EVFR_CTFF_Pos (17U)
\r
10653 #define LEDTS_EVFR_CTFF_Msk (0x00000001U << LEDTS_EVFR_CTFF_Pos)
\r
10655 #define LEDTS_EVFR_CTPF_Pos (18U)
\r
10656 #define LEDTS_EVFR_CTPF_Msk (0x00000001U << LEDTS_EVFR_CTPF_Pos)
\r
10658 /* LEDTS_TSVAL = Touch-sense TS-Counter Value*/
\r
10659 #define LEDTS_TSVAL_TSCTRVALR_Pos (0U)
\r
10660 #define LEDTS_TSVAL_TSCTRVALR_Msk (0x0000FFFFU << LEDTS_TSVAL_TSCTRVALR_Pos)
\r
10662 #define LEDTS_TSVAL_TSCTRVAL_Pos (16U)
\r
10663 #define LEDTS_TSVAL_TSCTRVAL_Msk (0x0000FFFFU << LEDTS_TSVAL_TSCTRVAL_Pos)
\r
10665 /* LEDTS_LINE0 = Line Pattern Register 0*/
\r
10666 #define LEDTS_LINE0_LINE_0_Pos (0U)
\r
10667 #define LEDTS_LINE0_LINE_0_Msk (0x000000FFU << LEDTS_LINE0_LINE_0_Pos)
\r
10669 #define LEDTS_LINE0_LINE_1_Pos (8U)
\r
10670 #define LEDTS_LINE0_LINE_1_Msk (0x000000FFU << LEDTS_LINE0_LINE_1_Pos)
\r
10672 #define LEDTS_LINE0_LINE_2_Pos (16U)
\r
10673 #define LEDTS_LINE0_LINE_2_Msk (0x000000FFU << LEDTS_LINE0_LINE_2_Pos)
\r
10675 #define LEDTS_LINE0_LINE_3_Pos (24U)
\r
10676 #define LEDTS_LINE0_LINE_3_Msk (0x000000FFU << LEDTS_LINE0_LINE_3_Pos)
\r
10678 /* LEDTS_LINE1 = Line Pattern Register 1*/
\r
10679 #define LEDTS_LINE1_LINE_4_Pos (0U)
\r
10680 #define LEDTS_LINE1_LINE_4_Msk (0x000000FFU << LEDTS_LINE1_LINE_4_Pos)
\r
10682 #define LEDTS_LINE1_LINE_5_Pos (8U)
\r
10683 #define LEDTS_LINE1_LINE_5_Msk (0x000000FFU << LEDTS_LINE1_LINE_5_Pos)
\r
10685 #define LEDTS_LINE1_LINE_6_Pos (16U)
\r
10686 #define LEDTS_LINE1_LINE_6_Msk (0x000000FFU << LEDTS_LINE1_LINE_6_Pos)
\r
10688 #define LEDTS_LINE1_LINE_A_Pos (24U)
\r
10689 #define LEDTS_LINE1_LINE_A_Msk (0x000000FFU << LEDTS_LINE1_LINE_A_Pos)
\r
10691 /* LEDTS_LDCMP0 = LED Compare Register 0*/
\r
10692 #define LEDTS_LDCMP0_CMP_LD0_Pos (0U)
\r
10693 #define LEDTS_LDCMP0_CMP_LD0_Msk (0x000000FFU << LEDTS_LDCMP0_CMP_LD0_Pos)
\r
10695 #define LEDTS_LDCMP0_CMP_LD1_Pos (8U)
\r
10696 #define LEDTS_LDCMP0_CMP_LD1_Msk (0x000000FFU << LEDTS_LDCMP0_CMP_LD1_Pos)
\r
10698 #define LEDTS_LDCMP0_CMP_LD2_Pos (16U)
\r
10699 #define LEDTS_LDCMP0_CMP_LD2_Msk (0x000000FFU << LEDTS_LDCMP0_CMP_LD2_Pos)
\r
10701 #define LEDTS_LDCMP0_CMP_LD3_Pos (24U)
\r
10702 #define LEDTS_LDCMP0_CMP_LD3_Msk (0x000000FFU << LEDTS_LDCMP0_CMP_LD3_Pos)
\r
10704 /* LEDTS_LDCMP1 = LED Compare Register 1*/
\r
10705 #define LEDTS_LDCMP1_CMP_LD4_Pos (0U)
\r
10706 #define LEDTS_LDCMP1_CMP_LD4_Msk (0x000000FFU << LEDTS_LDCMP1_CMP_LD4_Pos)
\r
10708 #define LEDTS_LDCMP1_CMP_LD5_Pos (8U)
\r
10709 #define LEDTS_LDCMP1_CMP_LD5_Msk (0x000000FFU << LEDTS_LDCMP1_CMP_LD5_Pos)
\r
10711 #define LEDTS_LDCMP1_CMP_LD6_Pos (16U)
\r
10712 #define LEDTS_LDCMP1_CMP_LD6_Msk (0x000000FFU << LEDTS_LDCMP1_CMP_LD6_Pos)
\r
10714 #define LEDTS_LDCMP1_CMP_LDATSCOM_Pos (24U)
\r
10715 #define LEDTS_LDCMP1_CMP_LDATSCOM_Msk (0x000000FFU << LEDTS_LDCMP1_CMP_LDATSCOM_Pos)
\r
10717 /* LEDTS_TSCMP0 = Touch-sense Compare Register 0*/
\r
10718 #define LEDTS_TSCMP0_CMP_TS0_Pos (0U)
\r
10719 #define LEDTS_TSCMP0_CMP_TS0_Msk (0x000000FFU << LEDTS_TSCMP0_CMP_TS0_Pos)
\r
10721 #define LEDTS_TSCMP0_CMP_TS1_Pos (8U)
\r
10722 #define LEDTS_TSCMP0_CMP_TS1_Msk (0x000000FFU << LEDTS_TSCMP0_CMP_TS1_Pos)
\r
10724 #define LEDTS_TSCMP0_CMP_TS2_Pos (16U)
\r
10725 #define LEDTS_TSCMP0_CMP_TS2_Msk (0x000000FFU << LEDTS_TSCMP0_CMP_TS2_Pos)
\r
10727 #define LEDTS_TSCMP0_CMP_TS3_Pos (24U)
\r
10728 #define LEDTS_TSCMP0_CMP_TS3_Msk (0x000000FFU << LEDTS_TSCMP0_CMP_TS3_Pos)
\r
10730 /* LEDTS_TSCMP1 = Touch-sense Compare Register 1*/
\r
10731 #define LEDTS_TSCMP1_CMP_TS4_Pos (0U)
\r
10732 #define LEDTS_TSCMP1_CMP_TS4_Msk (0x000000FFU << LEDTS_TSCMP1_CMP_TS4_Pos)
\r
10734 #define LEDTS_TSCMP1_CMP_TS5_Pos (8U)
\r
10735 #define LEDTS_TSCMP1_CMP_TS5_Msk (0x000000FFU << LEDTS_TSCMP1_CMP_TS5_Pos)
\r
10737 #define LEDTS_TSCMP1_CMP_TS6_Pos (16U)
\r
10738 #define LEDTS_TSCMP1_CMP_TS6_Msk (0x000000FFU << LEDTS_TSCMP1_CMP_TS6_Pos)
\r
10740 #define LEDTS_TSCMP1_CMP_TS7_Pos (24U)
\r
10741 #define LEDTS_TSCMP1_CMP_TS7_Msk (0x000000FFU << LEDTS_TSCMP1_CMP_TS7_Pos)
\r
10745 /*** PBAx Bit Fileds *******************/
\r
10746 /***************************************************************************/
\r
10749 /* PBA_STS = Peripheral Bridge Status Register*/
\r
10750 #define PBA_STS_WERR_Pos (0U)
\r
10751 #define PBA_STS_WERR_Msk (0x00000001U << PBA_STS_WERR_Pos)
\r
10753 /* PBA_WADDR = PBA Write Error Address Register*/
\r
10754 #define PBA_WADDR_WADDR_Pos (0U)
\r
10755 #define PBA_WADDR_WADDR_Msk (0xFFFFFFFFU << PBA_WADDR_WADDR_Pos)
\r
10759 /*** PMU0 Bit Fileds *******************/
\r
10760 /***************************************************************************/
\r
10763 /* PMU_ID = PMU0 Identification Register*/
\r
10764 #define PMU_ID_MOD_REV_Pos (0U)
\r
10765 #define PMU_ID_MOD_REV_Msk (0x000000FFU << PMU_ID_MOD_REV_Pos)
\r
10767 #define PMU_ID_MOD_TYPE_Pos (8U)
\r
10768 #define PMU_ID_MOD_TYPE_Msk (0x000000FFU << PMU_ID_MOD_TYPE_Pos)
\r
10770 #define PMU_ID_MOD_NUMBER_Pos (16U)
\r
10771 #define PMU_ID_MOD_NUMBER_Msk (0x0000FFFFU << PMU_ID_MOD_NUMBER_Pos)
\r
10775 // ------------------------------------------------------------------------------------------------
\r
10776 // ----- PORT0 Position & Mask -----
\r
10777 // ------------------------------------------------------------------------------------------------
\r
10780 // ---------------------------------------- PORT0_OUT -------------------------------------------
\r
10781 #define PORT0_OUT_P0_Pos 0 /*!< PORT0 OUT: P0 Position */
\r
10782 #define PORT0_OUT_P0_Msk (0x01UL << PORT0_OUT_P0_Pos) /*!< PORT0 OUT: P0 Mask */
\r
10783 #define PORT0_OUT_P1_Pos 1 /*!< PORT0 OUT: P1 Position */
\r
10784 #define PORT0_OUT_P1_Msk (0x01UL << PORT0_OUT_P1_Pos) /*!< PORT0 OUT: P1 Mask */
\r
10785 #define PORT0_OUT_P2_Pos 2 /*!< PORT0 OUT: P2 Position */
\r
10786 #define PORT0_OUT_P2_Msk (0x01UL << PORT0_OUT_P2_Pos) /*!< PORT0 OUT: P2 Mask */
\r
10787 #define PORT0_OUT_P3_Pos 3 /*!< PORT0 OUT: P3 Position */
\r
10788 #define PORT0_OUT_P3_Msk (0x01UL << PORT0_OUT_P3_Pos) /*!< PORT0 OUT: P3 Mask */
\r
10789 #define PORT0_OUT_P4_Pos 4 /*!< PORT0 OUT: P4 Position */
\r
10790 #define PORT0_OUT_P4_Msk (0x01UL << PORT0_OUT_P4_Pos) /*!< PORT0 OUT: P4 Mask */
\r
10791 #define PORT0_OUT_P5_Pos 5 /*!< PORT0 OUT: P5 Position */
\r
10792 #define PORT0_OUT_P5_Msk (0x01UL << PORT0_OUT_P5_Pos) /*!< PORT0 OUT: P5 Mask */
\r
10793 #define PORT0_OUT_P6_Pos 6 /*!< PORT0 OUT: P6 Position */
\r
10794 #define PORT0_OUT_P6_Msk (0x01UL << PORT0_OUT_P6_Pos) /*!< PORT0 OUT: P6 Mask */
\r
10795 #define PORT0_OUT_P7_Pos 7 /*!< PORT0 OUT: P7 Position */
\r
10796 #define PORT0_OUT_P7_Msk (0x01UL << PORT0_OUT_P7_Pos) /*!< PORT0 OUT: P7 Mask */
\r
10797 #define PORT0_OUT_P8_Pos 8 /*!< PORT0 OUT: P8 Position */
\r
10798 #define PORT0_OUT_P8_Msk (0x01UL << PORT0_OUT_P8_Pos) /*!< PORT0 OUT: P8 Mask */
\r
10799 #define PORT0_OUT_P9_Pos 9 /*!< PORT0 OUT: P9 Position */
\r
10800 #define PORT0_OUT_P9_Msk (0x01UL << PORT0_OUT_P9_Pos) /*!< PORT0 OUT: P9 Mask */
\r
10801 #define PORT0_OUT_P10_Pos 10 /*!< PORT0 OUT: P10 Position */
\r
10802 #define PORT0_OUT_P10_Msk (0x01UL << PORT0_OUT_P10_Pos) /*!< PORT0 OUT: P10 Mask */
\r
10803 #define PORT0_OUT_P11_Pos 11 /*!< PORT0 OUT: P11 Position */
\r
10804 #define PORT0_OUT_P11_Msk (0x01UL << PORT0_OUT_P11_Pos) /*!< PORT0 OUT: P11 Mask */
\r
10805 #define PORT0_OUT_P12_Pos 12 /*!< PORT0 OUT: P12 Position */
\r
10806 #define PORT0_OUT_P12_Msk (0x01UL << PORT0_OUT_P12_Pos) /*!< PORT0 OUT: P12 Mask */
\r
10807 #define PORT0_OUT_P13_Pos 13 /*!< PORT0 OUT: P13 Position */
\r
10808 #define PORT0_OUT_P13_Msk (0x01UL << PORT0_OUT_P13_Pos) /*!< PORT0 OUT: P13 Mask */
\r
10809 #define PORT0_OUT_P14_Pos 14 /*!< PORT0 OUT: P14 Position */
\r
10810 #define PORT0_OUT_P14_Msk (0x01UL << PORT0_OUT_P14_Pos) /*!< PORT0 OUT: P14 Mask */
\r
10811 #define PORT0_OUT_P15_Pos 15 /*!< PORT0 OUT: P15 Position */
\r
10812 #define PORT0_OUT_P15_Msk (0x01UL << PORT0_OUT_P15_Pos) /*!< PORT0 OUT: P15 Mask */
\r
10814 // ---------------------------------------- PORT0_OMR -------------------------------------------
\r
10815 #define PORT0_OMR_PS0_Pos 0 /*!< PORT0 OMR: PS0 Position */
\r
10816 #define PORT0_OMR_PS0_Msk (0x01UL << PORT0_OMR_PS0_Pos) /*!< PORT0 OMR: PS0 Mask */
\r
10817 #define PORT0_OMR_PS1_Pos 1 /*!< PORT0 OMR: PS1 Position */
\r
10818 #define PORT0_OMR_PS1_Msk (0x01UL << PORT0_OMR_PS1_Pos) /*!< PORT0 OMR: PS1 Mask */
\r
10819 #define PORT0_OMR_PS2_Pos 2 /*!< PORT0 OMR: PS2 Position */
\r
10820 #define PORT0_OMR_PS2_Msk (0x01UL << PORT0_OMR_PS2_Pos) /*!< PORT0 OMR: PS2 Mask */
\r
10821 #define PORT0_OMR_PS3_Pos 3 /*!< PORT0 OMR: PS3 Position */
\r
10822 #define PORT0_OMR_PS3_Msk (0x01UL << PORT0_OMR_PS3_Pos) /*!< PORT0 OMR: PS3 Mask */
\r
10823 #define PORT0_OMR_PS4_Pos 4 /*!< PORT0 OMR: PS4 Position */
\r
10824 #define PORT0_OMR_PS4_Msk (0x01UL << PORT0_OMR_PS4_Pos) /*!< PORT0 OMR: PS4 Mask */
\r
10825 #define PORT0_OMR_PS5_Pos 5 /*!< PORT0 OMR: PS5 Position */
\r
10826 #define PORT0_OMR_PS5_Msk (0x01UL << PORT0_OMR_PS5_Pos) /*!< PORT0 OMR: PS5 Mask */
\r
10827 #define PORT0_OMR_PS6_Pos 6 /*!< PORT0 OMR: PS6 Position */
\r
10828 #define PORT0_OMR_PS6_Msk (0x01UL << PORT0_OMR_PS6_Pos) /*!< PORT0 OMR: PS6 Mask */
\r
10829 #define PORT0_OMR_PS7_Pos 7 /*!< PORT0 OMR: PS7 Position */
\r
10830 #define PORT0_OMR_PS7_Msk (0x01UL << PORT0_OMR_PS7_Pos) /*!< PORT0 OMR: PS7 Mask */
\r
10831 #define PORT0_OMR_PS8_Pos 8 /*!< PORT0 OMR: PS8 Position */
\r
10832 #define PORT0_OMR_PS8_Msk (0x01UL << PORT0_OMR_PS8_Pos) /*!< PORT0 OMR: PS8 Mask */
\r
10833 #define PORT0_OMR_PS9_Pos 9 /*!< PORT0 OMR: PS9 Position */
\r
10834 #define PORT0_OMR_PS9_Msk (0x01UL << PORT0_OMR_PS9_Pos) /*!< PORT0 OMR: PS9 Mask */
\r
10835 #define PORT0_OMR_PS10_Pos 10 /*!< PORT0 OMR: PS10 Position */
\r
10836 #define PORT0_OMR_PS10_Msk (0x01UL << PORT0_OMR_PS10_Pos) /*!< PORT0 OMR: PS10 Mask */
\r
10837 #define PORT0_OMR_PS11_Pos 11 /*!< PORT0 OMR: PS11 Position */
\r
10838 #define PORT0_OMR_PS11_Msk (0x01UL << PORT0_OMR_PS11_Pos) /*!< PORT0 OMR: PS11 Mask */
\r
10839 #define PORT0_OMR_PS12_Pos 12 /*!< PORT0 OMR: PS12 Position */
\r
10840 #define PORT0_OMR_PS12_Msk (0x01UL << PORT0_OMR_PS12_Pos) /*!< PORT0 OMR: PS12 Mask */
\r
10841 #define PORT0_OMR_PS13_Pos 13 /*!< PORT0 OMR: PS13 Position */
\r
10842 #define PORT0_OMR_PS13_Msk (0x01UL << PORT0_OMR_PS13_Pos) /*!< PORT0 OMR: PS13 Mask */
\r
10843 #define PORT0_OMR_PS14_Pos 14 /*!< PORT0 OMR: PS14 Position */
\r
10844 #define PORT0_OMR_PS14_Msk (0x01UL << PORT0_OMR_PS14_Pos) /*!< PORT0 OMR: PS14 Mask */
\r
10845 #define PORT0_OMR_PS15_Pos 15 /*!< PORT0 OMR: PS15 Position */
\r
10846 #define PORT0_OMR_PS15_Msk (0x01UL << PORT0_OMR_PS15_Pos) /*!< PORT0 OMR: PS15 Mask */
\r
10847 #define PORT0_OMR_PR0_Pos 16 /*!< PORT0 OMR: PR0 Position */
\r
10848 #define PORT0_OMR_PR0_Msk (0x01UL << PORT0_OMR_PR0_Pos) /*!< PORT0 OMR: PR0 Mask */
\r
10849 #define PORT0_OMR_PR1_Pos 17 /*!< PORT0 OMR: PR1 Position */
\r
10850 #define PORT0_OMR_PR1_Msk (0x01UL << PORT0_OMR_PR1_Pos) /*!< PORT0 OMR: PR1 Mask */
\r
10851 #define PORT0_OMR_PR2_Pos 18 /*!< PORT0 OMR: PR2 Position */
\r
10852 #define PORT0_OMR_PR2_Msk (0x01UL << PORT0_OMR_PR2_Pos) /*!< PORT0 OMR: PR2 Mask */
\r
10853 #define PORT0_OMR_PR3_Pos 19 /*!< PORT0 OMR: PR3 Position */
\r
10854 #define PORT0_OMR_PR3_Msk (0x01UL << PORT0_OMR_PR3_Pos) /*!< PORT0 OMR: PR3 Mask */
\r
10855 #define PORT0_OMR_PR4_Pos 20 /*!< PORT0 OMR: PR4 Position */
\r
10856 #define PORT0_OMR_PR4_Msk (0x01UL << PORT0_OMR_PR4_Pos) /*!< PORT0 OMR: PR4 Mask */
\r
10857 #define PORT0_OMR_PR5_Pos 21 /*!< PORT0 OMR: PR5 Position */
\r
10858 #define PORT0_OMR_PR5_Msk (0x01UL << PORT0_OMR_PR5_Pos) /*!< PORT0 OMR: PR5 Mask */
\r
10859 #define PORT0_OMR_PR6_Pos 22 /*!< PORT0 OMR: PR6 Position */
\r
10860 #define PORT0_OMR_PR6_Msk (0x01UL << PORT0_OMR_PR6_Pos) /*!< PORT0 OMR: PR6 Mask */
\r
10861 #define PORT0_OMR_PR7_Pos 23 /*!< PORT0 OMR: PR7 Position */
\r
10862 #define PORT0_OMR_PR7_Msk (0x01UL << PORT0_OMR_PR7_Pos) /*!< PORT0 OMR: PR7 Mask */
\r
10863 #define PORT0_OMR_PR8_Pos 24 /*!< PORT0 OMR: PR8 Position */
\r
10864 #define PORT0_OMR_PR8_Msk (0x01UL << PORT0_OMR_PR8_Pos) /*!< PORT0 OMR: PR8 Mask */
\r
10865 #define PORT0_OMR_PR9_Pos 25 /*!< PORT0 OMR: PR9 Position */
\r
10866 #define PORT0_OMR_PR9_Msk (0x01UL << PORT0_OMR_PR9_Pos) /*!< PORT0 OMR: PR9 Mask */
\r
10867 #define PORT0_OMR_PR10_Pos 26 /*!< PORT0 OMR: PR10 Position */
\r
10868 #define PORT0_OMR_PR10_Msk (0x01UL << PORT0_OMR_PR10_Pos) /*!< PORT0 OMR: PR10 Mask */
\r
10869 #define PORT0_OMR_PR11_Pos 27 /*!< PORT0 OMR: PR11 Position */
\r
10870 #define PORT0_OMR_PR11_Msk (0x01UL << PORT0_OMR_PR11_Pos) /*!< PORT0 OMR: PR11 Mask */
\r
10871 #define PORT0_OMR_PR12_Pos 28 /*!< PORT0 OMR: PR12 Position */
\r
10872 #define PORT0_OMR_PR12_Msk (0x01UL << PORT0_OMR_PR12_Pos) /*!< PORT0 OMR: PR12 Mask */
\r
10873 #define PORT0_OMR_PR13_Pos 29 /*!< PORT0 OMR: PR13 Position */
\r
10874 #define PORT0_OMR_PR13_Msk (0x01UL << PORT0_OMR_PR13_Pos) /*!< PORT0 OMR: PR13 Mask */
\r
10875 #define PORT0_OMR_PR14_Pos 30 /*!< PORT0 OMR: PR14 Position */
\r
10876 #define PORT0_OMR_PR14_Msk (0x01UL << PORT0_OMR_PR14_Pos) /*!< PORT0 OMR: PR14 Mask */
\r
10877 #define PORT0_OMR_PR15_Pos 31 /*!< PORT0 OMR: PR15 Position */
\r
10878 #define PORT0_OMR_PR15_Msk (0x01UL << PORT0_OMR_PR15_Pos) /*!< PORT0 OMR: PR15 Mask */
\r
10880 // --------------------------------------- PORT0_IOCR0 ------------------------------------------
\r
10881 #define PORT0_IOCR0_PC0_Pos 3 /*!< PORT0 IOCR0: PC0 Position */
\r
10882 #define PORT0_IOCR0_PC0_Msk (0x1fUL << PORT0_IOCR0_PC0_Pos) /*!< PORT0 IOCR0: PC0 Mask */
\r
10883 #define PORT0_IOCR0_PC1_Pos 11 /*!< PORT0 IOCR0: PC1 Position */
\r
10884 #define PORT0_IOCR0_PC1_Msk (0x1fUL << PORT0_IOCR0_PC1_Pos) /*!< PORT0 IOCR0: PC1 Mask */
\r
10885 #define PORT0_IOCR0_PC2_Pos 19 /*!< PORT0 IOCR0: PC2 Position */
\r
10886 #define PORT0_IOCR0_PC2_Msk (0x1fUL << PORT0_IOCR0_PC2_Pos) /*!< PORT0 IOCR0: PC2 Mask */
\r
10887 #define PORT0_IOCR0_PC3_Pos 27 /*!< PORT0 IOCR0: PC3 Position */
\r
10888 #define PORT0_IOCR0_PC3_Msk (0x1fUL << PORT0_IOCR0_PC3_Pos) /*!< PORT0 IOCR0: PC3 Mask */
\r
10890 // --------------------------------------- PORT0_IOCR4 ------------------------------------------
\r
10891 #define PORT0_IOCR4_PC4_Pos 3 /*!< PORT0 IOCR4: PC4 Position */
\r
10892 #define PORT0_IOCR4_PC4_Msk (0x1fUL << PORT0_IOCR4_PC4_Pos) /*!< PORT0 IOCR4: PC4 Mask */
\r
10893 #define PORT0_IOCR4_PC5_Pos 11 /*!< PORT0 IOCR4: PC5 Position */
\r
10894 #define PORT0_IOCR4_PC5_Msk (0x1fUL << PORT0_IOCR4_PC5_Pos) /*!< PORT0 IOCR4: PC5 Mask */
\r
10895 #define PORT0_IOCR4_PC6_Pos 19 /*!< PORT0 IOCR4: PC6 Position */
\r
10896 #define PORT0_IOCR4_PC6_Msk (0x1fUL << PORT0_IOCR4_PC6_Pos) /*!< PORT0 IOCR4: PC6 Mask */
\r
10897 #define PORT0_IOCR4_PC7_Pos 27 /*!< PORT0 IOCR4: PC7 Position */
\r
10898 #define PORT0_IOCR4_PC7_Msk (0x1fUL << PORT0_IOCR4_PC7_Pos) /*!< PORT0 IOCR4: PC7 Mask */
\r
10900 // --------------------------------------- PORT0_IOCR8 ------------------------------------------
\r
10901 #define PORT0_IOCR8_PC8_Pos 3 /*!< PORT0 IOCR8: PC8 Position */
\r
10902 #define PORT0_IOCR8_PC8_Msk (0x1fUL << PORT0_IOCR8_PC8_Pos) /*!< PORT0 IOCR8: PC8 Mask */
\r
10903 #define PORT0_IOCR8_PC9_Pos 11 /*!< PORT0 IOCR8: PC9 Position */
\r
10904 #define PORT0_IOCR8_PC9_Msk (0x1fUL << PORT0_IOCR8_PC9_Pos) /*!< PORT0 IOCR8: PC9 Mask */
\r
10905 #define PORT0_IOCR8_PC10_Pos 19 /*!< PORT0 IOCR8: PC10 Position */
\r
10906 #define PORT0_IOCR8_PC10_Msk (0x1fUL << PORT0_IOCR8_PC10_Pos) /*!< PORT0 IOCR8: PC10 Mask */
\r
10907 #define PORT0_IOCR8_PC11_Pos 27 /*!< PORT0 IOCR8: PC11 Position */
\r
10908 #define PORT0_IOCR8_PC11_Msk (0x1fUL << PORT0_IOCR8_PC11_Pos) /*!< PORT0 IOCR8: PC11 Mask */
\r
10910 // -------------------------------------- PORT0_IOCR12 ------------------------------------------
\r
10911 #define PORT0_IOCR12_PC12_Pos 3 /*!< PORT0 IOCR12: PC12 Position */
\r
10912 #define PORT0_IOCR12_PC12_Msk (0x1fUL << PORT0_IOCR12_PC12_Pos) /*!< PORT0 IOCR12: PC12 Mask */
\r
10913 #define PORT0_IOCR12_PC13_Pos 11 /*!< PORT0 IOCR12: PC13 Position */
\r
10914 #define PORT0_IOCR12_PC13_Msk (0x1fUL << PORT0_IOCR12_PC13_Pos) /*!< PORT0 IOCR12: PC13 Mask */
\r
10915 #define PORT0_IOCR12_PC14_Pos 19 /*!< PORT0 IOCR12: PC14 Position */
\r
10916 #define PORT0_IOCR12_PC14_Msk (0x1fUL << PORT0_IOCR12_PC14_Pos) /*!< PORT0 IOCR12: PC14 Mask */
\r
10917 #define PORT0_IOCR12_PC15_Pos 27 /*!< PORT0 IOCR12: PC15 Position */
\r
10918 #define PORT0_IOCR12_PC15_Msk (0x1fUL << PORT0_IOCR12_PC15_Pos) /*!< PORT0 IOCR12: PC15 Mask */
\r
10920 // ---------------------------------------- PORT0_IN --------------------------------------------
\r
10921 #define PORT0_IN_P0_Pos 0 /*!< PORT0 IN: P0 Position */
\r
10922 #define PORT0_IN_P0_Msk (0x01UL << PORT0_IN_P0_Pos) /*!< PORT0 IN: P0 Mask */
\r
10923 #define PORT0_IN_P1_Pos 1 /*!< PORT0 IN: P1 Position */
\r
10924 #define PORT0_IN_P1_Msk (0x01UL << PORT0_IN_P1_Pos) /*!< PORT0 IN: P1 Mask */
\r
10925 #define PORT0_IN_P2_Pos 2 /*!< PORT0 IN: P2 Position */
\r
10926 #define PORT0_IN_P2_Msk (0x01UL << PORT0_IN_P2_Pos) /*!< PORT0 IN: P2 Mask */
\r
10927 #define PORT0_IN_P3_Pos 3 /*!< PORT0 IN: P3 Position */
\r
10928 #define PORT0_IN_P3_Msk (0x01UL << PORT0_IN_P3_Pos) /*!< PORT0 IN: P3 Mask */
\r
10929 #define PORT0_IN_P4_Pos 4 /*!< PORT0 IN: P4 Position */
\r
10930 #define PORT0_IN_P4_Msk (0x01UL << PORT0_IN_P4_Pos) /*!< PORT0 IN: P4 Mask */
\r
10931 #define PORT0_IN_P5_Pos 5 /*!< PORT0 IN: P5 Position */
\r
10932 #define PORT0_IN_P5_Msk (0x01UL << PORT0_IN_P5_Pos) /*!< PORT0 IN: P5 Mask */
\r
10933 #define PORT0_IN_P6_Pos 6 /*!< PORT0 IN: P6 Position */
\r
10934 #define PORT0_IN_P6_Msk (0x01UL << PORT0_IN_P6_Pos) /*!< PORT0 IN: P6 Mask */
\r
10935 #define PORT0_IN_P7_Pos 7 /*!< PORT0 IN: P7 Position */
\r
10936 #define PORT0_IN_P7_Msk (0x01UL << PORT0_IN_P7_Pos) /*!< PORT0 IN: P7 Mask */
\r
10937 #define PORT0_IN_P8_Pos 8 /*!< PORT0 IN: P8 Position */
\r
10938 #define PORT0_IN_P8_Msk (0x01UL << PORT0_IN_P8_Pos) /*!< PORT0 IN: P8 Mask */
\r
10939 #define PORT0_IN_P9_Pos 9 /*!< PORT0 IN: P9 Position */
\r
10940 #define PORT0_IN_P9_Msk (0x01UL << PORT0_IN_P9_Pos) /*!< PORT0 IN: P9 Mask */
\r
10941 #define PORT0_IN_P10_Pos 10 /*!< PORT0 IN: P10 Position */
\r
10942 #define PORT0_IN_P10_Msk (0x01UL << PORT0_IN_P10_Pos) /*!< PORT0 IN: P10 Mask */
\r
10943 #define PORT0_IN_P11_Pos 11 /*!< PORT0 IN: P11 Position */
\r
10944 #define PORT0_IN_P11_Msk (0x01UL << PORT0_IN_P11_Pos) /*!< PORT0 IN: P11 Mask */
\r
10945 #define PORT0_IN_P12_Pos 12 /*!< PORT0 IN: P12 Position */
\r
10946 #define PORT0_IN_P12_Msk (0x01UL << PORT0_IN_P12_Pos) /*!< PORT0 IN: P12 Mask */
\r
10947 #define PORT0_IN_P13_Pos 13 /*!< PORT0 IN: P13 Position */
\r
10948 #define PORT0_IN_P13_Msk (0x01UL << PORT0_IN_P13_Pos) /*!< PORT0 IN: P13 Mask */
\r
10949 #define PORT0_IN_P14_Pos 14 /*!< PORT0 IN: P14 Position */
\r
10950 #define PORT0_IN_P14_Msk (0x01UL << PORT0_IN_P14_Pos) /*!< PORT0 IN: P14 Mask */
\r
10951 #define PORT0_IN_P15_Pos 15 /*!< PORT0 IN: P15 Position */
\r
10952 #define PORT0_IN_P15_Msk (0x01UL << PORT0_IN_P15_Pos) /*!< PORT0 IN: P15 Mask */
\r
10954 // --------------------------------------- PORT0_PDR0 -------------------------------------------
\r
10955 #define PORT0_PDR0_PD0_Pos 0 /*!< PORT0 PDR0: PD0 Position */
\r
10956 #define PORT0_PDR0_PD0_Msk (0x07UL << PORT0_PDR0_PD0_Pos) /*!< PORT0 PDR0: PD0 Mask */
\r
10957 #define PORT0_PDR0_PD1_Pos 4 /*!< PORT0 PDR0: PD1 Position */
\r
10958 #define PORT0_PDR0_PD1_Msk (0x07UL << PORT0_PDR0_PD1_Pos) /*!< PORT0 PDR0: PD1 Mask */
\r
10959 #define PORT0_PDR0_PD2_Pos 8 /*!< PORT0 PDR0: PD2 Position */
\r
10960 #define PORT0_PDR0_PD2_Msk (0x07UL << PORT0_PDR0_PD2_Pos) /*!< PORT0 PDR0: PD2 Mask */
\r
10961 #define PORT0_PDR0_PD3_Pos 12 /*!< PORT0 PDR0: PD3 Position */
\r
10962 #define PORT0_PDR0_PD3_Msk (0x07UL << PORT0_PDR0_PD3_Pos) /*!< PORT0 PDR0: PD3 Mask */
\r
10963 #define PORT0_PDR0_PD4_Pos 16 /*!< PORT0 PDR0: PD4 Position */
\r
10964 #define PORT0_PDR0_PD4_Msk (0x07UL << PORT0_PDR0_PD4_Pos) /*!< PORT0 PDR0: PD4 Mask */
\r
10965 #define PORT0_PDR0_PD5_Pos 20 /*!< PORT0 PDR0: PD5 Position */
\r
10966 #define PORT0_PDR0_PD5_Msk (0x07UL << PORT0_PDR0_PD5_Pos) /*!< PORT0 PDR0: PD5 Mask */
\r
10967 #define PORT0_PDR0_PD6_Pos 24 /*!< PORT0 PDR0: PD6 Position */
\r
10968 #define PORT0_PDR0_PD6_Msk (0x07UL << PORT0_PDR0_PD6_Pos) /*!< PORT0 PDR0: PD6 Mask */
\r
10969 #define PORT0_PDR0_PD7_Pos 28 /*!< PORT0 PDR0: PD7 Position */
\r
10970 #define PORT0_PDR0_PD7_Msk (0x07UL << PORT0_PDR0_PD7_Pos) /*!< PORT0 PDR0: PD7 Mask */
\r
10972 // --------------------------------------- PORT0_PDR1 -------------------------------------------
\r
10973 #define PORT0_PDR1_PD8_Pos 0 /*!< PORT0 PDR1: PD8 Position */
\r
10974 #define PORT0_PDR1_PD8_Msk (0x07UL << PORT0_PDR1_PD8_Pos) /*!< PORT0 PDR1: PD8 Mask */
\r
10975 #define PORT0_PDR1_PD9_Pos 4 /*!< PORT0 PDR1: PD9 Position */
\r
10976 #define PORT0_PDR1_PD9_Msk (0x07UL << PORT0_PDR1_PD9_Pos) /*!< PORT0 PDR1: PD9 Mask */
\r
10977 #define PORT0_PDR1_PD10_Pos 8 /*!< PORT0 PDR1: PD10 Position */
\r
10978 #define PORT0_PDR1_PD10_Msk (0x07UL << PORT0_PDR1_PD10_Pos) /*!< PORT0 PDR1: PD10 Mask */
\r
10979 #define PORT0_PDR1_PD11_Pos 12 /*!< PORT0 PDR1: PD11 Position */
\r
10980 #define PORT0_PDR1_PD11_Msk (0x07UL << PORT0_PDR1_PD11_Pos) /*!< PORT0 PDR1: PD11 Mask */
\r
10981 #define PORT0_PDR1_PD12_Pos 16 /*!< PORT0 PDR1: PD12 Position */
\r
10982 #define PORT0_PDR1_PD12_Msk (0x07UL << PORT0_PDR1_PD12_Pos) /*!< PORT0 PDR1: PD12 Mask */
\r
10983 #define PORT0_PDR1_PD13_Pos 20 /*!< PORT0 PDR1: PD13 Position */
\r
10984 #define PORT0_PDR1_PD13_Msk (0x07UL << PORT0_PDR1_PD13_Pos) /*!< PORT0 PDR1: PD13 Mask */
\r
10985 #define PORT0_PDR1_PD14_Pos 24 /*!< PORT0 PDR1: PD14 Position */
\r
10986 #define PORT0_PDR1_PD14_Msk (0x07UL << PORT0_PDR1_PD14_Pos) /*!< PORT0 PDR1: PD14 Mask */
\r
10987 #define PORT0_PDR1_PD15_Pos 28 /*!< PORT0 PDR1: PD15 Position */
\r
10988 #define PORT0_PDR1_PD15_Msk (0x07UL << PORT0_PDR1_PD15_Pos) /*!< PORT0 PDR1: PD15 Mask */
\r
10990 // --------------------------------------- PORT0_PDISC ------------------------------------------
\r
10991 #define PORT0_PDISC_PDIS0_Pos 0 /*!< PORT0 PDISC: PDIS0 Position */
\r
10992 #define PORT0_PDISC_PDIS0_Msk (0x01UL << PORT0_PDISC_PDIS0_Pos) /*!< PORT0 PDISC: PDIS0 Mask */
\r
10993 #define PORT0_PDISC_PDIS1_Pos 1 /*!< PORT0 PDISC: PDIS1 Position */
\r
10994 #define PORT0_PDISC_PDIS1_Msk (0x01UL << PORT0_PDISC_PDIS1_Pos) /*!< PORT0 PDISC: PDIS1 Mask */
\r
10995 #define PORT0_PDISC_PDIS2_Pos 2 /*!< PORT0 PDISC: PDIS2 Position */
\r
10996 #define PORT0_PDISC_PDIS2_Msk (0x01UL << PORT0_PDISC_PDIS2_Pos) /*!< PORT0 PDISC: PDIS2 Mask */
\r
10997 #define PORT0_PDISC_PDIS3_Pos 3 /*!< PORT0 PDISC: PDIS3 Position */
\r
10998 #define PORT0_PDISC_PDIS3_Msk (0x01UL << PORT0_PDISC_PDIS3_Pos) /*!< PORT0 PDISC: PDIS3 Mask */
\r
10999 #define PORT0_PDISC_PDIS4_Pos 4 /*!< PORT0 PDISC: PDIS4 Position */
\r
11000 #define PORT0_PDISC_PDIS4_Msk (0x01UL << PORT0_PDISC_PDIS4_Pos) /*!< PORT0 PDISC: PDIS4 Mask */
\r
11001 #define PORT0_PDISC_PDIS5_Pos 5 /*!< PORT0 PDISC: PDIS5 Position */
\r
11002 #define PORT0_PDISC_PDIS5_Msk (0x01UL << PORT0_PDISC_PDIS5_Pos) /*!< PORT0 PDISC: PDIS5 Mask */
\r
11003 #define PORT0_PDISC_PDIS6_Pos 6 /*!< PORT0 PDISC: PDIS6 Position */
\r
11004 #define PORT0_PDISC_PDIS6_Msk (0x01UL << PORT0_PDISC_PDIS6_Pos) /*!< PORT0 PDISC: PDIS6 Mask */
\r
11005 #define PORT0_PDISC_PDIS7_Pos 7 /*!< PORT0 PDISC: PDIS7 Position */
\r
11006 #define PORT0_PDISC_PDIS7_Msk (0x01UL << PORT0_PDISC_PDIS7_Pos) /*!< PORT0 PDISC: PDIS7 Mask */
\r
11007 #define PORT0_PDISC_PDIS8_Pos 8 /*!< PORT0 PDISC: PDIS8 Position */
\r
11008 #define PORT0_PDISC_PDIS8_Msk (0x01UL << PORT0_PDISC_PDIS8_Pos) /*!< PORT0 PDISC: PDIS8 Mask */
\r
11009 #define PORT0_PDISC_PDIS9_Pos 9 /*!< PORT0 PDISC: PDIS9 Position */
\r
11010 #define PORT0_PDISC_PDIS9_Msk (0x01UL << PORT0_PDISC_PDIS9_Pos) /*!< PORT0 PDISC: PDIS9 Mask */
\r
11011 #define PORT0_PDISC_PDIS10_Pos 10 /*!< PORT0 PDISC: PDIS10 Position */
\r
11012 #define PORT0_PDISC_PDIS10_Msk (0x01UL << PORT0_PDISC_PDIS10_Pos) /*!< PORT0 PDISC: PDIS10 Mask */
\r
11013 #define PORT0_PDISC_PDIS11_Pos 11 /*!< PORT0 PDISC: PDIS11 Position */
\r
11014 #define PORT0_PDISC_PDIS11_Msk (0x01UL << PORT0_PDISC_PDIS11_Pos) /*!< PORT0 PDISC: PDIS11 Mask */
\r
11015 #define PORT0_PDISC_PDIS12_Pos 12 /*!< PORT0 PDISC: PDIS12 Position */
\r
11016 #define PORT0_PDISC_PDIS12_Msk (0x01UL << PORT0_PDISC_PDIS12_Pos) /*!< PORT0 PDISC: PDIS12 Mask */
\r
11017 #define PORT0_PDISC_PDIS13_Pos 13 /*!< PORT0 PDISC: PDIS13 Position */
\r
11018 #define PORT0_PDISC_PDIS13_Msk (0x01UL << PORT0_PDISC_PDIS13_Pos) /*!< PORT0 PDISC: PDIS13 Mask */
\r
11019 #define PORT0_PDISC_PDIS14_Pos 14 /*!< PORT0 PDISC: PDIS14 Position */
\r
11020 #define PORT0_PDISC_PDIS14_Msk (0x01UL << PORT0_PDISC_PDIS14_Pos) /*!< PORT0 PDISC: PDIS14 Mask */
\r
11021 #define PORT0_PDISC_PDIS15_Pos 15 /*!< PORT0 PDISC: PDIS15 Position */
\r
11022 #define PORT0_PDISC_PDIS15_Msk (0x01UL << PORT0_PDISC_PDIS15_Pos) /*!< PORT0 PDISC: PDIS15 Mask */
\r
11024 // ---------------------------------------- PORT0_PPS -------------------------------------------
\r
11025 #define PORT0_PPS_PPS0_Pos 0 /*!< PORT0 PPS: PPS0 Position */
\r
11026 #define PORT0_PPS_PPS0_Msk (0x01UL << PORT0_PPS_PPS0_Pos) /*!< PORT0 PPS: PPS0 Mask */
\r
11027 #define PORT0_PPS_PPS1_Pos 1 /*!< PORT0 PPS: PPS1 Position */
\r
11028 #define PORT0_PPS_PPS1_Msk (0x01UL << PORT0_PPS_PPS1_Pos) /*!< PORT0 PPS: PPS1 Mask */
\r
11029 #define PORT0_PPS_PPS2_Pos 2 /*!< PORT0 PPS: PPS2 Position */
\r
11030 #define PORT0_PPS_PPS2_Msk (0x01UL << PORT0_PPS_PPS2_Pos) /*!< PORT0 PPS: PPS2 Mask */
\r
11031 #define PORT0_PPS_PPS3_Pos 3 /*!< PORT0 PPS: PPS3 Position */
\r
11032 #define PORT0_PPS_PPS3_Msk (0x01UL << PORT0_PPS_PPS3_Pos) /*!< PORT0 PPS: PPS3 Mask */
\r
11033 #define PORT0_PPS_PPS4_Pos 4 /*!< PORT0 PPS: PPS4 Position */
\r
11034 #define PORT0_PPS_PPS4_Msk (0x01UL << PORT0_PPS_PPS4_Pos) /*!< PORT0 PPS: PPS4 Mask */
\r
11035 #define PORT0_PPS_PPS5_Pos 5 /*!< PORT0 PPS: PPS5 Position */
\r
11036 #define PORT0_PPS_PPS5_Msk (0x01UL << PORT0_PPS_PPS5_Pos) /*!< PORT0 PPS: PPS5 Mask */
\r
11037 #define PORT0_PPS_PPS6_Pos 6 /*!< PORT0 PPS: PPS6 Position */
\r
11038 #define PORT0_PPS_PPS6_Msk (0x01UL << PORT0_PPS_PPS6_Pos) /*!< PORT0 PPS: PPS6 Mask */
\r
11039 #define PORT0_PPS_PPS7_Pos 7 /*!< PORT0 PPS: PPS7 Position */
\r
11040 #define PORT0_PPS_PPS7_Msk (0x01UL << PORT0_PPS_PPS7_Pos) /*!< PORT0 PPS: PPS7 Mask */
\r
11041 #define PORT0_PPS_PPS8_Pos 8 /*!< PORT0 PPS: PPS8 Position */
\r
11042 #define PORT0_PPS_PPS8_Msk (0x01UL << PORT0_PPS_PPS8_Pos) /*!< PORT0 PPS: PPS8 Mask */
\r
11043 #define PORT0_PPS_PPS9_Pos 9 /*!< PORT0 PPS: PPS9 Position */
\r
11044 #define PORT0_PPS_PPS9_Msk (0x01UL << PORT0_PPS_PPS9_Pos) /*!< PORT0 PPS: PPS9 Mask */
\r
11045 #define PORT0_PPS_PPS10_Pos 10 /*!< PORT0 PPS: PPS10 Position */
\r
11046 #define PORT0_PPS_PPS10_Msk (0x01UL << PORT0_PPS_PPS10_Pos) /*!< PORT0 PPS: PPS10 Mask */
\r
11047 #define PORT0_PPS_PPS11_Pos 11 /*!< PORT0 PPS: PPS11 Position */
\r
11048 #define PORT0_PPS_PPS11_Msk (0x01UL << PORT0_PPS_PPS11_Pos) /*!< PORT0 PPS: PPS11 Mask */
\r
11049 #define PORT0_PPS_PPS12_Pos 12 /*!< PORT0 PPS: PPS12 Position */
\r
11050 #define PORT0_PPS_PPS12_Msk (0x01UL << PORT0_PPS_PPS12_Pos) /*!< PORT0 PPS: PPS12 Mask */
\r
11051 #define PORT0_PPS_PPS13_Pos 13 /*!< PORT0 PPS: PPS13 Position */
\r
11052 #define PORT0_PPS_PPS13_Msk (0x01UL << PORT0_PPS_PPS13_Pos) /*!< PORT0 PPS: PPS13 Mask */
\r
11053 #define PORT0_PPS_PPS14_Pos 14 /*!< PORT0 PPS: PPS14 Position */
\r
11054 #define PORT0_PPS_PPS14_Msk (0x01UL << PORT0_PPS_PPS14_Pos) /*!< PORT0 PPS: PPS14 Mask */
\r
11055 #define PORT0_PPS_PPS15_Pos 15 /*!< PORT0 PPS: PPS15 Position */
\r
11056 #define PORT0_PPS_PPS15_Msk (0x01UL << PORT0_PPS_PPS15_Pos) /*!< PORT0 PPS: PPS15 Mask */
\r
11058 // --------------------------------------- PORT0_HWSEL ------------------------------------------
\r
11059 #define PORT0_HWSEL_HW0_Pos 0 /*!< PORT0 HWSEL: HW0 Position */
\r
11060 #define PORT0_HWSEL_HW0_Msk (0x03UL << PORT0_HWSEL_HW0_Pos) /*!< PORT0 HWSEL: HW0 Mask */
\r
11061 #define PORT0_HWSEL_HW1_Pos 2 /*!< PORT0 HWSEL: HW1 Position */
\r
11062 #define PORT0_HWSEL_HW1_Msk (0x03UL << PORT0_HWSEL_HW1_Pos) /*!< PORT0 HWSEL: HW1 Mask */
\r
11063 #define PORT0_HWSEL_HW2_Pos 4 /*!< PORT0 HWSEL: HW2 Position */
\r
11064 #define PORT0_HWSEL_HW2_Msk (0x03UL << PORT0_HWSEL_HW2_Pos) /*!< PORT0 HWSEL: HW2 Mask */
\r
11065 #define PORT0_HWSEL_HW3_Pos 6 /*!< PORT0 HWSEL: HW3 Position */
\r
11066 #define PORT0_HWSEL_HW3_Msk (0x03UL << PORT0_HWSEL_HW3_Pos) /*!< PORT0 HWSEL: HW3 Mask */
\r
11067 #define PORT0_HWSEL_HW4_Pos 8 /*!< PORT0 HWSEL: HW4 Position */
\r
11068 #define PORT0_HWSEL_HW4_Msk (0x03UL << PORT0_HWSEL_HW4_Pos) /*!< PORT0 HWSEL: HW4 Mask */
\r
11069 #define PORT0_HWSEL_HW5_Pos 10 /*!< PORT0 HWSEL: HW5 Position */
\r
11070 #define PORT0_HWSEL_HW5_Msk (0x03UL << PORT0_HWSEL_HW5_Pos) /*!< PORT0 HWSEL: HW5 Mask */
\r
11071 #define PORT0_HWSEL_HW6_Pos 12 /*!< PORT0 HWSEL: HW6 Position */
\r
11072 #define PORT0_HWSEL_HW6_Msk (0x03UL << PORT0_HWSEL_HW6_Pos) /*!< PORT0 HWSEL: HW6 Mask */
\r
11073 #define PORT0_HWSEL_HW7_Pos 14 /*!< PORT0 HWSEL: HW7 Position */
\r
11074 #define PORT0_HWSEL_HW7_Msk (0x03UL << PORT0_HWSEL_HW7_Pos) /*!< PORT0 HWSEL: HW7 Mask */
\r
11075 #define PORT0_HWSEL_HW8_Pos 16 /*!< PORT0 HWSEL: HW8 Position */
\r
11076 #define PORT0_HWSEL_HW8_Msk (0x03UL << PORT0_HWSEL_HW8_Pos) /*!< PORT0 HWSEL: HW8 Mask */
\r
11077 #define PORT0_HWSEL_HW9_Pos 18 /*!< PORT0 HWSEL: HW9 Position */
\r
11078 #define PORT0_HWSEL_HW9_Msk (0x03UL << PORT0_HWSEL_HW9_Pos) /*!< PORT0 HWSEL: HW9 Mask */
\r
11079 #define PORT0_HWSEL_HW10_Pos 20 /*!< PORT0 HWSEL: HW10 Position */
\r
11080 #define PORT0_HWSEL_HW10_Msk (0x03UL << PORT0_HWSEL_HW10_Pos) /*!< PORT0 HWSEL: HW10 Mask */
\r
11081 #define PORT0_HWSEL_HW11_Pos 22 /*!< PORT0 HWSEL: HW11 Position */
\r
11082 #define PORT0_HWSEL_HW11_Msk (0x03UL << PORT0_HWSEL_HW11_Pos) /*!< PORT0 HWSEL: HW11 Mask */
\r
11083 #define PORT0_HWSEL_HW12_Pos 24 /*!< PORT0 HWSEL: HW12 Position */
\r
11084 #define PORT0_HWSEL_HW12_Msk (0x03UL << PORT0_HWSEL_HW12_Pos) /*!< PORT0 HWSEL: HW12 Mask */
\r
11085 #define PORT0_HWSEL_HW13_Pos 26 /*!< PORT0 HWSEL: HW13 Position */
\r
11086 #define PORT0_HWSEL_HW13_Msk (0x03UL << PORT0_HWSEL_HW13_Pos) /*!< PORT0 HWSEL: HW13 Mask */
\r
11087 #define PORT0_HWSEL_HW14_Pos 28 /*!< PORT0 HWSEL: HW14 Position */
\r
11088 #define PORT0_HWSEL_HW14_Msk (0x03UL << PORT0_HWSEL_HW14_Pos) /*!< PORT0 HWSEL: HW14 Mask */
\r
11089 #define PORT0_HWSEL_HW15_Pos 30 /*!< PORT0 HWSEL: HW15 Position */
\r
11090 #define PORT0_HWSEL_HW15_Msk (0x03UL << PORT0_HWSEL_HW15_Pos) /*!< PORT0 HWSEL: HW15 Mask */
\r
11093 // ------------------------------------------------------------------------------------------------
\r
11094 // ----- PORT1 Position & Mask -----
\r
11095 // ------------------------------------------------------------------------------------------------
\r
11098 // ---------------------------------------- PORT1_OUT -------------------------------------------
\r
11099 #define PORT1_OUT_P0_Pos 0 /*!< PORT1 OUT: P0 Position */
\r
11100 #define PORT1_OUT_P0_Msk (0x01UL << PORT1_OUT_P0_Pos) /*!< PORT1 OUT: P0 Mask */
\r
11101 #define PORT1_OUT_P1_Pos 1 /*!< PORT1 OUT: P1 Position */
\r
11102 #define PORT1_OUT_P1_Msk (0x01UL << PORT1_OUT_P1_Pos) /*!< PORT1 OUT: P1 Mask */
\r
11103 #define PORT1_OUT_P2_Pos 2 /*!< PORT1 OUT: P2 Position */
\r
11104 #define PORT1_OUT_P2_Msk (0x01UL << PORT1_OUT_P2_Pos) /*!< PORT1 OUT: P2 Mask */
\r
11105 #define PORT1_OUT_P3_Pos 3 /*!< PORT1 OUT: P3 Position */
\r
11106 #define PORT1_OUT_P3_Msk (0x01UL << PORT1_OUT_P3_Pos) /*!< PORT1 OUT: P3 Mask */
\r
11107 #define PORT1_OUT_P4_Pos 4 /*!< PORT1 OUT: P4 Position */
\r
11108 #define PORT1_OUT_P4_Msk (0x01UL << PORT1_OUT_P4_Pos) /*!< PORT1 OUT: P4 Mask */
\r
11109 #define PORT1_OUT_P5_Pos 5 /*!< PORT1 OUT: P5 Position */
\r
11110 #define PORT1_OUT_P5_Msk (0x01UL << PORT1_OUT_P5_Pos) /*!< PORT1 OUT: P5 Mask */
\r
11111 #define PORT1_OUT_P6_Pos 6 /*!< PORT1 OUT: P6 Position */
\r
11112 #define PORT1_OUT_P6_Msk (0x01UL << PORT1_OUT_P6_Pos) /*!< PORT1 OUT: P6 Mask */
\r
11113 #define PORT1_OUT_P7_Pos 7 /*!< PORT1 OUT: P7 Position */
\r
11114 #define PORT1_OUT_P7_Msk (0x01UL << PORT1_OUT_P7_Pos) /*!< PORT1 OUT: P7 Mask */
\r
11115 #define PORT1_OUT_P8_Pos 8 /*!< PORT1 OUT: P8 Position */
\r
11116 #define PORT1_OUT_P8_Msk (0x01UL << PORT1_OUT_P8_Pos) /*!< PORT1 OUT: P8 Mask */
\r
11117 #define PORT1_OUT_P9_Pos 9 /*!< PORT1 OUT: P9 Position */
\r
11118 #define PORT1_OUT_P9_Msk (0x01UL << PORT1_OUT_P9_Pos) /*!< PORT1 OUT: P9 Mask */
\r
11119 #define PORT1_OUT_P10_Pos 10 /*!< PORT1 OUT: P10 Position */
\r
11120 #define PORT1_OUT_P10_Msk (0x01UL << PORT1_OUT_P10_Pos) /*!< PORT1 OUT: P10 Mask */
\r
11121 #define PORT1_OUT_P11_Pos 11 /*!< PORT1 OUT: P11 Position */
\r
11122 #define PORT1_OUT_P11_Msk (0x01UL << PORT1_OUT_P11_Pos) /*!< PORT1 OUT: P11 Mask */
\r
11123 #define PORT1_OUT_P12_Pos 12 /*!< PORT1 OUT: P12 Position */
\r
11124 #define PORT1_OUT_P12_Msk (0x01UL << PORT1_OUT_P12_Pos) /*!< PORT1 OUT: P12 Mask */
\r
11125 #define PORT1_OUT_P13_Pos 13 /*!< PORT1 OUT: P13 Position */
\r
11126 #define PORT1_OUT_P13_Msk (0x01UL << PORT1_OUT_P13_Pos) /*!< PORT1 OUT: P13 Mask */
\r
11127 #define PORT1_OUT_P14_Pos 14 /*!< PORT1 OUT: P14 Position */
\r
11128 #define PORT1_OUT_P14_Msk (0x01UL << PORT1_OUT_P14_Pos) /*!< PORT1 OUT: P14 Mask */
\r
11129 #define PORT1_OUT_P15_Pos 15 /*!< PORT1 OUT: P15 Position */
\r
11130 #define PORT1_OUT_P15_Msk (0x01UL << PORT1_OUT_P15_Pos) /*!< PORT1 OUT: P15 Mask */
\r
11132 // ---------------------------------------- PORT1_OMR -------------------------------------------
\r
11133 #define PORT1_OMR_PS0_Pos 0 /*!< PORT1 OMR: PS0 Position */
\r
11134 #define PORT1_OMR_PS0_Msk (0x01UL << PORT1_OMR_PS0_Pos) /*!< PORT1 OMR: PS0 Mask */
\r
11135 #define PORT1_OMR_PS1_Pos 1 /*!< PORT1 OMR: PS1 Position */
\r
11136 #define PORT1_OMR_PS1_Msk (0x01UL << PORT1_OMR_PS1_Pos) /*!< PORT1 OMR: PS1 Mask */
\r
11137 #define PORT1_OMR_PS2_Pos 2 /*!< PORT1 OMR: PS2 Position */
\r
11138 #define PORT1_OMR_PS2_Msk (0x01UL << PORT1_OMR_PS2_Pos) /*!< PORT1 OMR: PS2 Mask */
\r
11139 #define PORT1_OMR_PS3_Pos 3 /*!< PORT1 OMR: PS3 Position */
\r
11140 #define PORT1_OMR_PS3_Msk (0x01UL << PORT1_OMR_PS3_Pos) /*!< PORT1 OMR: PS3 Mask */
\r
11141 #define PORT1_OMR_PS4_Pos 4 /*!< PORT1 OMR: PS4 Position */
\r
11142 #define PORT1_OMR_PS4_Msk (0x01UL << PORT1_OMR_PS4_Pos) /*!< PORT1 OMR: PS4 Mask */
\r
11143 #define PORT1_OMR_PS5_Pos 5 /*!< PORT1 OMR: PS5 Position */
\r
11144 #define PORT1_OMR_PS5_Msk (0x01UL << PORT1_OMR_PS5_Pos) /*!< PORT1 OMR: PS5 Mask */
\r
11145 #define PORT1_OMR_PS6_Pos 6 /*!< PORT1 OMR: PS6 Position */
\r
11146 #define PORT1_OMR_PS6_Msk (0x01UL << PORT1_OMR_PS6_Pos) /*!< PORT1 OMR: PS6 Mask */
\r
11147 #define PORT1_OMR_PS7_Pos 7 /*!< PORT1 OMR: PS7 Position */
\r
11148 #define PORT1_OMR_PS7_Msk (0x01UL << PORT1_OMR_PS7_Pos) /*!< PORT1 OMR: PS7 Mask */
\r
11149 #define PORT1_OMR_PS8_Pos 8 /*!< PORT1 OMR: PS8 Position */
\r
11150 #define PORT1_OMR_PS8_Msk (0x01UL << PORT1_OMR_PS8_Pos) /*!< PORT1 OMR: PS8 Mask */
\r
11151 #define PORT1_OMR_PS9_Pos 9 /*!< PORT1 OMR: PS9 Position */
\r
11152 #define PORT1_OMR_PS9_Msk (0x01UL << PORT1_OMR_PS9_Pos) /*!< PORT1 OMR: PS9 Mask */
\r
11153 #define PORT1_OMR_PS10_Pos 10 /*!< PORT1 OMR: PS10 Position */
\r
11154 #define PORT1_OMR_PS10_Msk (0x01UL << PORT1_OMR_PS10_Pos) /*!< PORT1 OMR: PS10 Mask */
\r
11155 #define PORT1_OMR_PS11_Pos 11 /*!< PORT1 OMR: PS11 Position */
\r
11156 #define PORT1_OMR_PS11_Msk (0x01UL << PORT1_OMR_PS11_Pos) /*!< PORT1 OMR: PS11 Mask */
\r
11157 #define PORT1_OMR_PS12_Pos 12 /*!< PORT1 OMR: PS12 Position */
\r
11158 #define PORT1_OMR_PS12_Msk (0x01UL << PORT1_OMR_PS12_Pos) /*!< PORT1 OMR: PS12 Mask */
\r
11159 #define PORT1_OMR_PS13_Pos 13 /*!< PORT1 OMR: PS13 Position */
\r
11160 #define PORT1_OMR_PS13_Msk (0x01UL << PORT1_OMR_PS13_Pos) /*!< PORT1 OMR: PS13 Mask */
\r
11161 #define PORT1_OMR_PS14_Pos 14 /*!< PORT1 OMR: PS14 Position */
\r
11162 #define PORT1_OMR_PS14_Msk (0x01UL << PORT1_OMR_PS14_Pos) /*!< PORT1 OMR: PS14 Mask */
\r
11163 #define PORT1_OMR_PS15_Pos 15 /*!< PORT1 OMR: PS15 Position */
\r
11164 #define PORT1_OMR_PS15_Msk (0x01UL << PORT1_OMR_PS15_Pos) /*!< PORT1 OMR: PS15 Mask */
\r
11165 #define PORT1_OMR_PR0_Pos 16 /*!< PORT1 OMR: PR0 Position */
\r
11166 #define PORT1_OMR_PR0_Msk (0x01UL << PORT1_OMR_PR0_Pos) /*!< PORT1 OMR: PR0 Mask */
\r
11167 #define PORT1_OMR_PR1_Pos 17 /*!< PORT1 OMR: PR1 Position */
\r
11168 #define PORT1_OMR_PR1_Msk (0x01UL << PORT1_OMR_PR1_Pos) /*!< PORT1 OMR: PR1 Mask */
\r
11169 #define PORT1_OMR_PR2_Pos 18 /*!< PORT1 OMR: PR2 Position */
\r
11170 #define PORT1_OMR_PR2_Msk (0x01UL << PORT1_OMR_PR2_Pos) /*!< PORT1 OMR: PR2 Mask */
\r
11171 #define PORT1_OMR_PR3_Pos 19 /*!< PORT1 OMR: PR3 Position */
\r
11172 #define PORT1_OMR_PR3_Msk (0x01UL << PORT1_OMR_PR3_Pos) /*!< PORT1 OMR: PR3 Mask */
\r
11173 #define PORT1_OMR_PR4_Pos 20 /*!< PORT1 OMR: PR4 Position */
\r
11174 #define PORT1_OMR_PR4_Msk (0x01UL << PORT1_OMR_PR4_Pos) /*!< PORT1 OMR: PR4 Mask */
\r
11175 #define PORT1_OMR_PR5_Pos 21 /*!< PORT1 OMR: PR5 Position */
\r
11176 #define PORT1_OMR_PR5_Msk (0x01UL << PORT1_OMR_PR5_Pos) /*!< PORT1 OMR: PR5 Mask */
\r
11177 #define PORT1_OMR_PR6_Pos 22 /*!< PORT1 OMR: PR6 Position */
\r
11178 #define PORT1_OMR_PR6_Msk (0x01UL << PORT1_OMR_PR6_Pos) /*!< PORT1 OMR: PR6 Mask */
\r
11179 #define PORT1_OMR_PR7_Pos 23 /*!< PORT1 OMR: PR7 Position */
\r
11180 #define PORT1_OMR_PR7_Msk (0x01UL << PORT1_OMR_PR7_Pos) /*!< PORT1 OMR: PR7 Mask */
\r
11181 #define PORT1_OMR_PR8_Pos 24 /*!< PORT1 OMR: PR8 Position */
\r
11182 #define PORT1_OMR_PR8_Msk (0x01UL << PORT1_OMR_PR8_Pos) /*!< PORT1 OMR: PR8 Mask */
\r
11183 #define PORT1_OMR_PR9_Pos 25 /*!< PORT1 OMR: PR9 Position */
\r
11184 #define PORT1_OMR_PR9_Msk (0x01UL << PORT1_OMR_PR9_Pos) /*!< PORT1 OMR: PR9 Mask */
\r
11185 #define PORT1_OMR_PR10_Pos 26 /*!< PORT1 OMR: PR10 Position */
\r
11186 #define PORT1_OMR_PR10_Msk (0x01UL << PORT1_OMR_PR10_Pos) /*!< PORT1 OMR: PR10 Mask */
\r
11187 #define PORT1_OMR_PR11_Pos 27 /*!< PORT1 OMR: PR11 Position */
\r
11188 #define PORT1_OMR_PR11_Msk (0x01UL << PORT1_OMR_PR11_Pos) /*!< PORT1 OMR: PR11 Mask */
\r
11189 #define PORT1_OMR_PR12_Pos 28 /*!< PORT1 OMR: PR12 Position */
\r
11190 #define PORT1_OMR_PR12_Msk (0x01UL << PORT1_OMR_PR12_Pos) /*!< PORT1 OMR: PR12 Mask */
\r
11191 #define PORT1_OMR_PR13_Pos 29 /*!< PORT1 OMR: PR13 Position */
\r
11192 #define PORT1_OMR_PR13_Msk (0x01UL << PORT1_OMR_PR13_Pos) /*!< PORT1 OMR: PR13 Mask */
\r
11193 #define PORT1_OMR_PR14_Pos 30 /*!< PORT1 OMR: PR14 Position */
\r
11194 #define PORT1_OMR_PR14_Msk (0x01UL << PORT1_OMR_PR14_Pos) /*!< PORT1 OMR: PR14 Mask */
\r
11195 #define PORT1_OMR_PR15_Pos 31 /*!< PORT1 OMR: PR15 Position */
\r
11196 #define PORT1_OMR_PR15_Msk (0x01UL << PORT1_OMR_PR15_Pos) /*!< PORT1 OMR: PR15 Mask */
\r
11198 // --------------------------------------- PORT1_IOCR0 ------------------------------------------
\r
11199 #define PORT1_IOCR0_PC0_Pos 3 /*!< PORT1 IOCR0: PC0 Position */
\r
11200 #define PORT1_IOCR0_PC0_Msk (0x1fUL << PORT1_IOCR0_PC0_Pos) /*!< PORT1 IOCR0: PC0 Mask */
\r
11201 #define PORT1_IOCR0_PC1_Pos 11 /*!< PORT1 IOCR0: PC1 Position */
\r
11202 #define PORT1_IOCR0_PC1_Msk (0x1fUL << PORT1_IOCR0_PC1_Pos) /*!< PORT1 IOCR0: PC1 Mask */
\r
11203 #define PORT1_IOCR0_PC2_Pos 19 /*!< PORT1 IOCR0: PC2 Position */
\r
11204 #define PORT1_IOCR0_PC2_Msk (0x1fUL << PORT1_IOCR0_PC2_Pos) /*!< PORT1 IOCR0: PC2 Mask */
\r
11205 #define PORT1_IOCR0_PC3_Pos 27 /*!< PORT1 IOCR0: PC3 Position */
\r
11206 #define PORT1_IOCR0_PC3_Msk (0x1fUL << PORT1_IOCR0_PC3_Pos) /*!< PORT1 IOCR0: PC3 Mask */
\r
11208 // --------------------------------------- PORT1_IOCR4 ------------------------------------------
\r
11209 #define PORT1_IOCR4_PC4_Pos 3 /*!< PORT1 IOCR4: PC4 Position */
\r
11210 #define PORT1_IOCR4_PC4_Msk (0x1fUL << PORT1_IOCR4_PC4_Pos) /*!< PORT1 IOCR4: PC4 Mask */
\r
11211 #define PORT1_IOCR4_PC5_Pos 11 /*!< PORT1 IOCR4: PC5 Position */
\r
11212 #define PORT1_IOCR4_PC5_Msk (0x1fUL << PORT1_IOCR4_PC5_Pos) /*!< PORT1 IOCR4: PC5 Mask */
\r
11213 #define PORT1_IOCR4_PC6_Pos 19 /*!< PORT1 IOCR4: PC6 Position */
\r
11214 #define PORT1_IOCR4_PC6_Msk (0x1fUL << PORT1_IOCR4_PC6_Pos) /*!< PORT1 IOCR4: PC6 Mask */
\r
11215 #define PORT1_IOCR4_PC7_Pos 27 /*!< PORT1 IOCR4: PC7 Position */
\r
11216 #define PORT1_IOCR4_PC7_Msk (0x1fUL << PORT1_IOCR4_PC7_Pos) /*!< PORT1 IOCR4: PC7 Mask */
\r
11218 // --------------------------------------- PORT1_IOCR8 ------------------------------------------
\r
11219 #define PORT1_IOCR8_PC8_Pos 3 /*!< PORT1 IOCR8: PC8 Position */
\r
11220 #define PORT1_IOCR8_PC8_Msk (0x1fUL << PORT1_IOCR8_PC8_Pos) /*!< PORT1 IOCR8: PC8 Mask */
\r
11221 #define PORT1_IOCR8_PC9_Pos 11 /*!< PORT1 IOCR8: PC9 Position */
\r
11222 #define PORT1_IOCR8_PC9_Msk (0x1fUL << PORT1_IOCR8_PC9_Pos) /*!< PORT1 IOCR8: PC9 Mask */
\r
11223 #define PORT1_IOCR8_PC10_Pos 19 /*!< PORT1 IOCR8: PC10 Position */
\r
11224 #define PORT1_IOCR8_PC10_Msk (0x1fUL << PORT1_IOCR8_PC10_Pos) /*!< PORT1 IOCR8: PC10 Mask */
\r
11225 #define PORT1_IOCR8_PC11_Pos 27 /*!< PORT1 IOCR8: PC11 Position */
\r
11226 #define PORT1_IOCR8_PC11_Msk (0x1fUL << PORT1_IOCR8_PC11_Pos) /*!< PORT1 IOCR8: PC11 Mask */
\r
11228 // -------------------------------------- PORT1_IOCR12 ------------------------------------------
\r
11229 #define PORT1_IOCR12_PC12_Pos 3 /*!< PORT1 IOCR12: PC12 Position */
\r
11230 #define PORT1_IOCR12_PC12_Msk (0x1fUL << PORT1_IOCR12_PC12_Pos) /*!< PORT1 IOCR12: PC12 Mask */
\r
11231 #define PORT1_IOCR12_PC13_Pos 11 /*!< PORT1 IOCR12: PC13 Position */
\r
11232 #define PORT1_IOCR12_PC13_Msk (0x1fUL << PORT1_IOCR12_PC13_Pos) /*!< PORT1 IOCR12: PC13 Mask */
\r
11233 #define PORT1_IOCR12_PC14_Pos 19 /*!< PORT1 IOCR12: PC14 Position */
\r
11234 #define PORT1_IOCR12_PC14_Msk (0x1fUL << PORT1_IOCR12_PC14_Pos) /*!< PORT1 IOCR12: PC14 Mask */
\r
11235 #define PORT1_IOCR12_PC15_Pos 27 /*!< PORT1 IOCR12: PC15 Position */
\r
11236 #define PORT1_IOCR12_PC15_Msk (0x1fUL << PORT1_IOCR12_PC15_Pos) /*!< PORT1 IOCR12: PC15 Mask */
\r
11238 // ---------------------------------------- PORT1_IN --------------------------------------------
\r
11239 #define PORT1_IN_P0_Pos 0 /*!< PORT1 IN: P0 Position */
\r
11240 #define PORT1_IN_P0_Msk (0x01UL << PORT1_IN_P0_Pos) /*!< PORT1 IN: P0 Mask */
\r
11241 #define PORT1_IN_P1_Pos 1 /*!< PORT1 IN: P1 Position */
\r
11242 #define PORT1_IN_P1_Msk (0x01UL << PORT1_IN_P1_Pos) /*!< PORT1 IN: P1 Mask */
\r
11243 #define PORT1_IN_P2_Pos 2 /*!< PORT1 IN: P2 Position */
\r
11244 #define PORT1_IN_P2_Msk (0x01UL << PORT1_IN_P2_Pos) /*!< PORT1 IN: P2 Mask */
\r
11245 #define PORT1_IN_P3_Pos 3 /*!< PORT1 IN: P3 Position */
\r
11246 #define PORT1_IN_P3_Msk (0x01UL << PORT1_IN_P3_Pos) /*!< PORT1 IN: P3 Mask */
\r
11247 #define PORT1_IN_P4_Pos 4 /*!< PORT1 IN: P4 Position */
\r
11248 #define PORT1_IN_P4_Msk (0x01UL << PORT1_IN_P4_Pos) /*!< PORT1 IN: P4 Mask */
\r
11249 #define PORT1_IN_P5_Pos 5 /*!< PORT1 IN: P5 Position */
\r
11250 #define PORT1_IN_P5_Msk (0x01UL << PORT1_IN_P5_Pos) /*!< PORT1 IN: P5 Mask */
\r
11251 #define PORT1_IN_P6_Pos 6 /*!< PORT1 IN: P6 Position */
\r
11252 #define PORT1_IN_P6_Msk (0x01UL << PORT1_IN_P6_Pos) /*!< PORT1 IN: P6 Mask */
\r
11253 #define PORT1_IN_P7_Pos 7 /*!< PORT1 IN: P7 Position */
\r
11254 #define PORT1_IN_P7_Msk (0x01UL << PORT1_IN_P7_Pos) /*!< PORT1 IN: P7 Mask */
\r
11255 #define PORT1_IN_P8_Pos 8 /*!< PORT1 IN: P8 Position */
\r
11256 #define PORT1_IN_P8_Msk (0x01UL << PORT1_IN_P8_Pos) /*!< PORT1 IN: P8 Mask */
\r
11257 #define PORT1_IN_P9_Pos 9 /*!< PORT1 IN: P9 Position */
\r
11258 #define PORT1_IN_P9_Msk (0x01UL << PORT1_IN_P9_Pos) /*!< PORT1 IN: P9 Mask */
\r
11259 #define PORT1_IN_P10_Pos 10 /*!< PORT1 IN: P10 Position */
\r
11260 #define PORT1_IN_P10_Msk (0x01UL << PORT1_IN_P10_Pos) /*!< PORT1 IN: P10 Mask */
\r
11261 #define PORT1_IN_P11_Pos 11 /*!< PORT1 IN: P11 Position */
\r
11262 #define PORT1_IN_P11_Msk (0x01UL << PORT1_IN_P11_Pos) /*!< PORT1 IN: P11 Mask */
\r
11263 #define PORT1_IN_P12_Pos 12 /*!< PORT1 IN: P12 Position */
\r
11264 #define PORT1_IN_P12_Msk (0x01UL << PORT1_IN_P12_Pos) /*!< PORT1 IN: P12 Mask */
\r
11265 #define PORT1_IN_P13_Pos 13 /*!< PORT1 IN: P13 Position */
\r
11266 #define PORT1_IN_P13_Msk (0x01UL << PORT1_IN_P13_Pos) /*!< PORT1 IN: P13 Mask */
\r
11267 #define PORT1_IN_P14_Pos 14 /*!< PORT1 IN: P14 Position */
\r
11268 #define PORT1_IN_P14_Msk (0x01UL << PORT1_IN_P14_Pos) /*!< PORT1 IN: P14 Mask */
\r
11269 #define PORT1_IN_P15_Pos 15 /*!< PORT1 IN: P15 Position */
\r
11270 #define PORT1_IN_P15_Msk (0x01UL << PORT1_IN_P15_Pos) /*!< PORT1 IN: P15 Mask */
\r
11272 // --------------------------------------- PORT1_PDR0 -------------------------------------------
\r
11273 #define PORT1_PDR0_PD0_Pos 0 /*!< PORT1 PDR0: PD0 Position */
\r
11274 #define PORT1_PDR0_PD0_Msk (0x07UL << PORT1_PDR0_PD0_Pos) /*!< PORT1 PDR0: PD0 Mask */
\r
11275 #define PORT1_PDR0_PD1_Pos 4 /*!< PORT1 PDR0: PD1 Position */
\r
11276 #define PORT1_PDR0_PD1_Msk (0x07UL << PORT1_PDR0_PD1_Pos) /*!< PORT1 PDR0: PD1 Mask */
\r
11277 #define PORT1_PDR0_PD2_Pos 8 /*!< PORT1 PDR0: PD2 Position */
\r
11278 #define PORT1_PDR0_PD2_Msk (0x07UL << PORT1_PDR0_PD2_Pos) /*!< PORT1 PDR0: PD2 Mask */
\r
11279 #define PORT1_PDR0_PD3_Pos 12 /*!< PORT1 PDR0: PD3 Position */
\r
11280 #define PORT1_PDR0_PD3_Msk (0x07UL << PORT1_PDR0_PD3_Pos) /*!< PORT1 PDR0: PD3 Mask */
\r
11281 #define PORT1_PDR0_PD4_Pos 16 /*!< PORT1 PDR0: PD4 Position */
\r
11282 #define PORT1_PDR0_PD4_Msk (0x07UL << PORT1_PDR0_PD4_Pos) /*!< PORT1 PDR0: PD4 Mask */
\r
11283 #define PORT1_PDR0_PD5_Pos 20 /*!< PORT1 PDR0: PD5 Position */
\r
11284 #define PORT1_PDR0_PD5_Msk (0x07UL << PORT1_PDR0_PD5_Pos) /*!< PORT1 PDR0: PD5 Mask */
\r
11285 #define PORT1_PDR0_PD6_Pos 24 /*!< PORT1 PDR0: PD6 Position */
\r
11286 #define PORT1_PDR0_PD6_Msk (0x07UL << PORT1_PDR0_PD6_Pos) /*!< PORT1 PDR0: PD6 Mask */
\r
11287 #define PORT1_PDR0_PD7_Pos 28 /*!< PORT1 PDR0: PD7 Position */
\r
11288 #define PORT1_PDR0_PD7_Msk (0x07UL << PORT1_PDR0_PD7_Pos) /*!< PORT1 PDR0: PD7 Mask */
\r
11290 // --------------------------------------- PORT1_PDR1 -------------------------------------------
\r
11291 #define PORT1_PDR1_PD8_Pos 0 /*!< PORT1 PDR1: PD8 Position */
\r
11292 #define PORT1_PDR1_PD8_Msk (0x07UL << PORT1_PDR1_PD8_Pos) /*!< PORT1 PDR1: PD8 Mask */
\r
11293 #define PORT1_PDR1_PD9_Pos 4 /*!< PORT1 PDR1: PD9 Position */
\r
11294 #define PORT1_PDR1_PD9_Msk (0x07UL << PORT1_PDR1_PD9_Pos) /*!< PORT1 PDR1: PD9 Mask */
\r
11295 #define PORT1_PDR1_PD10_Pos 8 /*!< PORT1 PDR1: PD10 Position */
\r
11296 #define PORT1_PDR1_PD10_Msk (0x07UL << PORT1_PDR1_PD10_Pos) /*!< PORT1 PDR1: PD10 Mask */
\r
11297 #define PORT1_PDR1_PD11_Pos 12 /*!< PORT1 PDR1: PD11 Position */
\r
11298 #define PORT1_PDR1_PD11_Msk (0x07UL << PORT1_PDR1_PD11_Pos) /*!< PORT1 PDR1: PD11 Mask */
\r
11299 #define PORT1_PDR1_PD12_Pos 16 /*!< PORT1 PDR1: PD12 Position */
\r
11300 #define PORT1_PDR1_PD12_Msk (0x07UL << PORT1_PDR1_PD12_Pos) /*!< PORT1 PDR1: PD12 Mask */
\r
11301 #define PORT1_PDR1_PD13_Pos 20 /*!< PORT1 PDR1: PD13 Position */
\r
11302 #define PORT1_PDR1_PD13_Msk (0x07UL << PORT1_PDR1_PD13_Pos) /*!< PORT1 PDR1: PD13 Mask */
\r
11303 #define PORT1_PDR1_PD14_Pos 24 /*!< PORT1 PDR1: PD14 Position */
\r
11304 #define PORT1_PDR1_PD14_Msk (0x07UL << PORT1_PDR1_PD14_Pos) /*!< PORT1 PDR1: PD14 Mask */
\r
11305 #define PORT1_PDR1_PD15_Pos 28 /*!< PORT1 PDR1: PD15 Position */
\r
11306 #define PORT1_PDR1_PD15_Msk (0x07UL << PORT1_PDR1_PD15_Pos) /*!< PORT1 PDR1: PD15 Mask */
\r
11308 // --------------------------------------- PORT1_PDISC ------------------------------------------
\r
11309 #define PORT1_PDISC_PDIS0_Pos 0 /*!< PORT1 PDISC: PDIS0 Position */
\r
11310 #define PORT1_PDISC_PDIS0_Msk (0x01UL << PORT1_PDISC_PDIS0_Pos) /*!< PORT1 PDISC: PDIS0 Mask */
\r
11311 #define PORT1_PDISC_PDIS1_Pos 1 /*!< PORT1 PDISC: PDIS1 Position */
\r
11312 #define PORT1_PDISC_PDIS1_Msk (0x01UL << PORT1_PDISC_PDIS1_Pos) /*!< PORT1 PDISC: PDIS1 Mask */
\r
11313 #define PORT1_PDISC_PDIS2_Pos 2 /*!< PORT1 PDISC: PDIS2 Position */
\r
11314 #define PORT1_PDISC_PDIS2_Msk (0x01UL << PORT1_PDISC_PDIS2_Pos) /*!< PORT1 PDISC: PDIS2 Mask */
\r
11315 #define PORT1_PDISC_PDIS3_Pos 3 /*!< PORT1 PDISC: PDIS3 Position */
\r
11316 #define PORT1_PDISC_PDIS3_Msk (0x01UL << PORT1_PDISC_PDIS3_Pos) /*!< PORT1 PDISC: PDIS3 Mask */
\r
11317 #define PORT1_PDISC_PDIS4_Pos 4 /*!< PORT1 PDISC: PDIS4 Position */
\r
11318 #define PORT1_PDISC_PDIS4_Msk (0x01UL << PORT1_PDISC_PDIS4_Pos) /*!< PORT1 PDISC: PDIS4 Mask */
\r
11319 #define PORT1_PDISC_PDIS5_Pos 5 /*!< PORT1 PDISC: PDIS5 Position */
\r
11320 #define PORT1_PDISC_PDIS5_Msk (0x01UL << PORT1_PDISC_PDIS5_Pos) /*!< PORT1 PDISC: PDIS5 Mask */
\r
11321 #define PORT1_PDISC_PDIS6_Pos 6 /*!< PORT1 PDISC: PDIS6 Position */
\r
11322 #define PORT1_PDISC_PDIS6_Msk (0x01UL << PORT1_PDISC_PDIS6_Pos) /*!< PORT1 PDISC: PDIS6 Mask */
\r
11323 #define PORT1_PDISC_PDIS7_Pos 7 /*!< PORT1 PDISC: PDIS7 Position */
\r
11324 #define PORT1_PDISC_PDIS7_Msk (0x01UL << PORT1_PDISC_PDIS7_Pos) /*!< PORT1 PDISC: PDIS7 Mask */
\r
11325 #define PORT1_PDISC_PDIS8_Pos 8 /*!< PORT1 PDISC: PDIS8 Position */
\r
11326 #define PORT1_PDISC_PDIS8_Msk (0x01UL << PORT1_PDISC_PDIS8_Pos) /*!< PORT1 PDISC: PDIS8 Mask */
\r
11327 #define PORT1_PDISC_PDIS9_Pos 9 /*!< PORT1 PDISC: PDIS9 Position */
\r
11328 #define PORT1_PDISC_PDIS9_Msk (0x01UL << PORT1_PDISC_PDIS9_Pos) /*!< PORT1 PDISC: PDIS9 Mask */
\r
11329 #define PORT1_PDISC_PDIS10_Pos 10 /*!< PORT1 PDISC: PDIS10 Position */
\r
11330 #define PORT1_PDISC_PDIS10_Msk (0x01UL << PORT1_PDISC_PDIS10_Pos) /*!< PORT1 PDISC: PDIS10 Mask */
\r
11331 #define PORT1_PDISC_PDIS11_Pos 11 /*!< PORT1 PDISC: PDIS11 Position */
\r
11332 #define PORT1_PDISC_PDIS11_Msk (0x01UL << PORT1_PDISC_PDIS11_Pos) /*!< PORT1 PDISC: PDIS11 Mask */
\r
11333 #define PORT1_PDISC_PDIS12_Pos 12 /*!< PORT1 PDISC: PDIS12 Position */
\r
11334 #define PORT1_PDISC_PDIS12_Msk (0x01UL << PORT1_PDISC_PDIS12_Pos) /*!< PORT1 PDISC: PDIS12 Mask */
\r
11335 #define PORT1_PDISC_PDIS13_Pos 13 /*!< PORT1 PDISC: PDIS13 Position */
\r
11336 #define PORT1_PDISC_PDIS13_Msk (0x01UL << PORT1_PDISC_PDIS13_Pos) /*!< PORT1 PDISC: PDIS13 Mask */
\r
11337 #define PORT1_PDISC_PDIS14_Pos 14 /*!< PORT1 PDISC: PDIS14 Position */
\r
11338 #define PORT1_PDISC_PDIS14_Msk (0x01UL << PORT1_PDISC_PDIS14_Pos) /*!< PORT1 PDISC: PDIS14 Mask */
\r
11339 #define PORT1_PDISC_PDIS15_Pos 15 /*!< PORT1 PDISC: PDIS15 Position */
\r
11340 #define PORT1_PDISC_PDIS15_Msk (0x01UL << PORT1_PDISC_PDIS15_Pos) /*!< PORT1 PDISC: PDIS15 Mask */
\r
11342 // ---------------------------------------- PORT1_PPS -------------------------------------------
\r
11343 #define PORT1_PPS_PPS0_Pos 0 /*!< PORT1 PPS: PPS0 Position */
\r
11344 #define PORT1_PPS_PPS0_Msk (0x01UL << PORT1_PPS_PPS0_Pos) /*!< PORT1 PPS: PPS0 Mask */
\r
11345 #define PORT1_PPS_PPS1_Pos 1 /*!< PORT1 PPS: PPS1 Position */
\r
11346 #define PORT1_PPS_PPS1_Msk (0x01UL << PORT1_PPS_PPS1_Pos) /*!< PORT1 PPS: PPS1 Mask */
\r
11347 #define PORT1_PPS_PPS2_Pos 2 /*!< PORT1 PPS: PPS2 Position */
\r
11348 #define PORT1_PPS_PPS2_Msk (0x01UL << PORT1_PPS_PPS2_Pos) /*!< PORT1 PPS: PPS2 Mask */
\r
11349 #define PORT1_PPS_PPS3_Pos 3 /*!< PORT1 PPS: PPS3 Position */
\r
11350 #define PORT1_PPS_PPS3_Msk (0x01UL << PORT1_PPS_PPS3_Pos) /*!< PORT1 PPS: PPS3 Mask */
\r
11351 #define PORT1_PPS_PPS4_Pos 4 /*!< PORT1 PPS: PPS4 Position */
\r
11352 #define PORT1_PPS_PPS4_Msk (0x01UL << PORT1_PPS_PPS4_Pos) /*!< PORT1 PPS: PPS4 Mask */
\r
11353 #define PORT1_PPS_PPS5_Pos 5 /*!< PORT1 PPS: PPS5 Position */
\r
11354 #define PORT1_PPS_PPS5_Msk (0x01UL << PORT1_PPS_PPS5_Pos) /*!< PORT1 PPS: PPS5 Mask */
\r
11355 #define PORT1_PPS_PPS6_Pos 6 /*!< PORT1 PPS: PPS6 Position */
\r
11356 #define PORT1_PPS_PPS6_Msk (0x01UL << PORT1_PPS_PPS6_Pos) /*!< PORT1 PPS: PPS6 Mask */
\r
11357 #define PORT1_PPS_PPS7_Pos 7 /*!< PORT1 PPS: PPS7 Position */
\r
11358 #define PORT1_PPS_PPS7_Msk (0x01UL << PORT1_PPS_PPS7_Pos) /*!< PORT1 PPS: PPS7 Mask */
\r
11359 #define PORT1_PPS_PPS8_Pos 8 /*!< PORT1 PPS: PPS8 Position */
\r
11360 #define PORT1_PPS_PPS8_Msk (0x01UL << PORT1_PPS_PPS8_Pos) /*!< PORT1 PPS: PPS8 Mask */
\r
11361 #define PORT1_PPS_PPS9_Pos 9 /*!< PORT1 PPS: PPS9 Position */
\r
11362 #define PORT1_PPS_PPS9_Msk (0x01UL << PORT1_PPS_PPS9_Pos) /*!< PORT1 PPS: PPS9 Mask */
\r
11363 #define PORT1_PPS_PPS10_Pos 10 /*!< PORT1 PPS: PPS10 Position */
\r
11364 #define PORT1_PPS_PPS10_Msk (0x01UL << PORT1_PPS_PPS10_Pos) /*!< PORT1 PPS: PPS10 Mask */
\r
11365 #define PORT1_PPS_PPS11_Pos 11 /*!< PORT1 PPS: PPS11 Position */
\r
11366 #define PORT1_PPS_PPS11_Msk (0x01UL << PORT1_PPS_PPS11_Pos) /*!< PORT1 PPS: PPS11 Mask */
\r
11367 #define PORT1_PPS_PPS12_Pos 12 /*!< PORT1 PPS: PPS12 Position */
\r
11368 #define PORT1_PPS_PPS12_Msk (0x01UL << PORT1_PPS_PPS12_Pos) /*!< PORT1 PPS: PPS12 Mask */
\r
11369 #define PORT1_PPS_PPS13_Pos 13 /*!< PORT1 PPS: PPS13 Position */
\r
11370 #define PORT1_PPS_PPS13_Msk (0x01UL << PORT1_PPS_PPS13_Pos) /*!< PORT1 PPS: PPS13 Mask */
\r
11371 #define PORT1_PPS_PPS14_Pos 14 /*!< PORT1 PPS: PPS14 Position */
\r
11372 #define PORT1_PPS_PPS14_Msk (0x01UL << PORT1_PPS_PPS14_Pos) /*!< PORT1 PPS: PPS14 Mask */
\r
11373 #define PORT1_PPS_PPS15_Pos 15 /*!< PORT1 PPS: PPS15 Position */
\r
11374 #define PORT1_PPS_PPS15_Msk (0x01UL << PORT1_PPS_PPS15_Pos) /*!< PORT1 PPS: PPS15 Mask */
\r
11376 // --------------------------------------- PORT1_HWSEL ------------------------------------------
\r
11377 #define PORT1_HWSEL_HW0_Pos 0 /*!< PORT1 HWSEL: HW0 Position */
\r
11378 #define PORT1_HWSEL_HW0_Msk (0x03UL << PORT1_HWSEL_HW0_Pos) /*!< PORT1 HWSEL: HW0 Mask */
\r
11379 #define PORT1_HWSEL_HW1_Pos 2 /*!< PORT1 HWSEL: HW1 Position */
\r
11380 #define PORT1_HWSEL_HW1_Msk (0x03UL << PORT1_HWSEL_HW1_Pos) /*!< PORT1 HWSEL: HW1 Mask */
\r
11381 #define PORT1_HWSEL_HW2_Pos 4 /*!< PORT1 HWSEL: HW2 Position */
\r
11382 #define PORT1_HWSEL_HW2_Msk (0x03UL << PORT1_HWSEL_HW2_Pos) /*!< PORT1 HWSEL: HW2 Mask */
\r
11383 #define PORT1_HWSEL_HW3_Pos 6 /*!< PORT1 HWSEL: HW3 Position */
\r
11384 #define PORT1_HWSEL_HW3_Msk (0x03UL << PORT1_HWSEL_HW3_Pos) /*!< PORT1 HWSEL: HW3 Mask */
\r
11385 #define PORT1_HWSEL_HW4_Pos 8 /*!< PORT1 HWSEL: HW4 Position */
\r
11386 #define PORT1_HWSEL_HW4_Msk (0x03UL << PORT1_HWSEL_HW4_Pos) /*!< PORT1 HWSEL: HW4 Mask */
\r
11387 #define PORT1_HWSEL_HW5_Pos 10 /*!< PORT1 HWSEL: HW5 Position */
\r
11388 #define PORT1_HWSEL_HW5_Msk (0x03UL << PORT1_HWSEL_HW5_Pos) /*!< PORT1 HWSEL: HW5 Mask */
\r
11389 #define PORT1_HWSEL_HW6_Pos 12 /*!< PORT1 HWSEL: HW6 Position */
\r
11390 #define PORT1_HWSEL_HW6_Msk (0x03UL << PORT1_HWSEL_HW6_Pos) /*!< PORT1 HWSEL: HW6 Mask */
\r
11391 #define PORT1_HWSEL_HW7_Pos 14 /*!< PORT1 HWSEL: HW7 Position */
\r
11392 #define PORT1_HWSEL_HW7_Msk (0x03UL << PORT1_HWSEL_HW7_Pos) /*!< PORT1 HWSEL: HW7 Mask */
\r
11393 #define PORT1_HWSEL_HW8_Pos 16 /*!< PORT1 HWSEL: HW8 Position */
\r
11394 #define PORT1_HWSEL_HW8_Msk (0x03UL << PORT1_HWSEL_HW8_Pos) /*!< PORT1 HWSEL: HW8 Mask */
\r
11395 #define PORT1_HWSEL_HW9_Pos 18 /*!< PORT1 HWSEL: HW9 Position */
\r
11396 #define PORT1_HWSEL_HW9_Msk (0x03UL << PORT1_HWSEL_HW9_Pos) /*!< PORT1 HWSEL: HW9 Mask */
\r
11397 #define PORT1_HWSEL_HW10_Pos 20 /*!< PORT1 HWSEL: HW10 Position */
\r
11398 #define PORT1_HWSEL_HW10_Msk (0x03UL << PORT1_HWSEL_HW10_Pos) /*!< PORT1 HWSEL: HW10 Mask */
\r
11399 #define PORT1_HWSEL_HW11_Pos 22 /*!< PORT1 HWSEL: HW11 Position */
\r
11400 #define PORT1_HWSEL_HW11_Msk (0x03UL << PORT1_HWSEL_HW11_Pos) /*!< PORT1 HWSEL: HW11 Mask */
\r
11401 #define PORT1_HWSEL_HW12_Pos 24 /*!< PORT1 HWSEL: HW12 Position */
\r
11402 #define PORT1_HWSEL_HW12_Msk (0x03UL << PORT1_HWSEL_HW12_Pos) /*!< PORT1 HWSEL: HW12 Mask */
\r
11403 #define PORT1_HWSEL_HW13_Pos 26 /*!< PORT1 HWSEL: HW13 Position */
\r
11404 #define PORT1_HWSEL_HW13_Msk (0x03UL << PORT1_HWSEL_HW13_Pos) /*!< PORT1 HWSEL: HW13 Mask */
\r
11405 #define PORT1_HWSEL_HW14_Pos 28 /*!< PORT1 HWSEL: HW14 Position */
\r
11406 #define PORT1_HWSEL_HW14_Msk (0x03UL << PORT1_HWSEL_HW14_Pos) /*!< PORT1 HWSEL: HW14 Mask */
\r
11407 #define PORT1_HWSEL_HW15_Pos 30 /*!< PORT1 HWSEL: HW15 Position */
\r
11408 #define PORT1_HWSEL_HW15_Msk (0x03UL << PORT1_HWSEL_HW15_Pos) /*!< PORT1 HWSEL: HW15 Mask */
\r
11411 // ------------------------------------------------------------------------------------------------
\r
11412 // ----- PORT2 Position & Mask -----
\r
11413 // ------------------------------------------------------------------------------------------------
\r
11416 // ---------------------------------------- PORT2_OUT -------------------------------------------
\r
11417 #define PORT2_OUT_P0_Pos 0 /*!< PORT2 OUT: P0 Position */
\r
11418 #define PORT2_OUT_P0_Msk (0x01UL << PORT2_OUT_P0_Pos) /*!< PORT2 OUT: P0 Mask */
\r
11419 #define PORT2_OUT_P1_Pos 1 /*!< PORT2 OUT: P1 Position */
\r
11420 #define PORT2_OUT_P1_Msk (0x01UL << PORT2_OUT_P1_Pos) /*!< PORT2 OUT: P1 Mask */
\r
11421 #define PORT2_OUT_P2_Pos 2 /*!< PORT2 OUT: P2 Position */
\r
11422 #define PORT2_OUT_P2_Msk (0x01UL << PORT2_OUT_P2_Pos) /*!< PORT2 OUT: P2 Mask */
\r
11423 #define PORT2_OUT_P3_Pos 3 /*!< PORT2 OUT: P3 Position */
\r
11424 #define PORT2_OUT_P3_Msk (0x01UL << PORT2_OUT_P3_Pos) /*!< PORT2 OUT: P3 Mask */
\r
11425 #define PORT2_OUT_P4_Pos 4 /*!< PORT2 OUT: P4 Position */
\r
11426 #define PORT2_OUT_P4_Msk (0x01UL << PORT2_OUT_P4_Pos) /*!< PORT2 OUT: P4 Mask */
\r
11427 #define PORT2_OUT_P5_Pos 5 /*!< PORT2 OUT: P5 Position */
\r
11428 #define PORT2_OUT_P5_Msk (0x01UL << PORT2_OUT_P5_Pos) /*!< PORT2 OUT: P5 Mask */
\r
11429 #define PORT2_OUT_P6_Pos 6 /*!< PORT2 OUT: P6 Position */
\r
11430 #define PORT2_OUT_P6_Msk (0x01UL << PORT2_OUT_P6_Pos) /*!< PORT2 OUT: P6 Mask */
\r
11431 #define PORT2_OUT_P7_Pos 7 /*!< PORT2 OUT: P7 Position */
\r
11432 #define PORT2_OUT_P7_Msk (0x01UL << PORT2_OUT_P7_Pos) /*!< PORT2 OUT: P7 Mask */
\r
11433 #define PORT2_OUT_P8_Pos 8 /*!< PORT2 OUT: P8 Position */
\r
11434 #define PORT2_OUT_P8_Msk (0x01UL << PORT2_OUT_P8_Pos) /*!< PORT2 OUT: P8 Mask */
\r
11435 #define PORT2_OUT_P9_Pos 9 /*!< PORT2 OUT: P9 Position */
\r
11436 #define PORT2_OUT_P9_Msk (0x01UL << PORT2_OUT_P9_Pos) /*!< PORT2 OUT: P9 Mask */
\r
11437 #define PORT2_OUT_P10_Pos 10 /*!< PORT2 OUT: P10 Position */
\r
11438 #define PORT2_OUT_P10_Msk (0x01UL << PORT2_OUT_P10_Pos) /*!< PORT2 OUT: P10 Mask */
\r
11439 #define PORT2_OUT_P11_Pos 11 /*!< PORT2 OUT: P11 Position */
\r
11440 #define PORT2_OUT_P11_Msk (0x01UL << PORT2_OUT_P11_Pos) /*!< PORT2 OUT: P11 Mask */
\r
11441 #define PORT2_OUT_P12_Pos 12 /*!< PORT2 OUT: P12 Position */
\r
11442 #define PORT2_OUT_P12_Msk (0x01UL << PORT2_OUT_P12_Pos) /*!< PORT2 OUT: P12 Mask */
\r
11443 #define PORT2_OUT_P13_Pos 13 /*!< PORT2 OUT: P13 Position */
\r
11444 #define PORT2_OUT_P13_Msk (0x01UL << PORT2_OUT_P13_Pos) /*!< PORT2 OUT: P13 Mask */
\r
11445 #define PORT2_OUT_P14_Pos 14 /*!< PORT2 OUT: P14 Position */
\r
11446 #define PORT2_OUT_P14_Msk (0x01UL << PORT2_OUT_P14_Pos) /*!< PORT2 OUT: P14 Mask */
\r
11447 #define PORT2_OUT_P15_Pos 15 /*!< PORT2 OUT: P15 Position */
\r
11448 #define PORT2_OUT_P15_Msk (0x01UL << PORT2_OUT_P15_Pos) /*!< PORT2 OUT: P15 Mask */
\r
11450 // ---------------------------------------- PORT2_OMR -------------------------------------------
\r
11451 #define PORT2_OMR_PS0_Pos 0 /*!< PORT2 OMR: PS0 Position */
\r
11452 #define PORT2_OMR_PS0_Msk (0x01UL << PORT2_OMR_PS0_Pos) /*!< PORT2 OMR: PS0 Mask */
\r
11453 #define PORT2_OMR_PS1_Pos 1 /*!< PORT2 OMR: PS1 Position */
\r
11454 #define PORT2_OMR_PS1_Msk (0x01UL << PORT2_OMR_PS1_Pos) /*!< PORT2 OMR: PS1 Mask */
\r
11455 #define PORT2_OMR_PS2_Pos 2 /*!< PORT2 OMR: PS2 Position */
\r
11456 #define PORT2_OMR_PS2_Msk (0x01UL << PORT2_OMR_PS2_Pos) /*!< PORT2 OMR: PS2 Mask */
\r
11457 #define PORT2_OMR_PS3_Pos 3 /*!< PORT2 OMR: PS3 Position */
\r
11458 #define PORT2_OMR_PS3_Msk (0x01UL << PORT2_OMR_PS3_Pos) /*!< PORT2 OMR: PS3 Mask */
\r
11459 #define PORT2_OMR_PS4_Pos 4 /*!< PORT2 OMR: PS4 Position */
\r
11460 #define PORT2_OMR_PS4_Msk (0x01UL << PORT2_OMR_PS4_Pos) /*!< PORT2 OMR: PS4 Mask */
\r
11461 #define PORT2_OMR_PS5_Pos 5 /*!< PORT2 OMR: PS5 Position */
\r
11462 #define PORT2_OMR_PS5_Msk (0x01UL << PORT2_OMR_PS5_Pos) /*!< PORT2 OMR: PS5 Mask */
\r
11463 #define PORT2_OMR_PS6_Pos 6 /*!< PORT2 OMR: PS6 Position */
\r
11464 #define PORT2_OMR_PS6_Msk (0x01UL << PORT2_OMR_PS6_Pos) /*!< PORT2 OMR: PS6 Mask */
\r
11465 #define PORT2_OMR_PS7_Pos 7 /*!< PORT2 OMR: PS7 Position */
\r
11466 #define PORT2_OMR_PS7_Msk (0x01UL << PORT2_OMR_PS7_Pos) /*!< PORT2 OMR: PS7 Mask */
\r
11467 #define PORT2_OMR_PS8_Pos 8 /*!< PORT2 OMR: PS8 Position */
\r
11468 #define PORT2_OMR_PS8_Msk (0x01UL << PORT2_OMR_PS8_Pos) /*!< PORT2 OMR: PS8 Mask */
\r
11469 #define PORT2_OMR_PS9_Pos 9 /*!< PORT2 OMR: PS9 Position */
\r
11470 #define PORT2_OMR_PS9_Msk (0x01UL << PORT2_OMR_PS9_Pos) /*!< PORT2 OMR: PS9 Mask */
\r
11471 #define PORT2_OMR_PS10_Pos 10 /*!< PORT2 OMR: PS10 Position */
\r
11472 #define PORT2_OMR_PS10_Msk (0x01UL << PORT2_OMR_PS10_Pos) /*!< PORT2 OMR: PS10 Mask */
\r
11473 #define PORT2_OMR_PS11_Pos 11 /*!< PORT2 OMR: PS11 Position */
\r
11474 #define PORT2_OMR_PS11_Msk (0x01UL << PORT2_OMR_PS11_Pos) /*!< PORT2 OMR: PS11 Mask */
\r
11475 #define PORT2_OMR_PS12_Pos 12 /*!< PORT2 OMR: PS12 Position */
\r
11476 #define PORT2_OMR_PS12_Msk (0x01UL << PORT2_OMR_PS12_Pos) /*!< PORT2 OMR: PS12 Mask */
\r
11477 #define PORT2_OMR_PS13_Pos 13 /*!< PORT2 OMR: PS13 Position */
\r
11478 #define PORT2_OMR_PS13_Msk (0x01UL << PORT2_OMR_PS13_Pos) /*!< PORT2 OMR: PS13 Mask */
\r
11479 #define PORT2_OMR_PS14_Pos 14 /*!< PORT2 OMR: PS14 Position */
\r
11480 #define PORT2_OMR_PS14_Msk (0x01UL << PORT2_OMR_PS14_Pos) /*!< PORT2 OMR: PS14 Mask */
\r
11481 #define PORT2_OMR_PS15_Pos 15 /*!< PORT2 OMR: PS15 Position */
\r
11482 #define PORT2_OMR_PS15_Msk (0x01UL << PORT2_OMR_PS15_Pos) /*!< PORT2 OMR: PS15 Mask */
\r
11483 #define PORT2_OMR_PR0_Pos 16 /*!< PORT2 OMR: PR0 Position */
\r
11484 #define PORT2_OMR_PR0_Msk (0x01UL << PORT2_OMR_PR0_Pos) /*!< PORT2 OMR: PR0 Mask */
\r
11485 #define PORT2_OMR_PR1_Pos 17 /*!< PORT2 OMR: PR1 Position */
\r
11486 #define PORT2_OMR_PR1_Msk (0x01UL << PORT2_OMR_PR1_Pos) /*!< PORT2 OMR: PR1 Mask */
\r
11487 #define PORT2_OMR_PR2_Pos 18 /*!< PORT2 OMR: PR2 Position */
\r
11488 #define PORT2_OMR_PR2_Msk (0x01UL << PORT2_OMR_PR2_Pos) /*!< PORT2 OMR: PR2 Mask */
\r
11489 #define PORT2_OMR_PR3_Pos 19 /*!< PORT2 OMR: PR3 Position */
\r
11490 #define PORT2_OMR_PR3_Msk (0x01UL << PORT2_OMR_PR3_Pos) /*!< PORT2 OMR: PR3 Mask */
\r
11491 #define PORT2_OMR_PR4_Pos 20 /*!< PORT2 OMR: PR4 Position */
\r
11492 #define PORT2_OMR_PR4_Msk (0x01UL << PORT2_OMR_PR4_Pos) /*!< PORT2 OMR: PR4 Mask */
\r
11493 #define PORT2_OMR_PR5_Pos 21 /*!< PORT2 OMR: PR5 Position */
\r
11494 #define PORT2_OMR_PR5_Msk (0x01UL << PORT2_OMR_PR5_Pos) /*!< PORT2 OMR: PR5 Mask */
\r
11495 #define PORT2_OMR_PR6_Pos 22 /*!< PORT2 OMR: PR6 Position */
\r
11496 #define PORT2_OMR_PR6_Msk (0x01UL << PORT2_OMR_PR6_Pos) /*!< PORT2 OMR: PR6 Mask */
\r
11497 #define PORT2_OMR_PR7_Pos 23 /*!< PORT2 OMR: PR7 Position */
\r
11498 #define PORT2_OMR_PR7_Msk (0x01UL << PORT2_OMR_PR7_Pos) /*!< PORT2 OMR: PR7 Mask */
\r
11499 #define PORT2_OMR_PR8_Pos 24 /*!< PORT2 OMR: PR8 Position */
\r
11500 #define PORT2_OMR_PR8_Msk (0x01UL << PORT2_OMR_PR8_Pos) /*!< PORT2 OMR: PR8 Mask */
\r
11501 #define PORT2_OMR_PR9_Pos 25 /*!< PORT2 OMR: PR9 Position */
\r
11502 #define PORT2_OMR_PR9_Msk (0x01UL << PORT2_OMR_PR9_Pos) /*!< PORT2 OMR: PR9 Mask */
\r
11503 #define PORT2_OMR_PR10_Pos 26 /*!< PORT2 OMR: PR10 Position */
\r
11504 #define PORT2_OMR_PR10_Msk (0x01UL << PORT2_OMR_PR10_Pos) /*!< PORT2 OMR: PR10 Mask */
\r
11505 #define PORT2_OMR_PR11_Pos 27 /*!< PORT2 OMR: PR11 Position */
\r
11506 #define PORT2_OMR_PR11_Msk (0x01UL << PORT2_OMR_PR11_Pos) /*!< PORT2 OMR: PR11 Mask */
\r
11507 #define PORT2_OMR_PR12_Pos 28 /*!< PORT2 OMR: PR12 Position */
\r
11508 #define PORT2_OMR_PR12_Msk (0x01UL << PORT2_OMR_PR12_Pos) /*!< PORT2 OMR: PR12 Mask */
\r
11509 #define PORT2_OMR_PR13_Pos 29 /*!< PORT2 OMR: PR13 Position */
\r
11510 #define PORT2_OMR_PR13_Msk (0x01UL << PORT2_OMR_PR13_Pos) /*!< PORT2 OMR: PR13 Mask */
\r
11511 #define PORT2_OMR_PR14_Pos 30 /*!< PORT2 OMR: PR14 Position */
\r
11512 #define PORT2_OMR_PR14_Msk (0x01UL << PORT2_OMR_PR14_Pos) /*!< PORT2 OMR: PR14 Mask */
\r
11513 #define PORT2_OMR_PR15_Pos 31 /*!< PORT2 OMR: PR15 Position */
\r
11514 #define PORT2_OMR_PR15_Msk (0x01UL << PORT2_OMR_PR15_Pos) /*!< PORT2 OMR: PR15 Mask */
\r
11516 // --------------------------------------- PORT2_IOCR0 ------------------------------------------
\r
11517 #define PORT2_IOCR0_PC0_Pos 3 /*!< PORT2 IOCR0: PC0 Position */
\r
11518 #define PORT2_IOCR0_PC0_Msk (0x1fUL << PORT2_IOCR0_PC0_Pos) /*!< PORT2 IOCR0: PC0 Mask */
\r
11519 #define PORT2_IOCR0_PC1_Pos 11 /*!< PORT2 IOCR0: PC1 Position */
\r
11520 #define PORT2_IOCR0_PC1_Msk (0x1fUL << PORT2_IOCR0_PC1_Pos) /*!< PORT2 IOCR0: PC1 Mask */
\r
11521 #define PORT2_IOCR0_PC2_Pos 19 /*!< PORT2 IOCR0: PC2 Position */
\r
11522 #define PORT2_IOCR0_PC2_Msk (0x1fUL << PORT2_IOCR0_PC2_Pos) /*!< PORT2 IOCR0: PC2 Mask */
\r
11523 #define PORT2_IOCR0_PC3_Pos 27 /*!< PORT2 IOCR0: PC3 Position */
\r
11524 #define PORT2_IOCR0_PC3_Msk (0x1fUL << PORT2_IOCR0_PC3_Pos) /*!< PORT2 IOCR0: PC3 Mask */
\r
11526 // --------------------------------------- PORT2_IOCR4 ------------------------------------------
\r
11527 #define PORT2_IOCR4_PC4_Pos 3 /*!< PORT2 IOCR4: PC4 Position */
\r
11528 #define PORT2_IOCR4_PC4_Msk (0x1fUL << PORT2_IOCR4_PC4_Pos) /*!< PORT2 IOCR4: PC4 Mask */
\r
11529 #define PORT2_IOCR4_PC5_Pos 11 /*!< PORT2 IOCR4: PC5 Position */
\r
11530 #define PORT2_IOCR4_PC5_Msk (0x1fUL << PORT2_IOCR4_PC5_Pos) /*!< PORT2 IOCR4: PC5 Mask */
\r
11531 #define PORT2_IOCR4_PC6_Pos 19 /*!< PORT2 IOCR4: PC6 Position */
\r
11532 #define PORT2_IOCR4_PC6_Msk (0x1fUL << PORT2_IOCR4_PC6_Pos) /*!< PORT2 IOCR4: PC6 Mask */
\r
11533 #define PORT2_IOCR4_PC7_Pos 27 /*!< PORT2 IOCR4: PC7 Position */
\r
11534 #define PORT2_IOCR4_PC7_Msk (0x1fUL << PORT2_IOCR4_PC7_Pos) /*!< PORT2 IOCR4: PC7 Mask */
\r
11536 // --------------------------------------- PORT2_IOCR8 ------------------------------------------
\r
11537 #define PORT2_IOCR8_PC8_Pos 3 /*!< PORT2 IOCR8: PC8 Position */
\r
11538 #define PORT2_IOCR8_PC8_Msk (0x1fUL << PORT2_IOCR8_PC8_Pos) /*!< PORT2 IOCR8: PC8 Mask */
\r
11539 #define PORT2_IOCR8_PC9_Pos 11 /*!< PORT2 IOCR8: PC9 Position */
\r
11540 #define PORT2_IOCR8_PC9_Msk (0x1fUL << PORT2_IOCR8_PC9_Pos) /*!< PORT2 IOCR8: PC9 Mask */
\r
11541 #define PORT2_IOCR8_PC10_Pos 19 /*!< PORT2 IOCR8: PC10 Position */
\r
11542 #define PORT2_IOCR8_PC10_Msk (0x1fUL << PORT2_IOCR8_PC10_Pos) /*!< PORT2 IOCR8: PC10 Mask */
\r
11543 #define PORT2_IOCR8_PC11_Pos 27 /*!< PORT2 IOCR8: PC11 Position */
\r
11544 #define PORT2_IOCR8_PC11_Msk (0x1fUL << PORT2_IOCR8_PC11_Pos) /*!< PORT2 IOCR8: PC11 Mask */
\r
11546 // -------------------------------------- PORT2_IOCR12 ------------------------------------------
\r
11547 #define PORT2_IOCR12_PC12_Pos 3 /*!< PORT2 IOCR12: PC12 Position */
\r
11548 #define PORT2_IOCR12_PC12_Msk (0x1fUL << PORT2_IOCR12_PC12_Pos) /*!< PORT2 IOCR12: PC12 Mask */
\r
11549 #define PORT2_IOCR12_PC13_Pos 11 /*!< PORT2 IOCR12: PC13 Position */
\r
11550 #define PORT2_IOCR12_PC13_Msk (0x1fUL << PORT2_IOCR12_PC13_Pos) /*!< PORT2 IOCR12: PC13 Mask */
\r
11551 #define PORT2_IOCR12_PC14_Pos 19 /*!< PORT2 IOCR12: PC14 Position */
\r
11552 #define PORT2_IOCR12_PC14_Msk (0x1fUL << PORT2_IOCR12_PC14_Pos) /*!< PORT2 IOCR12: PC14 Mask */
\r
11553 #define PORT2_IOCR12_PC15_Pos 27 /*!< PORT2 IOCR12: PC15 Position */
\r
11554 #define PORT2_IOCR12_PC15_Msk (0x1fUL << PORT2_IOCR12_PC15_Pos) /*!< PORT2 IOCR12: PC15 Mask */
\r
11556 // ---------------------------------------- PORT2_IN --------------------------------------------
\r
11557 #define PORT2_IN_P0_Pos 0 /*!< PORT2 IN: P0 Position */
\r
11558 #define PORT2_IN_P0_Msk (0x01UL << PORT2_IN_P0_Pos) /*!< PORT2 IN: P0 Mask */
\r
11559 #define PORT2_IN_P1_Pos 1 /*!< PORT2 IN: P1 Position */
\r
11560 #define PORT2_IN_P1_Msk (0x01UL << PORT2_IN_P1_Pos) /*!< PORT2 IN: P1 Mask */
\r
11561 #define PORT2_IN_P2_Pos 2 /*!< PORT2 IN: P2 Position */
\r
11562 #define PORT2_IN_P2_Msk (0x01UL << PORT2_IN_P2_Pos) /*!< PORT2 IN: P2 Mask */
\r
11563 #define PORT2_IN_P3_Pos 3 /*!< PORT2 IN: P3 Position */
\r
11564 #define PORT2_IN_P3_Msk (0x01UL << PORT2_IN_P3_Pos) /*!< PORT2 IN: P3 Mask */
\r
11565 #define PORT2_IN_P4_Pos 4 /*!< PORT2 IN: P4 Position */
\r
11566 #define PORT2_IN_P4_Msk (0x01UL << PORT2_IN_P4_Pos) /*!< PORT2 IN: P4 Mask */
\r
11567 #define PORT2_IN_P5_Pos 5 /*!< PORT2 IN: P5 Position */
\r
11568 #define PORT2_IN_P5_Msk (0x01UL << PORT2_IN_P5_Pos) /*!< PORT2 IN: P5 Mask */
\r
11569 #define PORT2_IN_P6_Pos 6 /*!< PORT2 IN: P6 Position */
\r
11570 #define PORT2_IN_P6_Msk (0x01UL << PORT2_IN_P6_Pos) /*!< PORT2 IN: P6 Mask */
\r
11571 #define PORT2_IN_P7_Pos 7 /*!< PORT2 IN: P7 Position */
\r
11572 #define PORT2_IN_P7_Msk (0x01UL << PORT2_IN_P7_Pos) /*!< PORT2 IN: P7 Mask */
\r
11573 #define PORT2_IN_P8_Pos 8 /*!< PORT2 IN: P8 Position */
\r
11574 #define PORT2_IN_P8_Msk (0x01UL << PORT2_IN_P8_Pos) /*!< PORT2 IN: P8 Mask */
\r
11575 #define PORT2_IN_P9_Pos 9 /*!< PORT2 IN: P9 Position */
\r
11576 #define PORT2_IN_P9_Msk (0x01UL << PORT2_IN_P9_Pos) /*!< PORT2 IN: P9 Mask */
\r
11577 #define PORT2_IN_P10_Pos 10 /*!< PORT2 IN: P10 Position */
\r
11578 #define PORT2_IN_P10_Msk (0x01UL << PORT2_IN_P10_Pos) /*!< PORT2 IN: P10 Mask */
\r
11579 #define PORT2_IN_P11_Pos 11 /*!< PORT2 IN: P11 Position */
\r
11580 #define PORT2_IN_P11_Msk (0x01UL << PORT2_IN_P11_Pos) /*!< PORT2 IN: P11 Mask */
\r
11581 #define PORT2_IN_P12_Pos 12 /*!< PORT2 IN: P12 Position */
\r
11582 #define PORT2_IN_P12_Msk (0x01UL << PORT2_IN_P12_Pos) /*!< PORT2 IN: P12 Mask */
\r
11583 #define PORT2_IN_P13_Pos 13 /*!< PORT2 IN: P13 Position */
\r
11584 #define PORT2_IN_P13_Msk (0x01UL << PORT2_IN_P13_Pos) /*!< PORT2 IN: P13 Mask */
\r
11585 #define PORT2_IN_P14_Pos 14 /*!< PORT2 IN: P14 Position */
\r
11586 #define PORT2_IN_P14_Msk (0x01UL << PORT2_IN_P14_Pos) /*!< PORT2 IN: P14 Mask */
\r
11587 #define PORT2_IN_P15_Pos 15 /*!< PORT2 IN: P15 Position */
\r
11588 #define PORT2_IN_P15_Msk (0x01UL << PORT2_IN_P15_Pos) /*!< PORT2 IN: P15 Mask */
\r
11590 // --------------------------------------- PORT2_PDR0 -------------------------------------------
\r
11591 #define PORT2_PDR0_PD0_Pos 0 /*!< PORT2 PDR0: PD0 Position */
\r
11592 #define PORT2_PDR0_PD0_Msk (0x07UL << PORT2_PDR0_PD0_Pos) /*!< PORT2 PDR0: PD0 Mask */
\r
11593 #define PORT2_PDR0_PD1_Pos 4 /*!< PORT2 PDR0: PD1 Position */
\r
11594 #define PORT2_PDR0_PD1_Msk (0x07UL << PORT2_PDR0_PD1_Pos) /*!< PORT2 PDR0: PD1 Mask */
\r
11595 #define PORT2_PDR0_PD2_Pos 8 /*!< PORT2 PDR0: PD2 Position */
\r
11596 #define PORT2_PDR0_PD2_Msk (0x07UL << PORT2_PDR0_PD2_Pos) /*!< PORT2 PDR0: PD2 Mask */
\r
11597 #define PORT2_PDR0_PD3_Pos 12 /*!< PORT2 PDR0: PD3 Position */
\r
11598 #define PORT2_PDR0_PD3_Msk (0x07UL << PORT2_PDR0_PD3_Pos) /*!< PORT2 PDR0: PD3 Mask */
\r
11599 #define PORT2_PDR0_PD4_Pos 16 /*!< PORT2 PDR0: PD4 Position */
\r
11600 #define PORT2_PDR0_PD4_Msk (0x07UL << PORT2_PDR0_PD4_Pos) /*!< PORT2 PDR0: PD4 Mask */
\r
11601 #define PORT2_PDR0_PD5_Pos 20 /*!< PORT2 PDR0: PD5 Position */
\r
11602 #define PORT2_PDR0_PD5_Msk (0x07UL << PORT2_PDR0_PD5_Pos) /*!< PORT2 PDR0: PD5 Mask */
\r
11603 #define PORT2_PDR0_PD6_Pos 24 /*!< PORT2 PDR0: PD6 Position */
\r
11604 #define PORT2_PDR0_PD6_Msk (0x07UL << PORT2_PDR0_PD6_Pos) /*!< PORT2 PDR0: PD6 Mask */
\r
11605 #define PORT2_PDR0_PD7_Pos 28 /*!< PORT2 PDR0: PD7 Position */
\r
11606 #define PORT2_PDR0_PD7_Msk (0x07UL << PORT2_PDR0_PD7_Pos) /*!< PORT2 PDR0: PD7 Mask */
\r
11608 // --------------------------------------- PORT2_PDR1 -------------------------------------------
\r
11609 #define PORT2_PDR1_PD8_Pos 0 /*!< PORT2 PDR1: PD8 Position */
\r
11610 #define PORT2_PDR1_PD8_Msk (0x07UL << PORT2_PDR1_PD8_Pos) /*!< PORT2 PDR1: PD8 Mask */
\r
11611 #define PORT2_PDR1_PD9_Pos 4 /*!< PORT2 PDR1: PD9 Position */
\r
11612 #define PORT2_PDR1_PD9_Msk (0x07UL << PORT2_PDR1_PD9_Pos) /*!< PORT2 PDR1: PD9 Mask */
\r
11613 #define PORT2_PDR1_PD10_Pos 8 /*!< PORT2 PDR1: PD10 Position */
\r
11614 #define PORT2_PDR1_PD10_Msk (0x07UL << PORT2_PDR1_PD10_Pos) /*!< PORT2 PDR1: PD10 Mask */
\r
11615 #define PORT2_PDR1_PD11_Pos 12 /*!< PORT2 PDR1: PD11 Position */
\r
11616 #define PORT2_PDR1_PD11_Msk (0x07UL << PORT2_PDR1_PD11_Pos) /*!< PORT2 PDR1: PD11 Mask */
\r
11617 #define PORT2_PDR1_PD12_Pos 16 /*!< PORT2 PDR1: PD12 Position */
\r
11618 #define PORT2_PDR1_PD12_Msk (0x07UL << PORT2_PDR1_PD12_Pos) /*!< PORT2 PDR1: PD12 Mask */
\r
11619 #define PORT2_PDR1_PD13_Pos 20 /*!< PORT2 PDR1: PD13 Position */
\r
11620 #define PORT2_PDR1_PD13_Msk (0x07UL << PORT2_PDR1_PD13_Pos) /*!< PORT2 PDR1: PD13 Mask */
\r
11621 #define PORT2_PDR1_PD14_Pos 24 /*!< PORT2 PDR1: PD14 Position */
\r
11622 #define PORT2_PDR1_PD14_Msk (0x07UL << PORT2_PDR1_PD14_Pos) /*!< PORT2 PDR1: PD14 Mask */
\r
11623 #define PORT2_PDR1_PD15_Pos 28 /*!< PORT2 PDR1: PD15 Position */
\r
11624 #define PORT2_PDR1_PD15_Msk (0x07UL << PORT2_PDR1_PD15_Pos) /*!< PORT2 PDR1: PD15 Mask */
\r
11626 // --------------------------------------- PORT2_PDISC ------------------------------------------
\r
11627 #define PORT2_PDISC_PDIS0_Pos 0 /*!< PORT2 PDISC: PDIS0 Position */
\r
11628 #define PORT2_PDISC_PDIS0_Msk (0x01UL << PORT2_PDISC_PDIS0_Pos) /*!< PORT2 PDISC: PDIS0 Mask */
\r
11629 #define PORT2_PDISC_PDIS1_Pos 1 /*!< PORT2 PDISC: PDIS1 Position */
\r
11630 #define PORT2_PDISC_PDIS1_Msk (0x01UL << PORT2_PDISC_PDIS1_Pos) /*!< PORT2 PDISC: PDIS1 Mask */
\r
11631 #define PORT2_PDISC_PDIS2_Pos 2 /*!< PORT2 PDISC: PDIS2 Position */
\r
11632 #define PORT2_PDISC_PDIS2_Msk (0x01UL << PORT2_PDISC_PDIS2_Pos) /*!< PORT2 PDISC: PDIS2 Mask */
\r
11633 #define PORT2_PDISC_PDIS3_Pos 3 /*!< PORT2 PDISC: PDIS3 Position */
\r
11634 #define PORT2_PDISC_PDIS3_Msk (0x01UL << PORT2_PDISC_PDIS3_Pos) /*!< PORT2 PDISC: PDIS3 Mask */
\r
11635 #define PORT2_PDISC_PDIS4_Pos 4 /*!< PORT2 PDISC: PDIS4 Position */
\r
11636 #define PORT2_PDISC_PDIS4_Msk (0x01UL << PORT2_PDISC_PDIS4_Pos) /*!< PORT2 PDISC: PDIS4 Mask */
\r
11637 #define PORT2_PDISC_PDIS5_Pos 5 /*!< PORT2 PDISC: PDIS5 Position */
\r
11638 #define PORT2_PDISC_PDIS5_Msk (0x01UL << PORT2_PDISC_PDIS5_Pos) /*!< PORT2 PDISC: PDIS5 Mask */
\r
11639 #define PORT2_PDISC_PDIS6_Pos 6 /*!< PORT2 PDISC: PDIS6 Position */
\r
11640 #define PORT2_PDISC_PDIS6_Msk (0x01UL << PORT2_PDISC_PDIS6_Pos) /*!< PORT2 PDISC: PDIS6 Mask */
\r
11641 #define PORT2_PDISC_PDIS7_Pos 7 /*!< PORT2 PDISC: PDIS7 Position */
\r
11642 #define PORT2_PDISC_PDIS7_Msk (0x01UL << PORT2_PDISC_PDIS7_Pos) /*!< PORT2 PDISC: PDIS7 Mask */
\r
11643 #define PORT2_PDISC_PDIS8_Pos 8 /*!< PORT2 PDISC: PDIS8 Position */
\r
11644 #define PORT2_PDISC_PDIS8_Msk (0x01UL << PORT2_PDISC_PDIS8_Pos) /*!< PORT2 PDISC: PDIS8 Mask */
\r
11645 #define PORT2_PDISC_PDIS9_Pos 9 /*!< PORT2 PDISC: PDIS9 Position */
\r
11646 #define PORT2_PDISC_PDIS9_Msk (0x01UL << PORT2_PDISC_PDIS9_Pos) /*!< PORT2 PDISC: PDIS9 Mask */
\r
11647 #define PORT2_PDISC_PDIS10_Pos 10 /*!< PORT2 PDISC: PDIS10 Position */
\r
11648 #define PORT2_PDISC_PDIS10_Msk (0x01UL << PORT2_PDISC_PDIS10_Pos) /*!< PORT2 PDISC: PDIS10 Mask */
\r
11649 #define PORT2_PDISC_PDIS11_Pos 11 /*!< PORT2 PDISC: PDIS11 Position */
\r
11650 #define PORT2_PDISC_PDIS11_Msk (0x01UL << PORT2_PDISC_PDIS11_Pos) /*!< PORT2 PDISC: PDIS11 Mask */
\r
11651 #define PORT2_PDISC_PDIS12_Pos 12 /*!< PORT2 PDISC: PDIS12 Position */
\r
11652 #define PORT2_PDISC_PDIS12_Msk (0x01UL << PORT2_PDISC_PDIS12_Pos) /*!< PORT2 PDISC: PDIS12 Mask */
\r
11653 #define PORT2_PDISC_PDIS13_Pos 13 /*!< PORT2 PDISC: PDIS13 Position */
\r
11654 #define PORT2_PDISC_PDIS13_Msk (0x01UL << PORT2_PDISC_PDIS13_Pos) /*!< PORT2 PDISC: PDIS13 Mask */
\r
11655 #define PORT2_PDISC_PDIS14_Pos 14 /*!< PORT2 PDISC: PDIS14 Position */
\r
11656 #define PORT2_PDISC_PDIS14_Msk (0x01UL << PORT2_PDISC_PDIS14_Pos) /*!< PORT2 PDISC: PDIS14 Mask */
\r
11657 #define PORT2_PDISC_PDIS15_Pos 15 /*!< PORT2 PDISC: PDIS15 Position */
\r
11658 #define PORT2_PDISC_PDIS15_Msk (0x01UL << PORT2_PDISC_PDIS15_Pos) /*!< PORT2 PDISC: PDIS15 Mask */
\r
11660 // ---------------------------------------- PORT2_PPS -------------------------------------------
\r
11661 #define PORT2_PPS_PPS0_Pos 0 /*!< PORT2 PPS: PPS0 Position */
\r
11662 #define PORT2_PPS_PPS0_Msk (0x01UL << PORT2_PPS_PPS0_Pos) /*!< PORT2 PPS: PPS0 Mask */
\r
11663 #define PORT2_PPS_PPS1_Pos 1 /*!< PORT2 PPS: PPS1 Position */
\r
11664 #define PORT2_PPS_PPS1_Msk (0x01UL << PORT2_PPS_PPS1_Pos) /*!< PORT2 PPS: PPS1 Mask */
\r
11665 #define PORT2_PPS_PPS2_Pos 2 /*!< PORT2 PPS: PPS2 Position */
\r
11666 #define PORT2_PPS_PPS2_Msk (0x01UL << PORT2_PPS_PPS2_Pos) /*!< PORT2 PPS: PPS2 Mask */
\r
11667 #define PORT2_PPS_PPS3_Pos 3 /*!< PORT2 PPS: PPS3 Position */
\r
11668 #define PORT2_PPS_PPS3_Msk (0x01UL << PORT2_PPS_PPS3_Pos) /*!< PORT2 PPS: PPS3 Mask */
\r
11669 #define PORT2_PPS_PPS4_Pos 4 /*!< PORT2 PPS: PPS4 Position */
\r
11670 #define PORT2_PPS_PPS4_Msk (0x01UL << PORT2_PPS_PPS4_Pos) /*!< PORT2 PPS: PPS4 Mask */
\r
11671 #define PORT2_PPS_PPS5_Pos 5 /*!< PORT2 PPS: PPS5 Position */
\r
11672 #define PORT2_PPS_PPS5_Msk (0x01UL << PORT2_PPS_PPS5_Pos) /*!< PORT2 PPS: PPS5 Mask */
\r
11673 #define PORT2_PPS_PPS6_Pos 6 /*!< PORT2 PPS: PPS6 Position */
\r
11674 #define PORT2_PPS_PPS6_Msk (0x01UL << PORT2_PPS_PPS6_Pos) /*!< PORT2 PPS: PPS6 Mask */
\r
11675 #define PORT2_PPS_PPS7_Pos 7 /*!< PORT2 PPS: PPS7 Position */
\r
11676 #define PORT2_PPS_PPS7_Msk (0x01UL << PORT2_PPS_PPS7_Pos) /*!< PORT2 PPS: PPS7 Mask */
\r
11677 #define PORT2_PPS_PPS8_Pos 8 /*!< PORT2 PPS: PPS8 Position */
\r
11678 #define PORT2_PPS_PPS8_Msk (0x01UL << PORT2_PPS_PPS8_Pos) /*!< PORT2 PPS: PPS8 Mask */
\r
11679 #define PORT2_PPS_PPS9_Pos 9 /*!< PORT2 PPS: PPS9 Position */
\r
11680 #define PORT2_PPS_PPS9_Msk (0x01UL << PORT2_PPS_PPS9_Pos) /*!< PORT2 PPS: PPS9 Mask */
\r
11681 #define PORT2_PPS_PPS10_Pos 10 /*!< PORT2 PPS: PPS10 Position */
\r
11682 #define PORT2_PPS_PPS10_Msk (0x01UL << PORT2_PPS_PPS10_Pos) /*!< PORT2 PPS: PPS10 Mask */
\r
11683 #define PORT2_PPS_PPS11_Pos 11 /*!< PORT2 PPS: PPS11 Position */
\r
11684 #define PORT2_PPS_PPS11_Msk (0x01UL << PORT2_PPS_PPS11_Pos) /*!< PORT2 PPS: PPS11 Mask */
\r
11685 #define PORT2_PPS_PPS12_Pos 12 /*!< PORT2 PPS: PPS12 Position */
\r
11686 #define PORT2_PPS_PPS12_Msk (0x01UL << PORT2_PPS_PPS12_Pos) /*!< PORT2 PPS: PPS12 Mask */
\r
11687 #define PORT2_PPS_PPS13_Pos 13 /*!< PORT2 PPS: PPS13 Position */
\r
11688 #define PORT2_PPS_PPS13_Msk (0x01UL << PORT2_PPS_PPS13_Pos) /*!< PORT2 PPS: PPS13 Mask */
\r
11689 #define PORT2_PPS_PPS14_Pos 14 /*!< PORT2 PPS: PPS14 Position */
\r
11690 #define PORT2_PPS_PPS14_Msk (0x01UL << PORT2_PPS_PPS14_Pos) /*!< PORT2 PPS: PPS14 Mask */
\r
11691 #define PORT2_PPS_PPS15_Pos 15 /*!< PORT2 PPS: PPS15 Position */
\r
11692 #define PORT2_PPS_PPS15_Msk (0x01UL << PORT2_PPS_PPS15_Pos) /*!< PORT2 PPS: PPS15 Mask */
\r
11694 // --------------------------------------- PORT2_HWSEL ------------------------------------------
\r
11695 #define PORT2_HWSEL_HW0_Pos 0 /*!< PORT2 HWSEL: HW0 Position */
\r
11696 #define PORT2_HWSEL_HW0_Msk (0x03UL << PORT2_HWSEL_HW0_Pos) /*!< PORT2 HWSEL: HW0 Mask */
\r
11697 #define PORT2_HWSEL_HW1_Pos 2 /*!< PORT2 HWSEL: HW1 Position */
\r
11698 #define PORT2_HWSEL_HW1_Msk (0x03UL << PORT2_HWSEL_HW1_Pos) /*!< PORT2 HWSEL: HW1 Mask */
\r
11699 #define PORT2_HWSEL_HW2_Pos 4 /*!< PORT2 HWSEL: HW2 Position */
\r
11700 #define PORT2_HWSEL_HW2_Msk (0x03UL << PORT2_HWSEL_HW2_Pos) /*!< PORT2 HWSEL: HW2 Mask */
\r
11701 #define PORT2_HWSEL_HW3_Pos 6 /*!< PORT2 HWSEL: HW3 Position */
\r
11702 #define PORT2_HWSEL_HW3_Msk (0x03UL << PORT2_HWSEL_HW3_Pos) /*!< PORT2 HWSEL: HW3 Mask */
\r
11703 #define PORT2_HWSEL_HW4_Pos 8 /*!< PORT2 HWSEL: HW4 Position */
\r
11704 #define PORT2_HWSEL_HW4_Msk (0x03UL << PORT2_HWSEL_HW4_Pos) /*!< PORT2 HWSEL: HW4 Mask */
\r
11705 #define PORT2_HWSEL_HW5_Pos 10 /*!< PORT2 HWSEL: HW5 Position */
\r
11706 #define PORT2_HWSEL_HW5_Msk (0x03UL << PORT2_HWSEL_HW5_Pos) /*!< PORT2 HWSEL: HW5 Mask */
\r
11707 #define PORT2_HWSEL_HW6_Pos 12 /*!< PORT2 HWSEL: HW6 Position */
\r
11708 #define PORT2_HWSEL_HW6_Msk (0x03UL << PORT2_HWSEL_HW6_Pos) /*!< PORT2 HWSEL: HW6 Mask */
\r
11709 #define PORT2_HWSEL_HW7_Pos 14 /*!< PORT2 HWSEL: HW7 Position */
\r
11710 #define PORT2_HWSEL_HW7_Msk (0x03UL << PORT2_HWSEL_HW7_Pos) /*!< PORT2 HWSEL: HW7 Mask */
\r
11711 #define PORT2_HWSEL_HW8_Pos 16 /*!< PORT2 HWSEL: HW8 Position */
\r
11712 #define PORT2_HWSEL_HW8_Msk (0x03UL << PORT2_HWSEL_HW8_Pos) /*!< PORT2 HWSEL: HW8 Mask */
\r
11713 #define PORT2_HWSEL_HW9_Pos 18 /*!< PORT2 HWSEL: HW9 Position */
\r
11714 #define PORT2_HWSEL_HW9_Msk (0x03UL << PORT2_HWSEL_HW9_Pos) /*!< PORT2 HWSEL: HW9 Mask */
\r
11715 #define PORT2_HWSEL_HW10_Pos 20 /*!< PORT2 HWSEL: HW10 Position */
\r
11716 #define PORT2_HWSEL_HW10_Msk (0x03UL << PORT2_HWSEL_HW10_Pos) /*!< PORT2 HWSEL: HW10 Mask */
\r
11717 #define PORT2_HWSEL_HW11_Pos 22 /*!< PORT2 HWSEL: HW11 Position */
\r
11718 #define PORT2_HWSEL_HW11_Msk (0x03UL << PORT2_HWSEL_HW11_Pos) /*!< PORT2 HWSEL: HW11 Mask */
\r
11719 #define PORT2_HWSEL_HW12_Pos 24 /*!< PORT2 HWSEL: HW12 Position */
\r
11720 #define PORT2_HWSEL_HW12_Msk (0x03UL << PORT2_HWSEL_HW12_Pos) /*!< PORT2 HWSEL: HW12 Mask */
\r
11721 #define PORT2_HWSEL_HW13_Pos 26 /*!< PORT2 HWSEL: HW13 Position */
\r
11722 #define PORT2_HWSEL_HW13_Msk (0x03UL << PORT2_HWSEL_HW13_Pos) /*!< PORT2 HWSEL: HW13 Mask */
\r
11723 #define PORT2_HWSEL_HW14_Pos 28 /*!< PORT2 HWSEL: HW14 Position */
\r
11724 #define PORT2_HWSEL_HW14_Msk (0x03UL << PORT2_HWSEL_HW14_Pos) /*!< PORT2 HWSEL: HW14 Mask */
\r
11725 #define PORT2_HWSEL_HW15_Pos 30 /*!< PORT2 HWSEL: HW15 Position */
\r
11726 #define PORT2_HWSEL_HW15_Msk (0x03UL << PORT2_HWSEL_HW15_Pos) /*!< PORT2 HWSEL: HW15 Mask */
\r
11729 // ------------------------------------------------------------------------------------------------
\r
11730 // ----- PORT3 Position & Mask -----
\r
11731 // ------------------------------------------------------------------------------------------------
\r
11734 // ---------------------------------------- PORT3_OUT -------------------------------------------
\r
11735 #define PORT3_OUT_P0_Pos 0 /*!< PORT3 OUT: P0 Position */
\r
11736 #define PORT3_OUT_P0_Msk (0x01UL << PORT3_OUT_P0_Pos) /*!< PORT3 OUT: P0 Mask */
\r
11737 #define PORT3_OUT_P1_Pos 1 /*!< PORT3 OUT: P1 Position */
\r
11738 #define PORT3_OUT_P1_Msk (0x01UL << PORT3_OUT_P1_Pos) /*!< PORT3 OUT: P1 Mask */
\r
11739 #define PORT3_OUT_P2_Pos 2 /*!< PORT3 OUT: P2 Position */
\r
11740 #define PORT3_OUT_P2_Msk (0x01UL << PORT3_OUT_P2_Pos) /*!< PORT3 OUT: P2 Mask */
\r
11741 #define PORT3_OUT_P3_Pos 3 /*!< PORT3 OUT: P3 Position */
\r
11742 #define PORT3_OUT_P3_Msk (0x01UL << PORT3_OUT_P3_Pos) /*!< PORT3 OUT: P3 Mask */
\r
11743 #define PORT3_OUT_P4_Pos 4 /*!< PORT3 OUT: P4 Position */
\r
11744 #define PORT3_OUT_P4_Msk (0x01UL << PORT3_OUT_P4_Pos) /*!< PORT3 OUT: P4 Mask */
\r
11745 #define PORT3_OUT_P5_Pos 5 /*!< PORT3 OUT: P5 Position */
\r
11746 #define PORT3_OUT_P5_Msk (0x01UL << PORT3_OUT_P5_Pos) /*!< PORT3 OUT: P5 Mask */
\r
11747 #define PORT3_OUT_P6_Pos 6 /*!< PORT3 OUT: P6 Position */
\r
11748 #define PORT3_OUT_P6_Msk (0x01UL << PORT3_OUT_P6_Pos) /*!< PORT3 OUT: P6 Mask */
\r
11749 #define PORT3_OUT_P7_Pos 7 /*!< PORT3 OUT: P7 Position */
\r
11750 #define PORT3_OUT_P7_Msk (0x01UL << PORT3_OUT_P7_Pos) /*!< PORT3 OUT: P7 Mask */
\r
11751 #define PORT3_OUT_P8_Pos 8 /*!< PORT3 OUT: P8 Position */
\r
11752 #define PORT3_OUT_P8_Msk (0x01UL << PORT3_OUT_P8_Pos) /*!< PORT3 OUT: P8 Mask */
\r
11753 #define PORT3_OUT_P9_Pos 9 /*!< PORT3 OUT: P9 Position */
\r
11754 #define PORT3_OUT_P9_Msk (0x01UL << PORT3_OUT_P9_Pos) /*!< PORT3 OUT: P9 Mask */
\r
11755 #define PORT3_OUT_P10_Pos 10 /*!< PORT3 OUT: P10 Position */
\r
11756 #define PORT3_OUT_P10_Msk (0x01UL << PORT3_OUT_P10_Pos) /*!< PORT3 OUT: P10 Mask */
\r
11757 #define PORT3_OUT_P11_Pos 11 /*!< PORT3 OUT: P11 Position */
\r
11758 #define PORT3_OUT_P11_Msk (0x01UL << PORT3_OUT_P11_Pos) /*!< PORT3 OUT: P11 Mask */
\r
11759 #define PORT3_OUT_P12_Pos 12 /*!< PORT3 OUT: P12 Position */
\r
11760 #define PORT3_OUT_P12_Msk (0x01UL << PORT3_OUT_P12_Pos) /*!< PORT3 OUT: P12 Mask */
\r
11761 #define PORT3_OUT_P13_Pos 13 /*!< PORT3 OUT: P13 Position */
\r
11762 #define PORT3_OUT_P13_Msk (0x01UL << PORT3_OUT_P13_Pos) /*!< PORT3 OUT: P13 Mask */
\r
11763 #define PORT3_OUT_P14_Pos 14 /*!< PORT3 OUT: P14 Position */
\r
11764 #define PORT3_OUT_P14_Msk (0x01UL << PORT3_OUT_P14_Pos) /*!< PORT3 OUT: P14 Mask */
\r
11765 #define PORT3_OUT_P15_Pos 15 /*!< PORT3 OUT: P15 Position */
\r
11766 #define PORT3_OUT_P15_Msk (0x01UL << PORT3_OUT_P15_Pos) /*!< PORT3 OUT: P15 Mask */
\r
11768 // ---------------------------------------- PORT3_OMR -------------------------------------------
\r
11769 #define PORT3_OMR_PS0_Pos 0 /*!< PORT3 OMR: PS0 Position */
\r
11770 #define PORT3_OMR_PS0_Msk (0x01UL << PORT3_OMR_PS0_Pos) /*!< PORT3 OMR: PS0 Mask */
\r
11771 #define PORT3_OMR_PS1_Pos 1 /*!< PORT3 OMR: PS1 Position */
\r
11772 #define PORT3_OMR_PS1_Msk (0x01UL << PORT3_OMR_PS1_Pos) /*!< PORT3 OMR: PS1 Mask */
\r
11773 #define PORT3_OMR_PS2_Pos 2 /*!< PORT3 OMR: PS2 Position */
\r
11774 #define PORT3_OMR_PS2_Msk (0x01UL << PORT3_OMR_PS2_Pos) /*!< PORT3 OMR: PS2 Mask */
\r
11775 #define PORT3_OMR_PS3_Pos 3 /*!< PORT3 OMR: PS3 Position */
\r
11776 #define PORT3_OMR_PS3_Msk (0x01UL << PORT3_OMR_PS3_Pos) /*!< PORT3 OMR: PS3 Mask */
\r
11777 #define PORT3_OMR_PS4_Pos 4 /*!< PORT3 OMR: PS4 Position */
\r
11778 #define PORT3_OMR_PS4_Msk (0x01UL << PORT3_OMR_PS4_Pos) /*!< PORT3 OMR: PS4 Mask */
\r
11779 #define PORT3_OMR_PS5_Pos 5 /*!< PORT3 OMR: PS5 Position */
\r
11780 #define PORT3_OMR_PS5_Msk (0x01UL << PORT3_OMR_PS5_Pos) /*!< PORT3 OMR: PS5 Mask */
\r
11781 #define PORT3_OMR_PS6_Pos 6 /*!< PORT3 OMR: PS6 Position */
\r
11782 #define PORT3_OMR_PS6_Msk (0x01UL << PORT3_OMR_PS6_Pos) /*!< PORT3 OMR: PS6 Mask */
\r
11783 #define PORT3_OMR_PS7_Pos 7 /*!< PORT3 OMR: PS7 Position */
\r
11784 #define PORT3_OMR_PS7_Msk (0x01UL << PORT3_OMR_PS7_Pos) /*!< PORT3 OMR: PS7 Mask */
\r
11785 #define PORT3_OMR_PS8_Pos 8 /*!< PORT3 OMR: PS8 Position */
\r
11786 #define PORT3_OMR_PS8_Msk (0x01UL << PORT3_OMR_PS8_Pos) /*!< PORT3 OMR: PS8 Mask */
\r
11787 #define PORT3_OMR_PS9_Pos 9 /*!< PORT3 OMR: PS9 Position */
\r
11788 #define PORT3_OMR_PS9_Msk (0x01UL << PORT3_OMR_PS9_Pos) /*!< PORT3 OMR: PS9 Mask */
\r
11789 #define PORT3_OMR_PS10_Pos 10 /*!< PORT3 OMR: PS10 Position */
\r
11790 #define PORT3_OMR_PS10_Msk (0x01UL << PORT3_OMR_PS10_Pos) /*!< PORT3 OMR: PS10 Mask */
\r
11791 #define PORT3_OMR_PS11_Pos 11 /*!< PORT3 OMR: PS11 Position */
\r
11792 #define PORT3_OMR_PS11_Msk (0x01UL << PORT3_OMR_PS11_Pos) /*!< PORT3 OMR: PS11 Mask */
\r
11793 #define PORT3_OMR_PS12_Pos 12 /*!< PORT3 OMR: PS12 Position */
\r
11794 #define PORT3_OMR_PS12_Msk (0x01UL << PORT3_OMR_PS12_Pos) /*!< PORT3 OMR: PS12 Mask */
\r
11795 #define PORT3_OMR_PS13_Pos 13 /*!< PORT3 OMR: PS13 Position */
\r
11796 #define PORT3_OMR_PS13_Msk (0x01UL << PORT3_OMR_PS13_Pos) /*!< PORT3 OMR: PS13 Mask */
\r
11797 #define PORT3_OMR_PS14_Pos 14 /*!< PORT3 OMR: PS14 Position */
\r
11798 #define PORT3_OMR_PS14_Msk (0x01UL << PORT3_OMR_PS14_Pos) /*!< PORT3 OMR: PS14 Mask */
\r
11799 #define PORT3_OMR_PS15_Pos 15 /*!< PORT3 OMR: PS15 Position */
\r
11800 #define PORT3_OMR_PS15_Msk (0x01UL << PORT3_OMR_PS15_Pos) /*!< PORT3 OMR: PS15 Mask */
\r
11801 #define PORT3_OMR_PR0_Pos 16 /*!< PORT3 OMR: PR0 Position */
\r
11802 #define PORT3_OMR_PR0_Msk (0x01UL << PORT3_OMR_PR0_Pos) /*!< PORT3 OMR: PR0 Mask */
\r
11803 #define PORT3_OMR_PR1_Pos 17 /*!< PORT3 OMR: PR1 Position */
\r
11804 #define PORT3_OMR_PR1_Msk (0x01UL << PORT3_OMR_PR1_Pos) /*!< PORT3 OMR: PR1 Mask */
\r
11805 #define PORT3_OMR_PR2_Pos 18 /*!< PORT3 OMR: PR2 Position */
\r
11806 #define PORT3_OMR_PR2_Msk (0x01UL << PORT3_OMR_PR2_Pos) /*!< PORT3 OMR: PR2 Mask */
\r
11807 #define PORT3_OMR_PR3_Pos 19 /*!< PORT3 OMR: PR3 Position */
\r
11808 #define PORT3_OMR_PR3_Msk (0x01UL << PORT3_OMR_PR3_Pos) /*!< PORT3 OMR: PR3 Mask */
\r
11809 #define PORT3_OMR_PR4_Pos 20 /*!< PORT3 OMR: PR4 Position */
\r
11810 #define PORT3_OMR_PR4_Msk (0x01UL << PORT3_OMR_PR4_Pos) /*!< PORT3 OMR: PR4 Mask */
\r
11811 #define PORT3_OMR_PR5_Pos 21 /*!< PORT3 OMR: PR5 Position */
\r
11812 #define PORT3_OMR_PR5_Msk (0x01UL << PORT3_OMR_PR5_Pos) /*!< PORT3 OMR: PR5 Mask */
\r
11813 #define PORT3_OMR_PR6_Pos 22 /*!< PORT3 OMR: PR6 Position */
\r
11814 #define PORT3_OMR_PR6_Msk (0x01UL << PORT3_OMR_PR6_Pos) /*!< PORT3 OMR: PR6 Mask */
\r
11815 #define PORT3_OMR_PR7_Pos 23 /*!< PORT3 OMR: PR7 Position */
\r
11816 #define PORT3_OMR_PR7_Msk (0x01UL << PORT3_OMR_PR7_Pos) /*!< PORT3 OMR: PR7 Mask */
\r
11817 #define PORT3_OMR_PR8_Pos 24 /*!< PORT3 OMR: PR8 Position */
\r
11818 #define PORT3_OMR_PR8_Msk (0x01UL << PORT3_OMR_PR8_Pos) /*!< PORT3 OMR: PR8 Mask */
\r
11819 #define PORT3_OMR_PR9_Pos 25 /*!< PORT3 OMR: PR9 Position */
\r
11820 #define PORT3_OMR_PR9_Msk (0x01UL << PORT3_OMR_PR9_Pos) /*!< PORT3 OMR: PR9 Mask */
\r
11821 #define PORT3_OMR_PR10_Pos 26 /*!< PORT3 OMR: PR10 Position */
\r
11822 #define PORT3_OMR_PR10_Msk (0x01UL << PORT3_OMR_PR10_Pos) /*!< PORT3 OMR: PR10 Mask */
\r
11823 #define PORT3_OMR_PR11_Pos 27 /*!< PORT3 OMR: PR11 Position */
\r
11824 #define PORT3_OMR_PR11_Msk (0x01UL << PORT3_OMR_PR11_Pos) /*!< PORT3 OMR: PR11 Mask */
\r
11825 #define PORT3_OMR_PR12_Pos 28 /*!< PORT3 OMR: PR12 Position */
\r
11826 #define PORT3_OMR_PR12_Msk (0x01UL << PORT3_OMR_PR12_Pos) /*!< PORT3 OMR: PR12 Mask */
\r
11827 #define PORT3_OMR_PR13_Pos 29 /*!< PORT3 OMR: PR13 Position */
\r
11828 #define PORT3_OMR_PR13_Msk (0x01UL << PORT3_OMR_PR13_Pos) /*!< PORT3 OMR: PR13 Mask */
\r
11829 #define PORT3_OMR_PR14_Pos 30 /*!< PORT3 OMR: PR14 Position */
\r
11830 #define PORT3_OMR_PR14_Msk (0x01UL << PORT3_OMR_PR14_Pos) /*!< PORT3 OMR: PR14 Mask */
\r
11831 #define PORT3_OMR_PR15_Pos 31 /*!< PORT3 OMR: PR15 Position */
\r
11832 #define PORT3_OMR_PR15_Msk (0x01UL << PORT3_OMR_PR15_Pos) /*!< PORT3 OMR: PR15 Mask */
\r
11834 // --------------------------------------- PORT3_IOCR0 ------------------------------------------
\r
11835 #define PORT3_IOCR0_PC0_Pos 3 /*!< PORT3 IOCR0: PC0 Position */
\r
11836 #define PORT3_IOCR0_PC0_Msk (0x1fUL << PORT3_IOCR0_PC0_Pos) /*!< PORT3 IOCR0: PC0 Mask */
\r
11837 #define PORT3_IOCR0_PC1_Pos 11 /*!< PORT3 IOCR0: PC1 Position */
\r
11838 #define PORT3_IOCR0_PC1_Msk (0x1fUL << PORT3_IOCR0_PC1_Pos) /*!< PORT3 IOCR0: PC1 Mask */
\r
11839 #define PORT3_IOCR0_PC2_Pos 19 /*!< PORT3 IOCR0: PC2 Position */
\r
11840 #define PORT3_IOCR0_PC2_Msk (0x1fUL << PORT3_IOCR0_PC2_Pos) /*!< PORT3 IOCR0: PC2 Mask */
\r
11841 #define PORT3_IOCR0_PC3_Pos 27 /*!< PORT3 IOCR0: PC3 Position */
\r
11842 #define PORT3_IOCR0_PC3_Msk (0x1fUL << PORT3_IOCR0_PC3_Pos) /*!< PORT3 IOCR0: PC3 Mask */
\r
11844 // --------------------------------------- PORT3_IOCR4 ------------------------------------------
\r
11845 #define PORT3_IOCR4_PC4_Pos 3 /*!< PORT3 IOCR4: PC4 Position */
\r
11846 #define PORT3_IOCR4_PC4_Msk (0x1fUL << PORT3_IOCR4_PC4_Pos) /*!< PORT3 IOCR4: PC4 Mask */
\r
11847 #define PORT3_IOCR4_PC5_Pos 11 /*!< PORT3 IOCR4: PC5 Position */
\r
11848 #define PORT3_IOCR4_PC5_Msk (0x1fUL << PORT3_IOCR4_PC5_Pos) /*!< PORT3 IOCR4: PC5 Mask */
\r
11849 #define PORT3_IOCR4_PC6_Pos 19 /*!< PORT3 IOCR4: PC6 Position */
\r
11850 #define PORT3_IOCR4_PC6_Msk (0x1fUL << PORT3_IOCR4_PC6_Pos) /*!< PORT3 IOCR4: PC6 Mask */
\r
11851 #define PORT3_IOCR4_PC7_Pos 27 /*!< PORT3 IOCR4: PC7 Position */
\r
11852 #define PORT3_IOCR4_PC7_Msk (0x1fUL << PORT3_IOCR4_PC7_Pos) /*!< PORT3 IOCR4: PC7 Mask */
\r
11854 // --------------------------------------- PORT3_IOCR8 ------------------------------------------
\r
11855 #define PORT3_IOCR8_PC8_Pos 3 /*!< PORT3 IOCR8: PC8 Position */
\r
11856 #define PORT3_IOCR8_PC8_Msk (0x1fUL << PORT3_IOCR8_PC8_Pos) /*!< PORT3 IOCR8: PC8 Mask */
\r
11857 #define PORT3_IOCR8_PC9_Pos 11 /*!< PORT3 IOCR8: PC9 Position */
\r
11858 #define PORT3_IOCR8_PC9_Msk (0x1fUL << PORT3_IOCR8_PC9_Pos) /*!< PORT3 IOCR8: PC9 Mask */
\r
11859 #define PORT3_IOCR8_PC10_Pos 19 /*!< PORT3 IOCR8: PC10 Position */
\r
11860 #define PORT3_IOCR8_PC10_Msk (0x1fUL << PORT3_IOCR8_PC10_Pos) /*!< PORT3 IOCR8: PC10 Mask */
\r
11861 #define PORT3_IOCR8_PC11_Pos 27 /*!< PORT3 IOCR8: PC11 Position */
\r
11862 #define PORT3_IOCR8_PC11_Msk (0x1fUL << PORT3_IOCR8_PC11_Pos) /*!< PORT3 IOCR8: PC11 Mask */
\r
11864 // -------------------------------------- PORT3_IOCR12 ------------------------------------------
\r
11865 #define PORT3_IOCR12_PC12_Pos 3 /*!< PORT3 IOCR12: PC12 Position */
\r
11866 #define PORT3_IOCR12_PC12_Msk (0x1fUL << PORT3_IOCR12_PC12_Pos) /*!< PORT3 IOCR12: PC12 Mask */
\r
11867 #define PORT3_IOCR12_PC13_Pos 11 /*!< PORT3 IOCR12: PC13 Position */
\r
11868 #define PORT3_IOCR12_PC13_Msk (0x1fUL << PORT3_IOCR12_PC13_Pos) /*!< PORT3 IOCR12: PC13 Mask */
\r
11869 #define PORT3_IOCR12_PC14_Pos 19 /*!< PORT3 IOCR12: PC14 Position */
\r
11870 #define PORT3_IOCR12_PC14_Msk (0x1fUL << PORT3_IOCR12_PC14_Pos) /*!< PORT3 IOCR12: PC14 Mask */
\r
11871 #define PORT3_IOCR12_PC15_Pos 27 /*!< PORT3 IOCR12: PC15 Position */
\r
11872 #define PORT3_IOCR12_PC15_Msk (0x1fUL << PORT3_IOCR12_PC15_Pos) /*!< PORT3 IOCR12: PC15 Mask */
\r
11874 // ---------------------------------------- PORT3_IN --------------------------------------------
\r
11875 #define PORT3_IN_P0_Pos 0 /*!< PORT3 IN: P0 Position */
\r
11876 #define PORT3_IN_P0_Msk (0x01UL << PORT3_IN_P0_Pos) /*!< PORT3 IN: P0 Mask */
\r
11877 #define PORT3_IN_P1_Pos 1 /*!< PORT3 IN: P1 Position */
\r
11878 #define PORT3_IN_P1_Msk (0x01UL << PORT3_IN_P1_Pos) /*!< PORT3 IN: P1 Mask */
\r
11879 #define PORT3_IN_P2_Pos 2 /*!< PORT3 IN: P2 Position */
\r
11880 #define PORT3_IN_P2_Msk (0x01UL << PORT3_IN_P2_Pos) /*!< PORT3 IN: P2 Mask */
\r
11881 #define PORT3_IN_P3_Pos 3 /*!< PORT3 IN: P3 Position */
\r
11882 #define PORT3_IN_P3_Msk (0x01UL << PORT3_IN_P3_Pos) /*!< PORT3 IN: P3 Mask */
\r
11883 #define PORT3_IN_P4_Pos 4 /*!< PORT3 IN: P4 Position */
\r
11884 #define PORT3_IN_P4_Msk (0x01UL << PORT3_IN_P4_Pos) /*!< PORT3 IN: P4 Mask */
\r
11885 #define PORT3_IN_P5_Pos 5 /*!< PORT3 IN: P5 Position */
\r
11886 #define PORT3_IN_P5_Msk (0x01UL << PORT3_IN_P5_Pos) /*!< PORT3 IN: P5 Mask */
\r
11887 #define PORT3_IN_P6_Pos 6 /*!< PORT3 IN: P6 Position */
\r
11888 #define PORT3_IN_P6_Msk (0x01UL << PORT3_IN_P6_Pos) /*!< PORT3 IN: P6 Mask */
\r
11889 #define PORT3_IN_P7_Pos 7 /*!< PORT3 IN: P7 Position */
\r
11890 #define PORT3_IN_P7_Msk (0x01UL << PORT3_IN_P7_Pos) /*!< PORT3 IN: P7 Mask */
\r
11891 #define PORT3_IN_P8_Pos 8 /*!< PORT3 IN: P8 Position */
\r
11892 #define PORT3_IN_P8_Msk (0x01UL << PORT3_IN_P8_Pos) /*!< PORT3 IN: P8 Mask */
\r
11893 #define PORT3_IN_P9_Pos 9 /*!< PORT3 IN: P9 Position */
\r
11894 #define PORT3_IN_P9_Msk (0x01UL << PORT3_IN_P9_Pos) /*!< PORT3 IN: P9 Mask */
\r
11895 #define PORT3_IN_P10_Pos 10 /*!< PORT3 IN: P10 Position */
\r
11896 #define PORT3_IN_P10_Msk (0x01UL << PORT3_IN_P10_Pos) /*!< PORT3 IN: P10 Mask */
\r
11897 #define PORT3_IN_P11_Pos 11 /*!< PORT3 IN: P11 Position */
\r
11898 #define PORT3_IN_P11_Msk (0x01UL << PORT3_IN_P11_Pos) /*!< PORT3 IN: P11 Mask */
\r
11899 #define PORT3_IN_P12_Pos 12 /*!< PORT3 IN: P12 Position */
\r
11900 #define PORT3_IN_P12_Msk (0x01UL << PORT3_IN_P12_Pos) /*!< PORT3 IN: P12 Mask */
\r
11901 #define PORT3_IN_P13_Pos 13 /*!< PORT3 IN: P13 Position */
\r
11902 #define PORT3_IN_P13_Msk (0x01UL << PORT3_IN_P13_Pos) /*!< PORT3 IN: P13 Mask */
\r
11903 #define PORT3_IN_P14_Pos 14 /*!< PORT3 IN: P14 Position */
\r
11904 #define PORT3_IN_P14_Msk (0x01UL << PORT3_IN_P14_Pos) /*!< PORT3 IN: P14 Mask */
\r
11905 #define PORT3_IN_P15_Pos 15 /*!< PORT3 IN: P15 Position */
\r
11906 #define PORT3_IN_P15_Msk (0x01UL << PORT3_IN_P15_Pos) /*!< PORT3 IN: P15 Mask */
\r
11908 // --------------------------------------- PORT3_PDR0 -------------------------------------------
\r
11909 #define PORT3_PDR0_PD0_Pos 0 /*!< PORT3 PDR0: PD0 Position */
\r
11910 #define PORT3_PDR0_PD0_Msk (0x07UL << PORT3_PDR0_PD0_Pos) /*!< PORT3 PDR0: PD0 Mask */
\r
11911 #define PORT3_PDR0_PD1_Pos 4 /*!< PORT3 PDR0: PD1 Position */
\r
11912 #define PORT3_PDR0_PD1_Msk (0x07UL << PORT3_PDR0_PD1_Pos) /*!< PORT3 PDR0: PD1 Mask */
\r
11913 #define PORT3_PDR0_PD2_Pos 8 /*!< PORT3 PDR0: PD2 Position */
\r
11914 #define PORT3_PDR0_PD2_Msk (0x07UL << PORT3_PDR0_PD2_Pos) /*!< PORT3 PDR0: PD2 Mask */
\r
11915 #define PORT3_PDR0_PD3_Pos 12 /*!< PORT3 PDR0: PD3 Position */
\r
11916 #define PORT3_PDR0_PD3_Msk (0x07UL << PORT3_PDR0_PD3_Pos) /*!< PORT3 PDR0: PD3 Mask */
\r
11917 #define PORT3_PDR0_PD4_Pos 16 /*!< PORT3 PDR0: PD4 Position */
\r
11918 #define PORT3_PDR0_PD4_Msk (0x07UL << PORT3_PDR0_PD4_Pos) /*!< PORT3 PDR0: PD4 Mask */
\r
11919 #define PORT3_PDR0_PD5_Pos 20 /*!< PORT3 PDR0: PD5 Position */
\r
11920 #define PORT3_PDR0_PD5_Msk (0x07UL << PORT3_PDR0_PD5_Pos) /*!< PORT3 PDR0: PD5 Mask */
\r
11921 #define PORT3_PDR0_PD6_Pos 24 /*!< PORT3 PDR0: PD6 Position */
\r
11922 #define PORT3_PDR0_PD6_Msk (0x07UL << PORT3_PDR0_PD6_Pos) /*!< PORT3 PDR0: PD6 Mask */
\r
11923 #define PORT3_PDR0_PD7_Pos 28 /*!< PORT3 PDR0: PD7 Position */
\r
11924 #define PORT3_PDR0_PD7_Msk (0x07UL << PORT3_PDR0_PD7_Pos) /*!< PORT3 PDR0: PD7 Mask */
\r
11926 // --------------------------------------- PORT3_PDR1 -------------------------------------------
\r
11927 #define PORT3_PDR1_PD8_Pos 0 /*!< PORT3 PDR1: PD8 Position */
\r
11928 #define PORT3_PDR1_PD8_Msk (0x07UL << PORT3_PDR1_PD8_Pos) /*!< PORT3 PDR1: PD8 Mask */
\r
11929 #define PORT3_PDR1_PD9_Pos 4 /*!< PORT3 PDR1: PD9 Position */
\r
11930 #define PORT3_PDR1_PD9_Msk (0x07UL << PORT3_PDR1_PD9_Pos) /*!< PORT3 PDR1: PD9 Mask */
\r
11931 #define PORT3_PDR1_PD10_Pos 8 /*!< PORT3 PDR1: PD10 Position */
\r
11932 #define PORT3_PDR1_PD10_Msk (0x07UL << PORT3_PDR1_PD10_Pos) /*!< PORT3 PDR1: PD10 Mask */
\r
11933 #define PORT3_PDR1_PD11_Pos 12 /*!< PORT3 PDR1: PD11 Position */
\r
11934 #define PORT3_PDR1_PD11_Msk (0x07UL << PORT3_PDR1_PD11_Pos) /*!< PORT3 PDR1: PD11 Mask */
\r
11935 #define PORT3_PDR1_PD12_Pos 16 /*!< PORT3 PDR1: PD12 Position */
\r
11936 #define PORT3_PDR1_PD12_Msk (0x07UL << PORT3_PDR1_PD12_Pos) /*!< PORT3 PDR1: PD12 Mask */
\r
11937 #define PORT3_PDR1_PD13_Pos 20 /*!< PORT3 PDR1: PD13 Position */
\r
11938 #define PORT3_PDR1_PD13_Msk (0x07UL << PORT3_PDR1_PD13_Pos) /*!< PORT3 PDR1: PD13 Mask */
\r
11939 #define PORT3_PDR1_PD14_Pos 24 /*!< PORT3 PDR1: PD14 Position */
\r
11940 #define PORT3_PDR1_PD14_Msk (0x07UL << PORT3_PDR1_PD14_Pos) /*!< PORT3 PDR1: PD14 Mask */
\r
11941 #define PORT3_PDR1_PD15_Pos 28 /*!< PORT3 PDR1: PD15 Position */
\r
11942 #define PORT3_PDR1_PD15_Msk (0x07UL << PORT3_PDR1_PD15_Pos) /*!< PORT3 PDR1: PD15 Mask */
\r
11944 // --------------------------------------- PORT3_PDISC ------------------------------------------
\r
11945 #define PORT3_PDISC_PDIS0_Pos 0 /*!< PORT3 PDISC: PDIS0 Position */
\r
11946 #define PORT3_PDISC_PDIS0_Msk (0x01UL << PORT3_PDISC_PDIS0_Pos) /*!< PORT3 PDISC: PDIS0 Mask */
\r
11947 #define PORT3_PDISC_PDIS1_Pos 1 /*!< PORT3 PDISC: PDIS1 Position */
\r
11948 #define PORT3_PDISC_PDIS1_Msk (0x01UL << PORT3_PDISC_PDIS1_Pos) /*!< PORT3 PDISC: PDIS1 Mask */
\r
11949 #define PORT3_PDISC_PDIS2_Pos 2 /*!< PORT3 PDISC: PDIS2 Position */
\r
11950 #define PORT3_PDISC_PDIS2_Msk (0x01UL << PORT3_PDISC_PDIS2_Pos) /*!< PORT3 PDISC: PDIS2 Mask */
\r
11951 #define PORT3_PDISC_PDIS3_Pos 3 /*!< PORT3 PDISC: PDIS3 Position */
\r
11952 #define PORT3_PDISC_PDIS3_Msk (0x01UL << PORT3_PDISC_PDIS3_Pos) /*!< PORT3 PDISC: PDIS3 Mask */
\r
11953 #define PORT3_PDISC_PDIS4_Pos 4 /*!< PORT3 PDISC: PDIS4 Position */
\r
11954 #define PORT3_PDISC_PDIS4_Msk (0x01UL << PORT3_PDISC_PDIS4_Pos) /*!< PORT3 PDISC: PDIS4 Mask */
\r
11955 #define PORT3_PDISC_PDIS5_Pos 5 /*!< PORT3 PDISC: PDIS5 Position */
\r
11956 #define PORT3_PDISC_PDIS5_Msk (0x01UL << PORT3_PDISC_PDIS5_Pos) /*!< PORT3 PDISC: PDIS5 Mask */
\r
11957 #define PORT3_PDISC_PDIS6_Pos 6 /*!< PORT3 PDISC: PDIS6 Position */
\r
11958 #define PORT3_PDISC_PDIS6_Msk (0x01UL << PORT3_PDISC_PDIS6_Pos) /*!< PORT3 PDISC: PDIS6 Mask */
\r
11959 #define PORT3_PDISC_PDIS7_Pos 7 /*!< PORT3 PDISC: PDIS7 Position */
\r
11960 #define PORT3_PDISC_PDIS7_Msk (0x01UL << PORT3_PDISC_PDIS7_Pos) /*!< PORT3 PDISC: PDIS7 Mask */
\r
11961 #define PORT3_PDISC_PDIS8_Pos 8 /*!< PORT3 PDISC: PDIS8 Position */
\r
11962 #define PORT3_PDISC_PDIS8_Msk (0x01UL << PORT3_PDISC_PDIS8_Pos) /*!< PORT3 PDISC: PDIS8 Mask */
\r
11963 #define PORT3_PDISC_PDIS9_Pos 9 /*!< PORT3 PDISC: PDIS9 Position */
\r
11964 #define PORT3_PDISC_PDIS9_Msk (0x01UL << PORT3_PDISC_PDIS9_Pos) /*!< PORT3 PDISC: PDIS9 Mask */
\r
11965 #define PORT3_PDISC_PDIS10_Pos 10 /*!< PORT3 PDISC: PDIS10 Position */
\r
11966 #define PORT3_PDISC_PDIS10_Msk (0x01UL << PORT3_PDISC_PDIS10_Pos) /*!< PORT3 PDISC: PDIS10 Mask */
\r
11967 #define PORT3_PDISC_PDIS11_Pos 11 /*!< PORT3 PDISC: PDIS11 Position */
\r
11968 #define PORT3_PDISC_PDIS11_Msk (0x01UL << PORT3_PDISC_PDIS11_Pos) /*!< PORT3 PDISC: PDIS11 Mask */
\r
11969 #define PORT3_PDISC_PDIS12_Pos 12 /*!< PORT3 PDISC: PDIS12 Position */
\r
11970 #define PORT3_PDISC_PDIS12_Msk (0x01UL << PORT3_PDISC_PDIS12_Pos) /*!< PORT3 PDISC: PDIS12 Mask */
\r
11971 #define PORT3_PDISC_PDIS13_Pos 13 /*!< PORT3 PDISC: PDIS13 Position */
\r
11972 #define PORT3_PDISC_PDIS13_Msk (0x01UL << PORT3_PDISC_PDIS13_Pos) /*!< PORT3 PDISC: PDIS13 Mask */
\r
11973 #define PORT3_PDISC_PDIS14_Pos 14 /*!< PORT3 PDISC: PDIS14 Position */
\r
11974 #define PORT3_PDISC_PDIS14_Msk (0x01UL << PORT3_PDISC_PDIS14_Pos) /*!< PORT3 PDISC: PDIS14 Mask */
\r
11975 #define PORT3_PDISC_PDIS15_Pos 15 /*!< PORT3 PDISC: PDIS15 Position */
\r
11976 #define PORT3_PDISC_PDIS15_Msk (0x01UL << PORT3_PDISC_PDIS15_Pos) /*!< PORT3 PDISC: PDIS15 Mask */
\r
11978 // ---------------------------------------- PORT3_PPS -------------------------------------------
\r
11979 #define PORT3_PPS_PPS0_Pos 0 /*!< PORT3 PPS: PPS0 Position */
\r
11980 #define PORT3_PPS_PPS0_Msk (0x01UL << PORT3_PPS_PPS0_Pos) /*!< PORT3 PPS: PPS0 Mask */
\r
11981 #define PORT3_PPS_PPS1_Pos 1 /*!< PORT3 PPS: PPS1 Position */
\r
11982 #define PORT3_PPS_PPS1_Msk (0x01UL << PORT3_PPS_PPS1_Pos) /*!< PORT3 PPS: PPS1 Mask */
\r
11983 #define PORT3_PPS_PPS2_Pos 2 /*!< PORT3 PPS: PPS2 Position */
\r
11984 #define PORT3_PPS_PPS2_Msk (0x01UL << PORT3_PPS_PPS2_Pos) /*!< PORT3 PPS: PPS2 Mask */
\r
11985 #define PORT3_PPS_PPS3_Pos 3 /*!< PORT3 PPS: PPS3 Position */
\r
11986 #define PORT3_PPS_PPS3_Msk (0x01UL << PORT3_PPS_PPS3_Pos) /*!< PORT3 PPS: PPS3 Mask */
\r
11987 #define PORT3_PPS_PPS4_Pos 4 /*!< PORT3 PPS: PPS4 Position */
\r
11988 #define PORT3_PPS_PPS4_Msk (0x01UL << PORT3_PPS_PPS4_Pos) /*!< PORT3 PPS: PPS4 Mask */
\r
11989 #define PORT3_PPS_PPS5_Pos 5 /*!< PORT3 PPS: PPS5 Position */
\r
11990 #define PORT3_PPS_PPS5_Msk (0x01UL << PORT3_PPS_PPS5_Pos) /*!< PORT3 PPS: PPS5 Mask */
\r
11991 #define PORT3_PPS_PPS6_Pos 6 /*!< PORT3 PPS: PPS6 Position */
\r
11992 #define PORT3_PPS_PPS6_Msk (0x01UL << PORT3_PPS_PPS6_Pos) /*!< PORT3 PPS: PPS6 Mask */
\r
11993 #define PORT3_PPS_PPS7_Pos 7 /*!< PORT3 PPS: PPS7 Position */
\r
11994 #define PORT3_PPS_PPS7_Msk (0x01UL << PORT3_PPS_PPS7_Pos) /*!< PORT3 PPS: PPS7 Mask */
\r
11995 #define PORT3_PPS_PPS8_Pos 8 /*!< PORT3 PPS: PPS8 Position */
\r
11996 #define PORT3_PPS_PPS8_Msk (0x01UL << PORT3_PPS_PPS8_Pos) /*!< PORT3 PPS: PPS8 Mask */
\r
11997 #define PORT3_PPS_PPS9_Pos 9 /*!< PORT3 PPS: PPS9 Position */
\r
11998 #define PORT3_PPS_PPS9_Msk (0x01UL << PORT3_PPS_PPS9_Pos) /*!< PORT3 PPS: PPS9 Mask */
\r
11999 #define PORT3_PPS_PPS10_Pos 10 /*!< PORT3 PPS: PPS10 Position */
\r
12000 #define PORT3_PPS_PPS10_Msk (0x01UL << PORT3_PPS_PPS10_Pos) /*!< PORT3 PPS: PPS10 Mask */
\r
12001 #define PORT3_PPS_PPS11_Pos 11 /*!< PORT3 PPS: PPS11 Position */
\r
12002 #define PORT3_PPS_PPS11_Msk (0x01UL << PORT3_PPS_PPS11_Pos) /*!< PORT3 PPS: PPS11 Mask */
\r
12003 #define PORT3_PPS_PPS12_Pos 12 /*!< PORT3 PPS: PPS12 Position */
\r
12004 #define PORT3_PPS_PPS12_Msk (0x01UL << PORT3_PPS_PPS12_Pos) /*!< PORT3 PPS: PPS12 Mask */
\r
12005 #define PORT3_PPS_PPS13_Pos 13 /*!< PORT3 PPS: PPS13 Position */
\r
12006 #define PORT3_PPS_PPS13_Msk (0x01UL << PORT3_PPS_PPS13_Pos) /*!< PORT3 PPS: PPS13 Mask */
\r
12007 #define PORT3_PPS_PPS14_Pos 14 /*!< PORT3 PPS: PPS14 Position */
\r
12008 #define PORT3_PPS_PPS14_Msk (0x01UL << PORT3_PPS_PPS14_Pos) /*!< PORT3 PPS: PPS14 Mask */
\r
12009 #define PORT3_PPS_PPS15_Pos 15 /*!< PORT3 PPS: PPS15 Position */
\r
12010 #define PORT3_PPS_PPS15_Msk (0x01UL << PORT3_PPS_PPS15_Pos) /*!< PORT3 PPS: PPS15 Mask */
\r
12012 // --------------------------------------- PORT3_HWSEL ------------------------------------------
\r
12013 #define PORT3_HWSEL_HW0_Pos 0 /*!< PORT3 HWSEL: HW0 Position */
\r
12014 #define PORT3_HWSEL_HW0_Msk (0x03UL << PORT3_HWSEL_HW0_Pos) /*!< PORT3 HWSEL: HW0 Mask */
\r
12015 #define PORT3_HWSEL_HW1_Pos 2 /*!< PORT3 HWSEL: HW1 Position */
\r
12016 #define PORT3_HWSEL_HW1_Msk (0x03UL << PORT3_HWSEL_HW1_Pos) /*!< PORT3 HWSEL: HW1 Mask */
\r
12017 #define PORT3_HWSEL_HW2_Pos 4 /*!< PORT3 HWSEL: HW2 Position */
\r
12018 #define PORT3_HWSEL_HW2_Msk (0x03UL << PORT3_HWSEL_HW2_Pos) /*!< PORT3 HWSEL: HW2 Mask */
\r
12019 #define PORT3_HWSEL_HW3_Pos 6 /*!< PORT3 HWSEL: HW3 Position */
\r
12020 #define PORT3_HWSEL_HW3_Msk (0x03UL << PORT3_HWSEL_HW3_Pos) /*!< PORT3 HWSEL: HW3 Mask */
\r
12021 #define PORT3_HWSEL_HW4_Pos 8 /*!< PORT3 HWSEL: HW4 Position */
\r
12022 #define PORT3_HWSEL_HW4_Msk (0x03UL << PORT3_HWSEL_HW4_Pos) /*!< PORT3 HWSEL: HW4 Mask */
\r
12023 #define PORT3_HWSEL_HW5_Pos 10 /*!< PORT3 HWSEL: HW5 Position */
\r
12024 #define PORT3_HWSEL_HW5_Msk (0x03UL << PORT3_HWSEL_HW5_Pos) /*!< PORT3 HWSEL: HW5 Mask */
\r
12025 #define PORT3_HWSEL_HW6_Pos 12 /*!< PORT3 HWSEL: HW6 Position */
\r
12026 #define PORT3_HWSEL_HW6_Msk (0x03UL << PORT3_HWSEL_HW6_Pos) /*!< PORT3 HWSEL: HW6 Mask */
\r
12027 #define PORT3_HWSEL_HW7_Pos 14 /*!< PORT3 HWSEL: HW7 Position */
\r
12028 #define PORT3_HWSEL_HW7_Msk (0x03UL << PORT3_HWSEL_HW7_Pos) /*!< PORT3 HWSEL: HW7 Mask */
\r
12029 #define PORT3_HWSEL_HW8_Pos 16 /*!< PORT3 HWSEL: HW8 Position */
\r
12030 #define PORT3_HWSEL_HW8_Msk (0x03UL << PORT3_HWSEL_HW8_Pos) /*!< PORT3 HWSEL: HW8 Mask */
\r
12031 #define PORT3_HWSEL_HW9_Pos 18 /*!< PORT3 HWSEL: HW9 Position */
\r
12032 #define PORT3_HWSEL_HW9_Msk (0x03UL << PORT3_HWSEL_HW9_Pos) /*!< PORT3 HWSEL: HW9 Mask */
\r
12033 #define PORT3_HWSEL_HW10_Pos 20 /*!< PORT3 HWSEL: HW10 Position */
\r
12034 #define PORT3_HWSEL_HW10_Msk (0x03UL << PORT3_HWSEL_HW10_Pos) /*!< PORT3 HWSEL: HW10 Mask */
\r
12035 #define PORT3_HWSEL_HW11_Pos 22 /*!< PORT3 HWSEL: HW11 Position */
\r
12036 #define PORT3_HWSEL_HW11_Msk (0x03UL << PORT3_HWSEL_HW11_Pos) /*!< PORT3 HWSEL: HW11 Mask */
\r
12037 #define PORT3_HWSEL_HW12_Pos 24 /*!< PORT3 HWSEL: HW12 Position */
\r
12038 #define PORT3_HWSEL_HW12_Msk (0x03UL << PORT3_HWSEL_HW12_Pos) /*!< PORT3 HWSEL: HW12 Mask */
\r
12039 #define PORT3_HWSEL_HW13_Pos 26 /*!< PORT3 HWSEL: HW13 Position */
\r
12040 #define PORT3_HWSEL_HW13_Msk (0x03UL << PORT3_HWSEL_HW13_Pos) /*!< PORT3 HWSEL: HW13 Mask */
\r
12041 #define PORT3_HWSEL_HW14_Pos 28 /*!< PORT3 HWSEL: HW14 Position */
\r
12042 #define PORT3_HWSEL_HW14_Msk (0x03UL << PORT3_HWSEL_HW14_Pos) /*!< PORT3 HWSEL: HW14 Mask */
\r
12043 #define PORT3_HWSEL_HW15_Pos 30 /*!< PORT3 HWSEL: HW15 Position */
\r
12044 #define PORT3_HWSEL_HW15_Msk (0x03UL << PORT3_HWSEL_HW15_Pos) /*!< PORT3 HWSEL: HW15 Mask */
\r
12047 // ------------------------------------------------------------------------------------------------
\r
12048 // ----- PORT4 Position & Mask -----
\r
12049 // ------------------------------------------------------------------------------------------------
\r
12052 // ---------------------------------------- PORT4_OUT -------------------------------------------
\r
12053 #define PORT4_OUT_P0_Pos 0 /*!< PORT4 OUT: P0 Position */
\r
12054 #define PORT4_OUT_P0_Msk (0x01UL << PORT4_OUT_P0_Pos) /*!< PORT4 OUT: P0 Mask */
\r
12055 #define PORT4_OUT_P1_Pos 1 /*!< PORT4 OUT: P1 Position */
\r
12056 #define PORT4_OUT_P1_Msk (0x01UL << PORT4_OUT_P1_Pos) /*!< PORT4 OUT: P1 Mask */
\r
12057 #define PORT4_OUT_P2_Pos 2 /*!< PORT4 OUT: P2 Position */
\r
12058 #define PORT4_OUT_P2_Msk (0x01UL << PORT4_OUT_P2_Pos) /*!< PORT4 OUT: P2 Mask */
\r
12059 #define PORT4_OUT_P3_Pos 3 /*!< PORT4 OUT: P3 Position */
\r
12060 #define PORT4_OUT_P3_Msk (0x01UL << PORT4_OUT_P3_Pos) /*!< PORT4 OUT: P3 Mask */
\r
12061 #define PORT4_OUT_P4_Pos 4 /*!< PORT4 OUT: P4 Position */
\r
12062 #define PORT4_OUT_P4_Msk (0x01UL << PORT4_OUT_P4_Pos) /*!< PORT4 OUT: P4 Mask */
\r
12063 #define PORT4_OUT_P5_Pos 5 /*!< PORT4 OUT: P5 Position */
\r
12064 #define PORT4_OUT_P5_Msk (0x01UL << PORT4_OUT_P5_Pos) /*!< PORT4 OUT: P5 Mask */
\r
12065 #define PORT4_OUT_P6_Pos 6 /*!< PORT4 OUT: P6 Position */
\r
12066 #define PORT4_OUT_P6_Msk (0x01UL << PORT4_OUT_P6_Pos) /*!< PORT4 OUT: P6 Mask */
\r
12067 #define PORT4_OUT_P7_Pos 7 /*!< PORT4 OUT: P7 Position */
\r
12068 #define PORT4_OUT_P7_Msk (0x01UL << PORT4_OUT_P7_Pos) /*!< PORT4 OUT: P7 Mask */
\r
12069 #define PORT4_OUT_P8_Pos 8 /*!< PORT4 OUT: P8 Position */
\r
12070 #define PORT4_OUT_P8_Msk (0x01UL << PORT4_OUT_P8_Pos) /*!< PORT4 OUT: P8 Mask */
\r
12071 #define PORT4_OUT_P9_Pos 9 /*!< PORT4 OUT: P9 Position */
\r
12072 #define PORT4_OUT_P9_Msk (0x01UL << PORT4_OUT_P9_Pos) /*!< PORT4 OUT: P9 Mask */
\r
12073 #define PORT4_OUT_P10_Pos 10 /*!< PORT4 OUT: P10 Position */
\r
12074 #define PORT4_OUT_P10_Msk (0x01UL << PORT4_OUT_P10_Pos) /*!< PORT4 OUT: P10 Mask */
\r
12075 #define PORT4_OUT_P11_Pos 11 /*!< PORT4 OUT: P11 Position */
\r
12076 #define PORT4_OUT_P11_Msk (0x01UL << PORT4_OUT_P11_Pos) /*!< PORT4 OUT: P11 Mask */
\r
12077 #define PORT4_OUT_P12_Pos 12 /*!< PORT4 OUT: P12 Position */
\r
12078 #define PORT4_OUT_P12_Msk (0x01UL << PORT4_OUT_P12_Pos) /*!< PORT4 OUT: P12 Mask */
\r
12079 #define PORT4_OUT_P13_Pos 13 /*!< PORT4 OUT: P13 Position */
\r
12080 #define PORT4_OUT_P13_Msk (0x01UL << PORT4_OUT_P13_Pos) /*!< PORT4 OUT: P13 Mask */
\r
12081 #define PORT4_OUT_P14_Pos 14 /*!< PORT4 OUT: P14 Position */
\r
12082 #define PORT4_OUT_P14_Msk (0x01UL << PORT4_OUT_P14_Pos) /*!< PORT4 OUT: P14 Mask */
\r
12083 #define PORT4_OUT_P15_Pos 15 /*!< PORT4 OUT: P15 Position */
\r
12084 #define PORT4_OUT_P15_Msk (0x01UL << PORT4_OUT_P15_Pos) /*!< PORT4 OUT: P15 Mask */
\r
12086 // ---------------------------------------- PORT4_OMR -------------------------------------------
\r
12087 #define PORT4_OMR_PS0_Pos 0 /*!< PORT4 OMR: PS0 Position */
\r
12088 #define PORT4_OMR_PS0_Msk (0x01UL << PORT4_OMR_PS0_Pos) /*!< PORT4 OMR: PS0 Mask */
\r
12089 #define PORT4_OMR_PS1_Pos 1 /*!< PORT4 OMR: PS1 Position */
\r
12090 #define PORT4_OMR_PS1_Msk (0x01UL << PORT4_OMR_PS1_Pos) /*!< PORT4 OMR: PS1 Mask */
\r
12091 #define PORT4_OMR_PS2_Pos 2 /*!< PORT4 OMR: PS2 Position */
\r
12092 #define PORT4_OMR_PS2_Msk (0x01UL << PORT4_OMR_PS2_Pos) /*!< PORT4 OMR: PS2 Mask */
\r
12093 #define PORT4_OMR_PS3_Pos 3 /*!< PORT4 OMR: PS3 Position */
\r
12094 #define PORT4_OMR_PS3_Msk (0x01UL << PORT4_OMR_PS3_Pos) /*!< PORT4 OMR: PS3 Mask */
\r
12095 #define PORT4_OMR_PS4_Pos 4 /*!< PORT4 OMR: PS4 Position */
\r
12096 #define PORT4_OMR_PS4_Msk (0x01UL << PORT4_OMR_PS4_Pos) /*!< PORT4 OMR: PS4 Mask */
\r
12097 #define PORT4_OMR_PS5_Pos 5 /*!< PORT4 OMR: PS5 Position */
\r
12098 #define PORT4_OMR_PS5_Msk (0x01UL << PORT4_OMR_PS5_Pos) /*!< PORT4 OMR: PS5 Mask */
\r
12099 #define PORT4_OMR_PS6_Pos 6 /*!< PORT4 OMR: PS6 Position */
\r
12100 #define PORT4_OMR_PS6_Msk (0x01UL << PORT4_OMR_PS6_Pos) /*!< PORT4 OMR: PS6 Mask */
\r
12101 #define PORT4_OMR_PS7_Pos 7 /*!< PORT4 OMR: PS7 Position */
\r
12102 #define PORT4_OMR_PS7_Msk (0x01UL << PORT4_OMR_PS7_Pos) /*!< PORT4 OMR: PS7 Mask */
\r
12103 #define PORT4_OMR_PS8_Pos 8 /*!< PORT4 OMR: PS8 Position */
\r
12104 #define PORT4_OMR_PS8_Msk (0x01UL << PORT4_OMR_PS8_Pos) /*!< PORT4 OMR: PS8 Mask */
\r
12105 #define PORT4_OMR_PS9_Pos 9 /*!< PORT4 OMR: PS9 Position */
\r
12106 #define PORT4_OMR_PS9_Msk (0x01UL << PORT4_OMR_PS9_Pos) /*!< PORT4 OMR: PS9 Mask */
\r
12107 #define PORT4_OMR_PS10_Pos 10 /*!< PORT4 OMR: PS10 Position */
\r
12108 #define PORT4_OMR_PS10_Msk (0x01UL << PORT4_OMR_PS10_Pos) /*!< PORT4 OMR: PS10 Mask */
\r
12109 #define PORT4_OMR_PS11_Pos 11 /*!< PORT4 OMR: PS11 Position */
\r
12110 #define PORT4_OMR_PS11_Msk (0x01UL << PORT4_OMR_PS11_Pos) /*!< PORT4 OMR: PS11 Mask */
\r
12111 #define PORT4_OMR_PS12_Pos 12 /*!< PORT4 OMR: PS12 Position */
\r
12112 #define PORT4_OMR_PS12_Msk (0x01UL << PORT4_OMR_PS12_Pos) /*!< PORT4 OMR: PS12 Mask */
\r
12113 #define PORT4_OMR_PS13_Pos 13 /*!< PORT4 OMR: PS13 Position */
\r
12114 #define PORT4_OMR_PS13_Msk (0x01UL << PORT4_OMR_PS13_Pos) /*!< PORT4 OMR: PS13 Mask */
\r
12115 #define PORT4_OMR_PS14_Pos 14 /*!< PORT4 OMR: PS14 Position */
\r
12116 #define PORT4_OMR_PS14_Msk (0x01UL << PORT4_OMR_PS14_Pos) /*!< PORT4 OMR: PS14 Mask */
\r
12117 #define PORT4_OMR_PS15_Pos 15 /*!< PORT4 OMR: PS15 Position */
\r
12118 #define PORT4_OMR_PS15_Msk (0x01UL << PORT4_OMR_PS15_Pos) /*!< PORT4 OMR: PS15 Mask */
\r
12119 #define PORT4_OMR_PR0_Pos 16 /*!< PORT4 OMR: PR0 Position */
\r
12120 #define PORT4_OMR_PR0_Msk (0x01UL << PORT4_OMR_PR0_Pos) /*!< PORT4 OMR: PR0 Mask */
\r
12121 #define PORT4_OMR_PR1_Pos 17 /*!< PORT4 OMR: PR1 Position */
\r
12122 #define PORT4_OMR_PR1_Msk (0x01UL << PORT4_OMR_PR1_Pos) /*!< PORT4 OMR: PR1 Mask */
\r
12123 #define PORT4_OMR_PR2_Pos 18 /*!< PORT4 OMR: PR2 Position */
\r
12124 #define PORT4_OMR_PR2_Msk (0x01UL << PORT4_OMR_PR2_Pos) /*!< PORT4 OMR: PR2 Mask */
\r
12125 #define PORT4_OMR_PR3_Pos 19 /*!< PORT4 OMR: PR3 Position */
\r
12126 #define PORT4_OMR_PR3_Msk (0x01UL << PORT4_OMR_PR3_Pos) /*!< PORT4 OMR: PR3 Mask */
\r
12127 #define PORT4_OMR_PR4_Pos 20 /*!< PORT4 OMR: PR4 Position */
\r
12128 #define PORT4_OMR_PR4_Msk (0x01UL << PORT4_OMR_PR4_Pos) /*!< PORT4 OMR: PR4 Mask */
\r
12129 #define PORT4_OMR_PR5_Pos 21 /*!< PORT4 OMR: PR5 Position */
\r
12130 #define PORT4_OMR_PR5_Msk (0x01UL << PORT4_OMR_PR5_Pos) /*!< PORT4 OMR: PR5 Mask */
\r
12131 #define PORT4_OMR_PR6_Pos 22 /*!< PORT4 OMR: PR6 Position */
\r
12132 #define PORT4_OMR_PR6_Msk (0x01UL << PORT4_OMR_PR6_Pos) /*!< PORT4 OMR: PR6 Mask */
\r
12133 #define PORT4_OMR_PR7_Pos 23 /*!< PORT4 OMR: PR7 Position */
\r
12134 #define PORT4_OMR_PR7_Msk (0x01UL << PORT4_OMR_PR7_Pos) /*!< PORT4 OMR: PR7 Mask */
\r
12135 #define PORT4_OMR_PR8_Pos 24 /*!< PORT4 OMR: PR8 Position */
\r
12136 #define PORT4_OMR_PR8_Msk (0x01UL << PORT4_OMR_PR8_Pos) /*!< PORT4 OMR: PR8 Mask */
\r
12137 #define PORT4_OMR_PR9_Pos 25 /*!< PORT4 OMR: PR9 Position */
\r
12138 #define PORT4_OMR_PR9_Msk (0x01UL << PORT4_OMR_PR9_Pos) /*!< PORT4 OMR: PR9 Mask */
\r
12139 #define PORT4_OMR_PR10_Pos 26 /*!< PORT4 OMR: PR10 Position */
\r
12140 #define PORT4_OMR_PR10_Msk (0x01UL << PORT4_OMR_PR10_Pos) /*!< PORT4 OMR: PR10 Mask */
\r
12141 #define PORT4_OMR_PR11_Pos 27 /*!< PORT4 OMR: PR11 Position */
\r
12142 #define PORT4_OMR_PR11_Msk (0x01UL << PORT4_OMR_PR11_Pos) /*!< PORT4 OMR: PR11 Mask */
\r
12143 #define PORT4_OMR_PR12_Pos 28 /*!< PORT4 OMR: PR12 Position */
\r
12144 #define PORT4_OMR_PR12_Msk (0x01UL << PORT4_OMR_PR12_Pos) /*!< PORT4 OMR: PR12 Mask */
\r
12145 #define PORT4_OMR_PR13_Pos 29 /*!< PORT4 OMR: PR13 Position */
\r
12146 #define PORT4_OMR_PR13_Msk (0x01UL << PORT4_OMR_PR13_Pos) /*!< PORT4 OMR: PR13 Mask */
\r
12147 #define PORT4_OMR_PR14_Pos 30 /*!< PORT4 OMR: PR14 Position */
\r
12148 #define PORT4_OMR_PR14_Msk (0x01UL << PORT4_OMR_PR14_Pos) /*!< PORT4 OMR: PR14 Mask */
\r
12149 #define PORT4_OMR_PR15_Pos 31 /*!< PORT4 OMR: PR15 Position */
\r
12150 #define PORT4_OMR_PR15_Msk (0x01UL << PORT4_OMR_PR15_Pos) /*!< PORT4 OMR: PR15 Mask */
\r
12152 // --------------------------------------- PORT4_IOCR0 ------------------------------------------
\r
12153 #define PORT4_IOCR0_PC0_Pos 3 /*!< PORT4 IOCR0: PC0 Position */
\r
12154 #define PORT4_IOCR0_PC0_Msk (0x1fUL << PORT4_IOCR0_PC0_Pos) /*!< PORT4 IOCR0: PC0 Mask */
\r
12155 #define PORT4_IOCR0_PC1_Pos 11 /*!< PORT4 IOCR0: PC1 Position */
\r
12156 #define PORT4_IOCR0_PC1_Msk (0x1fUL << PORT4_IOCR0_PC1_Pos) /*!< PORT4 IOCR0: PC1 Mask */
\r
12157 #define PORT4_IOCR0_PC2_Pos 19 /*!< PORT4 IOCR0: PC2 Position */
\r
12158 #define PORT4_IOCR0_PC2_Msk (0x1fUL << PORT4_IOCR0_PC2_Pos) /*!< PORT4 IOCR0: PC2 Mask */
\r
12159 #define PORT4_IOCR0_PC3_Pos 27 /*!< PORT4 IOCR0: PC3 Position */
\r
12160 #define PORT4_IOCR0_PC3_Msk (0x1fUL << PORT4_IOCR0_PC3_Pos) /*!< PORT4 IOCR0: PC3 Mask */
\r
12162 // --------------------------------------- PORT4_IOCR4 ------------------------------------------
\r
12163 #define PORT4_IOCR4_PC4_Pos 3 /*!< PORT4 IOCR4: PC4 Position */
\r
12164 #define PORT4_IOCR4_PC4_Msk (0x1fUL << PORT4_IOCR4_PC4_Pos) /*!< PORT4 IOCR4: PC4 Mask */
\r
12165 #define PORT4_IOCR4_PC5_Pos 11 /*!< PORT4 IOCR4: PC5 Position */
\r
12166 #define PORT4_IOCR4_PC5_Msk (0x1fUL << PORT4_IOCR4_PC5_Pos) /*!< PORT4 IOCR4: PC5 Mask */
\r
12167 #define PORT4_IOCR4_PC6_Pos 19 /*!< PORT4 IOCR4: PC6 Position */
\r
12168 #define PORT4_IOCR4_PC6_Msk (0x1fUL << PORT4_IOCR4_PC6_Pos) /*!< PORT4 IOCR4: PC6 Mask */
\r
12169 #define PORT4_IOCR4_PC7_Pos 27 /*!< PORT4 IOCR4: PC7 Position */
\r
12170 #define PORT4_IOCR4_PC7_Msk (0x1fUL << PORT4_IOCR4_PC7_Pos) /*!< PORT4 IOCR4: PC7 Mask */
\r
12172 // ---------------------------------------- PORT4_IN --------------------------------------------
\r
12173 #define PORT4_IN_P0_Pos 0 /*!< PORT4 IN: P0 Position */
\r
12174 #define PORT4_IN_P0_Msk (0x01UL << PORT4_IN_P0_Pos) /*!< PORT4 IN: P0 Mask */
\r
12175 #define PORT4_IN_P1_Pos 1 /*!< PORT4 IN: P1 Position */
\r
12176 #define PORT4_IN_P1_Msk (0x01UL << PORT4_IN_P1_Pos) /*!< PORT4 IN: P1 Mask */
\r
12177 #define PORT4_IN_P2_Pos 2 /*!< PORT4 IN: P2 Position */
\r
12178 #define PORT4_IN_P2_Msk (0x01UL << PORT4_IN_P2_Pos) /*!< PORT4 IN: P2 Mask */
\r
12179 #define PORT4_IN_P3_Pos 3 /*!< PORT4 IN: P3 Position */
\r
12180 #define PORT4_IN_P3_Msk (0x01UL << PORT4_IN_P3_Pos) /*!< PORT4 IN: P3 Mask */
\r
12181 #define PORT4_IN_P4_Pos 4 /*!< PORT4 IN: P4 Position */
\r
12182 #define PORT4_IN_P4_Msk (0x01UL << PORT4_IN_P4_Pos) /*!< PORT4 IN: P4 Mask */
\r
12183 #define PORT4_IN_P5_Pos 5 /*!< PORT4 IN: P5 Position */
\r
12184 #define PORT4_IN_P5_Msk (0x01UL << PORT4_IN_P5_Pos) /*!< PORT4 IN: P5 Mask */
\r
12185 #define PORT4_IN_P6_Pos 6 /*!< PORT4 IN: P6 Position */
\r
12186 #define PORT4_IN_P6_Msk (0x01UL << PORT4_IN_P6_Pos) /*!< PORT4 IN: P6 Mask */
\r
12187 #define PORT4_IN_P7_Pos 7 /*!< PORT4 IN: P7 Position */
\r
12188 #define PORT4_IN_P7_Msk (0x01UL << PORT4_IN_P7_Pos) /*!< PORT4 IN: P7 Mask */
\r
12189 #define PORT4_IN_P8_Pos 8 /*!< PORT4 IN: P8 Position */
\r
12190 #define PORT4_IN_P8_Msk (0x01UL << PORT4_IN_P8_Pos) /*!< PORT4 IN: P8 Mask */
\r
12191 #define PORT4_IN_P9_Pos 9 /*!< PORT4 IN: P9 Position */
\r
12192 #define PORT4_IN_P9_Msk (0x01UL << PORT4_IN_P9_Pos) /*!< PORT4 IN: P9 Mask */
\r
12193 #define PORT4_IN_P10_Pos 10 /*!< PORT4 IN: P10 Position */
\r
12194 #define PORT4_IN_P10_Msk (0x01UL << PORT4_IN_P10_Pos) /*!< PORT4 IN: P10 Mask */
\r
12195 #define PORT4_IN_P11_Pos 11 /*!< PORT4 IN: P11 Position */
\r
12196 #define PORT4_IN_P11_Msk (0x01UL << PORT4_IN_P11_Pos) /*!< PORT4 IN: P11 Mask */
\r
12197 #define PORT4_IN_P12_Pos 12 /*!< PORT4 IN: P12 Position */
\r
12198 #define PORT4_IN_P12_Msk (0x01UL << PORT4_IN_P12_Pos) /*!< PORT4 IN: P12 Mask */
\r
12199 #define PORT4_IN_P13_Pos 13 /*!< PORT4 IN: P13 Position */
\r
12200 #define PORT4_IN_P13_Msk (0x01UL << PORT4_IN_P13_Pos) /*!< PORT4 IN: P13 Mask */
\r
12201 #define PORT4_IN_P14_Pos 14 /*!< PORT4 IN: P14 Position */
\r
12202 #define PORT4_IN_P14_Msk (0x01UL << PORT4_IN_P14_Pos) /*!< PORT4 IN: P14 Mask */
\r
12203 #define PORT4_IN_P15_Pos 15 /*!< PORT4 IN: P15 Position */
\r
12204 #define PORT4_IN_P15_Msk (0x01UL << PORT4_IN_P15_Pos) /*!< PORT4 IN: P15 Mask */
\r
12206 // --------------------------------------- PORT4_PDR0 -------------------------------------------
\r
12207 #define PORT4_PDR0_PD0_Pos 0 /*!< PORT4 PDR0: PD0 Position */
\r
12208 #define PORT4_PDR0_PD0_Msk (0x07UL << PORT4_PDR0_PD0_Pos) /*!< PORT4 PDR0: PD0 Mask */
\r
12209 #define PORT4_PDR0_PD1_Pos 4 /*!< PORT4 PDR0: PD1 Position */
\r
12210 #define PORT4_PDR0_PD1_Msk (0x07UL << PORT4_PDR0_PD1_Pos) /*!< PORT4 PDR0: PD1 Mask */
\r
12211 #define PORT4_PDR0_PD2_Pos 8 /*!< PORT4 PDR0: PD2 Position */
\r
12212 #define PORT4_PDR0_PD2_Msk (0x07UL << PORT4_PDR0_PD2_Pos) /*!< PORT4 PDR0: PD2 Mask */
\r
12213 #define PORT4_PDR0_PD3_Pos 12 /*!< PORT4 PDR0: PD3 Position */
\r
12214 #define PORT4_PDR0_PD3_Msk (0x07UL << PORT4_PDR0_PD3_Pos) /*!< PORT4 PDR0: PD3 Mask */
\r
12215 #define PORT4_PDR0_PD4_Pos 16 /*!< PORT4 PDR0: PD4 Position */
\r
12216 #define PORT4_PDR0_PD4_Msk (0x07UL << PORT4_PDR0_PD4_Pos) /*!< PORT4 PDR0: PD4 Mask */
\r
12217 #define PORT4_PDR0_PD5_Pos 20 /*!< PORT4 PDR0: PD5 Position */
\r
12218 #define PORT4_PDR0_PD5_Msk (0x07UL << PORT4_PDR0_PD5_Pos) /*!< PORT4 PDR0: PD5 Mask */
\r
12219 #define PORT4_PDR0_PD6_Pos 24 /*!< PORT4 PDR0: PD6 Position */
\r
12220 #define PORT4_PDR0_PD6_Msk (0x07UL << PORT4_PDR0_PD6_Pos) /*!< PORT4 PDR0: PD6 Mask */
\r
12221 #define PORT4_PDR0_PD7_Pos 28 /*!< PORT4 PDR0: PD7 Position */
\r
12222 #define PORT4_PDR0_PD7_Msk (0x07UL << PORT4_PDR0_PD7_Pos) /*!< PORT4 PDR0: PD7 Mask */
\r
12224 // --------------------------------------- PORT4_PDISC ------------------------------------------
\r
12225 #define PORT4_PDISC_PDIS0_Pos 0 /*!< PORT4 PDISC: PDIS0 Position */
\r
12226 #define PORT4_PDISC_PDIS0_Msk (0x01UL << PORT4_PDISC_PDIS0_Pos) /*!< PORT4 PDISC: PDIS0 Mask */
\r
12227 #define PORT4_PDISC_PDIS1_Pos 1 /*!< PORT4 PDISC: PDIS1 Position */
\r
12228 #define PORT4_PDISC_PDIS1_Msk (0x01UL << PORT4_PDISC_PDIS1_Pos) /*!< PORT4 PDISC: PDIS1 Mask */
\r
12229 #define PORT4_PDISC_PDIS2_Pos 2 /*!< PORT4 PDISC: PDIS2 Position */
\r
12230 #define PORT4_PDISC_PDIS2_Msk (0x01UL << PORT4_PDISC_PDIS2_Pos) /*!< PORT4 PDISC: PDIS2 Mask */
\r
12231 #define PORT4_PDISC_PDIS3_Pos 3 /*!< PORT4 PDISC: PDIS3 Position */
\r
12232 #define PORT4_PDISC_PDIS3_Msk (0x01UL << PORT4_PDISC_PDIS3_Pos) /*!< PORT4 PDISC: PDIS3 Mask */
\r
12233 #define PORT4_PDISC_PDIS4_Pos 4 /*!< PORT4 PDISC: PDIS4 Position */
\r
12234 #define PORT4_PDISC_PDIS4_Msk (0x01UL << PORT4_PDISC_PDIS4_Pos) /*!< PORT4 PDISC: PDIS4 Mask */
\r
12235 #define PORT4_PDISC_PDIS5_Pos 5 /*!< PORT4 PDISC: PDIS5 Position */
\r
12236 #define PORT4_PDISC_PDIS5_Msk (0x01UL << PORT4_PDISC_PDIS5_Pos) /*!< PORT4 PDISC: PDIS5 Mask */
\r
12237 #define PORT4_PDISC_PDIS6_Pos 6 /*!< PORT4 PDISC: PDIS6 Position */
\r
12238 #define PORT4_PDISC_PDIS6_Msk (0x01UL << PORT4_PDISC_PDIS6_Pos) /*!< PORT4 PDISC: PDIS6 Mask */
\r
12239 #define PORT4_PDISC_PDIS7_Pos 7 /*!< PORT4 PDISC: PDIS7 Position */
\r
12240 #define PORT4_PDISC_PDIS7_Msk (0x01UL << PORT4_PDISC_PDIS7_Pos) /*!< PORT4 PDISC: PDIS7 Mask */
\r
12241 #define PORT4_PDISC_PDIS8_Pos 8 /*!< PORT4 PDISC: PDIS8 Position */
\r
12242 #define PORT4_PDISC_PDIS8_Msk (0x01UL << PORT4_PDISC_PDIS8_Pos) /*!< PORT4 PDISC: PDIS8 Mask */
\r
12243 #define PORT4_PDISC_PDIS9_Pos 9 /*!< PORT4 PDISC: PDIS9 Position */
\r
12244 #define PORT4_PDISC_PDIS9_Msk (0x01UL << PORT4_PDISC_PDIS9_Pos) /*!< PORT4 PDISC: PDIS9 Mask */
\r
12245 #define PORT4_PDISC_PDIS10_Pos 10 /*!< PORT4 PDISC: PDIS10 Position */
\r
12246 #define PORT4_PDISC_PDIS10_Msk (0x01UL << PORT4_PDISC_PDIS10_Pos) /*!< PORT4 PDISC: PDIS10 Mask */
\r
12247 #define PORT4_PDISC_PDIS11_Pos 11 /*!< PORT4 PDISC: PDIS11 Position */
\r
12248 #define PORT4_PDISC_PDIS11_Msk (0x01UL << PORT4_PDISC_PDIS11_Pos) /*!< PORT4 PDISC: PDIS11 Mask */
\r
12249 #define PORT4_PDISC_PDIS12_Pos 12 /*!< PORT4 PDISC: PDIS12 Position */
\r
12250 #define PORT4_PDISC_PDIS12_Msk (0x01UL << PORT4_PDISC_PDIS12_Pos) /*!< PORT4 PDISC: PDIS12 Mask */
\r
12251 #define PORT4_PDISC_PDIS13_Pos 13 /*!< PORT4 PDISC: PDIS13 Position */
\r
12252 #define PORT4_PDISC_PDIS13_Msk (0x01UL << PORT4_PDISC_PDIS13_Pos) /*!< PORT4 PDISC: PDIS13 Mask */
\r
12253 #define PORT4_PDISC_PDIS14_Pos 14 /*!< PORT4 PDISC: PDIS14 Position */
\r
12254 #define PORT4_PDISC_PDIS14_Msk (0x01UL << PORT4_PDISC_PDIS14_Pos) /*!< PORT4 PDISC: PDIS14 Mask */
\r
12255 #define PORT4_PDISC_PDIS15_Pos 15 /*!< PORT4 PDISC: PDIS15 Position */
\r
12256 #define PORT4_PDISC_PDIS15_Msk (0x01UL << PORT4_PDISC_PDIS15_Pos) /*!< PORT4 PDISC: PDIS15 Mask */
\r
12258 // ---------------------------------------- PORT4_PPS -------------------------------------------
\r
12259 #define PORT4_PPS_PPS0_Pos 0 /*!< PORT4 PPS: PPS0 Position */
\r
12260 #define PORT4_PPS_PPS0_Msk (0x01UL << PORT4_PPS_PPS0_Pos) /*!< PORT4 PPS: PPS0 Mask */
\r
12261 #define PORT4_PPS_PPS1_Pos 1 /*!< PORT4 PPS: PPS1 Position */
\r
12262 #define PORT4_PPS_PPS1_Msk (0x01UL << PORT4_PPS_PPS1_Pos) /*!< PORT4 PPS: PPS1 Mask */
\r
12263 #define PORT4_PPS_PPS2_Pos 2 /*!< PORT4 PPS: PPS2 Position */
\r
12264 #define PORT4_PPS_PPS2_Msk (0x01UL << PORT4_PPS_PPS2_Pos) /*!< PORT4 PPS: PPS2 Mask */
\r
12265 #define PORT4_PPS_PPS3_Pos 3 /*!< PORT4 PPS: PPS3 Position */
\r
12266 #define PORT4_PPS_PPS3_Msk (0x01UL << PORT4_PPS_PPS3_Pos) /*!< PORT4 PPS: PPS3 Mask */
\r
12267 #define PORT4_PPS_PPS4_Pos 4 /*!< PORT4 PPS: PPS4 Position */
\r
12268 #define PORT4_PPS_PPS4_Msk (0x01UL << PORT4_PPS_PPS4_Pos) /*!< PORT4 PPS: PPS4 Mask */
\r
12269 #define PORT4_PPS_PPS5_Pos 5 /*!< PORT4 PPS: PPS5 Position */
\r
12270 #define PORT4_PPS_PPS5_Msk (0x01UL << PORT4_PPS_PPS5_Pos) /*!< PORT4 PPS: PPS5 Mask */
\r
12271 #define PORT4_PPS_PPS6_Pos 6 /*!< PORT4 PPS: PPS6 Position */
\r
12272 #define PORT4_PPS_PPS6_Msk (0x01UL << PORT4_PPS_PPS6_Pos) /*!< PORT4 PPS: PPS6 Mask */
\r
12273 #define PORT4_PPS_PPS7_Pos 7 /*!< PORT4 PPS: PPS7 Position */
\r
12274 #define PORT4_PPS_PPS7_Msk (0x01UL << PORT4_PPS_PPS7_Pos) /*!< PORT4 PPS: PPS7 Mask */
\r
12275 #define PORT4_PPS_PPS8_Pos 8 /*!< PORT4 PPS: PPS8 Position */
\r
12276 #define PORT4_PPS_PPS8_Msk (0x01UL << PORT4_PPS_PPS8_Pos) /*!< PORT4 PPS: PPS8 Mask */
\r
12277 #define PORT4_PPS_PPS9_Pos 9 /*!< PORT4 PPS: PPS9 Position */
\r
12278 #define PORT4_PPS_PPS9_Msk (0x01UL << PORT4_PPS_PPS9_Pos) /*!< PORT4 PPS: PPS9 Mask */
\r
12279 #define PORT4_PPS_PPS10_Pos 10 /*!< PORT4 PPS: PPS10 Position */
\r
12280 #define PORT4_PPS_PPS10_Msk (0x01UL << PORT4_PPS_PPS10_Pos) /*!< PORT4 PPS: PPS10 Mask */
\r
12281 #define PORT4_PPS_PPS11_Pos 11 /*!< PORT4 PPS: PPS11 Position */
\r
12282 #define PORT4_PPS_PPS11_Msk (0x01UL << PORT4_PPS_PPS11_Pos) /*!< PORT4 PPS: PPS11 Mask */
\r
12283 #define PORT4_PPS_PPS12_Pos 12 /*!< PORT4 PPS: PPS12 Position */
\r
12284 #define PORT4_PPS_PPS12_Msk (0x01UL << PORT4_PPS_PPS12_Pos) /*!< PORT4 PPS: PPS12 Mask */
\r
12285 #define PORT4_PPS_PPS13_Pos 13 /*!< PORT4 PPS: PPS13 Position */
\r
12286 #define PORT4_PPS_PPS13_Msk (0x01UL << PORT4_PPS_PPS13_Pos) /*!< PORT4 PPS: PPS13 Mask */
\r
12287 #define PORT4_PPS_PPS14_Pos 14 /*!< PORT4 PPS: PPS14 Position */
\r
12288 #define PORT4_PPS_PPS14_Msk (0x01UL << PORT4_PPS_PPS14_Pos) /*!< PORT4 PPS: PPS14 Mask */
\r
12289 #define PORT4_PPS_PPS15_Pos 15 /*!< PORT4 PPS: PPS15 Position */
\r
12290 #define PORT4_PPS_PPS15_Msk (0x01UL << PORT4_PPS_PPS15_Pos) /*!< PORT4 PPS: PPS15 Mask */
\r
12292 // --------------------------------------- PORT4_HWSEL ------------------------------------------
\r
12293 #define PORT4_HWSEL_HW0_Pos 0 /*!< PORT4 HWSEL: HW0 Position */
\r
12294 #define PORT4_HWSEL_HW0_Msk (0x03UL << PORT4_HWSEL_HW0_Pos) /*!< PORT4 HWSEL: HW0 Mask */
\r
12295 #define PORT4_HWSEL_HW1_Pos 2 /*!< PORT4 HWSEL: HW1 Position */
\r
12296 #define PORT4_HWSEL_HW1_Msk (0x03UL << PORT4_HWSEL_HW1_Pos) /*!< PORT4 HWSEL: HW1 Mask */
\r
12297 #define PORT4_HWSEL_HW2_Pos 4 /*!< PORT4 HWSEL: HW2 Position */
\r
12298 #define PORT4_HWSEL_HW2_Msk (0x03UL << PORT4_HWSEL_HW2_Pos) /*!< PORT4 HWSEL: HW2 Mask */
\r
12299 #define PORT4_HWSEL_HW3_Pos 6 /*!< PORT4 HWSEL: HW3 Position */
\r
12300 #define PORT4_HWSEL_HW3_Msk (0x03UL << PORT4_HWSEL_HW3_Pos) /*!< PORT4 HWSEL: HW3 Mask */
\r
12301 #define PORT4_HWSEL_HW4_Pos 8 /*!< PORT4 HWSEL: HW4 Position */
\r
12302 #define PORT4_HWSEL_HW4_Msk (0x03UL << PORT4_HWSEL_HW4_Pos) /*!< PORT4 HWSEL: HW4 Mask */
\r
12303 #define PORT4_HWSEL_HW5_Pos 10 /*!< PORT4 HWSEL: HW5 Position */
\r
12304 #define PORT4_HWSEL_HW5_Msk (0x03UL << PORT4_HWSEL_HW5_Pos) /*!< PORT4 HWSEL: HW5 Mask */
\r
12305 #define PORT4_HWSEL_HW6_Pos 12 /*!< PORT4 HWSEL: HW6 Position */
\r
12306 #define PORT4_HWSEL_HW6_Msk (0x03UL << PORT4_HWSEL_HW6_Pos) /*!< PORT4 HWSEL: HW6 Mask */
\r
12307 #define PORT4_HWSEL_HW7_Pos 14 /*!< PORT4 HWSEL: HW7 Position */
\r
12308 #define PORT4_HWSEL_HW7_Msk (0x03UL << PORT4_HWSEL_HW7_Pos) /*!< PORT4 HWSEL: HW7 Mask */
\r
12309 #define PORT4_HWSEL_HW8_Pos 16 /*!< PORT4 HWSEL: HW8 Position */
\r
12310 #define PORT4_HWSEL_HW8_Msk (0x03UL << PORT4_HWSEL_HW8_Pos) /*!< PORT4 HWSEL: HW8 Mask */
\r
12311 #define PORT4_HWSEL_HW9_Pos 18 /*!< PORT4 HWSEL: HW9 Position */
\r
12312 #define PORT4_HWSEL_HW9_Msk (0x03UL << PORT4_HWSEL_HW9_Pos) /*!< PORT4 HWSEL: HW9 Mask */
\r
12313 #define PORT4_HWSEL_HW10_Pos 20 /*!< PORT4 HWSEL: HW10 Position */
\r
12314 #define PORT4_HWSEL_HW10_Msk (0x03UL << PORT4_HWSEL_HW10_Pos) /*!< PORT4 HWSEL: HW10 Mask */
\r
12315 #define PORT4_HWSEL_HW11_Pos 22 /*!< PORT4 HWSEL: HW11 Position */
\r
12316 #define PORT4_HWSEL_HW11_Msk (0x03UL << PORT4_HWSEL_HW11_Pos) /*!< PORT4 HWSEL: HW11 Mask */
\r
12317 #define PORT4_HWSEL_HW12_Pos 24 /*!< PORT4 HWSEL: HW12 Position */
\r
12318 #define PORT4_HWSEL_HW12_Msk (0x03UL << PORT4_HWSEL_HW12_Pos) /*!< PORT4 HWSEL: HW12 Mask */
\r
12319 #define PORT4_HWSEL_HW13_Pos 26 /*!< PORT4 HWSEL: HW13 Position */
\r
12320 #define PORT4_HWSEL_HW13_Msk (0x03UL << PORT4_HWSEL_HW13_Pos) /*!< PORT4 HWSEL: HW13 Mask */
\r
12321 #define PORT4_HWSEL_HW14_Pos 28 /*!< PORT4 HWSEL: HW14 Position */
\r
12322 #define PORT4_HWSEL_HW14_Msk (0x03UL << PORT4_HWSEL_HW14_Pos) /*!< PORT4 HWSEL: HW14 Mask */
\r
12323 #define PORT4_HWSEL_HW15_Pos 30 /*!< PORT4 HWSEL: HW15 Position */
\r
12324 #define PORT4_HWSEL_HW15_Msk (0x03UL << PORT4_HWSEL_HW15_Pos) /*!< PORT4 HWSEL: HW15 Mask */
\r
12327 // ------------------------------------------------------------------------------------------------
\r
12328 // ----- PORT5 Position & Mask -----
\r
12329 // ------------------------------------------------------------------------------------------------
\r
12332 // ---------------------------------------- PORT5_OUT -------------------------------------------
\r
12333 #define PORT5_OUT_P0_Pos 0 /*!< PORT5 OUT: P0 Position */
\r
12334 #define PORT5_OUT_P0_Msk (0x01UL << PORT5_OUT_P0_Pos) /*!< PORT5 OUT: P0 Mask */
\r
12335 #define PORT5_OUT_P1_Pos 1 /*!< PORT5 OUT: P1 Position */
\r
12336 #define PORT5_OUT_P1_Msk (0x01UL << PORT5_OUT_P1_Pos) /*!< PORT5 OUT: P1 Mask */
\r
12337 #define PORT5_OUT_P2_Pos 2 /*!< PORT5 OUT: P2 Position */
\r
12338 #define PORT5_OUT_P2_Msk (0x01UL << PORT5_OUT_P2_Pos) /*!< PORT5 OUT: P2 Mask */
\r
12339 #define PORT5_OUT_P3_Pos 3 /*!< PORT5 OUT: P3 Position */
\r
12340 #define PORT5_OUT_P3_Msk (0x01UL << PORT5_OUT_P3_Pos) /*!< PORT5 OUT: P3 Mask */
\r
12341 #define PORT5_OUT_P4_Pos 4 /*!< PORT5 OUT: P4 Position */
\r
12342 #define PORT5_OUT_P4_Msk (0x01UL << PORT5_OUT_P4_Pos) /*!< PORT5 OUT: P4 Mask */
\r
12343 #define PORT5_OUT_P5_Pos 5 /*!< PORT5 OUT: P5 Position */
\r
12344 #define PORT5_OUT_P5_Msk (0x01UL << PORT5_OUT_P5_Pos) /*!< PORT5 OUT: P5 Mask */
\r
12345 #define PORT5_OUT_P6_Pos 6 /*!< PORT5 OUT: P6 Position */
\r
12346 #define PORT5_OUT_P6_Msk (0x01UL << PORT5_OUT_P6_Pos) /*!< PORT5 OUT: P6 Mask */
\r
12347 #define PORT5_OUT_P7_Pos 7 /*!< PORT5 OUT: P7 Position */
\r
12348 #define PORT5_OUT_P7_Msk (0x01UL << PORT5_OUT_P7_Pos) /*!< PORT5 OUT: P7 Mask */
\r
12349 #define PORT5_OUT_P8_Pos 8 /*!< PORT5 OUT: P8 Position */
\r
12350 #define PORT5_OUT_P8_Msk (0x01UL << PORT5_OUT_P8_Pos) /*!< PORT5 OUT: P8 Mask */
\r
12351 #define PORT5_OUT_P9_Pos 9 /*!< PORT5 OUT: P9 Position */
\r
12352 #define PORT5_OUT_P9_Msk (0x01UL << PORT5_OUT_P9_Pos) /*!< PORT5 OUT: P9 Mask */
\r
12353 #define PORT5_OUT_P10_Pos 10 /*!< PORT5 OUT: P10 Position */
\r
12354 #define PORT5_OUT_P10_Msk (0x01UL << PORT5_OUT_P10_Pos) /*!< PORT5 OUT: P10 Mask */
\r
12355 #define PORT5_OUT_P11_Pos 11 /*!< PORT5 OUT: P11 Position */
\r
12356 #define PORT5_OUT_P11_Msk (0x01UL << PORT5_OUT_P11_Pos) /*!< PORT5 OUT: P11 Mask */
\r
12357 #define PORT5_OUT_P12_Pos 12 /*!< PORT5 OUT: P12 Position */
\r
12358 #define PORT5_OUT_P12_Msk (0x01UL << PORT5_OUT_P12_Pos) /*!< PORT5 OUT: P12 Mask */
\r
12359 #define PORT5_OUT_P13_Pos 13 /*!< PORT5 OUT: P13 Position */
\r
12360 #define PORT5_OUT_P13_Msk (0x01UL << PORT5_OUT_P13_Pos) /*!< PORT5 OUT: P13 Mask */
\r
12361 #define PORT5_OUT_P14_Pos 14 /*!< PORT5 OUT: P14 Position */
\r
12362 #define PORT5_OUT_P14_Msk (0x01UL << PORT5_OUT_P14_Pos) /*!< PORT5 OUT: P14 Mask */
\r
12363 #define PORT5_OUT_P15_Pos 15 /*!< PORT5 OUT: P15 Position */
\r
12364 #define PORT5_OUT_P15_Msk (0x01UL << PORT5_OUT_P15_Pos) /*!< PORT5 OUT: P15 Mask */
\r
12366 // ---------------------------------------- PORT5_OMR -------------------------------------------
\r
12367 #define PORT5_OMR_PS0_Pos 0 /*!< PORT5 OMR: PS0 Position */
\r
12368 #define PORT5_OMR_PS0_Msk (0x01UL << PORT5_OMR_PS0_Pos) /*!< PORT5 OMR: PS0 Mask */
\r
12369 #define PORT5_OMR_PS1_Pos 1 /*!< PORT5 OMR: PS1 Position */
\r
12370 #define PORT5_OMR_PS1_Msk (0x01UL << PORT5_OMR_PS1_Pos) /*!< PORT5 OMR: PS1 Mask */
\r
12371 #define PORT5_OMR_PS2_Pos 2 /*!< PORT5 OMR: PS2 Position */
\r
12372 #define PORT5_OMR_PS2_Msk (0x01UL << PORT5_OMR_PS2_Pos) /*!< PORT5 OMR: PS2 Mask */
\r
12373 #define PORT5_OMR_PS3_Pos 3 /*!< PORT5 OMR: PS3 Position */
\r
12374 #define PORT5_OMR_PS3_Msk (0x01UL << PORT5_OMR_PS3_Pos) /*!< PORT5 OMR: PS3 Mask */
\r
12375 #define PORT5_OMR_PS4_Pos 4 /*!< PORT5 OMR: PS4 Position */
\r
12376 #define PORT5_OMR_PS4_Msk (0x01UL << PORT5_OMR_PS4_Pos) /*!< PORT5 OMR: PS4 Mask */
\r
12377 #define PORT5_OMR_PS5_Pos 5 /*!< PORT5 OMR: PS5 Position */
\r
12378 #define PORT5_OMR_PS5_Msk (0x01UL << PORT5_OMR_PS5_Pos) /*!< PORT5 OMR: PS5 Mask */
\r
12379 #define PORT5_OMR_PS6_Pos 6 /*!< PORT5 OMR: PS6 Position */
\r
12380 #define PORT5_OMR_PS6_Msk (0x01UL << PORT5_OMR_PS6_Pos) /*!< PORT5 OMR: PS6 Mask */
\r
12381 #define PORT5_OMR_PS7_Pos 7 /*!< PORT5 OMR: PS7 Position */
\r
12382 #define PORT5_OMR_PS7_Msk (0x01UL << PORT5_OMR_PS7_Pos) /*!< PORT5 OMR: PS7 Mask */
\r
12383 #define PORT5_OMR_PS8_Pos 8 /*!< PORT5 OMR: PS8 Position */
\r
12384 #define PORT5_OMR_PS8_Msk (0x01UL << PORT5_OMR_PS8_Pos) /*!< PORT5 OMR: PS8 Mask */
\r
12385 #define PORT5_OMR_PS9_Pos 9 /*!< PORT5 OMR: PS9 Position */
\r
12386 #define PORT5_OMR_PS9_Msk (0x01UL << PORT5_OMR_PS9_Pos) /*!< PORT5 OMR: PS9 Mask */
\r
12387 #define PORT5_OMR_PS10_Pos 10 /*!< PORT5 OMR: PS10 Position */
\r
12388 #define PORT5_OMR_PS10_Msk (0x01UL << PORT5_OMR_PS10_Pos) /*!< PORT5 OMR: PS10 Mask */
\r
12389 #define PORT5_OMR_PS11_Pos 11 /*!< PORT5 OMR: PS11 Position */
\r
12390 #define PORT5_OMR_PS11_Msk (0x01UL << PORT5_OMR_PS11_Pos) /*!< PORT5 OMR: PS11 Mask */
\r
12391 #define PORT5_OMR_PS12_Pos 12 /*!< PORT5 OMR: PS12 Position */
\r
12392 #define PORT5_OMR_PS12_Msk (0x01UL << PORT5_OMR_PS12_Pos) /*!< PORT5 OMR: PS12 Mask */
\r
12393 #define PORT5_OMR_PS13_Pos 13 /*!< PORT5 OMR: PS13 Position */
\r
12394 #define PORT5_OMR_PS13_Msk (0x01UL << PORT5_OMR_PS13_Pos) /*!< PORT5 OMR: PS13 Mask */
\r
12395 #define PORT5_OMR_PS14_Pos 14 /*!< PORT5 OMR: PS14 Position */
\r
12396 #define PORT5_OMR_PS14_Msk (0x01UL << PORT5_OMR_PS14_Pos) /*!< PORT5 OMR: PS14 Mask */
\r
12397 #define PORT5_OMR_PS15_Pos 15 /*!< PORT5 OMR: PS15 Position */
\r
12398 #define PORT5_OMR_PS15_Msk (0x01UL << PORT5_OMR_PS15_Pos) /*!< PORT5 OMR: PS15 Mask */
\r
12399 #define PORT5_OMR_PR0_Pos 16 /*!< PORT5 OMR: PR0 Position */
\r
12400 #define PORT5_OMR_PR0_Msk (0x01UL << PORT5_OMR_PR0_Pos) /*!< PORT5 OMR: PR0 Mask */
\r
12401 #define PORT5_OMR_PR1_Pos 17 /*!< PORT5 OMR: PR1 Position */
\r
12402 #define PORT5_OMR_PR1_Msk (0x01UL << PORT5_OMR_PR1_Pos) /*!< PORT5 OMR: PR1 Mask */
\r
12403 #define PORT5_OMR_PR2_Pos 18 /*!< PORT5 OMR: PR2 Position */
\r
12404 #define PORT5_OMR_PR2_Msk (0x01UL << PORT5_OMR_PR2_Pos) /*!< PORT5 OMR: PR2 Mask */
\r
12405 #define PORT5_OMR_PR3_Pos 19 /*!< PORT5 OMR: PR3 Position */
\r
12406 #define PORT5_OMR_PR3_Msk (0x01UL << PORT5_OMR_PR3_Pos) /*!< PORT5 OMR: PR3 Mask */
\r
12407 #define PORT5_OMR_PR4_Pos 20 /*!< PORT5 OMR: PR4 Position */
\r
12408 #define PORT5_OMR_PR4_Msk (0x01UL << PORT5_OMR_PR4_Pos) /*!< PORT5 OMR: PR4 Mask */
\r
12409 #define PORT5_OMR_PR5_Pos 21 /*!< PORT5 OMR: PR5 Position */
\r
12410 #define PORT5_OMR_PR5_Msk (0x01UL << PORT5_OMR_PR5_Pos) /*!< PORT5 OMR: PR5 Mask */
\r
12411 #define PORT5_OMR_PR6_Pos 22 /*!< PORT5 OMR: PR6 Position */
\r
12412 #define PORT5_OMR_PR6_Msk (0x01UL << PORT5_OMR_PR6_Pos) /*!< PORT5 OMR: PR6 Mask */
\r
12413 #define PORT5_OMR_PR7_Pos 23 /*!< PORT5 OMR: PR7 Position */
\r
12414 #define PORT5_OMR_PR7_Msk (0x01UL << PORT5_OMR_PR7_Pos) /*!< PORT5 OMR: PR7 Mask */
\r
12415 #define PORT5_OMR_PR8_Pos 24 /*!< PORT5 OMR: PR8 Position */
\r
12416 #define PORT5_OMR_PR8_Msk (0x01UL << PORT5_OMR_PR8_Pos) /*!< PORT5 OMR: PR8 Mask */
\r
12417 #define PORT5_OMR_PR9_Pos 25 /*!< PORT5 OMR: PR9 Position */
\r
12418 #define PORT5_OMR_PR9_Msk (0x01UL << PORT5_OMR_PR9_Pos) /*!< PORT5 OMR: PR9 Mask */
\r
12419 #define PORT5_OMR_PR10_Pos 26 /*!< PORT5 OMR: PR10 Position */
\r
12420 #define PORT5_OMR_PR10_Msk (0x01UL << PORT5_OMR_PR10_Pos) /*!< PORT5 OMR: PR10 Mask */
\r
12421 #define PORT5_OMR_PR11_Pos 27 /*!< PORT5 OMR: PR11 Position */
\r
12422 #define PORT5_OMR_PR11_Msk (0x01UL << PORT5_OMR_PR11_Pos) /*!< PORT5 OMR: PR11 Mask */
\r
12423 #define PORT5_OMR_PR12_Pos 28 /*!< PORT5 OMR: PR12 Position */
\r
12424 #define PORT5_OMR_PR12_Msk (0x01UL << PORT5_OMR_PR12_Pos) /*!< PORT5 OMR: PR12 Mask */
\r
12425 #define PORT5_OMR_PR13_Pos 29 /*!< PORT5 OMR: PR13 Position */
\r
12426 #define PORT5_OMR_PR13_Msk (0x01UL << PORT5_OMR_PR13_Pos) /*!< PORT5 OMR: PR13 Mask */
\r
12427 #define PORT5_OMR_PR14_Pos 30 /*!< PORT5 OMR: PR14 Position */
\r
12428 #define PORT5_OMR_PR14_Msk (0x01UL << PORT5_OMR_PR14_Pos) /*!< PORT5 OMR: PR14 Mask */
\r
12429 #define PORT5_OMR_PR15_Pos 31 /*!< PORT5 OMR: PR15 Position */
\r
12430 #define PORT5_OMR_PR15_Msk (0x01UL << PORT5_OMR_PR15_Pos) /*!< PORT5 OMR: PR15 Mask */
\r
12432 // --------------------------------------- PORT5_IOCR0 ------------------------------------------
\r
12433 #define PORT5_IOCR0_PC0_Pos 3 /*!< PORT5 IOCR0: PC0 Position */
\r
12434 #define PORT5_IOCR0_PC0_Msk (0x1fUL << PORT5_IOCR0_PC0_Pos) /*!< PORT5 IOCR0: PC0 Mask */
\r
12435 #define PORT5_IOCR0_PC1_Pos 11 /*!< PORT5 IOCR0: PC1 Position */
\r
12436 #define PORT5_IOCR0_PC1_Msk (0x1fUL << PORT5_IOCR0_PC1_Pos) /*!< PORT5 IOCR0: PC1 Mask */
\r
12437 #define PORT5_IOCR0_PC2_Pos 19 /*!< PORT5 IOCR0: PC2 Position */
\r
12438 #define PORT5_IOCR0_PC2_Msk (0x1fUL << PORT5_IOCR0_PC2_Pos) /*!< PORT5 IOCR0: PC2 Mask */
\r
12439 #define PORT5_IOCR0_PC3_Pos 27 /*!< PORT5 IOCR0: PC3 Position */
\r
12440 #define PORT5_IOCR0_PC3_Msk (0x1fUL << PORT5_IOCR0_PC3_Pos) /*!< PORT5 IOCR0: PC3 Mask */
\r
12442 // --------------------------------------- PORT5_IOCR4 ------------------------------------------
\r
12443 #define PORT5_IOCR4_PC4_Pos 3 /*!< PORT5 IOCR4: PC4 Position */
\r
12444 #define PORT5_IOCR4_PC4_Msk (0x1fUL << PORT5_IOCR4_PC4_Pos) /*!< PORT5 IOCR4: PC4 Mask */
\r
12445 #define PORT5_IOCR4_PC5_Pos 11 /*!< PORT5 IOCR4: PC5 Position */
\r
12446 #define PORT5_IOCR4_PC5_Msk (0x1fUL << PORT5_IOCR4_PC5_Pos) /*!< PORT5 IOCR4: PC5 Mask */
\r
12447 #define PORT5_IOCR4_PC6_Pos 19 /*!< PORT5 IOCR4: PC6 Position */
\r
12448 #define PORT5_IOCR4_PC6_Msk (0x1fUL << PORT5_IOCR4_PC6_Pos) /*!< PORT5 IOCR4: PC6 Mask */
\r
12449 #define PORT5_IOCR4_PC7_Pos 27 /*!< PORT5 IOCR4: PC7 Position */
\r
12450 #define PORT5_IOCR4_PC7_Msk (0x1fUL << PORT5_IOCR4_PC7_Pos) /*!< PORT5 IOCR4: PC7 Mask */
\r
12452 // --------------------------------------- PORT5_IOCR8 ------------------------------------------
\r
12453 #define PORT5_IOCR8_PC8_Pos 3 /*!< PORT5 IOCR8: PC8 Position */
\r
12454 #define PORT5_IOCR8_PC8_Msk (0x1fUL << PORT5_IOCR8_PC8_Pos) /*!< PORT5 IOCR8: PC8 Mask */
\r
12455 #define PORT5_IOCR8_PC9_Pos 11 /*!< PORT5 IOCR8: PC9 Position */
\r
12456 #define PORT5_IOCR8_PC9_Msk (0x1fUL << PORT5_IOCR8_PC9_Pos) /*!< PORT5 IOCR8: PC9 Mask */
\r
12457 #define PORT5_IOCR8_PC10_Pos 19 /*!< PORT5 IOCR8: PC10 Position */
\r
12458 #define PORT5_IOCR8_PC10_Msk (0x1fUL << PORT5_IOCR8_PC10_Pos) /*!< PORT5 IOCR8: PC10 Mask */
\r
12459 #define PORT5_IOCR8_PC11_Pos 27 /*!< PORT5 IOCR8: PC11 Position */
\r
12460 #define PORT5_IOCR8_PC11_Msk (0x1fUL << PORT5_IOCR8_PC11_Pos) /*!< PORT5 IOCR8: PC11 Mask */
\r
12462 // ---------------------------------------- PORT5_IN --------------------------------------------
\r
12463 #define PORT5_IN_P0_Pos 0 /*!< PORT5 IN: P0 Position */
\r
12464 #define PORT5_IN_P0_Msk (0x01UL << PORT5_IN_P0_Pos) /*!< PORT5 IN: P0 Mask */
\r
12465 #define PORT5_IN_P1_Pos 1 /*!< PORT5 IN: P1 Position */
\r
12466 #define PORT5_IN_P1_Msk (0x01UL << PORT5_IN_P1_Pos) /*!< PORT5 IN: P1 Mask */
\r
12467 #define PORT5_IN_P2_Pos 2 /*!< PORT5 IN: P2 Position */
\r
12468 #define PORT5_IN_P2_Msk (0x01UL << PORT5_IN_P2_Pos) /*!< PORT5 IN: P2 Mask */
\r
12469 #define PORT5_IN_P3_Pos 3 /*!< PORT5 IN: P3 Position */
\r
12470 #define PORT5_IN_P3_Msk (0x01UL << PORT5_IN_P3_Pos) /*!< PORT5 IN: P3 Mask */
\r
12471 #define PORT5_IN_P4_Pos 4 /*!< PORT5 IN: P4 Position */
\r
12472 #define PORT5_IN_P4_Msk (0x01UL << PORT5_IN_P4_Pos) /*!< PORT5 IN: P4 Mask */
\r
12473 #define PORT5_IN_P5_Pos 5 /*!< PORT5 IN: P5 Position */
\r
12474 #define PORT5_IN_P5_Msk (0x01UL << PORT5_IN_P5_Pos) /*!< PORT5 IN: P5 Mask */
\r
12475 #define PORT5_IN_P6_Pos 6 /*!< PORT5 IN: P6 Position */
\r
12476 #define PORT5_IN_P6_Msk (0x01UL << PORT5_IN_P6_Pos) /*!< PORT5 IN: P6 Mask */
\r
12477 #define PORT5_IN_P7_Pos 7 /*!< PORT5 IN: P7 Position */
\r
12478 #define PORT5_IN_P7_Msk (0x01UL << PORT5_IN_P7_Pos) /*!< PORT5 IN: P7 Mask */
\r
12479 #define PORT5_IN_P8_Pos 8 /*!< PORT5 IN: P8 Position */
\r
12480 #define PORT5_IN_P8_Msk (0x01UL << PORT5_IN_P8_Pos) /*!< PORT5 IN: P8 Mask */
\r
12481 #define PORT5_IN_P9_Pos 9 /*!< PORT5 IN: P9 Position */
\r
12482 #define PORT5_IN_P9_Msk (0x01UL << PORT5_IN_P9_Pos) /*!< PORT5 IN: P9 Mask */
\r
12483 #define PORT5_IN_P10_Pos 10 /*!< PORT5 IN: P10 Position */
\r
12484 #define PORT5_IN_P10_Msk (0x01UL << PORT5_IN_P10_Pos) /*!< PORT5 IN: P10 Mask */
\r
12485 #define PORT5_IN_P11_Pos 11 /*!< PORT5 IN: P11 Position */
\r
12486 #define PORT5_IN_P11_Msk (0x01UL << PORT5_IN_P11_Pos) /*!< PORT5 IN: P11 Mask */
\r
12487 #define PORT5_IN_P12_Pos 12 /*!< PORT5 IN: P12 Position */
\r
12488 #define PORT5_IN_P12_Msk (0x01UL << PORT5_IN_P12_Pos) /*!< PORT5 IN: P12 Mask */
\r
12489 #define PORT5_IN_P13_Pos 13 /*!< PORT5 IN: P13 Position */
\r
12490 #define PORT5_IN_P13_Msk (0x01UL << PORT5_IN_P13_Pos) /*!< PORT5 IN: P13 Mask */
\r
12491 #define PORT5_IN_P14_Pos 14 /*!< PORT5 IN: P14 Position */
\r
12492 #define PORT5_IN_P14_Msk (0x01UL << PORT5_IN_P14_Pos) /*!< PORT5 IN: P14 Mask */
\r
12493 #define PORT5_IN_P15_Pos 15 /*!< PORT5 IN: P15 Position */
\r
12494 #define PORT5_IN_P15_Msk (0x01UL << PORT5_IN_P15_Pos) /*!< PORT5 IN: P15 Mask */
\r
12496 // --------------------------------------- PORT5_PDR0 -------------------------------------------
\r
12497 #define PORT5_PDR0_PD0_Pos 0 /*!< PORT5 PDR0: PD0 Position */
\r
12498 #define PORT5_PDR0_PD0_Msk (0x07UL << PORT5_PDR0_PD0_Pos) /*!< PORT5 PDR0: PD0 Mask */
\r
12499 #define PORT5_PDR0_PD1_Pos 4 /*!< PORT5 PDR0: PD1 Position */
\r
12500 #define PORT5_PDR0_PD1_Msk (0x07UL << PORT5_PDR0_PD1_Pos) /*!< PORT5 PDR0: PD1 Mask */
\r
12501 #define PORT5_PDR0_PD2_Pos 8 /*!< PORT5 PDR0: PD2 Position */
\r
12502 #define PORT5_PDR0_PD2_Msk (0x07UL << PORT5_PDR0_PD2_Pos) /*!< PORT5 PDR0: PD2 Mask */
\r
12503 #define PORT5_PDR0_PD3_Pos 12 /*!< PORT5 PDR0: PD3 Position */
\r
12504 #define PORT5_PDR0_PD3_Msk (0x07UL << PORT5_PDR0_PD3_Pos) /*!< PORT5 PDR0: PD3 Mask */
\r
12505 #define PORT5_PDR0_PD4_Pos 16 /*!< PORT5 PDR0: PD4 Position */
\r
12506 #define PORT5_PDR0_PD4_Msk (0x07UL << PORT5_PDR0_PD4_Pos) /*!< PORT5 PDR0: PD4 Mask */
\r
12507 #define PORT5_PDR0_PD5_Pos 20 /*!< PORT5 PDR0: PD5 Position */
\r
12508 #define PORT5_PDR0_PD5_Msk (0x07UL << PORT5_PDR0_PD5_Pos) /*!< PORT5 PDR0: PD5 Mask */
\r
12509 #define PORT5_PDR0_PD6_Pos 24 /*!< PORT5 PDR0: PD6 Position */
\r
12510 #define PORT5_PDR0_PD6_Msk (0x07UL << PORT5_PDR0_PD6_Pos) /*!< PORT5 PDR0: PD6 Mask */
\r
12511 #define PORT5_PDR0_PD7_Pos 28 /*!< PORT5 PDR0: PD7 Position */
\r
12512 #define PORT5_PDR0_PD7_Msk (0x07UL << PORT5_PDR0_PD7_Pos) /*!< PORT5 PDR0: PD7 Mask */
\r
12514 // --------------------------------------- PORT5_PDR1 -------------------------------------------
\r
12515 #define PORT5_PDR1_PD8_Pos 0 /*!< PORT5 PDR1: PD8 Position */
\r
12516 #define PORT5_PDR1_PD8_Msk (0x07UL << PORT5_PDR1_PD8_Pos) /*!< PORT5 PDR1: PD8 Mask */
\r
12517 #define PORT5_PDR1_PD9_Pos 4 /*!< PORT5 PDR1: PD9 Position */
\r
12518 #define PORT5_PDR1_PD9_Msk (0x07UL << PORT5_PDR1_PD9_Pos) /*!< PORT5 PDR1: PD9 Mask */
\r
12519 #define PORT5_PDR1_PD10_Pos 8 /*!< PORT5 PDR1: PD10 Position */
\r
12520 #define PORT5_PDR1_PD10_Msk (0x07UL << PORT5_PDR1_PD10_Pos) /*!< PORT5 PDR1: PD10 Mask */
\r
12521 #define PORT5_PDR1_PD11_Pos 12 /*!< PORT5 PDR1: PD11 Position */
\r
12522 #define PORT5_PDR1_PD11_Msk (0x07UL << PORT5_PDR1_PD11_Pos) /*!< PORT5 PDR1: PD11 Mask */
\r
12523 #define PORT5_PDR1_PD12_Pos 16 /*!< PORT5 PDR1: PD12 Position */
\r
12524 #define PORT5_PDR1_PD12_Msk (0x07UL << PORT5_PDR1_PD12_Pos) /*!< PORT5 PDR1: PD12 Mask */
\r
12525 #define PORT5_PDR1_PD13_Pos 20 /*!< PORT5 PDR1: PD13 Position */
\r
12526 #define PORT5_PDR1_PD13_Msk (0x07UL << PORT5_PDR1_PD13_Pos) /*!< PORT5 PDR1: PD13 Mask */
\r
12527 #define PORT5_PDR1_PD14_Pos 24 /*!< PORT5 PDR1: PD14 Position */
\r
12528 #define PORT5_PDR1_PD14_Msk (0x07UL << PORT5_PDR1_PD14_Pos) /*!< PORT5 PDR1: PD14 Mask */
\r
12529 #define PORT5_PDR1_PD15_Pos 28 /*!< PORT5 PDR1: PD15 Position */
\r
12530 #define PORT5_PDR1_PD15_Msk (0x07UL << PORT5_PDR1_PD15_Pos) /*!< PORT5 PDR1: PD15 Mask */
\r
12532 // --------------------------------------- PORT5_PDISC ------------------------------------------
\r
12533 #define PORT5_PDISC_PDIS0_Pos 0 /*!< PORT5 PDISC: PDIS0 Position */
\r
12534 #define PORT5_PDISC_PDIS0_Msk (0x01UL << PORT5_PDISC_PDIS0_Pos) /*!< PORT5 PDISC: PDIS0 Mask */
\r
12535 #define PORT5_PDISC_PDIS1_Pos 1 /*!< PORT5 PDISC: PDIS1 Position */
\r
12536 #define PORT5_PDISC_PDIS1_Msk (0x01UL << PORT5_PDISC_PDIS1_Pos) /*!< PORT5 PDISC: PDIS1 Mask */
\r
12537 #define PORT5_PDISC_PDIS2_Pos 2 /*!< PORT5 PDISC: PDIS2 Position */
\r
12538 #define PORT5_PDISC_PDIS2_Msk (0x01UL << PORT5_PDISC_PDIS2_Pos) /*!< PORT5 PDISC: PDIS2 Mask */
\r
12539 #define PORT5_PDISC_PDIS3_Pos 3 /*!< PORT5 PDISC: PDIS3 Position */
\r
12540 #define PORT5_PDISC_PDIS3_Msk (0x01UL << PORT5_PDISC_PDIS3_Pos) /*!< PORT5 PDISC: PDIS3 Mask */
\r
12541 #define PORT5_PDISC_PDIS4_Pos 4 /*!< PORT5 PDISC: PDIS4 Position */
\r
12542 #define PORT5_PDISC_PDIS4_Msk (0x01UL << PORT5_PDISC_PDIS4_Pos) /*!< PORT5 PDISC: PDIS4 Mask */
\r
12543 #define PORT5_PDISC_PDIS5_Pos 5 /*!< PORT5 PDISC: PDIS5 Position */
\r
12544 #define PORT5_PDISC_PDIS5_Msk (0x01UL << PORT5_PDISC_PDIS5_Pos) /*!< PORT5 PDISC: PDIS5 Mask */
\r
12545 #define PORT5_PDISC_PDIS6_Pos 6 /*!< PORT5 PDISC: PDIS6 Position */
\r
12546 #define PORT5_PDISC_PDIS6_Msk (0x01UL << PORT5_PDISC_PDIS6_Pos) /*!< PORT5 PDISC: PDIS6 Mask */
\r
12547 #define PORT5_PDISC_PDIS7_Pos 7 /*!< PORT5 PDISC: PDIS7 Position */
\r
12548 #define PORT5_PDISC_PDIS7_Msk (0x01UL << PORT5_PDISC_PDIS7_Pos) /*!< PORT5 PDISC: PDIS7 Mask */
\r
12549 #define PORT5_PDISC_PDIS8_Pos 8 /*!< PORT5 PDISC: PDIS8 Position */
\r
12550 #define PORT5_PDISC_PDIS8_Msk (0x01UL << PORT5_PDISC_PDIS8_Pos) /*!< PORT5 PDISC: PDIS8 Mask */
\r
12551 #define PORT5_PDISC_PDIS9_Pos 9 /*!< PORT5 PDISC: PDIS9 Position */
\r
12552 #define PORT5_PDISC_PDIS9_Msk (0x01UL << PORT5_PDISC_PDIS9_Pos) /*!< PORT5 PDISC: PDIS9 Mask */
\r
12553 #define PORT5_PDISC_PDIS10_Pos 10 /*!< PORT5 PDISC: PDIS10 Position */
\r
12554 #define PORT5_PDISC_PDIS10_Msk (0x01UL << PORT5_PDISC_PDIS10_Pos) /*!< PORT5 PDISC: PDIS10 Mask */
\r
12555 #define PORT5_PDISC_PDIS11_Pos 11 /*!< PORT5 PDISC: PDIS11 Position */
\r
12556 #define PORT5_PDISC_PDIS11_Msk (0x01UL << PORT5_PDISC_PDIS11_Pos) /*!< PORT5 PDISC: PDIS11 Mask */
\r
12557 #define PORT5_PDISC_PDIS12_Pos 12 /*!< PORT5 PDISC: PDIS12 Position */
\r
12558 #define PORT5_PDISC_PDIS12_Msk (0x01UL << PORT5_PDISC_PDIS12_Pos) /*!< PORT5 PDISC: PDIS12 Mask */
\r
12559 #define PORT5_PDISC_PDIS13_Pos 13 /*!< PORT5 PDISC: PDIS13 Position */
\r
12560 #define PORT5_PDISC_PDIS13_Msk (0x01UL << PORT5_PDISC_PDIS13_Pos) /*!< PORT5 PDISC: PDIS13 Mask */
\r
12561 #define PORT5_PDISC_PDIS14_Pos 14 /*!< PORT5 PDISC: PDIS14 Position */
\r
12562 #define PORT5_PDISC_PDIS14_Msk (0x01UL << PORT5_PDISC_PDIS14_Pos) /*!< PORT5 PDISC: PDIS14 Mask */
\r
12563 #define PORT5_PDISC_PDIS15_Pos 15 /*!< PORT5 PDISC: PDIS15 Position */
\r
12564 #define PORT5_PDISC_PDIS15_Msk (0x01UL << PORT5_PDISC_PDIS15_Pos) /*!< PORT5 PDISC: PDIS15 Mask */
\r
12566 // ---------------------------------------- PORT5_PPS -------------------------------------------
\r
12567 #define PORT5_PPS_PPS0_Pos 0 /*!< PORT5 PPS: PPS0 Position */
\r
12568 #define PORT5_PPS_PPS0_Msk (0x01UL << PORT5_PPS_PPS0_Pos) /*!< PORT5 PPS: PPS0 Mask */
\r
12569 #define PORT5_PPS_PPS1_Pos 1 /*!< PORT5 PPS: PPS1 Position */
\r
12570 #define PORT5_PPS_PPS1_Msk (0x01UL << PORT5_PPS_PPS1_Pos) /*!< PORT5 PPS: PPS1 Mask */
\r
12571 #define PORT5_PPS_PPS2_Pos 2 /*!< PORT5 PPS: PPS2 Position */
\r
12572 #define PORT5_PPS_PPS2_Msk (0x01UL << PORT5_PPS_PPS2_Pos) /*!< PORT5 PPS: PPS2 Mask */
\r
12573 #define PORT5_PPS_PPS3_Pos 3 /*!< PORT5 PPS: PPS3 Position */
\r
12574 #define PORT5_PPS_PPS3_Msk (0x01UL << PORT5_PPS_PPS3_Pos) /*!< PORT5 PPS: PPS3 Mask */
\r
12575 #define PORT5_PPS_PPS4_Pos 4 /*!< PORT5 PPS: PPS4 Position */
\r
12576 #define PORT5_PPS_PPS4_Msk (0x01UL << PORT5_PPS_PPS4_Pos) /*!< PORT5 PPS: PPS4 Mask */
\r
12577 #define PORT5_PPS_PPS5_Pos 5 /*!< PORT5 PPS: PPS5 Position */
\r
12578 #define PORT5_PPS_PPS5_Msk (0x01UL << PORT5_PPS_PPS5_Pos) /*!< PORT5 PPS: PPS5 Mask */
\r
12579 #define PORT5_PPS_PPS6_Pos 6 /*!< PORT5 PPS: PPS6 Position */
\r
12580 #define PORT5_PPS_PPS6_Msk (0x01UL << PORT5_PPS_PPS6_Pos) /*!< PORT5 PPS: PPS6 Mask */
\r
12581 #define PORT5_PPS_PPS7_Pos 7 /*!< PORT5 PPS: PPS7 Position */
\r
12582 #define PORT5_PPS_PPS7_Msk (0x01UL << PORT5_PPS_PPS7_Pos) /*!< PORT5 PPS: PPS7 Mask */
\r
12583 #define PORT5_PPS_PPS8_Pos 8 /*!< PORT5 PPS: PPS8 Position */
\r
12584 #define PORT5_PPS_PPS8_Msk (0x01UL << PORT5_PPS_PPS8_Pos) /*!< PORT5 PPS: PPS8 Mask */
\r
12585 #define PORT5_PPS_PPS9_Pos 9 /*!< PORT5 PPS: PPS9 Position */
\r
12586 #define PORT5_PPS_PPS9_Msk (0x01UL << PORT5_PPS_PPS9_Pos) /*!< PORT5 PPS: PPS9 Mask */
\r
12587 #define PORT5_PPS_PPS10_Pos 10 /*!< PORT5 PPS: PPS10 Position */
\r
12588 #define PORT5_PPS_PPS10_Msk (0x01UL << PORT5_PPS_PPS10_Pos) /*!< PORT5 PPS: PPS10 Mask */
\r
12589 #define PORT5_PPS_PPS11_Pos 11 /*!< PORT5 PPS: PPS11 Position */
\r
12590 #define PORT5_PPS_PPS11_Msk (0x01UL << PORT5_PPS_PPS11_Pos) /*!< PORT5 PPS: PPS11 Mask */
\r
12591 #define PORT5_PPS_PPS12_Pos 12 /*!< PORT5 PPS: PPS12 Position */
\r
12592 #define PORT5_PPS_PPS12_Msk (0x01UL << PORT5_PPS_PPS12_Pos) /*!< PORT5 PPS: PPS12 Mask */
\r
12593 #define PORT5_PPS_PPS13_Pos 13 /*!< PORT5 PPS: PPS13 Position */
\r
12594 #define PORT5_PPS_PPS13_Msk (0x01UL << PORT5_PPS_PPS13_Pos) /*!< PORT5 PPS: PPS13 Mask */
\r
12595 #define PORT5_PPS_PPS14_Pos 14 /*!< PORT5 PPS: PPS14 Position */
\r
12596 #define PORT5_PPS_PPS14_Msk (0x01UL << PORT5_PPS_PPS14_Pos) /*!< PORT5 PPS: PPS14 Mask */
\r
12597 #define PORT5_PPS_PPS15_Pos 15 /*!< PORT5 PPS: PPS15 Position */
\r
12598 #define PORT5_PPS_PPS15_Msk (0x01UL << PORT5_PPS_PPS15_Pos) /*!< PORT5 PPS: PPS15 Mask */
\r
12600 // --------------------------------------- PORT5_HWSEL ------------------------------------------
\r
12601 #define PORT5_HWSEL_HW0_Pos 0 /*!< PORT5 HWSEL: HW0 Position */
\r
12602 #define PORT5_HWSEL_HW0_Msk (0x03UL << PORT5_HWSEL_HW0_Pos) /*!< PORT5 HWSEL: HW0 Mask */
\r
12603 #define PORT5_HWSEL_HW1_Pos 2 /*!< PORT5 HWSEL: HW1 Position */
\r
12604 #define PORT5_HWSEL_HW1_Msk (0x03UL << PORT5_HWSEL_HW1_Pos) /*!< PORT5 HWSEL: HW1 Mask */
\r
12605 #define PORT5_HWSEL_HW2_Pos 4 /*!< PORT5 HWSEL: HW2 Position */
\r
12606 #define PORT5_HWSEL_HW2_Msk (0x03UL << PORT5_HWSEL_HW2_Pos) /*!< PORT5 HWSEL: HW2 Mask */
\r
12607 #define PORT5_HWSEL_HW3_Pos 6 /*!< PORT5 HWSEL: HW3 Position */
\r
12608 #define PORT5_HWSEL_HW3_Msk (0x03UL << PORT5_HWSEL_HW3_Pos) /*!< PORT5 HWSEL: HW3 Mask */
\r
12609 #define PORT5_HWSEL_HW4_Pos 8 /*!< PORT5 HWSEL: HW4 Position */
\r
12610 #define PORT5_HWSEL_HW4_Msk (0x03UL << PORT5_HWSEL_HW4_Pos) /*!< PORT5 HWSEL: HW4 Mask */
\r
12611 #define PORT5_HWSEL_HW5_Pos 10 /*!< PORT5 HWSEL: HW5 Position */
\r
12612 #define PORT5_HWSEL_HW5_Msk (0x03UL << PORT5_HWSEL_HW5_Pos) /*!< PORT5 HWSEL: HW5 Mask */
\r
12613 #define PORT5_HWSEL_HW6_Pos 12 /*!< PORT5 HWSEL: HW6 Position */
\r
12614 #define PORT5_HWSEL_HW6_Msk (0x03UL << PORT5_HWSEL_HW6_Pos) /*!< PORT5 HWSEL: HW6 Mask */
\r
12615 #define PORT5_HWSEL_HW7_Pos 14 /*!< PORT5 HWSEL: HW7 Position */
\r
12616 #define PORT5_HWSEL_HW7_Msk (0x03UL << PORT5_HWSEL_HW7_Pos) /*!< PORT5 HWSEL: HW7 Mask */
\r
12617 #define PORT5_HWSEL_HW8_Pos 16 /*!< PORT5 HWSEL: HW8 Position */
\r
12618 #define PORT5_HWSEL_HW8_Msk (0x03UL << PORT5_HWSEL_HW8_Pos) /*!< PORT5 HWSEL: HW8 Mask */
\r
12619 #define PORT5_HWSEL_HW9_Pos 18 /*!< PORT5 HWSEL: HW9 Position */
\r
12620 #define PORT5_HWSEL_HW9_Msk (0x03UL << PORT5_HWSEL_HW9_Pos) /*!< PORT5 HWSEL: HW9 Mask */
\r
12621 #define PORT5_HWSEL_HW10_Pos 20 /*!< PORT5 HWSEL: HW10 Position */
\r
12622 #define PORT5_HWSEL_HW10_Msk (0x03UL << PORT5_HWSEL_HW10_Pos) /*!< PORT5 HWSEL: HW10 Mask */
\r
12623 #define PORT5_HWSEL_HW11_Pos 22 /*!< PORT5 HWSEL: HW11 Position */
\r
12624 #define PORT5_HWSEL_HW11_Msk (0x03UL << PORT5_HWSEL_HW11_Pos) /*!< PORT5 HWSEL: HW11 Mask */
\r
12625 #define PORT5_HWSEL_HW12_Pos 24 /*!< PORT5 HWSEL: HW12 Position */
\r
12626 #define PORT5_HWSEL_HW12_Msk (0x03UL << PORT5_HWSEL_HW12_Pos) /*!< PORT5 HWSEL: HW12 Mask */
\r
12627 #define PORT5_HWSEL_HW13_Pos 26 /*!< PORT5 HWSEL: HW13 Position */
\r
12628 #define PORT5_HWSEL_HW13_Msk (0x03UL << PORT5_HWSEL_HW13_Pos) /*!< PORT5 HWSEL: HW13 Mask */
\r
12629 #define PORT5_HWSEL_HW14_Pos 28 /*!< PORT5 HWSEL: HW14 Position */
\r
12630 #define PORT5_HWSEL_HW14_Msk (0x03UL << PORT5_HWSEL_HW14_Pos) /*!< PORT5 HWSEL: HW14 Mask */
\r
12631 #define PORT5_HWSEL_HW15_Pos 30 /*!< PORT5 HWSEL: HW15 Position */
\r
12632 #define PORT5_HWSEL_HW15_Msk (0x03UL << PORT5_HWSEL_HW15_Pos) /*!< PORT5 HWSEL: HW15 Mask */
\r
12635 // ------------------------------------------------------------------------------------------------
\r
12636 // ----- PORT6 Position & Mask -----
\r
12637 // ------------------------------------------------------------------------------------------------
\r
12640 // ---------------------------------------- PORT6_OUT -------------------------------------------
\r
12641 #define PORT6_OUT_P0_Pos 0 /*!< PORT6 OUT: P0 Position */
\r
12642 #define PORT6_OUT_P0_Msk (0x01UL << PORT6_OUT_P0_Pos) /*!< PORT6 OUT: P0 Mask */
\r
12643 #define PORT6_OUT_P1_Pos 1 /*!< PORT6 OUT: P1 Position */
\r
12644 #define PORT6_OUT_P1_Msk (0x01UL << PORT6_OUT_P1_Pos) /*!< PORT6 OUT: P1 Mask */
\r
12645 #define PORT6_OUT_P2_Pos 2 /*!< PORT6 OUT: P2 Position */
\r
12646 #define PORT6_OUT_P2_Msk (0x01UL << PORT6_OUT_P2_Pos) /*!< PORT6 OUT: P2 Mask */
\r
12647 #define PORT6_OUT_P3_Pos 3 /*!< PORT6 OUT: P3 Position */
\r
12648 #define PORT6_OUT_P3_Msk (0x01UL << PORT6_OUT_P3_Pos) /*!< PORT6 OUT: P3 Mask */
\r
12649 #define PORT6_OUT_P4_Pos 4 /*!< PORT6 OUT: P4 Position */
\r
12650 #define PORT6_OUT_P4_Msk (0x01UL << PORT6_OUT_P4_Pos) /*!< PORT6 OUT: P4 Mask */
\r
12651 #define PORT6_OUT_P5_Pos 5 /*!< PORT6 OUT: P5 Position */
\r
12652 #define PORT6_OUT_P5_Msk (0x01UL << PORT6_OUT_P5_Pos) /*!< PORT6 OUT: P5 Mask */
\r
12653 #define PORT6_OUT_P6_Pos 6 /*!< PORT6 OUT: P6 Position */
\r
12654 #define PORT6_OUT_P6_Msk (0x01UL << PORT6_OUT_P6_Pos) /*!< PORT6 OUT: P6 Mask */
\r
12655 #define PORT6_OUT_P7_Pos 7 /*!< PORT6 OUT: P7 Position */
\r
12656 #define PORT6_OUT_P7_Msk (0x01UL << PORT6_OUT_P7_Pos) /*!< PORT6 OUT: P7 Mask */
\r
12657 #define PORT6_OUT_P8_Pos 8 /*!< PORT6 OUT: P8 Position */
\r
12658 #define PORT6_OUT_P8_Msk (0x01UL << PORT6_OUT_P8_Pos) /*!< PORT6 OUT: P8 Mask */
\r
12659 #define PORT6_OUT_P9_Pos 9 /*!< PORT6 OUT: P9 Position */
\r
12660 #define PORT6_OUT_P9_Msk (0x01UL << PORT6_OUT_P9_Pos) /*!< PORT6 OUT: P9 Mask */
\r
12661 #define PORT6_OUT_P10_Pos 10 /*!< PORT6 OUT: P10 Position */
\r
12662 #define PORT6_OUT_P10_Msk (0x01UL << PORT6_OUT_P10_Pos) /*!< PORT6 OUT: P10 Mask */
\r
12663 #define PORT6_OUT_P11_Pos 11 /*!< PORT6 OUT: P11 Position */
\r
12664 #define PORT6_OUT_P11_Msk (0x01UL << PORT6_OUT_P11_Pos) /*!< PORT6 OUT: P11 Mask */
\r
12665 #define PORT6_OUT_P12_Pos 12 /*!< PORT6 OUT: P12 Position */
\r
12666 #define PORT6_OUT_P12_Msk (0x01UL << PORT6_OUT_P12_Pos) /*!< PORT6 OUT: P12 Mask */
\r
12667 #define PORT6_OUT_P13_Pos 13 /*!< PORT6 OUT: P13 Position */
\r
12668 #define PORT6_OUT_P13_Msk (0x01UL << PORT6_OUT_P13_Pos) /*!< PORT6 OUT: P13 Mask */
\r
12669 #define PORT6_OUT_P14_Pos 14 /*!< PORT6 OUT: P14 Position */
\r
12670 #define PORT6_OUT_P14_Msk (0x01UL << PORT6_OUT_P14_Pos) /*!< PORT6 OUT: P14 Mask */
\r
12671 #define PORT6_OUT_P15_Pos 15 /*!< PORT6 OUT: P15 Position */
\r
12672 #define PORT6_OUT_P15_Msk (0x01UL << PORT6_OUT_P15_Pos) /*!< PORT6 OUT: P15 Mask */
\r
12674 // ---------------------------------------- PORT6_OMR -------------------------------------------
\r
12675 #define PORT6_OMR_PS0_Pos 0 /*!< PORT6 OMR: PS0 Position */
\r
12676 #define PORT6_OMR_PS0_Msk (0x01UL << PORT6_OMR_PS0_Pos) /*!< PORT6 OMR: PS0 Mask */
\r
12677 #define PORT6_OMR_PS1_Pos 1 /*!< PORT6 OMR: PS1 Position */
\r
12678 #define PORT6_OMR_PS1_Msk (0x01UL << PORT6_OMR_PS1_Pos) /*!< PORT6 OMR: PS1 Mask */
\r
12679 #define PORT6_OMR_PS2_Pos 2 /*!< PORT6 OMR: PS2 Position */
\r
12680 #define PORT6_OMR_PS2_Msk (0x01UL << PORT6_OMR_PS2_Pos) /*!< PORT6 OMR: PS2 Mask */
\r
12681 #define PORT6_OMR_PS3_Pos 3 /*!< PORT6 OMR: PS3 Position */
\r
12682 #define PORT6_OMR_PS3_Msk (0x01UL << PORT6_OMR_PS3_Pos) /*!< PORT6 OMR: PS3 Mask */
\r
12683 #define PORT6_OMR_PS4_Pos 4 /*!< PORT6 OMR: PS4 Position */
\r
12684 #define PORT6_OMR_PS4_Msk (0x01UL << PORT6_OMR_PS4_Pos) /*!< PORT6 OMR: PS4 Mask */
\r
12685 #define PORT6_OMR_PS5_Pos 5 /*!< PORT6 OMR: PS5 Position */
\r
12686 #define PORT6_OMR_PS5_Msk (0x01UL << PORT6_OMR_PS5_Pos) /*!< PORT6 OMR: PS5 Mask */
\r
12687 #define PORT6_OMR_PS6_Pos 6 /*!< PORT6 OMR: PS6 Position */
\r
12688 #define PORT6_OMR_PS6_Msk (0x01UL << PORT6_OMR_PS6_Pos) /*!< PORT6 OMR: PS6 Mask */
\r
12689 #define PORT6_OMR_PS7_Pos 7 /*!< PORT6 OMR: PS7 Position */
\r
12690 #define PORT6_OMR_PS7_Msk (0x01UL << PORT6_OMR_PS7_Pos) /*!< PORT6 OMR: PS7 Mask */
\r
12691 #define PORT6_OMR_PS8_Pos 8 /*!< PORT6 OMR: PS8 Position */
\r
12692 #define PORT6_OMR_PS8_Msk (0x01UL << PORT6_OMR_PS8_Pos) /*!< PORT6 OMR: PS8 Mask */
\r
12693 #define PORT6_OMR_PS9_Pos 9 /*!< PORT6 OMR: PS9 Position */
\r
12694 #define PORT6_OMR_PS9_Msk (0x01UL << PORT6_OMR_PS9_Pos) /*!< PORT6 OMR: PS9 Mask */
\r
12695 #define PORT6_OMR_PS10_Pos 10 /*!< PORT6 OMR: PS10 Position */
\r
12696 #define PORT6_OMR_PS10_Msk (0x01UL << PORT6_OMR_PS10_Pos) /*!< PORT6 OMR: PS10 Mask */
\r
12697 #define PORT6_OMR_PS11_Pos 11 /*!< PORT6 OMR: PS11 Position */
\r
12698 #define PORT6_OMR_PS11_Msk (0x01UL << PORT6_OMR_PS11_Pos) /*!< PORT6 OMR: PS11 Mask */
\r
12699 #define PORT6_OMR_PS12_Pos 12 /*!< PORT6 OMR: PS12 Position */
\r
12700 #define PORT6_OMR_PS12_Msk (0x01UL << PORT6_OMR_PS12_Pos) /*!< PORT6 OMR: PS12 Mask */
\r
12701 #define PORT6_OMR_PS13_Pos 13 /*!< PORT6 OMR: PS13 Position */
\r
12702 #define PORT6_OMR_PS13_Msk (0x01UL << PORT6_OMR_PS13_Pos) /*!< PORT6 OMR: PS13 Mask */
\r
12703 #define PORT6_OMR_PS14_Pos 14 /*!< PORT6 OMR: PS14 Position */
\r
12704 #define PORT6_OMR_PS14_Msk (0x01UL << PORT6_OMR_PS14_Pos) /*!< PORT6 OMR: PS14 Mask */
\r
12705 #define PORT6_OMR_PS15_Pos 15 /*!< PORT6 OMR: PS15 Position */
\r
12706 #define PORT6_OMR_PS15_Msk (0x01UL << PORT6_OMR_PS15_Pos) /*!< PORT6 OMR: PS15 Mask */
\r
12707 #define PORT6_OMR_PR0_Pos 16 /*!< PORT6 OMR: PR0 Position */
\r
12708 #define PORT6_OMR_PR0_Msk (0x01UL << PORT6_OMR_PR0_Pos) /*!< PORT6 OMR: PR0 Mask */
\r
12709 #define PORT6_OMR_PR1_Pos 17 /*!< PORT6 OMR: PR1 Position */
\r
12710 #define PORT6_OMR_PR1_Msk (0x01UL << PORT6_OMR_PR1_Pos) /*!< PORT6 OMR: PR1 Mask */
\r
12711 #define PORT6_OMR_PR2_Pos 18 /*!< PORT6 OMR: PR2 Position */
\r
12712 #define PORT6_OMR_PR2_Msk (0x01UL << PORT6_OMR_PR2_Pos) /*!< PORT6 OMR: PR2 Mask */
\r
12713 #define PORT6_OMR_PR3_Pos 19 /*!< PORT6 OMR: PR3 Position */
\r
12714 #define PORT6_OMR_PR3_Msk (0x01UL << PORT6_OMR_PR3_Pos) /*!< PORT6 OMR: PR3 Mask */
\r
12715 #define PORT6_OMR_PR4_Pos 20 /*!< PORT6 OMR: PR4 Position */
\r
12716 #define PORT6_OMR_PR4_Msk (0x01UL << PORT6_OMR_PR4_Pos) /*!< PORT6 OMR: PR4 Mask */
\r
12717 #define PORT6_OMR_PR5_Pos 21 /*!< PORT6 OMR: PR5 Position */
\r
12718 #define PORT6_OMR_PR5_Msk (0x01UL << PORT6_OMR_PR5_Pos) /*!< PORT6 OMR: PR5 Mask */
\r
12719 #define PORT6_OMR_PR6_Pos 22 /*!< PORT6 OMR: PR6 Position */
\r
12720 #define PORT6_OMR_PR6_Msk (0x01UL << PORT6_OMR_PR6_Pos) /*!< PORT6 OMR: PR6 Mask */
\r
12721 #define PORT6_OMR_PR7_Pos 23 /*!< PORT6 OMR: PR7 Position */
\r
12722 #define PORT6_OMR_PR7_Msk (0x01UL << PORT6_OMR_PR7_Pos) /*!< PORT6 OMR: PR7 Mask */
\r
12723 #define PORT6_OMR_PR8_Pos 24 /*!< PORT6 OMR: PR8 Position */
\r
12724 #define PORT6_OMR_PR8_Msk (0x01UL << PORT6_OMR_PR8_Pos) /*!< PORT6 OMR: PR8 Mask */
\r
12725 #define PORT6_OMR_PR9_Pos 25 /*!< PORT6 OMR: PR9 Position */
\r
12726 #define PORT6_OMR_PR9_Msk (0x01UL << PORT6_OMR_PR9_Pos) /*!< PORT6 OMR: PR9 Mask */
\r
12727 #define PORT6_OMR_PR10_Pos 26 /*!< PORT6 OMR: PR10 Position */
\r
12728 #define PORT6_OMR_PR10_Msk (0x01UL << PORT6_OMR_PR10_Pos) /*!< PORT6 OMR: PR10 Mask */
\r
12729 #define PORT6_OMR_PR11_Pos 27 /*!< PORT6 OMR: PR11 Position */
\r
12730 #define PORT6_OMR_PR11_Msk (0x01UL << PORT6_OMR_PR11_Pos) /*!< PORT6 OMR: PR11 Mask */
\r
12731 #define PORT6_OMR_PR12_Pos 28 /*!< PORT6 OMR: PR12 Position */
\r
12732 #define PORT6_OMR_PR12_Msk (0x01UL << PORT6_OMR_PR12_Pos) /*!< PORT6 OMR: PR12 Mask */
\r
12733 #define PORT6_OMR_PR13_Pos 29 /*!< PORT6 OMR: PR13 Position */
\r
12734 #define PORT6_OMR_PR13_Msk (0x01UL << PORT6_OMR_PR13_Pos) /*!< PORT6 OMR: PR13 Mask */
\r
12735 #define PORT6_OMR_PR14_Pos 30 /*!< PORT6 OMR: PR14 Position */
\r
12736 #define PORT6_OMR_PR14_Msk (0x01UL << PORT6_OMR_PR14_Pos) /*!< PORT6 OMR: PR14 Mask */
\r
12737 #define PORT6_OMR_PR15_Pos 31 /*!< PORT6 OMR: PR15 Position */
\r
12738 #define PORT6_OMR_PR15_Msk (0x01UL << PORT6_OMR_PR15_Pos) /*!< PORT6 OMR: PR15 Mask */
\r
12740 // --------------------------------------- PORT6_IOCR0 ------------------------------------------
\r
12741 #define PORT6_IOCR0_PC0_Pos 3 /*!< PORT6 IOCR0: PC0 Position */
\r
12742 #define PORT6_IOCR0_PC0_Msk (0x1fUL << PORT6_IOCR0_PC0_Pos) /*!< PORT6 IOCR0: PC0 Mask */
\r
12743 #define PORT6_IOCR0_PC1_Pos 11 /*!< PORT6 IOCR0: PC1 Position */
\r
12744 #define PORT6_IOCR0_PC1_Msk (0x1fUL << PORT6_IOCR0_PC1_Pos) /*!< PORT6 IOCR0: PC1 Mask */
\r
12745 #define PORT6_IOCR0_PC2_Pos 19 /*!< PORT6 IOCR0: PC2 Position */
\r
12746 #define PORT6_IOCR0_PC2_Msk (0x1fUL << PORT6_IOCR0_PC2_Pos) /*!< PORT6 IOCR0: PC2 Mask */
\r
12747 #define PORT6_IOCR0_PC3_Pos 27 /*!< PORT6 IOCR0: PC3 Position */
\r
12748 #define PORT6_IOCR0_PC3_Msk (0x1fUL << PORT6_IOCR0_PC3_Pos) /*!< PORT6 IOCR0: PC3 Mask */
\r
12750 // --------------------------------------- PORT6_IOCR4 ------------------------------------------
\r
12751 #define PORT6_IOCR4_PC4_Pos 3 /*!< PORT6 IOCR4: PC4 Position */
\r
12752 #define PORT6_IOCR4_PC4_Msk (0x1fUL << PORT6_IOCR4_PC4_Pos) /*!< PORT6 IOCR4: PC4 Mask */
\r
12753 #define PORT6_IOCR4_PC5_Pos 11 /*!< PORT6 IOCR4: PC5 Position */
\r
12754 #define PORT6_IOCR4_PC5_Msk (0x1fUL << PORT6_IOCR4_PC5_Pos) /*!< PORT6 IOCR4: PC5 Mask */
\r
12755 #define PORT6_IOCR4_PC6_Pos 19 /*!< PORT6 IOCR4: PC6 Position */
\r
12756 #define PORT6_IOCR4_PC6_Msk (0x1fUL << PORT6_IOCR4_PC6_Pos) /*!< PORT6 IOCR4: PC6 Mask */
\r
12757 #define PORT6_IOCR4_PC7_Pos 27 /*!< PORT6 IOCR4: PC7 Position */
\r
12758 #define PORT6_IOCR4_PC7_Msk (0x1fUL << PORT6_IOCR4_PC7_Pos) /*!< PORT6 IOCR4: PC7 Mask */
\r
12760 // ---------------------------------------- PORT6_IN --------------------------------------------
\r
12761 #define PORT6_IN_P0_Pos 0 /*!< PORT6 IN: P0 Position */
\r
12762 #define PORT6_IN_P0_Msk (0x01UL << PORT6_IN_P0_Pos) /*!< PORT6 IN: P0 Mask */
\r
12763 #define PORT6_IN_P1_Pos 1 /*!< PORT6 IN: P1 Position */
\r
12764 #define PORT6_IN_P1_Msk (0x01UL << PORT6_IN_P1_Pos) /*!< PORT6 IN: P1 Mask */
\r
12765 #define PORT6_IN_P2_Pos 2 /*!< PORT6 IN: P2 Position */
\r
12766 #define PORT6_IN_P2_Msk (0x01UL << PORT6_IN_P2_Pos) /*!< PORT6 IN: P2 Mask */
\r
12767 #define PORT6_IN_P3_Pos 3 /*!< PORT6 IN: P3 Position */
\r
12768 #define PORT6_IN_P3_Msk (0x01UL << PORT6_IN_P3_Pos) /*!< PORT6 IN: P3 Mask */
\r
12769 #define PORT6_IN_P4_Pos 4 /*!< PORT6 IN: P4 Position */
\r
12770 #define PORT6_IN_P4_Msk (0x01UL << PORT6_IN_P4_Pos) /*!< PORT6 IN: P4 Mask */
\r
12771 #define PORT6_IN_P5_Pos 5 /*!< PORT6 IN: P5 Position */
\r
12772 #define PORT6_IN_P5_Msk (0x01UL << PORT6_IN_P5_Pos) /*!< PORT6 IN: P5 Mask */
\r
12773 #define PORT6_IN_P6_Pos 6 /*!< PORT6 IN: P6 Position */
\r
12774 #define PORT6_IN_P6_Msk (0x01UL << PORT6_IN_P6_Pos) /*!< PORT6 IN: P6 Mask */
\r
12775 #define PORT6_IN_P7_Pos 7 /*!< PORT6 IN: P7 Position */
\r
12776 #define PORT6_IN_P7_Msk (0x01UL << PORT6_IN_P7_Pos) /*!< PORT6 IN: P7 Mask */
\r
12777 #define PORT6_IN_P8_Pos 8 /*!< PORT6 IN: P8 Position */
\r
12778 #define PORT6_IN_P8_Msk (0x01UL << PORT6_IN_P8_Pos) /*!< PORT6 IN: P8 Mask */
\r
12779 #define PORT6_IN_P9_Pos 9 /*!< PORT6 IN: P9 Position */
\r
12780 #define PORT6_IN_P9_Msk (0x01UL << PORT6_IN_P9_Pos) /*!< PORT6 IN: P9 Mask */
\r
12781 #define PORT6_IN_P10_Pos 10 /*!< PORT6 IN: P10 Position */
\r
12782 #define PORT6_IN_P10_Msk (0x01UL << PORT6_IN_P10_Pos) /*!< PORT6 IN: P10 Mask */
\r
12783 #define PORT6_IN_P11_Pos 11 /*!< PORT6 IN: P11 Position */
\r
12784 #define PORT6_IN_P11_Msk (0x01UL << PORT6_IN_P11_Pos) /*!< PORT6 IN: P11 Mask */
\r
12785 #define PORT6_IN_P12_Pos 12 /*!< PORT6 IN: P12 Position */
\r
12786 #define PORT6_IN_P12_Msk (0x01UL << PORT6_IN_P12_Pos) /*!< PORT6 IN: P12 Mask */
\r
12787 #define PORT6_IN_P13_Pos 13 /*!< PORT6 IN: P13 Position */
\r
12788 #define PORT6_IN_P13_Msk (0x01UL << PORT6_IN_P13_Pos) /*!< PORT6 IN: P13 Mask */
\r
12789 #define PORT6_IN_P14_Pos 14 /*!< PORT6 IN: P14 Position */
\r
12790 #define PORT6_IN_P14_Msk (0x01UL << PORT6_IN_P14_Pos) /*!< PORT6 IN: P14 Mask */
\r
12791 #define PORT6_IN_P15_Pos 15 /*!< PORT6 IN: P15 Position */
\r
12792 #define PORT6_IN_P15_Msk (0x01UL << PORT6_IN_P15_Pos) /*!< PORT6 IN: P15 Mask */
\r
12794 // --------------------------------------- PORT6_PDR0 -------------------------------------------
\r
12795 #define PORT6_PDR0_PD0_Pos 0 /*!< PORT6 PDR0: PD0 Position */
\r
12796 #define PORT6_PDR0_PD0_Msk (0x07UL << PORT6_PDR0_PD0_Pos) /*!< PORT6 PDR0: PD0 Mask */
\r
12797 #define PORT6_PDR0_PD1_Pos 4 /*!< PORT6 PDR0: PD1 Position */
\r
12798 #define PORT6_PDR0_PD1_Msk (0x07UL << PORT6_PDR0_PD1_Pos) /*!< PORT6 PDR0: PD1 Mask */
\r
12799 #define PORT6_PDR0_PD2_Pos 8 /*!< PORT6 PDR0: PD2 Position */
\r
12800 #define PORT6_PDR0_PD2_Msk (0x07UL << PORT6_PDR0_PD2_Pos) /*!< PORT6 PDR0: PD2 Mask */
\r
12801 #define PORT6_PDR0_PD3_Pos 12 /*!< PORT6 PDR0: PD3 Position */
\r
12802 #define PORT6_PDR0_PD3_Msk (0x07UL << PORT6_PDR0_PD3_Pos) /*!< PORT6 PDR0: PD3 Mask */
\r
12803 #define PORT6_PDR0_PD4_Pos 16 /*!< PORT6 PDR0: PD4 Position */
\r
12804 #define PORT6_PDR0_PD4_Msk (0x07UL << PORT6_PDR0_PD4_Pos) /*!< PORT6 PDR0: PD4 Mask */
\r
12805 #define PORT6_PDR0_PD5_Pos 20 /*!< PORT6 PDR0: PD5 Position */
\r
12806 #define PORT6_PDR0_PD5_Msk (0x07UL << PORT6_PDR0_PD5_Pos) /*!< PORT6 PDR0: PD5 Mask */
\r
12807 #define PORT6_PDR0_PD6_Pos 24 /*!< PORT6 PDR0: PD6 Position */
\r
12808 #define PORT6_PDR0_PD6_Msk (0x07UL << PORT6_PDR0_PD6_Pos) /*!< PORT6 PDR0: PD6 Mask */
\r
12809 #define PORT6_PDR0_PD7_Pos 28 /*!< PORT6 PDR0: PD7 Position */
\r
12810 #define PORT6_PDR0_PD7_Msk (0x07UL << PORT6_PDR0_PD7_Pos) /*!< PORT6 PDR0: PD7 Mask */
\r
12812 // --------------------------------------- PORT6_PDISC ------------------------------------------
\r
12813 #define PORT6_PDISC_PDIS0_Pos 0 /*!< PORT6 PDISC: PDIS0 Position */
\r
12814 #define PORT6_PDISC_PDIS0_Msk (0x01UL << PORT6_PDISC_PDIS0_Pos) /*!< PORT6 PDISC: PDIS0 Mask */
\r
12815 #define PORT6_PDISC_PDIS1_Pos 1 /*!< PORT6 PDISC: PDIS1 Position */
\r
12816 #define PORT6_PDISC_PDIS1_Msk (0x01UL << PORT6_PDISC_PDIS1_Pos) /*!< PORT6 PDISC: PDIS1 Mask */
\r
12817 #define PORT6_PDISC_PDIS2_Pos 2 /*!< PORT6 PDISC: PDIS2 Position */
\r
12818 #define PORT6_PDISC_PDIS2_Msk (0x01UL << PORT6_PDISC_PDIS2_Pos) /*!< PORT6 PDISC: PDIS2 Mask */
\r
12819 #define PORT6_PDISC_PDIS3_Pos 3 /*!< PORT6 PDISC: PDIS3 Position */
\r
12820 #define PORT6_PDISC_PDIS3_Msk (0x01UL << PORT6_PDISC_PDIS3_Pos) /*!< PORT6 PDISC: PDIS3 Mask */
\r
12821 #define PORT6_PDISC_PDIS4_Pos 4 /*!< PORT6 PDISC: PDIS4 Position */
\r
12822 #define PORT6_PDISC_PDIS4_Msk (0x01UL << PORT6_PDISC_PDIS4_Pos) /*!< PORT6 PDISC: PDIS4 Mask */
\r
12823 #define PORT6_PDISC_PDIS5_Pos 5 /*!< PORT6 PDISC: PDIS5 Position */
\r
12824 #define PORT6_PDISC_PDIS5_Msk (0x01UL << PORT6_PDISC_PDIS5_Pos) /*!< PORT6 PDISC: PDIS5 Mask */
\r
12825 #define PORT6_PDISC_PDIS6_Pos 6 /*!< PORT6 PDISC: PDIS6 Position */
\r
12826 #define PORT6_PDISC_PDIS6_Msk (0x01UL << PORT6_PDISC_PDIS6_Pos) /*!< PORT6 PDISC: PDIS6 Mask */
\r
12827 #define PORT6_PDISC_PDIS7_Pos 7 /*!< PORT6 PDISC: PDIS7 Position */
\r
12828 #define PORT6_PDISC_PDIS7_Msk (0x01UL << PORT6_PDISC_PDIS7_Pos) /*!< PORT6 PDISC: PDIS7 Mask */
\r
12829 #define PORT6_PDISC_PDIS8_Pos 8 /*!< PORT6 PDISC: PDIS8 Position */
\r
12830 #define PORT6_PDISC_PDIS8_Msk (0x01UL << PORT6_PDISC_PDIS8_Pos) /*!< PORT6 PDISC: PDIS8 Mask */
\r
12831 #define PORT6_PDISC_PDIS9_Pos 9 /*!< PORT6 PDISC: PDIS9 Position */
\r
12832 #define PORT6_PDISC_PDIS9_Msk (0x01UL << PORT6_PDISC_PDIS9_Pos) /*!< PORT6 PDISC: PDIS9 Mask */
\r
12833 #define PORT6_PDISC_PDIS10_Pos 10 /*!< PORT6 PDISC: PDIS10 Position */
\r
12834 #define PORT6_PDISC_PDIS10_Msk (0x01UL << PORT6_PDISC_PDIS10_Pos) /*!< PORT6 PDISC: PDIS10 Mask */
\r
12835 #define PORT6_PDISC_PDIS11_Pos 11 /*!< PORT6 PDISC: PDIS11 Position */
\r
12836 #define PORT6_PDISC_PDIS11_Msk (0x01UL << PORT6_PDISC_PDIS11_Pos) /*!< PORT6 PDISC: PDIS11 Mask */
\r
12837 #define PORT6_PDISC_PDIS12_Pos 12 /*!< PORT6 PDISC: PDIS12 Position */
\r
12838 #define PORT6_PDISC_PDIS12_Msk (0x01UL << PORT6_PDISC_PDIS12_Pos) /*!< PORT6 PDISC: PDIS12 Mask */
\r
12839 #define PORT6_PDISC_PDIS13_Pos 13 /*!< PORT6 PDISC: PDIS13 Position */
\r
12840 #define PORT6_PDISC_PDIS13_Msk (0x01UL << PORT6_PDISC_PDIS13_Pos) /*!< PORT6 PDISC: PDIS13 Mask */
\r
12841 #define PORT6_PDISC_PDIS14_Pos 14 /*!< PORT6 PDISC: PDIS14 Position */
\r
12842 #define PORT6_PDISC_PDIS14_Msk (0x01UL << PORT6_PDISC_PDIS14_Pos) /*!< PORT6 PDISC: PDIS14 Mask */
\r
12843 #define PORT6_PDISC_PDIS15_Pos 15 /*!< PORT6 PDISC: PDIS15 Position */
\r
12844 #define PORT6_PDISC_PDIS15_Msk (0x01UL << PORT6_PDISC_PDIS15_Pos) /*!< PORT6 PDISC: PDIS15 Mask */
\r
12846 // ---------------------------------------- PORT6_PPS -------------------------------------------
\r
12847 #define PORT6_PPS_PPS0_Pos 0 /*!< PORT6 PPS: PPS0 Position */
\r
12848 #define PORT6_PPS_PPS0_Msk (0x01UL << PORT6_PPS_PPS0_Pos) /*!< PORT6 PPS: PPS0 Mask */
\r
12849 #define PORT6_PPS_PPS1_Pos 1 /*!< PORT6 PPS: PPS1 Position */
\r
12850 #define PORT6_PPS_PPS1_Msk (0x01UL << PORT6_PPS_PPS1_Pos) /*!< PORT6 PPS: PPS1 Mask */
\r
12851 #define PORT6_PPS_PPS2_Pos 2 /*!< PORT6 PPS: PPS2 Position */
\r
12852 #define PORT6_PPS_PPS2_Msk (0x01UL << PORT6_PPS_PPS2_Pos) /*!< PORT6 PPS: PPS2 Mask */
\r
12853 #define PORT6_PPS_PPS3_Pos 3 /*!< PORT6 PPS: PPS3 Position */
\r
12854 #define PORT6_PPS_PPS3_Msk (0x01UL << PORT6_PPS_PPS3_Pos) /*!< PORT6 PPS: PPS3 Mask */
\r
12855 #define PORT6_PPS_PPS4_Pos 4 /*!< PORT6 PPS: PPS4 Position */
\r
12856 #define PORT6_PPS_PPS4_Msk (0x01UL << PORT6_PPS_PPS4_Pos) /*!< PORT6 PPS: PPS4 Mask */
\r
12857 #define PORT6_PPS_PPS5_Pos 5 /*!< PORT6 PPS: PPS5 Position */
\r
12858 #define PORT6_PPS_PPS5_Msk (0x01UL << PORT6_PPS_PPS5_Pos) /*!< PORT6 PPS: PPS5 Mask */
\r
12859 #define PORT6_PPS_PPS6_Pos 6 /*!< PORT6 PPS: PPS6 Position */
\r
12860 #define PORT6_PPS_PPS6_Msk (0x01UL << PORT6_PPS_PPS6_Pos) /*!< PORT6 PPS: PPS6 Mask */
\r
12861 #define PORT6_PPS_PPS7_Pos 7 /*!< PORT6 PPS: PPS7 Position */
\r
12862 #define PORT6_PPS_PPS7_Msk (0x01UL << PORT6_PPS_PPS7_Pos) /*!< PORT6 PPS: PPS7 Mask */
\r
12863 #define PORT6_PPS_PPS8_Pos 8 /*!< PORT6 PPS: PPS8 Position */
\r
12864 #define PORT6_PPS_PPS8_Msk (0x01UL << PORT6_PPS_PPS8_Pos) /*!< PORT6 PPS: PPS8 Mask */
\r
12865 #define PORT6_PPS_PPS9_Pos 9 /*!< PORT6 PPS: PPS9 Position */
\r
12866 #define PORT6_PPS_PPS9_Msk (0x01UL << PORT6_PPS_PPS9_Pos) /*!< PORT6 PPS: PPS9 Mask */
\r
12867 #define PORT6_PPS_PPS10_Pos 10 /*!< PORT6 PPS: PPS10 Position */
\r
12868 #define PORT6_PPS_PPS10_Msk (0x01UL << PORT6_PPS_PPS10_Pos) /*!< PORT6 PPS: PPS10 Mask */
\r
12869 #define PORT6_PPS_PPS11_Pos 11 /*!< PORT6 PPS: PPS11 Position */
\r
12870 #define PORT6_PPS_PPS11_Msk (0x01UL << PORT6_PPS_PPS11_Pos) /*!< PORT6 PPS: PPS11 Mask */
\r
12871 #define PORT6_PPS_PPS12_Pos 12 /*!< PORT6 PPS: PPS12 Position */
\r
12872 #define PORT6_PPS_PPS12_Msk (0x01UL << PORT6_PPS_PPS12_Pos) /*!< PORT6 PPS: PPS12 Mask */
\r
12873 #define PORT6_PPS_PPS13_Pos 13 /*!< PORT6 PPS: PPS13 Position */
\r
12874 #define PORT6_PPS_PPS13_Msk (0x01UL << PORT6_PPS_PPS13_Pos) /*!< PORT6 PPS: PPS13 Mask */
\r
12875 #define PORT6_PPS_PPS14_Pos 14 /*!< PORT6 PPS: PPS14 Position */
\r
12876 #define PORT6_PPS_PPS14_Msk (0x01UL << PORT6_PPS_PPS14_Pos) /*!< PORT6 PPS: PPS14 Mask */
\r
12877 #define PORT6_PPS_PPS15_Pos 15 /*!< PORT6 PPS: PPS15 Position */
\r
12878 #define PORT6_PPS_PPS15_Msk (0x01UL << PORT6_PPS_PPS15_Pos) /*!< PORT6 PPS: PPS15 Mask */
\r
12880 // --------------------------------------- PORT6_HWSEL ------------------------------------------
\r
12881 #define PORT6_HWSEL_HW0_Pos 0 /*!< PORT6 HWSEL: HW0 Position */
\r
12882 #define PORT6_HWSEL_HW0_Msk (0x03UL << PORT6_HWSEL_HW0_Pos) /*!< PORT6 HWSEL: HW0 Mask */
\r
12883 #define PORT6_HWSEL_HW1_Pos 2 /*!< PORT6 HWSEL: HW1 Position */
\r
12884 #define PORT6_HWSEL_HW1_Msk (0x03UL << PORT6_HWSEL_HW1_Pos) /*!< PORT6 HWSEL: HW1 Mask */
\r
12885 #define PORT6_HWSEL_HW2_Pos 4 /*!< PORT6 HWSEL: HW2 Position */
\r
12886 #define PORT6_HWSEL_HW2_Msk (0x03UL << PORT6_HWSEL_HW2_Pos) /*!< PORT6 HWSEL: HW2 Mask */
\r
12887 #define PORT6_HWSEL_HW3_Pos 6 /*!< PORT6 HWSEL: HW3 Position */
\r
12888 #define PORT6_HWSEL_HW3_Msk (0x03UL << PORT6_HWSEL_HW3_Pos) /*!< PORT6 HWSEL: HW3 Mask */
\r
12889 #define PORT6_HWSEL_HW4_Pos 8 /*!< PORT6 HWSEL: HW4 Position */
\r
12890 #define PORT6_HWSEL_HW4_Msk (0x03UL << PORT6_HWSEL_HW4_Pos) /*!< PORT6 HWSEL: HW4 Mask */
\r
12891 #define PORT6_HWSEL_HW5_Pos 10 /*!< PORT6 HWSEL: HW5 Position */
\r
12892 #define PORT6_HWSEL_HW5_Msk (0x03UL << PORT6_HWSEL_HW5_Pos) /*!< PORT6 HWSEL: HW5 Mask */
\r
12893 #define PORT6_HWSEL_HW6_Pos 12 /*!< PORT6 HWSEL: HW6 Position */
\r
12894 #define PORT6_HWSEL_HW6_Msk (0x03UL << PORT6_HWSEL_HW6_Pos) /*!< PORT6 HWSEL: HW6 Mask */
\r
12895 #define PORT6_HWSEL_HW7_Pos 14 /*!< PORT6 HWSEL: HW7 Position */
\r
12896 #define PORT6_HWSEL_HW7_Msk (0x03UL << PORT6_HWSEL_HW7_Pos) /*!< PORT6 HWSEL: HW7 Mask */
\r
12897 #define PORT6_HWSEL_HW8_Pos 16 /*!< PORT6 HWSEL: HW8 Position */
\r
12898 #define PORT6_HWSEL_HW8_Msk (0x03UL << PORT6_HWSEL_HW8_Pos) /*!< PORT6 HWSEL: HW8 Mask */
\r
12899 #define PORT6_HWSEL_HW9_Pos 18 /*!< PORT6 HWSEL: HW9 Position */
\r
12900 #define PORT6_HWSEL_HW9_Msk (0x03UL << PORT6_HWSEL_HW9_Pos) /*!< PORT6 HWSEL: HW9 Mask */
\r
12901 #define PORT6_HWSEL_HW10_Pos 20 /*!< PORT6 HWSEL: HW10 Position */
\r
12902 #define PORT6_HWSEL_HW10_Msk (0x03UL << PORT6_HWSEL_HW10_Pos) /*!< PORT6 HWSEL: HW10 Mask */
\r
12903 #define PORT6_HWSEL_HW11_Pos 22 /*!< PORT6 HWSEL: HW11 Position */
\r
12904 #define PORT6_HWSEL_HW11_Msk (0x03UL << PORT6_HWSEL_HW11_Pos) /*!< PORT6 HWSEL: HW11 Mask */
\r
12905 #define PORT6_HWSEL_HW12_Pos 24 /*!< PORT6 HWSEL: HW12 Position */
\r
12906 #define PORT6_HWSEL_HW12_Msk (0x03UL << PORT6_HWSEL_HW12_Pos) /*!< PORT6 HWSEL: HW12 Mask */
\r
12907 #define PORT6_HWSEL_HW13_Pos 26 /*!< PORT6 HWSEL: HW13 Position */
\r
12908 #define PORT6_HWSEL_HW13_Msk (0x03UL << PORT6_HWSEL_HW13_Pos) /*!< PORT6 HWSEL: HW13 Mask */
\r
12909 #define PORT6_HWSEL_HW14_Pos 28 /*!< PORT6 HWSEL: HW14 Position */
\r
12910 #define PORT6_HWSEL_HW14_Msk (0x03UL << PORT6_HWSEL_HW14_Pos) /*!< PORT6 HWSEL: HW14 Mask */
\r
12911 #define PORT6_HWSEL_HW15_Pos 30 /*!< PORT6 HWSEL: HW15 Position */
\r
12912 #define PORT6_HWSEL_HW15_Msk (0x03UL << PORT6_HWSEL_HW15_Pos) /*!< PORT6 HWSEL: HW15 Mask */
\r
12915 // ------------------------------------------------------------------------------------------------
\r
12916 // ----- PORT14 Position & Mask -----
\r
12917 // ------------------------------------------------------------------------------------------------
\r
12920 // --------------------------------------- PORT14_OUT -------------------------------------------
\r
12921 #define PORT14_OUT_P0_Pos 0 /*!< PORT14 OUT: P0 Position */
\r
12922 #define PORT14_OUT_P0_Msk (0x01UL << PORT14_OUT_P0_Pos) /*!< PORT14 OUT: P0 Mask */
\r
12923 #define PORT14_OUT_P1_Pos 1 /*!< PORT14 OUT: P1 Position */
\r
12924 #define PORT14_OUT_P1_Msk (0x01UL << PORT14_OUT_P1_Pos) /*!< PORT14 OUT: P1 Mask */
\r
12925 #define PORT14_OUT_P2_Pos 2 /*!< PORT14 OUT: P2 Position */
\r
12926 #define PORT14_OUT_P2_Msk (0x01UL << PORT14_OUT_P2_Pos) /*!< PORT14 OUT: P2 Mask */
\r
12927 #define PORT14_OUT_P3_Pos 3 /*!< PORT14 OUT: P3 Position */
\r
12928 #define PORT14_OUT_P3_Msk (0x01UL << PORT14_OUT_P3_Pos) /*!< PORT14 OUT: P3 Mask */
\r
12929 #define PORT14_OUT_P4_Pos 4 /*!< PORT14 OUT: P4 Position */
\r
12930 #define PORT14_OUT_P4_Msk (0x01UL << PORT14_OUT_P4_Pos) /*!< PORT14 OUT: P4 Mask */
\r
12931 #define PORT14_OUT_P5_Pos 5 /*!< PORT14 OUT: P5 Position */
\r
12932 #define PORT14_OUT_P5_Msk (0x01UL << PORT14_OUT_P5_Pos) /*!< PORT14 OUT: P5 Mask */
\r
12933 #define PORT14_OUT_P6_Pos 6 /*!< PORT14 OUT: P6 Position */
\r
12934 #define PORT14_OUT_P6_Msk (0x01UL << PORT14_OUT_P6_Pos) /*!< PORT14 OUT: P6 Mask */
\r
12935 #define PORT14_OUT_P7_Pos 7 /*!< PORT14 OUT: P7 Position */
\r
12936 #define PORT14_OUT_P7_Msk (0x01UL << PORT14_OUT_P7_Pos) /*!< PORT14 OUT: P7 Mask */
\r
12937 #define PORT14_OUT_P8_Pos 8 /*!< PORT14 OUT: P8 Position */
\r
12938 #define PORT14_OUT_P8_Msk (0x01UL << PORT14_OUT_P8_Pos) /*!< PORT14 OUT: P8 Mask */
\r
12939 #define PORT14_OUT_P9_Pos 9 /*!< PORT14 OUT: P9 Position */
\r
12940 #define PORT14_OUT_P9_Msk (0x01UL << PORT14_OUT_P9_Pos) /*!< PORT14 OUT: P9 Mask */
\r
12941 #define PORT14_OUT_P10_Pos 10 /*!< PORT14 OUT: P10 Position */
\r
12942 #define PORT14_OUT_P10_Msk (0x01UL << PORT14_OUT_P10_Pos) /*!< PORT14 OUT: P10 Mask */
\r
12943 #define PORT14_OUT_P11_Pos 11 /*!< PORT14 OUT: P11 Position */
\r
12944 #define PORT14_OUT_P11_Msk (0x01UL << PORT14_OUT_P11_Pos) /*!< PORT14 OUT: P11 Mask */
\r
12945 #define PORT14_OUT_P12_Pos 12 /*!< PORT14 OUT: P12 Position */
\r
12946 #define PORT14_OUT_P12_Msk (0x01UL << PORT14_OUT_P12_Pos) /*!< PORT14 OUT: P12 Mask */
\r
12947 #define PORT14_OUT_P13_Pos 13 /*!< PORT14 OUT: P13 Position */
\r
12948 #define PORT14_OUT_P13_Msk (0x01UL << PORT14_OUT_P13_Pos) /*!< PORT14 OUT: P13 Mask */
\r
12949 #define PORT14_OUT_P14_Pos 14 /*!< PORT14 OUT: P14 Position */
\r
12950 #define PORT14_OUT_P14_Msk (0x01UL << PORT14_OUT_P14_Pos) /*!< PORT14 OUT: P14 Mask */
\r
12951 #define PORT14_OUT_P15_Pos 15 /*!< PORT14 OUT: P15 Position */
\r
12952 #define PORT14_OUT_P15_Msk (0x01UL << PORT14_OUT_P15_Pos) /*!< PORT14 OUT: P15 Mask */
\r
12954 // --------------------------------------- PORT14_OMR -------------------------------------------
\r
12955 #define PORT14_OMR_PS0_Pos 0 /*!< PORT14 OMR: PS0 Position */
\r
12956 #define PORT14_OMR_PS0_Msk (0x01UL << PORT14_OMR_PS0_Pos) /*!< PORT14 OMR: PS0 Mask */
\r
12957 #define PORT14_OMR_PS1_Pos 1 /*!< PORT14 OMR: PS1 Position */
\r
12958 #define PORT14_OMR_PS1_Msk (0x01UL << PORT14_OMR_PS1_Pos) /*!< PORT14 OMR: PS1 Mask */
\r
12959 #define PORT14_OMR_PS2_Pos 2 /*!< PORT14 OMR: PS2 Position */
\r
12960 #define PORT14_OMR_PS2_Msk (0x01UL << PORT14_OMR_PS2_Pos) /*!< PORT14 OMR: PS2 Mask */
\r
12961 #define PORT14_OMR_PS3_Pos 3 /*!< PORT14 OMR: PS3 Position */
\r
12962 #define PORT14_OMR_PS3_Msk (0x01UL << PORT14_OMR_PS3_Pos) /*!< PORT14 OMR: PS3 Mask */
\r
12963 #define PORT14_OMR_PS4_Pos 4 /*!< PORT14 OMR: PS4 Position */
\r
12964 #define PORT14_OMR_PS4_Msk (0x01UL << PORT14_OMR_PS4_Pos) /*!< PORT14 OMR: PS4 Mask */
\r
12965 #define PORT14_OMR_PS5_Pos 5 /*!< PORT14 OMR: PS5 Position */
\r
12966 #define PORT14_OMR_PS5_Msk (0x01UL << PORT14_OMR_PS5_Pos) /*!< PORT14 OMR: PS5 Mask */
\r
12967 #define PORT14_OMR_PS6_Pos 6 /*!< PORT14 OMR: PS6 Position */
\r
12968 #define PORT14_OMR_PS6_Msk (0x01UL << PORT14_OMR_PS6_Pos) /*!< PORT14 OMR: PS6 Mask */
\r
12969 #define PORT14_OMR_PS7_Pos 7 /*!< PORT14 OMR: PS7 Position */
\r
12970 #define PORT14_OMR_PS7_Msk (0x01UL << PORT14_OMR_PS7_Pos) /*!< PORT14 OMR: PS7 Mask */
\r
12971 #define PORT14_OMR_PS8_Pos 8 /*!< PORT14 OMR: PS8 Position */
\r
12972 #define PORT14_OMR_PS8_Msk (0x01UL << PORT14_OMR_PS8_Pos) /*!< PORT14 OMR: PS8 Mask */
\r
12973 #define PORT14_OMR_PS9_Pos 9 /*!< PORT14 OMR: PS9 Position */
\r
12974 #define PORT14_OMR_PS9_Msk (0x01UL << PORT14_OMR_PS9_Pos) /*!< PORT14 OMR: PS9 Mask */
\r
12975 #define PORT14_OMR_PS10_Pos 10 /*!< PORT14 OMR: PS10 Position */
\r
12976 #define PORT14_OMR_PS10_Msk (0x01UL << PORT14_OMR_PS10_Pos) /*!< PORT14 OMR: PS10 Mask */
\r
12977 #define PORT14_OMR_PS11_Pos 11 /*!< PORT14 OMR: PS11 Position */
\r
12978 #define PORT14_OMR_PS11_Msk (0x01UL << PORT14_OMR_PS11_Pos) /*!< PORT14 OMR: PS11 Mask */
\r
12979 #define PORT14_OMR_PS12_Pos 12 /*!< PORT14 OMR: PS12 Position */
\r
12980 #define PORT14_OMR_PS12_Msk (0x01UL << PORT14_OMR_PS12_Pos) /*!< PORT14 OMR: PS12 Mask */
\r
12981 #define PORT14_OMR_PS13_Pos 13 /*!< PORT14 OMR: PS13 Position */
\r
12982 #define PORT14_OMR_PS13_Msk (0x01UL << PORT14_OMR_PS13_Pos) /*!< PORT14 OMR: PS13 Mask */
\r
12983 #define PORT14_OMR_PS14_Pos 14 /*!< PORT14 OMR: PS14 Position */
\r
12984 #define PORT14_OMR_PS14_Msk (0x01UL << PORT14_OMR_PS14_Pos) /*!< PORT14 OMR: PS14 Mask */
\r
12985 #define PORT14_OMR_PS15_Pos 15 /*!< PORT14 OMR: PS15 Position */
\r
12986 #define PORT14_OMR_PS15_Msk (0x01UL << PORT14_OMR_PS15_Pos) /*!< PORT14 OMR: PS15 Mask */
\r
12987 #define PORT14_OMR_PR0_Pos 16 /*!< PORT14 OMR: PR0 Position */
\r
12988 #define PORT14_OMR_PR0_Msk (0x01UL << PORT14_OMR_PR0_Pos) /*!< PORT14 OMR: PR0 Mask */
\r
12989 #define PORT14_OMR_PR1_Pos 17 /*!< PORT14 OMR: PR1 Position */
\r
12990 #define PORT14_OMR_PR1_Msk (0x01UL << PORT14_OMR_PR1_Pos) /*!< PORT14 OMR: PR1 Mask */
\r
12991 #define PORT14_OMR_PR2_Pos 18 /*!< PORT14 OMR: PR2 Position */
\r
12992 #define PORT14_OMR_PR2_Msk (0x01UL << PORT14_OMR_PR2_Pos) /*!< PORT14 OMR: PR2 Mask */
\r
12993 #define PORT14_OMR_PR3_Pos 19 /*!< PORT14 OMR: PR3 Position */
\r
12994 #define PORT14_OMR_PR3_Msk (0x01UL << PORT14_OMR_PR3_Pos) /*!< PORT14 OMR: PR3 Mask */
\r
12995 #define PORT14_OMR_PR4_Pos 20 /*!< PORT14 OMR: PR4 Position */
\r
12996 #define PORT14_OMR_PR4_Msk (0x01UL << PORT14_OMR_PR4_Pos) /*!< PORT14 OMR: PR4 Mask */
\r
12997 #define PORT14_OMR_PR5_Pos 21 /*!< PORT14 OMR: PR5 Position */
\r
12998 #define PORT14_OMR_PR5_Msk (0x01UL << PORT14_OMR_PR5_Pos) /*!< PORT14 OMR: PR5 Mask */
\r
12999 #define PORT14_OMR_PR6_Pos 22 /*!< PORT14 OMR: PR6 Position */
\r
13000 #define PORT14_OMR_PR6_Msk (0x01UL << PORT14_OMR_PR6_Pos) /*!< PORT14 OMR: PR6 Mask */
\r
13001 #define PORT14_OMR_PR7_Pos 23 /*!< PORT14 OMR: PR7 Position */
\r
13002 #define PORT14_OMR_PR7_Msk (0x01UL << PORT14_OMR_PR7_Pos) /*!< PORT14 OMR: PR7 Mask */
\r
13003 #define PORT14_OMR_PR8_Pos 24 /*!< PORT14 OMR: PR8 Position */
\r
13004 #define PORT14_OMR_PR8_Msk (0x01UL << PORT14_OMR_PR8_Pos) /*!< PORT14 OMR: PR8 Mask */
\r
13005 #define PORT14_OMR_PR9_Pos 25 /*!< PORT14 OMR: PR9 Position */
\r
13006 #define PORT14_OMR_PR9_Msk (0x01UL << PORT14_OMR_PR9_Pos) /*!< PORT14 OMR: PR9 Mask */
\r
13007 #define PORT14_OMR_PR10_Pos 26 /*!< PORT14 OMR: PR10 Position */
\r
13008 #define PORT14_OMR_PR10_Msk (0x01UL << PORT14_OMR_PR10_Pos) /*!< PORT14 OMR: PR10 Mask */
\r
13009 #define PORT14_OMR_PR11_Pos 27 /*!< PORT14 OMR: PR11 Position */
\r
13010 #define PORT14_OMR_PR11_Msk (0x01UL << PORT14_OMR_PR11_Pos) /*!< PORT14 OMR: PR11 Mask */
\r
13011 #define PORT14_OMR_PR12_Pos 28 /*!< PORT14 OMR: PR12 Position */
\r
13012 #define PORT14_OMR_PR12_Msk (0x01UL << PORT14_OMR_PR12_Pos) /*!< PORT14 OMR: PR12 Mask */
\r
13013 #define PORT14_OMR_PR13_Pos 29 /*!< PORT14 OMR: PR13 Position */
\r
13014 #define PORT14_OMR_PR13_Msk (0x01UL << PORT14_OMR_PR13_Pos) /*!< PORT14 OMR: PR13 Mask */
\r
13015 #define PORT14_OMR_PR14_Pos 30 /*!< PORT14 OMR: PR14 Position */
\r
13016 #define PORT14_OMR_PR14_Msk (0x01UL << PORT14_OMR_PR14_Pos) /*!< PORT14 OMR: PR14 Mask */
\r
13017 #define PORT14_OMR_PR15_Pos 31 /*!< PORT14 OMR: PR15 Position */
\r
13018 #define PORT14_OMR_PR15_Msk (0x01UL << PORT14_OMR_PR15_Pos) /*!< PORT14 OMR: PR15 Mask */
\r
13020 // -------------------------------------- PORT14_IOCR0 ------------------------------------------
\r
13021 #define PORT14_IOCR0_PC0_Pos 3 /*!< PORT14 IOCR0: PC0 Position */
\r
13022 #define PORT14_IOCR0_PC0_Msk (0x1fUL << PORT14_IOCR0_PC0_Pos) /*!< PORT14 IOCR0: PC0 Mask */
\r
13023 #define PORT14_IOCR0_PC1_Pos 11 /*!< PORT14 IOCR0: PC1 Position */
\r
13024 #define PORT14_IOCR0_PC1_Msk (0x1fUL << PORT14_IOCR0_PC1_Pos) /*!< PORT14 IOCR0: PC1 Mask */
\r
13025 #define PORT14_IOCR0_PC2_Pos 19 /*!< PORT14 IOCR0: PC2 Position */
\r
13026 #define PORT14_IOCR0_PC2_Msk (0x1fUL << PORT14_IOCR0_PC2_Pos) /*!< PORT14 IOCR0: PC2 Mask */
\r
13027 #define PORT14_IOCR0_PC3_Pos 27 /*!< PORT14 IOCR0: PC3 Position */
\r
13028 #define PORT14_IOCR0_PC3_Msk (0x1fUL << PORT14_IOCR0_PC3_Pos) /*!< PORT14 IOCR0: PC3 Mask */
\r
13030 // -------------------------------------- PORT14_IOCR4 ------------------------------------------
\r
13031 #define PORT14_IOCR4_PC4_Pos 3 /*!< PORT14 IOCR4: PC4 Position */
\r
13032 #define PORT14_IOCR4_PC4_Msk (0x1fUL << PORT14_IOCR4_PC4_Pos) /*!< PORT14 IOCR4: PC4 Mask */
\r
13033 #define PORT14_IOCR4_PC5_Pos 11 /*!< PORT14 IOCR4: PC5 Position */
\r
13034 #define PORT14_IOCR4_PC5_Msk (0x1fUL << PORT14_IOCR4_PC5_Pos) /*!< PORT14 IOCR4: PC5 Mask */
\r
13035 #define PORT14_IOCR4_PC6_Pos 19 /*!< PORT14 IOCR4: PC6 Position */
\r
13036 #define PORT14_IOCR4_PC6_Msk (0x1fUL << PORT14_IOCR4_PC6_Pos) /*!< PORT14 IOCR4: PC6 Mask */
\r
13037 #define PORT14_IOCR4_PC7_Pos 27 /*!< PORT14 IOCR4: PC7 Position */
\r
13038 #define PORT14_IOCR4_PC7_Msk (0x1fUL << PORT14_IOCR4_PC7_Pos) /*!< PORT14 IOCR4: PC7 Mask */
\r
13040 // -------------------------------------- PORT14_IOCR8 ------------------------------------------
\r
13041 #define PORT14_IOCR8_PC8_Pos 3 /*!< PORT14 IOCR8: PC8 Position */
\r
13042 #define PORT14_IOCR8_PC8_Msk (0x1fUL << PORT14_IOCR8_PC8_Pos) /*!< PORT14 IOCR8: PC8 Mask */
\r
13043 #define PORT14_IOCR8_PC9_Pos 11 /*!< PORT14 IOCR8: PC9 Position */
\r
13044 #define PORT14_IOCR8_PC9_Msk (0x1fUL << PORT14_IOCR8_PC9_Pos) /*!< PORT14 IOCR8: PC9 Mask */
\r
13045 #define PORT14_IOCR8_PC10_Pos 19 /*!< PORT14 IOCR8: PC10 Position */
\r
13046 #define PORT14_IOCR8_PC10_Msk (0x1fUL << PORT14_IOCR8_PC10_Pos) /*!< PORT14 IOCR8: PC10 Mask */
\r
13047 #define PORT14_IOCR8_PC11_Pos 27 /*!< PORT14 IOCR8: PC11 Position */
\r
13048 #define PORT14_IOCR8_PC11_Msk (0x1fUL << PORT14_IOCR8_PC11_Pos) /*!< PORT14 IOCR8: PC11 Mask */
\r
13050 // -------------------------------------- PORT14_IOCR12 -----------------------------------------
\r
13051 #define PORT14_IOCR12_PC12_Pos 3 /*!< PORT14 IOCR12: PC12 Position */
\r
13052 #define PORT14_IOCR12_PC12_Msk (0x1fUL << PORT14_IOCR12_PC12_Pos) /*!< PORT14 IOCR12: PC12 Mask */
\r
13053 #define PORT14_IOCR12_PC13_Pos 11 /*!< PORT14 IOCR12: PC13 Position */
\r
13054 #define PORT14_IOCR12_PC13_Msk (0x1fUL << PORT14_IOCR12_PC13_Pos) /*!< PORT14 IOCR12: PC13 Mask */
\r
13055 #define PORT14_IOCR12_PC14_Pos 19 /*!< PORT14 IOCR12: PC14 Position */
\r
13056 #define PORT14_IOCR12_PC14_Msk (0x1fUL << PORT14_IOCR12_PC14_Pos) /*!< PORT14 IOCR12: PC14 Mask */
\r
13057 #define PORT14_IOCR12_PC15_Pos 27 /*!< PORT14 IOCR12: PC15 Position */
\r
13058 #define PORT14_IOCR12_PC15_Msk (0x1fUL << PORT14_IOCR12_PC15_Pos) /*!< PORT14 IOCR12: PC15 Mask */
\r
13060 // ---------------------------------------- PORT14_IN -------------------------------------------
\r
13061 #define PORT14_IN_P0_Pos 0 /*!< PORT14 IN: P0 Position */
\r
13062 #define PORT14_IN_P0_Msk (0x01UL << PORT14_IN_P0_Pos) /*!< PORT14 IN: P0 Mask */
\r
13063 #define PORT14_IN_P1_Pos 1 /*!< PORT14 IN: P1 Position */
\r
13064 #define PORT14_IN_P1_Msk (0x01UL << PORT14_IN_P1_Pos) /*!< PORT14 IN: P1 Mask */
\r
13065 #define PORT14_IN_P2_Pos 2 /*!< PORT14 IN: P2 Position */
\r
13066 #define PORT14_IN_P2_Msk (0x01UL << PORT14_IN_P2_Pos) /*!< PORT14 IN: P2 Mask */
\r
13067 #define PORT14_IN_P3_Pos 3 /*!< PORT14 IN: P3 Position */
\r
13068 #define PORT14_IN_P3_Msk (0x01UL << PORT14_IN_P3_Pos) /*!< PORT14 IN: P3 Mask */
\r
13069 #define PORT14_IN_P4_Pos 4 /*!< PORT14 IN: P4 Position */
\r
13070 #define PORT14_IN_P4_Msk (0x01UL << PORT14_IN_P4_Pos) /*!< PORT14 IN: P4 Mask */
\r
13071 #define PORT14_IN_P5_Pos 5 /*!< PORT14 IN: P5 Position */
\r
13072 #define PORT14_IN_P5_Msk (0x01UL << PORT14_IN_P5_Pos) /*!< PORT14 IN: P5 Mask */
\r
13073 #define PORT14_IN_P6_Pos 6 /*!< PORT14 IN: P6 Position */
\r
13074 #define PORT14_IN_P6_Msk (0x01UL << PORT14_IN_P6_Pos) /*!< PORT14 IN: P6 Mask */
\r
13075 #define PORT14_IN_P7_Pos 7 /*!< PORT14 IN: P7 Position */
\r
13076 #define PORT14_IN_P7_Msk (0x01UL << PORT14_IN_P7_Pos) /*!< PORT14 IN: P7 Mask */
\r
13077 #define PORT14_IN_P8_Pos 8 /*!< PORT14 IN: P8 Position */
\r
13078 #define PORT14_IN_P8_Msk (0x01UL << PORT14_IN_P8_Pos) /*!< PORT14 IN: P8 Mask */
\r
13079 #define PORT14_IN_P9_Pos 9 /*!< PORT14 IN: P9 Position */
\r
13080 #define PORT14_IN_P9_Msk (0x01UL << PORT14_IN_P9_Pos) /*!< PORT14 IN: P9 Mask */
\r
13081 #define PORT14_IN_P10_Pos 10 /*!< PORT14 IN: P10 Position */
\r
13082 #define PORT14_IN_P10_Msk (0x01UL << PORT14_IN_P10_Pos) /*!< PORT14 IN: P10 Mask */
\r
13083 #define PORT14_IN_P11_Pos 11 /*!< PORT14 IN: P11 Position */
\r
13084 #define PORT14_IN_P11_Msk (0x01UL << PORT14_IN_P11_Pos) /*!< PORT14 IN: P11 Mask */
\r
13085 #define PORT14_IN_P12_Pos 12 /*!< PORT14 IN: P12 Position */
\r
13086 #define PORT14_IN_P12_Msk (0x01UL << PORT14_IN_P12_Pos) /*!< PORT14 IN: P12 Mask */
\r
13087 #define PORT14_IN_P13_Pos 13 /*!< PORT14 IN: P13 Position */
\r
13088 #define PORT14_IN_P13_Msk (0x01UL << PORT14_IN_P13_Pos) /*!< PORT14 IN: P13 Mask */
\r
13089 #define PORT14_IN_P14_Pos 14 /*!< PORT14 IN: P14 Position */
\r
13090 #define PORT14_IN_P14_Msk (0x01UL << PORT14_IN_P14_Pos) /*!< PORT14 IN: P14 Mask */
\r
13091 #define PORT14_IN_P15_Pos 15 /*!< PORT14 IN: P15 Position */
\r
13092 #define PORT14_IN_P15_Msk (0x01UL << PORT14_IN_P15_Pos) /*!< PORT14 IN: P15 Mask */
\r
13094 // -------------------------------------- PORT14_PDISC ------------------------------------------
\r
13095 #define PORT14_PDISC_PDIS0_Pos 0 /*!< PORT14 PDISC: PDIS0 Position */
\r
13096 #define PORT14_PDISC_PDIS0_Msk (0x01UL << PORT14_PDISC_PDIS0_Pos) /*!< PORT14 PDISC: PDIS0 Mask */
\r
13097 #define PORT14_PDISC_PDIS1_Pos 1 /*!< PORT14 PDISC: PDIS1 Position */
\r
13098 #define PORT14_PDISC_PDIS1_Msk (0x01UL << PORT14_PDISC_PDIS1_Pos) /*!< PORT14 PDISC: PDIS1 Mask */
\r
13099 #define PORT14_PDISC_PDIS2_Pos 2 /*!< PORT14 PDISC: PDIS2 Position */
\r
13100 #define PORT14_PDISC_PDIS2_Msk (0x01UL << PORT14_PDISC_PDIS2_Pos) /*!< PORT14 PDISC: PDIS2 Mask */
\r
13101 #define PORT14_PDISC_PDIS3_Pos 3 /*!< PORT14 PDISC: PDIS3 Position */
\r
13102 #define PORT14_PDISC_PDIS3_Msk (0x01UL << PORT14_PDISC_PDIS3_Pos) /*!< PORT14 PDISC: PDIS3 Mask */
\r
13103 #define PORT14_PDISC_PDIS4_Pos 4 /*!< PORT14 PDISC: PDIS4 Position */
\r
13104 #define PORT14_PDISC_PDIS4_Msk (0x01UL << PORT14_PDISC_PDIS4_Pos) /*!< PORT14 PDISC: PDIS4 Mask */
\r
13105 #define PORT14_PDISC_PDIS5_Pos 5 /*!< PORT14 PDISC: PDIS5 Position */
\r
13106 #define PORT14_PDISC_PDIS5_Msk (0x01UL << PORT14_PDISC_PDIS5_Pos) /*!< PORT14 PDISC: PDIS5 Mask */
\r
13107 #define PORT14_PDISC_PDIS6_Pos 6 /*!< PORT14 PDISC: PDIS6 Position */
\r
13108 #define PORT14_PDISC_PDIS6_Msk (0x01UL << PORT14_PDISC_PDIS6_Pos) /*!< PORT14 PDISC: PDIS6 Mask */
\r
13109 #define PORT14_PDISC_PDIS7_Pos 7 /*!< PORT14 PDISC: PDIS7 Position */
\r
13110 #define PORT14_PDISC_PDIS7_Msk (0x01UL << PORT14_PDISC_PDIS7_Pos) /*!< PORT14 PDISC: PDIS7 Mask */
\r
13111 #define PORT14_PDISC_PDIS8_Pos 8 /*!< PORT14 PDISC: PDIS8 Position */
\r
13112 #define PORT14_PDISC_PDIS8_Msk (0x01UL << PORT14_PDISC_PDIS8_Pos) /*!< PORT14 PDISC: PDIS8 Mask */
\r
13113 #define PORT14_PDISC_PDIS9_Pos 9 /*!< PORT14 PDISC: PDIS9 Position */
\r
13114 #define PORT14_PDISC_PDIS9_Msk (0x01UL << PORT14_PDISC_PDIS9_Pos) /*!< PORT14 PDISC: PDIS9 Mask */
\r
13115 #define PORT14_PDISC_PDIS12_Pos 12 /*!< PORT14 PDISC: PDIS12 Position */
\r
13116 #define PORT14_PDISC_PDIS12_Msk (0x01UL << PORT14_PDISC_PDIS12_Pos) /*!< PORT14 PDISC: PDIS12 Mask */
\r
13117 #define PORT14_PDISC_PDIS13_Pos 13 /*!< PORT14 PDISC: PDIS13 Position */
\r
13118 #define PORT14_PDISC_PDIS13_Msk (0x01UL << PORT14_PDISC_PDIS13_Pos) /*!< PORT14 PDISC: PDIS13 Mask */
\r
13119 #define PORT14_PDISC_PDIS14_Pos 14 /*!< PORT14 PDISC: PDIS14 Position */
\r
13120 #define PORT14_PDISC_PDIS14_Msk (0x01UL << PORT14_PDISC_PDIS14_Pos) /*!< PORT14 PDISC: PDIS14 Mask */
\r
13121 #define PORT14_PDISC_PDIS15_Pos 15 /*!< PORT14 PDISC: PDIS15 Position */
\r
13122 #define PORT14_PDISC_PDIS15_Msk (0x01UL << PORT14_PDISC_PDIS15_Pos) /*!< PORT14 PDISC: PDIS15 Mask */
\r
13124 // --------------------------------------- PORT14_PPS -------------------------------------------
\r
13125 #define PORT14_PPS_PPS0_Pos 0 /*!< PORT14 PPS: PPS0 Position */
\r
13126 #define PORT14_PPS_PPS0_Msk (0x01UL << PORT14_PPS_PPS0_Pos) /*!< PORT14 PPS: PPS0 Mask */
\r
13127 #define PORT14_PPS_PPS1_Pos 1 /*!< PORT14 PPS: PPS1 Position */
\r
13128 #define PORT14_PPS_PPS1_Msk (0x01UL << PORT14_PPS_PPS1_Pos) /*!< PORT14 PPS: PPS1 Mask */
\r
13129 #define PORT14_PPS_PPS2_Pos 2 /*!< PORT14 PPS: PPS2 Position */
\r
13130 #define PORT14_PPS_PPS2_Msk (0x01UL << PORT14_PPS_PPS2_Pos) /*!< PORT14 PPS: PPS2 Mask */
\r
13131 #define PORT14_PPS_PPS3_Pos 3 /*!< PORT14 PPS: PPS3 Position */
\r
13132 #define PORT14_PPS_PPS3_Msk (0x01UL << PORT14_PPS_PPS3_Pos) /*!< PORT14 PPS: PPS3 Mask */
\r
13133 #define PORT14_PPS_PPS4_Pos 4 /*!< PORT14 PPS: PPS4 Position */
\r
13134 #define PORT14_PPS_PPS4_Msk (0x01UL << PORT14_PPS_PPS4_Pos) /*!< PORT14 PPS: PPS4 Mask */
\r
13135 #define PORT14_PPS_PPS5_Pos 5 /*!< PORT14 PPS: PPS5 Position */
\r
13136 #define PORT14_PPS_PPS5_Msk (0x01UL << PORT14_PPS_PPS5_Pos) /*!< PORT14 PPS: PPS5 Mask */
\r
13137 #define PORT14_PPS_PPS6_Pos 6 /*!< PORT14 PPS: PPS6 Position */
\r
13138 #define PORT14_PPS_PPS6_Msk (0x01UL << PORT14_PPS_PPS6_Pos) /*!< PORT14 PPS: PPS6 Mask */
\r
13139 #define PORT14_PPS_PPS7_Pos 7 /*!< PORT14 PPS: PPS7 Position */
\r
13140 #define PORT14_PPS_PPS7_Msk (0x01UL << PORT14_PPS_PPS7_Pos) /*!< PORT14 PPS: PPS7 Mask */
\r
13141 #define PORT14_PPS_PPS8_Pos 8 /*!< PORT14 PPS: PPS8 Position */
\r
13142 #define PORT14_PPS_PPS8_Msk (0x01UL << PORT14_PPS_PPS8_Pos) /*!< PORT14 PPS: PPS8 Mask */
\r
13143 #define PORT14_PPS_PPS9_Pos 9 /*!< PORT14 PPS: PPS9 Position */
\r
13144 #define PORT14_PPS_PPS9_Msk (0x01UL << PORT14_PPS_PPS9_Pos) /*!< PORT14 PPS: PPS9 Mask */
\r
13145 #define PORT14_PPS_PPS10_Pos 10 /*!< PORT14 PPS: PPS10 Position */
\r
13146 #define PORT14_PPS_PPS10_Msk (0x01UL << PORT14_PPS_PPS10_Pos) /*!< PORT14 PPS: PPS10 Mask */
\r
13147 #define PORT14_PPS_PPS11_Pos 11 /*!< PORT14 PPS: PPS11 Position */
\r
13148 #define PORT14_PPS_PPS11_Msk (0x01UL << PORT14_PPS_PPS11_Pos) /*!< PORT14 PPS: PPS11 Mask */
\r
13149 #define PORT14_PPS_PPS12_Pos 12 /*!< PORT14 PPS: PPS12 Position */
\r
13150 #define PORT14_PPS_PPS12_Msk (0x01UL << PORT14_PPS_PPS12_Pos) /*!< PORT14 PPS: PPS12 Mask */
\r
13151 #define PORT14_PPS_PPS13_Pos 13 /*!< PORT14 PPS: PPS13 Position */
\r
13152 #define PORT14_PPS_PPS13_Msk (0x01UL << PORT14_PPS_PPS13_Pos) /*!< PORT14 PPS: PPS13 Mask */
\r
13153 #define PORT14_PPS_PPS14_Pos 14 /*!< PORT14 PPS: PPS14 Position */
\r
13154 #define PORT14_PPS_PPS14_Msk (0x01UL << PORT14_PPS_PPS14_Pos) /*!< PORT14 PPS: PPS14 Mask */
\r
13155 #define PORT14_PPS_PPS15_Pos 15 /*!< PORT14 PPS: PPS15 Position */
\r
13156 #define PORT14_PPS_PPS15_Msk (0x01UL << PORT14_PPS_PPS15_Pos) /*!< PORT14 PPS: PPS15 Mask */
\r
13158 // -------------------------------------- PORT14_HWSEL ------------------------------------------
\r
13159 #define PORT14_HWSEL_HW0_Pos 0 /*!< PORT14 HWSEL: HW0 Position */
\r
13160 #define PORT14_HWSEL_HW0_Msk (0x03UL << PORT14_HWSEL_HW0_Pos) /*!< PORT14 HWSEL: HW0 Mask */
\r
13161 #define PORT14_HWSEL_HW1_Pos 2 /*!< PORT14 HWSEL: HW1 Position */
\r
13162 #define PORT14_HWSEL_HW1_Msk (0x03UL << PORT14_HWSEL_HW1_Pos) /*!< PORT14 HWSEL: HW1 Mask */
\r
13163 #define PORT14_HWSEL_HW2_Pos 4 /*!< PORT14 HWSEL: HW2 Position */
\r
13164 #define PORT14_HWSEL_HW2_Msk (0x03UL << PORT14_HWSEL_HW2_Pos) /*!< PORT14 HWSEL: HW2 Mask */
\r
13165 #define PORT14_HWSEL_HW3_Pos 6 /*!< PORT14 HWSEL: HW3 Position */
\r
13166 #define PORT14_HWSEL_HW3_Msk (0x03UL << PORT14_HWSEL_HW3_Pos) /*!< PORT14 HWSEL: HW3 Mask */
\r
13167 #define PORT14_HWSEL_HW4_Pos 8 /*!< PORT14 HWSEL: HW4 Position */
\r
13168 #define PORT14_HWSEL_HW4_Msk (0x03UL << PORT14_HWSEL_HW4_Pos) /*!< PORT14 HWSEL: HW4 Mask */
\r
13169 #define PORT14_HWSEL_HW5_Pos 10 /*!< PORT14 HWSEL: HW5 Position */
\r
13170 #define PORT14_HWSEL_HW5_Msk (0x03UL << PORT14_HWSEL_HW5_Pos) /*!< PORT14 HWSEL: HW5 Mask */
\r
13171 #define PORT14_HWSEL_HW6_Pos 12 /*!< PORT14 HWSEL: HW6 Position */
\r
13172 #define PORT14_HWSEL_HW6_Msk (0x03UL << PORT14_HWSEL_HW6_Pos) /*!< PORT14 HWSEL: HW6 Mask */
\r
13173 #define PORT14_HWSEL_HW7_Pos 14 /*!< PORT14 HWSEL: HW7 Position */
\r
13174 #define PORT14_HWSEL_HW7_Msk (0x03UL << PORT14_HWSEL_HW7_Pos) /*!< PORT14 HWSEL: HW7 Mask */
\r
13175 #define PORT14_HWSEL_HW8_Pos 16 /*!< PORT14 HWSEL: HW8 Position */
\r
13176 #define PORT14_HWSEL_HW8_Msk (0x03UL << PORT14_HWSEL_HW8_Pos) /*!< PORT14 HWSEL: HW8 Mask */
\r
13177 #define PORT14_HWSEL_HW9_Pos 18 /*!< PORT14 HWSEL: HW9 Position */
\r
13178 #define PORT14_HWSEL_HW9_Msk (0x03UL << PORT14_HWSEL_HW9_Pos) /*!< PORT14 HWSEL: HW9 Mask */
\r
13179 #define PORT14_HWSEL_HW10_Pos 20 /*!< PORT14 HWSEL: HW10 Position */
\r
13180 #define PORT14_HWSEL_HW10_Msk (0x03UL << PORT14_HWSEL_HW10_Pos) /*!< PORT14 HWSEL: HW10 Mask */
\r
13181 #define PORT14_HWSEL_HW11_Pos 22 /*!< PORT14 HWSEL: HW11 Position */
\r
13182 #define PORT14_HWSEL_HW11_Msk (0x03UL << PORT14_HWSEL_HW11_Pos) /*!< PORT14 HWSEL: HW11 Mask */
\r
13183 #define PORT14_HWSEL_HW12_Pos 24 /*!< PORT14 HWSEL: HW12 Position */
\r
13184 #define PORT14_HWSEL_HW12_Msk (0x03UL << PORT14_HWSEL_HW12_Pos) /*!< PORT14 HWSEL: HW12 Mask */
\r
13185 #define PORT14_HWSEL_HW13_Pos 26 /*!< PORT14 HWSEL: HW13 Position */
\r
13186 #define PORT14_HWSEL_HW13_Msk (0x03UL << PORT14_HWSEL_HW13_Pos) /*!< PORT14 HWSEL: HW13 Mask */
\r
13187 #define PORT14_HWSEL_HW14_Pos 28 /*!< PORT14 HWSEL: HW14 Position */
\r
13188 #define PORT14_HWSEL_HW14_Msk (0x03UL << PORT14_HWSEL_HW14_Pos) /*!< PORT14 HWSEL: HW14 Mask */
\r
13189 #define PORT14_HWSEL_HW15_Pos 30 /*!< PORT14 HWSEL: HW15 Position */
\r
13190 #define PORT14_HWSEL_HW15_Msk (0x03UL << PORT14_HWSEL_HW15_Pos) /*!< PORT14 HWSEL: HW15 Mask */
\r
13193 // ------------------------------------------------------------------------------------------------
\r
13194 // ----- PORT15 Position & Mask -----
\r
13195 // ------------------------------------------------------------------------------------------------
\r
13198 // --------------------------------------- PORT15_OUT -------------------------------------------
\r
13199 #define PORT15_OUT_P0_Pos 0 /*!< PORT15 OUT: P0 Position */
\r
13200 #define PORT15_OUT_P0_Msk (0x01UL << PORT15_OUT_P0_Pos) /*!< PORT15 OUT: P0 Mask */
\r
13201 #define PORT15_OUT_P1_Pos 1 /*!< PORT15 OUT: P1 Position */
\r
13202 #define PORT15_OUT_P1_Msk (0x01UL << PORT15_OUT_P1_Pos) /*!< PORT15 OUT: P1 Mask */
\r
13203 #define PORT15_OUT_P2_Pos 2 /*!< PORT15 OUT: P2 Position */
\r
13204 #define PORT15_OUT_P2_Msk (0x01UL << PORT15_OUT_P2_Pos) /*!< PORT15 OUT: P2 Mask */
\r
13205 #define PORT15_OUT_P3_Pos 3 /*!< PORT15 OUT: P3 Position */
\r
13206 #define PORT15_OUT_P3_Msk (0x01UL << PORT15_OUT_P3_Pos) /*!< PORT15 OUT: P3 Mask */
\r
13207 #define PORT15_OUT_P4_Pos 4 /*!< PORT15 OUT: P4 Position */
\r
13208 #define PORT15_OUT_P4_Msk (0x01UL << PORT15_OUT_P4_Pos) /*!< PORT15 OUT: P4 Mask */
\r
13209 #define PORT15_OUT_P5_Pos 5 /*!< PORT15 OUT: P5 Position */
\r
13210 #define PORT15_OUT_P5_Msk (0x01UL << PORT15_OUT_P5_Pos) /*!< PORT15 OUT: P5 Mask */
\r
13211 #define PORT15_OUT_P6_Pos 6 /*!< PORT15 OUT: P6 Position */
\r
13212 #define PORT15_OUT_P6_Msk (0x01UL << PORT15_OUT_P6_Pos) /*!< PORT15 OUT: P6 Mask */
\r
13213 #define PORT15_OUT_P7_Pos 7 /*!< PORT15 OUT: P7 Position */
\r
13214 #define PORT15_OUT_P7_Msk (0x01UL << PORT15_OUT_P7_Pos) /*!< PORT15 OUT: P7 Mask */
\r
13215 #define PORT15_OUT_P8_Pos 8 /*!< PORT15 OUT: P8 Position */
\r
13216 #define PORT15_OUT_P8_Msk (0x01UL << PORT15_OUT_P8_Pos) /*!< PORT15 OUT: P8 Mask */
\r
13217 #define PORT15_OUT_P9_Pos 9 /*!< PORT15 OUT: P9 Position */
\r
13218 #define PORT15_OUT_P9_Msk (0x01UL << PORT15_OUT_P9_Pos) /*!< PORT15 OUT: P9 Mask */
\r
13219 #define PORT15_OUT_P10_Pos 10 /*!< PORT15 OUT: P10 Position */
\r
13220 #define PORT15_OUT_P10_Msk (0x01UL << PORT15_OUT_P10_Pos) /*!< PORT15 OUT: P10 Mask */
\r
13221 #define PORT15_OUT_P11_Pos 11 /*!< PORT15 OUT: P11 Position */
\r
13222 #define PORT15_OUT_P11_Msk (0x01UL << PORT15_OUT_P11_Pos) /*!< PORT15 OUT: P11 Mask */
\r
13223 #define PORT15_OUT_P12_Pos 12 /*!< PORT15 OUT: P12 Position */
\r
13224 #define PORT15_OUT_P12_Msk (0x01UL << PORT15_OUT_P12_Pos) /*!< PORT15 OUT: P12 Mask */
\r
13225 #define PORT15_OUT_P13_Pos 13 /*!< PORT15 OUT: P13 Position */
\r
13226 #define PORT15_OUT_P13_Msk (0x01UL << PORT15_OUT_P13_Pos) /*!< PORT15 OUT: P13 Mask */
\r
13227 #define PORT15_OUT_P14_Pos 14 /*!< PORT15 OUT: P14 Position */
\r
13228 #define PORT15_OUT_P14_Msk (0x01UL << PORT15_OUT_P14_Pos) /*!< PORT15 OUT: P14 Mask */
\r
13229 #define PORT15_OUT_P15_Pos 15 /*!< PORT15 OUT: P15 Position */
\r
13230 #define PORT15_OUT_P15_Msk (0x01UL << PORT15_OUT_P15_Pos) /*!< PORT15 OUT: P15 Mask */
\r
13232 // --------------------------------------- PORT15_OMR -------------------------------------------
\r
13233 #define PORT15_OMR_PS0_Pos 0 /*!< PORT15 OMR: PS0 Position */
\r
13234 #define PORT15_OMR_PS0_Msk (0x01UL << PORT15_OMR_PS0_Pos) /*!< PORT15 OMR: PS0 Mask */
\r
13235 #define PORT15_OMR_PS1_Pos 1 /*!< PORT15 OMR: PS1 Position */
\r
13236 #define PORT15_OMR_PS1_Msk (0x01UL << PORT15_OMR_PS1_Pos) /*!< PORT15 OMR: PS1 Mask */
\r
13237 #define PORT15_OMR_PS2_Pos 2 /*!< PORT15 OMR: PS2 Position */
\r
13238 #define PORT15_OMR_PS2_Msk (0x01UL << PORT15_OMR_PS2_Pos) /*!< PORT15 OMR: PS2 Mask */
\r
13239 #define PORT15_OMR_PS3_Pos 3 /*!< PORT15 OMR: PS3 Position */
\r
13240 #define PORT15_OMR_PS3_Msk (0x01UL << PORT15_OMR_PS3_Pos) /*!< PORT15 OMR: PS3 Mask */
\r
13241 #define PORT15_OMR_PS4_Pos 4 /*!< PORT15 OMR: PS4 Position */
\r
13242 #define PORT15_OMR_PS4_Msk (0x01UL << PORT15_OMR_PS4_Pos) /*!< PORT15 OMR: PS4 Mask */
\r
13243 #define PORT15_OMR_PS5_Pos 5 /*!< PORT15 OMR: PS5 Position */
\r
13244 #define PORT15_OMR_PS5_Msk (0x01UL << PORT15_OMR_PS5_Pos) /*!< PORT15 OMR: PS5 Mask */
\r
13245 #define PORT15_OMR_PS6_Pos 6 /*!< PORT15 OMR: PS6 Position */
\r
13246 #define PORT15_OMR_PS6_Msk (0x01UL << PORT15_OMR_PS6_Pos) /*!< PORT15 OMR: PS6 Mask */
\r
13247 #define PORT15_OMR_PS7_Pos 7 /*!< PORT15 OMR: PS7 Position */
\r
13248 #define PORT15_OMR_PS7_Msk (0x01UL << PORT15_OMR_PS7_Pos) /*!< PORT15 OMR: PS7 Mask */
\r
13249 #define PORT15_OMR_PS8_Pos 8 /*!< PORT15 OMR: PS8 Position */
\r
13250 #define PORT15_OMR_PS8_Msk (0x01UL << PORT15_OMR_PS8_Pos) /*!< PORT15 OMR: PS8 Mask */
\r
13251 #define PORT15_OMR_PS9_Pos 9 /*!< PORT15 OMR: PS9 Position */
\r
13252 #define PORT15_OMR_PS9_Msk (0x01UL << PORT15_OMR_PS9_Pos) /*!< PORT15 OMR: PS9 Mask */
\r
13253 #define PORT15_OMR_PS10_Pos 10 /*!< PORT15 OMR: PS10 Position */
\r
13254 #define PORT15_OMR_PS10_Msk (0x01UL << PORT15_OMR_PS10_Pos) /*!< PORT15 OMR: PS10 Mask */
\r
13255 #define PORT15_OMR_PS11_Pos 11 /*!< PORT15 OMR: PS11 Position */
\r
13256 #define PORT15_OMR_PS11_Msk (0x01UL << PORT15_OMR_PS11_Pos) /*!< PORT15 OMR: PS11 Mask */
\r
13257 #define PORT15_OMR_PS12_Pos 12 /*!< PORT15 OMR: PS12 Position */
\r
13258 #define PORT15_OMR_PS12_Msk (0x01UL << PORT15_OMR_PS12_Pos) /*!< PORT15 OMR: PS12 Mask */
\r
13259 #define PORT15_OMR_PS13_Pos 13 /*!< PORT15 OMR: PS13 Position */
\r
13260 #define PORT15_OMR_PS13_Msk (0x01UL << PORT15_OMR_PS13_Pos) /*!< PORT15 OMR: PS13 Mask */
\r
13261 #define PORT15_OMR_PS14_Pos 14 /*!< PORT15 OMR: PS14 Position */
\r
13262 #define PORT15_OMR_PS14_Msk (0x01UL << PORT15_OMR_PS14_Pos) /*!< PORT15 OMR: PS14 Mask */
\r
13263 #define PORT15_OMR_PS15_Pos 15 /*!< PORT15 OMR: PS15 Position */
\r
13264 #define PORT15_OMR_PS15_Msk (0x01UL << PORT15_OMR_PS15_Pos) /*!< PORT15 OMR: PS15 Mask */
\r
13265 #define PORT15_OMR_PR0_Pos 16 /*!< PORT15 OMR: PR0 Position */
\r
13266 #define PORT15_OMR_PR0_Msk (0x01UL << PORT15_OMR_PR0_Pos) /*!< PORT15 OMR: PR0 Mask */
\r
13267 #define PORT15_OMR_PR1_Pos 17 /*!< PORT15 OMR: PR1 Position */
\r
13268 #define PORT15_OMR_PR1_Msk (0x01UL << PORT15_OMR_PR1_Pos) /*!< PORT15 OMR: PR1 Mask */
\r
13269 #define PORT15_OMR_PR2_Pos 18 /*!< PORT15 OMR: PR2 Position */
\r
13270 #define PORT15_OMR_PR2_Msk (0x01UL << PORT15_OMR_PR2_Pos) /*!< PORT15 OMR: PR2 Mask */
\r
13271 #define PORT15_OMR_PR3_Pos 19 /*!< PORT15 OMR: PR3 Position */
\r
13272 #define PORT15_OMR_PR3_Msk (0x01UL << PORT15_OMR_PR3_Pos) /*!< PORT15 OMR: PR3 Mask */
\r
13273 #define PORT15_OMR_PR4_Pos 20 /*!< PORT15 OMR: PR4 Position */
\r
13274 #define PORT15_OMR_PR4_Msk (0x01UL << PORT15_OMR_PR4_Pos) /*!< PORT15 OMR: PR4 Mask */
\r
13275 #define PORT15_OMR_PR5_Pos 21 /*!< PORT15 OMR: PR5 Position */
\r
13276 #define PORT15_OMR_PR5_Msk (0x01UL << PORT15_OMR_PR5_Pos) /*!< PORT15 OMR: PR5 Mask */
\r
13277 #define PORT15_OMR_PR6_Pos 22 /*!< PORT15 OMR: PR6 Position */
\r
13278 #define PORT15_OMR_PR6_Msk (0x01UL << PORT15_OMR_PR6_Pos) /*!< PORT15 OMR: PR6 Mask */
\r
13279 #define PORT15_OMR_PR7_Pos 23 /*!< PORT15 OMR: PR7 Position */
\r
13280 #define PORT15_OMR_PR7_Msk (0x01UL << PORT15_OMR_PR7_Pos) /*!< PORT15 OMR: PR7 Mask */
\r
13281 #define PORT15_OMR_PR8_Pos 24 /*!< PORT15 OMR: PR8 Position */
\r
13282 #define PORT15_OMR_PR8_Msk (0x01UL << PORT15_OMR_PR8_Pos) /*!< PORT15 OMR: PR8 Mask */
\r
13283 #define PORT15_OMR_PR9_Pos 25 /*!< PORT15 OMR: PR9 Position */
\r
13284 #define PORT15_OMR_PR9_Msk (0x01UL << PORT15_OMR_PR9_Pos) /*!< PORT15 OMR: PR9 Mask */
\r
13285 #define PORT15_OMR_PR10_Pos 26 /*!< PORT15 OMR: PR10 Position */
\r
13286 #define PORT15_OMR_PR10_Msk (0x01UL << PORT15_OMR_PR10_Pos) /*!< PORT15 OMR: PR10 Mask */
\r
13287 #define PORT15_OMR_PR11_Pos 27 /*!< PORT15 OMR: PR11 Position */
\r
13288 #define PORT15_OMR_PR11_Msk (0x01UL << PORT15_OMR_PR11_Pos) /*!< PORT15 OMR: PR11 Mask */
\r
13289 #define PORT15_OMR_PR12_Pos 28 /*!< PORT15 OMR: PR12 Position */
\r
13290 #define PORT15_OMR_PR12_Msk (0x01UL << PORT15_OMR_PR12_Pos) /*!< PORT15 OMR: PR12 Mask */
\r
13291 #define PORT15_OMR_PR13_Pos 29 /*!< PORT15 OMR: PR13 Position */
\r
13292 #define PORT15_OMR_PR13_Msk (0x01UL << PORT15_OMR_PR13_Pos) /*!< PORT15 OMR: PR13 Mask */
\r
13293 #define PORT15_OMR_PR14_Pos 30 /*!< PORT15 OMR: PR14 Position */
\r
13294 #define PORT15_OMR_PR14_Msk (0x01UL << PORT15_OMR_PR14_Pos) /*!< PORT15 OMR: PR14 Mask */
\r
13295 #define PORT15_OMR_PR15_Pos 31 /*!< PORT15 OMR: PR15 Position */
\r
13296 #define PORT15_OMR_PR15_Msk (0x01UL << PORT15_OMR_PR15_Pos) /*!< PORT15 OMR: PR15 Mask */
\r
13298 // -------------------------------------- PORT15_IOCR0 ------------------------------------------
\r
13299 #define PORT15_IOCR0_PC0_Pos 3 /*!< PORT15 IOCR0: PC0 Position */
\r
13300 #define PORT15_IOCR0_PC0_Msk (0x1fUL << PORT15_IOCR0_PC0_Pos) /*!< PORT15 IOCR0: PC0 Mask */
\r
13301 #define PORT15_IOCR0_PC1_Pos 11 /*!< PORT15 IOCR0: PC1 Position */
\r
13302 #define PORT15_IOCR0_PC1_Msk (0x1fUL << PORT15_IOCR0_PC1_Pos) /*!< PORT15 IOCR0: PC1 Mask */
\r
13303 #define PORT15_IOCR0_PC2_Pos 19 /*!< PORT15 IOCR0: PC2 Position */
\r
13304 #define PORT15_IOCR0_PC2_Msk (0x1fUL << PORT15_IOCR0_PC2_Pos) /*!< PORT15 IOCR0: PC2 Mask */
\r
13305 #define PORT15_IOCR0_PC3_Pos 27 /*!< PORT15 IOCR0: PC3 Position */
\r
13306 #define PORT15_IOCR0_PC3_Msk (0x1fUL << PORT15_IOCR0_PC3_Pos) /*!< PORT15 IOCR0: PC3 Mask */
\r
13308 // -------------------------------------- PORT15_IOCR4 ------------------------------------------
\r
13309 #define PORT15_IOCR4_PC4_Pos 3 /*!< PORT15 IOCR4: PC4 Position */
\r
13310 #define PORT15_IOCR4_PC4_Msk (0x1fUL << PORT15_IOCR4_PC4_Pos) /*!< PORT15 IOCR4: PC4 Mask */
\r
13311 #define PORT15_IOCR4_PC5_Pos 11 /*!< PORT15 IOCR4: PC5 Position */
\r
13312 #define PORT15_IOCR4_PC5_Msk (0x1fUL << PORT15_IOCR4_PC5_Pos) /*!< PORT15 IOCR4: PC5 Mask */
\r
13313 #define PORT15_IOCR4_PC6_Pos 19 /*!< PORT15 IOCR4: PC6 Position */
\r
13314 #define PORT15_IOCR4_PC6_Msk (0x1fUL << PORT15_IOCR4_PC6_Pos) /*!< PORT15 IOCR4: PC6 Mask */
\r
13315 #define PORT15_IOCR4_PC7_Pos 27 /*!< PORT15 IOCR4: PC7 Position */
\r
13316 #define PORT15_IOCR4_PC7_Msk (0x1fUL << PORT15_IOCR4_PC7_Pos) /*!< PORT15 IOCR4: PC7 Mask */
\r
13318 // -------------------------------------- PORT15_IOCR8 ------------------------------------------
\r
13319 #define PORT15_IOCR8_PC8_Pos 3 /*!< PORT15 IOCR8: PC8 Position */
\r
13320 #define PORT15_IOCR8_PC8_Msk (0x1fUL << PORT15_IOCR8_PC8_Pos) /*!< PORT15 IOCR8: PC8 Mask */
\r
13321 #define PORT15_IOCR8_PC9_Pos 11 /*!< PORT15 IOCR8: PC9 Position */
\r
13322 #define PORT15_IOCR8_PC9_Msk (0x1fUL << PORT15_IOCR8_PC9_Pos) /*!< PORT15 IOCR8: PC9 Mask */
\r
13323 #define PORT15_IOCR8_PC10_Pos 19 /*!< PORT15 IOCR8: PC10 Position */
\r
13324 #define PORT15_IOCR8_PC10_Msk (0x1fUL << PORT15_IOCR8_PC10_Pos) /*!< PORT15 IOCR8: PC10 Mask */
\r
13325 #define PORT15_IOCR8_PC11_Pos 27 /*!< PORT15 IOCR8: PC11 Position */
\r
13326 #define PORT15_IOCR8_PC11_Msk (0x1fUL << PORT15_IOCR8_PC11_Pos) /*!< PORT15 IOCR8: PC11 Mask */
\r
13328 // -------------------------------------- PORT15_IOCR12 -----------------------------------------
\r
13329 #define PORT15_IOCR12_PC12_Pos 3 /*!< PORT15 IOCR12: PC12 Position */
\r
13330 #define PORT15_IOCR12_PC12_Msk (0x1fUL << PORT15_IOCR12_PC12_Pos) /*!< PORT15 IOCR12: PC12 Mask */
\r
13331 #define PORT15_IOCR12_PC13_Pos 11 /*!< PORT15 IOCR12: PC13 Position */
\r
13332 #define PORT15_IOCR12_PC13_Msk (0x1fUL << PORT15_IOCR12_PC13_Pos) /*!< PORT15 IOCR12: PC13 Mask */
\r
13333 #define PORT15_IOCR12_PC14_Pos 19 /*!< PORT15 IOCR12: PC14 Position */
\r
13334 #define PORT15_IOCR12_PC14_Msk (0x1fUL << PORT15_IOCR12_PC14_Pos) /*!< PORT15 IOCR12: PC14 Mask */
\r
13335 #define PORT15_IOCR12_PC15_Pos 27 /*!< PORT15 IOCR12: PC15 Position */
\r
13336 #define PORT15_IOCR12_PC15_Msk (0x1fUL << PORT15_IOCR12_PC15_Pos) /*!< PORT15 IOCR12: PC15 Mask */
\r
13338 // ---------------------------------------- PORT15_IN -------------------------------------------
\r
13339 #define PORT15_IN_P0_Pos 0 /*!< PORT15 IN: P0 Position */
\r
13340 #define PORT15_IN_P0_Msk (0x01UL << PORT15_IN_P0_Pos) /*!< PORT15 IN: P0 Mask */
\r
13341 #define PORT15_IN_P1_Pos 1 /*!< PORT15 IN: P1 Position */
\r
13342 #define PORT15_IN_P1_Msk (0x01UL << PORT15_IN_P1_Pos) /*!< PORT15 IN: P1 Mask */
\r
13343 #define PORT15_IN_P2_Pos 2 /*!< PORT15 IN: P2 Position */
\r
13344 #define PORT15_IN_P2_Msk (0x01UL << PORT15_IN_P2_Pos) /*!< PORT15 IN: P2 Mask */
\r
13345 #define PORT15_IN_P3_Pos 3 /*!< PORT15 IN: P3 Position */
\r
13346 #define PORT15_IN_P3_Msk (0x01UL << PORT15_IN_P3_Pos) /*!< PORT15 IN: P3 Mask */
\r
13347 #define PORT15_IN_P4_Pos 4 /*!< PORT15 IN: P4 Position */
\r
13348 #define PORT15_IN_P4_Msk (0x01UL << PORT15_IN_P4_Pos) /*!< PORT15 IN: P4 Mask */
\r
13349 #define PORT15_IN_P5_Pos 5 /*!< PORT15 IN: P5 Position */
\r
13350 #define PORT15_IN_P5_Msk (0x01UL << PORT15_IN_P5_Pos) /*!< PORT15 IN: P5 Mask */
\r
13351 #define PORT15_IN_P6_Pos 6 /*!< PORT15 IN: P6 Position */
\r
13352 #define PORT15_IN_P6_Msk (0x01UL << PORT15_IN_P6_Pos) /*!< PORT15 IN: P6 Mask */
\r
13353 #define PORT15_IN_P7_Pos 7 /*!< PORT15 IN: P7 Position */
\r
13354 #define PORT15_IN_P7_Msk (0x01UL << PORT15_IN_P7_Pos) /*!< PORT15 IN: P7 Mask */
\r
13355 #define PORT15_IN_P8_Pos 8 /*!< PORT15 IN: P8 Position */
\r
13356 #define PORT15_IN_P8_Msk (0x01UL << PORT15_IN_P8_Pos) /*!< PORT15 IN: P8 Mask */
\r
13357 #define PORT15_IN_P9_Pos 9 /*!< PORT15 IN: P9 Position */
\r
13358 #define PORT15_IN_P9_Msk (0x01UL << PORT15_IN_P9_Pos) /*!< PORT15 IN: P9 Mask */
\r
13359 #define PORT15_IN_P10_Pos 10 /*!< PORT15 IN: P10 Position */
\r
13360 #define PORT15_IN_P10_Msk (0x01UL << PORT15_IN_P10_Pos) /*!< PORT15 IN: P10 Mask */
\r
13361 #define PORT15_IN_P11_Pos 11 /*!< PORT15 IN: P11 Position */
\r
13362 #define PORT15_IN_P11_Msk (0x01UL << PORT15_IN_P11_Pos) /*!< PORT15 IN: P11 Mask */
\r
13363 #define PORT15_IN_P12_Pos 12 /*!< PORT15 IN: P12 Position */
\r
13364 #define PORT15_IN_P12_Msk (0x01UL << PORT15_IN_P12_Pos) /*!< PORT15 IN: P12 Mask */
\r
13365 #define PORT15_IN_P13_Pos 13 /*!< PORT15 IN: P13 Position */
\r
13366 #define PORT15_IN_P13_Msk (0x01UL << PORT15_IN_P13_Pos) /*!< PORT15 IN: P13 Mask */
\r
13367 #define PORT15_IN_P14_Pos 14 /*!< PORT15 IN: P14 Position */
\r
13368 #define PORT15_IN_P14_Msk (0x01UL << PORT15_IN_P14_Pos) /*!< PORT15 IN: P14 Mask */
\r
13369 #define PORT15_IN_P15_Pos 15 /*!< PORT15 IN: P15 Position */
\r
13370 #define PORT15_IN_P15_Msk (0x01UL << PORT15_IN_P15_Pos) /*!< PORT15 IN: P15 Mask */
\r
13372 // -------------------------------------- PORT15_PDISC ------------------------------------------
\r
13373 #define PORT15_PDISC_PDIS2_Pos 2 /*!< PORT15 PDISC: PDIS2 Position */
\r
13374 #define PORT15_PDISC_PDIS2_Msk (0x01UL << PORT15_PDISC_PDIS2_Pos) /*!< PORT15 PDISC: PDIS2 Mask */
\r
13375 #define PORT15_PDISC_PDIS3_Pos 3 /*!< PORT15 PDISC: PDIS3 Position */
\r
13376 #define PORT15_PDISC_PDIS3_Msk (0x01UL << PORT15_PDISC_PDIS3_Pos) /*!< PORT15 PDISC: PDIS3 Mask */
\r
13377 #define PORT15_PDISC_PDIS4_Pos 4 /*!< PORT15 PDISC: PDIS4 Position */
\r
13378 #define PORT15_PDISC_PDIS4_Msk (0x01UL << PORT15_PDISC_PDIS4_Pos) /*!< PORT15 PDISC: PDIS4 Mask */
\r
13379 #define PORT15_PDISC_PDIS5_Pos 5 /*!< PORT15 PDISC: PDIS5 Position */
\r
13380 #define PORT15_PDISC_PDIS5_Msk (0x01UL << PORT15_PDISC_PDIS5_Pos) /*!< PORT15 PDISC: PDIS5 Mask */
\r
13381 #define PORT15_PDISC_PDIS6_Pos 6 /*!< PORT15 PDISC: PDIS6 Position */
\r
13382 #define PORT15_PDISC_PDIS6_Msk (0x01UL << PORT15_PDISC_PDIS6_Pos) /*!< PORT15 PDISC: PDIS6 Mask */
\r
13383 #define PORT15_PDISC_PDIS7_Pos 7 /*!< PORT15 PDISC: PDIS7 Position */
\r
13384 #define PORT15_PDISC_PDIS7_Msk (0x01UL << PORT15_PDISC_PDIS7_Pos) /*!< PORT15 PDISC: PDIS7 Mask */
\r
13385 #define PORT15_PDISC_PDIS8_Pos 8 /*!< PORT15 PDISC: PDIS8 Position */
\r
13386 #define PORT15_PDISC_PDIS8_Msk (0x01UL << PORT15_PDISC_PDIS8_Pos) /*!< PORT15 PDISC: PDIS8 Mask */
\r
13387 #define PORT15_PDISC_PDIS9_Pos 9 /*!< PORT15 PDISC: PDIS9 Position */
\r
13388 #define PORT15_PDISC_PDIS9_Msk (0x01UL << PORT15_PDISC_PDIS9_Pos) /*!< PORT15 PDISC: PDIS9 Mask */
\r
13389 #define PORT15_PDISC_PDIS12_Pos 12 /*!< PORT15 PDISC: PDIS12 Position */
\r
13390 #define PORT15_PDISC_PDIS12_Msk (0x01UL << PORT15_PDISC_PDIS12_Pos) /*!< PORT15 PDISC: PDIS12 Mask */
\r
13391 #define PORT15_PDISC_PDIS13_Pos 13 /*!< PORT15 PDISC: PDIS13 Position */
\r
13392 #define PORT15_PDISC_PDIS13_Msk (0x01UL << PORT15_PDISC_PDIS13_Pos) /*!< PORT15 PDISC: PDIS13 Mask */
\r
13393 #define PORT15_PDISC_PDIS14_Pos 14 /*!< PORT15 PDISC: PDIS14 Position */
\r
13394 #define PORT15_PDISC_PDIS14_Msk (0x01UL << PORT15_PDISC_PDIS14_Pos) /*!< PORT15 PDISC: PDIS14 Mask */
\r
13395 #define PORT15_PDISC_PDIS15_Pos 15 /*!< PORT15 PDISC: PDIS15 Position */
\r
13396 #define PORT15_PDISC_PDIS15_Msk (0x01UL << PORT15_PDISC_PDIS15_Pos) /*!< PORT15 PDISC: PDIS15 Mask */
\r
13398 // --------------------------------------- PORT15_PPS -------------------------------------------
\r
13399 #define PORT15_PPS_PPS0_Pos 0 /*!< PORT15 PPS: PPS0 Position */
\r
13400 #define PORT15_PPS_PPS0_Msk (0x01UL << PORT15_PPS_PPS0_Pos) /*!< PORT15 PPS: PPS0 Mask */
\r
13401 #define PORT15_PPS_PPS1_Pos 1 /*!< PORT15 PPS: PPS1 Position */
\r
13402 #define PORT15_PPS_PPS1_Msk (0x01UL << PORT15_PPS_PPS1_Pos) /*!< PORT15 PPS: PPS1 Mask */
\r
13403 #define PORT15_PPS_PPS2_Pos 2 /*!< PORT15 PPS: PPS2 Position */
\r
13404 #define PORT15_PPS_PPS2_Msk (0x01UL << PORT15_PPS_PPS2_Pos) /*!< PORT15 PPS: PPS2 Mask */
\r
13405 #define PORT15_PPS_PPS3_Pos 3 /*!< PORT15 PPS: PPS3 Position */
\r
13406 #define PORT15_PPS_PPS3_Msk (0x01UL << PORT15_PPS_PPS3_Pos) /*!< PORT15 PPS: PPS3 Mask */
\r
13407 #define PORT15_PPS_PPS4_Pos 4 /*!< PORT15 PPS: PPS4 Position */
\r
13408 #define PORT15_PPS_PPS4_Msk (0x01UL << PORT15_PPS_PPS4_Pos) /*!< PORT15 PPS: PPS4 Mask */
\r
13409 #define PORT15_PPS_PPS5_Pos 5 /*!< PORT15 PPS: PPS5 Position */
\r
13410 #define PORT15_PPS_PPS5_Msk (0x01UL << PORT15_PPS_PPS5_Pos) /*!< PORT15 PPS: PPS5 Mask */
\r
13411 #define PORT15_PPS_PPS6_Pos 6 /*!< PORT15 PPS: PPS6 Position */
\r
13412 #define PORT15_PPS_PPS6_Msk (0x01UL << PORT15_PPS_PPS6_Pos) /*!< PORT15 PPS: PPS6 Mask */
\r
13413 #define PORT15_PPS_PPS7_Pos 7 /*!< PORT15 PPS: PPS7 Position */
\r
13414 #define PORT15_PPS_PPS7_Msk (0x01UL << PORT15_PPS_PPS7_Pos) /*!< PORT15 PPS: PPS7 Mask */
\r
13415 #define PORT15_PPS_PPS8_Pos 8 /*!< PORT15 PPS: PPS8 Position */
\r
13416 #define PORT15_PPS_PPS8_Msk (0x01UL << PORT15_PPS_PPS8_Pos) /*!< PORT15 PPS: PPS8 Mask */
\r
13417 #define PORT15_PPS_PPS9_Pos 9 /*!< PORT15 PPS: PPS9 Position */
\r
13418 #define PORT15_PPS_PPS9_Msk (0x01UL << PORT15_PPS_PPS9_Pos) /*!< PORT15 PPS: PPS9 Mask */
\r
13419 #define PORT15_PPS_PPS10_Pos 10 /*!< PORT15 PPS: PPS10 Position */
\r
13420 #define PORT15_PPS_PPS10_Msk (0x01UL << PORT15_PPS_PPS10_Pos) /*!< PORT15 PPS: PPS10 Mask */
\r
13421 #define PORT15_PPS_PPS11_Pos 11 /*!< PORT15 PPS: PPS11 Position */
\r
13422 #define PORT15_PPS_PPS11_Msk (0x01UL << PORT15_PPS_PPS11_Pos) /*!< PORT15 PPS: PPS11 Mask */
\r
13423 #define PORT15_PPS_PPS12_Pos 12 /*!< PORT15 PPS: PPS12 Position */
\r
13424 #define PORT15_PPS_PPS12_Msk (0x01UL << PORT15_PPS_PPS12_Pos) /*!< PORT15 PPS: PPS12 Mask */
\r
13425 #define PORT15_PPS_PPS13_Pos 13 /*!< PORT15 PPS: PPS13 Position */
\r
13426 #define PORT15_PPS_PPS13_Msk (0x01UL << PORT15_PPS_PPS13_Pos) /*!< PORT15 PPS: PPS13 Mask */
\r
13427 #define PORT15_PPS_PPS14_Pos 14 /*!< PORT15 PPS: PPS14 Position */
\r
13428 #define PORT15_PPS_PPS14_Msk (0x01UL << PORT15_PPS_PPS14_Pos) /*!< PORT15 PPS: PPS14 Mask */
\r
13429 #define PORT15_PPS_PPS15_Pos 15 /*!< PORT15 PPS: PPS15 Position */
\r
13430 #define PORT15_PPS_PPS15_Msk (0x01UL << PORT15_PPS_PPS15_Pos) /*!< PORT15 PPS: PPS15 Mask */
\r
13432 // -------------------------------------- PORT15_HWSEL ------------------------------------------
\r
13433 #define PORT15_HWSEL_HW0_Pos 0 /*!< PORT15 HWSEL: HW0 Position */
\r
13434 #define PORT15_HWSEL_HW0_Msk (0x03UL << PORT15_HWSEL_HW0_Pos) /*!< PORT15 HWSEL: HW0 Mask */
\r
13435 #define PORT15_HWSEL_HW1_Pos 2 /*!< PORT15 HWSEL: HW1 Position */
\r
13436 #define PORT15_HWSEL_HW1_Msk (0x03UL << PORT15_HWSEL_HW1_Pos) /*!< PORT15 HWSEL: HW1 Mask */
\r
13437 #define PORT15_HWSEL_HW2_Pos 4 /*!< PORT15 HWSEL: HW2 Position */
\r
13438 #define PORT15_HWSEL_HW2_Msk (0x03UL << PORT15_HWSEL_HW2_Pos) /*!< PORT15 HWSEL: HW2 Mask */
\r
13439 #define PORT15_HWSEL_HW3_Pos 6 /*!< PORT15 HWSEL: HW3 Position */
\r
13440 #define PORT15_HWSEL_HW3_Msk (0x03UL << PORT15_HWSEL_HW3_Pos) /*!< PORT15 HWSEL: HW3 Mask */
\r
13441 #define PORT15_HWSEL_HW4_Pos 8 /*!< PORT15 HWSEL: HW4 Position */
\r
13442 #define PORT15_HWSEL_HW4_Msk (0x03UL << PORT15_HWSEL_HW4_Pos) /*!< PORT15 HWSEL: HW4 Mask */
\r
13443 #define PORT15_HWSEL_HW5_Pos 10 /*!< PORT15 HWSEL: HW5 Position */
\r
13444 #define PORT15_HWSEL_HW5_Msk (0x03UL << PORT15_HWSEL_HW5_Pos) /*!< PORT15 HWSEL: HW5 Mask */
\r
13445 #define PORT15_HWSEL_HW6_Pos 12 /*!< PORT15 HWSEL: HW6 Position */
\r
13446 #define PORT15_HWSEL_HW6_Msk (0x03UL << PORT15_HWSEL_HW6_Pos) /*!< PORT15 HWSEL: HW6 Mask */
\r
13447 #define PORT15_HWSEL_HW7_Pos 14 /*!< PORT15 HWSEL: HW7 Position */
\r
13448 #define PORT15_HWSEL_HW7_Msk (0x03UL << PORT15_HWSEL_HW7_Pos) /*!< PORT15 HWSEL: HW7 Mask */
\r
13449 #define PORT15_HWSEL_HW8_Pos 16 /*!< PORT15 HWSEL: HW8 Position */
\r
13450 #define PORT15_HWSEL_HW8_Msk (0x03UL << PORT15_HWSEL_HW8_Pos) /*!< PORT15 HWSEL: HW8 Mask */
\r
13451 #define PORT15_HWSEL_HW9_Pos 18 /*!< PORT15 HWSEL: HW9 Position */
\r
13452 #define PORT15_HWSEL_HW9_Msk (0x03UL << PORT15_HWSEL_HW9_Pos) /*!< PORT15 HWSEL: HW9 Mask */
\r
13453 #define PORT15_HWSEL_HW10_Pos 20 /*!< PORT15 HWSEL: HW10 Position */
\r
13454 #define PORT15_HWSEL_HW10_Msk (0x03UL << PORT15_HWSEL_HW10_Pos) /*!< PORT15 HWSEL: HW10 Mask */
\r
13455 #define PORT15_HWSEL_HW11_Pos 22 /*!< PORT15 HWSEL: HW11 Position */
\r
13456 #define PORT15_HWSEL_HW11_Msk (0x03UL << PORT15_HWSEL_HW11_Pos) /*!< PORT15 HWSEL: HW11 Mask */
\r
13457 #define PORT15_HWSEL_HW12_Pos 24 /*!< PORT15 HWSEL: HW12 Position */
\r
13458 #define PORT15_HWSEL_HW12_Msk (0x03UL << PORT15_HWSEL_HW12_Pos) /*!< PORT15 HWSEL: HW12 Mask */
\r
13459 #define PORT15_HWSEL_HW13_Pos 26 /*!< PORT15 HWSEL: HW13 Position */
\r
13460 #define PORT15_HWSEL_HW13_Msk (0x03UL << PORT15_HWSEL_HW13_Pos) /*!< PORT15 HWSEL: HW13 Mask */
\r
13461 #define PORT15_HWSEL_HW14_Pos 28 /*!< PORT15 HWSEL: HW14 Position */
\r
13462 #define PORT15_HWSEL_HW14_Msk (0x03UL << PORT15_HWSEL_HW14_Pos) /*!< PORT15 HWSEL: HW14 Mask */
\r
13463 #define PORT15_HWSEL_HW15_Pos 30 /*!< PORT15 HWSEL: HW15 Position */
\r
13464 #define PORT15_HWSEL_HW15_Msk (0x03UL << PORT15_HWSEL_HW15_Pos) /*!< PORT15 HWSEL: HW15 Mask */
\r
13467 /*** POSIFx Bit Fileds *******************/
\r
13468 /***************************************************************************/
\r
13471 /* POSIF_PCONF = Architectural Overview configuration*/
\r
13472 #define POSIF_PCONF_FSEL_Pos (0U)
\r
13473 #define POSIF_PCONF_FSEL_Msk (0x00000003U << POSIF_PCONF_FSEL_Pos)
\r
13475 #define POSIF_PCONF_QDCM_Pos (2U)
\r
13476 #define POSIF_PCONF_QDCM_Msk (0x00000001U << POSIF_PCONF_QDCM_Pos)
\r
13478 #define POSIF_PCONF_HIDG_Pos (4U)
\r
13479 #define POSIF_PCONF_HIDG_Msk (0x00000001U << POSIF_PCONF_HIDG_Pos)
\r
13481 #define POSIF_PCONF_MCUE_Pos (5U)
\r
13482 #define POSIF_PCONF_MCUE_Msk (0x00000001U << POSIF_PCONF_MCUE_Pos)
\r
13484 #define POSIF_PCONF_INSEL0_Pos (8U)
\r
13485 #define POSIF_PCONF_INSEL0_Msk (0x00000003U << POSIF_PCONF_INSEL0_Pos)
\r
13487 #define POSIF_PCONF_INSEL1_Pos (10U)
\r
13488 #define POSIF_PCONF_INSEL1_Msk (0x00000003U << POSIF_PCONF_INSEL1_Pos)
\r
13490 #define POSIF_PCONF_INSEL2_Pos (12U)
\r
13491 #define POSIF_PCONF_INSEL2_Msk (0x00000003U << POSIF_PCONF_INSEL2_Pos)
\r
13493 #define POSIF_PCONF_DSEL_Pos (16U)
\r
13494 #define POSIF_PCONF_DSEL_Msk (0x00000001U << POSIF_PCONF_DSEL_Pos)
\r
13496 #define POSIF_PCONF_SPES_Pos (17U)
\r
13497 #define POSIF_PCONF_SPES_Msk (0x00000001U << POSIF_PCONF_SPES_Pos)
\r
13499 #define POSIF_PCONF_MSETS_Pos (18U)
\r
13500 #define POSIF_PCONF_MSETS_Msk (0x00000007U << POSIF_PCONF_MSETS_Pos)
\r
13502 #define POSIF_PCONF_MSES_Pos (21U)
\r
13503 #define POSIF_PCONF_MSES_Msk (0x00000001U << POSIF_PCONF_MSES_Pos)
\r
13505 #define POSIF_PCONF_MSYNS_Pos (22U)
\r
13506 #define POSIF_PCONF_MSYNS_Msk (0x00000003U << POSIF_PCONF_MSYNS_Pos)
\r
13508 #define POSIF_PCONF_EWIS_Pos (24U)
\r
13509 #define POSIF_PCONF_EWIS_Msk (0x00000003U << POSIF_PCONF_EWIS_Pos)
\r
13511 #define POSIF_PCONF_EWIE_Pos (26U)
\r
13512 #define POSIF_PCONF_EWIE_Msk (0x00000001U << POSIF_PCONF_EWIE_Pos)
\r
13514 #define POSIF_PCONF_EWIL_Pos (27U)
\r
13515 #define POSIF_PCONF_EWIL_Msk (0x00000001U << POSIF_PCONF_EWIL_Pos)
\r
13517 #define POSIF_PCONF_LPC_Pos (28U)
\r
13518 #define POSIF_PCONF_LPC_Msk (0x00000007U << POSIF_PCONF_LPC_Pos)
\r
13520 /* POSIF_PSUS = Architectural Overview Suspend Config*/
\r
13521 #define POSIF_PSUS_QSUS_Pos (0U)
\r
13522 #define POSIF_PSUS_QSUS_Msk (0x00000003U << POSIF_PSUS_QSUS_Pos)
\r
13524 #define POSIF_PSUS_MSUS_Pos (2U)
\r
13525 #define POSIF_PSUS_MSUS_Msk (0x00000003U << POSIF_PSUS_MSUS_Pos)
\r
13527 /* POSIF_PRUNS = Architectural Overview Run Bit Set*/
\r
13528 #define POSIF_PRUNS_SRB_Pos (0U)
\r
13529 #define POSIF_PRUNS_SRB_Msk (0x00000001U << POSIF_PRUNS_SRB_Pos)
\r
13531 /* POSIF_PRUNC = Architectural Overview Run Bit Clear*/
\r
13532 #define POSIF_PRUNC_CRB_Pos (0U)
\r
13533 #define POSIF_PRUNC_CRB_Msk (0x00000001U << POSIF_PRUNC_CRB_Pos)
\r
13535 #define POSIF_PRUNC_CSM_Pos (1U)
\r
13536 #define POSIF_PRUNC_CSM_Msk (0x00000001U << POSIF_PRUNC_CSM_Pos)
\r
13538 /* POSIF_PRUN = Architectural Overview Run Bit Status*/
\r
13539 #define POSIF_PRUN_RB_Pos (0U)
\r
13540 #define POSIF_PRUN_RB_Msk (0x00000001U << POSIF_PRUN_RB_Pos)
\r
13542 /* POSIF_MIDR = Module Identification register*/
\r
13543 #define POSIF_MIDR_MODR_Pos (0U)
\r
13544 #define POSIF_MIDR_MODR_Msk (0x000000FFU << POSIF_MIDR_MODR_Pos)
\r
13546 #define POSIF_MIDR_MODT_Pos (8U)
\r
13547 #define POSIF_MIDR_MODT_Msk (0x000000FFU << POSIF_MIDR_MODT_Pos)
\r
13549 #define POSIF_MIDR_MODN_Pos (16U)
\r
13550 #define POSIF_MIDR_MODN_Msk (0x0000FFFFU << POSIF_MIDR_MODN_Pos)
\r
13552 /* POSIF_HALP = Hall Sensor Patterns*/
\r
13553 #define POSIF_HALP_HCP_Pos (0U)
\r
13554 #define POSIF_HALP_HCP_Msk (0x00000007U << POSIF_HALP_HCP_Pos)
\r
13556 #define POSIF_HALP_HEP_Pos (3U)
\r
13557 #define POSIF_HALP_HEP_Msk (0x00000007U << POSIF_HALP_HEP_Pos)
\r
13559 /* POSIF_HALPS = Hall Sensor Shadow Patterns*/
\r
13560 #define POSIF_HALPS_HCPS_Pos (0U)
\r
13561 #define POSIF_HALPS_HCPS_Msk (0x00000007U << POSIF_HALPS_HCPS_Pos)
\r
13563 #define POSIF_HALPS_HEPS_Pos (3U)
\r
13564 #define POSIF_HALPS_HEPS_Msk (0x00000007U << POSIF_HALPS_HEPS_Pos)
\r
13566 /* POSIF_MCM = Multi Channel Pattern*/
\r
13567 #define POSIF_MCM_MCMP_Pos (0U)
\r
13568 #define POSIF_MCM_MCMP_Msk (0x0000FFFFU << POSIF_MCM_MCMP_Pos)
\r
13570 /* POSIF_MCSM = Multi Channel Shadow Pattern*/
\r
13571 #define POSIF_MCSM_MCMPS_Pos (0U)
\r
13572 #define POSIF_MCSM_MCMPS_Msk (0x0000FFFFU << POSIF_MCSM_MCMPS_Pos)
\r
13574 /* POSIF_MCMS = Multi Channel Pattern Control set*/
\r
13575 #define POSIF_MCMS_MNPS_Pos (0U)
\r
13576 #define POSIF_MCMS_MNPS_Msk (0x00000001U << POSIF_MCMS_MNPS_Pos)
\r
13578 #define POSIF_MCMS_STHR_Pos (1U)
\r
13579 #define POSIF_MCMS_STHR_Msk (0x00000001U << POSIF_MCMS_STHR_Pos)
\r
13581 #define POSIF_MCMS_STMR_Pos (2U)
\r
13582 #define POSIF_MCMS_STMR_Msk (0x00000001U << POSIF_MCMS_STMR_Pos)
\r
13584 /* POSIF_MCMC = Multi Channel Pattern Control clear*/
\r
13585 #define POSIF_MCMC_MNPC_Pos (0U)
\r
13586 #define POSIF_MCMC_MNPC_Msk (0x00000001U << POSIF_MCMC_MNPC_Pos)
\r
13588 #define POSIF_MCMC_MPC_Pos (1U)
\r
13589 #define POSIF_MCMC_MPC_Msk (0x00000001U << POSIF_MCMC_MPC_Pos)
\r
13591 /* POSIF_MCMF = Multi Channel Pattern Control flag*/
\r
13592 #define POSIF_MCMF_MSS_Pos (0U)
\r
13593 #define POSIF_MCMF_MSS_Msk (0x00000001U << POSIF_MCMF_MSS_Pos)
\r
13595 /* POSIF_QDC = Quadrature Decoder Control*/
\r
13596 #define POSIF_QDC_PALS_Pos (0U)
\r
13597 #define POSIF_QDC_PALS_Msk (0x00000001U << POSIF_QDC_PALS_Pos)
\r
13599 #define POSIF_QDC_PBLS_Pos (1U)
\r
13600 #define POSIF_QDC_PBLS_Msk (0x00000001U << POSIF_QDC_PBLS_Pos)
\r
13602 #define POSIF_QDC_PHS_Pos (2U)
\r
13603 #define POSIF_QDC_PHS_Msk (0x00000001U << POSIF_QDC_PHS_Pos)
\r
13605 #define POSIF_QDC_ICM_Pos (4U)
\r
13606 #define POSIF_QDC_ICM_Msk (0x00000003U << POSIF_QDC_ICM_Pos)
\r
13608 #define POSIF_QDC_DVAL_Pos (8U)
\r
13609 #define POSIF_QDC_DVAL_Msk (0x00000001U << POSIF_QDC_DVAL_Pos)
\r
13611 /* POSIF_PFLG = Architectural Overview Interrupt Flags*/
\r
13612 #define POSIF_PFLG_CHES_Pos (0U)
\r
13613 #define POSIF_PFLG_CHES_Msk (0x00000001U << POSIF_PFLG_CHES_Pos)
\r
13615 #define POSIF_PFLG_WHES_Pos (1U)
\r
13616 #define POSIF_PFLG_WHES_Msk (0x00000001U << POSIF_PFLG_WHES_Pos)
\r
13618 #define POSIF_PFLG_HIES_Pos (2U)
\r
13619 #define POSIF_PFLG_HIES_Msk (0x00000001U << POSIF_PFLG_HIES_Pos)
\r
13621 #define POSIF_PFLG_MSTS_Pos (4U)
\r
13622 #define POSIF_PFLG_MSTS_Msk (0x00000001U << POSIF_PFLG_MSTS_Pos)
\r
13624 #define POSIF_PFLG_INDXS_Pos (8U)
\r
13625 #define POSIF_PFLG_INDXS_Msk (0x00000001U << POSIF_PFLG_INDXS_Pos)
\r
13627 #define POSIF_PFLG_ERRS_Pos (9U)
\r
13628 #define POSIF_PFLG_ERRS_Msk (0x00000001U << POSIF_PFLG_ERRS_Pos)
\r
13630 #define POSIF_PFLG_CNTS_Pos (10U)
\r
13631 #define POSIF_PFLG_CNTS_Msk (0x00000001U << POSIF_PFLG_CNTS_Pos)
\r
13633 #define POSIF_PFLG_DIRS_Pos (11U)
\r
13634 #define POSIF_PFLG_DIRS_Msk (0x00000001U << POSIF_PFLG_DIRS_Pos)
\r
13636 #define POSIF_PFLG_PCLKS_Pos (12U)
\r
13637 #define POSIF_PFLG_PCLKS_Msk (0x00000001U << POSIF_PFLG_PCLKS_Pos)
\r
13639 /* POSIF_PFLGE = Architectural Overview Interrupt Enable*/
\r
13640 #define POSIF_PFLGE_ECHE_Pos (0U)
\r
13641 #define POSIF_PFLGE_ECHE_Msk (0x00000001U << POSIF_PFLGE_ECHE_Pos)
\r
13643 #define POSIF_PFLGE_EWHE_Pos (1U)
\r
13644 #define POSIF_PFLGE_EWHE_Msk (0x00000001U << POSIF_PFLGE_EWHE_Pos)
\r
13646 #define POSIF_PFLGE_EHIE_Pos (2U)
\r
13647 #define POSIF_PFLGE_EHIE_Msk (0x00000001U << POSIF_PFLGE_EHIE_Pos)
\r
13649 #define POSIF_PFLGE_EMST_Pos (4U)
\r
13650 #define POSIF_PFLGE_EMST_Msk (0x00000001U << POSIF_PFLGE_EMST_Pos)
\r
13652 #define POSIF_PFLGE_EINDX_Pos (8U)
\r
13653 #define POSIF_PFLGE_EINDX_Msk (0x00000001U << POSIF_PFLGE_EINDX_Pos)
\r
13655 #define POSIF_PFLGE_EERR_Pos (9U)
\r
13656 #define POSIF_PFLGE_EERR_Msk (0x00000001U << POSIF_PFLGE_EERR_Pos)
\r
13658 #define POSIF_PFLGE_ECNT_Pos (10U)
\r
13659 #define POSIF_PFLGE_ECNT_Msk (0x00000001U << POSIF_PFLGE_ECNT_Pos)
\r
13661 #define POSIF_PFLGE_EDIR_Pos (11U)
\r
13662 #define POSIF_PFLGE_EDIR_Msk (0x00000001U << POSIF_PFLGE_EDIR_Pos)
\r
13664 #define POSIF_PFLGE_EPCLK_Pos (12U)
\r
13665 #define POSIF_PFLGE_EPCLK_Msk (0x00000001U << POSIF_PFLGE_EPCLK_Pos)
\r
13667 #define POSIF_PFLGE_CHESEL_Pos (16U)
\r
13668 #define POSIF_PFLGE_CHESEL_Msk (0x00000001U << POSIF_PFLGE_CHESEL_Pos)
\r
13670 #define POSIF_PFLGE_WHESEL_Pos (17U)
\r
13671 #define POSIF_PFLGE_WHESEL_Msk (0x00000001U << POSIF_PFLGE_WHESEL_Pos)
\r
13673 #define POSIF_PFLGE_HIESEL_Pos (18U)
\r
13674 #define POSIF_PFLGE_HIESEL_Msk (0x00000001U << POSIF_PFLGE_HIESEL_Pos)
\r
13676 #define POSIF_PFLGE_MSTSEL_Pos (20U)
\r
13677 #define POSIF_PFLGE_MSTSEL_Msk (0x00000001U << POSIF_PFLGE_MSTSEL_Pos)
\r
13679 #define POSIF_PFLGE_INDSEL_Pos (24U)
\r
13680 #define POSIF_PFLGE_INDSEL_Msk (0x00000001U << POSIF_PFLGE_INDSEL_Pos)
\r
13682 #define POSIF_PFLGE_ERRSEL_Pos (25U)
\r
13683 #define POSIF_PFLGE_ERRSEL_Msk (0x00000001U << POSIF_PFLGE_ERRSEL_Pos)
\r
13685 #define POSIF_PFLGE_CNTSEL_Pos (26U)
\r
13686 #define POSIF_PFLGE_CNTSEL_Msk (0x00000001U << POSIF_PFLGE_CNTSEL_Pos)
\r
13688 #define POSIF_PFLGE_DIRSEL_Pos (27U)
\r
13689 #define POSIF_PFLGE_DIRSEL_Msk (0x00000001U << POSIF_PFLGE_DIRSEL_Pos)
\r
13691 #define POSIF_PFLGE_PCLSEL_Pos (28U)
\r
13692 #define POSIF_PFLGE_PCLSEL_Msk (0x00000001U << POSIF_PFLGE_PCLSEL_Pos)
\r
13694 /* POSIF_SPFLG = Architectural Overview Interrupt Set*/
\r
13695 #define POSIF_SPFLG_SCHE_Pos (0U)
\r
13696 #define POSIF_SPFLG_SCHE_Msk (0x00000001U << POSIF_SPFLG_SCHE_Pos)
\r
13698 #define POSIF_SPFLG_SWHE_Pos (1U)
\r
13699 #define POSIF_SPFLG_SWHE_Msk (0x00000001U << POSIF_SPFLG_SWHE_Pos)
\r
13701 #define POSIF_SPFLG_SHIE_Pos (2U)
\r
13702 #define POSIF_SPFLG_SHIE_Msk (0x00000001U << POSIF_SPFLG_SHIE_Pos)
\r
13704 #define POSIF_SPFLG_SMST_Pos (4U)
\r
13705 #define POSIF_SPFLG_SMST_Msk (0x00000001U << POSIF_SPFLG_SMST_Pos)
\r
13707 #define POSIF_SPFLG_SINDX_Pos (8U)
\r
13708 #define POSIF_SPFLG_SINDX_Msk (0x00000001U << POSIF_SPFLG_SINDX_Pos)
\r
13710 #define POSIF_SPFLG_SERR_Pos (9U)
\r
13711 #define POSIF_SPFLG_SERR_Msk (0x00000001U << POSIF_SPFLG_SERR_Pos)
\r
13713 #define POSIF_SPFLG_SCNT_Pos (10U)
\r
13714 #define POSIF_SPFLG_SCNT_Msk (0x00000001U << POSIF_SPFLG_SCNT_Pos)
\r
13716 #define POSIF_SPFLG_SDIR_Pos (11U)
\r
13717 #define POSIF_SPFLG_SDIR_Msk (0x00000001U << POSIF_SPFLG_SDIR_Pos)
\r
13719 #define POSIF_SPFLG_SPCLK_Pos (12U)
\r
13720 #define POSIF_SPFLG_SPCLK_Msk (0x00000001U << POSIF_SPFLG_SPCLK_Pos)
\r
13722 /* POSIF_RPFLG = Architectural Overview Interrupt Clear*/
\r
13723 #define POSIF_RPFLG_RCHE_Pos (0U)
\r
13724 #define POSIF_RPFLG_RCHE_Msk (0x00000001U << POSIF_RPFLG_RCHE_Pos)
\r
13726 #define POSIF_RPFLG_RWHE_Pos (1U)
\r
13727 #define POSIF_RPFLG_RWHE_Msk (0x00000001U << POSIF_RPFLG_RWHE_Pos)
\r
13729 #define POSIF_RPFLG_RHIE_Pos (2U)
\r
13730 #define POSIF_RPFLG_RHIE_Msk (0x00000001U << POSIF_RPFLG_RHIE_Pos)
\r
13732 #define POSIF_RPFLG_RMST_Pos (4U)
\r
13733 #define POSIF_RPFLG_RMST_Msk (0x00000001U << POSIF_RPFLG_RMST_Pos)
\r
13735 #define POSIF_RPFLG_RINDX_Pos (8U)
\r
13736 #define POSIF_RPFLG_RINDX_Msk (0x00000001U << POSIF_RPFLG_RINDX_Pos)
\r
13738 #define POSIF_RPFLG_RERR_Pos (9U)
\r
13739 #define POSIF_RPFLG_RERR_Msk (0x00000001U << POSIF_RPFLG_RERR_Pos)
\r
13741 #define POSIF_RPFLG_RCNT_Pos (10U)
\r
13742 #define POSIF_RPFLG_RCNT_Msk (0x00000001U << POSIF_RPFLG_RCNT_Pos)
\r
13744 #define POSIF_RPFLG_RDIR_Pos (11U)
\r
13745 #define POSIF_RPFLG_RDIR_Msk (0x00000001U << POSIF_RPFLG_RDIR_Pos)
\r
13747 #define POSIF_RPFLG_RPCLK_Pos (12U)
\r
13748 #define POSIF_RPFLG_RPCLK_Msk (0x00000001U << POSIF_RPFLG_RPCLK_Pos)
\r
13750 // ------------------------------------------------------------------------------------------------
\r
13751 // ----- PPB Position & Mask -----
\r
13752 // ------------------------------------------------------------------------------------------------
\r
13754 // ---------------------------------------- PPB_ACTLR -------------------------------------------
\r
13755 #define PPB_ACTLR_DISMCYCINT_Pos 0 /*!< PPB ACTLR: DISMCYCINT Position */
\r
13756 #define PPB_ACTLR_DISMCYCINT_Msk (0x01UL << PPB_ACTLR_DISMCYCINT_Pos) /*!< PPB ACTLR: DISMCYCINT Mask */
\r
13757 #define PPB_ACTLR_DISDEFWBUF_Pos 1 /*!< PPB ACTLR: DISDEFWBUF Position */
\r
13758 #define PPB_ACTLR_DISDEFWBUF_Msk (0x01UL << PPB_ACTLR_DISDEFWBUF_Pos) /*!< PPB ACTLR: DISDEFWBUF Mask */
\r
13759 #define PPB_ACTLR_DISFOLD_Pos 2 /*!< PPB ACTLR: DISFOLD Position */
\r
13760 #define PPB_ACTLR_DISFOLD_Msk (0x01UL << PPB_ACTLR_DISFOLD_Pos) /*!< PPB ACTLR: DISFOLD Mask */
\r
13761 #define PPB_ACTLR_DISFPCA_Pos 8 /*!< PPB ACTLR: DISFPCA Position */
\r
13762 #define PPB_ACTLR_DISFPCA_Msk (0x01UL << PPB_ACTLR_DISFPCA_Pos) /*!< PPB ACTLR: DISFPCA Mask */
\r
13763 #define PPB_ACTLR_DISOOFP_Pos 9 /*!< PPB ACTLR: DISOOFP Position */
\r
13764 #define PPB_ACTLR_DISOOFP_Msk (0x01UL << PPB_ACTLR_DISOOFP_Pos) /*!< PPB ACTLR: DISOOFP Mask */
\r
13766 // -------------------------------------- PPB_SYST_CSR ------------------------------------------
\r
13767 #define PPB_SYST_CSR_ENABLE_Pos 0 /*!< PPB SYST_CSR: ENABLE Position */
\r
13768 #define PPB_SYST_CSR_ENABLE_Msk (0x01UL << PPB_SYST_CSR_ENABLE_Pos) /*!< PPB SYST_CSR: ENABLE Mask */
\r
13769 #define PPB_SYST_CSR_TICKINT_Pos 1 /*!< PPB SYST_CSR: TICKINT Position */
\r
13770 #define PPB_SYST_CSR_TICKINT_Msk (0x01UL << PPB_SYST_CSR_TICKINT_Pos) /*!< PPB SYST_CSR: TICKINT Mask */
\r
13771 #define PPB_SYST_CSR_CLKSOURCE_Pos 2 /*!< PPB SYST_CSR: CLKSOURCE Position */
\r
13772 #define PPB_SYST_CSR_CLKSOURCE_Msk (0x01UL << PPB_SYST_CSR_CLKSOURCE_Pos) /*!< PPB SYST_CSR: CLKSOURCE Mask */
\r
13773 #define PPB_SYST_CSR_COUNTFLAG_Pos 16 /*!< PPB SYST_CSR: COUNTFLAG Position */
\r
13774 #define PPB_SYST_CSR_COUNTFLAG_Msk (0x01UL << PPB_SYST_CSR_COUNTFLAG_Pos) /*!< PPB SYST_CSR: COUNTFLAG Mask */
\r
13776 // -------------------------------------- PPB_SYST_RVR ------------------------------------------
\r
13777 #define PPB_SYST_RVR_RELOAD_Pos 0 /*!< PPB SYST_RVR: RELOAD Position */
\r
13778 #define PPB_SYST_RVR_RELOAD_Msk (0x00ffffffUL << PPB_SYST_RVR_RELOAD_Pos) /*!< PPB SYST_RVR: RELOAD Mask */
\r
13780 // -------------------------------------- PPB_SYST_CVR ------------------------------------------
\r
13781 #define PPB_SYST_CVR_CURRENT_Pos 0 /*!< PPB SYST_CVR: CURRENT Position */
\r
13782 #define PPB_SYST_CVR_CURRENT_Msk (0x00ffffffUL << PPB_SYST_CVR_CURRENT_Pos) /*!< PPB SYST_CVR: CURRENT Mask */
\r
13784 // ------------------------------------- PPB_SYST_CALIB -----------------------------------------
\r
13785 #define PPB_SYST_CALIB_TENMS_Pos 0 /*!< PPB SYST_CALIB: TENMS Position */
\r
13786 #define PPB_SYST_CALIB_TENMS_Msk (0x00ffffffUL << PPB_SYST_CALIB_TENMS_Pos) /*!< PPB SYST_CALIB: TENMS Mask */
\r
13787 #define PPB_SYST_CALIB_SKEW_Pos 30 /*!< PPB SYST_CALIB: SKEW Position */
\r
13788 #define PPB_SYST_CALIB_SKEW_Msk (0x01UL << PPB_SYST_CALIB_SKEW_Pos) /*!< PPB SYST_CALIB: SKEW Mask */
\r
13789 #define PPB_SYST_CALIB_NOREF_Pos 31 /*!< PPB SYST_CALIB: NOREF Position */
\r
13790 #define PPB_SYST_CALIB_NOREF_Msk (0x01UL << PPB_SYST_CALIB_NOREF_Pos) /*!< PPB SYST_CALIB: NOREF Mask */
\r
13792 // ------------------------------------- PPB_NVIC_ISER0 -----------------------------------------
\r
13793 #define PPB_NVIC_ISER0_SETENA_Pos 0 /*!< PPB NVIC_ISER0: SETENA Position */
\r
13794 #define PPB_NVIC_ISER0_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER0_SETENA_Pos) /*!< PPB NVIC_ISER0: SETENA Mask */
\r
13796 // ------------------------------------- PPB_NVIC_ISER1 -----------------------------------------
\r
13797 #define PPB_NVIC_ISER1_SETENA_Pos 0 /*!< PPB NVIC_ISER1: SETENA Position */
\r
13798 #define PPB_NVIC_ISER1_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER1_SETENA_Pos) /*!< PPB NVIC_ISER1: SETENA Mask */
\r
13800 // ------------------------------------- PPB_NVIC_ISER2 -----------------------------------------
\r
13801 #define PPB_NVIC_ISER2_SETENA_Pos 0 /*!< PPB NVIC_ISER2: SETENA Position */
\r
13802 #define PPB_NVIC_ISER2_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER2_SETENA_Pos) /*!< PPB NVIC_ISER2: SETENA Mask */
\r
13804 // ------------------------------------- PPB_NVIC_ISER3 -----------------------------------------
\r
13805 #define PPB_NVIC_ISER3_SETENA_Pos 0 /*!< PPB NVIC_ISER3: SETENA Position */
\r
13806 #define PPB_NVIC_ISER3_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER3_SETENA_Pos) /*!< PPB NVIC_ISER3: SETENA Mask */
\r
13808 // ------------------------------------- PPB_NVIC_ISCER0 ----------------------------------------
\r
13809 #define PPB_NVIC_ISCER0_CLRENA_Pos 0 /*!< PPB NVIC_ISCER0: CLRENA Position */
\r
13810 #define PPB_NVIC_ISCER0_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ISCER0_CLRENA_Pos) /*!< PPB NVIC_ISCER0: CLRENA Mask */
\r
13812 // ------------------------------------- PPB_NVIC_ISCER1 ----------------------------------------
\r
13813 #define PPB_NVIC_ISCER1_CLRENA_Pos 0 /*!< PPB NVIC_ISCER1: CLRENA Position */
\r
13814 #define PPB_NVIC_ISCER1_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ISCER1_CLRENA_Pos) /*!< PPB NVIC_ISCER1: CLRENA Mask */
\r
13816 // ------------------------------------- PPB_NVIC_ISCER2 ----------------------------------------
\r
13817 #define PPB_NVIC_ISCER2_CLRENA_Pos 0 /*!< PPB NVIC_ISCER2: CLRENA Position */
\r
13818 #define PPB_NVIC_ISCER2_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ISCER2_CLRENA_Pos) /*!< PPB NVIC_ISCER2: CLRENA Mask */
\r
13820 // ------------------------------------- PPB_NVIC_ISCER3 ----------------------------------------
\r
13821 #define PPB_NVIC_ISCER3_CLRENA_Pos 0 /*!< PPB NVIC_ISCER3: CLRENA Position */
\r
13822 #define PPB_NVIC_ISCER3_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ISCER3_CLRENA_Pos) /*!< PPB NVIC_ISCER3: CLRENA Mask */
\r
13824 // ------------------------------------- PPB_NVIC_ISSPR0 ----------------------------------------
\r
13825 #define PPB_NVIC_ISSPR0_SETPEND_Pos 0 /*!< PPB NVIC_ISSPR0: SETPEND Position */
\r
13826 #define PPB_NVIC_ISSPR0_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISSPR0_SETPEND_Pos) /*!< PPB NVIC_ISSPR0: SETPEND Mask */
\r
13828 // ------------------------------------- PPB_NVIC_ISSPR1 ----------------------------------------
\r
13829 #define PPB_NVIC_ISSPR1_SETPEND_Pos 0 /*!< PPB NVIC_ISSPR1: SETPEND Position */
\r
13830 #define PPB_NVIC_ISSPR1_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISSPR1_SETPEND_Pos) /*!< PPB NVIC_ISSPR1: SETPEND Mask */
\r
13832 // ------------------------------------- PPB_NVIC_ISSPR2 ----------------------------------------
\r
13833 #define PPB_NVIC_ISSPR2_SETPEND_Pos 0 /*!< PPB NVIC_ISSPR2: SETPEND Position */
\r
13834 #define PPB_NVIC_ISSPR2_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISSPR2_SETPEND_Pos) /*!< PPB NVIC_ISSPR2: SETPEND Mask */
\r
13836 // ------------------------------------- PPB_NVIC_ISSPR3 ----------------------------------------
\r
13837 #define PPB_NVIC_ISSPR3_SETPEND_Pos 0 /*!< PPB NVIC_ISSPR3: SETPEND Position */
\r
13838 #define PPB_NVIC_ISSPR3_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISSPR3_SETPEND_Pos) /*!< PPB NVIC_ISSPR3: SETPEND Mask */
\r
13840 // ------------------------------------- PPB_NVIC_ICPR0 -----------------------------------------
\r
13841 #define PPB_NVIC_ICPR0_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR0: CLRPEND Position */
\r
13842 #define PPB_NVIC_ICPR0_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR0_CLRPEND_Pos) /*!< PPB NVIC_ICPR0: CLRPEND Mask */
\r
13844 // ------------------------------------- PPB_NVIC_ICPR1 -----------------------------------------
\r
13845 #define PPB_NVIC_ICPR1_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR1: CLRPEND Position */
\r
13846 #define PPB_NVIC_ICPR1_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR1_CLRPEND_Pos) /*!< PPB NVIC_ICPR1: CLRPEND Mask */
\r
13848 // ------------------------------------- PPB_NVIC_ICPR2 -----------------------------------------
\r
13849 #define PPB_NVIC_ICPR2_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR2: CLRPEND Position */
\r
13850 #define PPB_NVIC_ICPR2_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR2_CLRPEND_Pos) /*!< PPB NVIC_ICPR2: CLRPEND Mask */
\r
13852 // ------------------------------------- PPB_NVIC_ICPR3 -----------------------------------------
\r
13853 #define PPB_NVIC_ICPR3_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR3: CLRPEND Position */
\r
13854 #define PPB_NVIC_ICPR3_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR3_CLRPEND_Pos) /*!< PPB NVIC_ICPR3: CLRPEND Mask */
\r
13856 // ------------------------------------- PPB_NVIC_IABR0 -----------------------------------------
\r
13857 #define PPB_NVIC_IABR0_ACTIVE_Pos 0 /*!< PPB NVIC_IABR0: ACTIVE Position */
\r
13858 #define PPB_NVIC_IABR0_ACTIVE_Msk (0xffffffffUL << PPB_NVIC_IABR0_ACTIVE_Pos) /*!< PPB NVIC_IABR0: ACTIVE Mask */
\r
13860 // ------------------------------------- PPB_NVIC_IABR1 -----------------------------------------
\r
13861 #define PPB_NVIC_IABR1_ACTIVE_Pos 0 /*!< PPB NVIC_IABR1: ACTIVE Position */
\r
13862 #define PPB_NVIC_IABR1_ACTIVE_Msk (0xffffffffUL << PPB_NVIC_IABR1_ACTIVE_Pos) /*!< PPB NVIC_IABR1: ACTIVE Mask */
\r
13864 // ------------------------------------- PPB_NVIC_IABR2 -----------------------------------------
\r
13865 #define PPB_NVIC_IABR2_ACTIVE_Pos 0 /*!< PPB NVIC_IABR2: ACTIVE Position */
\r
13866 #define PPB_NVIC_IABR2_ACTIVE_Msk (0xffffffffUL << PPB_NVIC_IABR2_ACTIVE_Pos) /*!< PPB NVIC_IABR2: ACTIVE Mask */
\r
13868 // ------------------------------------- PPB_NVIC_IABR3 -----------------------------------------
\r
13869 #define PPB_NVIC_IABR3_ACTIVE_Pos 0 /*!< PPB NVIC_IABR3: ACTIVE Position */
\r
13870 #define PPB_NVIC_IABR3_ACTIVE_Msk (0xffffffffUL << PPB_NVIC_IABR3_ACTIVE_Pos) /*!< PPB NVIC_IABR3: ACTIVE Mask */
\r
13872 // -------------------------------------- PPB_NVIC_IPR0 -----------------------------------------
\r
13873 #define PPB_NVIC_IPR0_PRI_0_Pos 0 /*!< PPB NVIC_IPR0: PRI_0 Position */
\r
13874 #define PPB_NVIC_IPR0_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_0_Pos) /*!< PPB NVIC_IPR0: PRI_0 Mask */
\r
13875 #define PPB_NVIC_IPR0_PRI_1_Pos 8 /*!< PPB NVIC_IPR0: PRI_1 Position */
\r
13876 #define PPB_NVIC_IPR0_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_1_Pos) /*!< PPB NVIC_IPR0: PRI_1 Mask */
\r
13877 #define PPB_NVIC_IPR0_PRI_2_Pos 16 /*!< PPB NVIC_IPR0: PRI_2 Position */
\r
13878 #define PPB_NVIC_IPR0_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_2_Pos) /*!< PPB NVIC_IPR0: PRI_2 Mask */
\r
13879 #define PPB_NVIC_IPR0_PRI_3_Pos 24 /*!< PPB NVIC_IPR0: PRI_3 Position */
\r
13880 #define PPB_NVIC_IPR0_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_3_Pos) /*!< PPB NVIC_IPR0: PRI_3 Mask */
\r
13882 // -------------------------------------- PPB_NVIC_IPR1 -----------------------------------------
\r
13883 #define PPB_NVIC_IPR1_PRI_0_Pos 0 /*!< PPB NVIC_IPR1: PRI_0 Position */
\r
13884 #define PPB_NVIC_IPR1_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_0_Pos) /*!< PPB NVIC_IPR1: PRI_0 Mask */
\r
13885 #define PPB_NVIC_IPR1_PRI_1_Pos 8 /*!< PPB NVIC_IPR1: PRI_1 Position */
\r
13886 #define PPB_NVIC_IPR1_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_1_Pos) /*!< PPB NVIC_IPR1: PRI_1 Mask */
\r
13887 #define PPB_NVIC_IPR1_PRI_2_Pos 16 /*!< PPB NVIC_IPR1: PRI_2 Position */
\r
13888 #define PPB_NVIC_IPR1_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_2_Pos) /*!< PPB NVIC_IPR1: PRI_2 Mask */
\r
13889 #define PPB_NVIC_IPR1_PRI_3_Pos 24 /*!< PPB NVIC_IPR1: PRI_3 Position */
\r
13890 #define PPB_NVIC_IPR1_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_3_Pos) /*!< PPB NVIC_IPR1: PRI_3 Mask */
\r
13892 // -------------------------------------- PPB_NVIC_IPR2 -----------------------------------------
\r
13893 #define PPB_NVIC_IPR2_PRI_0_Pos 0 /*!< PPB NVIC_IPR2: PRI_0 Position */
\r
13894 #define PPB_NVIC_IPR2_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_0_Pos) /*!< PPB NVIC_IPR2: PRI_0 Mask */
\r
13895 #define PPB_NVIC_IPR2_PRI_1_Pos 8 /*!< PPB NVIC_IPR2: PRI_1 Position */
\r
13896 #define PPB_NVIC_IPR2_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_1_Pos) /*!< PPB NVIC_IPR2: PRI_1 Mask */
\r
13897 #define PPB_NVIC_IPR2_PRI_2_Pos 16 /*!< PPB NVIC_IPR2: PRI_2 Position */
\r
13898 #define PPB_NVIC_IPR2_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_2_Pos) /*!< PPB NVIC_IPR2: PRI_2 Mask */
\r
13899 #define PPB_NVIC_IPR2_PRI_3_Pos 24 /*!< PPB NVIC_IPR2: PRI_3 Position */
\r
13900 #define PPB_NVIC_IPR2_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_3_Pos) /*!< PPB NVIC_IPR2: PRI_3 Mask */
\r
13902 // -------------------------------------- PPB_NVIC_IPR3 -----------------------------------------
\r
13903 #define PPB_NVIC_IPR3_PRI_0_Pos 0 /*!< PPB NVIC_IPR3: PRI_0 Position */
\r
13904 #define PPB_NVIC_IPR3_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_0_Pos) /*!< PPB NVIC_IPR3: PRI_0 Mask */
\r
13905 #define PPB_NVIC_IPR3_PRI_1_Pos 8 /*!< PPB NVIC_IPR3: PRI_1 Position */
\r
13906 #define PPB_NVIC_IPR3_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_1_Pos) /*!< PPB NVIC_IPR3: PRI_1 Mask */
\r
13907 #define PPB_NVIC_IPR3_PRI_2_Pos 16 /*!< PPB NVIC_IPR3: PRI_2 Position */
\r
13908 #define PPB_NVIC_IPR3_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_2_Pos) /*!< PPB NVIC_IPR3: PRI_2 Mask */
\r
13909 #define PPB_NVIC_IPR3_PRI_3_Pos 24 /*!< PPB NVIC_IPR3: PRI_3 Position */
\r
13910 #define PPB_NVIC_IPR3_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_3_Pos) /*!< PPB NVIC_IPR3: PRI_3 Mask */
\r
13912 // -------------------------------------- PPB_NVIC_IPR4 -----------------------------------------
\r
13913 #define PPB_NVIC_IPR4_PRI_0_Pos 0 /*!< PPB NVIC_IPR4: PRI_0 Position */
\r
13914 #define PPB_NVIC_IPR4_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_0_Pos) /*!< PPB NVIC_IPR4: PRI_0 Mask */
\r
13915 #define PPB_NVIC_IPR4_PRI_1_Pos 8 /*!< PPB NVIC_IPR4: PRI_1 Position */
\r
13916 #define PPB_NVIC_IPR4_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_1_Pos) /*!< PPB NVIC_IPR4: PRI_1 Mask */
\r
13917 #define PPB_NVIC_IPR4_PRI_2_Pos 16 /*!< PPB NVIC_IPR4: PRI_2 Position */
\r
13918 #define PPB_NVIC_IPR4_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_2_Pos) /*!< PPB NVIC_IPR4: PRI_2 Mask */
\r
13919 #define PPB_NVIC_IPR4_PRI_3_Pos 24 /*!< PPB NVIC_IPR4: PRI_3 Position */
\r
13920 #define PPB_NVIC_IPR4_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_3_Pos) /*!< PPB NVIC_IPR4: PRI_3 Mask */
\r
13922 // -------------------------------------- PPB_NVIC_IPR5 -----------------------------------------
\r
13923 #define PPB_NVIC_IPR5_PRI_0_Pos 0 /*!< PPB NVIC_IPR5: PRI_0 Position */
\r
13924 #define PPB_NVIC_IPR5_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_0_Pos) /*!< PPB NVIC_IPR5: PRI_0 Mask */
\r
13925 #define PPB_NVIC_IPR5_PRI_1_Pos 8 /*!< PPB NVIC_IPR5: PRI_1 Position */
\r
13926 #define PPB_NVIC_IPR5_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_1_Pos) /*!< PPB NVIC_IPR5: PRI_1 Mask */
\r
13927 #define PPB_NVIC_IPR5_PRI_2_Pos 16 /*!< PPB NVIC_IPR5: PRI_2 Position */
\r
13928 #define PPB_NVIC_IPR5_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_2_Pos) /*!< PPB NVIC_IPR5: PRI_2 Mask */
\r
13929 #define PPB_NVIC_IPR5_PRI_3_Pos 24 /*!< PPB NVIC_IPR5: PRI_3 Position */
\r
13930 #define PPB_NVIC_IPR5_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_3_Pos) /*!< PPB NVIC_IPR5: PRI_3 Mask */
\r
13932 // -------------------------------------- PPB_NVIC_IPR6 -----------------------------------------
\r
13933 #define PPB_NVIC_IPR6_PRI_0_Pos 0 /*!< PPB NVIC_IPR6: PRI_0 Position */
\r
13934 #define PPB_NVIC_IPR6_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_0_Pos) /*!< PPB NVIC_IPR6: PRI_0 Mask */
\r
13935 #define PPB_NVIC_IPR6_PRI_1_Pos 8 /*!< PPB NVIC_IPR6: PRI_1 Position */
\r
13936 #define PPB_NVIC_IPR6_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_1_Pos) /*!< PPB NVIC_IPR6: PRI_1 Mask */
\r
13937 #define PPB_NVIC_IPR6_PRI_2_Pos 16 /*!< PPB NVIC_IPR6: PRI_2 Position */
\r
13938 #define PPB_NVIC_IPR6_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_2_Pos) /*!< PPB NVIC_IPR6: PRI_2 Mask */
\r
13939 #define PPB_NVIC_IPR6_PRI_3_Pos 24 /*!< PPB NVIC_IPR6: PRI_3 Position */
\r
13940 #define PPB_NVIC_IPR6_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_3_Pos) /*!< PPB NVIC_IPR6: PRI_3 Mask */
\r
13942 // -------------------------------------- PPB_NVIC_IPR7 -----------------------------------------
\r
13943 #define PPB_NVIC_IPR7_PRI_0_Pos 0 /*!< PPB NVIC_IPR7: PRI_0 Position */
\r
13944 #define PPB_NVIC_IPR7_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_0_Pos) /*!< PPB NVIC_IPR7: PRI_0 Mask */
\r
13945 #define PPB_NVIC_IPR7_PRI_1_Pos 8 /*!< PPB NVIC_IPR7: PRI_1 Position */
\r
13946 #define PPB_NVIC_IPR7_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_1_Pos) /*!< PPB NVIC_IPR7: PRI_1 Mask */
\r
13947 #define PPB_NVIC_IPR7_PRI_2_Pos 16 /*!< PPB NVIC_IPR7: PRI_2 Position */
\r
13948 #define PPB_NVIC_IPR7_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_2_Pos) /*!< PPB NVIC_IPR7: PRI_2 Mask */
\r
13949 #define PPB_NVIC_IPR7_PRI_3_Pos 24 /*!< PPB NVIC_IPR7: PRI_3 Position */
\r
13950 #define PPB_NVIC_IPR7_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_3_Pos) /*!< PPB NVIC_IPR7: PRI_3 Mask */
\r
13952 // -------------------------------------- PPB_NVIC_IPR8 -----------------------------------------
\r
13953 #define PPB_NVIC_IPR8_PRI_0_Pos 0 /*!< PPB NVIC_IPR8: PRI_0 Position */
\r
13954 #define PPB_NVIC_IPR8_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR8_PRI_0_Pos) /*!< PPB NVIC_IPR8: PRI_0 Mask */
\r
13955 #define PPB_NVIC_IPR8_PRI_1_Pos 8 /*!< PPB NVIC_IPR8: PRI_1 Position */
\r
13956 #define PPB_NVIC_IPR8_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR8_PRI_1_Pos) /*!< PPB NVIC_IPR8: PRI_1 Mask */
\r
13957 #define PPB_NVIC_IPR8_PRI_2_Pos 16 /*!< PPB NVIC_IPR8: PRI_2 Position */
\r
13958 #define PPB_NVIC_IPR8_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR8_PRI_2_Pos) /*!< PPB NVIC_IPR8: PRI_2 Mask */
\r
13959 #define PPB_NVIC_IPR8_PRI_3_Pos 24 /*!< PPB NVIC_IPR8: PRI_3 Position */
\r
13960 #define PPB_NVIC_IPR8_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR8_PRI_3_Pos) /*!< PPB NVIC_IPR8: PRI_3 Mask */
\r
13962 // -------------------------------------- PPB_NVIC_IPR9 -----------------------------------------
\r
13963 #define PPB_NVIC_IPR9_PRI_0_Pos 0 /*!< PPB NVIC_IPR9: PRI_0 Position */
\r
13964 #define PPB_NVIC_IPR9_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR9_PRI_0_Pos) /*!< PPB NVIC_IPR9: PRI_0 Mask */
\r
13965 #define PPB_NVIC_IPR9_PRI_1_Pos 8 /*!< PPB NVIC_IPR9: PRI_1 Position */
\r
13966 #define PPB_NVIC_IPR9_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR9_PRI_1_Pos) /*!< PPB NVIC_IPR9: PRI_1 Mask */
\r
13967 #define PPB_NVIC_IPR9_PRI_2_Pos 16 /*!< PPB NVIC_IPR9: PRI_2 Position */
\r
13968 #define PPB_NVIC_IPR9_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR9_PRI_2_Pos) /*!< PPB NVIC_IPR9: PRI_2 Mask */
\r
13969 #define PPB_NVIC_IPR9_PRI_3_Pos 24 /*!< PPB NVIC_IPR9: PRI_3 Position */
\r
13970 #define PPB_NVIC_IPR9_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR9_PRI_3_Pos) /*!< PPB NVIC_IPR9: PRI_3 Mask */
\r
13972 // ------------------------------------- PPB_NVIC_IPR10 -----------------------------------------
\r
13973 #define PPB_NVIC_IPR10_PRI_0_Pos 0 /*!< PPB NVIC_IPR10: PRI_0 Position */
\r
13974 #define PPB_NVIC_IPR10_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR10_PRI_0_Pos) /*!< PPB NVIC_IPR10: PRI_0 Mask */
\r
13975 #define PPB_NVIC_IPR10_PRI_1_Pos 8 /*!< PPB NVIC_IPR10: PRI_1 Position */
\r
13976 #define PPB_NVIC_IPR10_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR10_PRI_1_Pos) /*!< PPB NVIC_IPR10: PRI_1 Mask */
\r
13977 #define PPB_NVIC_IPR10_PRI_2_Pos 16 /*!< PPB NVIC_IPR10: PRI_2 Position */
\r
13978 #define PPB_NVIC_IPR10_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR10_PRI_2_Pos) /*!< PPB NVIC_IPR10: PRI_2 Mask */
\r
13979 #define PPB_NVIC_IPR10_PRI_3_Pos 24 /*!< PPB NVIC_IPR10: PRI_3 Position */
\r
13980 #define PPB_NVIC_IPR10_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR10_PRI_3_Pos) /*!< PPB NVIC_IPR10: PRI_3 Mask */
\r
13982 // ------------------------------------- PPB_NVIC_IPR11 -----------------------------------------
\r
13983 #define PPB_NVIC_IPR11_PRI_0_Pos 0 /*!< PPB NVIC_IPR11: PRI_0 Position */
\r
13984 #define PPB_NVIC_IPR11_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR11_PRI_0_Pos) /*!< PPB NVIC_IPR11: PRI_0 Mask */
\r
13985 #define PPB_NVIC_IPR11_PRI_1_Pos 8 /*!< PPB NVIC_IPR11: PRI_1 Position */
\r
13986 #define PPB_NVIC_IPR11_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR11_PRI_1_Pos) /*!< PPB NVIC_IPR11: PRI_1 Mask */
\r
13987 #define PPB_NVIC_IPR11_PRI_2_Pos 16 /*!< PPB NVIC_IPR11: PRI_2 Position */
\r
13988 #define PPB_NVIC_IPR11_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR11_PRI_2_Pos) /*!< PPB NVIC_IPR11: PRI_2 Mask */
\r
13989 #define PPB_NVIC_IPR11_PRI_3_Pos 24 /*!< PPB NVIC_IPR11: PRI_3 Position */
\r
13990 #define PPB_NVIC_IPR11_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR11_PRI_3_Pos) /*!< PPB NVIC_IPR11: PRI_3 Mask */
\r
13992 // ------------------------------------- PPB_NVIC_IPR12 -----------------------------------------
\r
13993 #define PPB_NVIC_IPR12_PRI_0_Pos 0 /*!< PPB NVIC_IPR12: PRI_0 Position */
\r
13994 #define PPB_NVIC_IPR12_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR12_PRI_0_Pos) /*!< PPB NVIC_IPR12: PRI_0 Mask */
\r
13995 #define PPB_NVIC_IPR12_PRI_1_Pos 8 /*!< PPB NVIC_IPR12: PRI_1 Position */
\r
13996 #define PPB_NVIC_IPR12_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR12_PRI_1_Pos) /*!< PPB NVIC_IPR12: PRI_1 Mask */
\r
13997 #define PPB_NVIC_IPR12_PRI_2_Pos 16 /*!< PPB NVIC_IPR12: PRI_2 Position */
\r
13998 #define PPB_NVIC_IPR12_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR12_PRI_2_Pos) /*!< PPB NVIC_IPR12: PRI_2 Mask */
\r
13999 #define PPB_NVIC_IPR12_PRI_3_Pos 24 /*!< PPB NVIC_IPR12: PRI_3 Position */
\r
14000 #define PPB_NVIC_IPR12_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR12_PRI_3_Pos) /*!< PPB NVIC_IPR12: PRI_3 Mask */
\r
14002 // ------------------------------------- PPB_NVIC_IPR13 -----------------------------------------
\r
14003 #define PPB_NVIC_IPR13_PRI_0_Pos 0 /*!< PPB NVIC_IPR13: PRI_0 Position */
\r
14004 #define PPB_NVIC_IPR13_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR13_PRI_0_Pos) /*!< PPB NVIC_IPR13: PRI_0 Mask */
\r
14005 #define PPB_NVIC_IPR13_PRI_1_Pos 8 /*!< PPB NVIC_IPR13: PRI_1 Position */
\r
14006 #define PPB_NVIC_IPR13_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR13_PRI_1_Pos) /*!< PPB NVIC_IPR13: PRI_1 Mask */
\r
14007 #define PPB_NVIC_IPR13_PRI_2_Pos 16 /*!< PPB NVIC_IPR13: PRI_2 Position */
\r
14008 #define PPB_NVIC_IPR13_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR13_PRI_2_Pos) /*!< PPB NVIC_IPR13: PRI_2 Mask */
\r
14009 #define PPB_NVIC_IPR13_PRI_3_Pos 24 /*!< PPB NVIC_IPR13: PRI_3 Position */
\r
14010 #define PPB_NVIC_IPR13_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR13_PRI_3_Pos) /*!< PPB NVIC_IPR13: PRI_3 Mask */
\r
14012 // ------------------------------------- PPB_NVIC_IPR14 -----------------------------------------
\r
14013 #define PPB_NVIC_IPR14_PRI_0_Pos 0 /*!< PPB NVIC_IPR14: PRI_0 Position */
\r
14014 #define PPB_NVIC_IPR14_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR14_PRI_0_Pos) /*!< PPB NVIC_IPR14: PRI_0 Mask */
\r
14015 #define PPB_NVIC_IPR14_PRI_1_Pos 8 /*!< PPB NVIC_IPR14: PRI_1 Position */
\r
14016 #define PPB_NVIC_IPR14_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR14_PRI_1_Pos) /*!< PPB NVIC_IPR14: PRI_1 Mask */
\r
14017 #define PPB_NVIC_IPR14_PRI_2_Pos 16 /*!< PPB NVIC_IPR14: PRI_2 Position */
\r
14018 #define PPB_NVIC_IPR14_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR14_PRI_2_Pos) /*!< PPB NVIC_IPR14: PRI_2 Mask */
\r
14019 #define PPB_NVIC_IPR14_PRI_3_Pos 24 /*!< PPB NVIC_IPR14: PRI_3 Position */
\r
14020 #define PPB_NVIC_IPR14_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR14_PRI_3_Pos) /*!< PPB NVIC_IPR14: PRI_3 Mask */
\r
14022 // ------------------------------------- PPB_NVIC_IPR15 -----------------------------------------
\r
14023 #define PPB_NVIC_IPR15_PRI_0_Pos 0 /*!< PPB NVIC_IPR15: PRI_0 Position */
\r
14024 #define PPB_NVIC_IPR15_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR15_PRI_0_Pos) /*!< PPB NVIC_IPR15: PRI_0 Mask */
\r
14025 #define PPB_NVIC_IPR15_PRI_1_Pos 8 /*!< PPB NVIC_IPR15: PRI_1 Position */
\r
14026 #define PPB_NVIC_IPR15_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR15_PRI_1_Pos) /*!< PPB NVIC_IPR15: PRI_1 Mask */
\r
14027 #define PPB_NVIC_IPR15_PRI_2_Pos 16 /*!< PPB NVIC_IPR15: PRI_2 Position */
\r
14028 #define PPB_NVIC_IPR15_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR15_PRI_2_Pos) /*!< PPB NVIC_IPR15: PRI_2 Mask */
\r
14029 #define PPB_NVIC_IPR15_PRI_3_Pos 24 /*!< PPB NVIC_IPR15: PRI_3 Position */
\r
14030 #define PPB_NVIC_IPR15_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR15_PRI_3_Pos) /*!< PPB NVIC_IPR15: PRI_3 Mask */
\r
14032 // ------------------------------------- PPB_NVIC_IPR16 -----------------------------------------
\r
14033 #define PPB_NVIC_IPR16_PRI_0_Pos 0 /*!< PPB NVIC_IPR16: PRI_0 Position */
\r
14034 #define PPB_NVIC_IPR16_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR16_PRI_0_Pos) /*!< PPB NVIC_IPR16: PRI_0 Mask */
\r
14035 #define PPB_NVIC_IPR16_PRI_1_Pos 8 /*!< PPB NVIC_IPR16: PRI_1 Position */
\r
14036 #define PPB_NVIC_IPR16_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR16_PRI_1_Pos) /*!< PPB NVIC_IPR16: PRI_1 Mask */
\r
14037 #define PPB_NVIC_IPR16_PRI_2_Pos 16 /*!< PPB NVIC_IPR16: PRI_2 Position */
\r
14038 #define PPB_NVIC_IPR16_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR16_PRI_2_Pos) /*!< PPB NVIC_IPR16: PRI_2 Mask */
\r
14039 #define PPB_NVIC_IPR16_PRI_3_Pos 24 /*!< PPB NVIC_IPR16: PRI_3 Position */
\r
14040 #define PPB_NVIC_IPR16_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR16_PRI_3_Pos) /*!< PPB NVIC_IPR16: PRI_3 Mask */
\r
14042 // ------------------------------------- PPB_NVIC_IPR17 -----------------------------------------
\r
14043 #define PPB_NVIC_IPR17_PRI_0_Pos 0 /*!< PPB NVIC_IPR17: PRI_0 Position */
\r
14044 #define PPB_NVIC_IPR17_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR17_PRI_0_Pos) /*!< PPB NVIC_IPR17: PRI_0 Mask */
\r
14045 #define PPB_NVIC_IPR17_PRI_1_Pos 8 /*!< PPB NVIC_IPR17: PRI_1 Position */
\r
14046 #define PPB_NVIC_IPR17_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR17_PRI_1_Pos) /*!< PPB NVIC_IPR17: PRI_1 Mask */
\r
14047 #define PPB_NVIC_IPR17_PRI_2_Pos 16 /*!< PPB NVIC_IPR17: PRI_2 Position */
\r
14048 #define PPB_NVIC_IPR17_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR17_PRI_2_Pos) /*!< PPB NVIC_IPR17: PRI_2 Mask */
\r
14049 #define PPB_NVIC_IPR17_PRI_3_Pos 24 /*!< PPB NVIC_IPR17: PRI_3 Position */
\r
14050 #define PPB_NVIC_IPR17_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR17_PRI_3_Pos) /*!< PPB NVIC_IPR17: PRI_3 Mask */
\r
14052 // ------------------------------------- PPB_NVIC_IPR18 -----------------------------------------
\r
14053 #define PPB_NVIC_IPR18_PRI_0_Pos 0 /*!< PPB NVIC_IPR18: PRI_0 Position */
\r
14054 #define PPB_NVIC_IPR18_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR18_PRI_0_Pos) /*!< PPB NVIC_IPR18: PRI_0 Mask */
\r
14055 #define PPB_NVIC_IPR18_PRI_1_Pos 8 /*!< PPB NVIC_IPR18: PRI_1 Position */
\r
14056 #define PPB_NVIC_IPR18_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR18_PRI_1_Pos) /*!< PPB NVIC_IPR18: PRI_1 Mask */
\r
14057 #define PPB_NVIC_IPR18_PRI_2_Pos 16 /*!< PPB NVIC_IPR18: PRI_2 Position */
\r
14058 #define PPB_NVIC_IPR18_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR18_PRI_2_Pos) /*!< PPB NVIC_IPR18: PRI_2 Mask */
\r
14059 #define PPB_NVIC_IPR18_PRI_3_Pos 24 /*!< PPB NVIC_IPR18: PRI_3 Position */
\r
14060 #define PPB_NVIC_IPR18_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR18_PRI_3_Pos) /*!< PPB NVIC_IPR18: PRI_3 Mask */
\r
14062 // ------------------------------------- PPB_NVIC_IPR19 -----------------------------------------
\r
14063 #define PPB_NVIC_IPR19_PRI_0_Pos 0 /*!< PPB NVIC_IPR19: PRI_0 Position */
\r
14064 #define PPB_NVIC_IPR19_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR19_PRI_0_Pos) /*!< PPB NVIC_IPR19: PRI_0 Mask */
\r
14065 #define PPB_NVIC_IPR19_PRI_1_Pos 8 /*!< PPB NVIC_IPR19: PRI_1 Position */
\r
14066 #define PPB_NVIC_IPR19_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR19_PRI_1_Pos) /*!< PPB NVIC_IPR19: PRI_1 Mask */
\r
14067 #define PPB_NVIC_IPR19_PRI_2_Pos 16 /*!< PPB NVIC_IPR19: PRI_2 Position */
\r
14068 #define PPB_NVIC_IPR19_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR19_PRI_2_Pos) /*!< PPB NVIC_IPR19: PRI_2 Mask */
\r
14069 #define PPB_NVIC_IPR19_PRI_3_Pos 24 /*!< PPB NVIC_IPR19: PRI_3 Position */
\r
14070 #define PPB_NVIC_IPR19_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR19_PRI_3_Pos) /*!< PPB NVIC_IPR19: PRI_3 Mask */
\r
14072 // ------------------------------------- PPB_NVIC_IPR20 -----------------------------------------
\r
14073 #define PPB_NVIC_IPR20_PRI_0_Pos 0 /*!< PPB NVIC_IPR20: PRI_0 Position */
\r
14074 #define PPB_NVIC_IPR20_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR20_PRI_0_Pos) /*!< PPB NVIC_IPR20: PRI_0 Mask */
\r
14075 #define PPB_NVIC_IPR20_PRI_1_Pos 8 /*!< PPB NVIC_IPR20: PRI_1 Position */
\r
14076 #define PPB_NVIC_IPR20_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR20_PRI_1_Pos) /*!< PPB NVIC_IPR20: PRI_1 Mask */
\r
14077 #define PPB_NVIC_IPR20_PRI_2_Pos 16 /*!< PPB NVIC_IPR20: PRI_2 Position */
\r
14078 #define PPB_NVIC_IPR20_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR20_PRI_2_Pos) /*!< PPB NVIC_IPR20: PRI_2 Mask */
\r
14079 #define PPB_NVIC_IPR20_PRI_3_Pos 24 /*!< PPB NVIC_IPR20: PRI_3 Position */
\r
14080 #define PPB_NVIC_IPR20_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR20_PRI_3_Pos) /*!< PPB NVIC_IPR20: PRI_3 Mask */
\r
14082 // ------------------------------------- PPB_NVIC_IPR21 -----------------------------------------
\r
14083 #define PPB_NVIC_IPR21_PRI_0_Pos 0 /*!< PPB NVIC_IPR21: PRI_0 Position */
\r
14084 #define PPB_NVIC_IPR21_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR21_PRI_0_Pos) /*!< PPB NVIC_IPR21: PRI_0 Mask */
\r
14085 #define PPB_NVIC_IPR21_PRI_1_Pos 8 /*!< PPB NVIC_IPR21: PRI_1 Position */
\r
14086 #define PPB_NVIC_IPR21_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR21_PRI_1_Pos) /*!< PPB NVIC_IPR21: PRI_1 Mask */
\r
14087 #define PPB_NVIC_IPR21_PRI_2_Pos 16 /*!< PPB NVIC_IPR21: PRI_2 Position */
\r
14088 #define PPB_NVIC_IPR21_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR21_PRI_2_Pos) /*!< PPB NVIC_IPR21: PRI_2 Mask */
\r
14089 #define PPB_NVIC_IPR21_PRI_3_Pos 24 /*!< PPB NVIC_IPR21: PRI_3 Position */
\r
14090 #define PPB_NVIC_IPR21_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR21_PRI_3_Pos) /*!< PPB NVIC_IPR21: PRI_3 Mask */
\r
14092 // ------------------------------------- PPB_NVIC_IPR22 -----------------------------------------
\r
14093 #define PPB_NVIC_IPR22_PRI_0_Pos 0 /*!< PPB NVIC_IPR22: PRI_0 Position */
\r
14094 #define PPB_NVIC_IPR22_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR22_PRI_0_Pos) /*!< PPB NVIC_IPR22: PRI_0 Mask */
\r
14095 #define PPB_NVIC_IPR22_PRI_1_Pos 8 /*!< PPB NVIC_IPR22: PRI_1 Position */
\r
14096 #define PPB_NVIC_IPR22_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR22_PRI_1_Pos) /*!< PPB NVIC_IPR22: PRI_1 Mask */
\r
14097 #define PPB_NVIC_IPR22_PRI_2_Pos 16 /*!< PPB NVIC_IPR22: PRI_2 Position */
\r
14098 #define PPB_NVIC_IPR22_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR22_PRI_2_Pos) /*!< PPB NVIC_IPR22: PRI_2 Mask */
\r
14099 #define PPB_NVIC_IPR22_PRI_3_Pos 24 /*!< PPB NVIC_IPR22: PRI_3 Position */
\r
14100 #define PPB_NVIC_IPR22_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR22_PRI_3_Pos) /*!< PPB NVIC_IPR22: PRI_3 Mask */
\r
14102 // ------------------------------------- PPB_NVIC_IPR23 -----------------------------------------
\r
14103 #define PPB_NVIC_IPR23_PRI_0_Pos 0 /*!< PPB NVIC_IPR23: PRI_0 Position */
\r
14104 #define PPB_NVIC_IPR23_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR23_PRI_0_Pos) /*!< PPB NVIC_IPR23: PRI_0 Mask */
\r
14105 #define PPB_NVIC_IPR23_PRI_1_Pos 8 /*!< PPB NVIC_IPR23: PRI_1 Position */
\r
14106 #define PPB_NVIC_IPR23_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR23_PRI_1_Pos) /*!< PPB NVIC_IPR23: PRI_1 Mask */
\r
14107 #define PPB_NVIC_IPR23_PRI_2_Pos 16 /*!< PPB NVIC_IPR23: PRI_2 Position */
\r
14108 #define PPB_NVIC_IPR23_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR23_PRI_2_Pos) /*!< PPB NVIC_IPR23: PRI_2 Mask */
\r
14109 #define PPB_NVIC_IPR23_PRI_3_Pos 24 /*!< PPB NVIC_IPR23: PRI_3 Position */
\r
14110 #define PPB_NVIC_IPR23_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR23_PRI_3_Pos) /*!< PPB NVIC_IPR23: PRI_3 Mask */
\r
14112 // ------------------------------------- PPB_NVIC_IPR24 -----------------------------------------
\r
14113 #define PPB_NVIC_IPR24_PRI_0_Pos 0 /*!< PPB NVIC_IPR24: PRI_0 Position */
\r
14114 #define PPB_NVIC_IPR24_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR24_PRI_0_Pos) /*!< PPB NVIC_IPR24: PRI_0 Mask */
\r
14115 #define PPB_NVIC_IPR24_PRI_1_Pos 8 /*!< PPB NVIC_IPR24: PRI_1 Position */
\r
14116 #define PPB_NVIC_IPR24_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR24_PRI_1_Pos) /*!< PPB NVIC_IPR24: PRI_1 Mask */
\r
14117 #define PPB_NVIC_IPR24_PRI_2_Pos 16 /*!< PPB NVIC_IPR24: PRI_2 Position */
\r
14118 #define PPB_NVIC_IPR24_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR24_PRI_2_Pos) /*!< PPB NVIC_IPR24: PRI_2 Mask */
\r
14119 #define PPB_NVIC_IPR24_PRI_3_Pos 24 /*!< PPB NVIC_IPR24: PRI_3 Position */
\r
14120 #define PPB_NVIC_IPR24_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR24_PRI_3_Pos) /*!< PPB NVIC_IPR24: PRI_3 Mask */
\r
14122 // ------------------------------------- PPB_NVIC_IPR25 -----------------------------------------
\r
14123 #define PPB_NVIC_IPR25_PRI_0_Pos 0 /*!< PPB NVIC_IPR25: PRI_0 Position */
\r
14124 #define PPB_NVIC_IPR25_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR25_PRI_0_Pos) /*!< PPB NVIC_IPR25: PRI_0 Mask */
\r
14125 #define PPB_NVIC_IPR25_PRI_1_Pos 8 /*!< PPB NVIC_IPR25: PRI_1 Position */
\r
14126 #define PPB_NVIC_IPR25_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR25_PRI_1_Pos) /*!< PPB NVIC_IPR25: PRI_1 Mask */
\r
14127 #define PPB_NVIC_IPR25_PRI_2_Pos 16 /*!< PPB NVIC_IPR25: PRI_2 Position */
\r
14128 #define PPB_NVIC_IPR25_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR25_PRI_2_Pos) /*!< PPB NVIC_IPR25: PRI_2 Mask */
\r
14129 #define PPB_NVIC_IPR25_PRI_3_Pos 24 /*!< PPB NVIC_IPR25: PRI_3 Position */
\r
14130 #define PPB_NVIC_IPR25_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR25_PRI_3_Pos) /*!< PPB NVIC_IPR25: PRI_3 Mask */
\r
14132 // ------------------------------------- PPB_NVIC_IPR26 -----------------------------------------
\r
14133 #define PPB_NVIC_IPR26_PRI_0_Pos 0 /*!< PPB NVIC_IPR26: PRI_0 Position */
\r
14134 #define PPB_NVIC_IPR26_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR26_PRI_0_Pos) /*!< PPB NVIC_IPR26: PRI_0 Mask */
\r
14135 #define PPB_NVIC_IPR26_PRI_1_Pos 8 /*!< PPB NVIC_IPR26: PRI_1 Position */
\r
14136 #define PPB_NVIC_IPR26_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR26_PRI_1_Pos) /*!< PPB NVIC_IPR26: PRI_1 Mask */
\r
14137 #define PPB_NVIC_IPR26_PRI_2_Pos 16 /*!< PPB NVIC_IPR26: PRI_2 Position */
\r
14138 #define PPB_NVIC_IPR26_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR26_PRI_2_Pos) /*!< PPB NVIC_IPR26: PRI_2 Mask */
\r
14139 #define PPB_NVIC_IPR26_PRI_3_Pos 24 /*!< PPB NVIC_IPR26: PRI_3 Position */
\r
14140 #define PPB_NVIC_IPR26_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR26_PRI_3_Pos) /*!< PPB NVIC_IPR26: PRI_3 Mask */
\r
14142 // ------------------------------------- PPB_NVIC_IPR27 -----------------------------------------
\r
14143 #define PPB_NVIC_IPR27_PRI_0_Pos 0 /*!< PPB NVIC_IPR27: PRI_0 Position */
\r
14144 #define PPB_NVIC_IPR27_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR27_PRI_0_Pos) /*!< PPB NVIC_IPR27: PRI_0 Mask */
\r
14145 #define PPB_NVIC_IPR27_PRI_1_Pos 8 /*!< PPB NVIC_IPR27: PRI_1 Position */
\r
14146 #define PPB_NVIC_IPR27_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR27_PRI_1_Pos) /*!< PPB NVIC_IPR27: PRI_1 Mask */
\r
14147 #define PPB_NVIC_IPR27_PRI_2_Pos 16 /*!< PPB NVIC_IPR27: PRI_2 Position */
\r
14148 #define PPB_NVIC_IPR27_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR27_PRI_2_Pos) /*!< PPB NVIC_IPR27: PRI_2 Mask */
\r
14149 #define PPB_NVIC_IPR27_PRI_3_Pos 24 /*!< PPB NVIC_IPR27: PRI_3 Position */
\r
14150 #define PPB_NVIC_IPR27_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR27_PRI_3_Pos) /*!< PPB NVIC_IPR27: PRI_3 Mask */
\r
14152 // ---------------------------------------- PPB_CPUID -------------------------------------------
\r
14153 #define PPB_CPUID_Revision_Pos 0 /*!< PPB CPUID: Revision Position */
\r
14154 #define PPB_CPUID_Revision_Msk (0x0fUL << PPB_CPUID_Revision_Pos) /*!< PPB CPUID: Revision Mask */
\r
14155 #define PPB_CPUID_PartNo_Pos 4 /*!< PPB CPUID: PartNo Position */
\r
14156 #define PPB_CPUID_PartNo_Msk (0x00000fffUL << PPB_CPUID_PartNo_Pos) /*!< PPB CPUID: PartNo Mask */
\r
14157 #define PPB_CPUID_Constant_Pos 16 /*!< PPB CPUID: Constant Position */
\r
14158 #define PPB_CPUID_Constant_Msk (0x0fUL << PPB_CPUID_Constant_Pos) /*!< PPB CPUID: Constant Mask */
\r
14159 #define PPB_CPUID_Variant_Pos 20 /*!< PPB CPUID: Variant Position */
\r
14160 #define PPB_CPUID_Variant_Msk (0x0fUL << PPB_CPUID_Variant_Pos) /*!< PPB CPUID: Variant Mask */
\r
14161 #define PPB_CPUID_Implementer_Pos 24 /*!< PPB CPUID: Implementer Position */
\r
14162 #define PPB_CPUID_Implementer_Msk (0x000000ffUL << PPB_CPUID_Implementer_Pos) /*!< PPB CPUID: Implementer Mask */
\r
14164 // ---------------------------------------- PPB_ICSR --------------------------------------------
\r
14165 #define PPB_ICSR_VECTACTIVE_Pos 0 /*!< PPB ICSR: VECTACTIVE Position */
\r
14166 #define PPB_ICSR_VECTACTIVE_Msk (0x000001ffUL << PPB_ICSR_VECTACTIVE_Pos) /*!< PPB ICSR: VECTACTIVE Mask */
\r
14167 #define PPB_ICSR_RETTOBASE_Pos 11 /*!< PPB ICSR: RETTOBASE Position */
\r
14168 #define PPB_ICSR_RETTOBASE_Msk (0x01UL << PPB_ICSR_RETTOBASE_Pos) /*!< PPB ICSR: RETTOBASE Mask */
\r
14169 #define PPB_ICSR_VECTPENDING_Pos 12 /*!< PPB ICSR: VECTPENDING Position */
\r
14170 #define PPB_ICSR_VECTPENDING_Msk (0x3fUL << PPB_ICSR_VECTPENDING_Pos) /*!< PPB ICSR: VECTPENDING Mask */
\r
14171 #define PPB_ICSR_ISRPENDING_Pos 22 /*!< PPB ICSR: ISRPENDING Position */
\r
14172 #define PPB_ICSR_ISRPENDING_Msk (0x01UL << PPB_ICSR_ISRPENDING_Pos) /*!< PPB ICSR: ISRPENDING Mask */
\r
14173 #define PPB_ICSR_Res_Pos 23 /*!< PPB ICSR: Res Position */
\r
14174 #define PPB_ICSR_Res_Msk (0x01UL << PPB_ICSR_Res_Pos) /*!< PPB ICSR: Res Mask */
\r
14175 #define PPB_ICSR_PENDSTCLR_Pos 25 /*!< PPB ICSR: PENDSTCLR Position */
\r
14176 #define PPB_ICSR_PENDSTCLR_Msk (0x01UL << PPB_ICSR_PENDSTCLR_Pos) /*!< PPB ICSR: PENDSTCLR Mask */
\r
14177 #define PPB_ICSR_PENDSTSET_Pos 26 /*!< PPB ICSR: PENDSTSET Position */
\r
14178 #define PPB_ICSR_PENDSTSET_Msk (0x01UL << PPB_ICSR_PENDSTSET_Pos) /*!< PPB ICSR: PENDSTSET Mask */
\r
14179 #define PPB_ICSR_PENDSVCLR_Pos 27 /*!< PPB ICSR: PENDSVCLR Position */
\r
14180 #define PPB_ICSR_PENDSVCLR_Msk (0x01UL << PPB_ICSR_PENDSVCLR_Pos) /*!< PPB ICSR: PENDSVCLR Mask */
\r
14181 #define PPB_ICSR_PENDSVSET_Pos 28 /*!< PPB ICSR: PENDSVSET Position */
\r
14182 #define PPB_ICSR_PENDSVSET_Msk (0x01UL << PPB_ICSR_PENDSVSET_Pos) /*!< PPB ICSR: PENDSVSET Mask */
\r
14183 #define PPB_ICSR_NMIPENDSET_Pos 31 /*!< PPB ICSR: NMIPENDSET Position */
\r
14184 #define PPB_ICSR_NMIPENDSET_Msk (0x01UL << PPB_ICSR_NMIPENDSET_Pos) /*!< PPB ICSR: NMIPENDSET Mask */
\r
14186 // ---------------------------------------- PPB_VTOR --------------------------------------------
\r
14187 #define PPB_VTOR_TBLOFF_Pos 8 /*!< PPB VTOR: TBLOFF Position */
\r
14188 #define PPB_VTOR_TBLOFF_Msk (0x00ffffffUL << PPB_VTOR_TBLOFF_Pos) /*!< PPB VTOR: TBLOFF Mask */
\r
14190 // ---------------------------------------- PPB_AIRCR -------------------------------------------
\r
14191 #define PPB_AIRCR_VECTRESET_Pos 0 /*!< PPB AIRCR: VECTRESET Position */
\r
14192 #define PPB_AIRCR_VECTRESET_Msk (0x01UL << PPB_AIRCR_VECTRESET_Pos) /*!< PPB AIRCR: VECTRESET Mask */
\r
14193 #define PPB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< PPB AIRCR: VECTCLRACTIVE Position */
\r
14194 #define PPB_AIRCR_VECTCLRACTIVE_Msk (0x01UL << PPB_AIRCR_VECTCLRACTIVE_Pos) /*!< PPB AIRCR: VECTCLRACTIVE Mask */
\r
14195 #define PPB_AIRCR_SYSRESETREQ_Pos 2 /*!< PPB AIRCR: SYSRESETREQ Position */
\r
14196 #define PPB_AIRCR_SYSRESETREQ_Msk (0x01UL << PPB_AIRCR_SYSRESETREQ_Pos) /*!< PPB AIRCR: SYSRESETREQ Mask */
\r
14197 #define PPB_AIRCR_PRIGROUP_Pos 8 /*!< PPB AIRCR: PRIGROUP Position */
\r
14198 #define PPB_AIRCR_PRIGROUP_Msk (0x07UL << PPB_AIRCR_PRIGROUP_Pos) /*!< PPB AIRCR: PRIGROUP Mask */
\r
14199 #define PPB_AIRCR_ENDIANNESS_Pos 15 /*!< PPB AIRCR: ENDIANNESS Position */
\r
14200 #define PPB_AIRCR_ENDIANNESS_Msk (0x01UL << PPB_AIRCR_ENDIANNESS_Pos) /*!< PPB AIRCR: ENDIANNESS Mask */
\r
14201 #define PPB_AIRCR_VECTKEY_Pos 16 /*!< PPB AIRCR: VECTKEY Position */
\r
14202 #define PPB_AIRCR_VECTKEY_Msk (0x0000ffffUL << PPB_AIRCR_VECTKEY_Pos) /*!< PPB AIRCR: VECTKEY Mask */
\r
14204 // ----------------------------------------- PPB_SCR --------------------------------------------
\r
14205 #define PPB_SCR_SLEEPONEXIT_Pos 1 /*!< PPB SCR: SLEEPONEXIT Position */
\r
14206 #define PPB_SCR_SLEEPONEXIT_Msk (0x01UL << PPB_SCR_SLEEPONEXIT_Pos) /*!< PPB SCR: SLEEPONEXIT Mask */
\r
14207 #define PPB_SCR_SLEEPDEEP_Pos 2 /*!< PPB SCR: SLEEPDEEP Position */
\r
14208 #define PPB_SCR_SLEEPDEEP_Msk (0x01UL << PPB_SCR_SLEEPDEEP_Pos) /*!< PPB SCR: SLEEPDEEP Mask */
\r
14209 #define PPB_SCR_SEVONPEND_Pos 4 /*!< PPB SCR: SEVONPEND Position */
\r
14210 #define PPB_SCR_SEVONPEND_Msk (0x01UL << PPB_SCR_SEVONPEND_Pos) /*!< PPB SCR: SEVONPEND Mask */
\r
14212 // ----------------------------------------- PPB_CCR --------------------------------------------
\r
14213 #define PPB_CCR_NONBASETHRDENA_Pos 0 /*!< PPB CCR: NONBASETHRDENA Position */
\r
14214 #define PPB_CCR_NONBASETHRDENA_Msk (0x01UL << PPB_CCR_NONBASETHRDENA_Pos) /*!< PPB CCR: NONBASETHRDENA Mask */
\r
14215 #define PPB_CCR_USERSETMPEND_Pos 1 /*!< PPB CCR: USERSETMPEND Position */
\r
14216 #define PPB_CCR_USERSETMPEND_Msk (0x01UL << PPB_CCR_USERSETMPEND_Pos) /*!< PPB CCR: USERSETMPEND Mask */
\r
14217 #define PPB_CCR_UNALIGN_TRP_Pos 3 /*!< PPB CCR: UNALIGN_TRP Position */
\r
14218 #define PPB_CCR_UNALIGN_TRP_Msk (0x01UL << PPB_CCR_UNALIGN_TRP_Pos) /*!< PPB CCR: UNALIGN_TRP Mask */
\r
14219 #define PPB_CCR_DIV_0_TRP_Pos 4 /*!< PPB CCR: DIV_0_TRP Position */
\r
14220 #define PPB_CCR_DIV_0_TRP_Msk (0x01UL << PPB_CCR_DIV_0_TRP_Pos) /*!< PPB CCR: DIV_0_TRP Mask */
\r
14221 #define PPB_CCR_BFHFNMIGN_Pos 8 /*!< PPB CCR: BFHFNMIGN Position */
\r
14222 #define PPB_CCR_BFHFNMIGN_Msk (0x01UL << PPB_CCR_BFHFNMIGN_Pos) /*!< PPB CCR: BFHFNMIGN Mask */
\r
14223 #define PPB_CCR_STKALIGN_Pos 9 /*!< PPB CCR: STKALIGN Position */
\r
14224 #define PPB_CCR_STKALIGN_Msk (0x01UL << PPB_CCR_STKALIGN_Pos) /*!< PPB CCR: STKALIGN Mask */
\r
14226 // ---------------------------------------- PPB_SHPR1 -------------------------------------------
\r
14227 #define PPB_SHPR1_PRI_4_Pos 0 /*!< PPB SHPR1: PRI_4 Position */
\r
14228 #define PPB_SHPR1_PRI_4_Msk (0x000000ffUL << PPB_SHPR1_PRI_4_Pos) /*!< PPB SHPR1: PRI_4 Mask */
\r
14229 #define PPB_SHPR1_PRI_5_Pos 8 /*!< PPB SHPR1: PRI_5 Position */
\r
14230 #define PPB_SHPR1_PRI_5_Msk (0x000000ffUL << PPB_SHPR1_PRI_5_Pos) /*!< PPB SHPR1: PRI_5 Mask */
\r
14231 #define PPB_SHPR1_PRI_6_Pos 16 /*!< PPB SHPR1: PRI_6 Position */
\r
14232 #define PPB_SHPR1_PRI_6_Msk (0x000000ffUL << PPB_SHPR1_PRI_6_Pos) /*!< PPB SHPR1: PRI_6 Mask */
\r
14234 // ---------------------------------------- PPB_SHPR2 -------------------------------------------
\r
14235 #define PPB_SHPR2_PRI_11_Pos 24 /*!< PPB SHPR2: PRI_11 Position */
\r
14236 #define PPB_SHPR2_PRI_11_Msk (0x000000ffUL << PPB_SHPR2_PRI_11_Pos) /*!< PPB SHPR2: PRI_11 Mask */
\r
14238 // ---------------------------------------- PPB_SHPR3 -------------------------------------------
\r
14239 #define PPB_SHPR3_PRI_14_Pos 16 /*!< PPB SHPR3: PRI_14 Position */
\r
14240 #define PPB_SHPR3_PRI_14_Msk (0x000000ffUL << PPB_SHPR3_PRI_14_Pos) /*!< PPB SHPR3: PRI_14 Mask */
\r
14241 #define PPB_SHPR3_PRI_15_Pos 24 /*!< PPB SHPR3: PRI_15 Position */
\r
14242 #define PPB_SHPR3_PRI_15_Msk (0x000000ffUL << PPB_SHPR3_PRI_15_Pos) /*!< PPB SHPR3: PRI_15 Mask */
\r
14244 // ---------------------------------------- PPB_SHCSR -------------------------------------------
\r
14245 #define PPB_SHCSR_MEMFAULTACT_Pos 0 /*!< PPB SHCSR: MEMFAULTACT Position */
\r
14246 #define PPB_SHCSR_MEMFAULTACT_Msk (0x01UL << PPB_SHCSR_MEMFAULTACT_Pos) /*!< PPB SHCSR: MEMFAULTACT Mask */
\r
14247 #define PPB_SHCSR_BUSFAULTACT_Pos 1 /*!< PPB SHCSR: BUSFAULTACT Position */
\r
14248 #define PPB_SHCSR_BUSFAULTACT_Msk (0x01UL << PPB_SHCSR_BUSFAULTACT_Pos) /*!< PPB SHCSR: BUSFAULTACT Mask */
\r
14249 #define PPB_SHCSR_USGFAULTACT_Pos 3 /*!< PPB SHCSR: USGFAULTACT Position */
\r
14250 #define PPB_SHCSR_USGFAULTACT_Msk (0x01UL << PPB_SHCSR_USGFAULTACT_Pos) /*!< PPB SHCSR: USGFAULTACT Mask */
\r
14251 #define PPB_SHCSR_SVCALLACT_Pos 7 /*!< PPB SHCSR: SVCALLACT Position */
\r
14252 #define PPB_SHCSR_SVCALLACT_Msk (0x01UL << PPB_SHCSR_SVCALLACT_Pos) /*!< PPB SHCSR: SVCALLACT Mask */
\r
14253 #define PPB_SHCSR_MONITORACT_Pos 8 /*!< PPB SHCSR: MONITORACT Position */
\r
14254 #define PPB_SHCSR_MONITORACT_Msk (0x01UL << PPB_SHCSR_MONITORACT_Pos) /*!< PPB SHCSR: MONITORACT Mask */
\r
14255 #define PPB_SHCSR_PENDSVACT_Pos 10 /*!< PPB SHCSR: PENDSVACT Position */
\r
14256 #define PPB_SHCSR_PENDSVACT_Msk (0x01UL << PPB_SHCSR_PENDSVACT_Pos) /*!< PPB SHCSR: PENDSVACT Mask */
\r
14257 #define PPB_SHCSR_SYSTICKACT_Pos 11 /*!< PPB SHCSR: SYSTICKACT Position */
\r
14258 #define PPB_SHCSR_SYSTICKACT_Msk (0x01UL << PPB_SHCSR_SYSTICKACT_Pos) /*!< PPB SHCSR: SYSTICKACT Mask */
\r
14259 #define PPB_SHCSR_USGFAULTPENDED_Pos 12 /*!< PPB SHCSR: USGFAULTPENDED Position */
\r
14260 #define PPB_SHCSR_USGFAULTPENDED_Msk (0x01UL << PPB_SHCSR_USGFAULTPENDED_Pos) /*!< PPB SHCSR: USGFAULTPENDED Mask */
\r
14261 #define PPB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< PPB SHCSR: MEMFAULTPENDED Position */
\r
14262 #define PPB_SHCSR_MEMFAULTPENDED_Msk (0x01UL << PPB_SHCSR_MEMFAULTPENDED_Pos) /*!< PPB SHCSR: MEMFAULTPENDED Mask */
\r
14263 #define PPB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< PPB SHCSR: BUSFAULTPENDED Position */
\r
14264 #define PPB_SHCSR_BUSFAULTPENDED_Msk (0x01UL << PPB_SHCSR_BUSFAULTPENDED_Pos) /*!< PPB SHCSR: BUSFAULTPENDED Mask */
\r
14265 #define PPB_SHCSR_SVCALLPENDED_Pos 15 /*!< PPB SHCSR: SVCALLPENDED Position */
\r
14266 #define PPB_SHCSR_SVCALLPENDED_Msk (0x01UL << PPB_SHCSR_SVCALLPENDED_Pos) /*!< PPB SHCSR: SVCALLPENDED Mask */
\r
14267 #define PPB_SHCSR_MEMFAULTENA_Pos 16 /*!< PPB SHCSR: MEMFAULTENA Position */
\r
14268 #define PPB_SHCSR_MEMFAULTENA_Msk (0x01UL << PPB_SHCSR_MEMFAULTENA_Pos) /*!< PPB SHCSR: MEMFAULTENA Mask */
\r
14269 #define PPB_SHCSR_BUSFAULTENA_Pos 17 /*!< PPB SHCSR: BUSFAULTENA Position */
\r
14270 #define PPB_SHCSR_BUSFAULTENA_Msk (0x01UL << PPB_SHCSR_BUSFAULTENA_Pos) /*!< PPB SHCSR: BUSFAULTENA Mask */
\r
14271 #define PPB_SHCSR_USGFAULTENA_Pos 18 /*!< PPB SHCSR: USGFAULTENA Position */
\r
14272 #define PPB_SHCSR_USGFAULTENA_Msk (0x01UL << PPB_SHCSR_USGFAULTENA_Pos) /*!< PPB SHCSR: USGFAULTENA Mask */
\r
14274 // ---------------------------------------- PPB_CFSR --------------------------------------------
\r
14275 #define PPB_CFSR_IACCVIOL_Pos 0 /*!< PPB CFSR: IACCVIOL Position */
\r
14276 #define PPB_CFSR_IACCVIOL_Msk (0x01UL << PPB_CFSR_IACCVIOL_Pos) /*!< PPB CFSR: IACCVIOL Mask */
\r
14277 #define PPB_CFSR_DACCVIOL_Pos 1 /*!< PPB CFSR: DACCVIOL Position */
\r
14278 #define PPB_CFSR_DACCVIOL_Msk (0x01UL << PPB_CFSR_DACCVIOL_Pos) /*!< PPB CFSR: DACCVIOL Mask */
\r
14279 #define PPB_CFSR_MUNSTKERR_Pos 3 /*!< PPB CFSR: MUNSTKERR Position */
\r
14280 #define PPB_CFSR_MUNSTKERR_Msk (0x01UL << PPB_CFSR_MUNSTKERR_Pos) /*!< PPB CFSR: MUNSTKERR Mask */
\r
14281 #define PPB_CFSR_MSTKERR_Pos 4 /*!< PPB CFSR: MSTKERR Position */
\r
14282 #define PPB_CFSR_MSTKERR_Msk (0x01UL << PPB_CFSR_MSTKERR_Pos) /*!< PPB CFSR: MSTKERR Mask */
\r
14283 #define PPB_CFSR_MLSPERR_Pos 5 /*!< PPB CFSR: MLSPERR Position */
\r
14284 #define PPB_CFSR_MLSPERR_Msk (0x01UL << PPB_CFSR_MLSPERR_Pos) /*!< PPB CFSR: MLSPERR Mask */
\r
14285 #define PPB_CFSR_MMARVALID_Pos 7 /*!< PPB CFSR: MMARVALID Position */
\r
14286 #define PPB_CFSR_MMARVALID_Msk (0x01UL << PPB_CFSR_MMARVALID_Pos) /*!< PPB CFSR: MMARVALID Mask */
\r
14287 #define PPB_CFSR_IBUSERR_Pos 8 /*!< PPB CFSR: IBUSERR Position */
\r
14288 #define PPB_CFSR_IBUSERR_Msk (0x01UL << PPB_CFSR_IBUSERR_Pos) /*!< PPB CFSR: IBUSERR Mask */
\r
14289 #define PPB_CFSR_PRECISERR_Pos 9 /*!< PPB CFSR: PRECISERR Position */
\r
14290 #define PPB_CFSR_PRECISERR_Msk (0x01UL << PPB_CFSR_PRECISERR_Pos) /*!< PPB CFSR: PRECISERR Mask */
\r
14291 #define PPB_CFSR_IMPRECISERR_Pos 10 /*!< PPB CFSR: IMPRECISERR Position */
\r
14292 #define PPB_CFSR_IMPRECISERR_Msk (0x01UL << PPB_CFSR_IMPRECISERR_Pos) /*!< PPB CFSR: IMPRECISERR Mask */
\r
14293 #define PPB_CFSR_UNSTKERR_Pos 11 /*!< PPB CFSR: UNSTKERR Position */
\r
14294 #define PPB_CFSR_UNSTKERR_Msk (0x01UL << PPB_CFSR_UNSTKERR_Pos) /*!< PPB CFSR: UNSTKERR Mask */
\r
14295 #define PPB_CFSR_STKERR_Pos 12 /*!< PPB CFSR: STKERR Position */
\r
14296 #define PPB_CFSR_STKERR_Msk (0x01UL << PPB_CFSR_STKERR_Pos) /*!< PPB CFSR: STKERR Mask */
\r
14297 #define PPB_CFSR_LSPERR_Pos 13 /*!< PPB CFSR: LSPERR Position */
\r
14298 #define PPB_CFSR_LSPERR_Msk (0x01UL << PPB_CFSR_LSPERR_Pos) /*!< PPB CFSR: LSPERR Mask */
\r
14299 #define PPB_CFSR_BFARVALID_Pos 15 /*!< PPB CFSR: BFARVALID Position */
\r
14300 #define PPB_CFSR_BFARVALID_Msk (0x01UL << PPB_CFSR_BFARVALID_Pos) /*!< PPB CFSR: BFARVALID Mask */
\r
14301 #define PPB_CFSR_UNDEFINSTR_Pos 16 /*!< PPB CFSR: UNDEFINSTR Position */
\r
14302 #define PPB_CFSR_UNDEFINSTR_Msk (0x01UL << PPB_CFSR_UNDEFINSTR_Pos) /*!< PPB CFSR: UNDEFINSTR Mask */
\r
14303 #define PPB_CFSR_INVSTATE_Pos 17 /*!< PPB CFSR: INVSTATE Position */
\r
14304 #define PPB_CFSR_INVSTATE_Msk (0x01UL << PPB_CFSR_INVSTATE_Pos) /*!< PPB CFSR: INVSTATE Mask */
\r
14305 #define PPB_CFSR_INVPC_Pos 18 /*!< PPB CFSR: INVPC Position */
\r
14306 #define PPB_CFSR_INVPC_Msk (0x01UL << PPB_CFSR_INVPC_Pos) /*!< PPB CFSR: INVPC Mask */
\r
14307 #define PPB_CFSR_NOCP_Pos 19 /*!< PPB CFSR: NOCP Position */
\r
14308 #define PPB_CFSR_NOCP_Msk (0x01UL << PPB_CFSR_NOCP_Pos) /*!< PPB CFSR: NOCP Mask */
\r
14309 #define PPB_CFSR_UNALIGNED_Pos 24 /*!< PPB CFSR: UNALIGNED Position */
\r
14310 #define PPB_CFSR_UNALIGNED_Msk (0x01UL << PPB_CFSR_UNALIGNED_Pos) /*!< PPB CFSR: UNALIGNED Mask */
\r
14311 #define PPB_CFSR_DIVBYZERO_Pos 25 /*!< PPB CFSR: DIVBYZERO Position */
\r
14312 #define PPB_CFSR_DIVBYZERO_Msk (0x01UL << PPB_CFSR_DIVBYZERO_Pos) /*!< PPB CFSR: DIVBYZERO Mask */
\r
14314 // ---------------------------------------- PPB_HFSR --------------------------------------------
\r
14315 #define PPB_HFSR_VECTTBL_Pos 1 /*!< PPB HFSR: VECTTBL Position */
\r
14316 #define PPB_HFSR_VECTTBL_Msk (0x01UL << PPB_HFSR_VECTTBL_Pos) /*!< PPB HFSR: VECTTBL Mask */
\r
14317 #define PPB_HFSR_FORCED_Pos 30 /*!< PPB HFSR: FORCED Position */
\r
14318 #define PPB_HFSR_FORCED_Msk (0x01UL << PPB_HFSR_FORCED_Pos) /*!< PPB HFSR: FORCED Mask */
\r
14319 #define PPB_HFSR_DEBUGEVT_Pos 31 /*!< PPB HFSR: DEBUGEVT Position */
\r
14320 #define PPB_HFSR_DEBUGEVT_Msk (0x01UL << PPB_HFSR_DEBUGEVT_Pos) /*!< PPB HFSR: DEBUGEVT Mask */
\r
14322 // ---------------------------------------- PPB_MMFAR -------------------------------------------
\r
14323 #define PPB_MMFAR_ADDRESS_Pos 0 /*!< PPB MMFAR: ADDRESS Position */
\r
14324 #define PPB_MMFAR_ADDRESS_Msk (0xffffffffUL << PPB_MMFAR_ADDRESS_Pos) /*!< PPB MMFAR: ADDRESS Mask */
\r
14326 // ---------------------------------------- PPB_BFAR --------------------------------------------
\r
14327 #define PPB_BFAR_ADDRESS_Pos 0 /*!< PPB BFAR: ADDRESS Position */
\r
14328 #define PPB_BFAR_ADDRESS_Msk (0xffffffffUL << PPB_BFAR_ADDRESS_Pos) /*!< PPB BFAR: ADDRESS Mask */
\r
14330 // ---------------------------------------- PPB_AFSR --------------------------------------------
\r
14331 #define PPB_AFSR_VALUE_Pos 0 /*!< PPB AFSR: VALUE Position */
\r
14332 #define PPB_AFSR_VALUE_Msk (0xffffffffUL << PPB_AFSR_VALUE_Pos) /*!< PPB AFSR: VALUE Mask */
\r
14334 // ---------------------------------------- PPB_CPACR -------------------------------------------
\r
14335 #define PPB_CPACR_CP10_Pos 20 /*!< PPB CPACR: CP10 Position */
\r
14336 #define PPB_CPACR_CP10_Msk (0x03UL << PPB_CPACR_CP10_Pos) /*!< PPB CPACR: CP10 Mask */
\r
14337 #define PPB_CPACR_CP11_Pos 22 /*!< PPB CPACR: CP11 Position */
\r
14338 #define PPB_CPACR_CP11_Msk (0x03UL << PPB_CPACR_CP11_Pos) /*!< PPB CPACR: CP11 Mask */
\r
14340 // -------------------------------------- PPB_MPU_TYPE ------------------------------------------
\r
14341 #define PPB_MPU_TYPE_SEPARATE_Pos 0 /*!< PPB MPU_TYPE: SEPARATE Position */
\r
14342 #define PPB_MPU_TYPE_SEPARATE_Msk (0x01UL << PPB_MPU_TYPE_SEPARATE_Pos) /*!< PPB MPU_TYPE: SEPARATE Mask */
\r
14343 #define PPB_MPU_TYPE_DREGION_Pos 8 /*!< PPB MPU_TYPE: DREGION Position */
\r
14344 #define PPB_MPU_TYPE_DREGION_Msk (0x000000ffUL << PPB_MPU_TYPE_DREGION_Pos) /*!< PPB MPU_TYPE: DREGION Mask */
\r
14345 #define PPB_MPU_TYPE_IREGION_Pos 16 /*!< PPB MPU_TYPE: IREGION Position */
\r
14346 #define PPB_MPU_TYPE_IREGION_Msk (0x000000ffUL << PPB_MPU_TYPE_IREGION_Pos) /*!< PPB MPU_TYPE: IREGION Mask */
\r
14348 // -------------------------------------- PPB_MPU_CTRL ------------------------------------------
\r
14349 #define PPB_MPU_CTRL_ENABLE_Pos 0 /*!< PPB MPU_CTRL: ENABLE Position */
\r
14350 #define PPB_MPU_CTRL_ENABLE_Msk (0x01UL << PPB_MPU_CTRL_ENABLE_Pos) /*!< PPB MPU_CTRL: ENABLE Mask */
\r
14351 #define PPB_MPU_CTRL_HFNMIENA_Pos 1 /*!< PPB MPU_CTRL: HFNMIENA Position */
\r
14352 #define PPB_MPU_CTRL_HFNMIENA_Msk (0x01UL << PPB_MPU_CTRL_HFNMIENA_Pos) /*!< PPB MPU_CTRL: HFNMIENA Mask */
\r
14353 #define PPB_MPU_CTRL_PRIVDEFENA_Pos 2 /*!< PPB MPU_CTRL: PRIVDEFENA Position */
\r
14354 #define PPB_MPU_CTRL_PRIVDEFENA_Msk (0x01UL << PPB_MPU_CTRL_PRIVDEFENA_Pos) /*!< PPB MPU_CTRL: PRIVDEFENA Mask */
\r
14356 // --------------------------------------- PPB_MPU_RNR ------------------------------------------
\r
14357 #define PPB_MPU_RNR_REGION_Pos 0 /*!< PPB MPU_RNR: REGION Position */
\r
14358 #define PPB_MPU_RNR_REGION_Msk (0x000000ffUL << PPB_MPU_RNR_REGION_Pos) /*!< PPB MPU_RNR: REGION Mask */
\r
14360 // -------------------------------------- PPB_MPU_RBAR ------------------------------------------
\r
14361 #define PPB_MPU_RBAR_REGION_Pos 0 /*!< PPB MPU_RBAR: REGION Position */
\r
14362 #define PPB_MPU_RBAR_REGION_Msk (0x0fUL << PPB_MPU_RBAR_REGION_Pos) /*!< PPB MPU_RBAR: REGION Mask */
\r
14363 #define PPB_MPU_RBAR_VALID_Pos 4 /*!< PPB MPU_RBAR: VALID Position */
\r
14364 #define PPB_MPU_RBAR_VALID_Msk (0x01UL << PPB_MPU_RBAR_VALID_Pos) /*!< PPB MPU_RBAR: VALID Mask */
\r
14365 #define PPB_MPU_RBAR_ADDR_Pos 9 /*!< PPB MPU_RBAR: ADDR Position */
\r
14366 #define PPB_MPU_RBAR_ADDR_Msk (0x007fffffUL << PPB_MPU_RBAR_ADDR_Pos) /*!< PPB MPU_RBAR: ADDR Mask */
\r
14368 // -------------------------------------- PPB_MPU_RASR ------------------------------------------
\r
14369 #define PPB_MPU_RASR_ENABLE_Pos 0 /*!< PPB MPU_RASR: ENABLE Position */
\r
14370 #define PPB_MPU_RASR_ENABLE_Msk (0x01UL << PPB_MPU_RASR_ENABLE_Pos) /*!< PPB MPU_RASR: ENABLE Mask */
\r
14371 #define PPB_MPU_RASR_SIZE_Pos 1 /*!< PPB MPU_RASR: SIZE Position */
\r
14372 #define PPB_MPU_RASR_SIZE_Msk (0x1fUL << PPB_MPU_RASR_SIZE_Pos) /*!< PPB MPU_RASR: SIZE Mask */
\r
14373 #define PPB_MPU_RASR_SRD_Pos 8 /*!< PPB MPU_RASR: SRD Position */
\r
14374 #define PPB_MPU_RASR_SRD_Msk (0x000000ffUL << PPB_MPU_RASR_SRD_Pos) /*!< PPB MPU_RASR: SRD Mask */
\r
14375 #define PPB_MPU_RASR_B_Pos 16 /*!< PPB MPU_RASR: B Position */
\r
14376 #define PPB_MPU_RASR_B_Msk (0x01UL << PPB_MPU_RASR_B_Pos) /*!< PPB MPU_RASR: B Mask */
\r
14377 #define PPB_MPU_RASR_C_Pos 17 /*!< PPB MPU_RASR: C Position */
\r
14378 #define PPB_MPU_RASR_C_Msk (0x01UL << PPB_MPU_RASR_C_Pos) /*!< PPB MPU_RASR: C Mask */
\r
14379 #define PPB_MPU_RASR_S_Pos 18 /*!< PPB MPU_RASR: S Position */
\r
14380 #define PPB_MPU_RASR_S_Msk (0x01UL << PPB_MPU_RASR_S_Pos) /*!< PPB MPU_RASR: S Mask */
\r
14381 #define PPB_MPU_RASR_TEX_Pos 19 /*!< PPB MPU_RASR: TEX Position */
\r
14382 #define PPB_MPU_RASR_TEX_Msk (0x07UL << PPB_MPU_RASR_TEX_Pos) /*!< PPB MPU_RASR: TEX Mask */
\r
14383 #define PPB_MPU_RASR_AP_Pos 24 /*!< PPB MPU_RASR: AP Position */
\r
14384 #define PPB_MPU_RASR_AP_Msk (0x07UL << PPB_MPU_RASR_AP_Pos) /*!< PPB MPU_RASR: AP Mask */
\r
14385 #define PPB_MPU_RASR_XN_Pos 28 /*!< PPB MPU_RASR: XN Position */
\r
14386 #define PPB_MPU_RASR_XN_Msk (0x01UL << PPB_MPU_RASR_XN_Pos) /*!< PPB MPU_RASR: XN Mask */
\r
14388 // ------------------------------------- PPB_MPU_RBAR_A1 ----------------------------------------
\r
14389 #define PPB_MPU_RBAR_A1_REGION_Pos 0 /*!< PPB MPU_RBAR_A1: REGION Position */
\r
14390 #define PPB_MPU_RBAR_A1_REGION_Msk (0x0fUL << PPB_MPU_RBAR_A1_REGION_Pos) /*!< PPB MPU_RBAR_A1: REGION Mask */
\r
14391 #define PPB_MPU_RBAR_A1_VALID_Pos 4 /*!< PPB MPU_RBAR_A1: VALID Position */
\r
14392 #define PPB_MPU_RBAR_A1_VALID_Msk (0x01UL << PPB_MPU_RBAR_A1_VALID_Pos) /*!< PPB MPU_RBAR_A1: VALID Mask */
\r
14393 #define PPB_MPU_RBAR_A1_ADDR_Pos 9 /*!< PPB MPU_RBAR_A1: ADDR Position */
\r
14394 #define PPB_MPU_RBAR_A1_ADDR_Msk (0x007fffffUL << PPB_MPU_RBAR_A1_ADDR_Pos) /*!< PPB MPU_RBAR_A1: ADDR Mask */
\r
14396 // ------------------------------------- PPB_MPU_RASR_A1 ----------------------------------------
\r
14397 #define PPB_MPU_RASR_A1_ENABLE_Pos 0 /*!< PPB MPU_RASR_A1: ENABLE Position */
\r
14398 #define PPB_MPU_RASR_A1_ENABLE_Msk (0x01UL << PPB_MPU_RASR_A1_ENABLE_Pos) /*!< PPB MPU_RASR_A1: ENABLE Mask */
\r
14399 #define PPB_MPU_RASR_A1_SIZE_Pos 1 /*!< PPB MPU_RASR_A1: SIZE Position */
\r
14400 #define PPB_MPU_RASR_A1_SIZE_Msk (0x1fUL << PPB_MPU_RASR_A1_SIZE_Pos) /*!< PPB MPU_RASR_A1: SIZE Mask */
\r
14401 #define PPB_MPU_RASR_A1_SRD_Pos 8 /*!< PPB MPU_RASR_A1: SRD Position */
\r
14402 #define PPB_MPU_RASR_A1_SRD_Msk (0x000000ffUL << PPB_MPU_RASR_A1_SRD_Pos) /*!< PPB MPU_RASR_A1: SRD Mask */
\r
14403 #define PPB_MPU_RASR_A1_B_Pos 16 /*!< PPB MPU_RASR_A1: B Position */
\r
14404 #define PPB_MPU_RASR_A1_B_Msk (0x01UL << PPB_MPU_RASR_A1_B_Pos) /*!< PPB MPU_RASR_A1: B Mask */
\r
14405 #define PPB_MPU_RASR_A1_C_Pos 17 /*!< PPB MPU_RASR_A1: C Position */
\r
14406 #define PPB_MPU_RASR_A1_C_Msk (0x01UL << PPB_MPU_RASR_A1_C_Pos) /*!< PPB MPU_RASR_A1: C Mask */
\r
14407 #define PPB_MPU_RASR_A1_S_Pos 18 /*!< PPB MPU_RASR_A1: S Position */
\r
14408 #define PPB_MPU_RASR_A1_S_Msk (0x01UL << PPB_MPU_RASR_A1_S_Pos) /*!< PPB MPU_RASR_A1: S Mask */
\r
14409 #define PPB_MPU_RASR_A1_TEX_Pos 19 /*!< PPB MPU_RASR_A1: TEX Position */
\r
14410 #define PPB_MPU_RASR_A1_TEX_Msk (0x07UL << PPB_MPU_RASR_A1_TEX_Pos) /*!< PPB MPU_RASR_A1: TEX Mask */
\r
14411 #define PPB_MPU_RASR_A1_AP_Pos 24 /*!< PPB MPU_RASR_A1: AP Position */
\r
14412 #define PPB_MPU_RASR_A1_AP_Msk (0x07UL << PPB_MPU_RASR_A1_AP_Pos) /*!< PPB MPU_RASR_A1: AP Mask */
\r
14413 #define PPB_MPU_RASR_A1_XN_Pos 28 /*!< PPB MPU_RASR_A1: XN Position */
\r
14414 #define PPB_MPU_RASR_A1_XN_Msk (0x01UL << PPB_MPU_RASR_A1_XN_Pos) /*!< PPB MPU_RASR_A1: XN Mask */
\r
14416 // ------------------------------------- PPB_MPU_RBAR_A2 ----------------------------------------
\r
14417 #define PPB_MPU_RBAR_A2_REGION_Pos 0 /*!< PPB MPU_RBAR_A2: REGION Position */
\r
14418 #define PPB_MPU_RBAR_A2_REGION_Msk (0x0fUL << PPB_MPU_RBAR_A2_REGION_Pos) /*!< PPB MPU_RBAR_A2: REGION Mask */
\r
14419 #define PPB_MPU_RBAR_A2_VALID_Pos 4 /*!< PPB MPU_RBAR_A2: VALID Position */
\r
14420 #define PPB_MPU_RBAR_A2_VALID_Msk (0x01UL << PPB_MPU_RBAR_A2_VALID_Pos) /*!< PPB MPU_RBAR_A2: VALID Mask */
\r
14421 #define PPB_MPU_RBAR_A2_ADDR_Pos 9 /*!< PPB MPU_RBAR_A2: ADDR Position */
\r
14422 #define PPB_MPU_RBAR_A2_ADDR_Msk (0x007fffffUL << PPB_MPU_RBAR_A2_ADDR_Pos) /*!< PPB MPU_RBAR_A2: ADDR Mask */
\r
14424 // ------------------------------------- PPB_MPU_RASR_A2 ----------------------------------------
\r
14425 #define PPB_MPU_RASR_A2_ENABLE_Pos 0 /*!< PPB MPU_RASR_A2: ENABLE Position */
\r
14426 #define PPB_MPU_RASR_A2_ENABLE_Msk (0x01UL << PPB_MPU_RASR_A2_ENABLE_Pos) /*!< PPB MPU_RASR_A2: ENABLE Mask */
\r
14427 #define PPB_MPU_RASR_A2_SIZE_Pos 1 /*!< PPB MPU_RASR_A2: SIZE Position */
\r
14428 #define PPB_MPU_RASR_A2_SIZE_Msk (0x1fUL << PPB_MPU_RASR_A2_SIZE_Pos) /*!< PPB MPU_RASR_A2: SIZE Mask */
\r
14429 #define PPB_MPU_RASR_A2_SRD_Pos 8 /*!< PPB MPU_RASR_A2: SRD Position */
\r
14430 #define PPB_MPU_RASR_A2_SRD_Msk (0x000000ffUL << PPB_MPU_RASR_A2_SRD_Pos) /*!< PPB MPU_RASR_A2: SRD Mask */
\r
14431 #define PPB_MPU_RASR_A2_B_Pos 16 /*!< PPB MPU_RASR_A2: B Position */
\r
14432 #define PPB_MPU_RASR_A2_B_Msk (0x01UL << PPB_MPU_RASR_A2_B_Pos) /*!< PPB MPU_RASR_A2: B Mask */
\r
14433 #define PPB_MPU_RASR_A2_C_Pos 17 /*!< PPB MPU_RASR_A2: C Position */
\r
14434 #define PPB_MPU_RASR_A2_C_Msk (0x01UL << PPB_MPU_RASR_A2_C_Pos) /*!< PPB MPU_RASR_A2: C Mask */
\r
14435 #define PPB_MPU_RASR_A2_S_Pos 18 /*!< PPB MPU_RASR_A2: S Position */
\r
14436 #define PPB_MPU_RASR_A2_S_Msk (0x01UL << PPB_MPU_RASR_A2_S_Pos) /*!< PPB MPU_RASR_A2: S Mask */
\r
14437 #define PPB_MPU_RASR_A2_TEX_Pos 19 /*!< PPB MPU_RASR_A2: TEX Position */
\r
14438 #define PPB_MPU_RASR_A2_TEX_Msk (0x07UL << PPB_MPU_RASR_A2_TEX_Pos) /*!< PPB MPU_RASR_A2: TEX Mask */
\r
14439 #define PPB_MPU_RASR_A2_AP_Pos 24 /*!< PPB MPU_RASR_A2: AP Position */
\r
14440 #define PPB_MPU_RASR_A2_AP_Msk (0x07UL << PPB_MPU_RASR_A2_AP_Pos) /*!< PPB MPU_RASR_A2: AP Mask */
\r
14441 #define PPB_MPU_RASR_A2_XN_Pos 28 /*!< PPB MPU_RASR_A2: XN Position */
\r
14442 #define PPB_MPU_RASR_A2_XN_Msk (0x01UL << PPB_MPU_RASR_A2_XN_Pos) /*!< PPB MPU_RASR_A2: XN Mask */
\r
14444 // ------------------------------------- PPB_MPU_RBAR_A3 ----------------------------------------
\r
14445 #define PPB_MPU_RBAR_A3_REGION_Pos 0 /*!< PPB MPU_RBAR_A3: REGION Position */
\r
14446 #define PPB_MPU_RBAR_A3_REGION_Msk (0x0fUL << PPB_MPU_RBAR_A3_REGION_Pos) /*!< PPB MPU_RBAR_A3: REGION Mask */
\r
14447 #define PPB_MPU_RBAR_A3_VALID_Pos 4 /*!< PPB MPU_RBAR_A3: VALID Position */
\r
14448 #define PPB_MPU_RBAR_A3_VALID_Msk (0x01UL << PPB_MPU_RBAR_A3_VALID_Pos) /*!< PPB MPU_RBAR_A3: VALID Mask */
\r
14449 #define PPB_MPU_RBAR_A3_ADDR_Pos 9 /*!< PPB MPU_RBAR_A3: ADDR Position */
\r
14450 #define PPB_MPU_RBAR_A3_ADDR_Msk (0x007fffffUL << PPB_MPU_RBAR_A3_ADDR_Pos) /*!< PPB MPU_RBAR_A3: ADDR Mask */
\r
14452 // ------------------------------------- PPB_MPU_RASR_A3 ----------------------------------------
\r
14453 #define PPB_MPU_RASR_A3_ENABLE_Pos 0 /*!< PPB MPU_RASR_A3: ENABLE Position */
\r
14454 #define PPB_MPU_RASR_A3_ENABLE_Msk (0x01UL << PPB_MPU_RASR_A3_ENABLE_Pos) /*!< PPB MPU_RASR_A3: ENABLE Mask */
\r
14455 #define PPB_MPU_RASR_A3_SIZE_Pos 1 /*!< PPB MPU_RASR_A3: SIZE Position */
\r
14456 #define PPB_MPU_RASR_A3_SIZE_Msk (0x1fUL << PPB_MPU_RASR_A3_SIZE_Pos) /*!< PPB MPU_RASR_A3: SIZE Mask */
\r
14457 #define PPB_MPU_RASR_A3_SRD_Pos 8 /*!< PPB MPU_RASR_A3: SRD Position */
\r
14458 #define PPB_MPU_RASR_A3_SRD_Msk (0x000000ffUL << PPB_MPU_RASR_A3_SRD_Pos) /*!< PPB MPU_RASR_A3: SRD Mask */
\r
14459 #define PPB_MPU_RASR_A3_B_Pos 16 /*!< PPB MPU_RASR_A3: B Position */
\r
14460 #define PPB_MPU_RASR_A3_B_Msk (0x01UL << PPB_MPU_RASR_A3_B_Pos) /*!< PPB MPU_RASR_A3: B Mask */
\r
14461 #define PPB_MPU_RASR_A3_C_Pos 17 /*!< PPB MPU_RASR_A3: C Position */
\r
14462 #define PPB_MPU_RASR_A3_C_Msk (0x01UL << PPB_MPU_RASR_A3_C_Pos) /*!< PPB MPU_RASR_A3: C Mask */
\r
14463 #define PPB_MPU_RASR_A3_S_Pos 18 /*!< PPB MPU_RASR_A3: S Position */
\r
14464 #define PPB_MPU_RASR_A3_S_Msk (0x01UL << PPB_MPU_RASR_A3_S_Pos) /*!< PPB MPU_RASR_A3: S Mask */
\r
14465 #define PPB_MPU_RASR_A3_TEX_Pos 19 /*!< PPB MPU_RASR_A3: TEX Position */
\r
14466 #define PPB_MPU_RASR_A3_TEX_Msk (0x07UL << PPB_MPU_RASR_A3_TEX_Pos) /*!< PPB MPU_RASR_A3: TEX Mask */
\r
14467 #define PPB_MPU_RASR_A3_AP_Pos 24 /*!< PPB MPU_RASR_A3: AP Position */
\r
14468 #define PPB_MPU_RASR_A3_AP_Msk (0x07UL << PPB_MPU_RASR_A3_AP_Pos) /*!< PPB MPU_RASR_A3: AP Mask */
\r
14469 #define PPB_MPU_RASR_A3_XN_Pos 28 /*!< PPB MPU_RASR_A3: XN Position */
\r
14470 #define PPB_MPU_RASR_A3_XN_Msk (0x01UL << PPB_MPU_RASR_A3_XN_Pos) /*!< PPB MPU_RASR_A3: XN Mask */
\r
14472 // ---------------------------------------- PPB_STIR --------------------------------------------
\r
14473 #define PPB_STIR_INTID_Pos 0 /*!< PPB STIR: INTID Position */
\r
14474 #define PPB_STIR_INTID_Msk (0x000001ffUL << PPB_STIR_INTID_Pos) /*!< PPB STIR: INTID Mask */
\r
14476 // ---------------------------------------- PPB_FPCCR -------------------------------------------
\r
14477 #define PPB_FPCCR_LSPACT_Pos 0 /*!< PPB FPCCR: LSPACT Position */
\r
14478 #define PPB_FPCCR_LSPACT_Msk (0x01UL << PPB_FPCCR_LSPACT_Pos) /*!< PPB FPCCR: LSPACT Mask */
\r
14479 #define PPB_FPCCR_USER_Pos 1 /*!< PPB FPCCR: USER Position */
\r
14480 #define PPB_FPCCR_USER_Msk (0x01UL << PPB_FPCCR_USER_Pos) /*!< PPB FPCCR: USER Mask */
\r
14481 #define PPB_FPCCR_THREAD_Pos 3 /*!< PPB FPCCR: THREAD Position */
\r
14482 #define PPB_FPCCR_THREAD_Msk (0x01UL << PPB_FPCCR_THREAD_Pos) /*!< PPB FPCCR: THREAD Mask */
\r
14483 #define PPB_FPCCR_HFRDY_Pos 4 /*!< PPB FPCCR: HFRDY Position */
\r
14484 #define PPB_FPCCR_HFRDY_Msk (0x01UL << PPB_FPCCR_HFRDY_Pos) /*!< PPB FPCCR: HFRDY Mask */
\r
14485 #define PPB_FPCCR_MMRDY_Pos 5 /*!< PPB FPCCR: MMRDY Position */
\r
14486 #define PPB_FPCCR_MMRDY_Msk (0x01UL << PPB_FPCCR_MMRDY_Pos) /*!< PPB FPCCR: MMRDY Mask */
\r
14487 #define PPB_FPCCR_BFRDY_Pos 6 /*!< PPB FPCCR: BFRDY Position */
\r
14488 #define PPB_FPCCR_BFRDY_Msk (0x01UL << PPB_FPCCR_BFRDY_Pos) /*!< PPB FPCCR: BFRDY Mask */
\r
14489 #define PPB_FPCCR_MONRDY_Pos 8 /*!< PPB FPCCR: MONRDY Position */
\r
14490 #define PPB_FPCCR_MONRDY_Msk (0x01UL << PPB_FPCCR_MONRDY_Pos) /*!< PPB FPCCR: MONRDY Mask */
\r
14491 #define PPB_FPCCR_LSPEN_Pos 30 /*!< PPB FPCCR: LSPEN Position */
\r
14492 #define PPB_FPCCR_LSPEN_Msk (0x01UL << PPB_FPCCR_LSPEN_Pos) /*!< PPB FPCCR: LSPEN Mask */
\r
14493 #define PPB_FPCCR_ASPEN_Pos 31 /*!< PPB FPCCR: ASPEN Position */
\r
14494 #define PPB_FPCCR_ASPEN_Msk (0x01UL << PPB_FPCCR_ASPEN_Pos) /*!< PPB FPCCR: ASPEN Mask */
\r
14496 // ---------------------------------------- PPB_FPCAR -------------------------------------------
\r
14497 #define PPB_FPCAR_ADDRESS_Pos 3 /*!< PPB FPCAR: ADDRESS Position */
\r
14498 #define PPB_FPCAR_ADDRESS_Msk (0x1fffffffUL << PPB_FPCAR_ADDRESS_Pos) /*!< PPB FPCAR: ADDRESS Mask */
\r
14500 // --------------------------------------- PPB_FPDSCR -------------------------------------------
\r
14501 #define PPB_FPDSCR_RMode_Pos 22 /*!< PPB FPDSCR: RMode Position */
\r
14502 #define PPB_FPDSCR_RMode_Msk (0x03UL << PPB_FPDSCR_RMode_Pos) /*!< PPB FPDSCR: RMode Mask */
\r
14503 #define PPB_FPDSCR_FZ_Pos 24 /*!< PPB FPDSCR: FZ Position */
\r
14504 #define PPB_FPDSCR_FZ_Msk (0x01UL << PPB_FPDSCR_FZ_Pos) /*!< PPB FPDSCR: FZ Mask */
\r
14505 #define PPB_FPDSCR_DN_Pos 25 /*!< PPB FPDSCR: DN Position */
\r
14506 #define PPB_FPDSCR_DN_Msk (0x01UL << PPB_FPDSCR_DN_Pos) /*!< PPB FPDSCR: DN Mask */
\r
14507 #define PPB_FPDSCR_AHP_Pos 26 /*!< PPB FPDSCR: AHP Position */
\r
14508 #define PPB_FPDSCR_AHP_Msk (0x01UL << PPB_FPDSCR_AHP_Pos) /*!< PPB FPDSCR: AHP Mask */
\r
14510 /*** PREF Bit Fileds *******************/
\r
14511 /***************************************************************************/
\r
14514 /* PREF_PCON = Prefetch Configuration Register*/
\r
14515 #define PREF_PCON_IBYP_Pos (0U)
\r
14516 #define PREF_PCON_IBYP_Msk (0x00000001U << PREF_PCON_IBYP_Pos)
\r
14518 #define PREF_PCON_IINV_Pos (1U)
\r
14519 #define PREF_PCON_IINV_Msk (0x00000001U << PREF_PCON_IINV_Pos)
\r
14521 #define PREF_PCON_PBS_Pos (16U)
\r
14522 #define PREF_PCON_PBS_Msk (0x00000001U << PREF_PCON_PBS_Pos)
\r
14526 /*** RTC Bit Fileds *******************/
\r
14527 /***************************************************************************/
\r
14530 /* RTC_ID = RTC ID Register*/
\r
14531 #define RTC_ID_ID_Pos (0U)
\r
14532 #define RTC_ID_ID_Msk (0xFFFFFFFFU << RTC_ID_ID_Pos)
\r
14534 /* RTC_CTR = RTC Control Register*/
\r
14535 #define RTC_CTR_ENB_Pos (0U)
\r
14536 #define RTC_CTR_ENB_Msk (0x00000001U << RTC_CTR_ENB_Pos)
\r
14538 #define RTC_CTR_TAE_Pos (2U)
\r
14539 #define RTC_CTR_TAE_Msk (0x00000001U << RTC_CTR_TAE_Pos)
\r
14541 #define RTC_CTR_ESEC_Pos (8U)
\r
14542 #define RTC_CTR_ESEC_Msk (0x00000001U << RTC_CTR_ESEC_Pos)
\r
14544 #define RTC_CTR_EMIC_Pos (9U)
\r
14545 #define RTC_CTR_EMIC_Msk (0x00000001U << RTC_CTR_EMIC_Pos)
\r
14547 #define RTC_CTR_EHOC_Pos (10U)
\r
14548 #define RTC_CTR_EHOC_Msk (0x00000001U << RTC_CTR_EHOC_Pos)
\r
14550 #define RTC_CTR_EDAC_Pos (11U)
\r
14551 #define RTC_CTR_EDAC_Msk (0x00000001U << RTC_CTR_EDAC_Pos)
\r
14553 #define RTC_CTR_EDAWEC_Pos (12U)
\r
14554 #define RTC_CTR_EDAWEC_Msk (0x00000001U << RTC_CTR_EDAWEC_Pos)
\r
14556 #define RTC_CTR_EMOC_Pos (13U)
\r
14557 #define RTC_CTR_EMOC_Msk (0x00000001U << RTC_CTR_EMOC_Pos)
\r
14559 #define RTC_CTR_EYEC_Pos (14U)
\r
14560 #define RTC_CTR_EYEC_Msk (0x00000001U << RTC_CTR_EYEC_Pos)
\r
14562 #define RTC_CTR_DIV_Pos (16U)
\r
14563 #define RTC_CTR_DIV_Msk (0x0000FFFFU << RTC_CTR_DIV_Pos)
\r
14565 /* RTC_RAWSTAT = RTC Raw Service Request Register*/
\r
14566 #define RTC_RAWSTAT_RPSE_Pos (0U)
\r
14567 #define RTC_RAWSTAT_RPSE_Msk (0x00000001U << RTC_RAWSTAT_RPSE_Pos)
\r
14569 #define RTC_RAWSTAT_RPMI_Pos (1U)
\r
14570 #define RTC_RAWSTAT_RPMI_Msk (0x00000001U << RTC_RAWSTAT_RPMI_Pos)
\r
14572 #define RTC_RAWSTAT_RPHO_Pos (2U)
\r
14573 #define RTC_RAWSTAT_RPHO_Msk (0x00000001U << RTC_RAWSTAT_RPHO_Pos)
\r
14575 #define RTC_RAWSTAT_RPDA_Pos (3U)
\r
14576 #define RTC_RAWSTAT_RPDA_Msk (0x00000001U << RTC_RAWSTAT_RPDA_Pos)
\r
14578 #define RTC_RAWSTAT_RPMO_Pos (5U)
\r
14579 #define RTC_RAWSTAT_RPMO_Msk (0x00000001U << RTC_RAWSTAT_RPMO_Pos)
\r
14581 #define RTC_RAWSTAT_RPYE_Pos (6U)
\r
14582 #define RTC_RAWSTAT_RPYE_Msk (0x00000001U << RTC_RAWSTAT_RPYE_Pos)
\r
14584 #define RTC_RAWSTAT_RAI_Pos (8U)
\r
14585 #define RTC_RAWSTAT_RAI_Msk (0x00000001U << RTC_RAWSTAT_RAI_Pos)
\r
14587 /* RTC_STSSR = RTC Service Request Status Register*/
\r
14588 #define RTC_STSSR_SPSE_Pos (0U)
\r
14589 #define RTC_STSSR_SPSE_Msk (0x00000001U << RTC_STSSR_SPSE_Pos)
\r
14591 #define RTC_STSSR_SPMI_Pos (1U)
\r
14592 #define RTC_STSSR_SPMI_Msk (0x00000001U << RTC_STSSR_SPMI_Pos)
\r
14594 #define RTC_STSSR_SPHO_Pos (2U)
\r
14595 #define RTC_STSSR_SPHO_Msk (0x00000001U << RTC_STSSR_SPHO_Pos)
\r
14597 #define RTC_STSSR_SPDA_Pos (3U)
\r
14598 #define RTC_STSSR_SPDA_Msk (0x00000001U << RTC_STSSR_SPDA_Pos)
\r
14600 #define RTC_STSSR_SPMO_Pos (5U)
\r
14601 #define RTC_STSSR_SPMO_Msk (0x00000001U << RTC_STSSR_SPMO_Pos)
\r
14603 #define RTC_STSSR_SPYE_Pos (6U)
\r
14604 #define RTC_STSSR_SPYE_Msk (0x00000001U << RTC_STSSR_SPYE_Pos)
\r
14606 #define RTC_STSSR_SAI_Pos (8U)
\r
14607 #define RTC_STSSR_SAI_Msk (0x00000001U << RTC_STSSR_SAI_Pos)
\r
14609 /* RTC_MSKSR = RTC Service Request Mask Register*/
\r
14610 #define RTC_MSKSR_MPSE_Pos (0U)
\r
14611 #define RTC_MSKSR_MPSE_Msk (0x00000001U << RTC_MSKSR_MPSE_Pos)
\r
14613 #define RTC_MSKSR_MPMI_Pos (1U)
\r
14614 #define RTC_MSKSR_MPMI_Msk (0x00000001U << RTC_MSKSR_MPMI_Pos)
\r
14616 #define RTC_MSKSR_MPHO_Pos (2U)
\r
14617 #define RTC_MSKSR_MPHO_Msk (0x00000001U << RTC_MSKSR_MPHO_Pos)
\r
14619 #define RTC_MSKSR_MPDA_Pos (3U)
\r
14620 #define RTC_MSKSR_MPDA_Msk (0x00000001U << RTC_MSKSR_MPDA_Pos)
\r
14622 #define RTC_MSKSR_MPMO_Pos (5U)
\r
14623 #define RTC_MSKSR_MPMO_Msk (0x00000001U << RTC_MSKSR_MPMO_Pos)
\r
14625 #define RTC_MSKSR_MPYE_Pos (6U)
\r
14626 #define RTC_MSKSR_MPYE_Msk (0x00000001U << RTC_MSKSR_MPYE_Pos)
\r
14628 #define RTC_MSKSR_MAI_Pos (8U)
\r
14629 #define RTC_MSKSR_MAI_Msk (0x00000001U << RTC_MSKSR_MAI_Pos)
\r
14631 /* RTC_CLRSR = RTC Clear Service Request Register*/
\r
14632 #define RTC_CLRSR_RPSE_Pos (0U)
\r
14633 #define RTC_CLRSR_RPSE_Msk (0x00000001U << RTC_CLRSR_RPSE_Pos)
\r
14635 #define RTC_CLRSR_RPMI_Pos (1U)
\r
14636 #define RTC_CLRSR_RPMI_Msk (0x00000001U << RTC_CLRSR_RPMI_Pos)
\r
14638 #define RTC_CLRSR_RPHO_Pos (2U)
\r
14639 #define RTC_CLRSR_RPHO_Msk (0x00000001U << RTC_CLRSR_RPHO_Pos)
\r
14641 #define RTC_CLRSR_RPDA_Pos (3U)
\r
14642 #define RTC_CLRSR_RPDA_Msk (0x00000001U << RTC_CLRSR_RPDA_Pos)
\r
14644 #define RTC_CLRSR_RPMO_Pos (5U)
\r
14645 #define RTC_CLRSR_RPMO_Msk (0x00000001U << RTC_CLRSR_RPMO_Pos)
\r
14647 #define RTC_CLRSR_RPYE_Pos (6U)
\r
14648 #define RTC_CLRSR_RPYE_Msk (0x00000001U << RTC_CLRSR_RPYE_Pos)
\r
14650 #define RTC_CLRSR_RAI_Pos (8U)
\r
14651 #define RTC_CLRSR_RAI_Msk (0x00000001U << RTC_CLRSR_RAI_Pos)
\r
14653 /* RTC_ATIM0 = RTC Alarm Time Register 0*/
\r
14654 #define RTC_ATIM0_ASE_Pos (0U)
\r
14655 #define RTC_ATIM0_ASE_Msk (0x0000003FU << RTC_ATIM0_ASE_Pos)
\r
14657 #define RTC_ATIM0_AMI_Pos (8U)
\r
14658 #define RTC_ATIM0_AMI_Msk (0x0000003FU << RTC_ATIM0_AMI_Pos)
\r
14660 #define RTC_ATIM0_AHO_Pos (16U)
\r
14661 #define RTC_ATIM0_AHO_Msk (0x0000001FU << RTC_ATIM0_AHO_Pos)
\r
14663 #define RTC_ATIM0_ADA_Pos (24U)
\r
14664 #define RTC_ATIM0_ADA_Msk (0x0000001FU << RTC_ATIM0_ADA_Pos)
\r
14666 /* RTC_ATIM1 = RTC Alarm Time Register 1*/
\r
14667 #define RTC_ATIM1_ADAWE_Pos (0U)
\r
14668 #define RTC_ATIM1_ADAWE_Msk (0x00000007U << RTC_ATIM1_ADAWE_Pos)
\r
14670 #define RTC_ATIM1_AMO_Pos (8U)
\r
14671 #define RTC_ATIM1_AMO_Msk (0x0000000FU << RTC_ATIM1_AMO_Pos)
\r
14673 #define RTC_ATIM1_AYE_Pos (16U)
\r
14674 #define RTC_ATIM1_AYE_Msk (0x0000FFFFU << RTC_ATIM1_AYE_Pos)
\r
14676 /* RTC_TIM0 = RTC Time Register 0*/
\r
14677 #define RTC_TIM0_SE_Pos (0U)
\r
14678 #define RTC_TIM0_SE_Msk (0x0000003FU << RTC_TIM0_SE_Pos)
\r
14680 #define RTC_TIM0_MI_Pos (8U)
\r
14681 #define RTC_TIM0_MI_Msk (0x0000003FU << RTC_TIM0_MI_Pos)
\r
14683 #define RTC_TIM0_HO_Pos (16U)
\r
14684 #define RTC_TIM0_HO_Msk (0x0000001FU << RTC_TIM0_HO_Pos)
\r
14686 #define RTC_TIM0_DA_Pos (24U)
\r
14687 #define RTC_TIM0_DA_Msk (0x0000001FU << RTC_TIM0_DA_Pos)
\r
14689 /* RTC_TIM1 = RTC Time Register 1*/
\r
14690 #define RTC_TIM1_DAWE_Pos (0U)
\r
14691 #define RTC_TIM1_DAWE_Msk (0x00000007U << RTC_TIM1_DAWE_Pos)
\r
14693 #define RTC_TIM1_MO_Pos (8U)
\r
14694 #define RTC_TIM1_MO_Msk (0x0000000FU << RTC_TIM1_MO_Pos)
\r
14696 #define RTC_TIM1_YE_Pos (16U)
\r
14697 #define RTC_TIM1_YE_Msk (0x0000FFFFU << RTC_TIM1_YE_Pos)
\r
14701 /*** SCU Bit Fileds *******************/
\r
14702 /***************************************************************************/
\r
14705 /* SCU_PLL_PLLSTAT = PLL Status Register*/
\r
14706 #define SCU_PLL_PLLSTAT_VCOBYST_Pos (0U)
\r
14707 #define SCU_PLL_PLLSTAT_VCOBYST_Msk (0x00000001U << SCU_PLL_PLLSTAT_VCOBYST_Pos)
\r
14709 #define SCU_PLL_PLLSTAT_PWDSTAT_Pos (1U)
\r
14710 #define SCU_PLL_PLLSTAT_PWDSTAT_Msk (0x00000001U << SCU_PLL_PLLSTAT_PWDSTAT_Pos)
\r
14712 #define SCU_PLL_PLLSTAT_VCOLOCK_Pos (2U)
\r
14713 #define SCU_PLL_PLLSTAT_VCOLOCK_Msk (0x00000001U << SCU_PLL_PLLSTAT_VCOLOCK_Pos)
\r
14715 #define SCU_PLL_PLLSTAT_K1RDY_Pos (4U)
\r
14716 #define SCU_PLL_PLLSTAT_K1RDY_Msk (0x00000001U << SCU_PLL_PLLSTAT_K1RDY_Pos)
\r
14718 #define SCU_PLL_PLLSTAT_K2RDY_Pos (5U)
\r
14719 #define SCU_PLL_PLLSTAT_K2RDY_Msk (0x00000001U << SCU_PLL_PLLSTAT_K2RDY_Pos)
\r
14721 #define SCU_PLL_PLLSTAT_BY_Pos (6U)
\r
14722 #define SCU_PLL_PLLSTAT_BY_Msk (0x00000001U << SCU_PLL_PLLSTAT_BY_Pos)
\r
14724 #define SCU_PLL_PLLSTAT_PLLLV_Pos (7U)
\r
14725 #define SCU_PLL_PLLSTAT_PLLLV_Msk (0x00000001U << SCU_PLL_PLLSTAT_PLLLV_Pos)
\r
14727 #define SCU_PLL_PLLSTAT_PLLHV_Pos (8U)
\r
14728 #define SCU_PLL_PLLSTAT_PLLHV_Msk (0x00000001U << SCU_PLL_PLLSTAT_PLLHV_Pos)
\r
14730 #define SCU_PLL_PLLSTAT_PLLSP_Pos (9U)
\r
14731 #define SCU_PLL_PLLSTAT_PLLSP_Msk (0x00000001U << SCU_PLL_PLLSTAT_PLLSP_Pos)
\r
14733 /* SCU_PLL_PLLCON0 = PLL Configuration x Register*/
\r
14734 #define SCU_PLL_PLLCON0_VCOBYP_Pos (0U)
\r
14735 #define SCU_PLL_PLLCON0_VCOBYP_Msk (0x00000001U << SCU_PLL_PLLCON0_VCOBYP_Pos)
\r
14737 #define SCU_PLL_PLLCON0_VCOPWD_Pos (1U)
\r
14738 #define SCU_PLL_PLLCON0_VCOPWD_Msk (0x00000001U << SCU_PLL_PLLCON0_VCOPWD_Pos)
\r
14740 #define SCU_PLL_PLLCON0_VCOTR_Pos (2U)
\r
14741 #define SCU_PLL_PLLCON0_VCOTR_Msk (0x00000001U << SCU_PLL_PLLCON0_VCOTR_Pos)
\r
14743 #define SCU_PLL_PLLCON0_FINDIS_Pos (4U)
\r
14744 #define SCU_PLL_PLLCON0_FINDIS_Msk (0x00000001U << SCU_PLL_PLLCON0_FINDIS_Pos)
\r
14746 #define SCU_PLL_PLLCON0_OSCDISCDIS_Pos (6U)
\r
14747 #define SCU_PLL_PLLCON0_OSCDISCDIS_Msk (0x00000001U << SCU_PLL_PLLCON0_OSCDISCDIS_Pos)
\r
14749 #define SCU_PLL_PLLCON0_PLLPWD_Pos (16U)
\r
14750 #define SCU_PLL_PLLCON0_PLLPWD_Msk (0x00000001U << SCU_PLL_PLLCON0_PLLPWD_Pos)
\r
14752 #define SCU_PLL_PLLCON0_OSCRES_Pos (17U)
\r
14753 #define SCU_PLL_PLLCON0_OSCRES_Msk (0x00000001U << SCU_PLL_PLLCON0_OSCRES_Pos)
\r
14755 #define SCU_PLL_PLLCON0_RESLD_Pos (18U)
\r
14756 #define SCU_PLL_PLLCON0_RESLD_Msk (0x00000001U << SCU_PLL_PLLCON0_RESLD_Pos)
\r
14758 #define SCU_PLL_PLLCON0_AOTREN_Pos (19U)
\r
14759 #define SCU_PLL_PLLCON0_AOTREN_Msk (0x00000001U << SCU_PLL_PLLCON0_AOTREN_Pos)
\r
14761 #define SCU_PLL_PLLCON0_FOTR_Pos (20U)
\r
14762 #define SCU_PLL_PLLCON0_FOTR_Msk (0x00000001U << SCU_PLL_PLLCON0_FOTR_Pos)
\r
14764 /* SCU_PLL_PLLCON1 = PLL Configuration 1 Register*/
\r
14765 #define SCU_PLL_PLLCON1_K1DIV_Pos (0U)
\r
14766 #define SCU_PLL_PLLCON1_K1DIV_Msk (0x0000007FU << SCU_PLL_PLLCON1_K1DIV_Pos)
\r
14768 #define SCU_PLL_PLLCON1_NDIV_Pos (8U)
\r
14769 #define SCU_PLL_PLLCON1_NDIV_Msk (0x0000007FU << SCU_PLL_PLLCON1_NDIV_Pos)
\r
14771 #define SCU_PLL_PLLCON1_K2DIV_Pos (16U)
\r
14772 #define SCU_PLL_PLLCON1_K2DIV_Msk (0x0000007FU << SCU_PLL_PLLCON1_K2DIV_Pos)
\r
14774 #define SCU_PLL_PLLCON1_PDIV_Pos (24U)
\r
14775 #define SCU_PLL_PLLCON1_PDIV_Msk (0x0000000FU << SCU_PLL_PLLCON1_PDIV_Pos)
\r
14777 /* SCU_PLL_PLLCON2 = PLL Configuration 2 Register*/
\r
14778 #define SCU_PLL_PLLCON2_PINSEL_Pos (0U)
\r
14779 #define SCU_PLL_PLLCON2_PINSEL_Msk (0x00000001U << SCU_PLL_PLLCON2_PINSEL_Pos)
\r
14781 #define SCU_PLL_PLLCON2_K1INSEL_Pos (8U)
\r
14782 #define SCU_PLL_PLLCON2_K1INSEL_Msk (0x00000001U << SCU_PLL_PLLCON2_K1INSEL_Pos)
\r
14784 /* SCU_PLL_USBPLL_PLLSTAT = USB PLL Status Register*/
\r
14785 #define SCU_PLL_USBPLLSTAT_VCOBYST_Pos (0U)
\r
14786 #define SCU_PLL_USBPLLSTAT_VCOBYST_Msk (0x00000001U << SCU_PLL_USBPLLSTAT_VCOBYST_Pos)
\r
14788 #define SCU_PLL_USBPLLSTAT_PWDSTAT_Pos (1U)
\r
14789 #define SCU_PLL_USBPLLSTAT_PWDSTAT_Msk (0x00000001U << SCU_PLL_USBPLLSTAT_PWDSTAT_Pos)
\r
14791 #define SCU_PLL_USBPLLSTAT_VCOLOCK_Pos (2U)
\r
14792 #define SCU_PLL_USBPLLSTAT_VCOLOCK_Msk (0x00000001U << SCU_PLL_USBPLLSTAT_VCOLOCK_Pos)
\r
14794 #define SCU_PLL_USBPLLSTAT_BY_Pos (6U)
\r
14795 #define SCU_PLL_USBPLLSTAT_BY_Msk (0x00000001U << SCU_PLL_USBPLLSTAT_BY_Pos)
\r
14797 #define SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos (7U)
\r
14798 #define SCU_PLL_USBPLLSTAT_VCOLOCKED_Msk (0x00000001U << SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos)
\r
14800 /* SCU_PLL_USBPLLCON = USB PLL Configuration Register*/
\r
14801 #define SCU_PLL_USBPLLCON_VCOBYP_Pos (0U)
\r
14802 #define SCU_PLL_USBPLLCON_VCOBYP_Msk (0x00000001U << SCU_PLL_USBPLLCON_VCOBYP_Pos)
\r
14804 #define SCU_PLL_USBPLLCON_VCOPWD_Pos (1U)
\r
14805 #define SCU_PLL_USBPLLCON_VCOPWD_Msk (0x00000001U << SCU_PLL_USBPLLCON_VCOPWD_Pos)
\r
14807 #define SCU_PLL_USBPLLCON_VCOTR_Pos (2U)
\r
14808 #define SCU_PLL_USBPLLCON_VCOTR_Msk (0x00000001U << SCU_PLL_USBPLLCON_VCOTR_Pos)
\r
14810 #define SCU_PLL_USBPLLCON_FINDIS_Pos (4U)
\r
14811 #define SCU_PLL_USBPLLCON_FINDIS_Msk (0x00000001U << SCU_PLL_USBPLLCON_FINDIS_Pos)
\r
14813 #define SCU_PLL_USBPLLCON_OSCDISCDIS_Pos (6U)
\r
14814 #define SCU_PLL_USBPLLCON_OSCDISCDIS_Msk (0x00000001U << SCU_PLL_USBPLLCON_OSCDISCDIS_Pos)
\r
14816 #define SCU_PLL_USBPLLCON_NDIV_Pos (8U)
\r
14817 #define SCU_PLL_USBPLLCON_NDIV_Msk (0x0000007FU << SCU_PLL_USBPLLCON_NDIV_Pos)
\r
14819 #define SCU_PLL_USBPLLCON_PLLPWD_Pos (16U)
\r
14820 #define SCU_PLL_USBPLLCON_PLLPWD_Msk (0x00000001U << SCU_PLL_USBPLLCON_PLLPWD_Pos)
\r
14822 #define SCU_PLL_USBPLLCON_RESLD_Pos (18U)
\r
14823 #define SCU_PLL_USBPLLCON_RESLD_Msk (0x00000001U << SCU_PLL_USBPLLCON_RESLD_Pos)
\r
14825 #define SCU_PLL_USBPLLCON_PDIV_Pos (24U)
\r
14826 #define SCU_PLL_USBPLLCON_PDIV_Msk (0x0000000FU << SCU_PLL_USBPLLCON_PDIV_Pos)
\r
14828 /* SCU_PLL_CLKMXSTAT = Clock Multiplexing Status Register*/
\r
14829 #define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos (0U)
\r
14830 #define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Msk (0x00000007U << SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos)
\r
14832 /* SCU_OSC_OSCHPSTAT = OSC_HP Status Register*/
\r
14833 #define SCU_OSC_OSCHPSTAT_X1D_Pos (0U)
\r
14834 #define SCU_OSC_OSCHPSTAT_X1D_Msk (0x00000001U << SCU_OSC_OSCHPSTAT_X1D_Pos)
\r
14836 /* SCU_OSC_OSCHPCTRL = OSC_HP Control Register*/
\r
14837 #define SCU_OSC_OSCHPCTRL_X1DEN_Pos (0U)
\r
14838 #define SCU_OSC_OSCHPCTRL_X1DEN_Msk (0x00000001U << SCU_OSC_OSCHPCTRL_X1DEN_Pos)
\r
14840 #define SCU_OSC_OSCHPCTRL_SHBY_Pos (1U)
\r
14841 #define SCU_OSC_OSCHPCTRL_SHBY_Msk (0x00000001U << SCU_OSC_OSCHPCTRL_SHBY_Pos)
\r
14843 #define SCU_OSC_OSCHPCTRL_GAINSEL_Pos (2U)
\r
14844 #define SCU_OSC_OSCHPCTRL_GAINSEL_Msk (0x00000003U << SCU_OSC_OSCHPCTRL_GAINSEL_Pos)
\r
14846 #define SCU_OSC_OSCHPCTRL_MODE_Pos (4U)
\r
14847 #define SCU_OSC_OSCHPCTRL_MODE_Msk (0x00000003U << SCU_OSC_OSCHPCTRL_MODE_Pos)
\r
14849 #define SCU_OSC_OSCHPCTRL_OSCVAL_Pos (16U)
\r
14850 #define SCU_OSC_OSCHPCTRL_OSCVAL_Msk (0x0000001FU << SCU_OSC_OSCHPCTRL_OSCVAL_Pos)
\r
14852 /* SCU_CLK_CLKSTAT = Clock Status Register*/
\r
14853 #define SCU_CLK_CLKSTAT_USBCST_Pos (0U)
\r
14854 #define SCU_CLK_CLKSTAT_USBCST_Msk (0x00000001U << SCU_CLK_CLKSTAT_USBCST_Pos)
\r
14856 #define SCU_CLK_CLKSTAT_MMCCST_Pos (1U)
\r
14857 #define SCU_CLK_CLKSTAT_MMCCST_Msk (0x00000001U << SCU_CLK_CLKSTAT_MMCCST_Pos)
\r
14859 #define SCU_CLK_CLKSTAT_ETH0CST_Pos (2U)
\r
14860 #define SCU_CLK_CLKSTAT_ETH0CST_Msk (0x00000001U << SCU_CLK_CLKSTAT_ETH0CST_Pos)
\r
14862 #define SCU_CLK_CLKSTAT_EBUCST_Pos (3U)
\r
14863 #define SCU_CLK_CLKSTAT_EBUCST_Msk (0x00000001U << SCU_CLK_CLKSTAT_EBUCST_Pos)
\r
14865 #define SCU_CLK_CLKSTAT_CCUCST_Pos (4U)
\r
14866 #define SCU_CLK_CLKSTAT_CCUCST_Msk (0x00000001U << SCU_CLK_CLKSTAT_CCUCST_Pos)
\r
14868 #define SCU_CLK_CLKSTAT_WDTCST_Pos (5U)
\r
14869 #define SCU_CLK_CLKSTAT_WDTCST_Msk (0x00000001U << SCU_CLK_CLKSTAT_WDTCST_Pos)
\r
14871 /* SCU_CLK_CLKSET = CLK Set Register*/
\r
14872 #define SCU_CLK_CLKSET_USBCEN_Pos (0U)
\r
14873 #define SCU_CLK_CLKSET_USBCEN_Msk (0x00000001U << SCU_CLK_CLKSET_USBCEN_Pos)
\r
14875 #define SCU_CLK_CLKSET_MMCCEN_Pos (1U)
\r
14876 #define SCU_CLK_CLKSET_MMCCEN_Msk (0x00000001U << SCU_CLK_CLKSET_MMCCEN_Pos)
\r
14878 #define SCU_CLK_CLKSET_ETH0CEN_Pos (2U)
\r
14879 #define SCU_CLK_CLKSET_ETH0CEN_Msk (0x00000001U << SCU_CLK_CLKSET_ETH0CEN_Pos)
\r
14881 #define SCU_CLK_CLKSET_EBUCEN_Pos (3U)
\r
14882 #define SCU_CLK_CLKSET_EBUCEN_Msk (0x00000001U << SCU_CLK_CLKSET_EBUCEN_Pos)
\r
14884 #define SCU_CLK_CLKSET_CCUCEN_Pos (4U)
\r
14885 #define SCU_CLK_CLKSET_CCUCEN_Msk (0x00000001U << SCU_CLK_CLKSET_CCUCEN_Pos)
\r
14887 #define SCU_CLK_CLKSET_WDTCEN_Pos (5U)
\r
14888 #define SCU_CLK_CLKSET_WDTCEN_Msk (0x00000001U << SCU_CLK_CLKSET_WDTCEN_Pos)
\r
14890 /* SCU_CLK_CLKCLR = CLK Clear Register*/
\r
14891 #define SCU_CLK_CLKCLR_USBCDI_Pos (0U)
\r
14892 #define SCU_CLK_CLKCLR_USBCDI_Msk (0x00000001U << SCU_CLK_CLKCLR_USBCDI_Pos)
\r
14894 #define SCU_CLK_CLKCLR_MMCCDI_Pos (1U)
\r
14895 #define SCU_CLK_CLKCLR_MMCCDI_Msk (0x00000001U << SCU_CLK_CLKCLR_MMCCDI_Pos)
\r
14897 #define SCU_CLK_CLKCLR_ETH0CDI_Pos (2U)
\r
14898 #define SCU_CLK_CLKCLR_ETH0CDI_Msk (0x00000001U << SCU_CLK_CLKCLR_ETH0CDI_Pos)
\r
14900 #define SCU_CLK_CLKCLR_EBUCDI_Pos (3U)
\r
14901 #define SCU_CLK_CLKCLR_EBUCDI_Msk (0x00000001U << SCU_CLK_CLKCLR_EBUCDI_Pos)
\r
14903 #define SCU_CLK_CLKCLR_CCUCDI_Pos (4U)
\r
14904 #define SCU_CLK_CLKCLR_CCUCDI_Msk (0x00000001U << SCU_CLK_CLKCLR_CCUCDI_Pos)
\r
14906 #define SCU_CLK_CLKCLR_WDTCDI_Pos (5U)
\r
14907 #define SCU_CLK_CLKCLR_WDTCDI_Msk (0x00000001U << SCU_CLK_CLKCLR_WDTCDI_Pos)
\r
14909 /* SCU_CLK_SYSCLKCR = System Clock Control Register*/
\r
14910 #define SCU_CLK_SYSCLKCR_SYSDIV_Pos (0U)
\r
14911 #define SCU_CLK_SYSCLKCR_SYSDIV_Msk (0x000000FFU << SCU_CLK_SYSCLKCR_SYSDIV_Pos)
\r
14913 #define SCU_CLK_SYSCLKCR_SYSSEL_Pos (16U)
\r
14914 #define SCU_CLK_SYSCLKCR_SYSSEL_Msk (0x00000003U << SCU_CLK_SYSCLKCR_SYSSEL_Pos)
\r
14916 /* SCU_CLK_CPUCLKCR = CPU Clock Control Register*/
\r
14917 #define SCU_CLK_CPUCLKCR_CPUDIV_Pos (0U)
\r
14918 #define SCU_CLK_CPUCLKCR_CPUDIV_Msk (0x00000001U << SCU_CLK_CPUCLKCR_CPUDIV_Pos)
\r
14920 /* SCU_CLK_PBCLKCR = Peripheral Bus Clock Control Register*/
\r
14921 #define SCU_CLK_PBCLKCR_PBDIV_Pos (0U)
\r
14922 #define SCU_CLK_PBCLKCR_PBDIV_Msk (0x00000001U << SCU_CLK_PBCLKCR_PBDIV_Pos)
\r
14924 /* SCU_CLK_USBCLKCR = USB Clock Control Register*/
\r
14925 #define SCU_CLK_USBCLKCR_USBDIV_Pos (0U)
\r
14926 #define SCU_CLK_USBCLKCR_USBDIV_Msk (0x00000007U << SCU_CLK_USBCLKCR_USBDIV_Pos)
\r
14928 #define SCU_CLK_USBCLKCR_USBSEL_Pos (16U)
\r
14929 #define SCU_CLK_USBCLKCR_USBSEL_Msk (0x00000001U << SCU_CLK_USBCLKCR_USBSEL_Pos)
\r
14931 /* SCU_CLK_EBUCLKCR = EBU Clock Control Register*/
\r
14932 #define SCU_CLK_EBUCLKCR_EBUDIV_Pos (0U)
\r
14933 #define SCU_CLK_EBUCLKCR_EBUDIV_Msk (0x0000003FU << SCU_CLK_EBUCLKCR_EBUDIV_Pos)
\r
14935 /* SCU_CLK_CCUCLKCR = CCU Clock Control Register*/
\r
14936 #define SCU_CLK_CCUCLKCR_CCUDIV_Pos (0U)
\r
14937 #define SCU_CLK_CCUCLKCR_CCUDIV_Msk (0x00000001U << SCU_CLK_CCUCLKCR_CCUDIV_Pos)
\r
14939 /* SCU_CLK_WDTCLKCR = WDT Clock Control Register*/
\r
14940 #define SCU_CLK_WDTCLKCR_WDTDIV_Pos (0U)
\r
14941 #define SCU_CLK_WDTCLKCR_WDTDIV_Msk (0x000000FFU << SCU_CLK_WDTCLKCR_WDTDIV_Pos)
\r
14943 #define SCU_CLK_WDTCLKCR_WDTSEL_Pos (16U)
\r
14944 #define SCU_CLK_WDTCLKCR_WDTSEL_Msk (0x00000003U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
\r
14946 /* SCU_CLK_EXTCLKCR = External Clock Control*/
\r
14947 #define SCU_CLK_EXTCLKCR_ECKSEL_Pos (0U)
\r
14948 #define SCU_CLK_EXTCLKCR_ECKSEL_Msk (0x00000003U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
\r
14950 #define SCU_CLK_EXTCLKCR_ECKDIV_Pos (16U)
\r
14951 #define SCU_CLK_EXTCLKCR_ECKDIV_Msk (0x000001FFU << SCU_CLK_EXTCLKCR_ECKDIV_Pos)
\r
14953 /* SCU_CLK_SLEEPCR = Sleep Control Register*/
\r
14954 #define SCU_CLK_SLEEPCR_SYSSEL_Pos (0U)
\r
14955 #define SCU_CLK_SLEEPCR_SYSSEL_Msk (0x00000003U << SCU_CLK_SLEEPCR_SYSSEL_Pos)
\r
14957 #define SCU_CLK_SLEEPCR_USBCR_Pos (16U)
\r
14958 #define SCU_CLK_SLEEPCR_USBCR_Msk (0x00000001U << SCU_CLK_SLEEPCR_USBCR_Pos)
\r
14960 #define SCU_CLK_SLEEPCR_MMCCR_Pos (17U)
\r
14961 #define SCU_CLK_SLEEPCR_MMCCR_Msk (0x00000001U << SCU_CLK_SLEEPCR_MMCCR_Pos)
\r
14963 #define SCU_CLK_SLEEPCR_ETH0CR_Pos (18U)
\r
14964 #define SCU_CLK_SLEEPCR_ETH0CR_Msk (0x00000001U << SCU_CLK_SLEEPCR_ETH0CR_Pos)
\r
14966 #define SCU_CLK_SLEEPCR_EBUCR_Pos (19U)
\r
14967 #define SCU_CLK_SLEEPCR_EBUCR_Msk (0x00000001U << SCU_CLK_SLEEPCR_EBUCR_Pos)
\r
14969 #define SCU_CLK_SLEEPCR_CCUCR_Pos (20U)
\r
14970 #define SCU_CLK_SLEEPCR_CCUCR_Msk (0x00000001U << SCU_CLK_SLEEPCR_CCUCR_Pos)
\r
14972 #define SCU_CLK_SLEEPCR_WDTCR_Pos (21U)
\r
14973 #define SCU_CLK_SLEEPCR_WDTCR_Msk (0x00000001U << SCU_CLK_SLEEPCR_WDTCR_Pos)
\r
14975 /* SCU_CLK_DSLEEPCR = Deep Sleep Control Register*/
\r
14976 #define SCU_CLK_DSLEEPCR_SYSSEL_Pos (0U)
\r
14977 #define SCU_CLK_DSLEEPCR_SYSSEL_Msk (0x00000003U << SCU_CLK_DSLEEPCR_SYSSEL_Pos)
\r
14979 #define SCU_CLK_DSLEEPCR_FPDN_Pos (11U)
\r
14980 #define SCU_CLK_DSLEEPCR_FPDN_Msk (0x00000001U << SCU_CLK_DSLEEPCR_FPDN_Pos)
\r
14982 #define SCU_CLK_DSLEEPCR_PLLPDN_Pos (12U)
\r
14983 #define SCU_CLK_DSLEEPCR_PLLPDN_Msk (0x00000001U << SCU_CLK_DSLEEPCR_PLLPDN_Pos)
\r
14985 #define SCU_CLK_DSLEEPCR_VCOPDN_Pos (13U)
\r
14986 #define SCU_CLK_DSLEEPCR_VCOPDN_Msk (0x00000001U << SCU_CLK_DSLEEPCR_VCOPDN_Pos)
\r
14988 #define SCU_CLK_DSLEEPCR_USBCR_Pos (16U)
\r
14989 #define SCU_CLK_DSLEEPCR_USBCR_Msk (0x00000001U << SCU_CLK_DSLEEPCR_USBCR_Pos)
\r
14991 #define SCU_CLK_DSLEEPCR_MMCCR_Pos (17U)
\r
14992 #define SCU_CLK_DSLEEPCR_MMCCR_Msk (0x00000001U << SCU_CLK_DSLEEPCR_MMCCR_Pos)
\r
14994 #define SCU_CLK_DSLEEPCR_ETH0CR_Pos (18U)
\r
14995 #define SCU_CLK_DSLEEPCR_ETH0CR_Msk (0x00000001U << SCU_CLK_DSLEEPCR_ETH0CR_Pos)
\r
14997 #define SCU_CLK_DSLEEPCR_EBUCR_Pos (19U)
\r
14998 #define SCU_CLK_DSLEEPCR_EBUCR_Msk (0x00000001U << SCU_CLK_DSLEEPCR_EBUCR_Pos)
\r
15000 #define SCU_CLK_DSLEEPCR_CCUCR_Pos (20U)
\r
15001 #define SCU_CLK_DSLEEPCR_CCUCR_Msk (0x00000001U << SCU_CLK_DSLEEPCR_CCUCR_Pos)
\r
15003 #define SCU_CLK_DSLEEPCR_WDTCR_Pos (21U)
\r
15004 #define SCU_CLK_DSLEEPCR_WDTCR_Msk (0x00000001U << SCU_CLK_DSLEEPCR_WDTCR_Pos)
\r
15008 /*** SCU Bit Fileds *******************/
\r
15009 /***************************************************************************/
\r
15012 /* SCU_GENERAL_ID = SCU Module ID Register*/
\r
15013 #define SCU_GENERAL_ID_ID_Pos (0U)
\r
15014 #define SCU_GENERAL_ID_ID_Msk (0xFFFFFFFFU << SCU_GENERAL_ID_ID_Pos)
\r
15016 /* SCU_GENERAL_IDCHIP = Chip ID Register*/
\r
15017 #define SCU_GENERAL_IDCHIP_IDCHIP_Pos (0U)
\r
15018 #define SCU_GENERAL_IDCHIP_IDCHIP_Msk (0xFFFFFFFFU << SCU_GENERAL_IDCHIP_IDCHIP_Pos)
\r
15020 /* SCU_GENERAL_IDMANUF = Manufactory ID Register*/
\r
15021 #define SCU_GENERAL_IDMANUF_IDMANUF_Pos (0U)
\r
15022 #define SCU_GENERAL_IDMANUF_IDMANUF_Msk (0xFFFFFFFFU << SCU_GENERAL_IDMANUF_IDMANUF_Pos)
\r
15024 /* SCU_GENERAL_STCON = Startup Configuration Register*/
\r
15025 #define SCU_GENERAL_STCON_HWCON_Pos (0U)
\r
15026 #define SCU_GENERAL_STCON_HWCON_Msk (0x00000003U << SCU_GENERAL_STCON_HWCON_Pos)
\r
15028 #define SCU_GENERAL_STCON_SWCON_Pos (8U)
\r
15029 #define SCU_GENERAL_STCON_SWCON_Msk (0x0000000FU << SCU_GENERAL_STCON_SWCON_Pos)
\r
15031 /* SCU_GENERAL_GPRx = General Purpose Register*/
\r
15032 #define SCU_GENERAL_GPR_DAT_Pos (0U)
\r
15033 #define SCU_GENERAL_GPR_DAT_Msk (0xFFFFFFFFU << SCU_GENERAL_GPR_DAT_Pos)
\r
15035 /* SCU_GENERAL_CCUCON = CCU Control Register*/
\r
15036 #define SCU_GENERAL_CCUCON_GSC40_Pos (0U)
\r
15037 #define SCU_GENERAL_CCUCON_GSC40_Msk (0x00000001U << SCU_GENERAL_CCUCON_GSC40_Pos)
\r
15039 #define SCU_GENERAL_CCUCON_GSC41_Pos (1U)
\r
15040 #define SCU_GENERAL_CCUCON_GSC41_Msk (0x00000001U << SCU_GENERAL_CCUCON_GSC41_Pos)
\r
15042 #define SCU_GENERAL_CCUCON_GSC42_Pos (2U)
\r
15043 #define SCU_GENERAL_CCUCON_GSC42_Msk (0x00000001U << SCU_GENERAL_CCUCON_GSC42_Pos)
\r
15045 #define SCU_GENERAL_CCUCON_GSC43_Pos (3U)
\r
15046 #define SCU_GENERAL_CCUCON_GSC43_Msk (0x00000001U << SCU_GENERAL_CCUCON_GSC43_Pos)
\r
15048 #define SCU_GENERAL_CCUCON_GSC80_Pos (8U)
\r
15049 #define SCU_GENERAL_CCUCON_GSC80_Msk (0x00000001U << SCU_GENERAL_CCUCON_GSC80_Pos)
\r
15051 #define SCU_GENERAL_CCUCON_GSC81_Pos (9U)
\r
15052 #define SCU_GENERAL_CCUCON_GSC81_Msk (0x00000001U << SCU_GENERAL_CCUCON_GSC81_Pos)
\r
15054 /* SCU_GENERAL_DTSCON = Die Temperature Sensor Control Register*/
\r
15055 #define SCU_GENERAL_DTSCON_PWD_Pos (0U)
\r
15056 #define SCU_GENERAL_DTSCON_PWD_Msk (0x00000001U << SCU_GENERAL_DTSCON_PWD_Pos)
\r
15058 #define SCU_GENERAL_DTSCON_START_Pos (1U)
\r
15059 #define SCU_GENERAL_DTSCON_START_Msk (0x00000001U << SCU_GENERAL_DTSCON_START_Pos)
\r
15061 #define SCU_GENERAL_DTSCON_OFFSET_Pos (4U)
\r
15062 #define SCU_GENERAL_DTSCON_OFFSET_Msk (0x0000007FU << SCU_GENERAL_DTSCON_OFFSET_Pos)
\r
15064 #define SCU_GENERAL_DTSCON_GAIN_Pos (11U)
\r
15065 #define SCU_GENERAL_DTSCON_GAIN_Msk (0x0000003FU << SCU_GENERAL_DTSCON_GAIN_Pos)
\r
15067 #define SCU_GENERAL_DTSCON_REFTRIM_Pos (17U)
\r
15068 #define SCU_GENERAL_DTSCON_REFTRIM_Msk (0x00000007U << SCU_GENERAL_DTSCON_REFTRIM_Pos)
\r
15070 #define SCU_GENERAL_DTSCON_BGTRIM_Pos (20U)
\r
15071 #define SCU_GENERAL_DTSCON_BGTRIM_Msk (0x0000000FU << SCU_GENERAL_DTSCON_BGTRIM_Pos)
\r
15073 /* SCU_GENERAL_DTSSTAT = Die Temperature Sensor Status Register*/
\r
15074 #define SCU_GENERAL_DTSSTAT_RESULT_Pos (0U)
\r
15075 #define SCU_GENERAL_DTSSTAT_RESULT_Msk (0x000003FFU << SCU_GENERAL_DTSSTAT_RESULT_Pos)
\r
15077 #define SCU_GENERAL_DTSSTAT_RDY_Pos (14U)
\r
15078 #define SCU_GENERAL_DTSSTAT_RDY_Msk (0x00000001U << SCU_GENERAL_DTSSTAT_RDY_Pos)
\r
15080 #define SCU_GENERAL_DTSSTAT_BUSY_Pos (15U)
\r
15081 #define SCU_GENERAL_DTSSTAT_BUSY_Msk (0x00000001U << SCU_GENERAL_DTSSTAT_BUSY_Pos)
\r
15083 /* SCU_GENERAL_SDMMCDEL = SD-MMC Delay Control Register*/
\r
15084 #define SCU_GENERAL_SDMMCDEL_TAPEN_Pos (0U)
\r
15085 #define SCU_GENERAL_SDMMCDEL_TAPEN_Msk (0x00000001U << SCU_GENERAL_SDMMCDEL_TAPEN_Pos)
\r
15087 #define SCU_GENERAL_SDMMCDEL_DLYCTRL_Pos (2U)
\r
15088 #define SCU_GENERAL_SDMMCDEL_DLYCTRL_Msk (0x00000003U << SCU_GENERAL_SDMMCDEL_DLYCTRL_Pos)
\r
15090 #define SCU_GENERAL_SDMMCDEL_TAPDEL_Pos (4U)
\r
15091 #define SCU_GENERAL_SDMMCDEL_TAPDEL_Msk (0x0000000FU << SCU_GENERAL_SDMMCDEL_TAPDEL_Pos)
\r
15093 /* SCU_GENERAL_GORCEN = Out of Range Comparator Enable Register 0*/
\r
15094 #define SCU_GENERAL_GORCEN_ENORC6_Pos (6U)
\r
15095 #define SCU_GENERAL_GORCEN_ENORC6_Msk (0x00000001U << SCU_GENERAL_GORCEN_ENORC6_Pos)
\r
15097 #define SCU_GENERAL_GORCEN_ENORC7_Pos (7U)
\r
15098 #define SCU_GENERAL_GORCEN_ENORC7_Msk (0x00000001U << SCU_GENERAL_GORCEN_ENORC7_Pos)
\r
15100 /* SCU_GENERAL_MIRRSTS = Mirror Update Status Register*/
\r
15101 #define SCU_GENERAL_MIRRSTS_HDSTAT_Pos (0U)
\r
15102 #define SCU_GENERAL_MIRRSTS_HDSTAT_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_HDSTAT_Pos)
\r
15104 #define SCU_GENERAL_MIRRSTS_HDCLR_Pos (1U)
\r
15105 #define SCU_GENERAL_MIRRSTS_HDCLR_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_HDCLR_Pos)
\r
15107 #define SCU_GENERAL_MIRRSTS_HDSET_Pos (2U)
\r
15108 #define SCU_GENERAL_MIRRSTS_HDSET_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_HDSET_Pos)
\r
15110 #define SCU_GENERAL_MIRRSTS_HDCR_Pos (3U)
\r
15111 #define SCU_GENERAL_MIRRSTS_HDCR_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_HDCR_Pos)
\r
15113 #define SCU_GENERAL_MIRRSTS_OSCSITRIM_Pos (4U)
\r
15114 #define SCU_GENERAL_MIRRSTS_OSCSITRIM_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_OSCSITRIM_Pos)
\r
15116 #define SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos (5U)
\r
15117 #define SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos)
\r
15119 #define SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos (6U)
\r
15120 #define SCU_GENERAL_MIRRSTS_OSCULSTAT_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos)
\r
15122 #define SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos (7U)
\r
15123 #define SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos)
\r
15125 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos (8U)
\r
15126 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_RTC_CTR_Pos)
\r
15128 #define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos (9U)
\r
15129 #define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos)
\r
15131 #define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos (10U)
\r
15132 #define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos)
\r
15134 #define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos (11U)
\r
15135 #define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos)
\r
15137 #define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos (12U)
\r
15138 #define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos)
\r
15140 #define SCU_GENERAL_MIRRSTS_RMX_Pos (13U)
\r
15141 #define SCU_GENERAL_MIRRSTS_RMX_Msk (0x00000001U << SCU_GENERAL_MIRRSTS_RMX_Pos)
\r
15143 /* SCU_GENERAL_RMACR = Retention Memory Access Control Register*/
\r
15144 #define SCU_GENERAL_RMACR_RDWR_Pos (0U)
\r
15145 #define SCU_GENERAL_RMACR_RDWR_Msk (0x00000001U << SCU_GENERAL_RMACR_RDWR_Pos)
\r
15147 #define SCU_GENERAL_RMACR_ADDR_Pos (16U)
\r
15148 #define SCU_GENERAL_RMACR_ADDR_Msk (0x0000000FU << SCU_GENERAL_RMACR_ADDR_Pos)
\r
15150 /* SCU_GENERAL_RMDATA = Retention Memory Access Data Register*/
\r
15151 #define SCU_GENERAL_RMDATA_DATA_Pos (0U)
\r
15152 #define SCU_GENERAL_RMDATA_DATA_Msk (0xFFFFFFFFU << SCU_GENERAL_RMDATA_DATA_Pos)
\r
15154 /* SCU_PARITY_PETE = Parity Error Trap Enable Register*/
\r
15155 #define SCU_PARITY_PETE_PETEPS_Pos (0U)
\r
15156 #define SCU_PARITY_PETE_PETEPS_Msk (0x00000001U << SCU_PARITY_PETE_PETEPS_Pos)
\r
15158 #define SCU_PARITY_PETE_PETEDS1_Pos (1U)
\r
15159 #define SCU_PARITY_PETE_PETEDS1_Msk (0x00000001U << SCU_PARITY_PETE_PETEDS1_Pos)
\r
15161 #define SCU_PARITY_PETE_PETEDS2_Pos (2U)
\r
15162 #define SCU_PARITY_PETE_PETEDS2_Msk (0x00000001U << SCU_PARITY_PETE_PETEDS2_Pos)
\r
15164 #define SCU_PARITY_PETE_PETEU0_Pos (8U)
\r
15165 #define SCU_PARITY_PETE_PETEU0_Msk (0x00000001U << SCU_PARITY_PETE_PETEU0_Pos)
\r
15167 #define SCU_PARITY_PETE_PETEU1_Pos (9U)
\r
15168 #define SCU_PARITY_PETE_PETEU1_Msk (0x00000001U << SCU_PARITY_PETE_PETEU1_Pos)
\r
15170 #define SCU_PARITY_PETE_PETEU2_Pos (10U)
\r
15171 #define SCU_PARITY_PETE_PETEU2_Msk (0x00000001U << SCU_PARITY_PETE_PETEU2_Pos)
\r
15173 #define SCU_PARITY_PETE_PETEMC_Pos (12U)
\r
15174 #define SCU_PARITY_PETE_PETEMC_Msk (0x00000001U << SCU_PARITY_PETE_PETEMC_Pos)
\r
15176 #define SCU_PARITY_PETE_PETEPPRF_Pos (13U)
\r
15177 #define SCU_PARITY_PETE_PETEPPRF_Msk (0x00000001U << SCU_PARITY_PETE_PETEPPRF_Pos)
\r
15179 #define SCU_PARITY_PETE_PETEUSB_Pos (16U)
\r
15180 #define SCU_PARITY_PETE_PETEUSB_Msk (0x00000001U << SCU_PARITY_PETE_PETEUSB_Pos)
\r
15182 #define SCU_PARITY_PETE_PETEETH0TX_Pos (17U)
\r
15183 #define SCU_PARITY_PETE_PETEETH0TX_Msk (0x00000001U << SCU_PARITY_PETE_PETEETH0TX_Pos)
\r
15185 #define SCU_PARITY_PETE_PETEETH0RX_Pos (18U)
\r
15186 #define SCU_PARITY_PETE_PETEETH0RX_Msk (0x00000001U << SCU_PARITY_PETE_PETEETH0RX_Pos)
\r
15188 #define SCU_PARITY_PETE_PETESD0_Pos (19U)
\r
15189 #define SCU_PARITY_PETE_PETESD0_Msk (0x00000001U << SCU_PARITY_PETE_PETESD0_Pos)
\r
15191 #define SCU_PARITY_PETE_PETESD1_Pos (20U)
\r
15192 #define SCU_PARITY_PETE_PETESD1_Msk (0x00000001U << SCU_PARITY_PETE_PETESD1_Pos)
\r
15194 /* SCU_PARITY_MCHKCON = Memory Checking Control Register*/
\r
15195 #define SCU_PARITY_MCHKCON_SELPS_Pos (0U)
\r
15196 #define SCU_PARITY_MCHKCON_SELPS_Msk (0x00000001U << SCU_PARITY_MCHKCON_SELPS_Pos)
\r
15198 #define SCU_PARITY_MCHKCON_SELDS1_Pos (1U)
\r
15199 #define SCU_PARITY_MCHKCON_SELDS1_Msk (0x00000001U << SCU_PARITY_MCHKCON_SELDS1_Pos)
\r
15201 #define SCU_PARITY_MCHKCON_SELDS2_Pos (2U)
\r
15202 #define SCU_PARITY_MCHKCON_SELDS2_Msk (0x00000001U << SCU_PARITY_MCHKCON_SELDS2_Pos)
\r
15204 #define SCU_PARITY_MCHKCON_USIC0DRA_Pos (8U)
\r
15205 #define SCU_PARITY_MCHKCON_USIC0DRA_Msk (0x00000001U << SCU_PARITY_MCHKCON_USIC0DRA_Pos)
\r
15207 #define SCU_PARITY_MCHKCON_USIC1DRA_Pos (9U)
\r
15208 #define SCU_PARITY_MCHKCON_USIC1DRA_Msk (0x00000001U << SCU_PARITY_MCHKCON_USIC1DRA_Pos)
\r
15210 #define SCU_PARITY_MCHKCON_USIC2DRA_Pos (10U)
\r
15211 #define SCU_PARITY_MCHKCON_USIC2DRA_Msk (0x00000001U << SCU_PARITY_MCHKCON_USIC2DRA_Pos)
\r
15213 #define SCU_PARITY_MCHKCON_MCANDRA_Pos (12U)
\r
15214 #define SCU_PARITY_MCHKCON_MCANDRA_Msk (0x00000001U << SCU_PARITY_MCHKCON_MCANDRA_Pos)
\r
15216 #define SCU_PARITY_MCHKCON_PPRFDRA_Pos (13U)
\r
15217 #define SCU_PARITY_MCHKCON_PPRFDRA_Msk (0x00000001U << SCU_PARITY_MCHKCON_PPRFDRA_Pos)
\r
15219 #define SCU_PARITY_MCHKCON_SELUSB_Pos (16U)
\r
15220 #define SCU_PARITY_MCHKCON_SELUSB_Msk (0x00000001U << SCU_PARITY_MCHKCON_SELUSB_Pos)
\r
15222 #define SCU_PARITY_MCHKCON_SELETH0TX_Pos (17U)
\r
15223 #define SCU_PARITY_MCHKCON_SELETH0TX_Msk (0x00000001U << SCU_PARITY_MCHKCON_SELETH0TX_Pos)
\r
15225 #define SCU_PARITY_MCHKCON_SELETH0RX_Pos (18U)
\r
15226 #define SCU_PARITY_MCHKCON_SELETH0RX_Msk (0x00000001U << SCU_PARITY_MCHKCON_SELETH0RX_Pos)
\r
15228 #define SCU_PARITY_MCHKCON_SELSD0_Pos (19U)
\r
15229 #define SCU_PARITY_MCHKCON_SELSD0_Msk (0x00000001U << SCU_PARITY_MCHKCON_SELSD0_Pos)
\r
15231 #define SCU_PARITY_MCHKCON_SELSD1_Pos (20U)
\r
15232 #define SCU_PARITY_MCHKCON_SELSD1_Msk (0x00000001U << SCU_PARITY_MCHKCON_SELSD1_Pos)
\r
15234 /* SCU_PARITY_PEEN = Parity Error Enable Register*/
\r
15235 #define SCU_PARITY_PEEN_PEENPS_Pos (0U)
\r
15236 #define SCU_PARITY_PEEN_PEENPS_Msk (0x00000001U << SCU_PARITY_PEEN_PEENPS_Pos)
\r
15238 #define SCU_PARITY_PEEN_PEENDS1_Pos (1U)
\r
15239 #define SCU_PARITY_PEEN_PEENDS1_Msk (0x00000001U << SCU_PARITY_PEEN_PEENDS1_Pos)
\r
15241 #define SCU_PARITY_PEEN_PEENDS2_Pos (2U)
\r
15242 #define SCU_PARITY_PEEN_PEENDS2_Msk (0x00000001U << SCU_PARITY_PEEN_PEENDS2_Pos)
\r
15244 #define SCU_PARITY_PEEN_PEENU0_Pos (8U)
\r
15245 #define SCU_PARITY_PEEN_PEENU0_Msk (0x00000001U << SCU_PARITY_PEEN_PEENU0_Pos)
\r
15247 #define SCU_PARITY_PEEN_PEENU1_Pos (9U)
\r
15248 #define SCU_PARITY_PEEN_PEENU1_Msk (0x00000001U << SCU_PARITY_PEEN_PEENU1_Pos)
\r
15250 #define SCU_PARITY_PEEN_PEENU2_Pos (10U)
\r
15251 #define SCU_PARITY_PEEN_PEENU2_Msk (0x00000001U << SCU_PARITY_PEEN_PEENU2_Pos)
\r
15253 #define SCU_PARITY_PEEN_PEENMC_Pos (12U)
\r
15254 #define SCU_PARITY_PEEN_PEENMC_Msk (0x00000001U << SCU_PARITY_PEEN_PEENMC_Pos)
\r
15256 #define SCU_PARITY_PEEN_PEENPPRF_Pos (13U)
\r
15257 #define SCU_PARITY_PEEN_PEENPPRF_Msk (0x00000001U << SCU_PARITY_PEEN_PEENPPRF_Pos)
\r
15259 #define SCU_PARITY_PEEN_PEENUSB_Pos (16U)
\r
15260 #define SCU_PARITY_PEEN_PEENUSB_Msk (0x00000001U << SCU_PARITY_PEEN_PEENUSB_Pos)
\r
15262 #define SCU_PARITY_PEEN_PEENETH0TX_Pos (17U)
\r
15263 #define SCU_PARITY_PEEN_PEENETH0TX_Msk (0x00000001U << SCU_PARITY_PEEN_PEENETH0TX_Pos)
\r
15265 #define SCU_PARITY_PEEN_PEENETH0RX_Pos (18U)
\r
15266 #define SCU_PARITY_PEEN_PEENETH0RX_Msk (0x00000001U << SCU_PARITY_PEEN_PEENETH0RX_Pos)
\r
15268 #define SCU_PARITY_PEEN_PEENSD0_Pos (19U)
\r
15269 #define SCU_PARITY_PEEN_PEENSD0_Msk (0x00000001U << SCU_PARITY_PEEN_PEENSD0_Pos)
\r
15271 #define SCU_PARITY_PEEN_PEENSD1_Pos (20U)
\r
15272 #define SCU_PARITY_PEEN_PEENSD1_Msk (0x00000001U << SCU_PARITY_PEEN_PEENSD1_Pos)
\r
15274 /* SCU_PARITY_PERSTEN = Parity Error Reset Enable Register*/
\r
15275 #define SCU_PARITY_PERSTEN_RSEN_Pos (0U)
\r
15276 #define SCU_PARITY_PERSTEN_RSEN_Msk (0x00000001U << SCU_PARITY_PERSTEN_RSEN_Pos)
\r
15278 /* SCU_PARITY_PEFLAG = Parity Error Flag Register*/
\r
15279 #define SCU_PARITY_PEFLAG_PEFPS_Pos (0U)
\r
15280 #define SCU_PARITY_PEFLAG_PEFPS_Msk (0x00000001U << SCU_PARITY_PEFLAG_PEFPS_Pos)
\r
15282 #define SCU_PARITY_PEFLAG_PEFDS1_Pos (1U)
\r
15283 #define SCU_PARITY_PEFLAG_PEFDS1_Msk (0x00000001U << SCU_PARITY_PEFLAG_PEFDS1_Pos)
\r
15285 #define SCU_PARITY_PEFLAG_PEFDS2_Pos (2U)
\r
15286 #define SCU_PARITY_PEFLAG_PEFDS2_Msk (0x00000001U << SCU_PARITY_PEFLAG_PEFDS2_Pos)
\r
15288 #define SCU_PARITY_PEFLAG_PEFU0_Pos (8U)
\r
15289 #define SCU_PARITY_PEFLAG_PEFU0_Msk (0x00000001U << SCU_PARITY_PEFLAG_PEFU0_Pos)
\r
15291 #define SCU_PARITY_PEFLAG_PEFU1_Pos (9U)
\r
15292 #define SCU_PARITY_PEFLAG_PEFU1_Msk (0x00000001U << SCU_PARITY_PEFLAG_PEFU1_Pos)
\r
15294 #define SCU_PARITY_PEFLAG_PEFU2_Pos (10U)
\r
15295 #define SCU_PARITY_PEFLAG_PEFU2_Msk (0x00000001U << SCU_PARITY_PEFLAG_PEFU2_Pos)
\r
15297 #define SCU_PARITY_PEFLAG_PEFMC_Pos (12U)
\r
15298 #define SCU_PARITY_PEFLAG_PEFMC_Msk (0x00000001U << SCU_PARITY_PEFLAG_PEFMC_Pos)
\r
15300 #define SCU_PARITY_PEFLAG_PEFPPRF_Pos (13U)
\r
15301 #define SCU_PARITY_PEFLAG_PEFPPRF_Msk (0x00000001U << SCU_PARITY_PEFLAG_PEFPPRF_Pos)
\r
15303 #define SCU_PARITY_PEFLAG_PEUSB_Pos (16U)
\r
15304 #define SCU_PARITY_PEFLAG_PEUSB_Msk (0x00000001U << SCU_PARITY_PEFLAG_PEUSB_Pos)
\r
15306 #define SCU_PARITY_PEFLAG_PEETH0TX_Pos (17U)
\r
15307 #define SCU_PARITY_PEFLAG_PEETH0TX_Msk (0x00000001U << SCU_PARITY_PEFLAG_PEETH0TX_Pos)
\r
15309 #define SCU_PARITY_PEFLAG_PEETH0RX_Pos (18U)
\r
15310 #define SCU_PARITY_PEFLAG_PEETH0RX_Msk (0x00000001U << SCU_PARITY_PEFLAG_PEETH0RX_Pos)
\r
15312 #define SCU_PARITY_PEFLAG_PESD0_Pos (19U)
\r
15313 #define SCU_PARITY_PEFLAG_PESD0_Msk (0x00000001U << SCU_PARITY_PEFLAG_PESD0_Pos)
\r
15315 #define SCU_PARITY_PEFLAG_PESD1_Pos (20U)
\r
15316 #define SCU_PARITY_PEFLAG_PESD1_Msk (0x00000001U << SCU_PARITY_PEFLAG_PESD1_Pos)
\r
15318 /* SCU_PARITY_PMTPR = Parity Memory Test Pattern Register*/
\r
15319 #define SCU_PARITY_PMTPR_PRD_Pos (8U)
\r
15320 #define SCU_PARITY_PMTPR_PRD_Msk (0x000000FFU << SCU_PARITY_PMTPR_PRD_Pos)
\r
15322 #define SCU_PARITY_PMTPR_PWR_Pos (0U)
\r
15323 #define SCU_PARITY_PMTPR_PWR_Msk (0x000000FFU << SCU_PARITY_PMTPR_PWR_Pos)
\r
15325 /* SCU_PARITY_PMTSR = Parity Memory Test Select Register*/
\r
15326 #define SCU_PARITY_PMTSR_MTENPS_Pos (0U)
\r
15327 #define SCU_PARITY_PMTSR_MTENPS_Msk (0x00000001U << SCU_PARITY_PMTSR_MTENPS_Pos)
\r
15329 #define SCU_PARITY_PMTSR_MTENDS1_Pos (1U)
\r
15330 #define SCU_PARITY_PMTSR_MTENDS1_Msk (0x00000001U << SCU_PARITY_PMTSR_MTENDS1_Pos)
\r
15332 #define SCU_PARITY_PMTSR_MTENDS2_Pos (2U)
\r
15333 #define SCU_PARITY_PMTSR_MTENDS2_Msk (0x00000001U << SCU_PARITY_PMTSR_MTENDS2_Pos)
\r
15335 #define SCU_PARITY_PMTSR_MTEU0_Pos (8U)
\r
15336 #define SCU_PARITY_PMTSR_MTEU0_Msk (0x00000001U << SCU_PARITY_PMTSR_MTEU0_Pos)
\r
15338 #define SCU_PARITY_PMTSR_MTEU1_Pos (9U)
\r
15339 #define SCU_PARITY_PMTSR_MTEU1_Msk (0x00000001U << SCU_PARITY_PMTSR_MTEU1_Pos)
\r
15341 #define SCU_PARITY_PMTSR_MTEU2_Pos (10U)
\r
15342 #define SCU_PARITY_PMTSR_MTEU2_Msk (0x00000001U << SCU_PARITY_PMTSR_MTEU2_Pos)
\r
15344 #define SCU_PARITY_PMTSR_MTEMC_Pos (12U)
\r
15345 #define SCU_PARITY_PMTSR_MTEMC_Msk (0x00000001U << SCU_PARITY_PMTSR_MTEMC_Pos)
\r
15347 #define SCU_PARITY_PMTSR_MTEPPRF_Pos (13U)
\r
15348 #define SCU_PARITY_PMTSR_MTEPPRF_Msk (0x00000001U << SCU_PARITY_PMTSR_MTEPPRF_Pos)
\r
15350 #define SCU_PARITY_PMTSR_MTUSB_Pos (16U)
\r
15351 #define SCU_PARITY_PMTSR_MTUSB_Msk (0x00000001U << SCU_PARITY_PMTSR_MTUSB_Pos)
\r
15353 #define SCU_PARITY_PMTSR_MTETH0TX_Pos (17U)
\r
15354 #define SCU_PARITY_PMTSR_MTETH0TX_Msk (0x00000001U << SCU_PARITY_PMTSR_MTETH0TX_Pos)
\r
15356 #define SCU_PARITY_PMTSR_MTETH0RX_Pos (18U)
\r
15357 #define SCU_PARITY_PMTSR_MTETH0RX_Msk (0x00000001U << SCU_PARITY_PMTSR_MTETH0RX_Pos)
\r
15359 #define SCU_PARITY_PMTSR_MTSD0_Pos (19U)
\r
15360 #define SCU_PARITY_PMTSR_MTSD0_Msk (0x00000001U << SCU_PARITY_PMTSR_MTSD0_Pos)
\r
15362 #define SCU_PARITY_PMTSR_MTSD1_Pos (20U)
\r
15363 #define SCU_PARITY_PMTSR_MTSD1_Msk (0x00000001U << SCU_PARITY_PMTSR_MTSD1_Pos)
\r
15365 /* SCU_INTERRUPT_SRSTAT = SCU Service Request Status*/
\r
15366 #define SCU_INTERRUPT_SRSTAT_PRWARN_Pos (0U)
\r
15367 #define SCU_INTERRUPT_SRSTAT_PRWARN_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_PRWARN_Pos)
\r
15369 #define SCU_INTERRUPT_SRSTAT_PI_Pos (1U)
\r
15370 #define SCU_INTERRUPT_SRSTAT_PI_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_PI_Pos)
\r
15372 #define SCU_INTERRUPT_SRSTAT_AI_Pos (2U)
\r
15373 #define SCU_INTERRUPT_SRSTAT_AI_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_AI_Pos)
\r
15375 #define SCU_INTERRUPT_SRSTAT_DLROVR_Pos (3U)
\r
15376 #define SCU_INTERRUPT_SRSTAT_DLROVR_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_DLROVR_Pos)
\r
15378 #define SCU_INTERRUPT_SRSTAT_HDSTAT_Pos (16U)
\r
15379 #define SCU_INTERRUPT_SRSTAT_HDSTAT_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_HDSTAT_Pos)
\r
15381 #define SCU_INTERRUPT_SRSTAT_HDCLR_Pos (17U)
\r
15382 #define SCU_INTERRUPT_SRSTAT_HDCLR_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_HDCLR_Pos)
\r
15384 #define SCU_INTERRUPT_SRSTAT_HDSET_Pos (18U)
\r
15385 #define SCU_INTERRUPT_SRSTAT_HDSET_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_HDSET_Pos)
\r
15387 #define SCU_INTERRUPT_SRSTAT_HDCR_Pos (19U)
\r
15388 #define SCU_INTERRUPT_SRSTAT_HDCR_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_HDCR_Pos)
\r
15390 #define SCU_INTERRUPT_SRSTAT_OSCSITRIM_Pos (20U)
\r
15391 #define SCU_INTERRUPT_SRSTAT_OSCSITRIM_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_OSCSITRIM_Pos)
\r
15393 #define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos (21U)
\r
15394 #define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos)
\r
15396 #define SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos (22U)
\r
15397 #define SCU_INTERRUPT_SRSTAT_OSCULSTAT_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos)
\r
15399 #define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos (23U)
\r
15400 #define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos)
\r
15402 #define SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos (24U)
\r
15403 #define SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos)
\r
15405 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos (25U)
\r
15406 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos)
\r
15408 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos (26U)
\r
15409 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos)
\r
15411 #define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos (27U)
\r
15412 #define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos)
\r
15414 #define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos (28U)
\r
15415 #define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos)
\r
15417 #define SCU_INTERRUPT_SRSTAT_RMX_Pos (29U)
\r
15418 #define SCU_INTERRUPT_SRSTAT_RMX_Msk (0x00000001U << SCU_INTERRUPT_SRSTAT_RMX_Pos)
\r
15420 /* SCU_INTERRUPT_SRRAW = SCU Raw Service Request Status*/
\r
15421 #define SCU_INTERRUPT_SRRAW_PRWARN_Pos (0U)
\r
15422 #define SCU_INTERRUPT_SRRAW_PRWARN_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_PRWARN_Pos)
\r
15424 #define SCU_INTERRUPT_SRRAW_PI_Pos (1U)
\r
15425 #define SCU_INTERRUPT_SRRAW_PI_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_PI_Pos)
\r
15427 #define SCU_INTERRUPT_SRRAW_AI_Pos (2U)
\r
15428 #define SCU_INTERRUPT_SRRAW_AI_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_AI_Pos)
\r
15430 #define SCU_INTERRUPT_SRRAW_DLROVR_Pos (3U)
\r
15431 #define SCU_INTERRUPT_SRRAW_DLROVR_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_DLROVR_Pos)
\r
15433 #define SCU_INTERRUPT_SRRAW_HDSTAT_Pos (16U)
\r
15434 #define SCU_INTERRUPT_SRRAW_HDSTAT_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_HDSTAT_Pos)
\r
15436 #define SCU_INTERRUPT_SRRAW_HDCLR_Pos (17U)
\r
15437 #define SCU_INTERRUPT_SRRAW_HDCLR_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_HDCLR_Pos)
\r
15439 #define SCU_INTERRUPT_SRRAW_HDSET_Pos (18U)
\r
15440 #define SCU_INTERRUPT_SRRAW_HDSET_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_HDSET_Pos)
\r
15442 #define SCU_INTERRUPT_SRRAW_HDCR_Pos (19U)
\r
15443 #define SCU_INTERRUPT_SRRAW_HDCR_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_HDCR_Pos)
\r
15445 #define SCU_INTERRUPT_SRRAW_OSCSITRIM_Pos (20U)
\r
15446 #define SCU_INTERRUPT_SRRAW_OSCSITRIM_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_OSCSITRIM_Pos)
\r
15448 #define SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos (21U)
\r
15449 #define SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos)
\r
15451 #define SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos (22U)
\r
15452 #define SCU_INTERRUPT_SRRAW_OSCULSTAT_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos)
\r
15454 #define SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos (23U)
\r
15455 #define SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos)
\r
15457 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos (24U)
\r
15458 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_RTC_CTR_Pos)
\r
15460 #define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos (25U)
\r
15461 #define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos)
\r
15463 #define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos (26U)
\r
15464 #define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos)
\r
15466 #define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos (27U)
\r
15467 #define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos)
\r
15469 #define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos (28U)
\r
15470 #define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos)
\r
15472 #define SCU_INTERRUPT_SRRAW_RMX_Pos (29U)
\r
15473 #define SCU_INTERRUPT_SRRAW_RMX_Msk (0x00000001U << SCU_INTERRUPT_SRRAW_RMX_Pos)
\r
15475 /* SCU_INTERRUPT_SRMSK = SCU Service Request Mask*/
\r
15476 #define SCU_INTERRUPT_SRMSK_PRWARN_Pos (0U)
\r
15477 #define SCU_INTERRUPT_SRMSK_PRWARN_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_PRWARN_Pos)
\r
15479 #define SCU_INTERRUPT_SRMSK_PI_Pos (1U)
\r
15480 #define SCU_INTERRUPT_SRMSK_PI_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_PI_Pos)
\r
15482 #define SCU_INTERRUPT_SRMSK_AI_Pos (2U)
\r
15483 #define SCU_INTERRUPT_SRMSK_AI_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_AI_Pos)
\r
15485 #define SCU_INTERRUPT_SRMSK_DLROVR_Pos (3U)
\r
15486 #define SCU_INTERRUPT_SRMSK_DLROVR_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_DLROVR_Pos)
\r
15488 #define SCU_INTERRUPT_SRMSK_HDSTAT_Pos (16U)
\r
15489 #define SCU_INTERRUPT_SRMSK_HDSTAT_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_HDSTAT_Pos)
\r
15491 #define SCU_INTERRUPT_SRMSK_HDCLR_Pos (17U)
\r
15492 #define SCU_INTERRUPT_SRMSK_HDCLR_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_HDCLR_Pos)
\r
15494 #define SCU_INTERRUPT_SRMSK_HDSET_Pos (18U)
\r
15495 #define SCU_INTERRUPT_SRMSK_HDSET_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_HDSET_Pos)
\r
15497 #define SCU_INTERRUPT_SRMSK_HDCR_Pos (19U)
\r
15498 #define SCU_INTERRUPT_SRMSK_HDCR_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_HDCR_Pos)
\r
15500 #define SCU_INTERRUPT_SRMSK_OSCSITRIM_Pos (20U)
\r
15501 #define SCU_INTERRUPT_SRMSK_OSCSITRIM_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_OSCSITRIM_Pos)
\r
15503 #define SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos (21U)
\r
15504 #define SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos)
\r
15506 #define SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos (22U)
\r
15507 #define SCU_INTERRUPT_SRMSK_OSCULSTAT_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos)
\r
15509 #define SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos (23U)
\r
15510 #define SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos)
\r
15512 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos (24U)
\r
15513 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_RTC_CTR_Pos)
\r
15515 #define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos (25U)
\r
15516 #define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos)
\r
15518 #define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos (26U)
\r
15519 #define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos)
\r
15521 #define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos (27U)
\r
15522 #define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos)
\r
15524 #define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos (28U)
\r
15525 #define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos)
\r
15527 #define SCU_INTERRUPT_SRMSK_RMX_Pos (29U)
\r
15528 #define SCU_INTERRUPT_SRMSK_RMX_Msk (0x00000001U << SCU_INTERRUPT_SRMSK_RMX_Pos)
\r
15530 /* SCU_INTERRUPT_SRCLR = SCU Service Request Clear*/
\r
15531 #define SCU_INTERRUPT_SRCLR_PRWARN_Pos (0U)
\r
15532 #define SCU_INTERRUPT_SRCLR_PRWARN_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_PRWARN_Pos)
\r
15534 #define SCU_INTERRUPT_SRCLR_PI_Pos (1U)
\r
15535 #define SCU_INTERRUPT_SRCLR_PI_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_PI_Pos)
\r
15537 #define SCU_INTERRUPT_SRCLR_AI_Pos (2U)
\r
15538 #define SCU_INTERRUPT_SRCLR_AI_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_AI_Pos)
\r
15540 #define SCU_INTERRUPT_SRCLR_DLROVR_Pos (3U)
\r
15541 #define SCU_INTERRUPT_SRCLR_DLROVR_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_DLROVR_Pos)
\r
15543 #define SCU_INTERRUPT_SRCLR_HDSTAT_Pos (16U)
\r
15544 #define SCU_INTERRUPT_SRCLR_HDSTAT_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_HDSTAT_Pos)
\r
15546 #define SCU_INTERRUPT_SRCLR_HDCLR_Pos (17U)
\r
15547 #define SCU_INTERRUPT_SRCLR_HDCLR_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_HDCLR_Pos)
\r
15549 #define SCU_INTERRUPT_SRCLR_HDSET_Pos (18U)
\r
15550 #define SCU_INTERRUPT_SRCLR_HDSET_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_HDSET_Pos)
\r
15552 #define SCU_INTERRUPT_SRCLR_HDCR_Pos (19U)
\r
15553 #define SCU_INTERRUPT_SRCLR_HDCR_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_HDCR_Pos)
\r
15555 #define SCU_INTERRUPT_SRCLR_OSCSITRIM_Pos (20U)
\r
15556 #define SCU_INTERRUPT_SRCLR_OSCSITRIM_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_OSCSITRIM_Pos)
\r
15558 #define SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos (21U)
\r
15559 #define SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos)
\r
15561 #define SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos (22U)
\r
15562 #define SCU_INTERRUPT_SRCLR_OSCULSTAT_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos)
\r
15564 #define SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos (23U)
\r
15565 #define SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos)
\r
15567 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos (24U)
\r
15568 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_RTC_CTR_Pos)
\r
15570 #define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos (25U)
\r
15571 #define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos)
\r
15573 #define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos (26U)
\r
15574 #define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos)
\r
15576 #define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos (27U)
\r
15577 #define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos)
\r
15579 #define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos (28U)
\r
15580 #define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos)
\r
15582 #define SCU_INTERRUPT_SRCLR_RMX_Pos (29U)
\r
15583 #define SCU_INTERRUPT_SRCLR_RMX_Msk (0x00000001U << SCU_INTERRUPT_SRCLR_RMX_Pos)
\r
15585 /* SCU_INTERRUPT_SRSET = SCU Service Request Set*/
\r
15586 #define SCU_INTERRUPT_SRSET_PRWARN_Pos (0U)
\r
15587 #define SCU_INTERRUPT_SRSET_PRWARN_Msk (0x00000001U << SCU_INTERRUPT_SRSET_PRWARN_Pos)
\r
15589 #define SCU_INTERRUPT_SRSET_PI_Pos (1U)
\r
15590 #define SCU_INTERRUPT_SRSET_PI_Msk (0x00000001U << SCU_INTERRUPT_SRSET_PI_Pos)
\r
15592 #define SCU_INTERRUPT_SRSET_AI_Pos (2U)
\r
15593 #define SCU_INTERRUPT_SRSET_AI_Msk (0x00000001U << SCU_INTERRUPT_SRSET_AI_Pos)
\r
15595 #define SCU_INTERRUPT_SRSET_DLROVR_Pos (3U)
\r
15596 #define SCU_INTERRUPT_SRSET_DLROVR_Msk (0x00000001U << SCU_INTERRUPT_SRSET_DLROVR_Pos)
\r
15598 #define SCU_INTERRUPT_SRSET_HDSTAT_Pos (16U)
\r
15599 #define SCU_INTERRUPT_SRSET_HDSTAT_Msk (0x00000001U << SCU_INTERRUPT_SRSET_HDSTAT_Pos)
\r
15601 #define SCU_INTERRUPT_SRSET_HDCRCLR_Pos (17U)
\r
15602 #define SCU_INTERRUPT_SRSET_HDCRCLR_Msk (0x00000001U << SCU_INTERRUPT_SRSET_HDCRCLR_Pos)
\r
15604 #define SCU_INTERRUPT_SRSET_HDCRSET_Pos (18U)
\r
15605 #define SCU_INTERRUPT_SRSET_HDCRSET_Msk (0x00000001U << SCU_INTERRUPT_SRSET_HDCRSET_Pos)
\r
15607 #define SCU_INTERRUPT_SRSET_HDCR_Pos (19U)
\r
15608 #define SCU_INTERRUPT_SRSET_HDCR_Msk (0x00000001U << SCU_INTERRUPT_SRSET_HDCR_Pos)
\r
15610 #define SCU_INTERRUPT_SRSET_OSCSITRIM_Pos (20U)
\r
15611 #define SCU_INTERRUPT_SRSET_OSCSITRIM_Msk (0x00000001U << SCU_INTERRUPT_SRSET_OSCSITRIM_Pos)
\r
15613 #define SCU_INTERRUPT_SRSET_OSCSICTRL_Pos (21U)
\r
15614 #define SCU_INTERRUPT_SRSET_OSCSICTRL_Msk (0x00000001U << SCU_INTERRUPT_SRSET_OSCSICTRL_Pos)
\r
15616 #define SCU_INTERRUPT_SRSET_OSCULSTAT_Pos (22U)
\r
15617 #define SCU_INTERRUPT_SRSET_OSCULSTAT_Msk (0x00000001U << SCU_INTERRUPT_SRSET_OSCULSTAT_Pos)
\r
15619 #define SCU_INTERRUPT_SRSET_OSCULCTRL_Pos (23U)
\r
15620 #define SCU_INTERRUPT_SRSET_OSCULCTRL_Msk (0x00000001U << SCU_INTERRUPT_SRSET_OSCULCTRL_Pos)
\r
15622 #define SCU_INTERRUPT_SRSET_RTC_CTR_Pos (24U)
\r
15623 #define SCU_INTERRUPT_SRSET_RTC_CTR_Msk (0x00000001U << SCU_INTERRUPT_SRSET_RTC_CTR_Pos)
\r
15625 #define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos (25U)
\r
15626 #define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk (0x00000001U << SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos)
\r
15628 #define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos (26U)
\r
15629 #define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk (0x00000001U << SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos)
\r
15631 #define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos (27U)
\r
15632 #define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk (0x00000001U << SCU_INTERRUPT_SRSET_RTC_TIM0_Pos)
\r
15634 #define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos (28U)
\r
15635 #define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk (0x00000001U << SCU_INTERRUPT_SRSET_RTC_TIM1_Pos)
\r
15637 #define SCU_INTERRUPT_SRSET_RMX_Pos (29U)
\r
15638 #define SCU_INTERRUPT_SRSET_RMX_Msk (0x00000001U << SCU_INTERRUPT_SRSET_RMX_Pos)
\r
15640 /* SCU_INTERRUPT_NMIREQEN = SCU Service Request Mask*/
\r
15641 #define SCU_INTERRUPT_NMIREQEN_PRWARN_Pos (0U)
\r
15642 #define SCU_INTERRUPT_NMIREQEN_PRWARN_Msk (0x00000001U << SCU_INTERRUPT_NMIREQEN_PRWARN_Pos)
\r
15644 #define SCU_INTERRUPT_NMIREQEN_PI_Pos (1U)
\r
15645 #define SCU_INTERRUPT_NMIREQEN_PI_Msk (0x00000001U << SCU_INTERRUPT_NMIREQEN_PI_Pos)
\r
15647 #define SCU_INTERRUPT_NMIREQEN_AI_Pos (2U)
\r
15648 #define SCU_INTERRUPT_NMIREQEN_AI_Msk (0x00000001U << SCU_INTERRUPT_NMIREQEN_AI_Pos)
\r
15650 #define SCU_INTERRUPT_NMIREQEN_ERU00_Pos (16U)
\r
15651 #define SCU_INTERRUPT_NMIREQEN_ERU00_Msk (0x00000001U << SCU_INTERRUPT_NMIREQEN_ERU00_Pos)
\r
15653 #define SCU_INTERRUPT_NMIREQEN_ERU01_Pos (17U)
\r
15654 #define SCU_INTERRUPT_NMIREQEN_ERU01_Msk (0x00000001U << SCU_INTERRUPT_NMIREQEN_ERU01_Pos)
\r
15656 #define SCU_INTERRUPT_NMIREQEN_ERU02_Pos (18U)
\r
15657 #define SCU_INTERRUPT_NMIREQEN_ERU02_Msk (0x00000001U << SCU_INTERRUPT_NMIREQEN_ERU02_Pos)
\r
15659 #define SCU_INTERRUPT_NMIREQEN_ERU03_Pos (19U)
\r
15660 #define SCU_INTERRUPT_NMIREQEN_ERU03_Msk (0x00000001U << SCU_INTERRUPT_NMIREQEN_ERU03_Pos)
\r
15662 /* SCU_TRAP_TRAPSTAT = Trap Status Register*/
\r
15663 #define SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos (0U)
\r
15664 #define SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk (0x00000001U << SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos)
\r
15666 #define SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos (2U)
\r
15667 #define SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk (0x00000001U << SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos)
\r
15669 #define SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos (3U)
\r
15670 #define SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk (0x00000001U << SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos)
\r
15672 #define SCU_TRAP_TRAPSTAT_PET_Pos (4U)
\r
15673 #define SCU_TRAP_TRAPSTAT_PET_Msk (0x00000001U << SCU_TRAP_TRAPSTAT_PET_Pos)
\r
15675 #define SCU_TRAP_TRAPSTAT_BRWNT_Pos (5U)
\r
15676 #define SCU_TRAP_TRAPSTAT_BRWNT_Msk (0x00000001U << SCU_TRAP_TRAPSTAT_BRWNT_Pos)
\r
15678 #define SCU_TRAP_TRAPSTAT_ULPWDGT_Pos (6U)
\r
15679 #define SCU_TRAP_TRAPSTAT_ULPWDGT_Msk (0x00000001U << SCU_TRAP_TRAPSTAT_ULPWDGT_Pos)
\r
15681 #define SCU_TRAP_TRAPSTAT_BWERR0T_Pos (7U)
\r
15682 #define SCU_TRAP_TRAPSTAT_BWERR0T_Msk (0x00000001U << SCU_TRAP_TRAPSTAT_BWERR0T_Pos)
\r
15684 #define SCU_TRAP_TRAPSTAT_BWERR1T_Pos (8U)
\r
15685 #define SCU_TRAP_TRAPSTAT_BWERR1T_Msk (0x00000001U << SCU_TRAP_TRAPSTAT_BWERR1T_Pos)
\r
15687 /* SCU_TRAP_TRAPRAW = Trap Raw Status Register*/
\r
15688 #define SCU_TRAP_TRAPRAW_SOSCWDGT_Pos (0U)
\r
15689 #define SCU_TRAP_TRAPRAW_SOSCWDGT_Msk (0x00000001U << SCU_TRAP_TRAPRAW_SOSCWDGT_Pos)
\r
15691 #define SCU_TRAP_TRAPRAW_SVCOLCKT_Pos (2U)
\r
15692 #define SCU_TRAP_TRAPRAW_SVCOLCKT_Msk (0x00000001U << SCU_TRAP_TRAPRAW_SVCOLCKT_Pos)
\r
15694 #define SCU_TRAP_TRAPRAW_UVCOLCKT_Pos (3U)
\r
15695 #define SCU_TRAP_TRAPRAW_UVCOLCKT_Msk (0x00000001U << SCU_TRAP_TRAPRAW_UVCOLCKT_Pos)
\r
15697 #define SCU_TRAP_TRAPRAW_PET_Pos (4U)
\r
15698 #define SCU_TRAP_TRAPRAW_PET_Msk (0x00000001U << SCU_TRAP_TRAPRAW_PET_Pos)
\r
15700 #define SCU_TRAP_TRAPRAW_BRWNT_Pos (5U)
\r
15701 #define SCU_TRAP_TRAPRAW_BRWNT_Msk (0x00000001U << SCU_TRAP_TRAPRAW_BRWNT_Pos)
\r
15703 #define SCU_TRAP_TRAPRAW_ULPWDGT_Pos (6U)
\r
15704 #define SCU_TRAP_TRAPRAW_ULPWDGT_Msk (0x00000001U << SCU_TRAP_TRAPRAW_ULPWDGT_Pos)
\r
15706 #define SCU_TRAP_TRAPRAW_BWERR0T_Pos (7U)
\r
15707 #define SCU_TRAP_TRAPRAW_BWERR0T_Msk (0x00000001U << SCU_TRAP_TRAPRAW_BWERR0T_Pos)
\r
15709 #define SCU_TRAP_TRAPRAW_BWERR1T_Pos (8U)
\r
15710 #define SCU_TRAP_TRAPRAW_BWERR1T_Msk (0x00000001U << SCU_TRAP_TRAPRAW_BWERR1T_Pos)
\r
15712 /* SCU_TRAP_TRAPDIS = Trap Disable Register*/
\r
15713 #define SCU_TRAP_TRAPDIS_SOSCWDGT_Pos (0U)
\r
15714 #define SCU_TRAP_TRAPDIS_SOSCWDGT_Msk (0x00000001U << SCU_TRAP_TRAPDIS_SOSCWDGT_Pos)
\r
15716 #define SCU_TRAP_TRAPDIS_SVCOLCKT_Pos (2U)
\r
15717 #define SCU_TRAP_TRAPDIS_SVCOLCKT_Msk (0x00000001U << SCU_TRAP_TRAPDIS_SVCOLCKT_Pos)
\r
15719 #define SCU_TRAP_TRAPDIS_UVCOLCKT_Pos (3U)
\r
15720 #define SCU_TRAP_TRAPDIS_UVCOLCKT_Msk (0x00000001U << SCU_TRAP_TRAPDIS_UVCOLCKT_Pos)
\r
15722 #define SCU_TRAP_TRAPDIS_PET_Pos (4U)
\r
15723 #define SCU_TRAP_TRAPDIS_PET_Msk (0x00000001U << SCU_TRAP_TRAPDIS_PET_Pos)
\r
15725 #define SCU_TRAP_TRAPDIS_BRWNT_Pos (5U)
\r
15726 #define SCU_TRAP_TRAPDIS_BRWNT_Msk (0x00000001U << SCU_TRAP_TRAPDIS_BRWNT_Pos)
\r
15728 #define SCU_TRAP_TRAPDIS_ULPWDGT_Pos (6U)
\r
15729 #define SCU_TRAP_TRAPDIS_ULPWDGT_Msk (0x00000001U << SCU_TRAP_TRAPDIS_ULPWDGT_Pos)
\r
15731 #define SCU_TRAP_TRAPDIS_BWERR0T_Pos (7U)
\r
15732 #define SCU_TRAP_TRAPDIS_BWERR0T_Msk (0x00000001U << SCU_TRAP_TRAPDIS_BWERR0T_Pos)
\r
15734 #define SCU_TRAP_TRAPDIS_BWERR1T_Pos (8U)
\r
15735 #define SCU_TRAP_TRAPDIS_BWERR1T_Msk (0x00000001U << SCU_TRAP_TRAPDIS_BWERR1T_Pos)
\r
15737 /* SCU_TRAP_TRAPCLR = Trap Clear Register*/
\r
15738 #define SCU_TRAP_TRAPCLR_SOSCWDGT_Pos (0U)
\r
15739 #define SCU_TRAP_TRAPCLR_SOSCWDGT_Msk (0x00000001U << SCU_TRAP_TRAPCLR_SOSCWDGT_Pos)
\r
15741 #define SCU_TRAP_TRAPCLR_SVCOLCKT_Pos (2U)
\r
15742 #define SCU_TRAP_TRAPCLR_SVCOLCKT_Msk (0x00000001U << SCU_TRAP_TRAPCLR_SVCOLCKT_Pos)
\r
15744 #define SCU_TRAP_TRAPCLR_UVCOLCKT_Pos (3U)
\r
15745 #define SCU_TRAP_TRAPCLR_UVCOLCKT_Msk (0x00000001U << SCU_TRAP_TRAPCLR_UVCOLCKT_Pos)
\r
15747 #define SCU_TRAP_TRAPCLR_PET_Pos (4U)
\r
15748 #define SCU_TRAP_TRAPCLR_PET_Msk (0x00000001U << SCU_TRAP_TRAPCLR_PET_Pos)
\r
15750 #define SCU_TRAP_TRAPCLR_BRWNT_Pos (5U)
\r
15751 #define SCU_TRAP_TRAPCLR_BRWNT_Msk (0x00000001U << SCU_TRAP_TRAPCLR_BRWNT_Pos)
\r
15753 #define SCU_TRAP_TRAPCLR_ULPWDGT_Pos (6U)
\r
15754 #define SCU_TRAP_TRAPCLR_ULPWDGT_Msk (0x00000001U << SCU_TRAP_TRAPCLR_ULPWDGT_Pos)
\r
15756 #define SCU_TRAP_TRAPCLR_BWERR0T_Pos (7U)
\r
15757 #define SCU_TRAP_TRAPCLR_BWERR0T_Msk (0x00000001U << SCU_TRAP_TRAPCLR_BWERR0T_Pos)
\r
15759 #define SCU_TRAP_TRAPCLR_BWERR1T_Pos (8U)
\r
15760 #define SCU_TRAP_TRAPCLR_BWERR1T_Msk (0x00000001U << SCU_TRAP_TRAPCLR_BWERR1T_Pos)
\r
15762 /* SCU_TRAP_TRAPSET = Trap Set Register*/
\r
15763 #define SCU_TRAP_TRAPSET_SOSCWDGT_Pos (0U)
\r
15764 #define SCU_TRAP_TRAPSET_SOSCWDGT_Msk (0x00000001U << SCU_TRAP_TRAPSET_SOSCWDGT_Pos)
\r
15766 #define SCU_TRAP_TRAPSET_SVCOLCKT_Pos (2U)
\r
15767 #define SCU_TRAP_TRAPSET_SVCOLCKT_Msk (0x00000001U << SCU_TRAP_TRAPSET_SVCOLCKT_Pos)
\r
15769 #define SCU_TRAP_TRAPSET_UVCOLCKT_Pos (3U)
\r
15770 #define SCU_TRAP_TRAPSET_UVCOLCKT_Msk (0x00000001U << SCU_TRAP_TRAPSET_UVCOLCKT_Pos)
\r
15772 #define SCU_TRAP_TRAPSET_PET_Pos (4U)
\r
15773 #define SCU_TRAP_TRAPSET_PET_Msk (0x00000001U << SCU_TRAP_TRAPSET_PET_Pos)
\r
15775 #define SCU_TRAP_TRAPSET_BRWNT_Pos (5U)
\r
15776 #define SCU_TRAP_TRAPSET_BRWNT_Msk (0x00000001U << SCU_TRAP_TRAPSET_BRWNT_Pos)
\r
15778 #define SCU_TRAP_TRAPSET_ULPWDT_Pos (6U)
\r
15779 #define SCU_TRAP_TRAPSET_ULPWDT_Msk (0x00000001U << SCU_TRAP_TRAPSET_ULPWDT_Pos)
\r
15781 #define SCU_TRAP_TRAPSET_BWERR0T_Pos (7U)
\r
15782 #define SCU_TRAP_TRAPSET_BWERR0T_Msk (0x00000001U << SCU_TRAP_TRAPSET_BWERR0T_Pos)
\r
15784 #define SCU_TRAP_TRAPSET_BWERR1T_Pos (8U)
\r
15785 #define SCU_TRAP_TRAPSET_BWERR1T_Msk (0x00000001U << SCU_TRAP_TRAPSET_BWERR1T_Pos)
\r
15789 /*** SCU Bit Fileds *******************/
\r
15790 /***************************************************************************/
\r
15793 /* SCU_HIBERNATE_HDSTAT = Hibernate Domain Control & Status Register*/
\r
15794 #define SCU_HIBERNATE_HDSTAT_EPEV_Pos (0U)
\r
15795 #define SCU_HIBERNATE_HDSTAT_EPEV_Msk (0x00000001U << SCU_HIBERNATE_HDSTAT_EPEV_Pos)
\r
15797 #define SCU_HIBERNATE_HDSTAT_ENEV_Pos (1U)
\r
15798 #define SCU_HIBERNATE_HDSTAT_ENEV_Msk (0x00000001U << SCU_HIBERNATE_HDSTAT_ENEV_Pos)
\r
15800 #define SCU_HIBERNATE_HDSTAT_RTCEV_Pos (2U)
\r
15801 #define SCU_HIBERNATE_HDSTAT_RTCEV_Msk (0x00000001U << SCU_HIBERNATE_HDSTAT_RTCEV_Pos)
\r
15803 #define SCU_HIBERNATE_HDSTAT_ULPWDG_Pos (3U)
\r
15804 #define SCU_HIBERNATE_HDSTAT_ULPWDG_Msk (0x00000001U << SCU_HIBERNATE_HDSTAT_ULPWDG_Pos)
\r
15806 #define SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos (4U)
\r
15807 #define SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk (0x00000001U << SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos)
\r
15809 /* SCU_HIBERNATE_HDCLR = Hibernate Domain Status Clear Register*/
\r
15810 #define SCU_HIBERNATE_HDCLR_EPEV_Pos (0U)
\r
15811 #define SCU_HIBERNATE_HDCLR_EPEV_Msk (0x00000001U << SCU_HIBERNATE_HDCLR_EPEV_Pos)
\r
15813 #define SCU_HIBERNATE_HDCLR_ENEV_Pos (1U)
\r
15814 #define SCU_HIBERNATE_HDCLR_ENEV_Msk (0x00000001U << SCU_HIBERNATE_HDCLR_ENEV_Pos)
\r
15816 #define SCU_HIBERNATE_HDCLR_RTCEV_Pos (2U)
\r
15817 #define SCU_HIBERNATE_HDCLR_RTCEV_Msk (0x00000001U << SCU_HIBERNATE_HDCLR_RTCEV_Pos)
\r
15819 #define SCU_HIBERNATE_HDCLR_ULPWDG_Pos (3U)
\r
15820 #define SCU_HIBERNATE_HDCLR_ULPWDG_Msk (0x00000001U << SCU_HIBERNATE_HDCLR_ULPWDG_Pos)
\r
15822 /* SCU_HIBERNATE_HDSET = Hibernate Domain Status Set Register*/
\r
15823 #define SCU_HIBERNATE_HDSET_EPEV_Pos (0U)
\r
15824 #define SCU_HIBERNATE_HDSET_EPEV_Msk (0x00000001U << SCU_HIBERNATE_HDSET_EPEV_Pos)
\r
15826 #define SCU_HIBERNATE_HDSET_ENEV_Pos (1U)
\r
15827 #define SCU_HIBERNATE_HDSET_ENEV_Msk (0x00000001U << SCU_HIBERNATE_HDSET_ENEV_Pos)
\r
15829 #define SCU_HIBERNATE_HDSET_RTCEV_Pos (2U)
\r
15830 #define SCU_HIBERNATE_HDSET_RTCEV_Msk (0x00000001U << SCU_HIBERNATE_HDSET_RTCEV_Pos)
\r
15832 #define SCU_HIBERNATE_HDSET_ULPWDG_Pos (3U)
\r
15833 #define SCU_HIBERNATE_HDSET_ULPWDG_Msk (0x00000001U << SCU_HIBERNATE_HDSET_ULPWDG_Pos)
\r
15835 /* SCU_HIBERNATE_HDCR = Hibernate Domain Configuration Register*/
\r
15836 #define SCU_HIBERNATE_HDCR_WKPEP_Pos (0U)
\r
15837 #define SCU_HIBERNATE_HDCR_WKPEP_Msk (0x00000001U << SCU_HIBERNATE_HDCR_WKPEP_Pos)
\r
15839 #define SCU_HIBERNATE_HDCR_WKPEN_Pos (1U)
\r
15840 #define SCU_HIBERNATE_HDCR_WKPEN_Msk (0x00000001U << SCU_HIBERNATE_HDCR_WKPEN_Pos)
\r
15842 #define SCU_HIBERNATE_HDCR_RTCE_Pos (2U)
\r
15843 #define SCU_HIBERNATE_HDCR_RTCE_Msk (0x00000001U << SCU_HIBERNATE_HDCR_RTCE_Pos)
\r
15845 #define SCU_HIBERNATE_HDCR_ULPWDGEN_Pos (3U)
\r
15846 #define SCU_HIBERNATE_HDCR_ULPWDGEN_Msk (0x00000001U << SCU_HIBERNATE_HDCR_ULPWDGEN_Pos)
\r
15848 #define SCU_HIBERNATE_HDCR_HIB_Pos (4U)
\r
15849 #define SCU_HIBERNATE_HDCR_HIB_Msk (0x00000001U << SCU_HIBERNATE_HDCR_HIB_Pos)
\r
15851 #define SCU_HIBERNATE_HDCR_RCS_Pos (6U)
\r
15852 #define SCU_HIBERNATE_HDCR_RCS_Msk (0x00000001U << SCU_HIBERNATE_HDCR_RCS_Pos)
\r
15854 #define SCU_HIBERNATE_HDCR_STDBYSEL_Pos (7U)
\r
15855 #define SCU_HIBERNATE_HDCR_STDBYSEL_Msk (0x00000001U << SCU_HIBERNATE_HDCR_STDBYSEL_Pos)
\r
15857 #define SCU_HIBERNATE_HDCR_WKUPSEL_Pos (8U)
\r
15858 #define SCU_HIBERNATE_HDCR_WKUPSEL_Msk (0x00000001U << SCU_HIBERNATE_HDCR_WKUPSEL_Pos)
\r
15860 #define SCU_HIBERNATE_HDCR_GPI0SEL_Pos (10U)
\r
15861 #define SCU_HIBERNATE_HDCR_GPI0SEL_Msk (0x00000001U << SCU_HIBERNATE_HDCR_GPI0SEL_Pos)
\r
15863 #define SCU_HIBERNATE_HDCR_HIBIO0POL_Pos (12U)
\r
15864 #define SCU_HIBERNATE_HDCR_HIBIO0POL_Msk (0x00000001U << SCU_HIBERNATE_HDCR_HIBIO0POL_Pos)
\r
15866 #define SCU_HIBERNATE_HDCR_HIBIO1POL_Pos (13U)
\r
15867 #define SCU_HIBERNATE_HDCR_HIBIO1POL_Msk (0x00000001U << SCU_HIBERNATE_HDCR_HIBIO1POL_Pos)
\r
15869 #define SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos (16U)
\r
15870 #define SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk (0x0000000FU << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos)
\r
15872 #define SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos (20U)
\r
15873 #define SCU_HIBERNATE_HDCR_HIBIO1SEL_Msk (0x0000000FU << SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos)
\r
15875 /* SCU_HIBERNATE_OSCSICTRL = OSC_SI Control Register*/
\r
15876 #define SCU_HIBERNATE_OSCSICTRL_PWD_Pos (0U)
\r
15877 #define SCU_HIBERNATE_OSCSICTRL_PWD_Msk (0x00000001U << SCU_HIBERNATE_OSCSICTRL_PWD_Pos)
\r
15879 /* SCU_HIBERNATE_OSCULSTAT = OSC_ULP Status Register*/
\r
15880 #define SCU_HIBERNATE_OSCULSTAT_X1D_Pos (0U)
\r
15881 #define SCU_HIBERNATE_OSCULSTAT_X1D_Msk (0x00000001U << SCU_HIBERNATE_OSCULSTAT_X1D_Pos)
\r
15883 /* SCU_HIBERNATE_OSCULCTRL = OSC_ULP Control Register*/
\r
15884 #define SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos (0U)
\r
15885 #define SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk (0x00000001U << SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos)
\r
15887 #define SCU_HIBERNATE_OSCULCTRL_MODE_Pos (4U)
\r
15888 #define SCU_HIBERNATE_OSCULCTRL_MODE_Msk (0x00000003U << SCU_HIBERNATE_OSCULCTRL_MODE_Pos)
\r
15891 /*** SCU Bit Fileds *******************/
\r
15892 /***************************************************************************/
\r
15895 /* SCU_POWER_PWRSTAT = PCU Status Register*/
\r
15896 #define SCU_POWER_PWRSTAT_HIBEN_Pos (0U)
\r
15897 #define SCU_POWER_PWRSTAT_HIBEN_Msk (0x00000001U << SCU_POWER_PWRSTAT_HIBEN_Pos)
\r
15899 #define SCU_POWER_PWRSTAT_HPSS_Pos (1U)
\r
15900 #define SCU_POWER_PWRSTAT_HPSS_Msk (0x00000001U << SCU_POWER_PWRSTAT_HPSS_Pos)
\r
15902 #define SCU_POWER_PWRSTAT_USBPHYPDQ_Pos (16U)
\r
15903 #define SCU_POWER_PWRSTAT_USBPHYPDQ_Msk (0x00000001U << SCU_POWER_PWRSTAT_USBPHYPDQ_Pos)
\r
15905 #define SCU_POWER_PWRSTAT_USBOTGEN_Pos (17U)
\r
15906 #define SCU_POWER_PWRSTAT_USBOTGEN_Msk (0x00000001U << SCU_POWER_PWRSTAT_USBOTGEN_Pos)
\r
15908 #define SCU_POWER_PWRSTAT_USBPUWQ_Pos (18U)
\r
15909 #define SCU_POWER_PWRSTAT_USBPUWQ_Msk (0x00000001U << SCU_POWER_PWRSTAT_USBPUWQ_Pos)
\r
15911 /* SCU_POWER_PWRSET = PCU Set Control Register*/
\r
15912 #define SCU_POWER_PWRSET_HIB_Pos (0U)
\r
15913 #define SCU_POWER_PWRSET_HIB_Msk (0x00000001U << SCU_POWER_PWRSET_HIB_Pos)
\r
15915 #define SCU_POWER_PWRSET_USBPHYPDQ_Pos (16U)
\r
15916 #define SCU_POWER_PWRSET_USBPHYPDQ_Msk (0x00000001U << SCU_POWER_PWRSET_USBPHYPDQ_Pos)
\r
15918 #define SCU_POWER_PWRSET_USBOTGEN_Pos (17U)
\r
15919 #define SCU_POWER_PWRSET_USBOTGEN_Msk (0x00000001U << SCU_POWER_PWRSET_USBOTGEN_Pos)
\r
15921 #define SCU_POWER_PWRSET_USBPUWQ_Pos (18U)
\r
15922 #define SCU_POWER_PWRSET_USBPUWQ_Msk (0x00000001U << SCU_POWER_PWRSET_USBPUWQ_Pos)
\r
15924 /* SCU_POWER_PWRCLR = PCU Clear Control Register*/
\r
15925 #define SCU_POWER_PWRCLR_HIB_Pos (0U)
\r
15926 #define SCU_POWER_PWRCLR_HIB_Msk (0x00000001U << SCU_POWER_PWRCLR_HIB_Pos)
\r
15928 #define SCU_POWER_PWRCLR_USBPHYPDQ_Pos (16U)
\r
15929 #define SCU_POWER_PWRCLR_USBPHYPDQ_Msk (0x00000001U << SCU_POWER_PWRCLR_USBPHYPDQ_Pos)
\r
15931 #define SCU_POWER_PWRCLR_USBOTGEN_Pos (17U)
\r
15932 #define SCU_POWER_PWRCLR_USBOTGEN_Msk (0x00000001U << SCU_POWER_PWRCLR_USBOTGEN_Pos)
\r
15934 #define SCU_POWER_PWRCLR_USBPUWQ_Pos (18U)
\r
15935 #define SCU_POWER_PWRCLR_USBPUWQ_Msk (0x00000001U << SCU_POWER_PWRCLR_USBPUWQ_Pos)
\r
15937 /* SCU_POWER_EVRSTAT = EVR Status Register*/
\r
15938 #define SCU_POWER_EVRSTAT_OV13_Pos (1U)
\r
15939 #define SCU_POWER_EVRSTAT_OV13_Msk (0x00000001U << SCU_POWER_EVRSTAT_OV13_Pos)
\r
15941 /* SCU_POWER_EVRVADCSTAT = EVR VADC Status Register*/
\r
15942 #define SCU_POWER_EVRVADCSTAT_VADC13V_Pos (0U)
\r
15943 #define SCU_POWER_EVRVADCSTAT_VADC13V_Msk (0x000000FFU << SCU_POWER_EVRVADCSTAT_VADC13V_Pos)
\r
15945 #define SCU_POWER_EVRVADCSTAT_VADC33V_Pos (8U)
\r
15946 #define SCU_POWER_EVRVADCSTAT_VADC33V_Msk (0x000000FFU << SCU_POWER_EVRVADCSTAT_VADC33V_Pos)
\r
15948 /* SCU_POWER_PWRMON = EVR Power Monitor Control Register*/
\r
15949 #define SCU_POWER_PWRMON_THRS_Pos (0U)
\r
15950 #define SCU_POWER_PWRMON_THRS_Msk (0x000000FFU << SCU_POWER_PWRMON_THRS_Pos)
\r
15952 #define SCU_POWER_PWRMON_INTV_Pos (8U)
\r
15953 #define SCU_POWER_PWRMON_INTV_Msk (0x000000FFU << SCU_POWER_PWRMON_INTV_Pos)
\r
15955 #define SCU_POWER_PWRMON_ENB_Pos (16U)
\r
15956 #define SCU_POWER_PWRMON_ENB_Msk (0x00000001U << SCU_POWER_PWRMON_ENB_Pos)
\r
15959 /*** SCU Bit Fileds *******************/
\r
15960 /***************************************************************************/
\r
15963 /* SCU_RESET_RSTSTAT = RCU Reset Status*/
\r
15964 #define SCU_RESET_RSTSTAT_RSTSTAT_Pos (0U)
\r
15965 #define SCU_RESET_RSTSTAT_RSTSTAT_Msk (0x000000FFU << SCU_RESET_RSTSTAT_RSTSTAT_Pos)
\r
15967 #define SCU_RESET_RSTSTAT_HIBWK_Pos (8U)
\r
15968 #define SCU_RESET_RSTSTAT_HIBWK_Msk (0x00000001U << SCU_RESET_RSTSTAT_HIBWK_Pos)
\r
15970 #define SCU_RESET_RSTSTAT_HIBRS_Pos (9U)
\r
15971 #define SCU_RESET_RSTSTAT_HIBRS_Msk (0x00000001U << SCU_RESET_RSTSTAT_HIBRS_Pos)
\r
15973 #define SCU_RESET_RSTSTAT_LCKEN_Pos (10U)
\r
15974 #define SCU_RESET_RSTSTAT_LCKEN_Msk (0x00000001U << SCU_RESET_RSTSTAT_LCKEN_Pos)
\r
15976 /* SCU_RESET_RSTSET = RCU Reset Set Register*/
\r
15977 #define SCU_RESET_RSTSET_HIBWK_Pos (8U)
\r
15978 #define SCU_RESET_RSTSET_HIBWK_Msk (0x00000001U << SCU_RESET_RSTSET_HIBWK_Pos)
\r
15980 #define SCU_RESET_RSTSET_HIBRS_Pos (9U)
\r
15981 #define SCU_RESET_RSTSET_HIBRS_Msk (0x00000001U << SCU_RESET_RSTSET_HIBRS_Pos)
\r
15983 #define SCU_RESET_RSTSET_LCKEN_Pos (10U)
\r
15984 #define SCU_RESET_RSTSET_LCKEN_Msk (0x00000001U << SCU_RESET_RSTSET_LCKEN_Pos)
\r
15986 /* SCU_RESET_RSTCLR = RCU Reset Clear Register*/
\r
15987 #define SCU_RESET_RSTCLR_RSCLR_Pos (0U)
\r
15988 #define SCU_RESET_RSTCLR_RSCLR_Msk (0x00000001U << SCU_RESET_RSTCLR_RSCLR_Pos)
\r
15990 #define SCU_RESET_RSTCLR_HIBWK_Pos (8U)
\r
15991 #define SCU_RESET_RSTCLR_HIBWK_Msk (0x00000001U << SCU_RESET_RSTCLR_HIBWK_Pos)
\r
15993 #define SCU_RESET_RSTCLR_HIBRS_Pos (9U)
\r
15994 #define SCU_RESET_RSTCLR_HIBRS_Msk (0x00000001U << SCU_RESET_RSTCLR_HIBRS_Pos)
\r
15996 #define SCU_RESET_RSTCLR_LCKEN_Pos (10U)
\r
15997 #define SCU_RESET_RSTCLR_LCKEN_Msk (0x00000001U << SCU_RESET_RSTCLR_LCKEN_Pos)
\r
15999 /* SCU_RESET_PRSTAT0 = RCU Peripheral x Reset Status*/
\r
16000 #define SCU_RESET_PRSTAT0_VADCRS_Pos (0U)
\r
16001 #define SCU_RESET_PRSTAT0_VADCRS_Msk (0x00000001U << SCU_RESET_PRSTAT0_VADCRS_Pos)
\r
16003 #define SCU_RESET_PRSTAT0_DSDRS_Pos (1U)
\r
16004 #define SCU_RESET_PRSTAT0_DSDRS_Msk (0x00000001U << SCU_RESET_PRSTAT0_DSDRS_Pos)
\r
16006 #define SCU_RESET_PRSTAT0_CCU40RS_Pos (2U)
\r
16007 #define SCU_RESET_PRSTAT0_CCU40RS_Msk (0x00000001U << SCU_RESET_PRSTAT0_CCU40RS_Pos)
\r
16009 #define SCU_RESET_PRSTAT0_CCU41RS_Pos (3U)
\r
16010 #define SCU_RESET_PRSTAT0_CCU41RS_Msk (0x00000001U << SCU_RESET_PRSTAT0_CCU41RS_Pos)
\r
16012 #define SCU_RESET_PRSTAT0_CCU42RS_Pos (4U)
\r
16013 #define SCU_RESET_PRSTAT0_CCU42RS_Msk (0x00000001U << SCU_RESET_PRSTAT0_CCU42RS_Pos)
\r
16015 #define SCU_RESET_PRSTAT0_CCU80RS_Pos (7U)
\r
16016 #define SCU_RESET_PRSTAT0_CCU80RS_Msk (0x00000001U << SCU_RESET_PRSTAT0_CCU80RS_Pos)
\r
16018 #define SCU_RESET_PRSTAT0_CCU81RS_Pos (8U)
\r
16019 #define SCU_RESET_PRSTAT0_CCU81RS_Msk (0x00000001U << SCU_RESET_PRSTAT0_CCU81RS_Pos)
\r
16021 #define SCU_RESET_PRSTAT0_POSIF0RS_Pos (9U)
\r
16022 #define SCU_RESET_PRSTAT0_POSIF0RS_Msk (0x00000001U << SCU_RESET_PRSTAT0_POSIF0RS_Pos)
\r
16024 #define SCU_RESET_PRSTAT0_POSIF1RS_Pos (10U)
\r
16025 #define SCU_RESET_PRSTAT0_POSIF1RS_Msk (0x00000001U << SCU_RESET_PRSTAT0_POSIF1RS_Pos)
\r
16027 #define SCU_RESET_PRSTAT0_USIC0RS_Pos (11U)
\r
16028 #define SCU_RESET_PRSTAT0_USIC0RS_Msk (0x00000001U << SCU_RESET_PRSTAT0_USIC0RS_Pos)
\r
16030 #define SCU_RESET_PRSTAT0_ERU1RS_Pos (16U)
\r
16031 #define SCU_RESET_PRSTAT0_ERU1RS_Msk (0x00000001U << SCU_RESET_PRSTAT0_ERU1RS_Pos)
\r
16033 /* SCU_RESET_PRSET0 = RCU Peripheral x Reset Set*/
\r
16034 #define SCU_RESET_PRSET0_VADCRS_Pos (0U)
\r
16035 #define SCU_RESET_PRSET0_VADCRS_Msk (0x00000001U << SCU_RESET_PRSET0_VADCRS_Pos)
\r
16037 #define SCU_RESET_PRSET0_DSDRS_Pos (1U)
\r
16038 #define SCU_RESET_PRSET0_DSDRS_Msk (0x00000001U << SCU_RESET_PRSET0_DSDRS_Pos)
\r
16040 #define SCU_RESET_PRSET0_CCU40RS_Pos (2U)
\r
16041 #define SCU_RESET_PRSET0_CCU40RS_Msk (0x00000001U << SCU_RESET_PRSET0_CCU40RS_Pos)
\r
16043 #define SCU_RESET_PRSET0_CCU41RS_Pos (3U)
\r
16044 #define SCU_RESET_PRSET0_CCU41RS_Msk (0x00000001U << SCU_RESET_PRSET0_CCU41RS_Pos)
\r
16046 #define SCU_RESET_PRSET0_CCU42RS_Pos (4U)
\r
16047 #define SCU_RESET_PRSET0_CCU42RS_Msk (0x00000001U << SCU_RESET_PRSET0_CCU42RS_Pos)
\r
16049 #define SCU_RESET_PRSET0_CCU80RS_Pos (7U)
\r
16050 #define SCU_RESET_PRSET0_CCU80RS_Msk (0x00000001U << SCU_RESET_PRSET0_CCU80RS_Pos)
\r
16052 #define SCU_RESET_PRSET0_CCU81RS_Pos (8U)
\r
16053 #define SCU_RESET_PRSET0_CCU81RS_Msk (0x00000001U << SCU_RESET_PRSET0_CCU81RS_Pos)
\r
16055 #define SCU_RESET_PRSET0_POSIF0RS_Pos (9U)
\r
16056 #define SCU_RESET_PRSET0_POSIF0RS_Msk (0x00000001U << SCU_RESET_PRSET0_POSIF0RS_Pos)
\r
16058 #define SCU_RESET_PRSET0_POSIF1RS_Pos (10U)
\r
16059 #define SCU_RESET_PRSET0_POSIF1RS_Msk (0x00000001U << SCU_RESET_PRSET0_POSIF1RS_Pos)
\r
16061 #define SCU_RESET_PRSET0_USIC0RS_Pos (11U)
\r
16062 #define SCU_RESET_PRSET0_USIC0RS_Msk (0x00000001U << SCU_RESET_PRSET0_USIC0RS_Pos)
\r
16064 #define SCU_RESET_PRSET0_ERU1RS_Pos (16U)
\r
16065 #define SCU_RESET_PRSET0_ERU1RS_Msk (0x00000001U << SCU_RESET_PRSET0_ERU1RS_Pos)
\r
16067 /* SCU_RESET_PRCLR0 = RCU Peripheral x Reset Clear*/
\r
16068 #define SCU_RESET_PRCLR0_VADCRS_Pos (0U)
\r
16069 #define SCU_RESET_PRCLR0_VADCRS_Msk (0x00000001U << SCU_RESET_PRCLR0_VADCRS_Pos)
\r
16071 #define SCU_RESET_PRCLR0_DSDRS_Pos (1U)
\r
16072 #define SCU_RESET_PRCLR0_DSDRS_Msk (0x00000001U << SCU_RESET_PRCLR0_DSDRS_Pos)
\r
16074 #define SCU_RESET_PRCLR0_CCU40RS_Pos (2U)
\r
16075 #define SCU_RESET_PRCLR0_CCU40RS_Msk (0x00000001U << SCU_RESET_PRCLR0_CCU40RS_Pos)
\r
16077 #define SCU_RESET_PRCLR0_CCU41RS_Pos (3U)
\r
16078 #define SCU_RESET_PRCLR0_CCU41RS_Msk (0x00000001U << SCU_RESET_PRCLR0_CCU41RS_Pos)
\r
16080 #define SCU_RESET_PRCLR0_CCU42RS_Pos (4U)
\r
16081 #define SCU_RESET_PRCLR0_CCU42RS_Msk (0x00000001U << SCU_RESET_PRCLR0_CCU42RS_Pos)
\r
16083 #define SCU_RESET_PRCLR0_CCU80RS_Pos (7U)
\r
16084 #define SCU_RESET_PRCLR0_CCU80RS_Msk (0x00000001U << SCU_RESET_PRCLR0_CCU80RS_Pos)
\r
16086 #define SCU_RESET_PRCLR0_CCU81RS_Pos (8U)
\r
16087 #define SCU_RESET_PRCLR0_CCU81RS_Msk (0x00000001U << SCU_RESET_PRCLR0_CCU81RS_Pos)
\r
16089 #define SCU_RESET_PRCLR0_POSIF0RS_Pos (9U)
\r
16090 #define SCU_RESET_PRCLR0_POSIF0RS_Msk (0x00000001U << SCU_RESET_PRCLR0_POSIF0RS_Pos)
\r
16092 #define SCU_RESET_PRCLR0_POSIF1RS_Pos (10U)
\r
16093 #define SCU_RESET_PRCLR0_POSIF1RS_Msk (0x00000001U << SCU_RESET_PRCLR0_POSIF1RS_Pos)
\r
16095 #define SCU_RESET_PRCLR0_USIC0RS_Pos (11U)
\r
16096 #define SCU_RESET_PRCLR0_USIC0RS_Msk (0x00000001U << SCU_RESET_PRCLR0_USIC0RS_Pos)
\r
16098 #define SCU_RESET_PRCLR0_ERU1RS_Pos (16U)
\r
16099 #define SCU_RESET_PRCLR0_ERU1RS_Msk (0x00000001U << SCU_RESET_PRCLR0_ERU1RS_Pos)
\r
16101 /* SCU_RESET_PRSTAT1 = RCU Peripheral 1 Reset Status*/
\r
16102 #define SCU_RESET_PRSTAT1_CCU43RS_Pos (0U)
\r
16103 #define SCU_RESET_PRSTAT1_CCU43RS_Msk (0x00000001U << SCU_RESET_PRSTAT1_CCU43RS_Pos)
\r
16105 #define SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos (3U)
\r
16106 #define SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk (0x00000001U << SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos)
\r
16108 #define SCU_RESET_PRSTAT1_MCAN0RS_Pos (4U)
\r
16109 #define SCU_RESET_PRSTAT1_MCAN0RS_Msk (0x00000001U << SCU_RESET_PRSTAT1_MCAN0RS_Pos)
\r
16111 #define SCU_RESET_PRSTAT1_DACRS_Pos (5U)
\r
16112 #define SCU_RESET_PRSTAT1_DACRS_Msk (0x00000001U << SCU_RESET_PRSTAT1_DACRS_Pos)
\r
16114 #define SCU_RESET_PRSTAT1_MMCIRS_Pos (6U)
\r
16115 #define SCU_RESET_PRSTAT1_MMCIRS_Msk (0x00000001U << SCU_RESET_PRSTAT1_MMCIRS_Pos)
\r
16117 #define SCU_RESET_PRSTAT1_USIC1RS_Pos (7U)
\r
16118 #define SCU_RESET_PRSTAT1_USIC1RS_Msk (0x00000001U << SCU_RESET_PRSTAT1_USIC1RS_Pos)
\r
16120 #define SCU_RESET_PRSTAT1_USIC2RS_Pos (8U)
\r
16121 #define SCU_RESET_PRSTAT1_USIC2RS_Msk (0x00000001U << SCU_RESET_PRSTAT1_USIC2RS_Pos)
\r
16123 #define SCU_RESET_PRSTAT1_PPORTSRS_Pos (9U)
\r
16124 #define SCU_RESET_PRSTAT1_PPORTSRS_Msk (0x00000001U << SCU_RESET_PRSTAT1_PPORTSRS_Pos)
\r
16126 /* SCU_RESET_PRSET1 = RCU Peripheral 1 Reset Set*/
\r
16127 #define SCU_RESET_PRSET1_CCU43RS_Pos (0U)
\r
16128 #define SCU_RESET_PRSET1_CCU43RS_Msk (0x00000001U << SCU_RESET_PRSET1_CCU43RS_Pos)
\r
16130 #define SCU_RESET_PRSET1_LEDTSCU0RS_Pos (3U)
\r
16131 #define SCU_RESET_PRSET1_LEDTSCU0RS_Msk (0x00000001U << SCU_RESET_PRSET1_LEDTSCU0RS_Pos)
\r
16133 #define SCU_RESET_PRSET1_MCAN0RS_Pos (4U)
\r
16134 #define SCU_RESET_PRSET1_MCAN0RS_Msk (0x00000001U << SCU_RESET_PRSET1_MCAN0RS_Pos)
\r
16136 #define SCU_RESET_PRSET1_DACRS_Pos (5U)
\r
16137 #define SCU_RESET_PRSET1_DACRS_Msk (0x00000001U << SCU_RESET_PRSET1_DACRS_Pos)
\r
16139 #define SCU_RESET_PRSET1_MMCIRS_Pos (6U)
\r
16140 #define SCU_RESET_PRSET1_MMCIRS_Msk (0x00000001U << SCU_RESET_PRSET1_MMCIRS_Pos)
\r
16142 #define SCU_RESET_PRSET1_USIC1RS_Pos (7U)
\r
16143 #define SCU_RESET_PRSET1_USIC1RS_Msk (0x00000001U << SCU_RESET_PRSET1_USIC1RS_Pos)
\r
16145 #define SCU_RESET_PRSET1_USIC2RS_Pos (8U)
\r
16146 #define SCU_RESET_PRSET1_USIC2RS_Msk (0x00000001U << SCU_RESET_PRSET1_USIC2RS_Pos)
\r
16148 #define SCU_RESET_PRSET1_PPORTSRS_Pos (9U)
\r
16149 #define SCU_RESET_PRSET1_PPORTSRS_Msk (0x00000001U << SCU_RESET_PRSET1_PPORTSRS_Pos)
\r
16151 /* SCU_RESET_PRCLR1 = RCU Peripheral 1 Reset Clear*/
\r
16152 #define SCU_RESET_PRCLR1_CCU43RS_Pos (0U)
\r
16153 #define SCU_RESET_PRCLR1_CCU43RS_Msk (0x00000001U << SCU_RESET_PRCLR1_CCU43RS_Pos)
\r
16155 #define SCU_RESET_PRCLR1_LEDTSCU0RS_Pos (3U)
\r
16156 #define SCU_RESET_PRCLR1_LEDTSCU0RS_Msk (0x00000001U << SCU_RESET_PRCLR1_LEDTSCU0RS_Pos)
\r
16158 #define SCU_RESET_PRCLR1_MCAN0RS_Pos (4U)
\r
16159 #define SCU_RESET_PRCLR1_MCAN0RS_Msk (0x00000001U << SCU_RESET_PRCLR1_MCAN0RS_Pos)
\r
16161 #define SCU_RESET_PRCLR1_DACRS_Pos (5U)
\r
16162 #define SCU_RESET_PRCLR1_DACRS_Msk (0x00000001U << SCU_RESET_PRCLR1_DACRS_Pos)
\r
16164 #define SCU_RESET_PRCLR1_MMCIRS_Pos (6U)
\r
16165 #define SCU_RESET_PRCLR1_MMCIRS_Msk (0x00000001U << SCU_RESET_PRCLR1_MMCIRS_Pos)
\r
16167 #define SCU_RESET_PRCLR1_USIC1RS_Pos (7U)
\r
16168 #define SCU_RESET_PRCLR1_USIC1RS_Msk (0x00000001U << SCU_RESET_PRCLR1_USIC1RS_Pos)
\r
16170 #define SCU_RESET_PRCLR1_USIC2RS_Pos (8U)
\r
16171 #define SCU_RESET_PRCLR1_USIC2RS_Msk (0x00000001U << SCU_RESET_PRCLR1_USIC2RS_Pos)
\r
16173 #define SCU_RESET_PRCLR1_PPORTSRS_Pos (9U)
\r
16174 #define SCU_RESET_PRCLR1_PPORTSRS_Msk (0x00000001U << SCU_RESET_PRCLR1_PPORTSRS_Pos)
\r
16176 /* SCU_RESET_PRSTAT2 = RCU Peripheral 2 Reset Status*/
\r
16177 #define SCU_RESET_PRSTAT2_WDTRS_Pos (1U)
\r
16178 #define SCU_RESET_PRSTAT2_WDTRS_Msk (0x00000001U << SCU_RESET_PRSTAT2_WDTRS_Pos)
\r
16180 #define SCU_RESET_PRSTAT2_ETH0RS_Pos (2U)
\r
16181 #define SCU_RESET_PRSTAT2_ETH0RS_Msk (0x00000001U << SCU_RESET_PRSTAT2_ETH0RS_Pos)
\r
16183 #define SCU_RESET_PRSTAT2_DMA0RS_Pos (4U)
\r
16184 #define SCU_RESET_PRSTAT2_DMA0RS_Msk (0x00000001U << SCU_RESET_PRSTAT2_DMA0RS_Pos)
\r
16186 #define SCU_RESET_PRSTAT2_DMA1RS_Pos (5U)
\r
16187 #define SCU_RESET_PRSTAT2_DMA1RS_Msk (0x00000001U << SCU_RESET_PRSTAT2_DMA1RS_Pos)
\r
16189 #define SCU_RESET_PRSTAT2_FCERS_Pos (6U)
\r
16190 #define SCU_RESET_PRSTAT2_FCERS_Msk (0x00000001U << SCU_RESET_PRSTAT2_FCERS_Pos)
\r
16192 #define SCU_RESET_PRSTAT2_USBRS_Pos (7U)
\r
16193 #define SCU_RESET_PRSTAT2_USBRS_Msk (0x00000001U << SCU_RESET_PRSTAT2_USBRS_Pos)
\r
16195 /* SCU_RESET_PRSET2 = RCU Peripheral 2 Reset Set*/
\r
16196 #define SCU_RESET_PRSET2_WDTRS_Pos (1U)
\r
16197 #define SCU_RESET_PRSET2_WDTRS_Msk (0x00000001U << SCU_RESET_PRSET2_WDTRS_Pos)
\r
16199 #define SCU_RESET_PRSET2_ETH0RS_Pos (2U)
\r
16200 #define SCU_RESET_PRSET2_ETH0RS_Msk (0x00000001U << SCU_RESET_PRSET2_ETH0RS_Pos)
\r
16202 #define SCU_RESET_PRSET2_DMA0RS_Pos (4U)
\r
16203 #define SCU_RESET_PRSET2_DMA0RS_Msk (0x00000001U << SCU_RESET_PRSET2_DMA0RS_Pos)
\r
16205 #define SCU_RESET_PRSET2_DMA1RS_Pos (5U)
\r
16206 #define SCU_RESET_PRSET2_DMA1RS_Msk (0x00000001U << SCU_RESET_PRSET2_DMA1RS_Pos)
\r
16208 #define SCU_RESET_PRSET2_FCERS_Pos (6U)
\r
16209 #define SCU_RESET_PRSET2_FCERS_Msk (0x00000001U << SCU_RESET_PRSET2_FCERS_Pos)
\r
16211 #define SCU_RESET_PRSET2_USBRS_Pos (7U)
\r
16212 #define SCU_RESET_PRSET2_USBRS_Msk (0x00000001U << SCU_RESET_PRSET2_USBRS_Pos)
\r
16214 /* SCU_RESET_PRCLR2 = RCU Peripheral 2 Reset Clear*/
\r
16215 #define SCU_RESET_PRCLR2_WDTRS_Pos (1U)
\r
16216 #define SCU_RESET_PRCLR2_WDTRS_Msk (0x00000001U << SCU_RESET_PRCLR2_WDTRS_Pos)
\r
16218 #define SCU_RESET_PRCLR2_ETH0RS_Pos (2U)
\r
16219 #define SCU_RESET_PRCLR2_ETH0RS_Msk (0x00000001U << SCU_RESET_PRCLR2_ETH0RS_Pos)
\r
16221 #define SCU_RESET_PRCLR2_DMA0RS_Pos (4U)
\r
16222 #define SCU_RESET_PRCLR2_DMA0RS_Msk (0x00000001U << SCU_RESET_PRCLR2_DMA0RS_Pos)
\r
16224 #define SCU_RESET_PRCLR2_DMA1RS_Pos (5U)
\r
16225 #define SCU_RESET_PRCLR2_DMA1RS_Msk (0x00000001U << SCU_RESET_PRCLR2_DMA1RS_Pos)
\r
16227 #define SCU_RESET_PRCLR2_FCERS_Pos (6U)
\r
16228 #define SCU_RESET_PRCLR2_FCERS_Msk (0x00000001U << SCU_RESET_PRCLR2_FCERS_Pos)
\r
16230 #define SCU_RESET_PRCLR2_USBRS_Pos (7U)
\r
16231 #define SCU_RESET_PRCLR2_USBRS_Msk (0x00000001U << SCU_RESET_PRCLR2_USBRS_Pos)
\r
16233 /* SCU_RESET_PRSTAT3 = RCU Peripheral 3 Reset Status*/
\r
16234 #define SCU_RESET_PRSTAT3_EBURS_Pos (2U)
\r
16235 #define SCU_RESET_PRSTAT3_EBURS_Msk (0x00000001U << SCU_RESET_PRSTAT3_EBURS_Pos)
\r
16237 /* SCU_RESET_PRSET3 = RCU Peripheral 3 Reset Set*/
\r
16238 #define SCU_RESET_PRSET3_EBURS_Pos (2U)
\r
16239 #define SCU_RESET_PRSET3_EBURS_Msk (0x00000001U << SCU_RESET_PRSET3_EBURS_Pos)
\r
16241 /* SCU_RESET_PRCLR3 = RCU Peripheral 3 Reset Clear*/
\r
16242 #define SCU_RESET_PRCLR3_EBURS_Pos (2U)
\r
16243 #define SCU_RESET_PRCLR3_EBURS_Msk (0x00000001U << SCU_RESET_PRCLR3_EBURS_Pos)
\r
16247 /*** SDMMC Bit Fileds *******************/
\r
16248 /***************************************************************************/
\r
16251 /* SDMMC_BLOCK_SIZE = Block Size Register*/
\r
16252 #define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Pos (15U)
\r
16253 #define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Msk (0x00000001U << SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Pos)
\r
16255 #define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Pos (0U)
\r
16256 #define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Msk (0x00000FFFU << SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Pos)
\r
16258 /* SDMMC_BLOCK_COUNT = Block Count Register*/
\r
16259 #define SDMMC_BLOCK_COUNT_BLOCK_COUNT_Pos (0U)
\r
16260 #define SDMMC_BLOCK_COUNT_BLOCK_COUNT_Msk (0x0000FFFFU << SDMMC_BLOCK_COUNT_BLOCK_COUNT_Pos)
\r
16262 /* SDMMC_ARGUMENT1 = Argument1 Register*/
\r
16263 #define SDMMC_ARGUMENT1_ARGUMENT1_Pos (0U)
\r
16264 #define SDMMC_ARGUMENT1_ARGUMENT1_Msk (0xFFFFFFFFU << SDMMC_ARGUMENT1_ARGUMENT1_Pos)
\r
16266 /* SDMMC_TRANSFER_MODE = Transfer Mode Register*/
\r
16267 #define SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Pos (6U)
\r
16268 #define SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Msk (0x00000001U << SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Pos)
\r
16270 #define SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Pos (5U)
\r
16271 #define SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Msk (0x00000001U << SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Pos)
\r
16273 #define SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos (4U)
\r
16274 #define SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Msk (0x00000001U << SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos)
\r
16276 #define SDMMC_TRANSFER_MODE_ACMD_EN_Pos (2U)
\r
16277 #define SDMMC_TRANSFER_MODE_ACMD_EN_Msk (0x00000003U << SDMMC_TRANSFER_MODE_ACMD_EN_Pos)
\r
16279 #define SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Pos (1U)
\r
16280 #define SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Msk (0x00000001U << SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Pos)
\r
16282 /* SDMMC_COMMAND = Command Register*/
\r
16283 #define SDMMC_COMMAND_CMD_IND_Pos (8U)
\r
16284 #define SDMMC_COMMAND_CMD_IND_Msk (0x0000003FU << SDMMC_COMMAND_CMD_IND_Pos)
\r
16286 #define SDMMC_COMMAND_CMD_TYPE_Pos (6U)
\r
16287 #define SDMMC_COMMAND_CMD_TYPE_Msk (0x00000003U << SDMMC_COMMAND_CMD_TYPE_Pos)
\r
16289 #define SDMMC_COMMAND_DATA_PRESENT_SELECT_Pos (5U)
\r
16290 #define SDMMC_COMMAND_DATA_PRESENT_SELECT_Msk (0x00000001U << SDMMC_COMMAND_DATA_PRESENT_SELECT_Pos)
\r
16292 #define SDMMC_COMMAND_CMD_IND_CHECK_EN_Pos (4U)
\r
16293 #define SDMMC_COMMAND_CMD_IND_CHECK_EN_Msk (0x00000001U << SDMMC_COMMAND_CMD_IND_CHECK_EN_Pos)
\r
16295 #define SDMMC_COMMAND_CMD_CRC_CHECK_EN_Pos (3U)
\r
16296 #define SDMMC_COMMAND_CMD_CRC_CHECK_EN_Msk (0x00000001U << SDMMC_COMMAND_CMD_CRC_CHECK_EN_Pos)
\r
16298 #define SDMMC_COMMAND_RESP_TYPE_SELECT_Pos (0U)
\r
16299 #define SDMMC_COMMAND_RESP_TYPE_SELECT_Msk (0x00000003U << SDMMC_COMMAND_RESP_TYPE_SELECT_Pos)
\r
16301 /* SDMMC_RESPONSE0 = Response x Register*/
\r
16302 #define SDMMC_RESPONSE0_RESPONSE1_Pos (16U)
\r
16303 #define SDMMC_RESPONSE0_RESPONSE1_Msk (0x0000FFFFU << SDMMC_RESPONSE0_RESPONSE1_Pos)
\r
16305 #define SDMMC_RESPONSE0_RESPONSE0_Pos (0U)
\r
16306 #define SDMMC_RESPONSE0_RESPONSE0_Msk (0x0000FFFFU << SDMMC_RESPONSE0_RESPONSE0_Pos)
\r
16308 /* SDMMC_RESPONSE2 = Response 2 Register*/
\r
16309 #define SDMMC_RESPONSE2_RESPONSE3_Pos (16U)
\r
16310 #define SDMMC_RESPONSE2_RESPONSE3_Msk (0x0000FFFFU << SDMMC_RESPONSE2_RESPONSE3_Pos)
\r
16312 #define SDMMC_RESPONSE2_RESPONSE2_Pos (0U)
\r
16313 #define SDMMC_RESPONSE2_RESPONSE2_Msk (0x0000FFFFU << SDMMC_RESPONSE2_RESPONSE2_Pos)
\r
16315 /* SDMMC_RESPONSE4 = Response 4 Register*/
\r
16316 #define SDMMC_RESPONSE4_RESPONSE5_Pos (16U)
\r
16317 #define SDMMC_RESPONSE4_RESPONSE5_Msk (0x0000FFFFU << SDMMC_RESPONSE4_RESPONSE5_Pos)
\r
16319 #define SDMMC_RESPONSE4_RESPONSE4_Pos (0U)
\r
16320 #define SDMMC_RESPONSE4_RESPONSE4_Msk (0x0000FFFFU << SDMMC_RESPONSE4_RESPONSE4_Pos)
\r
16322 /* SDMMC_RESPONSE6 = Response 6 Register*/
\r
16323 #define SDMMC_RESPONSE6_RESPONSE7_Pos (16U)
\r
16324 #define SDMMC_RESPONSE6_RESPONSE7_Msk (0x0000FFFFU << SDMMC_RESPONSE6_RESPONSE7_Pos)
\r
16326 #define SDMMC_RESPONSE6_RESPONSE6_Pos (0U)
\r
16327 #define SDMMC_RESPONSE6_RESPONSE6_Msk (0x0000FFFFU << SDMMC_RESPONSE6_RESPONSE6_Pos)
\r
16329 /* SDMMC_DATA_BUFFER = Data Buffer Register*/
\r
16330 #define SDMMC_DATA_BUFFER_DATA_BUFFER_Pos (0U)
\r
16331 #define SDMMC_DATA_BUFFER_DATA_BUFFER_Msk (0xFFFFFFFFU << SDMMC_DATA_BUFFER_DATA_BUFFER_Pos)
\r
16333 /* SDMMC_PRESENT_STATE = Present State Register*/
\r
16334 #define SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Pos (25U)
\r
16335 #define SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Msk (0x0000000FU << SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Pos)
\r
16337 #define SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Pos (24U)
\r
16338 #define SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Msk (0x00000001U << SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Pos)
\r
16340 #define SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos (20U)
\r
16341 #define SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Msk (0x0000000FU << SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos)
\r
16343 #define SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Pos (19U)
\r
16344 #define SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Msk (0x00000001U << SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Pos)
\r
16346 #define SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Pos (18U)
\r
16347 #define SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Msk (0x00000001U << SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Pos)
\r
16349 #define SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Pos (17U)
\r
16350 #define SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Msk (0x00000001U << SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Pos)
\r
16352 #define SDMMC_PRESENT_STATE_CARD_INSERTED_Pos (16U)
\r
16353 #define SDMMC_PRESENT_STATE_CARD_INSERTED_Msk (0x00000001U << SDMMC_PRESENT_STATE_CARD_INSERTED_Pos)
\r
16355 #define SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Pos (11U)
\r
16356 #define SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Msk (0x00000001U << SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Pos)
\r
16358 #define SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Pos (10U)
\r
16359 #define SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Msk (0x00000001U << SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Pos)
\r
16361 #define SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Pos (9U)
\r
16362 #define SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Msk (0x00000001U << SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Pos)
\r
16364 #define SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Pos (8U)
\r
16365 #define SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Msk (0x00000001U << SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Pos)
\r
16367 #define SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Pos (2U)
\r
16368 #define SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Msk (0x00000001U << SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Pos)
\r
16370 #define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Pos (1U)
\r
16371 #define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Msk (0x00000001U << SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Pos)
\r
16373 #define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Pos (0U)
\r
16374 #define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Msk (0x00000001U << SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Pos)
\r
16376 /* SDMMC_HOST_CTRL = Host Control Register*/
\r
16377 #define SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos (7U)
\r
16378 #define SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Msk (0x00000001U << SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos)
\r
16380 #define SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos (6U)
\r
16381 #define SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Msk (0x00000001U << SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos)
\r
16383 #define SDMMC_HOST_CTRL_HIGH_SPEED_EN_Pos (2U)
\r
16384 #define SDMMC_HOST_CTRL_HIGH_SPEED_EN_Msk (0x00000001U << SDMMC_HOST_CTRL_HIGH_SPEED_EN_Pos)
\r
16386 #define SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos (1U)
\r
16387 #define SDMMC_HOST_CTRL_DATA_TX_WIDTH_Msk (0x00000001U << SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos)
\r
16389 #define SDMMC_HOST_CTRL_LED_CTRL_Pos (0U)
\r
16390 #define SDMMC_HOST_CTRL_LED_CTRL_Msk (0x00000001U << SDMMC_HOST_CTRL_LED_CTRL_Pos)
\r
16392 /* SDMMC_POWER_CTRL = Power Control Register*/
\r
16393 #define SDMMC_POWER_CTRL_HARDWARE_RESET_Pos (4U)
\r
16394 #define SDMMC_POWER_CTRL_HARDWARE_RESET_Msk (0x00000001U << SDMMC_POWER_CTRL_HARDWARE_RESET_Pos)
\r
16396 #define SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos (1U)
\r
16397 #define SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Msk (0x00000007U << SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos)
\r
16399 #define SDMMC_POWER_CTRL_SD_BUS_POWER_Pos (0U)
\r
16400 #define SDMMC_POWER_CTRL_SD_BUS_POWER_Msk (0x00000001U << SDMMC_POWER_CTRL_SD_BUS_POWER_Pos)
\r
16402 /* SDMMC_BLOCK_GAP_CTRL = Block Gap Control Register*/
\r
16403 #define SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Pos (4U)
\r
16404 #define SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Msk (0x00000001U << SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Pos)
\r
16406 #define SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Pos (3U)
\r
16407 #define SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk (0x00000001U << SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Pos)
\r
16409 #define SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Pos (2U)
\r
16410 #define SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Msk (0x00000001U << SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Pos)
\r
16412 #define SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos (1U)
\r
16413 #define SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Msk (0x00000001U << SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos)
\r
16415 #define SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Pos (0U)
\r
16416 #define SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Msk (0x00000001U << SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Pos)
\r
16418 /* SDMMC_WAKEUPORT_CTRL = Wake-up Control Register*/
\r
16419 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Pos (2U)
\r
16420 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Msk (0x00000001U << SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Pos)
\r
16422 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Pos (1U)
\r
16423 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Msk (0x00000001U << SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Pos)
\r
16425 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Pos (0U)
\r
16426 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Msk (0x00000001U << SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Pos)
\r
16428 /* SDMMC_CLOCK_CTRL = Clock Control Register*/
\r
16429 #define SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos (8U)
\r
16430 #define SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Msk (0x000000FFU << SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos)
\r
16432 #define SDMMC_CLOCK_CTRL_SDCLOCK_EN_Pos (2U)
\r
16433 #define SDMMC_CLOCK_CTRL_SDCLOCK_EN_Msk (0x00000001U << SDMMC_CLOCK_CTRL_SDCLOCK_EN_Pos)
\r
16435 #define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Pos (1U)
\r
16436 #define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Msk (0x00000001U << SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Pos)
\r
16438 #define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Pos (0U)
\r
16439 #define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Msk (0x00000001U << SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Pos)
\r
16441 /* SDMMC_TIMEOUT_CTRL = Timeout Control Register*/
\r
16442 #define SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos (0U)
\r
16443 #define SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Msk (0x0000000FU << SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos)
\r
16445 /* SDMMC_SW_RESET = Software Reset Register*/
\r
16446 #define SDMMC_SW_RESET_SW_RST_DAT_LINE_Pos (2U)
\r
16447 #define SDMMC_SW_RESET_SW_RST_DAT_LINE_Msk (0x00000001U << SDMMC_SW_RESET_SW_RST_DAT_LINE_Pos)
\r
16449 #define SDMMC_SW_RESET_SW_RST_CMD_LINE_Pos (1U)
\r
16450 #define SDMMC_SW_RESET_SW_RST_CMD_LINE_Msk (0x00000001U << SDMMC_SW_RESET_SW_RST_CMD_LINE_Pos)
\r
16452 #define SDMMC_SW_RESET_SW_RST_ALL_Pos (0U)
\r
16453 #define SDMMC_SW_RESET_SW_RST_ALL_Msk (0x00000001U << SDMMC_SW_RESET_SW_RST_ALL_Pos)
\r
16455 /* SDMMC_INT_STATUS_NORM = Normal Interrupt Status Register*/
\r
16456 #define SDMMC_INT_STATUS_NORM_ERR_INT_Pos (15U)
\r
16457 #define SDMMC_INT_STATUS_NORM_ERR_INT_Msk (0x00000001U << SDMMC_INT_STATUS_NORM_ERR_INT_Pos)
\r
16459 #define SDMMC_INT_STATUS_NORM_CARD_INT_Pos (8U)
\r
16460 #define SDMMC_INT_STATUS_NORM_CARD_INT_Msk (0x00000001U << SDMMC_INT_STATUS_NORM_CARD_INT_Pos)
\r
16462 #define SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Pos (7U)
\r
16463 #define SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Msk (0x00000001U << SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Pos)
\r
16465 #define SDMMC_INT_STATUS_NORM_CARD_INS_Pos (6U)
\r
16466 #define SDMMC_INT_STATUS_NORM_CARD_INS_Msk (0x00000001U << SDMMC_INT_STATUS_NORM_CARD_INS_Pos)
\r
16468 #define SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Pos (5U)
\r
16469 #define SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Msk (0x00000001U << SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Pos)
\r
16471 #define SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Pos (4U)
\r
16472 #define SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Msk (0x00000001U << SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Pos)
\r
16474 #define SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Pos (2U)
\r
16475 #define SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Msk (0x00000001U << SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Pos)
\r
16477 #define SDMMC_INT_STATUS_NORM_TX_COMPLETE_Pos (1U)
\r
16478 #define SDMMC_INT_STATUS_NORM_TX_COMPLETE_Msk (0x00000001U << SDMMC_INT_STATUS_NORM_TX_COMPLETE_Pos)
\r
16480 #define SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Pos (0U)
\r
16481 #define SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Msk (0x00000001U << SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Pos)
\r
16483 /* SDMMC_INT_STATUS_ERR = Error Interrupt Status Register*/
\r
16484 #define SDMMC_INT_STATUS_ERR_CEATA_ERR_Pos (13U)
\r
16485 #define SDMMC_INT_STATUS_ERR_CEATA_ERR_Msk (0x00000001U << SDMMC_INT_STATUS_ERR_CEATA_ERR_Pos)
\r
16487 #define SDMMC_INT_STATUS_ERR_ACMD_ERR_Pos (8U)
\r
16488 #define SDMMC_INT_STATUS_ERR_ACMD_ERR_Msk (0x00000001U << SDMMC_INT_STATUS_ERR_ACMD_ERR_Pos)
\r
16490 #define SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Pos (7U)
\r
16491 #define SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Msk (0x00000001U << SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Pos)
\r
16493 #define SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Pos (6U)
\r
16494 #define SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Msk (0x00000001U << SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Pos)
\r
16496 #define SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Pos (5U)
\r
16497 #define SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Msk (0x00000001U << SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Pos)
\r
16499 #define SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Pos (4U)
\r
16500 #define SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Msk (0x00000001U << SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Pos)
\r
16502 #define SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Pos (3U)
\r
16503 #define SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Msk (0x00000001U << SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Pos)
\r
16505 #define SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Pos (2U)
\r
16506 #define SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Msk (0x00000001U << SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Pos)
\r
16508 #define SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Pos (1U)
\r
16509 #define SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Msk (0x00000001U << SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Pos)
\r
16511 #define SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Pos (0U)
\r
16512 #define SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Msk (0x00000001U << SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Pos)
\r
16514 /* SDMMC_EN_INT_STATUS_NORM = Normal Interrupt Status Enable Register*/
\r
16515 #define SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Pos (15U)
\r
16516 #define SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Msk (0x00000001U << SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Pos)
\r
16518 #define SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Pos (8U)
\r
16519 #define SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Pos)
\r
16521 #define SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Pos (7U)
\r
16522 #define SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Pos)
\r
16524 #define SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Pos (6U)
\r
16525 #define SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Pos)
\r
16527 #define SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Pos (5U)
\r
16528 #define SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Pos)
\r
16530 #define SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Pos (4U)
\r
16531 #define SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Pos)
\r
16533 #define SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Pos (2U)
\r
16534 #define SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Pos)
\r
16536 #define SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Pos (1U)
\r
16537 #define SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Pos)
\r
16539 #define SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Pos (0U)
\r
16540 #define SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Pos)
\r
16542 /* SDMMC_EN_INT_STATUS_ERR = Error Interrupt Status Enable Register*/
\r
16543 #define SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Pos (13U)
\r
16544 #define SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Pos)
\r
16546 #define SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Pos (12U)
\r
16547 #define SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Pos)
\r
16549 #define SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Pos (8U)
\r
16550 #define SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Pos)
\r
16552 #define SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Pos (7U)
\r
16553 #define SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Pos)
\r
16555 #define SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Pos (6U)
\r
16556 #define SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Pos)
\r
16558 #define SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Pos (5U)
\r
16559 #define SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Pos)
\r
16561 #define SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Pos (4U)
\r
16562 #define SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Pos)
\r
16564 #define SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Pos (3U)
\r
16565 #define SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Pos)
\r
16567 #define SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Pos (2U)
\r
16568 #define SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Pos)
\r
16570 #define SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Pos (1U)
\r
16571 #define SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Pos)
\r
16573 #define SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Pos (0U)
\r
16574 #define SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Pos)
\r
16576 /* SDMMC_EN_INT_SIGNAL_NORM = Normal Interrupt Signal Enable Register*/
\r
16577 #define SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Pos (15U)
\r
16578 #define SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Pos)
\r
16580 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Pos (8U)
\r
16581 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Pos)
\r
16583 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Pos (7U)
\r
16584 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Pos)
\r
16586 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Pos (6U)
\r
16587 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Pos)
\r
16589 #define SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Pos (5U)
\r
16590 #define SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Pos)
\r
16592 #define SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Pos (4U)
\r
16593 #define SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Pos)
\r
16595 #define SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Pos (2U)
\r
16596 #define SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Pos)
\r
16598 #define SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Pos (1U)
\r
16599 #define SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Pos)
\r
16601 #define SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Pos (0U)
\r
16602 #define SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Pos)
\r
16604 /* SDMMC_EN_INT_SIGNAL_ERR = Error Interrupt Signal Enable Register*/
\r
16605 #define SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Pos (13U)
\r
16606 #define SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Pos)
\r
16608 #define SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Pos (12U)
\r
16609 #define SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Pos)
\r
16611 #define SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Pos (8U)
\r
16612 #define SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Pos)
\r
16614 #define SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Pos (7U)
\r
16615 #define SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Pos)
\r
16617 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Pos (6U)
\r
16618 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Pos)
\r
16620 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Pos (5U)
\r
16621 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Pos)
\r
16623 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Pos (4U)
\r
16624 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Pos)
\r
16626 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Pos (3U)
\r
16627 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Pos)
\r
16629 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Pos (2U)
\r
16630 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Pos)
\r
16632 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Pos (1U)
\r
16633 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Pos)
\r
16635 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Pos (0U)
\r
16636 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Msk (0x00000001U << SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Pos)
\r
16638 /* SDMMC_ACMD_ERR_STATUS = Auto CMD Error Status Register*/
\r
16639 #define SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Pos (7U)
\r
16640 #define SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Msk (0x00000001U << SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Pos)
\r
16642 #define SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Pos (4U)
\r
16643 #define SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Msk (0x00000001U << SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Pos)
\r
16645 #define SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Pos (3U)
\r
16646 #define SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Msk (0x00000001U << SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Pos)
\r
16648 #define SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Pos (2U)
\r
16649 #define SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Msk (0x00000001U << SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Pos)
\r
16651 #define SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Pos (1U)
\r
16652 #define SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Msk (0x00000001U << SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Pos)
\r
16654 #define SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Pos (0U)
\r
16655 #define SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Msk (0x00000001U << SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Pos)
\r
16657 /* SDMMC_FORCE_EVENT_ACMD_ERR_STATUS = Force Event Register for Auto CMD Error Status*/
\r
16658 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Pos (7U)
\r
16659 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Pos)
\r
16661 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Pos (4U)
\r
16662 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Pos)
\r
16664 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Pos (3U)
\r
16665 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Pos)
\r
16667 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Pos (2U)
\r
16668 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Pos)
\r
16670 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Pos (1U)
\r
16671 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Pos)
\r
16673 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Pos (0U)
\r
16674 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Msk (0x00000001U << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Pos)
\r
16676 /* SDMMC_FORCE_EVENT_ERR_STATUS = Force Event Register for Error Interrupt Status*/
\r
16677 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Pos (13U)
\r
16678 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Pos)
\r
16680 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Pos (12U)
\r
16681 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Pos)
\r
16683 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Pos (8U)
\r
16684 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Pos)
\r
16686 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Pos (7U)
\r
16687 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Pos)
\r
16689 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Pos (6U)
\r
16690 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Pos)
\r
16692 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Pos (5U)
\r
16693 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Pos)
\r
16695 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Pos (4U)
\r
16696 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Pos)
\r
16698 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Pos (3U)
\r
16699 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Pos)
\r
16701 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Pos (2U)
\r
16702 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Pos)
\r
16704 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Pos (1U)
\r
16705 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Pos)
\r
16707 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Pos (0U)
\r
16708 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Msk (0x00000001U << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Pos)
\r
16710 /* SDMMC_DEBUG_SEL = Debug Selection Register*/
\r
16711 #define SDMMC_DEBUG_SEL_DEBUG_SEL_Pos (0U)
\r
16712 #define SDMMC_DEBUG_SEL_DEBUG_SEL_Msk (0x00000001U << SDMMC_DEBUG_SEL_DEBUG_SEL_Pos)
\r
16714 /* SDMMC_SPI = SPI Interrupt Support Register*/
\r
16715 #define SDMMC_SPI_SPI_INT_SUPPORT_Pos (0U)
\r
16716 #define SDMMC_SPI_SPI_INT_SUPPORT_Msk (0x000000FFU << SDMMC_SPI_SPI_INT_SUPPORT_Pos)
\r
16718 /* SDMMC_SLOT_INT_STATUS = Slot Interrupt Status Register*/
\r
16719 #define SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Pos (0U)
\r
16720 #define SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Msk (0x000000FFU << SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Pos)
\r
16724 /*** TPIU Bit Fileds *******************/
\r
16725 /***************************************************************************/
\r
16728 // ------------------------------------- TPIU_TPIU_SSPSR ----------------------------------------
\r
16729 #define TPIU_TPIU_SSPSR_SWIDTH_Pos 0 /*!< TPIU TPIU_SSPSR: SWIDTH Position */
\r
16730 #define TPIU_TPIU_SSPSR_SWIDTH_Msk (0xffffffffUL << TPIU_TPIU_SSPSR_SWIDTH_Pos) /*!< TPIU TPIU_SSPSR: SWIDTH Mask */
\r
16732 // ------------------------------------- TPIU_TPIU_CSPSR ----------------------------------------
\r
16733 #define TPIU_TPIU_CSPSR_CWIDTH_Pos 0 /*!< TPIU TPIU_CSPSR: CWIDTH Position */
\r
16734 #define TPIU_TPIU_CSPSR_CWIDTH_Msk (0xffffffffUL << TPIU_TPIU_CSPSR_CWIDTH_Pos) /*!< TPIU TPIU_CSPSR: CWIDTH Mask */
\r
16736 // ------------------------------------- TPIU_TPIU_ACPR -----------------------------------------
\r
16737 #define TPIU_TPIU_ACPR_PRESCALER_Pos 0 /*!< TPIU TPIU_ACPR: PRESCALER Position */
\r
16738 #define TPIU_TPIU_ACPR_PRESCALER_Msk (0x00001fffUL << TPIU_TPIU_ACPR_PRESCALER_Pos) /*!< TPIU TPIU_ACPR: PRESCALER Mask */
\r
16739 #define TPIU_TPIU_ACPR_Reserved_Pos 13 /*!< TPIU TPIU_ACPR: Reserved Position */
\r
16740 #define TPIU_TPIU_ACPR_Reserved_Msk (0x0007ffffUL << TPIU_TPIU_ACPR_Reserved_Pos) /*!< TPIU TPIU_ACPR: Reserved Mask */
\r
16742 // ------------------------------------- TPIU_TPIU_SPPR -----------------------------------------
\r
16743 #define TPIU_TPIU_SPPR_TXMODE_Pos 0 /*!< TPIU TPIU_SPPR: TXMODE Position */
\r
16744 #define TPIU_TPIU_SPPR_TXMODE_Msk (0x03UL << TPIU_TPIU_SPPR_TXMODE_Pos) /*!< TPIU TPIU_SPPR: TXMODE Mask */
\r
16745 #define TPIU_TPIU_SPPR_Reserved_Pos 2 /*!< TPIU TPIU_SPPR: Reserved Position */
\r
16746 #define TPIU_TPIU_SPPR_Reserved_Msk (0x3fffffffUL << TPIU_TPIU_SPPR_Reserved_Pos) /*!< TPIU TPIU_SPPR: Reserved Mask */
\r
16748 // ------------------------------------- TPIU_TPIU_FFSR -----------------------------------------
\r
16749 #define TPIU_TPIU_FFSR_FlInProg_Pos 0 /*!< TPIU TPIU_FFSR: FlInProg Position */
\r
16750 #define TPIU_TPIU_FFSR_FlInProg_Msk (0x01UL << TPIU_TPIU_FFSR_FlInProg_Pos) /*!< TPIU TPIU_FFSR: FlInProg Mask */
\r
16751 #define TPIU_TPIU_FFSR_FtStopped_Pos 1 /*!< TPIU TPIU_FFSR: FtStopped Position */
\r
16752 #define TPIU_TPIU_FFSR_FtStopped_Msk (0x01UL << TPIU_TPIU_FFSR_FtStopped_Pos) /*!< TPIU TPIU_FFSR: FtStopped Mask */
\r
16753 #define TPIU_TPIU_FFSR_TCPresent_Pos 2 /*!< TPIU TPIU_FFSR: TCPresent Position */
\r
16754 #define TPIU_TPIU_FFSR_TCPresent_Msk (0x01UL << TPIU_TPIU_FFSR_TCPresent_Pos) /*!< TPIU TPIU_FFSR: TCPresent Mask */
\r
16755 #define TPIU_TPIU_FFSR_FtNonStop_Pos 3 /*!< TPIU TPIU_FFSR: FtNonStop Position */
\r
16756 #define TPIU_TPIU_FFSR_FtNonStop_Msk (0x01UL << TPIU_TPIU_FFSR_FtNonStop_Pos) /*!< TPIU TPIU_FFSR: FtNonStop Mask */
\r
16757 #define TPIU_TPIU_FFSR_Reserved_Pos 4 /*!< TPIU TPIU_FFSR: Reserved Position */
\r
16758 #define TPIU_TPIU_FFSR_Reserved_Msk (0x0fffffffUL << TPIU_TPIU_FFSR_Reserved_Pos) /*!< TPIU TPIU_FFSR: Reserved Mask */
\r
16760 // ------------------------------------- TPIU_TPIU_FFCR -----------------------------------------
\r
16761 #define TPIU_TPIU_FFCR_Reserved_Pos 0 /*!< TPIU TPIU_FFCR: Reserved Position */
\r
16762 #define TPIU_TPIU_FFCR_Reserved_Msk (0x01UL << TPIU_TPIU_FFCR_Reserved_Pos) /*!< TPIU TPIU_FFCR: Reserved Mask */
\r
16763 #define TPIU_TPIU_FFCR_EnFCont_Pos 1 /*!< TPIU TPIU_FFCR: EnFCont Position */
\r
16764 #define TPIU_TPIU_FFCR_EnFCont_Msk (0x01UL << TPIU_TPIU_FFCR_EnFCont_Pos) /*!< TPIU TPIU_FFCR: EnFCont Mask */
\r
16765 #define TPIU_TPIU_FFCR_Reserved1_Pos 2 /*!< TPIU TPIU_FFCR: Reserved1 Position */
\r
16766 #define TPIU_TPIU_FFCR_Reserved1_Msk (0x3fUL << TPIU_TPIU_FFCR_Reserved1_Pos) /*!< TPIU TPIU_FFCR: Reserved1 Mask */
\r
16767 #define TPIU_TPIU_FFCR_TrigIn_Pos 8 /*!< TPIU TPIU_FFCR: TrigIn Position */
\r
16768 #define TPIU_TPIU_FFCR_TrigIn_Msk (0x01UL << TPIU_TPIU_FFCR_TrigIn_Pos) /*!< TPIU TPIU_FFCR: TrigIn Mask */
\r
16769 #define TPIU_TPIU_FFCR_Reserved2_Pos 9 /*!< TPIU TPIU_FFCR: Reserved2 Position */
\r
16770 #define TPIU_TPIU_FFCR_Reserved2_Msk (0x007fffffUL << TPIU_TPIU_FFCR_Reserved2_Pos) /*!< TPIU TPIU_FFCR: Reserved2 Mask */
\r
16772 // ------------------------------------- TPIU_TPIU_FSCR -----------------------------------------
\r
16773 #define TPIU_TPIU_FSCR_Reserved_Pos 0 /*!< TPIU TPIU_FSCR: Reserved Position */
\r
16774 #define TPIU_TPIU_FSCR_Reserved_Msk (0xffffffffUL << TPIU_TPIU_FSCR_Reserved_Pos) /*!< TPIU TPIU_FSCR: Reserved Mask */
\r
16776 // -------------------------------------- TPIU_TRIGGER ------------------------------------------
\r
16777 #define TPIU_TRIGGER_TRIGGER_InputValue_Pos 0 /*!< TPIU TRIGGER: TRIGGER_InputValue Position */
\r
16778 #define TPIU_TRIGGER_TRIGGER_InputValue_Msk (0x01UL << TPIU_TRIGGER_TRIGGER_InputValue_Pos) /*!< TPIU TRIGGER: TRIGGER_InputValue Mask */
\r
16779 #define TPIU_TRIGGER_Reserved_Pos 1 /*!< TPIU TRIGGER: Reserved Position */
\r
16780 #define TPIU_TRIGGER_Reserved_Msk (0x7fffffffUL << TPIU_TRIGGER_Reserved_Pos) /*!< TPIU TRIGGER: Reserved Mask */
\r
16782 // ------------------------------------- TPIU_FIFO_Data0 ----------------------------------------
\r
16783 #define TPIU_FIFO_Data0_ETM_Data_0_Pos 0 /*!< TPIU FIFO_Data0: ETM_Data_0 Position */
\r
16784 #define TPIU_FIFO_Data0_ETM_Data_0_Msk (0x000000ffUL << TPIU_FIFO_Data0_ETM_Data_0_Pos) /*!< TPIU FIFO_Data0: ETM_Data_0 Mask */
\r
16785 #define TPIU_FIFO_Data0_ETM_Data_1_Pos 8 /*!< TPIU FIFO_Data0: ETM_Data_1 Position */
\r
16786 #define TPIU_FIFO_Data0_ETM_Data_1_Msk (0x000000ffUL << TPIU_FIFO_Data0_ETM_Data_1_Pos) /*!< TPIU FIFO_Data0: ETM_Data_1 Mask */
\r
16787 #define TPIU_FIFO_Data0_ETM_Data_2_Pos 16 /*!< TPIU FIFO_Data0: ETM_Data_2 Position */
\r
16788 #define TPIU_FIFO_Data0_ETM_Data_2_Msk (0x000000ffUL << TPIU_FIFO_Data0_ETM_Data_2_Pos) /*!< TPIU FIFO_Data0: ETM_Data_2 Mask */
\r
16789 #define TPIU_FIFO_Data0_ETM_ByteCount_Pos 24 /*!< TPIU FIFO_Data0: ETM_ByteCount Position */
\r
16790 #define TPIU_FIFO_Data0_ETM_ByteCount_Msk (0x03UL << TPIU_FIFO_Data0_ETM_ByteCount_Pos) /*!< TPIU FIFO_Data0: ETM_ByteCount Mask */
\r
16791 #define TPIU_FIFO_Data0_ETM_ATVALID_Input_Pos 26 /*!< TPIU FIFO_Data0: ETM_ATVALID_Input Position */
\r
16792 #define TPIU_FIFO_Data0_ETM_ATVALID_Input_Msk (0x01UL << TPIU_FIFO_Data0_ETM_ATVALID_Input_Pos) /*!< TPIU FIFO_Data0: ETM_ATVALID_Input Mask */
\r
16793 #define TPIU_FIFO_Data0_ITM_ByteCount_Pos 27 /*!< TPIU FIFO_Data0: ITM_ByteCount Position */
\r
16794 #define TPIU_FIFO_Data0_ITM_ByteCount_Msk (0x03UL << TPIU_FIFO_Data0_ITM_ByteCount_Pos) /*!< TPIU FIFO_Data0: ITM_ByteCount Mask */
\r
16795 #define TPIU_FIFO_Data0_ITM_ATVALID_Input_Pos 29 /*!< TPIU FIFO_Data0: ITM_ATVALID_Input Position */
\r
16796 #define TPIU_FIFO_Data0_ITM_ATVALID_Input_Msk (0x01UL << TPIU_FIFO_Data0_ITM_ATVALID_Input_Pos) /*!< TPIU FIFO_Data0: ITM_ATVALID_Input Mask */
\r
16797 #define TPIU_FIFO_Data0_Reserved_Pos 30 /*!< TPIU FIFO_Data0: Reserved Position */
\r
16798 #define TPIU_FIFO_Data0_Reserved_Msk (0x03UL << TPIU_FIFO_Data0_Reserved_Pos) /*!< TPIU FIFO_Data0: Reserved Mask */
\r
16800 // ------------------------------------- TPIU_ITATBCTR2 -----------------------------------------
\r
16801 #define TPIU_ITATBCTR2_ATREADY1_ATREADY2_Pos 0 /*!< TPIU ITATBCTR2: ATREADY1_ATREADY2 Position */
\r
16802 #define TPIU_ITATBCTR2_ATREADY1_ATREADY2_Msk (0x01UL << TPIU_ITATBCTR2_ATREADY1_ATREADY2_Pos) /*!< TPIU ITATBCTR2: ATREADY1_ATREADY2 Mask */
\r
16803 #define TPIU_ITATBCTR2_Reserved_Pos 1 /*!< TPIU ITATBCTR2: Reserved Position */
\r
16804 #define TPIU_ITATBCTR2_Reserved_Msk (0x7fffffffUL << TPIU_ITATBCTR2_Reserved_Pos) /*!< TPIU ITATBCTR2: Reserved Mask */
\r
16806 // ------------------------------------- TPIU_ITATBCTR0 -----------------------------------------
\r
16807 #define TPIU_ITATBCTR0_ATVALID1_ATVALID2_Pos 0 /*!< TPIU ITATBCTR0: ATVALID1_ATVALID2 Position */
\r
16808 #define TPIU_ITATBCTR0_ATVALID1_ATVALID2_Msk (0x01UL << TPIU_ITATBCTR0_ATVALID1_ATVALID2_Pos) /*!< TPIU ITATBCTR0: ATVALID1_ATVALID2 Mask */
\r
16809 #define TPIU_ITATBCTR0_Reserved_Pos 1 /*!< TPIU ITATBCTR0: Reserved Position */
\r
16810 #define TPIU_ITATBCTR0_Reserved_Msk (0x7fffffffUL << TPIU_ITATBCTR0_Reserved_Pos) /*!< TPIU ITATBCTR0: Reserved Mask */
\r
16812 // ------------------------------------- TPIU_FIFO_Data1 ----------------------------------------
\r
16813 #define TPIU_FIFO_Data1_ITM_Data_0_Pos 0 /*!< TPIU FIFO_Data1: ITM_Data_0 Position */
\r
16814 #define TPIU_FIFO_Data1_ITM_Data_0_Msk (0x000000ffUL << TPIU_FIFO_Data1_ITM_Data_0_Pos) /*!< TPIU FIFO_Data1: ITM_Data_0 Mask */
\r
16815 #define TPIU_FIFO_Data1_ITM_Data_1_Pos 8 /*!< TPIU FIFO_Data1: ITM_Data_1 Position */
\r
16816 #define TPIU_FIFO_Data1_ITM_Data_1_Msk (0x000000ffUL << TPIU_FIFO_Data1_ITM_Data_1_Pos) /*!< TPIU FIFO_Data1: ITM_Data_1 Mask */
\r
16817 #define TPIU_FIFO_Data1_ITM_Data_2_Pos 16 /*!< TPIU FIFO_Data1: ITM_Data_2 Position */
\r
16818 #define TPIU_FIFO_Data1_ITM_Data_2_Msk (0x000000ffUL << TPIU_FIFO_Data1_ITM_Data_2_Pos) /*!< TPIU FIFO_Data1: ITM_Data_2 Mask */
\r
16819 #define TPIU_FIFO_Data1_ETM_ByteCount_Pos 24 /*!< TPIU FIFO_Data1: ETM_ByteCount Position */
\r
16820 #define TPIU_FIFO_Data1_ETM_ByteCount_Msk (0x03UL << TPIU_FIFO_Data1_ETM_ByteCount_Pos) /*!< TPIU FIFO_Data1: ETM_ByteCount Mask */
\r
16821 #define TPIU_FIFO_Data1_ETM_ATVALID_Input_Pos 26 /*!< TPIU FIFO_Data1: ETM_ATVALID_Input Position */
\r
16822 #define TPIU_FIFO_Data1_ETM_ATVALID_Input_Msk (0x01UL << TPIU_FIFO_Data1_ETM_ATVALID_Input_Pos) /*!< TPIU FIFO_Data1: ETM_ATVALID_Input Mask */
\r
16823 #define TPIU_FIFO_Data1_ITM_ByteCount_Pos 27 /*!< TPIU FIFO_Data1: ITM_ByteCount Position */
\r
16824 #define TPIU_FIFO_Data1_ITM_ByteCount_Msk (0x03UL << TPIU_FIFO_Data1_ITM_ByteCount_Pos) /*!< TPIU FIFO_Data1: ITM_ByteCount Mask */
\r
16825 #define TPIU_FIFO_Data1_ITM_ATVALID_Input_Pos 29 /*!< TPIU FIFO_Data1: ITM_ATVALID_Input Position */
\r
16826 #define TPIU_FIFO_Data1_ITM_ATVALID_Input_Msk (0x01UL << TPIU_FIFO_Data1_ITM_ATVALID_Input_Pos) /*!< TPIU FIFO_Data1: ITM_ATVALID_Input Mask */
\r
16827 #define TPIU_FIFO_Data1_Reserved_Pos 30 /*!< TPIU FIFO_Data1: Reserved Position */
\r
16828 #define TPIU_FIFO_Data1_Reserved_Msk (0x03UL << TPIU_FIFO_Data1_Reserved_Pos) /*!< TPIU FIFO_Data1: Reserved Mask */
\r
16830 // --------------------------------------- TPIU_ITCTRL ------------------------------------------
\r
16831 #define TPIU_ITCTRL_Mode_Pos 0 /*!< TPIU ITCTRL: Mode Position */
\r
16832 #define TPIU_ITCTRL_Mode_Msk (0x03UL << TPIU_ITCTRL_Mode_Pos) /*!< TPIU ITCTRL: Mode Mask */
\r
16833 #define TPIU_ITCTRL_Reserved_Pos 2 /*!< TPIU ITCTRL: Reserved Position */
\r
16834 #define TPIU_ITCTRL_Reserved_Msk (0x3fffffffUL << TPIU_ITCTRL_Reserved_Pos) /*!< TPIU ITCTRL: Reserved Mask */
\r
16836 // -------------------------------------- TPIU_CLAIMSET -----------------------------------------
\r
16837 #define TPIU_CLAIMSET_ClaimTagSet_Pos 0 /*!< TPIU CLAIMSET: ClaimTagSet Position */
\r
16838 #define TPIU_CLAIMSET_ClaimTagSet_Msk (0xffffffffUL << TPIU_CLAIMSET_ClaimTagSet_Pos) /*!< TPIU CLAIMSET: ClaimTagSet Mask */
\r
16840 // -------------------------------------- TPIU_CLAIMCLR -----------------------------------------
\r
16841 #define TPIU_CLAIMCLR_ClaimTagClear_Pos 0 /*!< TPIU CLAIMCLR: ClaimTagClear Position */
\r
16842 #define TPIU_CLAIMCLR_ClaimTagClear_Msk (0xffffffffUL << TPIU_CLAIMCLR_ClaimTagClear_Pos) /*!< TPIU CLAIMCLR: ClaimTagClear Mask */
\r
16844 // --------------------------------------- TPIU_DEVID -------------------------------------------
\r
16845 #define TPIU_DEVID_NumberOfTraceInputs_Pos 0 /*!< TPIU DEVID: NumberOfTraceInputs Position */
\r
16846 #define TPIU_DEVID_NumberOfTraceInputs_Msk (0x1fUL << TPIU_DEVID_NumberOfTraceInputs_Pos) /*!< TPIU DEVID: NumberOfTraceInputs Mask */
\r
16847 #define TPIU_DEVID_AsynchronousTRACECLKIN_Pos 5 /*!< TPIU DEVID: AsynchronousTRACECLKIN Position */
\r
16848 #define TPIU_DEVID_AsynchronousTRACECLKIN_Msk (0x01UL << TPIU_DEVID_AsynchronousTRACECLKIN_Pos) /*!< TPIU DEVID: AsynchronousTRACECLKIN Mask */
\r
16849 #define TPIU_DEVID_MinimumBufferSize_Pos 6 /*!< TPIU DEVID: MinimumBufferSize Position */
\r
16850 #define TPIU_DEVID_MinimumBufferSize_Msk (0x07UL << TPIU_DEVID_MinimumBufferSize_Pos) /*!< TPIU DEVID: MinimumBufferSize Mask */
\r
16851 #define TPIU_DEVID_ParallelTracePortMode_Pos 9 /*!< TPIU DEVID: ParallelTracePortMode Position */
\r
16852 #define TPIU_DEVID_ParallelTracePortMode_Msk (0x01UL << TPIU_DEVID_ParallelTracePortMode_Pos) /*!< TPIU DEVID: ParallelTracePortMode Mask */
\r
16853 #define TPIU_DEVID_AsynchronousSerialWireOutput_Manchester_Pos10 /*!< TPIU DEVID: AsynchronousSerialWireOutput_Manchester Position */
\r
16854 #define TPIU_DEVID_AsynchronousSerialWireOutput_Manchester_Msk (0x01UL << TPIU_DEVID_AsynchronousSerialWireOutput_Manchester_Pos)/*!< TPIU DEVID: AsynchronousSerialWireOutput_Manchester Mask */
\r
16855 #define TPIU_DEVID_AsynchronousSerialWireOutput_NRZ_Pos 11 /*!< TPIU DEVID: AsynchronousSerialWireOutput_NRZ Position */
\r
16856 #define TPIU_DEVID_AsynchronousSerialWireOutput_NRZ_Msk (0x01UL << TPIU_DEVID_AsynchronousSerialWireOutput_NRZ_Pos)/*!< TPIU DEVID: AsynchronousSerialWireOutput_NRZ Mask */
\r
16857 #define TPIU_DEVID_Reserved_Pos 12 /*!< TPIU DEVID: Reserved Position */
\r
16858 #define TPIU_DEVID_Reserved_Msk (0x000fffffUL << TPIU_DEVID_Reserved_Pos) /*!< TPIU DEVID: Reserved Mask */
\r
16860 // -------------------------------------- TPIU_DEVTYPE ------------------------------------------
\r
16861 #define TPIU_DEVTYPE_MajorType_Pos 0 /*!< TPIU DEVTYPE: MajorType Position */
\r
16862 #define TPIU_DEVTYPE_MajorType_Msk (0x0fUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */
\r
16863 #define TPIU_DEVTYPE_SubType_Pos 4 /*!< TPIU DEVTYPE: SubType Position */
\r
16864 #define TPIU_DEVTYPE_SubType_Msk (0x0fUL << TPIU_DEVTYPE_SubType_Pos) /*!< TPIU DEVTYPE: SubType Mask */
\r
16865 #define TPIU_DEVTYPE_Reserved_Pos 8 /*!< TPIU DEVTYPE: Reserved Position */
\r
16866 #define TPIU_DEVTYPE_Reserved_Msk (0x00ffffffUL << TPIU_DEVTYPE_Reserved_Pos) /*!< TPIU DEVTYPE: Reserved Mask */
\r
16868 // -------------------------------------- TPIU_TPIUPID4 -----------------------------------------
\r
16869 #define TPIU_TPIUPID4_PID4_Pos 0 /*!< TPIU TPIUPID4: PID4 Position */
\r
16870 #define TPIU_TPIUPID4_PID4_Msk (0xffffffffUL << TPIU_TPIUPID4_PID4_Pos) /*!< TPIU TPIUPID4: PID4 Mask */
\r
16872 // -------------------------------------- TPIU_TPIUPID5 -----------------------------------------
\r
16873 #define TPIU_TPIUPID5_PID5_Pos 0 /*!< TPIU TPIUPID5: PID5 Position */
\r
16874 #define TPIU_TPIUPID5_PID5_Msk (0xffffffffUL << TPIU_TPIUPID5_PID5_Pos) /*!< TPIU TPIUPID5: PID5 Mask */
\r
16876 // -------------------------------------- TPIU_TPIUPID6 -----------------------------------------
\r
16877 #define TPIU_TPIUPID6_PID6_Pos 0 /*!< TPIU TPIUPID6: PID6 Position */
\r
16878 #define TPIU_TPIUPID6_PID6_Msk (0xffffffffUL << TPIU_TPIUPID6_PID6_Pos) /*!< TPIU TPIUPID6: PID6 Mask */
\r
16880 // -------------------------------------- TPIU_TPIUPID7 -----------------------------------------
\r
16881 #define TPIU_TPIUPID7_PID7_Pos 0 /*!< TPIU TPIUPID7: PID7 Position */
\r
16882 #define TPIU_TPIUPID7_PID7_Msk (0xffffffffUL << TPIU_TPIUPID7_PID7_Pos) /*!< TPIU TPIUPID7: PID7 Mask */
\r
16884 // -------------------------------------- TPIU_TPIUPID0 -----------------------------------------
\r
16885 #define TPIU_TPIUPID0_PID0_Pos 0 /*!< TPIU TPIUPID0: PID0 Position */
\r
16886 #define TPIU_TPIUPID0_PID0_Msk (0xffffffffUL << TPIU_TPIUPID0_PID0_Pos) /*!< TPIU TPIUPID0: PID0 Mask */
\r
16888 // -------------------------------------- TPIU_TPIUPID1 -----------------------------------------
\r
16889 #define TPIU_TPIUPID1_PID1_Pos 0 /*!< TPIU TPIUPID1: PID1 Position */
\r
16890 #define TPIU_TPIUPID1_PID1_Msk (0xffffffffUL << TPIU_TPIUPID1_PID1_Pos) /*!< TPIU TPIUPID1: PID1 Mask */
\r
16892 // -------------------------------------- TPIU_TPIUPID2 -----------------------------------------
\r
16893 #define TPIU_TPIUPID2_PID2_Pos 0 /*!< TPIU TPIUPID2: PID2 Position */
\r
16894 #define TPIU_TPIUPID2_PID2_Msk (0xffffffffUL << TPIU_TPIUPID2_PID2_Pos) /*!< TPIU TPIUPID2: PID2 Mask */
\r
16896 // -------------------------------------- TPIU_TPIUPID3 -----------------------------------------
\r
16897 #define TPIU_TPIUPID3_PID3_Pos 0 /*!< TPIU TPIUPID3: PID3 Position */
\r
16898 #define TPIU_TPIUPID3_PID3_Msk (0xffffffffUL << TPIU_TPIUPID3_PID3_Pos) /*!< TPIU TPIUPID3: PID3 Mask */
\r
16900 // -------------------------------------- TPIU_TPIUCID0 -----------------------------------------
\r
16901 #define TPIU_TPIUCID0_CID0_Pos 0 /*!< TPIU TPIUCID0: CID0 Position */
\r
16902 #define TPIU_TPIUCID0_CID0_Msk (0xffffffffUL << TPIU_TPIUCID0_CID0_Pos) /*!< TPIU TPIUCID0: CID0 Mask */
\r
16904 // -------------------------------------- TPIU_TPIUCID1 -----------------------------------------
\r
16905 #define TPIU_TPIUCID1_CID1_Pos 0 /*!< TPIU TPIUCID1: CID1 Position */
\r
16906 #define TPIU_TPIUCID1_CID1_Msk (0xffffffffUL << TPIU_TPIUCID1_CID1_Pos) /*!< TPIU TPIUCID1: CID1 Mask */
\r
16908 // -------------------------------------- TPIU_TPIUCID2 -----------------------------------------
\r
16909 #define TPIU_TPIUCID2_CID2_Pos 0 /*!< TPIU TPIUCID2: CID2 Position */
\r
16910 #define TPIU_TPIUCID2_CID2_Msk (0xffffffffUL << TPIU_TPIUCID2_CID2_Pos) /*!< TPIU TPIUCID2: CID2 Mask */
\r
16912 // -------------------------------------- TPIU_TPIUCID3 -----------------------------------------
\r
16913 #define TPIU_TPIUCID3_CID3_Pos 0 /*!< TPIU TPIUCID3: CID3 Position */
\r
16914 #define TPIU_TPIUCID3_CID3_Msk (0xffffffffUL << TPIU_TPIUCID3_CID3_Pos) /*!< TPIU TPIUCID3: CID3 Mask */
\r
16917 /*** USB0 Bit Fileds *******************/
\r
16918 /***************************************************************************/
\r
16921 /* USB_GOTGCTL = Control and Status Register*/
\r
16922 #define USB_GOTGCTL_SesReqScs_Pos (0U)
\r
16923 #define USB_GOTGCTL_SesReqScs_Msk (0x00000001U << USB_GOTGCTL_SesReqScs_Pos)
\r
16925 #define USB_GOTGCTL_SesReq_Pos (1U)
\r
16926 #define USB_GOTGCTL_SesReq_Msk (0x00000001U << USB_GOTGCTL_SesReq_Pos)
\r
16928 #define USB_GOTGCTL_VbvalidOvEn_Pos (2U)
\r
16929 #define USB_GOTGCTL_VbvalidOvEn_Msk (0x00000001U << USB_GOTGCTL_VbvalidOvEn_Pos)
\r
16931 #define USB_GOTGCTL_VbvalidOvVal_Pos (3U)
\r
16932 #define USB_GOTGCTL_VbvalidOvVal_Msk (0x00000001U << USB_GOTGCTL_VbvalidOvVal_Pos)
\r
16934 #define USB_GOTGCTL_AvalidOvEn_Pos (4U)
\r
16935 #define USB_GOTGCTL_AvalidOvEn_Msk (0x00000001U << USB_GOTGCTL_AvalidOvEn_Pos)
\r
16937 #define USB_GOTGCTL_AvalidOvVal_Pos (5U)
\r
16938 #define USB_GOTGCTL_AvalidOvVal_Msk (0x00000001U << USB_GOTGCTL_AvalidOvVal_Pos)
\r
16940 #define USB_GOTGCTL_BvalidOvEn_Pos (6U)
\r
16941 #define USB_GOTGCTL_BvalidOvEn_Msk (0x00000001U << USB_GOTGCTL_BvalidOvEn_Pos)
\r
16943 #define USB_GOTGCTL_BvalidOvVal_Pos (7U)
\r
16944 #define USB_GOTGCTL_BvalidOvVal_Msk (0x00000001U << USB_GOTGCTL_BvalidOvVal_Pos)
\r
16946 #define USB_GOTGCTL_HstNegScs_Pos (8U)
\r
16947 #define USB_GOTGCTL_HstNegScs_Msk (0x00000001U << USB_GOTGCTL_HstNegScs_Pos)
\r
16949 #define USB_GOTGCTL_HNPReq_Pos (9U)
\r
16950 #define USB_GOTGCTL_HNPReq_Msk (0x00000001U << USB_GOTGCTL_HNPReq_Pos)
\r
16952 #define USB_GOTGCTL_HstSetHNPEn_Pos (10U)
\r
16953 #define USB_GOTGCTL_HstSetHNPEn_Msk (0x00000001U << USB_GOTGCTL_HstSetHNPEn_Pos)
\r
16955 #define USB_GOTGCTL_DevHNPEn_Pos (11U)
\r
16956 #define USB_GOTGCTL_DevHNPEn_Msk (0x00000001U << USB_GOTGCTL_DevHNPEn_Pos)
\r
16958 #define USB_GOTGCTL_ConlDSts_Pos (16U)
\r
16959 #define USB_GOTGCTL_ConlDSts_Msk (0x00000001U << USB_GOTGCTL_ConlDSts_Pos)
\r
16961 #define USB_GOTGCTL_DbncTime_Pos (17U)
\r
16962 #define USB_GOTGCTL_DbncTime_Msk (0x00000001U << USB_GOTGCTL_DbncTime_Pos)
\r
16964 #define USB_GOTGCTL_ASesVId_Pos (18U)
\r
16965 #define USB_GOTGCTL_ASesVId_Msk (0x00000001U << USB_GOTGCTL_ASesVId_Pos)
\r
16967 #define USB_GOTGCTL_BSesVld_Pos (19U)
\r
16968 #define USB_GOTGCTL_BSesVld_Msk (0x00000001U << USB_GOTGCTL_BSesVld_Pos)
\r
16970 #define USB_GOTGCTL_OTGVer_Pos (20U)
\r
16971 #define USB_GOTGCTL_OTGVer_Msk (0x00000001U << USB_GOTGCTL_OTGVer_Pos)
\r
16973 /* USB_GOTGINT = OTG Interrupt Register*/
\r
16974 #define USB_GOTGINT_DbnceDone_Pos (19U)
\r
16975 #define USB_GOTGINT_DbnceDone_Msk (0x00000001U << USB_GOTGINT_DbnceDone_Pos)
\r
16977 #define USB_GOTGINT_ADevTOUTChg_Pos (18U)
\r
16978 #define USB_GOTGINT_ADevTOUTChg_Msk (0x00000001U << USB_GOTGINT_ADevTOUTChg_Pos)
\r
16980 #define USB_GOTGINT_HstNegDet_Pos (17U)
\r
16981 #define USB_GOTGINT_HstNegDet_Msk (0x00000001U << USB_GOTGINT_HstNegDet_Pos)
\r
16983 #define USB_GOTGINT_HstNegSucStsChng_Pos (9U)
\r
16984 #define USB_GOTGINT_HstNegSucStsChng_Msk (0x00000001U << USB_GOTGINT_HstNegSucStsChng_Pos)
\r
16986 #define USB_GOTGINT_SesReqSucStsChng_Pos (8U)
\r
16987 #define USB_GOTGINT_SesReqSucStsChng_Msk (0x00000001U << USB_GOTGINT_SesReqSucStsChng_Pos)
\r
16989 #define USB_GOTGINT_SesEndDet_Pos (2U)
\r
16990 #define USB_GOTGINT_SesEndDet_Msk (0x00000001U << USB_GOTGINT_SesEndDet_Pos)
\r
16992 /* USB_GAHBCFG = AHB Configuration Register*/
\r
16993 #define USB_GAHBCFG_NotiAllDmaWrit_Pos (22U)
\r
16994 #define USB_GAHBCFG_NotiAllDmaWrit_Msk (0x00000001U << USB_GAHBCFG_NotiAllDmaWrit_Pos)
\r
16996 #define USB_GAHBCFG_RemMemSupp_Pos (21U)
\r
16997 #define USB_GAHBCFG_RemMemSupp_Msk (0x00000001U << USB_GAHBCFG_RemMemSupp_Pos)
\r
16999 #define USB_GAHBCFG_PTxFEmpLvl_Pos (8U)
\r
17000 #define USB_GAHBCFG_PTxFEmpLvl_Msk (0x00000001U << USB_GAHBCFG_PTxFEmpLvl_Pos)
\r
17002 #define USB_GAHBCFG_NPTxFEmpLvl_Pos (7U)
\r
17003 #define USB_GAHBCFG_NPTxFEmpLvl_Msk (0x00000001U << USB_GAHBCFG_NPTxFEmpLvl_Pos)
\r
17005 #define USB_GAHBCFG_DMAEn_Pos (5U)
\r
17006 #define USB_GAHBCFG_DMAEn_Msk (0x00000001U << USB_GAHBCFG_DMAEn_Pos)
\r
17008 #define USB_GAHBCFG_HBstLen_Pos (1U)
\r
17009 #define USB_GAHBCFG_HBstLen_Msk (0x0000000FU << USB_GAHBCFG_HBstLen_Pos)
\r
17011 #define USB_GAHBCFG_GlblIntrMsk_Pos (0U)
\r
17012 #define USB_GAHBCFG_GlblIntrMsk_Msk (0x00000001U << USB_GAHBCFG_GlblIntrMsk_Pos)
\r
17014 /* USB_GUSBCFG = USB Configuration Register*/
\r
17015 #define USB_GUSBCFG_CTP_Pos (31U)
\r
17016 #define USB_GUSBCFG_CTP_Msk (0x00000001U << USB_GUSBCFG_CTP_Pos)
\r
17018 #define USB_GUSBCFG_ForceDevMode_Pos (30U)
\r
17019 #define USB_GUSBCFG_ForceDevMode_Msk (0x00000001U << USB_GUSBCFG_ForceDevMode_Pos)
\r
17021 #define USB_GUSBCFG_ForceHstMode_Pos (29U)
\r
17022 #define USB_GUSBCFG_ForceHstMode_Msk (0x00000001U << USB_GUSBCFG_ForceHstMode_Pos)
\r
17024 #define USB_GUSBCFG_TxEndDela_Pos (28U)
\r
17025 #define USB_GUSBCFG_TxEndDela_Msk (0x00000001U << USB_GUSBCFG_TxEndDela_Pos)
\r
17027 #define USB_GUSBCFG_OtgI2CSel_Pos (16U)
\r
17028 #define USB_GUSBCFG_OtgI2CSel_Msk (0x00000001U << USB_GUSBCFG_OtgI2CSel_Pos)
\r
17030 #define USB_GUSBCFG_USBTrdTim_Pos (10U)
\r
17031 #define USB_GUSBCFG_USBTrdTim_Msk (0x0000000FU << USB_GUSBCFG_USBTrdTim_Pos)
\r
17033 #define USB_GUSBCFG_HNPCap_Pos (9U)
\r
17034 #define USB_GUSBCFG_HNPCap_Msk (0x00000001U << USB_GUSBCFG_HNPCap_Pos)
\r
17036 #define USB_GUSBCFG_SRPCap_Pos (8U)
\r
17037 #define USB_GUSBCFG_SRPCap_Msk (0x00000001U << USB_GUSBCFG_SRPCap_Pos)
\r
17039 #define USB_GUSBCFG_PHYSel_Pos (6U)
\r
17040 #define USB_GUSBCFG_PHYSel_Msk (0x00000001U << USB_GUSBCFG_PHYSel_Pos)
\r
17042 #define USB_GUSBCFG_FSIntf_Pos (5U)
\r
17043 #define USB_GUSBCFG_FSIntf_Msk (0x00000001U << USB_GUSBCFG_FSIntf_Pos)
\r
17045 #define USB_GUSBCFG_PHYIf_Pos (3U)
\r
17046 #define USB_GUSBCFG_PHYIf_Msk (0x00000001U << USB_GUSBCFG_PHYIf_Pos)
\r
17048 #define USB_GUSBCFG_TOutCal_Pos (0U)
\r
17049 #define USB_GUSBCFG_TOutCal_Msk (0x00000007U << USB_GUSBCFG_TOutCal_Pos)
\r
17051 /* USB_GRSTCTL = Reset Register*/
\r
17052 #define USB_GRSTCTL_AHBIdle_Pos (31U)
\r
17053 #define USB_GRSTCTL_AHBIdle_Msk (0x00000001U << USB_GRSTCTL_AHBIdle_Pos)
\r
17055 #define USB_GRSTCTL_DMAReq_Pos (30U)
\r
17056 #define USB_GRSTCTL_DMAReq_Msk (0x00000001U << USB_GRSTCTL_DMAReq_Pos)
\r
17058 #define USB_GRSTCTL_TxFNum_Pos (6U)
\r
17059 #define USB_GRSTCTL_TxFNum_Msk (0x0000001FU << USB_GRSTCTL_TxFNum_Pos)
\r
17061 #define USB_GRSTCTL_TxFFlsh_Pos (5U)
\r
17062 #define USB_GRSTCTL_TxFFlsh_Msk (0x00000001U << USB_GRSTCTL_TxFFlsh_Pos)
\r
17064 #define USB_GRSTCTL_RxFFlsh_Pos (4U)
\r
17065 #define USB_GRSTCTL_RxFFlsh_Msk (0x00000001U << USB_GRSTCTL_RxFFlsh_Pos)
\r
17067 #define USB_GRSTCTL_FrmCntrRst_Pos (2U)
\r
17068 #define USB_GRSTCTL_FrmCntrRst_Msk (0x00000001U << USB_GRSTCTL_FrmCntrRst_Pos)
\r
17070 #define USB_GRSTCTL_CSftRst_Pos (0U)
\r
17071 #define USB_GRSTCTL_CSftRst_Msk (0x00000001U << USB_GRSTCTL_CSftRst_Pos)
\r
17073 /* USB_GINTSTS_HOSTMODE = Interrupt Register [Host Mode]*/
\r
17074 #define USB_GINTSTS_HOSTMODE_WkUpInt_Pos (31U)
\r
17075 #define USB_GINTSTS_HOSTMODE_WkUpInt_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_WkUpInt_Pos)
\r
17077 #define USB_GINTSTS_HOSTMODE_SessReqInt_Pos (30U)
\r
17078 #define USB_GINTSTS_HOSTMODE_SessReqInt_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_SessReqInt_Pos)
\r
17080 #define USB_GINTSTS_HOSTMODE_DisconnInt_Pos (29U)
\r
17081 #define USB_GINTSTS_HOSTMODE_DisconnInt_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_DisconnInt_Pos)
\r
17083 #define USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos (28U)
\r
17084 #define USB_GINTSTS_HOSTMODE_ConIDStsChng_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos)
\r
17086 #define USB_GINTSTS_HOSTMODE_PTxFEmp_Pos (26U)
\r
17087 #define USB_GINTSTS_HOSTMODE_PTxFEmp_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_PTxFEmp_Pos)
\r
17089 #define USB_GINTSTS_HOSTMODE_HChInt_Pos (25U)
\r
17090 #define USB_GINTSTS_HOSTMODE_HChInt_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_HChInt_Pos)
\r
17092 #define USB_GINTSTS_HOSTMODE_PrtInt_Pos (24U)
\r
17093 #define USB_GINTSTS_HOSTMODE_PrtInt_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_PrtInt_Pos)
\r
17095 #define USB_GINTSTS_HOSTMODE_incomplP_Pos (21U)
\r
17096 #define USB_GINTSTS_HOSTMODE_incomplP_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_incomplP_Pos)
\r
17098 #define USB_GINTSTS_HOSTMODE_RxFLvl_Pos (4U)
\r
17099 #define USB_GINTSTS_HOSTMODE_RxFLvl_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_RxFLvl_Pos)
\r
17101 #define USB_GINTSTS_HOSTMODE_Sof_Pos (3U)
\r
17102 #define USB_GINTSTS_HOSTMODE_Sof_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_Sof_Pos)
\r
17104 #define USB_GINTSTS_HOSTMODE_OTGInt_Pos (2U)
\r
17105 #define USB_GINTSTS_HOSTMODE_OTGInt_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_OTGInt_Pos)
\r
17107 #define USB_GINTSTS_HOSTMODE_ModeMis_Pos (1U)
\r
17108 #define USB_GINTSTS_HOSTMODE_ModeMis_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_ModeMis_Pos)
\r
17110 #define USB_GINTSTS_HOSTMODE_CurMod_Pos (0U)
\r
17111 #define USB_GINTSTS_HOSTMODE_CurMod_Msk (0x00000001U << USB_GINTSTS_HOSTMODE_CurMod_Pos)
\r
17113 /* USB_GINTSTS_DEVICEMODE = Interrupt Register [Device Mode]*/
\r
17114 #define USB_GINTSTS_DEVICEMODE_WkUpInt_Pos (31U)
\r
17115 #define USB_GINTSTS_DEVICEMODE_WkUpInt_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_WkUpInt_Pos)
\r
17117 #define USB_GINTSTS_DEVICEMODE_SessReqInt_Pos (30U)
\r
17118 #define USB_GINTSTS_DEVICEMODE_SessReqInt_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_SessReqInt_Pos)
\r
17120 #define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos (28U)
\r
17121 #define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos)
\r
17123 #define USB_GINTSTS_DEVICEMODE_ResetDet_Pos (23U)
\r
17124 #define USB_GINTSTS_DEVICEMODE_ResetDet_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_ResetDet_Pos)
\r
17126 #define USB_GINTSTS_DEVICEMODE_FetSusp_Pos (22U)
\r
17127 #define USB_GINTSTS_DEVICEMODE_FetSusp_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_FetSusp_Pos)
\r
17129 #define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos (21U)
\r
17130 #define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos)
\r
17132 #define USB_GINTSTS_DEVICEMODE_incompISOIN_Pos (20U)
\r
17133 #define USB_GINTSTS_DEVICEMODE_incompISOIN_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_incompISOIN_Pos)
\r
17135 #define USB_GINTSTS_DEVICEMODE_OEPInt_Pos (19U)
\r
17136 #define USB_GINTSTS_DEVICEMODE_OEPInt_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_OEPInt_Pos)
\r
17138 #define USB_GINTSTS_DEVICEMODE_IEPInt_Pos (18U)
\r
17139 #define USB_GINTSTS_DEVICEMODE_IEPInt_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_IEPInt_Pos)
\r
17141 #define USB_GINTSTS_DEVICEMODE_EOPF_Pos (15U)
\r
17142 #define USB_GINTSTS_DEVICEMODE_EOPF_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_EOPF_Pos)
\r
17144 #define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos (14U)
\r
17145 #define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos)
\r
17147 #define USB_GINTSTS_DEVICEMODE_EnumDone_Pos (13U)
\r
17148 #define USB_GINTSTS_DEVICEMODE_EnumDone_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_EnumDone_Pos)
\r
17150 #define USB_GINTSTS_DEVICEMODE_USBRst_Pos (12U)
\r
17151 #define USB_GINTSTS_DEVICEMODE_USBRst_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_USBRst_Pos)
\r
17153 #define USB_GINTSTS_DEVICEMODE_USBSusp_Pos (11U)
\r
17154 #define USB_GINTSTS_DEVICEMODE_USBSusp_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_USBSusp_Pos)
\r
17156 #define USB_GINTSTS_DEVICEMODE_ErlySusp_Pos (10U)
\r
17157 #define USB_GINTSTS_DEVICEMODE_ErlySusp_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_ErlySusp_Pos)
\r
17159 #define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos (7U)
\r
17160 #define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos)
\r
17162 #define USB_GINTSTS_DEVICEMODE_GINNakEff_Pos (6U)
\r
17163 #define USB_GINTSTS_DEVICEMODE_GINNakEff_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_GINNakEff_Pos)
\r
17165 #define USB_GINTSTS_DEVICEMODE_RxFLvl_Pos (4U)
\r
17166 #define USB_GINTSTS_DEVICEMODE_RxFLvl_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_RxFLvl_Pos)
\r
17168 #define USB_GINTSTS_DEVICEMODE_Sof_Pos (3U)
\r
17169 #define USB_GINTSTS_DEVICEMODE_Sof_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_Sof_Pos)
\r
17171 #define USB_GINTSTS_DEVICEMODE_OTGInt_Pos (2U)
\r
17172 #define USB_GINTSTS_DEVICEMODE_OTGInt_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_OTGInt_Pos)
\r
17174 #define USB_GINTSTS_DEVICEMODE_ModeMis_Pos (1U)
\r
17175 #define USB_GINTSTS_DEVICEMODE_ModeMis_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_ModeMis_Pos)
\r
17177 #define USB_GINTSTS_DEVICEMODE_CurMod_Pos (0U)
\r
17178 #define USB_GINTSTS_DEVICEMODE_CurMod_Msk (0x00000001U << USB_GINTSTS_DEVICEMODE_CurMod_Pos)
\r
17180 /* USB_GINTMSK_HOSTMODE = Interrupt Mask Register [Host Mode]*/
\r
17181 #define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos (31U)
\r
17182 #define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk (0x00000001U << USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos)
\r
17184 #define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos (30U)
\r
17185 #define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Msk (0x00000001U << USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos)
\r
17187 #define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos (29U)
\r
17188 #define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Msk (0x00000001U << USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos)
\r
17190 #define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos (28U)
\r
17191 #define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Msk (0x00000001U << USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos)
\r
17193 #define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos (26U)
\r
17194 #define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Msk (0x00000001U << USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos)
\r
17196 #define USB_GINTMSK_HOSTMODE_HChIntMsk_Pos (25U)
\r
17197 #define USB_GINTMSK_HOSTMODE_HChIntMsk_Msk (0x00000001U << USB_GINTMSK_HOSTMODE_HChIntMsk_Pos)
\r
17199 #define USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos (24U)
\r
17200 #define USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk (0x00000001U << USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos)
\r
17202 #define USB_GINTMSK_HOSTMODE_incomplPMsk_Pos (21U)
\r
17203 #define USB_GINTMSK_HOSTMODE_incomplPMsk_Msk (0x00000001U << USB_GINTMSK_HOSTMODE_incomplPMsk_Pos)
\r
17205 #define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos (4U)
\r
17206 #define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk (0x00000001U << USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos)
\r
17208 #define USB_GINTMSK_HOSTMODE_SofMsk_Pos (3U)
\r
17209 #define USB_GINTMSK_HOSTMODE_SofMsk_Msk (0x00000001U << USB_GINTMSK_HOSTMODE_SofMsk_Pos)
\r
17211 #define USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos (2U)
\r
17212 #define USB_GINTMSK_HOSTMODE_OTGIntMsk_Msk (0x00000001U << USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos)
\r
17214 #define USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos (1U)
\r
17215 #define USB_GINTMSK_HOSTMODE_ModeMisMsk_Msk (0x00000001U << USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos)
\r
17217 /* USB_GINTMSK_DEVICEMODE = Interrupt Mask Register [Device Mode]*/
\r
17218 #define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos (31U)
\r
17219 #define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos)
\r
17221 #define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos (30U)
\r
17222 #define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos)
\r
17224 #define USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Pos (29U)
\r
17225 #define USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Pos)
\r
17227 #define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos (28U)
\r
17228 #define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos)
\r
17230 #define USB_GINTMSK_DEVICEMODE_ResetDetMsk_Pos (23U)
\r
17231 #define USB_GINTMSK_DEVICEMODE_ResetDetMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_ResetDetMsk_Pos)
\r
17233 #define USB_GINTMSK_DEVICEMODE_FetSuspMsk_Pos (22U)
\r
17234 #define USB_GINTMSK_DEVICEMODE_FetSuspMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_FetSuspMsk_Pos)
\r
17236 #define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos (21U)
\r
17237 #define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos)
\r
17239 #define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos (20U)
\r
17240 #define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos)
\r
17242 #define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos (19U)
\r
17243 #define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos)
\r
17245 #define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos (18U)
\r
17246 #define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos)
\r
17248 #define USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos (15U)
\r
17249 #define USB_GINTMSK_DEVICEMODE_EOPFMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos)
\r
17251 #define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos (14U)
\r
17252 #define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos)
\r
17254 #define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos (13U)
\r
17255 #define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos)
\r
17257 #define USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos (12U)
\r
17258 #define USB_GINTMSK_DEVICEMODE_USBRstMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos)
\r
17260 #define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos (11U)
\r
17261 #define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos)
\r
17263 #define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos (10U)
\r
17264 #define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos)
\r
17266 #define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos (7U)
\r
17267 #define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos)
\r
17269 #define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos (6U)
\r
17270 #define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos)
\r
17272 #define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos (4U)
\r
17273 #define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos)
\r
17275 #define USB_GINTMSK_DEVICEMODE_SofMsk_Pos (3U)
\r
17276 #define USB_GINTMSK_DEVICEMODE_SofMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_SofMsk_Pos)
\r
17278 #define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos (2U)
\r
17279 #define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos)
\r
17281 #define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos (1U)
\r
17282 #define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Msk (0x00000001U << USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos)
\r
17284 /* USB_GRXSTSR_HOSTMODE = Receive Status Debug Read Register [Host Mode]*/
\r
17285 #define USB_GRXSTSR_HOSTMODE_PktSts_Pos (17U)
\r
17286 #define USB_GRXSTSR_HOSTMODE_PktSts_Msk (0x0000000FU << USB_GRXSTSR_HOSTMODE_PktSts_Pos)
\r
17288 #define USB_GRXSTSR_HOSTMODE_DPID_Pos (15U)
\r
17289 #define USB_GRXSTSR_HOSTMODE_DPID_Msk (0x00000003U << USB_GRXSTSR_HOSTMODE_DPID_Pos)
\r
17291 #define USB_GRXSTSR_HOSTMODE_BCnt_Pos (4U)
\r
17292 #define USB_GRXSTSR_HOSTMODE_BCnt_Msk (0x000007FFU << USB_GRXSTSR_HOSTMODE_BCnt_Pos)
\r
17294 #define USB_GRXSTSR_HOSTMODE_ChNum_Pos (0U)
\r
17295 #define USB_GRXSTSR_HOSTMODE_ChNum_Msk (0x0000000FU << USB_GRXSTSR_HOSTMODE_ChNum_Pos)
\r
17297 /* USB_GRXSTSR_DEVICEMODE = Receive Status Debug Read Register [Device Mode]*/
\r
17298 #define USB_GRXSTSR_DEVICEMODE_FN_Pos (21U)
\r
17299 #define USB_GRXSTSR_DEVICEMODE_FN_Msk (0x0000000FU << USB_GRXSTSR_DEVICEMODE_FN_Pos)
\r
17301 #define USB_GRXSTSR_DEVICEMODE_PktSts_Pos (17U)
\r
17302 #define USB_GRXSTSR_DEVICEMODE_PktSts_Msk (0x0000000FU << USB_GRXSTSR_DEVICEMODE_PktSts_Pos)
\r
17304 #define USB_GRXSTSR_DEVICEMODE_DPID_Pos (15U)
\r
17305 #define USB_GRXSTSR_DEVICEMODE_DPID_Msk (0x00000003U << USB_GRXSTSR_DEVICEMODE_DPID_Pos)
\r
17307 #define USB_GRXSTSR_DEVICEMODE_BCnt_Pos (4U)
\r
17308 #define USB_GRXSTSR_DEVICEMODE_BCnt_Msk (0x000007FFU << USB_GRXSTSR_DEVICEMODE_BCnt_Pos)
\r
17310 #define USB_GRXSTSR_DEVICEMODE_EPNum_Pos (0U)
\r
17311 #define USB_GRXSTSR_DEVICEMODE_EPNum_Msk (0x0000000FU << USB_GRXSTSR_DEVICEMODE_EPNum_Pos)
\r
17313 /* USB_GRXSTSP_HOSTMODE = Receive Status Read and Pop Register [Host Mode]*/
\r
17314 #define USB_GRXSTSP_HOSTMODE_PktSts_Pos (17U)
\r
17315 #define USB_GRXSTSP_HOSTMODE_PktSts_Msk (0x0000000FU << USB_GRXSTSP_HOSTMODE_PktSts_Pos)
\r
17317 #define USB_GRXSTSP_HOSTMODE_DPID_Pos (15U)
\r
17318 #define USB_GRXSTSP_HOSTMODE_DPID_Msk (0x00000003U << USB_GRXSTSP_HOSTMODE_DPID_Pos)
\r
17320 #define USB_GRXSTSP_HOSTMODE_BCnt_Pos (4U)
\r
17321 #define USB_GRXSTSP_HOSTMODE_BCnt_Msk (0x000007FFU << USB_GRXSTSP_HOSTMODE_BCnt_Pos)
\r
17323 #define USB_GRXSTSP_HOSTMODE_ChNum_Pos (0U)
\r
17324 #define USB_GRXSTSP_HOSTMODE_ChNum_Msk (0x0000000FU << USB_GRXSTSP_HOSTMODE_ChNum_Pos)
\r
17326 /* USB_GRXSTSP_DEVICEMODE = Receive Status Read and Pop Register [Device Mode]*/
\r
17327 #define USB_GRXSTSP_DEVICEMODE_FN_Pos (21U)
\r
17328 #define USB_GRXSTSP_DEVICEMODE_FN_Msk (0x0000000FU << USB_GRXSTSP_DEVICEMODE_FN_Pos)
\r
17330 #define USB_GRXSTSP_DEVICEMODE_PktSts_Pos (17U)
\r
17331 #define USB_GRXSTSP_DEVICEMODE_PktSts_Msk (0x0000000FU << USB_GRXSTSP_DEVICEMODE_PktSts_Pos)
\r
17333 #define USB_GRXSTSP_DEVICEMODE_DPID_Pos (15U)
\r
17334 #define USB_GRXSTSP_DEVICEMODE_DPID_Msk (0x00000003U << USB_GRXSTSP_DEVICEMODE_DPID_Pos)
\r
17336 #define USB_GRXSTSP_DEVICEMODE_BCnt_Pos (4U)
\r
17337 #define USB_GRXSTSP_DEVICEMODE_BCnt_Msk (0x000007FFU << USB_GRXSTSP_DEVICEMODE_BCnt_Pos)
\r
17339 #define USB_GRXSTSP_DEVICEMODE_EPNum_Pos (0U)
\r
17340 #define USB_GRXSTSP_DEVICEMODE_EPNum_Msk (0x0000000FU << USB_GRXSTSP_DEVICEMODE_EPNum_Pos)
\r
17342 /* USB_GRXFSIZ = Receive FIFO Size Register*/
\r
17343 #define USB_GRXFSIZ_RxFDep_Pos (0U)
\r
17344 #define USB_GRXFSIZ_RxFDep_Msk (0x0000FFFFU << USB_GRXFSIZ_RxFDep_Pos)
\r
17346 /* USB_GNPTXFSIZ_HOSTMODE = Non-Periodic Transmit FIFO Size Register [Host Mode]*/
\r
17347 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos (16U)
\r
17348 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Msk (0x0000FFFFU << USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos)
\r
17350 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos (0U)
\r
17351 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Msk (0x0000FFFFU << USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos)
\r
17353 /* USB_GNPTXFSIZ_DEVICEMODE = Non-Periodic Transmit FIFO Size Register [Device Mode]*/
\r
17354 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos (16U)
\r
17355 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Msk (0x0000FFFFU << USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos)
\r
17357 /* USB_GNPTXSTS = Non-Periodic Transmit FIFO/Queue Status Register*/
\r
17358 #define USB_GNPTXSTS_NPTxQTop_Pos (24U)
\r
17359 #define USB_GNPTXSTS_NPTxQTop_Msk (0x0000007FU << USB_GNPTXSTS_NPTxQTop_Pos)
\r
17361 #define USB_GNPTXSTS_NPTxQSpcAvail_Pos (16U)
\r
17362 #define USB_GNPTXSTS_NPTxQSpcAvail_Msk (0x000000FFU << USB_GNPTXSTS_NPTxQSpcAvail_Pos)
\r
17364 #define USB_GNPTXSTS_NPTxFSpcAvail_Pos (0U)
\r
17365 #define USB_GNPTXSTS_NPTxFSpcAvail_Msk (0x0000FFFFU << USB_GNPTXSTS_NPTxFSpcAvail_Pos)
\r
17367 /* USB_GUID = User ID Register*/
\r
17368 #define USB_GUID_UserID_Pos (0U)
\r
17369 #define USB_GUID_UserID_Msk (0xFFFFFFFFU << USB_GUID_UserID_Pos)
\r
17371 /* USB_GDFIFOCFG = Global DFIFO Software Config Register*/
\r
17372 #define USB_GDFIFOCFG_EPInfoBaseAddr_Pos (16U)
\r
17373 #define USB_GDFIFOCFG_EPInfoBaseAddr_Msk (0x0000FFFFU << USB_GDFIFOCFG_EPInfoBaseAddr_Pos)
\r
17375 #define USB_GDFIFOCFG_GDFIFOCfg_Pos (0U)
\r
17376 #define USB_GDFIFOCFG_GDFIFOCfg_Msk (0x0000FFFFU << USB_GDFIFOCFG_GDFIFOCfg_Pos)
\r
17378 /* USB_HPTXFSIZ = Host Periodic Transmit FIFO Size Register*/
\r
17379 #define USB_HPTXFSIZ_PTxFSize_Pos (16U)
\r
17380 #define USB_HPTXFSIZ_PTxFSize_Msk (0x0000FFFFU << USB_HPTXFSIZ_PTxFSize_Pos)
\r
17382 #define USB_HPTXFSIZ_PTxFStAddr_Pos (0U)
\r
17383 #define USB_HPTXFSIZ_PTxFStAddr_Msk (0x0000FFFFU << USB_HPTXFSIZ_PTxFStAddr_Pos)
\r
17385 /* USB_DIEPTXF1 = Device IN Endpoint Transmit FIFO Size Register*/
\r
17386 #define USB_DIEPTXF1_INEPnTxFDep_Pos (16U)
\r
17387 #define USB_DIEPTXF1_INEPnTxFDep_Msk (0x0000FFFFU << USB_DIEPTXF1_INEPnTxFDep_Pos)
\r
17389 #define USB_DIEPTXF1_INEPnTxFStAddr_Pos (0U)
\r
17390 #define USB_DIEPTXF1_INEPnTxFStAddr_Msk (0x0000FFFFU << USB_DIEPTXF1_INEPnTxFStAddr_Pos)
\r
17392 /* USB_DIEPTXF2 = Device IN Endpoint Transmit FIFO Size Register*/
\r
17393 #define USB_DIEPTXF2_INEPnTxFDep_Pos (16U)
\r
17394 #define USB_DIEPTXF2_INEPnTxFDep_Msk (0x0000FFFFU << USB_DIEPTXF2_INEPnTxFDep_Pos)
\r
17396 #define USB_DIEPTXF2_INEPnTxFStAddr_Pos (0U)
\r
17397 #define USB_DIEPTXF2_INEPnTxFStAddr_Msk (0x0000FFFFU << USB_DIEPTXF2_INEPnTxFStAddr_Pos)
\r
17399 /* USB_DIEPTXF3 = Device IN Endpoint Transmit FIFO Size Register*/
\r
17400 #define USB_DIEPTXF3_INEPnTxFDep_Pos (16U)
\r
17401 #define USB_DIEPTXF3_INEPnTxFDep_Msk (0x0000FFFFU << USB_DIEPTXF3_INEPnTxFDep_Pos)
\r
17403 #define USB_DIEPTXF3_INEPnTxFStAddr_Pos (0U)
\r
17404 #define USB_DIEPTXF3_INEPnTxFStAddr_Msk (0x0000FFFFU << USB_DIEPTXF3_INEPnTxFStAddr_Pos)
\r
17406 /* USB_DIEPTXF4 = Device IN Endpoint Transmit FIFO Size Register*/
\r
17407 #define USB_DIEPTXF4_INEPnTxFDep_Pos (16U)
\r
17408 #define USB_DIEPTXF4_INEPnTxFDep_Msk (0x0000FFFFU << USB_DIEPTXF4_INEPnTxFDep_Pos)
\r
17410 #define USB_DIEPTXF4_INEPnTxFStAddr_Pos (0U)
\r
17411 #define USB_DIEPTXF4_INEPnTxFStAddr_Msk (0x0000FFFFU << USB_DIEPTXF4_INEPnTxFStAddr_Pos)
\r
17413 /* USB_DIEPTXF5 = Device IN Endpoint Transmit FIFO Size Register*/
\r
17414 #define USB_DIEPTXF5_INEPnTxFDep_Pos (16U)
\r
17415 #define USB_DIEPTXF5_INEPnTxFDep_Msk (0x0000FFFFU << USB_DIEPTXF5_INEPnTxFDep_Pos)
\r
17417 #define USB_DIEPTXF5_INEPnTxFStAddr_Pos (0U)
\r
17418 #define USB_DIEPTXF5_INEPnTxFStAddr_Msk (0x0000FFFFU << USB_DIEPTXF5_INEPnTxFStAddr_Pos)
\r
17420 /* USB_DIEPTXF6 = Device IN Endpoint Transmit FIFO Size Register*/
\r
17421 #define USB_DIEPTXF6_INEPnTxFDep_Pos (16U)
\r
17422 #define USB_DIEPTXF6_INEPnTxFDep_Msk (0x0000FFFFU << USB_DIEPTXF6_INEPnTxFDep_Pos)
\r
17424 #define USB_DIEPTXF6_INEPnTxFStAddr_Pos (0U)
\r
17425 #define USB_DIEPTXF6_INEPnTxFStAddr_Msk (0x0000FFFFU << USB_DIEPTXF6_INEPnTxFStAddr_Pos)
\r
17427 /* USB_CH_HCFG = Host Configuration Register*/
\r
17428 #define USB_CH_HCFG_PerSchedEna_Pos (26U)
\r
17429 #define USB_CH_HCFG_PerSchedEna_Msk (0x00000001U << USB_CH_HCFG_PerSchedEna_Pos)
\r
17431 #define USB_CH_HCFG_FrListEn_Pos (24U)
\r
17432 #define USB_CH_HCFG_FrListEn_Msk (0x00000003U << USB_CH_HCFG_FrListEn_Pos)
\r
17434 #define USB_CH_HCFG_DescDMA_Pos (23U)
\r
17435 #define USB_CH_HCFG_DescDMA_Msk (0x00000001U << USB_CH_HCFG_DescDMA_Pos)
\r
17437 #define USB_CH_HCFG_ResValid_Pos (8U)
\r
17438 #define USB_CH_HCFG_ResValid_Msk (0x000000FFU << USB_CH_HCFG_ResValid_Pos)
\r
17440 #define USB_CH_HCFG_Ena32KHzS_Pos (7U)
\r
17441 #define USB_CH_HCFG_Ena32KHzS_Msk (0x00000001U << USB_CH_HCFG_Ena32KHzS_Pos)
\r
17443 #define USB_CH_HCFG_FSLSSupp_Pos (2U)
\r
17444 #define USB_CH_HCFG_FSLSSupp_Msk (0x00000001U << USB_CH_HCFG_FSLSSupp_Pos)
\r
17446 #define USB_CH_HCFG_FSLSPclkSel_Pos (0U)
\r
17447 #define USB_CH_HCFG_FSLSPclkSel_Msk (0x00000003U << USB_CH_HCFG_FSLSPclkSel_Pos)
\r
17449 /* USB_HFIR = Host Frame Interval Register*/
\r
17450 #define USB_HFIR_FrInt_Pos (0U)
\r
17451 #define USB_HFIR_FrInt_Msk (0x0000FFFFU << USB_HFIR_FrInt_Pos)
\r
17453 /* USB_HFNUM = Host Frame Number/Frame Time Remaining Register*/
\r
17454 #define USB_HFNUM_FrRem_Pos (16U)
\r
17455 #define USB_HFNUM_FrRem_Msk (0x0000FFFFU << USB_HFNUM_FrRem_Pos)
\r
17457 #define USB_HFNUM_FrNum_Pos (0U)
\r
17458 #define USB_HFNUM_FrNum_Msk (0x0000FFFFU << USB_HFNUM_FrNum_Pos)
\r
17460 /* USB_HPTXSTS = Host Periodic Transmit FIFO/ Queue Status Register*/
\r
17461 #define USB_HPTXSTS_PTxQTop_Pos (24U)
\r
17462 #define USB_HPTXSTS_PTxQTop_Msk (0x000000FFU << USB_HPTXSTS_PTxQTop_Pos)
\r
17464 #define USB_HPTXSTS_PTxQSpcAvail_Pos (16U)
\r
17465 #define USB_HPTXSTS_PTxQSpcAvail_Msk (0x000000FFU << USB_HPTXSTS_PTxQSpcAvail_Pos)
\r
17467 #define USB_HPTXSTS_PTxFSpcAvail_Pos (0U)
\r
17468 #define USB_HPTXSTS_PTxFSpcAvail_Msk (0x0000FFFFU << USB_HPTXSTS_PTxFSpcAvail_Pos)
\r
17470 /* USB_HAINT = Host All Channels Interrupt Register*/
\r
17471 #define USB_HAINT_HAINT_Pos (0U)
\r
17472 #define USB_HAINT_HAINT_Msk (0x00003FFFU << USB_HAINT_HAINT_Pos)
\r
17474 /* USB_HAINTMSK = Host All Channels Interrupt Mask Register*/
\r
17475 #define USB_HAINTMSK_HAINTMsk_Pos (0U)
\r
17476 #define USB_HAINTMSK_HAINTMsk_Msk (0x00003FFFU << USB_HAINTMSK_HAINTMsk_Pos)
\r
17478 /* USB_HFLBADDR = Host Frame List Base Address Register*/
\r
17479 #define USB_HFLBADDR_Starting_Address_Pos (0U)
\r
17480 #define USB_HFLBADDR_Starting_Address_Msk (0xFFFFFFFFU << USB_HFLBADDR_Starting_Address_Pos)
\r
17482 /* USB_HPRT = Host Port Control and Status Register*/
\r
17483 #define USB_HPRT_PrtSpd_Pos (17U)
\r
17484 #define USB_HPRT_PrtSpd_Msk (0x00000003U << USB_HPRT_PrtSpd_Pos)
\r
17486 #define USB_HPRT_PrtPwr_Pos (12U)
\r
17487 #define USB_HPRT_PrtPwr_Msk (0x00000001U << USB_HPRT_PrtPwr_Pos)
\r
17489 #define USB_HPRT_PrtLnSts_Pos (10U)
\r
17490 #define USB_HPRT_PrtLnSts_Msk (0x00000003U << USB_HPRT_PrtLnSts_Pos)
\r
17492 #define USB_HPRT_PrtRst_Pos (8U)
\r
17493 #define USB_HPRT_PrtRst_Msk (0x00000001U << USB_HPRT_PrtRst_Pos)
\r
17495 #define USB_HPRT_PrtSusp_Pos (7U)
\r
17496 #define USB_HPRT_PrtSusp_Msk (0x00000001U << USB_HPRT_PrtSusp_Pos)
\r
17498 #define USB_HPRT_PrtRes_Pos (6U)
\r
17499 #define USB_HPRT_PrtRes_Msk (0x00000001U << USB_HPRT_PrtRes_Pos)
\r
17501 #define USB_HPRT_PrtOvrCurrChng_Pos (5U)
\r
17502 #define USB_HPRT_PrtOvrCurrChng_Msk (0x00000001U << USB_HPRT_PrtOvrCurrChng_Pos)
\r
17504 #define USB_HPRT_PrtOvrCurrAct_Pos (4U)
\r
17505 #define USB_HPRT_PrtOvrCurrAct_Msk (0x00000001U << USB_HPRT_PrtOvrCurrAct_Pos)
\r
17507 #define USB_HPRT_PrtEnChng_Pos (3U)
\r
17508 #define USB_HPRT_PrtEnChng_Msk (0x00000001U << USB_HPRT_PrtEnChng_Pos)
\r
17510 #define USB_HPRT_PrtEna_Pos (2U)
\r
17511 #define USB_HPRT_PrtEna_Msk (0x00000001U << USB_HPRT_PrtEna_Pos)
\r
17513 #define USB_HPRT_PrtConnDet_Pos (1U)
\r
17514 #define USB_HPRT_PrtConnDet_Msk (0x00000001U << USB_HPRT_PrtConnDet_Pos)
\r
17516 #define USB_HPRT_PrtConnSts_Pos (0U)
\r
17517 #define USB_HPRT_PrtConnSts_Msk (0x00000001U << USB_HPRT_PrtConnSts_Pos)
\r
17519 /* USB_DCFG = Device Configuration Register*/
\r
17520 #define USB_DCFG_ResValid_Pos (26U)
\r
17521 #define USB_DCFG_ResValid_Msk (0x0000003FU << USB_DCFG_ResValid_Pos)
\r
17523 #define USB_DCFG_PerSchIntvl_Pos (24U)
\r
17524 #define USB_DCFG_PerSchIntvl_Msk (0x00000003U << USB_DCFG_PerSchIntvl_Pos)
\r
17526 #define USB_DCFG_DescDMA_Pos (23U)
\r
17527 #define USB_DCFG_DescDMA_Msk (0x00000001U << USB_DCFG_DescDMA_Pos)
\r
17529 #define USB_DCFG_EPMisCnt_Pos (18U)
\r
17530 #define USB_DCFG_EPMisCnt_Msk (0x0000001FU << USB_DCFG_EPMisCnt_Pos)
\r
17532 #define USB_DCFG_PerFrInt_Pos (11U)
\r
17533 #define USB_DCFG_PerFrInt_Msk (0x00000003U << USB_DCFG_PerFrInt_Pos)
\r
17535 #define USB_DCFG_DevAddr_Pos (4U)
\r
17536 #define USB_DCFG_DevAddr_Msk (0x0000007FU << USB_DCFG_DevAddr_Pos)
\r
17538 #define USB_DCFG_Ena32KHzS_Pos (3U)
\r
17539 #define USB_DCFG_Ena32KHzS_Msk (0x00000001U << USB_DCFG_Ena32KHzS_Pos)
\r
17541 #define USB_DCFG_NZStsOUTHShk_Pos (2U)
\r
17542 #define USB_DCFG_NZStsOUTHShk_Msk (0x00000001U << USB_DCFG_NZStsOUTHShk_Pos)
\r
17544 #define USB_DCFG_DevSpd_Pos (0U)
\r
17545 #define USB_DCFG_DevSpd_Msk (0x00000003U << USB_DCFG_DevSpd_Pos)
\r
17547 /* USB_DCTL = Device Control Register*/
\r
17548 #define USB_DCTL_NakOnBble_Pos (16U)
\r
17549 #define USB_DCTL_NakOnBble_Msk (0x00000001U << USB_DCTL_NakOnBble_Pos)
\r
17551 #define USB_DCTL_IgnrFrmNum_Pos (15U)
\r
17552 #define USB_DCTL_IgnrFrmNum_Msk (0x00000001U << USB_DCTL_IgnrFrmNum_Pos)
\r
17554 #define USB_DCTL_GMC_Pos (13U)
\r
17555 #define USB_DCTL_GMC_Msk (0x00000003U << USB_DCTL_GMC_Pos)
\r
17557 #define USB_DCTL_PWROnPrgDone_Pos (11U)
\r
17558 #define USB_DCTL_PWROnPrgDone_Msk (0x00000001U << USB_DCTL_PWROnPrgDone_Pos)
\r
17560 #define USB_DCTL_CGOUTNak_Pos (10U)
\r
17561 #define USB_DCTL_CGOUTNak_Msk (0x00000001U << USB_DCTL_CGOUTNak_Pos)
\r
17563 #define USB_DCTL_SGOUTNak_Pos (9U)
\r
17564 #define USB_DCTL_SGOUTNak_Msk (0x00000001U << USB_DCTL_SGOUTNak_Pos)
\r
17566 #define USB_DCTL_CGNPInNak_Pos (8U)
\r
17567 #define USB_DCTL_CGNPInNak_Msk (0x00000001U << USB_DCTL_CGNPInNak_Pos)
\r
17569 #define USB_DCTL_SGNPInNak_Pos (7U)
\r
17570 #define USB_DCTL_SGNPInNak_Msk (0x00000001U << USB_DCTL_SGNPInNak_Pos)
\r
17572 #define USB_DCTL_GOUTNakSts_Pos (3U)
\r
17573 #define USB_DCTL_GOUTNakSts_Msk (0x00000001U << USB_DCTL_GOUTNakSts_Pos)
\r
17575 #define USB_DCTL_GNPINNakSts_Pos (2U)
\r
17576 #define USB_DCTL_GNPINNakSts_Msk (0x00000001U << USB_DCTL_GNPINNakSts_Pos)
\r
17578 #define USB_DCTL_SftDiscon_Pos (1U)
\r
17579 #define USB_DCTL_SftDiscon_Msk (0x00000001U << USB_DCTL_SftDiscon_Pos)
\r
17581 #define USB_DCTL_RmtWkUpSig_Pos (0U)
\r
17582 #define USB_DCTL_RmtWkUpSig_Msk (0x00000001U << USB_DCTL_RmtWkUpSig_Pos)
\r
17584 /* USB_DSTS = Device Status Register*/
\r
17585 #define USB_DSTS_SOFFN_Pos (8U)
\r
17586 #define USB_DSTS_SOFFN_Msk (0x00003FFFU << USB_DSTS_SOFFN_Pos)
\r
17588 #define USB_DSTS_ErrticErr_Pos (3U)
\r
17589 #define USB_DSTS_ErrticErr_Msk (0x00000001U << USB_DSTS_ErrticErr_Pos)
\r
17591 #define USB_DSTS_EnumSpd_Pos (1U)
\r
17592 #define USB_DSTS_EnumSpd_Msk (0x00000003U << USB_DSTS_EnumSpd_Pos)
\r
17594 #define USB_DSTS_SuspSts_Pos (0U)
\r
17595 #define USB_DSTS_SuspSts_Msk (0x00000001U << USB_DSTS_SuspSts_Pos)
\r
17597 /* USB_DIEPMSK = Device IN Endpoint Common Interrupt Mask Register*/
\r
17598 #define USB_DIEPMSK_NAKMsk_Pos (13U)
\r
17599 #define USB_DIEPMSK_NAKMsk_Msk (0x00000001U << USB_DIEPMSK_NAKMsk_Pos)
\r
17601 #define USB_DIEPMSK_BNAInIntrMsk_Pos (9U)
\r
17602 #define USB_DIEPMSK_BNAInIntrMsk_Msk (0x00000001U << USB_DIEPMSK_BNAInIntrMsk_Pos)
\r
17604 #define USB_DIEPMSK_TxfifoUndrnMsk_Pos (8U)
\r
17605 #define USB_DIEPMSK_TxfifoUndrnMsk_Msk (0x00000001U << USB_DIEPMSK_TxfifoUndrnMsk_Pos)
\r
17607 #define USB_DIEPMSK_INEPNakEffMsk_Pos (6U)
\r
17608 #define USB_DIEPMSK_INEPNakEffMsk_Msk (0x00000001U << USB_DIEPMSK_INEPNakEffMsk_Pos)
\r
17610 #define USB_DIEPMSK_INTknEPMisMsk_Pos (5U)
\r
17611 #define USB_DIEPMSK_INTknEPMisMsk_Msk (0x00000001U << USB_DIEPMSK_INTknEPMisMsk_Pos)
\r
17613 #define USB_DIEPMSK_INTknTXFEmpMsk_Pos (4U)
\r
17614 #define USB_DIEPMSK_INTknTXFEmpMsk_Msk (0x00000001U << USB_DIEPMSK_INTknTXFEmpMsk_Pos)
\r
17616 #define USB_DIEPMSK_TimeOUTMsk_Pos (3U)
\r
17617 #define USB_DIEPMSK_TimeOUTMsk_Msk (0x00000001U << USB_DIEPMSK_TimeOUTMsk_Pos)
\r
17619 #define USB_DIEPMSK_AHBErrMsk_Pos (2U)
\r
17620 #define USB_DIEPMSK_AHBErrMsk_Msk (0x00000001U << USB_DIEPMSK_AHBErrMsk_Pos)
\r
17622 #define USB_DIEPMSK_EPDisbldMsk_Pos (1U)
\r
17623 #define USB_DIEPMSK_EPDisbldMsk_Msk (0x00000001U << USB_DIEPMSK_EPDisbldMsk_Pos)
\r
17625 #define USB_DIEPMSK_XferComplMsk_Pos (0U)
\r
17626 #define USB_DIEPMSK_XferComplMsk_Msk (0x00000001U << USB_DIEPMSK_XferComplMsk_Pos)
\r
17628 /* USB_DOEPMSK = Device OUT Endpoint Common Interrupt Mask Register*/
\r
17629 #define USB_DOEPMSK_NYETMsk_Pos (14U)
\r
17630 #define USB_DOEPMSK_NYETMsk_Msk (0x00000001U << USB_DOEPMSK_NYETMsk_Pos)
\r
17632 #define USB_DOEPMSK_NAKMsk_Pos (13U)
\r
17633 #define USB_DOEPMSK_NAKMsk_Msk (0x00000001U << USB_DOEPMSK_NAKMsk_Pos)
\r
17635 #define USB_DOEPMSK_BbleErrMsk_Pos (12U)
\r
17636 #define USB_DOEPMSK_BbleErrMsk_Msk (0x00000001U << USB_DOEPMSK_BbleErrMsk_Pos)
\r
17638 #define USB_DOEPMSK_BnaOutIntrMsk_Pos (9U)
\r
17639 #define USB_DOEPMSK_BnaOutIntrMsk_Msk (0x00000001U << USB_DOEPMSK_BnaOutIntrMsk_Pos)
\r
17641 #define USB_DOEPMSK_OutPktErrMsk_Pos (8U)
\r
17642 #define USB_DOEPMSK_OutPktErrMsk_Msk (0x00000001U << USB_DOEPMSK_OutPktErrMsk_Pos)
\r
17644 #define USB_DOEPMSK_Back2BackSETup_Pos (6U)
\r
17645 #define USB_DOEPMSK_Back2BackSETup_Msk (0x00000001U << USB_DOEPMSK_Back2BackSETup_Pos)
\r
17647 #define USB_DOEPMSK_OUTTknEPdisMsk_Pos (4U)
\r
17648 #define USB_DOEPMSK_OUTTknEPdisMsk_Msk (0x00000001U << USB_DOEPMSK_OUTTknEPdisMsk_Pos)
\r
17650 #define USB_DOEPMSK_SetUPMsk_Pos (3U)
\r
17651 #define USB_DOEPMSK_SetUPMsk_Msk (0x00000001U << USB_DOEPMSK_SetUPMsk_Pos)
\r
17653 #define USB_DOEPMSK_AHBErrMsk_Pos (2U)
\r
17654 #define USB_DOEPMSK_AHBErrMsk_Msk (0x00000001U << USB_DOEPMSK_AHBErrMsk_Pos)
\r
17656 #define USB_DOEPMSK_EPDisbldMsk_Pos (1U)
\r
17657 #define USB_DOEPMSK_EPDisbldMsk_Msk (0x00000001U << USB_DOEPMSK_EPDisbldMsk_Pos)
\r
17659 #define USB_DOEPMSK_XferComplMsk_Pos (0U)
\r
17660 #define USB_DOEPMSK_XferComplMsk_Msk (0x00000001U << USB_DOEPMSK_XferComplMsk_Pos)
\r
17662 /* USB_DAINT = Device All Endpoints Interrupt Register*/
\r
17663 #define USB_DAINT_OutEPInt_Pos (16U)
\r
17664 #define USB_DAINT_OutEPInt_Msk (0x0000FFFFU << USB_DAINT_OutEPInt_Pos)
\r
17666 #define USB_DAINT_InEpInt_Pos (0U)
\r
17667 #define USB_DAINT_InEpInt_Msk (0x0000FFFFU << USB_DAINT_InEpInt_Pos)
\r
17669 /* USB_DAINTMSK = Device All Endpoints Interrupt Mask Register*/
\r
17670 #define USB_DAINTMSK_OutEpMsk_Pos (16U)
\r
17671 #define USB_DAINTMSK_OutEpMsk_Msk (0x0000FFFFU << USB_DAINTMSK_OutEpMsk_Pos)
\r
17673 #define USB_DAINTMSK_InEpMsk_Pos (0U)
\r
17674 #define USB_DAINTMSK_InEpMsk_Msk (0x0000FFFFU << USB_DAINTMSK_InEpMsk_Pos)
\r
17676 /* USB_DVBUSDIS = Device VBUS Discharge Time Register*/
\r
17677 #define USB_DVBUSDIS_DVBUSDis_Pos (0U)
\r
17678 #define USB_DVBUSDIS_DVBUSDis_Msk (0x0000FFFFU << USB_DVBUSDIS_DVBUSDis_Pos)
\r
17680 /* USB_DVBUSPULSE = Device VBUS Pulsing Time Register*/
\r
17681 #define USB_DVBUSPULSE_DVBUSPulse_Pos (0U)
\r
17682 #define USB_DVBUSPULSE_DVBUSPulse_Msk (0x00000FFFU << USB_DVBUSPULSE_DVBUSPulse_Pos)
\r
17684 /* USB_DIEPEMPMSK = Device IN Endpoint FIFO Empty Interrupt Mask Register*/
\r
17685 #define USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos (0U)
\r
17686 #define USB_DIEPEMPMSK_InEpTxfEmpMsk_Msk (0x0000FFFFU << USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos)
\r
17688 /* USB_PCGCCTL = Power and Clock Gating Control Register*/
\r
17689 #define USB_PCGCCTL_ResetAfterSusp_Pos (8U)
\r
17690 #define USB_PCGCCTL_ResetAfterSusp_Msk (0x00000001U << USB_PCGCCTL_ResetAfterSusp_Pos)
\r
17692 #define USB_PCGCCTL_L1_Suspended_Pos (7U)
\r
17693 #define USB_PCGCCTL_L1_Suspended_Msk (0x00000001U << USB_PCGCCTL_L1_Suspended_Pos)
\r
17695 #define USB_PCGCCTL_PhySleep_Pos (6U)
\r
17696 #define USB_PCGCCTL_PhySleep_Msk (0x00000001U << USB_PCGCCTL_PhySleep_Pos)
\r
17698 #define USB_PCGCCTL_Enbl_L1Gating_Pos (5U)
\r
17699 #define USB_PCGCCTL_Enbl_L1Gating_Msk (0x00000001U << USB_PCGCCTL_Enbl_L1Gating_Pos)
\r
17701 #define USB_PCGCCTL_RstPdwnModule_Pos (3U)
\r
17702 #define USB_PCGCCTL_RstPdwnModule_Msk (0x00000001U << USB_PCGCCTL_RstPdwnModule_Pos)
\r
17704 #define USB_PCGCCTL_PwrClmp_Pos (2U)
\r
17705 #define USB_PCGCCTL_PwrClmp_Msk (0x00000001U << USB_PCGCCTL_PwrClmp_Pos)
\r
17707 #define USB_PCGCCTL_GateHclk_Pos (1U)
\r
17708 #define USB_PCGCCTL_GateHclk_Msk (0x00000001U << USB_PCGCCTL_GateHclk_Pos)
\r
17710 #define USB_PCGCCTL_StopPclk_Pos (0U)
\r
17711 #define USB_PCGCCTL_StopPclk_Msk (0x00000001U << USB_PCGCCTL_StopPclk_Pos)
\r
17713 /* USB_EP_DIEPCTL0 = Device Control IN Endpoint x Control Register*/
\r
17714 #define USB_EP_DIEPCTL0_EPEna_Pos (31U)
\r
17715 #define USB_EP_DIEPCTL0_EPEna_Msk (0x00000001U << USB_EP_DIEPCTL0_EPEna_Pos)
\r
17717 #define USB_EP_DIEPCTL0_EPDis_Pos (30U)
\r
17718 #define USB_EP_DIEPCTL0_EPDis_Msk (0x00000001U << USB_EP_DIEPCTL0_EPDis_Pos)
\r
17720 #define USB_EP_DIEPCTL0_SNAK_Pos (27U)
\r
17721 #define USB_EP_DIEPCTL0_SNAK_Msk (0x00000001U << USB_EP_DIEPCTL0_SNAK_Pos)
\r
17723 #define USB_EP_DIEPCTL0_CNAK_Pos (26U)
\r
17724 #define USB_EP_DIEPCTL0_CNAK_Msk (0x00000001U << USB_EP_DIEPCTL0_CNAK_Pos)
\r
17726 #define USB_EP_DIEPCTL0_TxFNum_Pos (22U)
\r
17727 #define USB_EP_DIEPCTL0_TxFNum_Msk (0x0000000FU << USB_EP_DIEPCTL0_TxFNum_Pos)
\r
17729 #define USB_EP_DIEPCTL0_Stall_Pos (21U)
\r
17730 #define USB_EP_DIEPCTL0_Stall_Msk (0x00000001U << USB_EP_DIEPCTL0_Stall_Pos)
\r
17732 #define USB_EP_DIEPCTL0_EPType_Pos (18U)
\r
17733 #define USB_EP_DIEPCTL0_EPType_Msk (0x00000003U << USB_EP_DIEPCTL0_EPType_Pos)
\r
17735 #define USB_EP_DIEPCTL0_NAKSts_Pos (17U)
\r
17736 #define USB_EP_DIEPCTL0_NAKSts_Msk (0x00000001U << USB_EP_DIEPCTL0_NAKSts_Pos)
\r
17738 #define USB_EP_DIEPCTL0_USBActEP_Pos (15U)
\r
17739 #define USB_EP_DIEPCTL0_USBActEP_Msk (0x00000001U << USB_EP_DIEPCTL0_USBActEP_Pos)
\r
17741 #define USB_EP_DIEPCTL0_NextEp_Pos (11U)
\r
17742 #define USB_EP_DIEPCTL0_NextEp_Msk (0x0000000FU << USB_EP_DIEPCTL0_NextEp_Pos)
\r
17744 #define USB_EP_DIEPCTL0_MPS_Pos (0U)
\r
17745 #define USB_EP_DIEPCTL0_MPS_Msk (0x00000003U << USB_EP_DIEPCTL0_MPS_Pos)
\r
17747 /* USB_EP_DIEPINT0 = Device Endpoint-0 Interrupt Register*/
\r
17748 #define USB_EP_DIEPINT0_NYETIntrpt_Pos (14U)
\r
17749 #define USB_EP_DIEPINT0_NYETIntrpt_Msk (0x00000001U << USB_EP_DIEPINT0_NYETIntrpt_Pos)
\r
17751 #define USB_EP_DIEPINT0_NAKIntrpt_Pos (13U)
\r
17752 #define USB_EP_DIEPINT0_NAKIntrpt_Msk (0x00000001U << USB_EP_DIEPINT0_NAKIntrpt_Pos)
\r
17754 #define USB_EP_DIEPINT0_BbleErrIntrpt_Pos (12U)
\r
17755 #define USB_EP_DIEPINT0_BbleErrIntrpt_Msk (0x00000001U << USB_EP_DIEPINT0_BbleErrIntrpt_Pos)
\r
17757 #define USB_EP_DIEPINT0_PktDrpSts_Pos (11U)
\r
17758 #define USB_EP_DIEPINT0_PktDrpSts_Msk (0x00000001U << USB_EP_DIEPINT0_PktDrpSts_Pos)
\r
17760 #define USB_EP_DIEPINT0_BNAIntr_Pos (9U)
\r
17761 #define USB_EP_DIEPINT0_BNAIntr_Msk (0x00000001U << USB_EP_DIEPINT0_BNAIntr_Pos)
\r
17763 #define USB_EP_DIEPINT0_TxfifoUndrn_Pos (8U)
\r
17764 #define USB_EP_DIEPINT0_TxfifoUndrn_Msk (0x00000001U << USB_EP_DIEPINT0_TxfifoUndrn_Pos)
\r
17766 #define USB_EP_DIEPINT0_TxFEmp_Pos (7U)
\r
17767 #define USB_EP_DIEPINT0_TxFEmp_Msk (0x00000001U << USB_EP_DIEPINT0_TxFEmp_Pos)
\r
17769 #define USB_EP_DIEPINT0_INEPNakEff_Pos (6U)
\r
17770 #define USB_EP_DIEPINT0_INEPNakEff_Msk (0x00000001U << USB_EP_DIEPINT0_INEPNakEff_Pos)
\r
17772 #define USB_EP_DIEPINT0_INTknEPMis_Pos (5U)
\r
17773 #define USB_EP_DIEPINT0_INTknEPMis_Msk (0x00000001U << USB_EP_DIEPINT0_INTknEPMis_Pos)
\r
17775 #define USB_EP_DIEPINT0_INTknTXFEmp_Pos (4U)
\r
17776 #define USB_EP_DIEPINT0_INTknTXFEmp_Msk (0x00000001U << USB_EP_DIEPINT0_INTknTXFEmp_Pos)
\r
17778 #define USB_EP_DIEPINT0_TimeOUT_Pos (3U)
\r
17779 #define USB_EP_DIEPINT0_TimeOUT_Msk (0x00000001U << USB_EP_DIEPINT0_TimeOUT_Pos)
\r
17781 #define USB_EP_DIEPINT0_AHBErr_Pos (2U)
\r
17782 #define USB_EP_DIEPINT0_AHBErr_Msk (0x00000001U << USB_EP_DIEPINT0_AHBErr_Pos)
\r
17784 #define USB_EP_DIEPINT0_EPDisbld_Pos (1U)
\r
17785 #define USB_EP_DIEPINT0_EPDisbld_Msk (0x00000001U << USB_EP_DIEPINT0_EPDisbld_Pos)
\r
17787 #define USB_EP_DIEPINT0_XferCompl_Pos (0U)
\r
17788 #define USB_EP_DIEPINT0_XferCompl_Msk (0x00000001U << USB_EP_DIEPINT0_XferCompl_Pos)
\r
17790 /* USB_EP_DIEPTSIZ0 = Device IN Endpoint x Transfer Size Register*/
\r
17791 #define USB_EP_DIEPTSIZ0_PktCnt_Pos (19U)
\r
17792 #define USB_EP_DIEPTSIZ0_PktCnt_Msk (0x00000003U << USB_EP_DIEPTSIZ0_PktCnt_Pos)
\r
17794 #define USB_EP_DIEPTSIZ0_XferSize_Pos (0U)
\r
17795 #define USB_EP_DIEPTSIZ0_XferSize_Msk (0x0000007FU << USB_EP_DIEPTSIZ0_XferSize_Pos)
\r
17797 /* USB_EP_DIEPDMA0 = Device Endpoint-0 DMA Address Register*/
\r
17798 #define USB_EP_DIEPDMA0_DMAAddr_Pos (0U)
\r
17799 #define USB_EP_DIEPDMA0_DMAAddr_Msk (0xFFFFFFFFU << USB_EP_DIEPDMA0_DMAAddr_Pos)
\r
17801 /* USB_EP_DTXFSTS0 = Device IN Endpoint Transmit FIFO Status Register*/
\r
17802 #define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos (0U)
\r
17803 #define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Msk (0x0000FFFFU << USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos)
\r
17805 /* USB_EP_DIEPDMAB0 = Device Endpoint-0 DMA Buffer Address Register*/
\r
17806 #define USB_EP_DIEPDMAB0_DMABufferAddr_Pos (0U)
\r
17807 #define USB_EP_DIEPDMAB0_DMABufferAddr_Msk (0xFFFFFFFFU << USB_EP_DIEPDMAB0_DMABufferAddr_Pos)
\r
17809 /* USB_EP_DOEPCTL0 = Device Control OUT Endpoint x Control Register*/
\r
17810 #define USB_EP_DOEPCTL0_EPEna_Pos (31U)
\r
17811 #define USB_EP_DOEPCTL0_EPEna_Msk (0x00000001U << USB_EP_DOEPCTL0_EPEna_Pos)
\r
17813 #define USB_EP_DOEPCTL0_EPDis_Pos (30U)
\r
17814 #define USB_EP_DOEPCTL0_EPDis_Msk (0x00000001U << USB_EP_DOEPCTL0_EPDis_Pos)
\r
17816 #define USB_EP_DOEPCTL0_SNAK_Pos (27U)
\r
17817 #define USB_EP_DOEPCTL0_SNAK_Msk (0x00000001U << USB_EP_DOEPCTL0_SNAK_Pos)
\r
17819 #define USB_EP_DOEPCTL0_CNAK_Pos (26U)
\r
17820 #define USB_EP_DOEPCTL0_CNAK_Msk (0x00000001U << USB_EP_DOEPCTL0_CNAK_Pos)
\r
17822 #define USB_EP_DOEPCTL0_Stall_Pos (21U)
\r
17823 #define USB_EP_DOEPCTL0_Stall_Msk (0x00000001U << USB_EP_DOEPCTL0_Stall_Pos)
\r
17825 #define USB_EP_DOEPCTL0_Snp_Pos (20U)
\r
17826 #define USB_EP_DOEPCTL0_Snp_Msk (0x00000001U << USB_EP_DOEPCTL0_Snp_Pos)
\r
17828 #define USB_EP_DOEPCTL0_EPType_Pos (18U)
\r
17829 #define USB_EP_DOEPCTL0_EPType_Msk (0x00000003U << USB_EP_DOEPCTL0_EPType_Pos)
\r
17831 #define USB_EP_DOEPCTL0_NAKSts_Pos (17U)
\r
17832 #define USB_EP_DOEPCTL0_NAKSts_Msk (0x00000001U << USB_EP_DOEPCTL0_NAKSts_Pos)
\r
17834 #define USB_EP_DOEPCTL0_USBActEP_Pos (15U)
\r
17835 #define USB_EP_DOEPCTL0_USBActEP_Msk (0x00000001U << USB_EP_DOEPCTL0_USBActEP_Pos)
\r
17837 #define USB_EP_DOEPCTL0_MPS_Pos (0U)
\r
17838 #define USB_EP_DOEPCTL0_MPS_Msk (0x00000003U << USB_EP_DOEPCTL0_MPS_Pos)
\r
17840 /* USB_EP_DOEPINT0 = Device Endpoint-0 Interrupt Register*/
\r
17841 #define USB_EP_DOEPINT0_NYETIntrpt_Pos (14U)
\r
17842 #define USB_EP_DOEPINT0_NYETIntrpt_Msk (0x00000001U << USB_EP_DOEPINT0_NYETIntrpt_Pos)
\r
17844 #define USB_EP_DOEPINT0_NAKIntrpt_Pos (13U)
\r
17845 #define USB_EP_DOEPINT0_NAKIntrpt_Msk (0x00000001U << USB_EP_DOEPINT0_NAKIntrpt_Pos)
\r
17847 #define USB_EP_DOEPINT0_BbleErrIntrpt_Pos (12U)
\r
17848 #define USB_EP_DOEPINT0_BbleErrIntrpt_Msk (0x00000001U << USB_EP_DOEPINT0_BbleErrIntrpt_Pos)
\r
17850 #define USB_EP_DOEPINT0_PktDrpSts_Pos (11U)
\r
17851 #define USB_EP_DOEPINT0_PktDrpSts_Msk (0x00000001U << USB_EP_DOEPINT0_PktDrpSts_Pos)
\r
17853 #define USB_EP_DOEPINT0_BNAIntr_Pos (9U)
\r
17854 #define USB_EP_DOEPINT0_BNAIntr_Msk (0x00000001U << USB_EP_DOEPINT0_BNAIntr_Pos)
\r
17856 #define USB_EP_DOEPINT0_OutPktErr_Pos (8U)
\r
17857 #define USB_EP_DOEPINT0_OutPktErr_Msk (0x00000001U << USB_EP_DOEPINT0_OutPktErr_Pos)
\r
17859 #define USB_EP_DOEPINT0_Back2BackSETup_Pos (6U)
\r
17860 #define USB_EP_DOEPINT0_Back2BackSETup_Msk (0x00000001U << USB_EP_DOEPINT0_Back2BackSETup_Pos)
\r
17862 #define USB_EP_DOEPINT0_StsPhseRcvd_Pos (5U)
\r
17863 #define USB_EP_DOEPINT0_StsPhseRcvd_Msk (0x00000001U << USB_EP_DOEPINT0_StsPhseRcvd_Pos)
\r
17865 #define USB_EP_DOEPINT0_OUTTknEPdis_Pos (4U)
\r
17866 #define USB_EP_DOEPINT0_OUTTknEPdis_Msk (0x00000001U << USB_EP_DOEPINT0_OUTTknEPdis_Pos)
\r
17868 #define USB_EP_DOEPINT0_SetUp_Pos (3U)
\r
17869 #define USB_EP_DOEPINT0_SetUp_Msk (0x00000001U << USB_EP_DOEPINT0_SetUp_Pos)
\r
17871 #define USB_EP_DOEPINT0_AHBErr_Pos (2U)
\r
17872 #define USB_EP_DOEPINT0_AHBErr_Msk (0x00000001U << USB_EP_DOEPINT0_AHBErr_Pos)
\r
17874 #define USB_EP_DOEPINT0_EPDisbld_Pos (1U)
\r
17875 #define USB_EP_DOEPINT0_EPDisbld_Msk (0x00000001U << USB_EP_DOEPINT0_EPDisbld_Pos)
\r
17877 #define USB_EP_DOEPINT0_XferCompl_Pos (0U)
\r
17878 #define USB_EP_DOEPINT0_XferCompl_Msk (0x00000001U << USB_EP_DOEPINT0_XferCompl_Pos)
\r
17880 /* USB_EP_DOEPTSIZ0 = Device OUT Endpoint x Transfer Size Register*/
\r
17881 #define USB_EP_DOEPTSIZ0_SUPCnt_Pos (29U)
\r
17882 #define USB_EP_DOEPTSIZ0_SUPCnt_Msk (0x00000003U << USB_EP_DOEPTSIZ0_SUPCnt_Pos)
\r
17884 #define USB_EP_DOEPTSIZ0_PktCnt_Pos (19U)
\r
17885 #define USB_EP_DOEPTSIZ0_PktCnt_Msk (0x00000003U << USB_EP_DOEPTSIZ0_PktCnt_Pos)
\r
17887 #define USB_EP_DOEPTSIZ0_XferSize_Pos (0U)
\r
17888 #define USB_EP_DOEPTSIZ0_XferSize_Msk (0x0000007FU << USB_EP_DOEPTSIZ0_XferSize_Pos)
\r
17890 /* USB_EP_DOEPDMA0 = Device Endpoint-0 DMA Address Register*/
\r
17891 #define USB_EP_DOEPDMA0_DMAAddr_Pos (0U)
\r
17892 #define USB_EP_DOEPDMA0_DMAAddr_Msk (0xFFFFFFFFU << USB_EP_DOEPDMA0_DMAAddr_Pos)
\r
17894 /* USB_EP_DOEPDMAB0 = Device Endpoint-0 DMA Buffer Address Register*/
\r
17895 #define USB_EP_DOEPDMAB0_DMABufferAddr_Pos (0U)
\r
17896 #define USB_EP_DOEPDMAB0_DMABufferAddr_Msk (0xFFFFFFFFU << USB_EP_DOEPDMAB0_DMABufferAddr_Pos)
\r
17898 /* USB_EP_DIEPCTL_INTBULK = Device Endpoint-1 Control Register [Interrupt/Bulk Endpoint]*/
\r
17899 #define USB_EP_DIEPCTL_INTBULK_EPEna_Pos (31U)
\r
17900 #define USB_EP_DIEPCTL_INTBULK_EPEna_Msk (0x00000001U << USB_EP_DIEPCTL_INTBULK_EPEna_Pos)
\r
17902 #define USB_EP_DIEPCTL_INTBULK_EPDis_Pos (30U)
\r
17903 #define USB_EP_DIEPCTL_INTBULK_EPDis_Msk (0x00000001U << USB_EP_DIEPCTL_INTBULK_EPDis_Pos)
\r
17905 #define USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos (29U)
\r
17906 #define USB_EP_DIEPCTL_INTBULK_SetD1PID_Msk (0x00000001U << USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos)
\r
17908 #define USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos (28U)
\r
17909 #define USB_EP_DIEPCTL_INTBULK_SetD0PID_Msk (0x00000001U << USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos)
\r
17911 #define USB_EP_DIEPCTL_INTBULK_SNAK_Pos (27U)
\r
17912 #define USB_EP_DIEPCTL_INTBULK_SNAK_Msk (0x00000001U << USB_EP_DIEPCTL_INTBULK_SNAK_Pos)
\r
17914 #define USB_EP_DIEPCTL_INTBULK_CNAK_Pos (26U)
\r
17915 #define USB_EP_DIEPCTL_INTBULK_CNAK_Msk (0x00000001U << USB_EP_DIEPCTL_INTBULK_CNAK_Pos)
\r
17917 #define USB_EP_DIEPCTL_INTBULK_TxFNum_Pos (22U)
\r
17918 #define USB_EP_DIEPCTL_INTBULK_TxFNum_Msk (0x0000000FU << USB_EP_DIEPCTL_INTBULK_TxFNum_Pos)
\r
17920 #define USB_EP_DIEPCTL_INTBULK_Stall_Pos (21U)
\r
17921 #define USB_EP_DIEPCTL_INTBULK_Stall_Msk (0x00000001U << USB_EP_DIEPCTL_INTBULK_Stall_Pos)
\r
17923 #define USB_EP_DIEPCTL_INTBULK_Snp_Pos (20U)
\r
17924 #define USB_EP_DIEPCTL_INTBULK_Snp_Msk (0x00000001U << USB_EP_DIEPCTL_INTBULK_Snp_Pos)
\r
17926 #define USB_EP_DIEPCTL_INTBULK_EPType_Pos (18U)
\r
17927 #define USB_EP_DIEPCTL_INTBULK_EPType_Msk (0x00000003U << USB_EP_DIEPCTL_INTBULK_EPType_Pos)
\r
17929 #define USB_EP_DIEPCTL_INTBULK_NAKSts_Pos (17U)
\r
17930 #define USB_EP_DIEPCTL_INTBULK_NAKSts_Msk (0x00000001U << USB_EP_DIEPCTL_INTBULK_NAKSts_Pos)
\r
17932 #define USB_EP_DIEPCTL_INTBULK_DPID_Pos (16U)
\r
17933 #define USB_EP_DIEPCTL_INTBULK_DPID_Msk (0x00000001U << USB_EP_DIEPCTL_INTBULK_DPID_Pos)
\r
17935 #define USB_EP_DIEPCTL_INTBULK_USBActEP_Pos (15U)
\r
17936 #define USB_EP_DIEPCTL_INTBULK_USBActEP_Msk (0x00000001U << USB_EP_DIEPCTL_INTBULK_USBActEP_Pos)
\r
17938 #define USB_EP_DIEPCTL_INTBULK_NextEp_Pos (11U)
\r
17939 #define USB_EP_DIEPCTL_INTBULK_NextEp_Msk (0x0000000FU << USB_EP_DIEPCTL_INTBULK_NextEp_Pos)
\r
17941 #define USB_EP_DIEPCTL_INTBULK_MPS_Pos (0U)
\r
17942 #define USB_EP_DIEPCTL_INTBULK_MPS_Msk (0x000007FFU << USB_EP_DIEPCTL_INTBULK_MPS_Pos)
\r
17944 /* USB_EP_DIEPCTL_ISOCONT = Device Endpoint-1 Control Register [Isochronous/Control Endpoint]*/
\r
17945 #define USB_EP_DIEPCTL_ISOCONT_EPEna_Pos (31U)
\r
17946 #define USB_EP_DIEPCTL_ISOCONT_EPEna_Msk (0x00000001U << USB_EP_DIEPCTL_ISOCONT_EPEna_Pos)
\r
17948 #define USB_EP_DIEPCTL_ISOCONT_EPDis_Pos (30U)
\r
17949 #define USB_EP_DIEPCTL_ISOCONT_EPDis_Msk (0x00000001U << USB_EP_DIEPCTL_ISOCONT_EPDis_Pos)
\r
17951 #define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos (29U)
\r
17952 #define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Msk (0x00000001U << USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos)
\r
17954 #define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos (28U)
\r
17955 #define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Msk (0x00000001U << USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos)
\r
17957 #define USB_EP_DIEPCTL_ISOCONT_SNAK_Pos (27U)
\r
17958 #define USB_EP_DIEPCTL_ISOCONT_SNAK_Msk (0x00000001U << USB_EP_DIEPCTL_ISOCONT_SNAK_Pos)
\r
17960 #define USB_EP_DIEPCTL_ISOCONT_CNAK_Pos (26U)
\r
17961 #define USB_EP_DIEPCTL_ISOCONT_CNAK_Msk (0x00000001U << USB_EP_DIEPCTL_ISOCONT_CNAK_Pos)
\r
17963 #define USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos (22U)
\r
17964 #define USB_EP_DIEPCTL_ISOCONT_TxFNum_Msk (0x0000000FU << USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos)
\r
17966 #define USB_EP_DIEPCTL_ISOCONT_Stall_Pos (21U)
\r
17967 #define USB_EP_DIEPCTL_ISOCONT_Stall_Msk (0x00000001U << USB_EP_DIEPCTL_ISOCONT_Stall_Pos)
\r
17969 #define USB_EP_DIEPCTL_ISOCONT_Snp_Pos (20U)
\r
17970 #define USB_EP_DIEPCTL_ISOCONT_Snp_Msk (0x00000001U << USB_EP_DIEPCTL_ISOCONT_Snp_Pos)
\r
17972 #define USB_EP_DIEPCTL_ISOCONT_EPType_Pos (18U)
\r
17973 #define USB_EP_DIEPCTL_ISOCONT_EPType_Msk (0x00000003U << USB_EP_DIEPCTL_ISOCONT_EPType_Pos)
\r
17975 #define USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos (17U)
\r
17976 #define USB_EP_DIEPCTL_ISOCONT_NAKSts_Msk (0x00000001U << USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos)
\r
17978 #define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos (16U)
\r
17979 #define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Msk (0x00000001U << USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos)
\r
17981 #define USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos (15U)
\r
17982 #define USB_EP_DIEPCTL_ISOCONT_USBActEP_Msk (0x00000001U << USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos)
\r
17984 #define USB_EP_DIEPCTL_ISOCONT_NextEp_Pos (11U)
\r
17985 #define USB_EP_DIEPCTL_ISOCONT_NextEp_Msk (0x0000000FU << USB_EP_DIEPCTL_ISOCONT_NextEp_Pos)
\r
17987 #define USB_EP_DIEPCTL_ISOCONT_MPS_Pos (0U)
\r
17988 #define USB_EP_DIEPCTL_ISOCONT_MPS_Msk (0x000007FFU << USB_EP_DIEPCTL_ISOCONT_MPS_Pos)
\r
17990 /* USB_EP_DIEPINTx = Device Endpoint-1 Interrupt Register*/
\r
17991 #define USB_EP_DIEPINT_NYETIntrpt_Pos (14U)
\r
17992 #define USB_EP_DIEPINT_NYETIntrpt_Msk (0x00000001U << USB_EP_DIEPINT_NYETIntrpt_Pos)
\r
17994 #define USB_EP_DIEPINT_NAKIntrpt_Pos (13U)
\r
17995 #define USB_EP_DIEPINT_NAKIntrpt_Msk (0x00000001U << USB_EP_DIEPINT_NAKIntrpt_Pos)
\r
17997 #define USB_EP_DIEPINT_BbleErrIntrpt_Pos (12U)
\r
17998 #define USB_EP_DIEPINT_BbleErrIntrpt_Msk (0x00000001U << USB_EP_DIEPINT_BbleErrIntrpt_Pos)
\r
18000 #define USB_EP_DIEPINT_PktDrpSts_Pos (11U)
\r
18001 #define USB_EP_DIEPINT_PktDrpSts_Msk (0x00000001U << USB_EP_DIEPINT_PktDrpSts_Pos)
\r
18003 #define USB_EP_DIEPINT_BNAIntr_Pos (9U)
\r
18004 #define USB_EP_DIEPINT_BNAIntr_Msk (0x00000001U << USB_EP_DIEPINT_BNAIntr_Pos)
\r
18006 #define USB_EP_DIEPINT_TxfifoUndrn_Pos (8U)
\r
18007 #define USB_EP_DIEPINT_TxfifoUndrn_Msk (0x00000001U << USB_EP_DIEPINT_TxfifoUndrn_Pos)
\r
18009 #define USB_EP_DIEPINT_TxFEmp_Pos (7U)
\r
18010 #define USB_EP_DIEPINT_TxFEmp_Msk (0x00000001U << USB_EP_DIEPINT_TxFEmp_Pos)
\r
18012 #define USB_EP_DIEPINT_INEPNakEff_Pos (6U)
\r
18013 #define USB_EP_DIEPINT_INEPNakEff_Msk (0x00000001U << USB_EP_DIEPINT_INEPNakEff_Pos)
\r
18015 #define USB_EP_DIEPINT_INTknEPMis_Pos (5U)
\r
18016 #define USB_EP_DIEPINT_INTknEPMis_Msk (0x00000001U << USB_EP_DIEPINT_INTknEPMis_Pos)
\r
18018 #define USB_EP_DIEPINT_INTknTXFEmp_Pos (4U)
\r
18019 #define USB_EP_DIEPINT_INTknTXFEmp_Msk (0x00000001U << USB_EP_DIEPINT_INTknTXFEmp_Pos)
\r
18021 #define USB_EP_DIEPINT_TimeOUT_Pos (3U)
\r
18022 #define USB_EP_DIEPINT_TimeOUT_Msk (0x00000001U << USB_EP_DIEPINT_TimeOUT_Pos)
\r
18024 #define USB_EP_DIEPINT_AHBErr_Pos (2U)
\r
18025 #define USB_EP_DIEPINT_AHBErr_Msk (0x00000001U << USB_EP_DIEPINT_AHBErr_Pos)
\r
18027 #define USB_EP_DIEPINT_EPDisbld_Pos (1U)
\r
18028 #define USB_EP_DIEPINT_EPDisbld_Msk (0x00000001U << USB_EP_DIEPINT_EPDisbld_Pos)
\r
18030 #define USB_EP_DIEPINT_XferCompl_Pos (0U)
\r
18031 #define USB_EP_DIEPINT_XferCompl_Msk (0x00000001U << USB_EP_DIEPINT_XferCompl_Pos)
\r
18033 /* USB_EP_DIEPTSIZx = Device Endpoint-1 Transfer Size Register*/
\r
18034 #define USB_EP_DIEPTSIZ_PktCnt_Pos (19U)
\r
18035 #define USB_EP_DIEPTSIZ_PktCnt_Msk (0x000003FFU << USB_EP_DIEPTSIZ_PktCnt_Pos)
\r
18037 #define USB_EP_DIEPTSIZ_XferSize_Pos (0U)
\r
18038 #define USB_EP_DIEPTSIZ_XferSize_Msk (0x0007FFFFU << USB_EP_DIEPTSIZ_XferSize_Pos)
\r
18040 /* USB_EP_DIEPDMAx = Device Endpoint-1 DMA Address Register*/
\r
18041 #define USB_EP_DIEPDMA_DMAAddr_Pos (0U)
\r
18042 #define USB_EP_DIEPDMA_DMAAddr_Msk (0xFFFFFFFFU << USB_EP_DIEPDMA_DMAAddr_Pos)
\r
18044 /* USB_EP_DTXFSTSx = Device IN Endpoint Transmit FIFO Status Register*/
\r
18045 #define USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos (0U)
\r
18046 #define USB_EP_DTXFSTS_INEPTxFSpcAvail_Msk (0x0000FFFFU << USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos)
\r
18048 /* USB_EP_DIEPDMABx = Device Endpoint-1 DMA Buffer Address Register*/
\r
18049 #define USB_EP_DIEPDMAB_DMABufferAddr_Pos (0U)
\r
18050 #define USB_EP_DIEPDMAB_DMABufferAddr_Msk (0xFFFFFFFFU << USB_EP_DIEPDMAB_DMABufferAddr_Pos)
\r
18052 /* USB_EP_DOEPCTL_INTBULK = Device Endpoint-1 Control Register [Interrupt/Bulk Endpoint]*/
\r
18053 #define USB_EP_DOEPCTL_INTBULK_EPEna_Pos (31U)
\r
18054 #define USB_EP_DOEPCTL_INTBULK_EPEna_Msk (0x00000001U << USB_EP_DOEPCTL_INTBULK_EPEna_Pos)
\r
18056 #define USB_EP_DOEPCTL_INTBULK_EPDis_Pos (30U)
\r
18057 #define USB_EP_DOEPCTL_INTBULK_EPDis_Msk (0x00000001U << USB_EP_DOEPCTL_INTBULK_EPDis_Pos)
\r
18059 #define USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos (29U)
\r
18060 #define USB_EP_DOEPCTL_INTBULK_SetD1PID_Msk (0x00000001U << USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos)
\r
18062 #define USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos (28U)
\r
18063 #define USB_EP_DOEPCTL_INTBULK_SetD0PID_Msk (0x00000001U << USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos)
\r
18065 #define USB_EP_DOEPCTL_INTBULK_SNAK_Pos (27U)
\r
18066 #define USB_EP_DOEPCTL_INTBULK_SNAK_Msk (0x00000001U << USB_EP_DOEPCTL_INTBULK_SNAK_Pos)
\r
18068 #define USB_EP_DOEPCTL_INTBULK_CNAK_Pos (26U)
\r
18069 #define USB_EP_DOEPCTL_INTBULK_CNAK_Msk (0x00000001U << USB_EP_DOEPCTL_INTBULK_CNAK_Pos)
\r
18071 #define USB_EP_DOEPCTL_INTBULK_TxFNum_Pos (22U)
\r
18072 #define USB_EP_DOEPCTL_INTBULK_TxFNum_Msk (0x0000000FU << USB_EP_DOEPCTL_INTBULK_TxFNum_Pos)
\r
18074 #define USB_EP_DOEPCTL_INTBULK_Stall_Pos (21U)
\r
18075 #define USB_EP_DOEPCTL_INTBULK_Stall_Msk (0x00000001U << USB_EP_DOEPCTL_INTBULK_Stall_Pos)
\r
18077 #define USB_EP_DOEPCTL_INTBULK_Snp_Pos (20U)
\r
18078 #define USB_EP_DOEPCTL_INTBULK_Snp_Msk (0x00000001U << USB_EP_DOEPCTL_INTBULK_Snp_Pos)
\r
18080 #define USB_EP_DOEPCTL_INTBULK_EPType_Pos (18U)
\r
18081 #define USB_EP_DOEPCTL_INTBULK_EPType_Msk (0x00000003U << USB_EP_DOEPCTL_INTBULK_EPType_Pos)
\r
18083 #define USB_EP_DOEPCTL_INTBULK_NAKSts_Pos (17U)
\r
18084 #define USB_EP_DOEPCTL_INTBULK_NAKSts_Msk (0x00000001U << USB_EP_DOEPCTL_INTBULK_NAKSts_Pos)
\r
18086 #define USB_EP_DOEPCTL_INTBULK_DPID_Pos (16U)
\r
18087 #define USB_EP_DOEPCTL_INTBULK_DPID_Msk (0x00000001U << USB_EP_DOEPCTL_INTBULK_DPID_Pos)
\r
18089 #define USB_EP_DOEPCTL_INTBULK_USBActEP_Pos (15U)
\r
18090 #define USB_EP_DOEPCTL_INTBULK_USBActEP_Msk (0x00000001U << USB_EP_DOEPCTL_INTBULK_USBActEP_Pos)
\r
18092 #define USB_EP_DOEPCTL_INTBULK_NextEp_Pos (11U)
\r
18093 #define USB_EP_DOEPCTL_INTBULK_NextEp_Msk (0x0000000FU << USB_EP_DOEPCTL_INTBULK_NextEp_Pos)
\r
18095 #define USB_EP_DOEPCTL_INTBULK_MPS_Pos (0U)
\r
18096 #define USB_EP_DOEPCTL_INTBULK_MPS_Msk (0x000007FFU << USB_EP_DOEPCTL_INTBULK_MPS_Pos)
\r
18098 /* USB_EP_DOEPCTL_ISOCONT = Device Endpoint-1 Control Register [Isochronous/Control Endpoint]*/
\r
18099 #define USB_EP_DOEPCTL_ISOCONT_EPEna_Pos (31U)
\r
18100 #define USB_EP_DOEPCTL_ISOCONT_EPEna_Msk (0x00000001U << USB_EP_DOEPCTL_ISOCONT_EPEna_Pos)
\r
18102 #define USB_EP_DOEPCTL_ISOCONT_EPDis_Pos (30U)
\r
18103 #define USB_EP_DOEPCTL_ISOCONT_EPDis_Msk (0x00000001U << USB_EP_DOEPCTL_ISOCONT_EPDis_Pos)
\r
18105 #define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos (29U)
\r
18106 #define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Msk (0x00000001U << USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos)
\r
18108 #define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos (28U)
\r
18109 #define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Msk (0x00000001U << USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos)
\r
18111 #define USB_EP_DOEPCTL_ISOCONT_SNAK_Pos (27U)
\r
18112 #define USB_EP_DOEPCTL_ISOCONT_SNAK_Msk (0x00000001U << USB_EP_DOEPCTL_ISOCONT_SNAK_Pos)
\r
18114 #define USB_EP_DOEPCTL_ISOCONT_CNAK_Pos (26U)
\r
18115 #define USB_EP_DOEPCTL_ISOCONT_CNAK_Msk (0x00000001U << USB_EP_DOEPCTL_ISOCONT_CNAK_Pos)
\r
18117 #define USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos (22U)
\r
18118 #define USB_EP_DOEPCTL_ISOCONT_TxFNum_Msk (0x0000000FU << USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos)
\r
18120 #define USB_EP_DOEPCTL_ISOCONT_Stall_Pos (21U)
\r
18121 #define USB_EP_DOEPCTL_ISOCONT_Stall_Msk (0x00000001U << USB_EP_DOEPCTL_ISOCONT_Stall_Pos)
\r
18123 #define USB_EP_DOEPCTL_ISOCONT_Snp_Pos (20U)
\r
18124 #define USB_EP_DOEPCTL_ISOCONT_Snp_Msk (0x00000001U << USB_EP_DOEPCTL_ISOCONT_Snp_Pos)
\r
18126 #define USB_EP_DOEPCTL_ISOCONT_EPType_Pos (18U)
\r
18127 #define USB_EP_DOEPCTL_ISOCONT_EPType_Msk (0x00000003U << USB_EP_DOEPCTL_ISOCONT_EPType_Pos)
\r
18129 #define USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos (17U)
\r
18130 #define USB_EP_DOEPCTL_ISOCONT_NAKSts_Msk (0x00000001U << USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos)
\r
18132 #define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos (16U)
\r
18133 #define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Msk (0x00000001U << USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos)
\r
18135 #define USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos (15U)
\r
18136 #define USB_EP_DOEPCTL_ISOCONT_USBActEP_Msk (0x00000001U << USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos)
\r
18138 #define USB_EP_DOEPCTL_ISOCONT_NextEp_Pos (11U)
\r
18139 #define USB_EP_DOEPCTL_ISOCONT_NextEp_Msk (0x0000000FU << USB_EP_DOEPCTL_ISOCONT_NextEp_Pos)
\r
18141 #define USB_EP_DOEPCTL_ISOCONT_MPS_Pos (0U)
\r
18142 #define USB_EP_DOEPCTL_ISOCONT_MPS_Msk (0x000007FFU << USB_EP_DOEPCTL_ISOCONT_MPS_Pos)
\r
18144 /* USB_EP_DOEPINTx = Device Endpoint-1 Interrupt Register*/
\r
18145 #define USB_EP_DOEPINT_NYETIntrpt_Pos (14U)
\r
18146 #define USB_EP_DOEPINT_NYETIntrpt_Msk (0x00000001U << USB_EP_DOEPINT_NYETIntrpt_Pos)
\r
18148 #define USB_EP_DOEPINT_NAKIntrpt_Pos (13U)
\r
18149 #define USB_EP_DOEPINT_NAKIntrpt_Msk (0x00000001U << USB_EP_DOEPINT_NAKIntrpt_Pos)
\r
18151 #define USB_EP_DOEPINT_BbleErrIntrpt_Pos (12U)
\r
18152 #define USB_EP_DOEPINT_BbleErrIntrpt_Msk (0x00000001U << USB_EP_DOEPINT_BbleErrIntrpt_Pos)
\r
18154 #define USB_EP_DOEPINT_PktDrpSts_Pos (11U)
\r
18155 #define USB_EP_DOEPINT_PktDrpSts_Msk (0x00000001U << USB_EP_DOEPINT_PktDrpSts_Pos)
\r
18157 #define USB_EP_DOEPINT_BNAIntr_Pos (9U)
\r
18158 #define USB_EP_DOEPINT_BNAIntr_Msk (0x00000001U << USB_EP_DOEPINT_BNAIntr_Pos)
\r
18160 #define USB_EP_DOEPINT_OutPktErr_Pos (8U)
\r
18161 #define USB_EP_DOEPINT_OutPktErr_Msk (0x00000001U << USB_EP_DOEPINT_OutPktErr_Pos)
\r
18163 #define USB_EP_DOEPINT_Back2BackSETup_Pos (6U)
\r
18164 #define USB_EP_DOEPINT_Back2BackSETup_Msk (0x00000001U << USB_EP_DOEPINT_Back2BackSETup_Pos)
\r
18166 #define USB_EP_DOEPINT_StsPhseRcvd_Pos (5U)
\r
18167 #define USB_EP_DOEPINT_StsPhseRcvd_Msk (0x00000001U << USB_EP_DOEPINT_StsPhseRcvd_Pos)
\r
18169 #define USB_EP_DOEPINT_OUTTknEPdis_Pos (4U)
\r
18170 #define USB_EP_DOEPINT_OUTTknEPdis_Msk (0x00000001U << USB_EP_DOEPINT_OUTTknEPdis_Pos)
\r
18172 #define USB_EP_DOEPINT_SetUp_Pos (3U)
\r
18173 #define USB_EP_DOEPINT_SetUp_Msk (0x00000001U << USB_EP_DOEPINT_SetUp_Pos)
\r
18175 #define USB_EP_DOEPINT_AHBErr_Pos (2U)
\r
18176 #define USB_EP_DOEPINT_AHBErr_Msk (0x00000001U << USB_EP_DOEPINT_AHBErr_Pos)
\r
18178 #define USB_EP_DOEPINT_EPDisbld_Pos (1U)
\r
18179 #define USB_EP_DOEPINT_EPDisbld_Msk (0x00000001U << USB_EP_DOEPINT_EPDisbld_Pos)
\r
18181 #define USB_EP_DOEPINT_XferCompl_Pos (0U)
\r
18182 #define USB_EP_DOEPINT_XferCompl_Msk (0x00000001U << USB_EP_DOEPINT_XferCompl_Pos)
\r
18184 /* USB_EP_DOEPTSIZ_ISO = Device Endpoint-1 Transfer Size Register [Isochronous OUT Endpoint]*/
\r
18185 #define USB_EP_DOEPTSIZ_ISO_RxDPID_Pos (29U)
\r
18186 #define USB_EP_DOEPTSIZ_ISO_RxDPID_Msk (0x00000003U << USB_EP_DOEPTSIZ_ISO_RxDPID_Pos)
\r
18188 #define USB_EP_DOEPTSIZ_ISO_PktCnt_Pos (19U)
\r
18189 #define USB_EP_DOEPTSIZ_ISO_PktCnt_Msk (0x000003FFU << USB_EP_DOEPTSIZ_ISO_PktCnt_Pos)
\r
18191 #define USB_EP_DOEPTSIZ_ISO_XferSize_Pos (0U)
\r
18192 #define USB_EP_DOEPTSIZ_ISO_XferSize_Msk (0x0007FFFFU << USB_EP_DOEPTSIZ_ISO_XferSize_Pos)
\r
18194 /* USB_EP_DOEPTSIZ_CONTROL = Device Endpoint-1 Transfer Size Register [Control OUT Endpoint]*/
\r
18195 #define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos (29U)
\r
18196 #define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Msk (0x00000003U << USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos)
\r
18198 #define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos (19U)
\r
18199 #define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Msk (0x000003FFU << USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos)
\r
18201 #define USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos (0U)
\r
18202 #define USB_EP_DOEPTSIZ_CONTROL_XferSize_Msk (0x0007FFFFU << USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos)
\r
18204 /* USB_EP_DOEPDMAx = Device Endpoint-1 DMA Address Register*/
\r
18205 #define USB_EP_DOEPDMA_DMAAddr_Pos (0U)
\r
18206 #define USB_EP_DOEPDMA_DMAAddr_Msk (0xFFFFFFFFU << USB_EP_DOEPDMA_DMAAddr_Pos)
\r
18208 /* USB_EP_DOEPDMABx = Device Endpoint-1 DMA Buffer Address Register*/
\r
18209 #define USB_EP_DOEPDMAB_DMABufferAddr_Pos (0U)
\r
18210 #define USB_EP_DOEPDMAB_DMABufferAddr_Msk (0xFFFFFFFFU << USB_EP_DOEPDMAB_DMABufferAddr_Pos)
\r
18212 /* USB_CH_HCCHARx = Host Channel-0 Characteristics Register*/
\r
18213 #define USB_CH_HCCHAR_ChEna_Pos (31U)
\r
18214 #define USB_CH_HCCHAR_ChEna_Msk (0x00000001U << USB_CH_HCCHAR_ChEna_Pos)
\r
18216 #define USB_CH_HCCHAR_ChDis_Pos (30U)
\r
18217 #define USB_CH_HCCHAR_ChDis_Msk (0x00000001U << USB_CH_HCCHAR_ChDis_Pos)
\r
18219 #define USB_CH_HCCHAR_OddFrm_Pos (29U)
\r
18220 #define USB_CH_HCCHAR_OddFrm_Msk (0x00000001U << USB_CH_HCCHAR_OddFrm_Pos)
\r
18222 #define USB_CH_HCCHAR_DevAddr_Pos (22U)
\r
18223 #define USB_CH_HCCHAR_DevAddr_Msk (0x0000007FU << USB_CH_HCCHAR_DevAddr_Pos)
\r
18225 #define USB_CH_HCCHAR_MC_EC_Pos (20U)
\r
18226 #define USB_CH_HCCHAR_MC_EC_Msk (0x00000003U << USB_CH_HCCHAR_MC_EC_Pos)
\r
18228 #define USB_CH_HCCHAR_EPType_Pos (18U)
\r
18229 #define USB_CH_HCCHAR_EPType_Msk (0x00000003U << USB_CH_HCCHAR_EPType_Pos)
\r
18231 #define USB_CH_HCCHAR_LSpdDev_Pos (17U)
\r
18232 #define USB_CH_HCCHAR_LSpdDev_Msk (0x00000001U << USB_CH_HCCHAR_LSpdDev_Pos)
\r
18234 #define USB_CH_HCCHAR_EPDir_Pos (15U)
\r
18235 #define USB_CH_HCCHAR_EPDir_Msk (0x00000001U << USB_CH_HCCHAR_EPDir_Pos)
\r
18237 #define USB_CH_HCCHAR_EPNum_Pos (11U)
\r
18238 #define USB_CH_HCCHAR_EPNum_Msk (0x0000000FU << USB_CH_HCCHAR_EPNum_Pos)
\r
18240 #define USB_CH_HCCHAR_MPS_Pos (0U)
\r
18241 #define USB_CH_HCCHAR_MPS_Msk (0x000007FFU << USB_CH_HCCHAR_MPS_Pos)
\r
18243 /* USB_CH_HCINTx = Host Channel-0 Interrupt Register*/
\r
18244 #define USB_CH_HCINT_DESC_LST_ROLLIntr_Pos (13U)
\r
18245 #define USB_CH_HCINT_DESC_LST_ROLLIntr_Msk (0x00000001U << USB_CH_HCINT_DESC_LST_ROLLIntr_Pos)
\r
18247 #define USB_CH_HCINT_XCS_XACT_ERR_Pos (12U)
\r
18248 #define USB_CH_HCINT_XCS_XACT_ERR_Msk (0x00000001U << USB_CH_HCINT_XCS_XACT_ERR_Pos)
\r
18250 #define USB_CH_HCINT_BNAIntr_Pos (11U)
\r
18251 #define USB_CH_HCINT_BNAIntr_Msk (0x00000001U << USB_CH_HCINT_BNAIntr_Pos)
\r
18253 #define USB_CH_HCINT_DataTglErr_Pos (10U)
\r
18254 #define USB_CH_HCINT_DataTglErr_Msk (0x00000001U << USB_CH_HCINT_DataTglErr_Pos)
\r
18256 #define USB_CH_HCINT_FrmOvrun_Pos (9U)
\r
18257 #define USB_CH_HCINT_FrmOvrun_Msk (0x00000001U << USB_CH_HCINT_FrmOvrun_Pos)
\r
18259 #define USB_CH_HCINT_BblErr_Pos (8U)
\r
18260 #define USB_CH_HCINT_BblErr_Msk (0x00000001U << USB_CH_HCINT_BblErr_Pos)
\r
18262 #define USB_CH_HCINT_XactErr_Pos (7U)
\r
18263 #define USB_CH_HCINT_XactErr_Msk (0x00000001U << USB_CH_HCINT_XactErr_Pos)
\r
18265 #define USB_CH_HCINT_NYET_Pos (6U)
\r
18266 #define USB_CH_HCINT_NYET_Msk (0x00000001U << USB_CH_HCINT_NYET_Pos)
\r
18268 #define USB_CH_HCINT_ACK_Pos (5U)
\r
18269 #define USB_CH_HCINT_ACK_Msk (0x00000001U << USB_CH_HCINT_ACK_Pos)
\r
18271 #define USB_CH_HCINT_NAK_Pos (4U)
\r
18272 #define USB_CH_HCINT_NAK_Msk (0x00000001U << USB_CH_HCINT_NAK_Pos)
\r
18274 #define USB_CH_HCINT_STALL_Pos (3U)
\r
18275 #define USB_CH_HCINT_STALL_Msk (0x00000001U << USB_CH_HCINT_STALL_Pos)
\r
18277 #define USB_CH_HCINT_AHBErr_Pos (2U)
\r
18278 #define USB_CH_HCINT_AHBErr_Msk (0x00000001U << USB_CH_HCINT_AHBErr_Pos)
\r
18280 #define USB_CH_HCINT_ChHltd_Pos (1U)
\r
18281 #define USB_CH_HCINT_ChHltd_Msk (0x00000001U << USB_CH_HCINT_ChHltd_Pos)
\r
18283 #define USB_CH_HCINT_XferCompl_Pos (0U)
\r
18284 #define USB_CH_HCINT_XferCompl_Msk (0x00000001U << USB_CH_HCINT_XferCompl_Pos)
\r
18286 /* USB_CH_HCINTMSKx = Host Channel-0 Interrupt Mask Register*/
\r
18287 #define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos (13U)
\r
18288 #define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Msk (0x00000001U << USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos)
\r
18290 #define USB_CH_HCINTMSK_BNAIntrMsk_Pos (11U)
\r
18291 #define USB_CH_HCINTMSK_BNAIntrMsk_Msk (0x00000001U << USB_CH_HCINTMSK_BNAIntrMsk_Pos)
\r
18293 #define USB_CH_HCINTMSK_DataTglErrMsk_Pos (10U)
\r
18294 #define USB_CH_HCINTMSK_DataTglErrMsk_Msk (0x00000001U << USB_CH_HCINTMSK_DataTglErrMsk_Pos)
\r
18296 #define USB_CH_HCINTMSK_FrmOvrunMsk_Pos (9U)
\r
18297 #define USB_CH_HCINTMSK_FrmOvrunMsk_Msk (0x00000001U << USB_CH_HCINTMSK_FrmOvrunMsk_Pos)
\r
18299 #define USB_CH_HCINTMSK_BblErrMsk_Pos (8U)
\r
18300 #define USB_CH_HCINTMSK_BblErrMsk_Msk (0x00000001U << USB_CH_HCINTMSK_BblErrMsk_Pos)
\r
18302 #define USB_CH_HCINTMSK_XactErrMsk_Pos (7U)
\r
18303 #define USB_CH_HCINTMSK_XactErrMsk_Msk (0x00000001U << USB_CH_HCINTMSK_XactErrMsk_Pos)
\r
18305 #define USB_CH_HCINTMSK_NyetMsk_Pos (6U)
\r
18306 #define USB_CH_HCINTMSK_NyetMsk_Msk (0x00000001U << USB_CH_HCINTMSK_NyetMsk_Pos)
\r
18308 #define USB_CH_HCINTMSK_AckMsk_Pos (5U)
\r
18309 #define USB_CH_HCINTMSK_AckMsk_Msk (0x00000001U << USB_CH_HCINTMSK_AckMsk_Pos)
\r
18311 #define USB_CH_HCINTMSK_NakMsk_Pos (4U)
\r
18312 #define USB_CH_HCINTMSK_NakMsk_Msk (0x00000001U << USB_CH_HCINTMSK_NakMsk_Pos)
\r
18314 #define USB_CH_HCINTMSK_StallMsk_Pos (3U)
\r
18315 #define USB_CH_HCINTMSK_StallMsk_Msk (0x00000001U << USB_CH_HCINTMSK_StallMsk_Pos)
\r
18317 #define USB_CH_HCINTMSK_AHBErrMsk_Pos (2U)
\r
18318 #define USB_CH_HCINTMSK_AHBErrMsk_Msk (0x00000001U << USB_CH_HCINTMSK_AHBErrMsk_Pos)
\r
18320 #define USB_CH_HCINTMSK_ChHltdMsk_Pos (1U)
\r
18321 #define USB_CH_HCINTMSK_ChHltdMsk_Msk (0x00000001U << USB_CH_HCINTMSK_ChHltdMsk_Pos)
\r
18323 #define USB_CH_HCINTMSK_XferComplMsk_Pos (0U)
\r
18324 #define USB_CH_HCINTMSK_XferComplMsk_Msk (0x00000001U << USB_CH_HCINTMSK_XferComplMsk_Pos)
\r
18326 /* USB_CH_HCTSIZ_SCATGATHER = Host Channel-0 Transfer Size Register [Scatter/Gather DMA Mode]*/
\r
18327 #define USB_CH_HCTSIZ_SCATGATHER_DoPng_Pos (31U)
\r
18328 #define USB_CH_HCTSIZ_SCATGATHER_DoPng_Msk (0x00000001U << USB_CH_HCTSIZ_SCATGATHER_DoPng_Pos)
\r
18330 #define USB_CH_HCTSIZ_SCATGATHER_Pid_Pos (29U)
\r
18331 #define USB_CH_HCTSIZ_SCATGATHER_Pid_Msk (0x00000003U << USB_CH_HCTSIZ_SCATGATHER_Pid_Pos)
\r
18333 #define USB_CH_HCTSIZ_SCATGATHER_NTD_Pos (8U)
\r
18334 #define USB_CH_HCTSIZ_SCATGATHER_NTD_Msk (0x000000FFU << USB_CH_HCTSIZ_SCATGATHER_NTD_Pos)
\r
18336 #define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos (0U)
\r
18337 #define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Msk (0x000000FFU << USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos)
\r
18339 /* USB_CH_HCTSIZ_BUFFERMODE = Host Channel-0 Transfer Size Register [Buffer DMA Mode]*/
\r
18340 #define USB_CH_HCTSIZ_BUFFERMODE_DoPng_Pos (31U)
\r
18341 #define USB_CH_HCTSIZ_BUFFERMODE_DoPng_Msk (0x00000001U << USB_CH_HCTSIZ_BUFFERMODE_DoPng_Pos)
\r
18343 #define USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos (29U)
\r
18344 #define USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk (0x00000003U << USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos)
\r
18346 #define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos (19U)
\r
18347 #define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk (0x000003FFU << USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos)
\r
18349 #define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos (0U)
\r
18350 #define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Msk (0x0007FFFFU << USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos)
\r
18352 /* USB_CH_HCDMA_SCATGATHER = Host Channel-0 DMA Address Register [Scatter/Gather DMA Mode]*/
\r
18353 #define USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos (9U)
\r
18354 #define USB_CH_HCDMA_SCATGATHER_DMAAddr_Msk (0x007FFFFFU << USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos)
\r
18356 #define USB_CH_HCDMA_SCATGATHER_CTD_Pos (3U)
\r
18357 #define USB_CH_HCDMA_SCATGATHER_CTD_Msk (0x0000003FU << USB_CH_HCDMA_SCATGATHER_CTD_Pos)
\r
18359 /* USB_CH_HCDMA_BUFFERMODE = Host Channel-0 DMA Address Register [Buffer DMA Mode]*/
\r
18360 #define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos (0U)
\r
18361 #define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Msk (0xFFFFFFFFU << USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos)
\r
18363 /* USB_CH_HCDMABx = Host Channel-0 DMA Buffer Address Register*/
\r
18364 #define USB_CH_HCDMAB_Buffer_Address_Pos (0U)
\r
18365 #define USB_CH_HCDMAB_Buffer_Address_Msk (0xFFFFFFFFU << USB_CH_HCDMAB_Buffer_Address_Pos)
\r
18369 /*** USICx Bit Fileds *******************/
\r
18370 /***************************************************************************/
\r
18373 /* USIC_ID = Module Identification Register*/
\r
18374 #define USIC_ID_MOD_REV_Pos (0U)
\r
18375 #define USIC_ID_MOD_REV_Msk (0x000000FFU << USIC_ID_MOD_REV_Pos)
\r
18377 #define USIC_ID_MOD_TYPE_Pos (8U)
\r
18378 #define USIC_ID_MOD_TYPE_Msk (0x000000FFU << USIC_ID_MOD_TYPE_Pos)
\r
18380 #define USIC_ID_MOD_NUMBER_Pos (16U)
\r
18381 #define USIC_ID_MOD_NUMBER_Msk (0x0000FFFFU << USIC_ID_MOD_NUMBER_Pos)
\r
18383 /* USIC_CH_CCFG = Channel Configuration Register*/
\r
18384 #define USIC_CH_CCFG_SSC_Pos (0U)
\r
18385 #define USIC_CH_CCFG_SSC_Msk (0x00000001U << USIC_CH_CCFG_SSC_Pos)
\r
18387 #define USIC_CH_CCFG_ASC_Pos (1U)
\r
18388 #define USIC_CH_CCFG_ASC_Msk (0x00000001U << USIC_CH_CCFG_ASC_Pos)
\r
18390 #define USIC_CH_CCFG_IIC_Pos (2U)
\r
18391 #define USIC_CH_CCFG_IIC_Msk (0x00000001U << USIC_CH_CCFG_IIC_Pos)
\r
18393 #define USIC_CH_CCFG_IIS_Pos (3U)
\r
18394 #define USIC_CH_CCFG_IIS_Msk (0x00000001U << USIC_CH_CCFG_IIS_Pos)
\r
18396 #define USIC_CH_CCFG_RB_Pos (6U)
\r
18397 #define USIC_CH_CCFG_RB_Msk (0x00000001U << USIC_CH_CCFG_RB_Pos)
\r
18399 #define USIC_CH_CCFG_TB_Pos (7U)
\r
18400 #define USIC_CH_CCFG_TB_Msk (0x00000001U << USIC_CH_CCFG_TB_Pos)
\r
18402 /* USIC_CH_KSCFG = Kernel State Configuration Register*/
\r
18403 #define USIC_CH_KSCFG_MODEN_Pos (0U)
\r
18404 #define USIC_CH_KSCFG_MODEN_Msk (0x00000001U << USIC_CH_KSCFG_MODEN_Pos)
\r
18406 #define USIC_CH_KSCFG_BPMODEN_Pos (1U)
\r
18407 #define USIC_CH_KSCFG_BPMODEN_Msk (0x00000001U << USIC_CH_KSCFG_BPMODEN_Pos)
\r
18409 #define USIC_CH_KSCFG_NOMCFG_Pos (4U)
\r
18410 #define USIC_CH_KSCFG_NOMCFG_Msk (0x00000003U << USIC_CH_KSCFG_NOMCFG_Pos)
\r
18412 #define USIC_CH_KSCFG_BPNOM_Pos (7U)
\r
18413 #define USIC_CH_KSCFG_BPNOM_Msk (0x00000001U << USIC_CH_KSCFG_BPNOM_Pos)
\r
18415 #define USIC_CH_KSCFG_SUMCFG_Pos (8U)
\r
18416 #define USIC_CH_KSCFG_SUMCFG_Msk (0x00000003U << USIC_CH_KSCFG_SUMCFG_Pos)
\r
18418 #define USIC_CH_KSCFG_BPSUM_Pos (11U)
\r
18419 #define USIC_CH_KSCFG_BPSUM_Msk (0x00000001U << USIC_CH_KSCFG_BPSUM_Pos)
\r
18421 /* USIC_CH_FDR = Fractional Divider Register*/
\r
18422 #define USIC_CH_FDR_STEP_Pos (0U)
\r
18423 #define USIC_CH_FDR_STEP_Msk (0x000003FFU << USIC_CH_FDR_STEP_Pos)
\r
18425 #define USIC_CH_FDR_DM_Pos (14U)
\r
18426 #define USIC_CH_FDR_DM_Msk (0x00000003U << USIC_CH_FDR_DM_Pos)
\r
18428 #define USIC_CH_FDR_RESULT_Pos (16U)
\r
18429 #define USIC_CH_FDR_RESULT_Msk (0x000003FFU << USIC_CH_FDR_RESULT_Pos)
\r
18431 /* USIC_CH_BRG = Baud Rate Generator Register*/
\r
18432 #define USIC_CH_BRG_CLKSEL_Pos (0U)
\r
18433 #define USIC_CH_BRG_CLKSEL_Msk (0x00000003U << USIC_CH_BRG_CLKSEL_Pos)
\r
18435 #define USIC_CH_BRG_TMEN_Pos (3U)
\r
18436 #define USIC_CH_BRG_TMEN_Msk (0x00000001U << USIC_CH_BRG_TMEN_Pos)
\r
18438 #define USIC_CH_BRG_PPPEN_Pos (4U)
\r
18439 #define USIC_CH_BRG_PPPEN_Msk (0x00000001U << USIC_CH_BRG_PPPEN_Pos)
\r
18441 #define USIC_CH_BRG_CTQSEL_Pos (6U)
\r
18442 #define USIC_CH_BRG_CTQSEL_Msk (0x00000003U << USIC_CH_BRG_CTQSEL_Pos)
\r
18444 #define USIC_CH_BRG_PCTQ_Pos (8U)
\r
18445 #define USIC_CH_BRG_PCTQ_Msk (0x00000003U << USIC_CH_BRG_PCTQ_Pos)
\r
18447 #define USIC_CH_BRG_DCTQ_Pos (10U)
\r
18448 #define USIC_CH_BRG_DCTQ_Msk (0x0000001FU << USIC_CH_BRG_DCTQ_Pos)
\r
18450 #define USIC_CH_BRG_PDIV_Pos (16U)
\r
18451 #define USIC_CH_BRG_PDIV_Msk (0x000003FFU << USIC_CH_BRG_PDIV_Pos)
\r
18453 #define USIC_CH_BRG_MCLKCFG_Pos (29U)
\r
18454 #define USIC_CH_BRG_MCLKCFG_Msk (0x00000001U << USIC_CH_BRG_MCLKCFG_Pos)
\r
18456 #define USIC_CH_BRG_SCLKCFG_Pos (30U)
\r
18457 #define USIC_CH_BRG_SCLKCFG_Msk (0x00000003U << USIC_CH_BRG_SCLKCFG_Pos)
\r
18459 /* USIC_CH_INPR = Interrupt Node Pointer Register*/
\r
18460 #define USIC_CH_INPR_TSINP_Pos (0U)
\r
18461 #define USIC_CH_INPR_TSINP_Msk (0x00000007U << USIC_CH_INPR_TSINP_Pos)
\r
18463 #define USIC_CH_INPR_TBINP_Pos (4U)
\r
18464 #define USIC_CH_INPR_TBINP_Msk (0x00000007U << USIC_CH_INPR_TBINP_Pos)
\r
18466 #define USIC_CH_INPR_RINP_Pos (8U)
\r
18467 #define USIC_CH_INPR_RINP_Msk (0x00000007U << USIC_CH_INPR_RINP_Pos)
\r
18469 #define USIC_CH_INPR_AINP_Pos (12U)
\r
18470 #define USIC_CH_INPR_AINP_Msk (0x00000007U << USIC_CH_INPR_AINP_Pos)
\r
18472 #define USIC_CH_INPR_PINP_Pos (16U)
\r
18473 #define USIC_CH_INPR_PINP_Msk (0x00000007U << USIC_CH_INPR_PINP_Pos)
\r
18475 /* USIC_CH_DX0CR = Input Control Register 0*/
\r
18476 #define USIC_CH_DX0CR_DSEL_Pos (0U)
\r
18477 #define USIC_CH_DX0CR_DSEL_Msk (0x00000007U << USIC_CH_DX0CR_DSEL_Pos)
\r
18479 #define USIC_CH_DX0CR_INSW_Pos (4U)
\r
18480 #define USIC_CH_DX0CR_INSW_Msk (0x00000001U << USIC_CH_DX0CR_INSW_Pos)
\r
18482 #define USIC_CH_DX0CR_DFEN_Pos (5U)
\r
18483 #define USIC_CH_DX0CR_DFEN_Msk (0x00000001U << USIC_CH_DX0CR_DFEN_Pos)
\r
18485 #define USIC_CH_DX0CR_DSEN_Pos (6U)
\r
18486 #define USIC_CH_DX0CR_DSEN_Msk (0x00000001U << USIC_CH_DX0CR_DSEN_Pos)
\r
18488 #define USIC_CH_DX0CR_DPOL_Pos (8U)
\r
18489 #define USIC_CH_DX0CR_DPOL_Msk (0x00000001U << USIC_CH_DX0CR_DPOL_Pos)
\r
18491 #define USIC_CH_DX0CR_SFSEL_Pos (9U)
\r
18492 #define USIC_CH_DX0CR_SFSEL_Msk (0x00000001U << USIC_CH_DX0CR_SFSEL_Pos)
\r
18494 #define USIC_CH_DX0CR_CM_Pos (10U)
\r
18495 #define USIC_CH_DX0CR_CM_Msk (0x00000003U << USIC_CH_DX0CR_CM_Pos)
\r
18497 #define USIC_CH_DX0CR_DXS_Pos (15U)
\r
18498 #define USIC_CH_DX0CR_DXS_Msk (0x00000001U << USIC_CH_DX0CR_DXS_Pos)
\r
18500 /* USIC_CH_DX1CR = Input Control Register 1*/
\r
18501 #define USIC_CH_DX1CR_DSEL_Pos (0U)
\r
18502 #define USIC_CH_DX1CR_DSEL_Msk (0x00000007U << USIC_CH_DX1CR_DSEL_Pos)
\r
18504 #define USIC_CH_DX1CR_DCEN_Pos (3U)
\r
18505 #define USIC_CH_DX1CR_DCEN_Msk (0x00000001U << USIC_CH_DX1CR_DCEN_Pos)
\r
18507 #define USIC_CH_DX1CR_INSW_Pos (4U)
\r
18508 #define USIC_CH_DX1CR_INSW_Msk (0x00000001U << USIC_CH_DX1CR_INSW_Pos)
\r
18510 #define USIC_CH_DX1CR_DFEN_Pos (5U)
\r
18511 #define USIC_CH_DX1CR_DFEN_Msk (0x00000001U << USIC_CH_DX1CR_DFEN_Pos)
\r
18513 #define USIC_CH_DX1CR_DSEN_Pos (6U)
\r
18514 #define USIC_CH_DX1CR_DSEN_Msk (0x00000001U << USIC_CH_DX1CR_DSEN_Pos)
\r
18516 #define USIC_CH_DX1CR_DPOL_Pos (8U)
\r
18517 #define USIC_CH_DX1CR_DPOL_Msk (0x00000001U << USIC_CH_DX1CR_DPOL_Pos)
\r
18519 #define USIC_CH_DX1CR_SFSEL_Pos (9U)
\r
18520 #define USIC_CH_DX1CR_SFSEL_Msk (0x00000001U << USIC_CH_DX1CR_SFSEL_Pos)
\r
18522 #define USIC_CH_DX1CR_CM_Pos (10U)
\r
18523 #define USIC_CH_DX1CR_CM_Msk (0x00000003U << USIC_CH_DX1CR_CM_Pos)
\r
18525 #define USIC_CH_DX1CR_DXS_Pos (15U)
\r
18526 #define USIC_CH_DX1CR_DXS_Msk (0x00000001U << USIC_CH_DX1CR_DXS_Pos)
\r
18528 /* USIC_CH_DX2CR = Input Control Register 2*/
\r
18529 #define USIC_CH_DX2CR_DSEL_Pos (0U)
\r
18530 #define USIC_CH_DX2CR_DSEL_Msk (0x00000007U << USIC_CH_DX2CR_DSEL_Pos)
\r
18532 #define USIC_CH_DX2CR_INSW_Pos (4U)
\r
18533 #define USIC_CH_DX2CR_INSW_Msk (0x00000001U << USIC_CH_DX2CR_INSW_Pos)
\r
18535 #define USIC_CH_DX2CR_DFEN_Pos (5U)
\r
18536 #define USIC_CH_DX2CR_DFEN_Msk (0x00000001U << USIC_CH_DX2CR_DFEN_Pos)
\r
18538 #define USIC_CH_DX2CR_DSEN_Pos (6U)
\r
18539 #define USIC_CH_DX2CR_DSEN_Msk (0x00000001U << USIC_CH_DX2CR_DSEN_Pos)
\r
18541 #define USIC_CH_DX2CR_DPOL_Pos (8U)
\r
18542 #define USIC_CH_DX2CR_DPOL_Msk (0x00000001U << USIC_CH_DX2CR_DPOL_Pos)
\r
18544 #define USIC_CH_DX2CR_SFSEL_Pos (9U)
\r
18545 #define USIC_CH_DX2CR_SFSEL_Msk (0x00000001U << USIC_CH_DX2CR_SFSEL_Pos)
\r
18547 #define USIC_CH_DX2CR_CM_Pos (10U)
\r
18548 #define USIC_CH_DX2CR_CM_Msk (0x00000003U << USIC_CH_DX2CR_CM_Pos)
\r
18550 #define USIC_CH_DX2CR_DXS_Pos (15U)
\r
18551 #define USIC_CH_DX2CR_DXS_Msk (0x00000001U << USIC_CH_DX2CR_DXS_Pos)
\r
18553 /* USIC_CH_DX3CR = Input Control Register 3*/
\r
18554 #define USIC_CH_DX3CR_DSEL_Pos (0U)
\r
18555 #define USIC_CH_DX3CR_DSEL_Msk (0x00000007U << USIC_CH_DX3CR_DSEL_Pos)
\r
18557 #define USIC_CH_DX3CR_INSW_Pos (4U)
\r
18558 #define USIC_CH_DX3CR_INSW_Msk (0x00000001U << USIC_CH_DX3CR_INSW_Pos)
\r
18560 #define USIC_CH_DX3CR_DFEN_Pos (5U)
\r
18561 #define USIC_CH_DX3CR_DFEN_Msk (0x00000001U << USIC_CH_DX3CR_DFEN_Pos)
\r
18563 #define USIC_CH_DX3CR_DSEN_Pos (6U)
\r
18564 #define USIC_CH_DX3CR_DSEN_Msk (0x00000001U << USIC_CH_DX3CR_DSEN_Pos)
\r
18566 #define USIC_CH_DX3CR_DPOL_Pos (8U)
\r
18567 #define USIC_CH_DX3CR_DPOL_Msk (0x00000001U << USIC_CH_DX3CR_DPOL_Pos)
\r
18569 #define USIC_CH_DX3CR_SFSEL_Pos (9U)
\r
18570 #define USIC_CH_DX3CR_SFSEL_Msk (0x00000001U << USIC_CH_DX3CR_SFSEL_Pos)
\r
18572 #define USIC_CH_DX3CR_CM_Pos (10U)
\r
18573 #define USIC_CH_DX3CR_CM_Msk (0x00000003U << USIC_CH_DX3CR_CM_Pos)
\r
18575 #define USIC_CH_DX3CR_DXS_Pos (15U)
\r
18576 #define USIC_CH_DX3CR_DXS_Msk (0x00000001U << USIC_CH_DX3CR_DXS_Pos)
\r
18578 /* USIC_CH_DX4CR = Input Control Register 4*/
\r
18579 #define USIC_CH_DX4CR_DSEL_Pos (0U)
\r
18580 #define USIC_CH_DX4CR_DSEL_Msk (0x00000007U << USIC_CH_DX4CR_DSEL_Pos)
\r
18582 #define USIC_CH_DX4CR_INSW_Pos (4U)
\r
18583 #define USIC_CH_DX4CR_INSW_Msk (0x00000001U << USIC_CH_DX4CR_INSW_Pos)
\r
18585 #define USIC_CH_DX4CR_DFEN_Pos (5U)
\r
18586 #define USIC_CH_DX4CR_DFEN_Msk (0x00000001U << USIC_CH_DX4CR_DFEN_Pos)
\r
18588 #define USIC_CH_DX4CR_DSEN_Pos (6U)
\r
18589 #define USIC_CH_DX4CR_DSEN_Msk (0x00000001U << USIC_CH_DX4CR_DSEN_Pos)
\r
18591 #define USIC_CH_DX4CR_DPOL_Pos (8U)
\r
18592 #define USIC_CH_DX4CR_DPOL_Msk (0x00000001U << USIC_CH_DX4CR_DPOL_Pos)
\r
18594 #define USIC_CH_DX4CR_SFSEL_Pos (9U)
\r
18595 #define USIC_CH_DX4CR_SFSEL_Msk (0x00000001U << USIC_CH_DX4CR_SFSEL_Pos)
\r
18597 #define USIC_CH_DX4CR_CM_Pos (10U)
\r
18598 #define USIC_CH_DX4CR_CM_Msk (0x00000003U << USIC_CH_DX4CR_CM_Pos)
\r
18600 #define USIC_CH_DX4CR_DXS_Pos (15U)
\r
18601 #define USIC_CH_DX4CR_DXS_Msk (0x00000001U << USIC_CH_DX4CR_DXS_Pos)
\r
18603 /* USIC_CH_DX5CR = Input Control Register 5*/
\r
18604 #define USIC_CH_DX5CR_DSEL_Pos (0U)
\r
18605 #define USIC_CH_DX5CR_DSEL_Msk (0x00000007U << USIC_CH_DX5CR_DSEL_Pos)
\r
18607 #define USIC_CH_DX5CR_INSW_Pos (4U)
\r
18608 #define USIC_CH_DX5CR_INSW_Msk (0x00000001U << USIC_CH_DX5CR_INSW_Pos)
\r
18610 #define USIC_CH_DX5CR_DFEN_Pos (5U)
\r
18611 #define USIC_CH_DX5CR_DFEN_Msk (0x00000001U << USIC_CH_DX5CR_DFEN_Pos)
\r
18613 #define USIC_CH_DX5CR_DSEN_Pos (6U)
\r
18614 #define USIC_CH_DX5CR_DSEN_Msk (0x00000001U << USIC_CH_DX5CR_DSEN_Pos)
\r
18616 #define USIC_CH_DX5CR_DPOL_Pos (8U)
\r
18617 #define USIC_CH_DX5CR_DPOL_Msk (0x00000001U << USIC_CH_DX5CR_DPOL_Pos)
\r
18619 #define USIC_CH_DX5CR_SFSEL_Pos (9U)
\r
18620 #define USIC_CH_DX5CR_SFSEL_Msk (0x00000001U << USIC_CH_DX5CR_SFSEL_Pos)
\r
18622 #define USIC_CH_DX5CR_CM_Pos (10U)
\r
18623 #define USIC_CH_DX5CR_CM_Msk (0x00000003U << USIC_CH_DX5CR_CM_Pos)
\r
18625 #define USIC_CH_DX5CR_DXS_Pos (15U)
\r
18626 #define USIC_CH_DX5CR_DXS_Msk (0x00000001U << USIC_CH_DX5CR_DXS_Pos)
\r
18628 /* USIC_CH_SCTR = Shift Control Register*/
\r
18629 #define USIC_CH_SCTR_SDIR_Pos (0U)
\r
18630 #define USIC_CH_SCTR_SDIR_Msk (0x00000001U << USIC_CH_SCTR_SDIR_Pos)
\r
18632 #define USIC_CH_SCTR_PDL_Pos (1U)
\r
18633 #define USIC_CH_SCTR_PDL_Msk (0x00000001U << USIC_CH_SCTR_PDL_Pos)
\r
18635 #define USIC_CH_SCTR_DSM_Pos (2U)
\r
18636 #define USIC_CH_SCTR_DSM_Msk (0x00000003U << USIC_CH_SCTR_DSM_Pos)
\r
18638 #define USIC_CH_SCTR_HPCDIR_Pos (4U)
\r
18639 #define USIC_CH_SCTR_HPCDIR_Msk (0x00000001U << USIC_CH_SCTR_HPCDIR_Pos)
\r
18641 #define USIC_CH_SCTR_DOCFG_Pos (6U)
\r
18642 #define USIC_CH_SCTR_DOCFG_Msk (0x00000003U << USIC_CH_SCTR_DOCFG_Pos)
\r
18644 #define USIC_CH_SCTR_TRM_Pos (8U)
\r
18645 #define USIC_CH_SCTR_TRM_Msk (0x00000003U << USIC_CH_SCTR_TRM_Pos)
\r
18647 #define USIC_CH_SCTR_FLE_Pos (16U)
\r
18648 #define USIC_CH_SCTR_FLE_Msk (0x0000003FU << USIC_CH_SCTR_FLE_Pos)
\r
18650 #define USIC_CH_SCTR_WLE_Pos (24U)
\r
18651 #define USIC_CH_SCTR_WLE_Msk (0x0000000FU << USIC_CH_SCTR_WLE_Pos)
\r
18653 /* USIC_CH_TCSR = Transmit Control/Status Register*/
\r
18654 #define USIC_CH_TCSR_WLEMD_Pos (0U)
\r
18655 #define USIC_CH_TCSR_WLEMD_Msk (0x00000001U << USIC_CH_TCSR_WLEMD_Pos)
\r
18657 #define USIC_CH_TCSR_SELMD_Pos (1U)
\r
18658 #define USIC_CH_TCSR_SELMD_Msk (0x00000001U << USIC_CH_TCSR_SELMD_Pos)
\r
18660 #define USIC_CH_TCSR_FLEMD_Pos (2U)
\r
18661 #define USIC_CH_TCSR_FLEMD_Msk (0x00000001U << USIC_CH_TCSR_FLEMD_Pos)
\r
18663 #define USIC_CH_TCSR_WAMD_Pos (3U)
\r
18664 #define USIC_CH_TCSR_WAMD_Msk (0x00000001U << USIC_CH_TCSR_WAMD_Pos)
\r
18666 #define USIC_CH_TCSR_HPCMD_Pos (4U)
\r
18667 #define USIC_CH_TCSR_HPCMD_Msk (0x00000001U << USIC_CH_TCSR_HPCMD_Pos)
\r
18669 #define USIC_CH_TCSR_SOF_Pos (5U)
\r
18670 #define USIC_CH_TCSR_SOF_Msk (0x00000001U << USIC_CH_TCSR_SOF_Pos)
\r
18672 #define USIC_CH_TCSR_EOF_Pos (6U)
\r
18673 #define USIC_CH_TCSR_EOF_Msk (0x00000001U << USIC_CH_TCSR_EOF_Pos)
\r
18675 #define USIC_CH_TCSR_TDV_Pos (7U)
\r
18676 #define USIC_CH_TCSR_TDV_Msk (0x00000001U << USIC_CH_TCSR_TDV_Pos)
\r
18678 #define USIC_CH_TCSR_TDSSM_Pos (8U)
\r
18679 #define USIC_CH_TCSR_TDSSM_Msk (0x00000001U << USIC_CH_TCSR_TDSSM_Pos)
\r
18681 #define USIC_CH_TCSR_TDEN_Pos (10U)
\r
18682 #define USIC_CH_TCSR_TDEN_Msk (0x00000003U << USIC_CH_TCSR_TDEN_Pos)
\r
18684 #define USIC_CH_TCSR_TDVTR_Pos (12U)
\r
18685 #define USIC_CH_TCSR_TDVTR_Msk (0x00000001U << USIC_CH_TCSR_TDVTR_Pos)
\r
18687 #define USIC_CH_TCSR_WA_Pos (13U)
\r
18688 #define USIC_CH_TCSR_WA_Msk (0x00000001U << USIC_CH_TCSR_WA_Pos)
\r
18690 #define USIC_CH_TCSR_TSOF_Pos (24U)
\r
18691 #define USIC_CH_TCSR_TSOF_Msk (0x00000001U << USIC_CH_TCSR_TSOF_Pos)
\r
18693 #define USIC_CH_TCSR_TV_Pos (26U)
\r
18694 #define USIC_CH_TCSR_TV_Msk (0x00000001U << USIC_CH_TCSR_TV_Pos)
\r
18696 #define USIC_CH_TCSR_TVC_Pos (27U)
\r
18697 #define USIC_CH_TCSR_TVC_Msk (0x00000001U << USIC_CH_TCSR_TVC_Pos)
\r
18699 #define USIC_CH_TCSR_TE_Pos (28U)
\r
18700 #define USIC_CH_TCSR_TE_Msk (0x00000001U << USIC_CH_TCSR_TE_Pos)
\r
18702 /* USIC_CH_PCR = Protocol Control Register*/
\r
18703 #define USIC_CH_PCR_CTR0_Pos (0U)
\r
18704 #define USIC_CH_PCR_CTR0_Msk (0x00000001U << USIC_CH_PCR_CTR0_Pos)
\r
18706 #define USIC_CH_PCR_CTR1_Pos (1U)
\r
18707 #define USIC_CH_PCR_CTR1_Msk (0x00000001U << USIC_CH_PCR_CTR1_Pos)
\r
18709 #define USIC_CH_PCR_CTR2_Pos (2U)
\r
18710 #define USIC_CH_PCR_CTR2_Msk (0x00000001U << USIC_CH_PCR_CTR2_Pos)
\r
18712 #define USIC_CH_PCR_CTR3_Pos (3U)
\r
18713 #define USIC_CH_PCR_CTR3_Msk (0x00000001U << USIC_CH_PCR_CTR3_Pos)
\r
18715 #define USIC_CH_PCR_CTR4_Pos (4U)
\r
18716 #define USIC_CH_PCR_CTR4_Msk (0x00000001U << USIC_CH_PCR_CTR4_Pos)
\r
18718 #define USIC_CH_PCR_CTR5_Pos (5U)
\r
18719 #define USIC_CH_PCR_CTR5_Msk (0x00000001U << USIC_CH_PCR_CTR5_Pos)
\r
18721 #define USIC_CH_PCR_CTR6_Pos (6U)
\r
18722 #define USIC_CH_PCR_CTR6_Msk (0x00000001U << USIC_CH_PCR_CTR6_Pos)
\r
18724 #define USIC_CH_PCR_CTR7_Pos (7U)
\r
18725 #define USIC_CH_PCR_CTR7_Msk (0x00000001U << USIC_CH_PCR_CTR7_Pos)
\r
18727 #define USIC_CH_PCR_CTR8_Pos (8U)
\r
18728 #define USIC_CH_PCR_CTR8_Msk (0x00000001U << USIC_CH_PCR_CTR8_Pos)
\r
18730 #define USIC_CH_PCR_CTR9_Pos (9U)
\r
18731 #define USIC_CH_PCR_CTR9_Msk (0x00000001U << USIC_CH_PCR_CTR9_Pos)
\r
18733 #define USIC_CH_PCR_CTR10_Pos (10U)
\r
18734 #define USIC_CH_PCR_CTR10_Msk (0x00000001U << USIC_CH_PCR_CTR10_Pos)
\r
18736 #define USIC_CH_PCR_CTR11_Pos (11U)
\r
18737 #define USIC_CH_PCR_CTR11_Msk (0x00000001U << USIC_CH_PCR_CTR11_Pos)
\r
18739 #define USIC_CH_PCR_CTR12_Pos (12U)
\r
18740 #define USIC_CH_PCR_CTR12_Msk (0x00000001U << USIC_CH_PCR_CTR12_Pos)
\r
18742 #define USIC_CH_PCR_CTR13_Pos (13U)
\r
18743 #define USIC_CH_PCR_CTR13_Msk (0x00000001U << USIC_CH_PCR_CTR13_Pos)
\r
18745 #define USIC_CH_PCR_CTR14_Pos (14U)
\r
18746 #define USIC_CH_PCR_CTR14_Msk (0x00000001U << USIC_CH_PCR_CTR14_Pos)
\r
18748 #define USIC_CH_PCR_CTR15_Pos (15U)
\r
18749 #define USIC_CH_PCR_CTR15_Msk (0x00000001U << USIC_CH_PCR_CTR15_Pos)
\r
18751 #define USIC_CH_PCR_CTR16_Pos (16U)
\r
18752 #define USIC_CH_PCR_CTR16_Msk (0x00000001U << USIC_CH_PCR_CTR16_Pos)
\r
18754 #define USIC_CH_PCR_CTR17_Pos (17U)
\r
18755 #define USIC_CH_PCR_CTR17_Msk (0x00000001U << USIC_CH_PCR_CTR17_Pos)
\r
18757 #define USIC_CH_PCR_CTR18_Pos (18U)
\r
18758 #define USIC_CH_PCR_CTR18_Msk (0x00000001U << USIC_CH_PCR_CTR18_Pos)
\r
18760 #define USIC_CH_PCR_CTR19_Pos (19U)
\r
18761 #define USIC_CH_PCR_CTR19_Msk (0x00000001U << USIC_CH_PCR_CTR19_Pos)
\r
18763 #define USIC_CH_PCR_CTR20_Pos (20U)
\r
18764 #define USIC_CH_PCR_CTR20_Msk (0x00000001U << USIC_CH_PCR_CTR20_Pos)
\r
18766 #define USIC_CH_PCR_CTR21_Pos (21U)
\r
18767 #define USIC_CH_PCR_CTR21_Msk (0x00000001U << USIC_CH_PCR_CTR21_Pos)
\r
18769 #define USIC_CH_PCR_CTR22_Pos (22U)
\r
18770 #define USIC_CH_PCR_CTR22_Msk (0x00000001U << USIC_CH_PCR_CTR22_Pos)
\r
18772 #define USIC_CH_PCR_CTR23_Pos (23U)
\r
18773 #define USIC_CH_PCR_CTR23_Msk (0x00000001U << USIC_CH_PCR_CTR23_Pos)
\r
18775 #define USIC_CH_PCR_CTR24_Pos (24U)
\r
18776 #define USIC_CH_PCR_CTR24_Msk (0x00000001U << USIC_CH_PCR_CTR24_Pos)
\r
18778 #define USIC_CH_PCR_CTR25_Pos (25U)
\r
18779 #define USIC_CH_PCR_CTR25_Msk (0x00000001U << USIC_CH_PCR_CTR25_Pos)
\r
18781 #define USIC_CH_PCR_CTR26_Pos (26U)
\r
18782 #define USIC_CH_PCR_CTR26_Msk (0x00000001U << USIC_CH_PCR_CTR26_Pos)
\r
18784 #define USIC_CH_PCR_CTR27_Pos (27U)
\r
18785 #define USIC_CH_PCR_CTR27_Msk (0x00000001U << USIC_CH_PCR_CTR27_Pos)
\r
18787 #define USIC_CH_PCR_CTR28_Pos (28U)
\r
18788 #define USIC_CH_PCR_CTR28_Msk (0x00000001U << USIC_CH_PCR_CTR28_Pos)
\r
18790 #define USIC_CH_PCR_CTR29_Pos (29U)
\r
18791 #define USIC_CH_PCR_CTR29_Msk (0x00000001U << USIC_CH_PCR_CTR29_Pos)
\r
18793 #define USIC_CH_PCR_CTR30_Pos (30U)
\r
18794 #define USIC_CH_PCR_CTR30_Msk (0x00000001U << USIC_CH_PCR_CTR30_Pos)
\r
18796 #define USIC_CH_PCR_CTR31_Pos (31U)
\r
18797 #define USIC_CH_PCR_CTR31_Msk (0x00000001U << USIC_CH_PCR_CTR31_Pos)
\r
18799 /* USIC_CH_PCR_ASCMode = Protocol Control Register [ASC Mode]*/
\r
18800 #define USIC_CH_PCR_ASCMode_SMD_Pos (0U)
\r
18801 #define USIC_CH_PCR_ASCMode_SMD_Msk (0x00000001U << USIC_CH_PCR_ASCMode_SMD_Pos)
\r
18803 #define USIC_CH_PCR_ASCMode_STPB_Pos (1U)
\r
18804 #define USIC_CH_PCR_ASCMode_STPB_Msk (0x00000001U << USIC_CH_PCR_ASCMode_STPB_Pos)
\r
18806 #define USIC_CH_PCR_ASCMode_IDM_Pos (2U)
\r
18807 #define USIC_CH_PCR_ASCMode_IDM_Msk (0x00000001U << USIC_CH_PCR_ASCMode_IDM_Pos)
\r
18809 #define USIC_CH_PCR_ASCMode_SBIEN_Pos (3U)
\r
18810 #define USIC_CH_PCR_ASCMode_SBIEN_Msk (0x00000001U << USIC_CH_PCR_ASCMode_SBIEN_Pos)
\r
18812 #define USIC_CH_PCR_ASCMode_CDEN_Pos (4U)
\r
18813 #define USIC_CH_PCR_ASCMode_CDEN_Msk (0x00000001U << USIC_CH_PCR_ASCMode_CDEN_Pos)
\r
18815 #define USIC_CH_PCR_ASCMode_RNIEN_Pos (5U)
\r
18816 #define USIC_CH_PCR_ASCMode_RNIEN_Msk (0x00000001U << USIC_CH_PCR_ASCMode_RNIEN_Pos)
\r
18818 #define USIC_CH_PCR_ASCMode_FEIEN_Pos (6U)
\r
18819 #define USIC_CH_PCR_ASCMode_FEIEN_Msk (0x00000001U << USIC_CH_PCR_ASCMode_FEIEN_Pos)
\r
18821 #define USIC_CH_PCR_ASCMode_FFIEN_Pos (7U)
\r
18822 #define USIC_CH_PCR_ASCMode_FFIEN_Msk (0x00000001U << USIC_CH_PCR_ASCMode_FFIEN_Pos)
\r
18824 #define USIC_CH_PCR_ASCMode_SP_Pos (8U)
\r
18825 #define USIC_CH_PCR_ASCMode_SP_Msk (0x0000001FU << USIC_CH_PCR_ASCMode_SP_Pos)
\r
18827 #define USIC_CH_PCR_ASCMode_PL_Pos (13U)
\r
18828 #define USIC_CH_PCR_ASCMode_PL_Msk (0x00000007U << USIC_CH_PCR_ASCMode_PL_Pos)
\r
18830 #define USIC_CH_PCR_ASCMode_RSTEN_Pos (16U)
\r
18831 #define USIC_CH_PCR_ASCMode_RSTEN_Msk (0x00000001U << USIC_CH_PCR_ASCMode_RSTEN_Pos)
\r
18833 #define USIC_CH_PCR_ASCMode_TSTEN_Pos (17U)
\r
18834 #define USIC_CH_PCR_ASCMode_TSTEN_Msk (0x00000001U << USIC_CH_PCR_ASCMode_TSTEN_Pos)
\r
18836 #define USIC_CH_PCR_ASCMode_MCLK_Pos (31U)
\r
18837 #define USIC_CH_PCR_ASCMode_MCLK_Msk (0x00000001U << USIC_CH_PCR_ASCMode_MCLK_Pos)
\r
18839 /* USIC_CH_PCR_SSCMode = Protocol Control Register [SSC Mode]*/
\r
18840 #define USIC_CH_PCR_SSCMode_MSLSEN_Pos (0U)
\r
18841 #define USIC_CH_PCR_SSCMode_MSLSEN_Msk (0x00000001U << USIC_CH_PCR_SSCMode_MSLSEN_Pos)
\r
18843 #define USIC_CH_PCR_SSCMode_SELCTR_Pos (1U)
\r
18844 #define USIC_CH_PCR_SSCMode_SELCTR_Msk (0x00000001U << USIC_CH_PCR_SSCMode_SELCTR_Pos)
\r
18846 #define USIC_CH_PCR_SSCMode_SELINV_Pos (2U)
\r
18847 #define USIC_CH_PCR_SSCMode_SELINV_Msk (0x00000001U << USIC_CH_PCR_SSCMode_SELINV_Pos)
\r
18849 #define USIC_CH_PCR_SSCMode_FEM_Pos (3U)
\r
18850 #define USIC_CH_PCR_SSCMode_FEM_Msk (0x00000001U << USIC_CH_PCR_SSCMode_FEM_Pos)
\r
18852 #define USIC_CH_PCR_SSCMode_CTQSEL1_Pos (4U)
\r
18853 #define USIC_CH_PCR_SSCMode_CTQSEL1_Msk (0x00000003U << USIC_CH_PCR_SSCMode_CTQSEL1_Pos)
\r
18855 #define USIC_CH_PCR_SSCMode_PCTQ1_Pos (6U)
\r
18856 #define USIC_CH_PCR_SSCMode_PCTQ1_Msk (0x00000003U << USIC_CH_PCR_SSCMode_PCTQ1_Pos)
\r
18858 #define USIC_CH_PCR_SSCMode_DCTQ1_Pos (8U)
\r
18859 #define USIC_CH_PCR_SSCMode_DCTQ1_Msk (0x0000001FU << USIC_CH_PCR_SSCMode_DCTQ1_Pos)
\r
18861 #define USIC_CH_PCR_SSCMode_PARIEN_Pos (13U)
\r
18862 #define USIC_CH_PCR_SSCMode_PARIEN_Msk (0x00000001U << USIC_CH_PCR_SSCMode_PARIEN_Pos)
\r
18864 #define USIC_CH_PCR_SSCMode_MSLSIEN_Pos (14U)
\r
18865 #define USIC_CH_PCR_SSCMode_MSLSIEN_Msk (0x00000001U << USIC_CH_PCR_SSCMode_MSLSIEN_Pos)
\r
18867 #define USIC_CH_PCR_SSCMode_DX2TIEN_Pos (15U)
\r
18868 #define USIC_CH_PCR_SSCMode_DX2TIEN_Msk (0x00000001U << USIC_CH_PCR_SSCMode_DX2TIEN_Pos)
\r
18870 #define USIC_CH_PCR_SSCMode_SELO_Pos (16U)
\r
18871 #define USIC_CH_PCR_SSCMode_SELO_Msk (0x000000FFU << USIC_CH_PCR_SSCMode_SELO_Pos)
\r
18873 #define USIC_CH_PCR_SSCMode_TIWEN_Pos (24U)
\r
18874 #define USIC_CH_PCR_SSCMode_TIWEN_Msk (0x00000001U << USIC_CH_PCR_SSCMode_TIWEN_Pos)
\r
18876 #define USIC_CH_PCR_SSCMode_MCLK_Pos (31U)
\r
18877 #define USIC_CH_PCR_SSCMode_MCLK_Msk (0x00000001U << USIC_CH_PCR_SSCMode_MCLK_Pos)
\r
18879 /* USIC_CH_PCR_IISMode = Protocol Control Register [IIS Mode]*/
\r
18880 #define USIC_CH_PCR_IISMode_WAGEN_Pos (0U)
\r
18881 #define USIC_CH_PCR_IISMode_WAGEN_Msk (0x00000001U << USIC_CH_PCR_IISMode_WAGEN_Pos)
\r
18883 #define USIC_CH_PCR_IISMode_DTEN_Pos (1U)
\r
18884 #define USIC_CH_PCR_IISMode_DTEN_Msk (0x00000001U << USIC_CH_PCR_IISMode_DTEN_Pos)
\r
18886 #define USIC_CH_PCR_IISMode_SELINV_Pos (2U)
\r
18887 #define USIC_CH_PCR_IISMode_SELINV_Msk (0x00000001U << USIC_CH_PCR_IISMode_SELINV_Pos)
\r
18889 #define USIC_CH_PCR_IISMode_WAFEIEN_Pos (4U)
\r
18890 #define USIC_CH_PCR_IISMode_WAFEIEN_Msk (0x00000001U << USIC_CH_PCR_IISMode_WAFEIEN_Pos)
\r
18892 #define USIC_CH_PCR_IISMode_WAREIEN_Pos (5U)
\r
18893 #define USIC_CH_PCR_IISMode_WAREIEN_Msk (0x00000001U << USIC_CH_PCR_IISMode_WAREIEN_Pos)
\r
18895 #define USIC_CH_PCR_IISMode_ENDIEN_Pos (6U)
\r
18896 #define USIC_CH_PCR_IISMode_ENDIEN_Msk (0x00000001U << USIC_CH_PCR_IISMode_ENDIEN_Pos)
\r
18898 #define USIC_CH_PCR_IISMode_DX2TIEN_Pos (15U)
\r
18899 #define USIC_CH_PCR_IISMode_DX2TIEN_Msk (0x00000001U << USIC_CH_PCR_IISMode_DX2TIEN_Pos)
\r
18901 #define USIC_CH_PCR_IISMode_TDEL_Pos (16U)
\r
18902 #define USIC_CH_PCR_IISMode_TDEL_Msk (0x0000003FU << USIC_CH_PCR_IISMode_TDEL_Pos)
\r
18904 #define USIC_CH_PCR_IISMode_MCLK_Pos (31U)
\r
18905 #define USIC_CH_PCR_IISMode_MCLK_Msk (0x00000001U << USIC_CH_PCR_IISMode_MCLK_Pos)
\r
18907 /* USIC_CH_PCR_IICMode = Protocol Control Register [IIC Mode]*/
\r
18908 #define USIC_CH_PCR_IICMode_SLAD_Pos (0U)
\r
18909 #define USIC_CH_PCR_IICMode_SLAD_Msk (0x0000FFFFU << USIC_CH_PCR_IICMode_SLAD_Pos)
\r
18911 #define USIC_CH_PCR_IICMode_ACK00_Pos (16U)
\r
18912 #define USIC_CH_PCR_IICMode_ACK00_Msk (0x00000001U << USIC_CH_PCR_IICMode_ACK00_Pos)
\r
18914 #define USIC_CH_PCR_IICMode_STIM_Pos (17U)
\r
18915 #define USIC_CH_PCR_IICMode_STIM_Msk (0x00000001U << USIC_CH_PCR_IICMode_STIM_Pos)
\r
18917 #define USIC_CH_PCR_IICMode_SCRIEN_Pos (18U)
\r
18918 #define USIC_CH_PCR_IICMode_SCRIEN_Msk (0x00000001U << USIC_CH_PCR_IICMode_SCRIEN_Pos)
\r
18920 #define USIC_CH_PCR_IICMode_RSCRIEN_Pos (19U)
\r
18921 #define USIC_CH_PCR_IICMode_RSCRIEN_Msk (0x00000001U << USIC_CH_PCR_IICMode_RSCRIEN_Pos)
\r
18923 #define USIC_CH_PCR_IICMode_PCRIEN_Pos (20U)
\r
18924 #define USIC_CH_PCR_IICMode_PCRIEN_Msk (0x00000001U << USIC_CH_PCR_IICMode_PCRIEN_Pos)
\r
18926 #define USIC_CH_PCR_IICMode_NACKIEN_Pos (21U)
\r
18927 #define USIC_CH_PCR_IICMode_NACKIEN_Msk (0x00000001U << USIC_CH_PCR_IICMode_NACKIEN_Pos)
\r
18929 #define USIC_CH_PCR_IICMode_ARLIEN_Pos (22U)
\r
18930 #define USIC_CH_PCR_IICMode_ARLIEN_Msk (0x00000001U << USIC_CH_PCR_IICMode_ARLIEN_Pos)
\r
18932 #define USIC_CH_PCR_IICMode_SRRIEN_Pos (23U)
\r
18933 #define USIC_CH_PCR_IICMode_SRRIEN_Msk (0x00000001U << USIC_CH_PCR_IICMode_SRRIEN_Pos)
\r
18935 #define USIC_CH_PCR_IICMode_ERRIEN_Pos (24U)
\r
18936 #define USIC_CH_PCR_IICMode_ERRIEN_Msk (0x00000001U << USIC_CH_PCR_IICMode_ERRIEN_Pos)
\r
18938 #define USIC_CH_PCR_IICMode_SACKDIS_Pos (25U)
\r
18939 #define USIC_CH_PCR_IICMode_SACKDIS_Msk (0x00000001U << USIC_CH_PCR_IICMode_SACKDIS_Pos)
\r
18941 #define USIC_CH_PCR_IICMode_HDEL_Pos (26U)
\r
18942 #define USIC_CH_PCR_IICMode_HDEL_Msk (0x0000000FU << USIC_CH_PCR_IICMode_HDEL_Pos)
\r
18944 #define USIC_CH_PCR_IICMode_ACKIEN_Pos (30U)
\r
18945 #define USIC_CH_PCR_IICMode_ACKIEN_Msk (0x00000001U << USIC_CH_PCR_IICMode_ACKIEN_Pos)
\r
18947 #define USIC_CH_PCR_IICMode_MCLK_Pos (31U)
\r
18948 #define USIC_CH_PCR_IICMode_MCLK_Msk (0x00000001U << USIC_CH_PCR_IICMode_MCLK_Pos)
\r
18950 /* USIC_CH_CCR = Channel Control Register*/
\r
18951 #define USIC_CH_CCR_MODE_Pos (0U)
\r
18952 #define USIC_CH_CCR_MODE_Msk (0x0000000FU << USIC_CH_CCR_MODE_Pos)
\r
18954 #define USIC_CH_CCR_HPCEN_Pos (6U)
\r
18955 #define USIC_CH_CCR_HPCEN_Msk (0x00000003U << USIC_CH_CCR_HPCEN_Pos)
\r
18957 #define USIC_CH_CCR_PM_Pos (8U)
\r
18958 #define USIC_CH_CCR_PM_Msk (0x00000003U << USIC_CH_CCR_PM_Pos)
\r
18960 #define USIC_CH_CCR_RSIEN_Pos (10U)
\r
18961 #define USIC_CH_CCR_RSIEN_Msk (0x00000001U << USIC_CH_CCR_RSIEN_Pos)
\r
18963 #define USIC_CH_CCR_DLIEN_Pos (11U)
\r
18964 #define USIC_CH_CCR_DLIEN_Msk (0x00000001U << USIC_CH_CCR_DLIEN_Pos)
\r
18966 #define USIC_CH_CCR_TSIEN_Pos (12U)
\r
18967 #define USIC_CH_CCR_TSIEN_Msk (0x00000001U << USIC_CH_CCR_TSIEN_Pos)
\r
18969 #define USIC_CH_CCR_TBIEN_Pos (13U)
\r
18970 #define USIC_CH_CCR_TBIEN_Msk (0x00000001U << USIC_CH_CCR_TBIEN_Pos)
\r
18972 #define USIC_CH_CCR_RIEN_Pos (14U)
\r
18973 #define USIC_CH_CCR_RIEN_Msk (0x00000001U << USIC_CH_CCR_RIEN_Pos)
\r
18975 #define USIC_CH_CCR_AIEN_Pos (15U)
\r
18976 #define USIC_CH_CCR_AIEN_Msk (0x00000001U << USIC_CH_CCR_AIEN_Pos)
\r
18978 #define USIC_CH_CCR_BRGIEN_Pos (16U)
\r
18979 #define USIC_CH_CCR_BRGIEN_Msk (0x00000001U << USIC_CH_CCR_BRGIEN_Pos)
\r
18981 /* USIC_CH_CMTR = Capture Mode Timer Register*/
\r
18982 #define USIC_CH_CMTR_CTV_Pos (0U)
\r
18983 #define USIC_CH_CMTR_CTV_Msk (0x000003FFU << USIC_CH_CMTR_CTV_Pos)
\r
18985 /* USIC_CH_PSR = Protocol Status Register*/
\r
18986 #define USIC_CH_PSR_ST0_Pos (0U)
\r
18987 #define USIC_CH_PSR_ST0_Msk (0x00000001U << USIC_CH_PSR_ST0_Pos)
\r
18989 #define USIC_CH_PSR_ST1_Pos (1U)
\r
18990 #define USIC_CH_PSR_ST1_Msk (0x00000001U << USIC_CH_PSR_ST1_Pos)
\r
18992 #define USIC_CH_PSR_ST2_Pos (2U)
\r
18993 #define USIC_CH_PSR_ST2_Msk (0x00000001U << USIC_CH_PSR_ST2_Pos)
\r
18995 #define USIC_CH_PSR_ST3_Pos (3U)
\r
18996 #define USIC_CH_PSR_ST3_Msk (0x00000001U << USIC_CH_PSR_ST3_Pos)
\r
18998 #define USIC_CH_PSR_ST4_Pos (4U)
\r
18999 #define USIC_CH_PSR_ST4_Msk (0x00000001U << USIC_CH_PSR_ST4_Pos)
\r
19001 #define USIC_CH_PSR_ST5_Pos (5U)
\r
19002 #define USIC_CH_PSR_ST5_Msk (0x00000001U << USIC_CH_PSR_ST5_Pos)
\r
19004 #define USIC_CH_PSR_ST6_Pos (6U)
\r
19005 #define USIC_CH_PSR_ST6_Msk (0x00000001U << USIC_CH_PSR_ST6_Pos)
\r
19007 #define USIC_CH_PSR_ST7_Pos (7U)
\r
19008 #define USIC_CH_PSR_ST7_Msk (0x00000001U << USIC_CH_PSR_ST7_Pos)
\r
19010 #define USIC_CH_PSR_ST8_Pos (8U)
\r
19011 #define USIC_CH_PSR_ST8_Msk (0x00000001U << USIC_CH_PSR_ST8_Pos)
\r
19013 #define USIC_CH_PSR_ST9_Pos (9U)
\r
19014 #define USIC_CH_PSR_ST9_Msk (0x00000001U << USIC_CH_PSR_ST9_Pos)
\r
19016 #define USIC_CH_PSR_RSIF_Pos (10U)
\r
19017 #define USIC_CH_PSR_RSIF_Msk (0x00000001U << USIC_CH_PSR_RSIF_Pos)
\r
19019 #define USIC_CH_PSR_DLIF_Pos (11U)
\r
19020 #define USIC_CH_PSR_DLIF_Msk (0x00000001U << USIC_CH_PSR_DLIF_Pos)
\r
19022 #define USIC_CH_PSR_TSIF_Pos (12U)
\r
19023 #define USIC_CH_PSR_TSIF_Msk (0x00000001U << USIC_CH_PSR_TSIF_Pos)
\r
19025 #define USIC_CH_PSR_TBIF_Pos (13U)
\r
19026 #define USIC_CH_PSR_TBIF_Msk (0x00000001U << USIC_CH_PSR_TBIF_Pos)
\r
19028 #define USIC_CH_PSR_RIF_Pos (14U)
\r
19029 #define USIC_CH_PSR_RIF_Msk (0x00000001U << USIC_CH_PSR_RIF_Pos)
\r
19031 #define USIC_CH_PSR_AIF_Pos (15U)
\r
19032 #define USIC_CH_PSR_AIF_Msk (0x00000001U << USIC_CH_PSR_AIF_Pos)
\r
19034 #define USIC_CH_PSR_BRGIF_Pos (16U)
\r
19035 #define USIC_CH_PSR_BRGIF_Msk (0x00000001U << USIC_CH_PSR_BRGIF_Pos)
\r
19037 /* USIC_CH_PSR_ASCMode = Protocol Status Register [ASC Mode]*/
\r
19038 #define USIC_CH_PSR_ASCMode_TXIDLE_Pos (0U)
\r
19039 #define USIC_CH_PSR_ASCMode_TXIDLE_Msk (0x00000001U << USIC_CH_PSR_ASCMode_TXIDLE_Pos)
\r
19041 #define USIC_CH_PSR_ASCMode_RXIDLE_Pos (1U)
\r
19042 #define USIC_CH_PSR_ASCMode_RXIDLE_Msk (0x00000001U << USIC_CH_PSR_ASCMode_RXIDLE_Pos)
\r
19044 #define USIC_CH_PSR_ASCMode_SBD_Pos (2U)
\r
19045 #define USIC_CH_PSR_ASCMode_SBD_Msk (0x00000001U << USIC_CH_PSR_ASCMode_SBD_Pos)
\r
19047 #define USIC_CH_PSR_ASCMode_COL_Pos (3U)
\r
19048 #define USIC_CH_PSR_ASCMode_COL_Msk (0x00000001U << USIC_CH_PSR_ASCMode_COL_Pos)
\r
19050 #define USIC_CH_PSR_ASCMode_RNS_Pos (4U)
\r
19051 #define USIC_CH_PSR_ASCMode_RNS_Msk (0x00000001U << USIC_CH_PSR_ASCMode_RNS_Pos)
\r
19053 #define USIC_CH_PSR_ASCMode_FER0_Pos (5U)
\r
19054 #define USIC_CH_PSR_ASCMode_FER0_Msk (0x00000001U << USIC_CH_PSR_ASCMode_FER0_Pos)
\r
19056 #define USIC_CH_PSR_ASCMode_FER1_Pos (6U)
\r
19057 #define USIC_CH_PSR_ASCMode_FER1_Msk (0x00000001U << USIC_CH_PSR_ASCMode_FER1_Pos)
\r
19059 #define USIC_CH_PSR_ASCMode_RFF_Pos (7U)
\r
19060 #define USIC_CH_PSR_ASCMode_RFF_Msk (0x00000001U << USIC_CH_PSR_ASCMode_RFF_Pos)
\r
19062 #define USIC_CH_PSR_ASCMode_TFF_Pos (8U)
\r
19063 #define USIC_CH_PSR_ASCMode_TFF_Msk (0x00000001U << USIC_CH_PSR_ASCMode_TFF_Pos)
\r
19065 #define USIC_CH_PSR_ASCMode_BUSY_Pos (9U)
\r
19066 #define USIC_CH_PSR_ASCMode_BUSY_Msk (0x00000001U << USIC_CH_PSR_ASCMode_BUSY_Pos)
\r
19068 #define USIC_CH_PSR_ASCMode_RSIF_Pos (10U)
\r
19069 #define USIC_CH_PSR_ASCMode_RSIF_Msk (0x00000001U << USIC_CH_PSR_ASCMode_RSIF_Pos)
\r
19071 #define USIC_CH_PSR_ASCMode_DLIF_Pos (11U)
\r
19072 #define USIC_CH_PSR_ASCMode_DLIF_Msk (0x00000001U << USIC_CH_PSR_ASCMode_DLIF_Pos)
\r
19074 #define USIC_CH_PSR_ASCMode_TSIF_Pos (12U)
\r
19075 #define USIC_CH_PSR_ASCMode_TSIF_Msk (0x00000001U << USIC_CH_PSR_ASCMode_TSIF_Pos)
\r
19077 #define USIC_CH_PSR_ASCMode_TBIF_Pos (13U)
\r
19078 #define USIC_CH_PSR_ASCMode_TBIF_Msk (0x00000001U << USIC_CH_PSR_ASCMode_TBIF_Pos)
\r
19080 #define USIC_CH_PSR_ASCMode_RIF_Pos (14U)
\r
19081 #define USIC_CH_PSR_ASCMode_RIF_Msk (0x00000001U << USIC_CH_PSR_ASCMode_RIF_Pos)
\r
19083 #define USIC_CH_PSR_ASCMode_AIF_Pos (15U)
\r
19084 #define USIC_CH_PSR_ASCMode_AIF_Msk (0x00000001U << USIC_CH_PSR_ASCMode_AIF_Pos)
\r
19086 #define USIC_CH_PSR_ASCMode_BRGIF_Pos (16U)
\r
19087 #define USIC_CH_PSR_ASCMode_BRGIF_Msk (0x00000001U << USIC_CH_PSR_ASCMode_BRGIF_Pos)
\r
19089 /* USIC_CH_PSR_SSCMode = Protocol Status Register [SSC Mode]*/
\r
19090 #define USIC_CH_PSR_SSCMode_MSLS_Pos (0U)
\r
19091 #define USIC_CH_PSR_SSCMode_MSLS_Msk (0x00000001U << USIC_CH_PSR_SSCMode_MSLS_Pos)
\r
19093 #define USIC_CH_PSR_SSCMode_DX2S_Pos (1U)
\r
19094 #define USIC_CH_PSR_SSCMode_DX2S_Msk (0x00000001U << USIC_CH_PSR_SSCMode_DX2S_Pos)
\r
19096 #define USIC_CH_PSR_SSCMode_MSLSEV_Pos (2U)
\r
19097 #define USIC_CH_PSR_SSCMode_MSLSEV_Msk (0x00000001U << USIC_CH_PSR_SSCMode_MSLSEV_Pos)
\r
19099 #define USIC_CH_PSR_SSCMode_DX2TEV_Pos (3U)
\r
19100 #define USIC_CH_PSR_SSCMode_DX2TEV_Msk (0x00000001U << USIC_CH_PSR_SSCMode_DX2TEV_Pos)
\r
19102 #define USIC_CH_PSR_SSCMode_PARERR_Pos (4U)
\r
19103 #define USIC_CH_PSR_SSCMode_PARERR_Msk (0x00000001U << USIC_CH_PSR_SSCMode_PARERR_Pos)
\r
19105 #define USIC_CH_PSR_SSCMode_RSIF_Pos (10U)
\r
19106 #define USIC_CH_PSR_SSCMode_RSIF_Msk (0x00000001U << USIC_CH_PSR_SSCMode_RSIF_Pos)
\r
19108 #define USIC_CH_PSR_SSCMode_DLIF_Pos (11U)
\r
19109 #define USIC_CH_PSR_SSCMode_DLIF_Msk (0x00000001U << USIC_CH_PSR_SSCMode_DLIF_Pos)
\r
19111 #define USIC_CH_PSR_SSCMode_TSIF_Pos (12U)
\r
19112 #define USIC_CH_PSR_SSCMode_TSIF_Msk (0x00000001U << USIC_CH_PSR_SSCMode_TSIF_Pos)
\r
19114 #define USIC_CH_PSR_SSCMode_TBIF_Pos (13U)
\r
19115 #define USIC_CH_PSR_SSCMode_TBIF_Msk (0x00000001U << USIC_CH_PSR_SSCMode_TBIF_Pos)
\r
19117 #define USIC_CH_PSR_SSCMode_RIF_Pos (14U)
\r
19118 #define USIC_CH_PSR_SSCMode_RIF_Msk (0x00000001U << USIC_CH_PSR_SSCMode_RIF_Pos)
\r
19120 #define USIC_CH_PSR_SSCMode_AIF_Pos (15U)
\r
19121 #define USIC_CH_PSR_SSCMode_AIF_Msk (0x00000001U << USIC_CH_PSR_SSCMode_AIF_Pos)
\r
19123 #define USIC_CH_PSR_SSCMode_BRGIF_Pos (16U)
\r
19124 #define USIC_CH_PSR_SSCMode_BRGIF_Msk (0x00000001U << USIC_CH_PSR_SSCMode_BRGIF_Pos)
\r
19126 /* USIC_CH_PSR_IISMode = Protocol Status Register [IIS Mode]*/
\r
19127 #define USIC_CH_PSR_IISMode_WA_Pos (0U)
\r
19128 #define USIC_CH_PSR_IISMode_WA_Msk (0x00000001U << USIC_CH_PSR_IISMode_WA_Pos)
\r
19130 #define USIC_CH_PSR_IISMode_DX2S_Pos (1U)
\r
19131 #define USIC_CH_PSR_IISMode_DX2S_Msk (0x00000001U << USIC_CH_PSR_IISMode_DX2S_Pos)
\r
19133 #define USIC_CH_PSR_IISMode_DX2TEV_Pos (3U)
\r
19134 #define USIC_CH_PSR_IISMode_DX2TEV_Msk (0x00000001U << USIC_CH_PSR_IISMode_DX2TEV_Pos)
\r
19136 #define USIC_CH_PSR_IISMode_WAFE_Pos (4U)
\r
19137 #define USIC_CH_PSR_IISMode_WAFE_Msk (0x00000001U << USIC_CH_PSR_IISMode_WAFE_Pos)
\r
19139 #define USIC_CH_PSR_IISMode_WARE_Pos (5U)
\r
19140 #define USIC_CH_PSR_IISMode_WARE_Msk (0x00000001U << USIC_CH_PSR_IISMode_WARE_Pos)
\r
19142 #define USIC_CH_PSR_IISMode_END_Pos (6U)
\r
19143 #define USIC_CH_PSR_IISMode_END_Msk (0x00000001U << USIC_CH_PSR_IISMode_END_Pos)
\r
19145 #define USIC_CH_PSR_IISMode_RSIF_Pos (10U)
\r
19146 #define USIC_CH_PSR_IISMode_RSIF_Msk (0x00000001U << USIC_CH_PSR_IISMode_RSIF_Pos)
\r
19148 #define USIC_CH_PSR_IISMode_DLIF_Pos (11U)
\r
19149 #define USIC_CH_PSR_IISMode_DLIF_Msk (0x00000001U << USIC_CH_PSR_IISMode_DLIF_Pos)
\r
19151 #define USIC_CH_PSR_IISMode_TSIF_Pos (12U)
\r
19152 #define USIC_CH_PSR_IISMode_TSIF_Msk (0x00000001U << USIC_CH_PSR_IISMode_TSIF_Pos)
\r
19154 #define USIC_CH_PSR_IISMode_TBIF_Pos (13U)
\r
19155 #define USIC_CH_PSR_IISMode_TBIF_Msk (0x00000001U << USIC_CH_PSR_IISMode_TBIF_Pos)
\r
19157 #define USIC_CH_PSR_IISMode_RIF_Pos (14U)
\r
19158 #define USIC_CH_PSR_IISMode_RIF_Msk (0x00000001U << USIC_CH_PSR_IISMode_RIF_Pos)
\r
19160 #define USIC_CH_PSR_IISMode_AIF_Pos (15U)
\r
19161 #define USIC_CH_PSR_IISMode_AIF_Msk (0x00000001U << USIC_CH_PSR_IISMode_AIF_Pos)
\r
19163 #define USIC_CH_PSR_IISMode_BRGIF_Pos (16U)
\r
19164 #define USIC_CH_PSR_IISMode_BRGIF_Msk (0x00000001U << USIC_CH_PSR_IISMode_BRGIF_Pos)
\r
19166 /* USIC_CH_PSR_IICMode = Protocol Status Register [IIC Mode]*/
\r
19167 #define USIC_CH_PSR_IICMode_SLSEL_Pos (0U)
\r
19168 #define USIC_CH_PSR_IICMode_SLSEL_Msk (0x00000001U << USIC_CH_PSR_IICMode_SLSEL_Pos)
\r
19170 #define USIC_CH_PSR_IICMode_WTDF_Pos (1U)
\r
19171 #define USIC_CH_PSR_IICMode_WTDF_Msk (0x00000001U << USIC_CH_PSR_IICMode_WTDF_Pos)
\r
19173 #define USIC_CH_PSR_IICMode_SCR_Pos (2U)
\r
19174 #define USIC_CH_PSR_IICMode_SCR_Msk (0x00000001U << USIC_CH_PSR_IICMode_SCR_Pos)
\r
19176 #define USIC_CH_PSR_IICMode_RSCR_Pos (3U)
\r
19177 #define USIC_CH_PSR_IICMode_RSCR_Msk (0x00000001U << USIC_CH_PSR_IICMode_RSCR_Pos)
\r
19179 #define USIC_CH_PSR_IICMode_PCR_Pos (4U)
\r
19180 #define USIC_CH_PSR_IICMode_PCR_Msk (0x00000001U << USIC_CH_PSR_IICMode_PCR_Pos)
\r
19182 #define USIC_CH_PSR_IICMode_NACK_Pos (5U)
\r
19183 #define USIC_CH_PSR_IICMode_NACK_Msk (0x00000001U << USIC_CH_PSR_IICMode_NACK_Pos)
\r
19185 #define USIC_CH_PSR_IICMode_ARL_Pos (6U)
\r
19186 #define USIC_CH_PSR_IICMode_ARL_Msk (0x00000001U << USIC_CH_PSR_IICMode_ARL_Pos)
\r
19188 #define USIC_CH_PSR_IICMode_SRR_Pos (7U)
\r
19189 #define USIC_CH_PSR_IICMode_SRR_Msk (0x00000001U << USIC_CH_PSR_IICMode_SRR_Pos)
\r
19191 #define USIC_CH_PSR_IICMode_ERR_Pos (8U)
\r
19192 #define USIC_CH_PSR_IICMode_ERR_Msk (0x00000001U << USIC_CH_PSR_IICMode_ERR_Pos)
\r
19194 #define USIC_CH_PSR_IICMode_ACK_Pos (9U)
\r
19195 #define USIC_CH_PSR_IICMode_ACK_Msk (0x00000001U << USIC_CH_PSR_IICMode_ACK_Pos)
\r
19197 #define USIC_CH_PSR_IICMode_RSIF_Pos (10U)
\r
19198 #define USIC_CH_PSR_IICMode_RSIF_Msk (0x00000001U << USIC_CH_PSR_IICMode_RSIF_Pos)
\r
19200 #define USIC_CH_PSR_IICMode_DLIF_Pos (11U)
\r
19201 #define USIC_CH_PSR_IICMode_DLIF_Msk (0x00000001U << USIC_CH_PSR_IICMode_DLIF_Pos)
\r
19203 #define USIC_CH_PSR_IICMode_TSIF_Pos (12U)
\r
19204 #define USIC_CH_PSR_IICMode_TSIF_Msk (0x00000001U << USIC_CH_PSR_IICMode_TSIF_Pos)
\r
19206 #define USIC_CH_PSR_IICMode_TBIF_Pos (13U)
\r
19207 #define USIC_CH_PSR_IICMode_TBIF_Msk (0x00000001U << USIC_CH_PSR_IICMode_TBIF_Pos)
\r
19209 #define USIC_CH_PSR_IICMode_RIF_Pos (14U)
\r
19210 #define USIC_CH_PSR_IICMode_RIF_Msk (0x00000001U << USIC_CH_PSR_IICMode_RIF_Pos)
\r
19212 #define USIC_CH_PSR_IICMode_AIF_Pos (15U)
\r
19213 #define USIC_CH_PSR_IICMode_AIF_Msk (0x00000001U << USIC_CH_PSR_IICMode_AIF_Pos)
\r
19215 #define USIC_CH_PSR_IICMode_BRGIF_Pos (16U)
\r
19216 #define USIC_CH_PSR_IICMode_BRGIF_Msk (0x00000001U << USIC_CH_PSR_IICMode_BRGIF_Pos)
\r
19218 /* USIC_CH_PSCR = Protocol Status Clear Register*/
\r
19219 #define USIC_CH_PSCR_CST0_Pos (0U)
\r
19220 #define USIC_CH_PSCR_CST0_Msk (0x00000001U << USIC_CH_PSCR_CST0_Pos)
\r
19222 #define USIC_CH_PSCR_CST1_Pos (1U)
\r
19223 #define USIC_CH_PSCR_CST1_Msk (0x00000001U << USIC_CH_PSCR_CST1_Pos)
\r
19225 #define USIC_CH_PSCR_CST2_Pos (2U)
\r
19226 #define USIC_CH_PSCR_CST2_Msk (0x00000001U << USIC_CH_PSCR_CST2_Pos)
\r
19228 #define USIC_CH_PSCR_CST3_Pos (3U)
\r
19229 #define USIC_CH_PSCR_CST3_Msk (0x00000001U << USIC_CH_PSCR_CST3_Pos)
\r
19231 #define USIC_CH_PSCR_CST4_Pos (4U)
\r
19232 #define USIC_CH_PSCR_CST4_Msk (0x00000001U << USIC_CH_PSCR_CST4_Pos)
\r
19234 #define USIC_CH_PSCR_CST5_Pos (5U)
\r
19235 #define USIC_CH_PSCR_CST5_Msk (0x00000001U << USIC_CH_PSCR_CST5_Pos)
\r
19237 #define USIC_CH_PSCR_CST6_Pos (6U)
\r
19238 #define USIC_CH_PSCR_CST6_Msk (0x00000001U << USIC_CH_PSCR_CST6_Pos)
\r
19240 #define USIC_CH_PSCR_CST7_Pos (7U)
\r
19241 #define USIC_CH_PSCR_CST7_Msk (0x00000001U << USIC_CH_PSCR_CST7_Pos)
\r
19243 #define USIC_CH_PSCR_CST8_Pos (8U)
\r
19244 #define USIC_CH_PSCR_CST8_Msk (0x00000001U << USIC_CH_PSCR_CST8_Pos)
\r
19246 #define USIC_CH_PSCR_CST9_Pos (9U)
\r
19247 #define USIC_CH_PSCR_CST9_Msk (0x00000001U << USIC_CH_PSCR_CST9_Pos)
\r
19249 #define USIC_CH_PSCR_CRSIF_Pos (10U)
\r
19250 #define USIC_CH_PSCR_CRSIF_Msk (0x00000001U << USIC_CH_PSCR_CRSIF_Pos)
\r
19252 #define USIC_CH_PSCR_CDLIF_Pos (11U)
\r
19253 #define USIC_CH_PSCR_CDLIF_Msk (0x00000001U << USIC_CH_PSCR_CDLIF_Pos)
\r
19255 #define USIC_CH_PSCR_CTSIF_Pos (12U)
\r
19256 #define USIC_CH_PSCR_CTSIF_Msk (0x00000001U << USIC_CH_PSCR_CTSIF_Pos)
\r
19258 #define USIC_CH_PSCR_CTBIF_Pos (13U)
\r
19259 #define USIC_CH_PSCR_CTBIF_Msk (0x00000001U << USIC_CH_PSCR_CTBIF_Pos)
\r
19261 #define USIC_CH_PSCR_CRIF_Pos (14U)
\r
19262 #define USIC_CH_PSCR_CRIF_Msk (0x00000001U << USIC_CH_PSCR_CRIF_Pos)
\r
19264 #define USIC_CH_PSCR_CAIF_Pos (15U)
\r
19265 #define USIC_CH_PSCR_CAIF_Msk (0x00000001U << USIC_CH_PSCR_CAIF_Pos)
\r
19267 #define USIC_CH_PSCR_CBRGIF_Pos (16U)
\r
19268 #define USIC_CH_PSCR_CBRGIF_Msk (0x00000001U << USIC_CH_PSCR_CBRGIF_Pos)
\r
19270 /* USIC_CH_RBUFSR = Receiver Buffer Status Register*/
\r
19271 #define USIC_CH_RBUFSR_WLEN_Pos (0U)
\r
19272 #define USIC_CH_RBUFSR_WLEN_Msk (0x0000000FU << USIC_CH_RBUFSR_WLEN_Pos)
\r
19274 #define USIC_CH_RBUFSR_SOF_Pos (6U)
\r
19275 #define USIC_CH_RBUFSR_SOF_Msk (0x00000001U << USIC_CH_RBUFSR_SOF_Pos)
\r
19277 #define USIC_CH_RBUFSR_PAR_Pos (8U)
\r
19278 #define USIC_CH_RBUFSR_PAR_Msk (0x00000001U << USIC_CH_RBUFSR_PAR_Pos)
\r
19280 #define USIC_CH_RBUFSR_PERR_Pos (9U)
\r
19281 #define USIC_CH_RBUFSR_PERR_Msk (0x00000001U << USIC_CH_RBUFSR_PERR_Pos)
\r
19283 #define USIC_CH_RBUFSR_RDV0_Pos (13U)
\r
19284 #define USIC_CH_RBUFSR_RDV0_Msk (0x00000001U << USIC_CH_RBUFSR_RDV0_Pos)
\r
19286 #define USIC_CH_RBUFSR_RDV1_Pos (14U)
\r
19287 #define USIC_CH_RBUFSR_RDV1_Msk (0x00000001U << USIC_CH_RBUFSR_RDV1_Pos)
\r
19289 #define USIC_CH_RBUFSR_DS_Pos (15U)
\r
19290 #define USIC_CH_RBUFSR_DS_Msk (0x00000001U << USIC_CH_RBUFSR_DS_Pos)
\r
19292 /* USIC_CH_RBUF = Receiver Buffer Register*/
\r
19293 #define USIC_CH_RBUF_DSR_Pos (0U)
\r
19294 #define USIC_CH_RBUF_DSR_Msk (0x0000FFFFU << USIC_CH_RBUF_DSR_Pos)
\r
19296 /* USIC_CH_RBUFD = Receiver Buffer Register for Debugger*/
\r
19297 #define USIC_CH_RBUFD_DSR_Pos (0U)
\r
19298 #define USIC_CH_RBUFD_DSR_Msk (0x0000FFFFU << USIC_CH_RBUFD_DSR_Pos)
\r
19300 /* USIC_CH_RBUF0 = Receiver Buffer Register 0*/
\r
19301 #define USIC_CH_RBUF0_DSR0_Pos (0U)
\r
19302 #define USIC_CH_RBUF0_DSR0_Msk (0x0000FFFFU << USIC_CH_RBUF0_DSR0_Pos)
\r
19304 /* USIC_CH_RBUF1 = Receiver Buffer Register 1*/
\r
19305 #define USIC_CH_RBUF1_DSR1_Pos (0U)
\r
19306 #define USIC_CH_RBUF1_DSR1_Msk (0x0000FFFFU << USIC_CH_RBUF1_DSR1_Pos)
\r
19308 /* USIC_CH_RBUF01SR = Receiver Buffer 01 Status Register*/
\r
19309 #define USIC_CH_RBUF01SR_WLEN0_Pos (0U)
\r
19310 #define USIC_CH_RBUF01SR_WLEN0_Msk (0x0000000FU << USIC_CH_RBUF01SR_WLEN0_Pos)
\r
19312 #define USIC_CH_RBUF01SR_SOF0_Pos (6U)
\r
19313 #define USIC_CH_RBUF01SR_SOF0_Msk (0x00000001U << USIC_CH_RBUF01SR_SOF0_Pos)
\r
19315 #define USIC_CH_RBUF01SR_PAR0_Pos (8U)
\r
19316 #define USIC_CH_RBUF01SR_PAR0_Msk (0x00000001U << USIC_CH_RBUF01SR_PAR0_Pos)
\r
19318 #define USIC_CH_RBUF01SR_PERR0_Pos (9U)
\r
19319 #define USIC_CH_RBUF01SR_PERR0_Msk (0x00000001U << USIC_CH_RBUF01SR_PERR0_Pos)
\r
19321 #define USIC_CH_RBUF01SR_RDV00_Pos (13U)
\r
19322 #define USIC_CH_RBUF01SR_RDV00_Msk (0x00000001U << USIC_CH_RBUF01SR_RDV00_Pos)
\r
19324 #define USIC_CH_RBUF01SR_RDV01_Pos (14U)
\r
19325 #define USIC_CH_RBUF01SR_RDV01_Msk (0x00000001U << USIC_CH_RBUF01SR_RDV01_Pos)
\r
19327 #define USIC_CH_RBUF01SR_DS0_Pos (15U)
\r
19328 #define USIC_CH_RBUF01SR_DS0_Msk (0x00000001U << USIC_CH_RBUF01SR_DS0_Pos)
\r
19330 #define USIC_CH_RBUF01SR_WLEN1_Pos (16U)
\r
19331 #define USIC_CH_RBUF01SR_WLEN1_Msk (0x0000000FU << USIC_CH_RBUF01SR_WLEN1_Pos)
\r
19333 #define USIC_CH_RBUF01SR_SOF1_Pos (22U)
\r
19334 #define USIC_CH_RBUF01SR_SOF1_Msk (0x00000001U << USIC_CH_RBUF01SR_SOF1_Pos)
\r
19336 #define USIC_CH_RBUF01SR_PAR1_Pos (24U)
\r
19337 #define USIC_CH_RBUF01SR_PAR1_Msk (0x00000001U << USIC_CH_RBUF01SR_PAR1_Pos)
\r
19339 #define USIC_CH_RBUF01SR_PERR1_Pos (25U)
\r
19340 #define USIC_CH_RBUF01SR_PERR1_Msk (0x00000001U << USIC_CH_RBUF01SR_PERR1_Pos)
\r
19342 #define USIC_CH_RBUF01SR_RDV10_Pos (29U)
\r
19343 #define USIC_CH_RBUF01SR_RDV10_Msk (0x00000001U << USIC_CH_RBUF01SR_RDV10_Pos)
\r
19345 #define USIC_CH_RBUF01SR_RDV11_Pos (30U)
\r
19346 #define USIC_CH_RBUF01SR_RDV11_Msk (0x00000001U << USIC_CH_RBUF01SR_RDV11_Pos)
\r
19348 #define USIC_CH_RBUF01SR_DS1_Pos (31U)
\r
19349 #define USIC_CH_RBUF01SR_DS1_Msk (0x00000001U << USIC_CH_RBUF01SR_DS1_Pos)
\r
19351 /* USIC_CH_FMR = Flag Modification Register*/
\r
19352 #define USIC_CH_FMR_MTDV_Pos (0U)
\r
19353 #define USIC_CH_FMR_MTDV_Msk (0x00000003U << USIC_CH_FMR_MTDV_Pos)
\r
19355 #define USIC_CH_FMR_ATVC_Pos (4U)
\r
19356 #define USIC_CH_FMR_ATVC_Msk (0x00000001U << USIC_CH_FMR_ATVC_Pos)
\r
19358 #define USIC_CH_FMR_CRDV0_Pos (14U)
\r
19359 #define USIC_CH_FMR_CRDV0_Msk (0x00000001U << USIC_CH_FMR_CRDV0_Pos)
\r
19361 #define USIC_CH_FMR_CRDV1_Pos (15U)
\r
19362 #define USIC_CH_FMR_CRDV1_Msk (0x00000001U << USIC_CH_FMR_CRDV1_Pos)
\r
19364 #define USIC_CH_FMR_SIO0_Pos (16U)
\r
19365 #define USIC_CH_FMR_SIO0_Msk (0x00000001U << USIC_CH_FMR_SIO0_Pos)
\r
19367 #define USIC_CH_FMR_SIO1_Pos (17U)
\r
19368 #define USIC_CH_FMR_SIO1_Msk (0x00000001U << USIC_CH_FMR_SIO1_Pos)
\r
19370 #define USIC_CH_FMR_SIO2_Pos (18U)
\r
19371 #define USIC_CH_FMR_SIO2_Msk (0x00000001U << USIC_CH_FMR_SIO2_Pos)
\r
19373 #define USIC_CH_FMR_SIO3_Pos (19U)
\r
19374 #define USIC_CH_FMR_SIO3_Msk (0x00000001U << USIC_CH_FMR_SIO3_Pos)
\r
19376 #define USIC_CH_FMR_SIO4_Pos (20U)
\r
19377 #define USIC_CH_FMR_SIO4_Msk (0x00000001U << USIC_CH_FMR_SIO4_Pos)
\r
19379 #define USIC_CH_FMR_SIO5_Pos (21U)
\r
19380 #define USIC_CH_FMR_SIO5_Msk (0x00000001U << USIC_CH_FMR_SIO5_Pos)
\r
19382 /* USIC_CH_TBUFxx = Transmit Buffer Input Location 00*/
\r
19383 #define USIC_CH_TBUF_TDATA_Pos (0U)
\r
19384 #define USIC_CH_TBUF_TDATA_Msk (0x0000FFFFU << USIC_CH_TBUF_TDATA_Pos)
\r
19386 /* USIC_CH_BYP = Bypass Data Register*/
\r
19387 #define USIC_CH_BYP_BDATA_Pos (0U)
\r
19388 #define USIC_CH_BYP_BDATA_Msk (0x0000FFFFU << USIC_CH_BYP_BDATA_Pos)
\r
19390 /* USIC_CH_BYPCR = Bypass Control Register*/
\r
19391 #define USIC_CH_BYPCR_BWLE_Pos (0U)
\r
19392 #define USIC_CH_BYPCR_BWLE_Msk (0x0000000FU << USIC_CH_BYPCR_BWLE_Pos)
\r
19394 #define USIC_CH_BYPCR_BDSSM_Pos (8U)
\r
19395 #define USIC_CH_BYPCR_BDSSM_Msk (0x00000001U << USIC_CH_BYPCR_BDSSM_Pos)
\r
19397 #define USIC_CH_BYPCR_BDEN_Pos (10U)
\r
19398 #define USIC_CH_BYPCR_BDEN_Msk (0x00000003U << USIC_CH_BYPCR_BDEN_Pos)
\r
19400 #define USIC_CH_BYPCR_BDVTR_Pos (12U)
\r
19401 #define USIC_CH_BYPCR_BDVTR_Msk (0x00000001U << USIC_CH_BYPCR_BDVTR_Pos)
\r
19403 #define USIC_CH_BYPCR_BPRIO_Pos (13U)
\r
19404 #define USIC_CH_BYPCR_BPRIO_Msk (0x00000001U << USIC_CH_BYPCR_BPRIO_Pos)
\r
19406 #define USIC_CH_BYPCR_BDV_Pos (15U)
\r
19407 #define USIC_CH_BYPCR_BDV_Msk (0x00000001U << USIC_CH_BYPCR_BDV_Pos)
\r
19409 #define USIC_CH_BYPCR_BSELO_Pos (16U)
\r
19410 #define USIC_CH_BYPCR_BSELO_Msk (0x0000001FU << USIC_CH_BYPCR_BSELO_Pos)
\r
19412 #define USIC_CH_BYPCR_BHPC_Pos (21U)
\r
19413 #define USIC_CH_BYPCR_BHPC_Msk (0x00000007U << USIC_CH_BYPCR_BHPC_Pos)
\r
19415 /* USIC_CH_TBCTR = Transmitter Buffer Control Register*/
\r
19416 #define USIC_CH_TBCTR_DPTR_Pos (0U)
\r
19417 #define USIC_CH_TBCTR_DPTR_Msk (0x0000003FU << USIC_CH_TBCTR_DPTR_Pos)
\r
19419 #define USIC_CH_TBCTR_LIMIT_Pos (8U)
\r
19420 #define USIC_CH_TBCTR_LIMIT_Msk (0x0000003FU << USIC_CH_TBCTR_LIMIT_Pos)
\r
19422 #define USIC_CH_TBCTR_STBTM_Pos (14U)
\r
19423 #define USIC_CH_TBCTR_STBTM_Msk (0x00000001U << USIC_CH_TBCTR_STBTM_Pos)
\r
19425 #define USIC_CH_TBCTR_STBTEN_Pos (15U)
\r
19426 #define USIC_CH_TBCTR_STBTEN_Msk (0x00000001U << USIC_CH_TBCTR_STBTEN_Pos)
\r
19428 #define USIC_CH_TBCTR_STBINP_Pos (16U)
\r
19429 #define USIC_CH_TBCTR_STBINP_Msk (0x00000007U << USIC_CH_TBCTR_STBINP_Pos)
\r
19431 #define USIC_CH_TBCTR_ATBINP_Pos (19U)
\r
19432 #define USIC_CH_TBCTR_ATBINP_Msk (0x00000007U << USIC_CH_TBCTR_ATBINP_Pos)
\r
19434 #define USIC_CH_TBCTR_SIZE_Pos (24U)
\r
19435 #define USIC_CH_TBCTR_SIZE_Msk (0x00000007U << USIC_CH_TBCTR_SIZE_Pos)
\r
19437 #define USIC_CH_TBCTR_LOF_Pos (28U)
\r
19438 #define USIC_CH_TBCTR_LOF_Msk (0x00000001U << USIC_CH_TBCTR_LOF_Pos)
\r
19440 #define USIC_CH_TBCTR_STBIEN_Pos (30U)
\r
19441 #define USIC_CH_TBCTR_STBIEN_Msk (0x00000001U << USIC_CH_TBCTR_STBIEN_Pos)
\r
19443 #define USIC_CH_TBCTR_TBERIEN_Pos (31U)
\r
19444 #define USIC_CH_TBCTR_TBERIEN_Msk (0x00000001U << USIC_CH_TBCTR_TBERIEN_Pos)
\r
19446 /* USIC_CH_RBCTR = Receiver Buffer Control Register*/
\r
19447 #define USIC_CH_RBCTR_DPTR_Pos (0U)
\r
19448 #define USIC_CH_RBCTR_DPTR_Msk (0x0000003FU << USIC_CH_RBCTR_DPTR_Pos)
\r
19450 #define USIC_CH_RBCTR_LIMIT_Pos (8U)
\r
19451 #define USIC_CH_RBCTR_LIMIT_Msk (0x0000003FU << USIC_CH_RBCTR_LIMIT_Pos)
\r
19453 #define USIC_CH_RBCTR_SRBTM_Pos (14U)
\r
19454 #define USIC_CH_RBCTR_SRBTM_Msk (0x00000001U << USIC_CH_RBCTR_SRBTM_Pos)
\r
19456 #define USIC_CH_RBCTR_SRBTEN_Pos (15U)
\r
19457 #define USIC_CH_RBCTR_SRBTEN_Msk (0x00000001U << USIC_CH_RBCTR_SRBTEN_Pos)
\r
19459 #define USIC_CH_RBCTR_SRBINP_Pos (16U)
\r
19460 #define USIC_CH_RBCTR_SRBINP_Msk (0x00000007U << USIC_CH_RBCTR_SRBINP_Pos)
\r
19462 #define USIC_CH_RBCTR_ARBINP_Pos (19U)
\r
19463 #define USIC_CH_RBCTR_ARBINP_Msk (0x00000007U << USIC_CH_RBCTR_ARBINP_Pos)
\r
19465 #define USIC_CH_RBCTR_RCIM_Pos (22U)
\r
19466 #define USIC_CH_RBCTR_RCIM_Msk (0x00000003U << USIC_CH_RBCTR_RCIM_Pos)
\r
19468 #define USIC_CH_RBCTR_SIZE_Pos (24U)
\r
19469 #define USIC_CH_RBCTR_SIZE_Msk (0x00000007U << USIC_CH_RBCTR_SIZE_Pos)
\r
19471 #define USIC_CH_RBCTR_RNM_Pos (27U)
\r
19472 #define USIC_CH_RBCTR_RNM_Msk (0x00000001U << USIC_CH_RBCTR_RNM_Pos)
\r
19474 #define USIC_CH_RBCTR_LOF_Pos (28U)
\r
19475 #define USIC_CH_RBCTR_LOF_Msk (0x00000001U << USIC_CH_RBCTR_LOF_Pos)
\r
19477 #define USIC_CH_RBCTR_ARBIEN_Pos (29U)
\r
19478 #define USIC_CH_RBCTR_ARBIEN_Msk (0x00000001U << USIC_CH_RBCTR_ARBIEN_Pos)
\r
19480 #define USIC_CH_RBCTR_SRBIEN_Pos (30U)
\r
19481 #define USIC_CH_RBCTR_SRBIEN_Msk (0x00000001U << USIC_CH_RBCTR_SRBIEN_Pos)
\r
19483 #define USIC_CH_RBCTR_RBERIEN_Pos (31U)
\r
19484 #define USIC_CH_RBCTR_RBERIEN_Msk (0x00000001U << USIC_CH_RBCTR_RBERIEN_Pos)
\r
19486 /* USIC_CH_TRBPTR = Transmit/Receive Buffer Pointer Register*/
\r
19487 #define USIC_CH_TRBPTR_TDIPTR_Pos (0U)
\r
19488 #define USIC_CH_TRBPTR_TDIPTR_Msk (0x0000003FU << USIC_CH_TRBPTR_TDIPTR_Pos)
\r
19490 #define USIC_CH_TRBPTR_TDOPTR_Pos (8U)
\r
19491 #define USIC_CH_TRBPTR_TDOPTR_Msk (0x0000003FU << USIC_CH_TRBPTR_TDOPTR_Pos)
\r
19493 #define USIC_CH_TRBPTR_RDIPTR_Pos (16U)
\r
19494 #define USIC_CH_TRBPTR_RDIPTR_Msk (0x0000003FU << USIC_CH_TRBPTR_RDIPTR_Pos)
\r
19496 #define USIC_CH_TRBPTR_RDOPTR_Pos (24U)
\r
19497 #define USIC_CH_TRBPTR_RDOPTR_Msk (0x0000003FU << USIC_CH_TRBPTR_RDOPTR_Pos)
\r
19499 /* USIC_CH_TRBSR = Transmit/Receive Buffer Status Register*/
\r
19500 #define USIC_CH_TRBSR_SRBI_Pos (0U)
\r
19501 #define USIC_CH_TRBSR_SRBI_Msk (0x00000001U << USIC_CH_TRBSR_SRBI_Pos)
\r
19503 #define USIC_CH_TRBSR_RBERI_Pos (1U)
\r
19504 #define USIC_CH_TRBSR_RBERI_Msk (0x00000001U << USIC_CH_TRBSR_RBERI_Pos)
\r
19506 #define USIC_CH_TRBSR_ARBI_Pos (2U)
\r
19507 #define USIC_CH_TRBSR_ARBI_Msk (0x00000001U << USIC_CH_TRBSR_ARBI_Pos)
\r
19509 #define USIC_CH_TRBSR_REMPTY_Pos (3U)
\r
19510 #define USIC_CH_TRBSR_REMPTY_Msk (0x00000001U << USIC_CH_TRBSR_REMPTY_Pos)
\r
19512 #define USIC_CH_TRBSR_RFULL_Pos (4U)
\r
19513 #define USIC_CH_TRBSR_RFULL_Msk (0x00000001U << USIC_CH_TRBSR_RFULL_Pos)
\r
19515 #define USIC_CH_TRBSR_RBUS_Pos (5U)
\r
19516 #define USIC_CH_TRBSR_RBUS_Msk (0x00000001U << USIC_CH_TRBSR_RBUS_Pos)
\r
19518 #define USIC_CH_TRBSR_SRBT_Pos (6U)
\r
19519 #define USIC_CH_TRBSR_SRBT_Msk (0x00000001U << USIC_CH_TRBSR_SRBT_Pos)
\r
19521 #define USIC_CH_TRBSR_STBI_Pos (8U)
\r
19522 #define USIC_CH_TRBSR_STBI_Msk (0x00000001U << USIC_CH_TRBSR_STBI_Pos)
\r
19524 #define USIC_CH_TRBSR_TBERI_Pos (9U)
\r
19525 #define USIC_CH_TRBSR_TBERI_Msk (0x00000001U << USIC_CH_TRBSR_TBERI_Pos)
\r
19527 #define USIC_CH_TRBSR_TEMPTY_Pos (11U)
\r
19528 #define USIC_CH_TRBSR_TEMPTY_Msk (0x00000001U << USIC_CH_TRBSR_TEMPTY_Pos)
\r
19530 #define USIC_CH_TRBSR_TFULL_Pos (12U)
\r
19531 #define USIC_CH_TRBSR_TFULL_Msk (0x00000001U << USIC_CH_TRBSR_TFULL_Pos)
\r
19533 #define USIC_CH_TRBSR_TBUS_Pos (13U)
\r
19534 #define USIC_CH_TRBSR_TBUS_Msk (0x00000001U << USIC_CH_TRBSR_TBUS_Pos)
\r
19536 #define USIC_CH_TRBSR_STBT_Pos (14U)
\r
19537 #define USIC_CH_TRBSR_STBT_Msk (0x00000001U << USIC_CH_TRBSR_STBT_Pos)
\r
19539 #define USIC_CH_TRBSR_RBFLVL_Pos (16U)
\r
19540 #define USIC_CH_TRBSR_RBFLVL_Msk (0x0000007FU << USIC_CH_TRBSR_RBFLVL_Pos)
\r
19542 #define USIC_CH_TRBSR_TBFLVL_Pos (24U)
\r
19543 #define USIC_CH_TRBSR_TBFLVL_Msk (0x0000007FU << USIC_CH_TRBSR_TBFLVL_Pos)
\r
19545 /* USIC_CH_TRBSCR = Transmit/Receive Buffer Status Clear Register*/
\r
19546 #define USIC_CH_TRBSCR_CSRBI_Pos (0U)
\r
19547 #define USIC_CH_TRBSCR_CSRBI_Msk (0x00000001U << USIC_CH_TRBSCR_CSRBI_Pos)
\r
19549 #define USIC_CH_TRBSCR_CRBERI_Pos (1U)
\r
19550 #define USIC_CH_TRBSCR_CRBERI_Msk (0x00000001U << USIC_CH_TRBSCR_CRBERI_Pos)
\r
19552 #define USIC_CH_TRBSCR_CARBI_Pos (2U)
\r
19553 #define USIC_CH_TRBSCR_CARBI_Msk (0x00000001U << USIC_CH_TRBSCR_CARBI_Pos)
\r
19555 #define USIC_CH_TRBSCR_CSTBI_Pos (8U)
\r
19556 #define USIC_CH_TRBSCR_CSTBI_Msk (0x00000001U << USIC_CH_TRBSCR_CSTBI_Pos)
\r
19558 #define USIC_CH_TRBSCR_CTBERI_Pos (9U)
\r
19559 #define USIC_CH_TRBSCR_CTBERI_Msk (0x00000001U << USIC_CH_TRBSCR_CTBERI_Pos)
\r
19561 #define USIC_CH_TRBSCR_CBDV_Pos (10U)
\r
19562 #define USIC_CH_TRBSCR_CBDV_Msk (0x00000001U << USIC_CH_TRBSCR_CBDV_Pos)
\r
19564 #define USIC_CH_TRBSCR_FLUSHRB_Pos (14U)
\r
19565 #define USIC_CH_TRBSCR_FLUSHRB_Msk (0x00000001U << USIC_CH_TRBSCR_FLUSHRB_Pos)
\r
19567 #define USIC_CH_TRBSCR_FLUSHTB_Pos (15U)
\r
19568 #define USIC_CH_TRBSCR_FLUSHTB_Msk (0x00000001U << USIC_CH_TRBSCR_FLUSHTB_Pos)
\r
19570 /* USIC_CH_OUTR = Receiver Buffer Output Register*/
\r
19571 #define USIC_CH_OUTR_DSR_Pos (0U)
\r
19572 #define USIC_CH_OUTR_DSR_Msk (0x0000FFFFU << USIC_CH_OUTR_DSR_Pos)
\r
19574 #define USIC_CH_OUTR_RCI_Pos (16U)
\r
19575 #define USIC_CH_OUTR_RCI_Msk (0x0000001FU << USIC_CH_OUTR_RCI_Pos)
\r
19577 /* USIC_CH_OUTDR = Receiver Buffer Output Register L for Debugger*/
\r
19578 #define USIC_CH_OUTDR_DSR_Pos (0U)
\r
19579 #define USIC_CH_OUTDR_DSR_Msk (0x0000FFFFU << USIC_CH_OUTDR_DSR_Pos)
\r
19581 #define USIC_CH_OUTDR_RCI_Pos (16U)
\r
19582 #define USIC_CH_OUTDR_RCI_Msk (0x0000001FU << USIC_CH_OUTDR_RCI_Pos)
\r
19584 /* USIC_CH_INxx = Transmit FIFO Buffer Input Location 00*/
\r
19585 #define USIC_CH_IN_TDATA_Pos (0U)
\r
19586 #define USIC_CH_IN_TDATA_Msk (0x0000FFFFU << USIC_CH_IN_TDATA_Pos)
\r
19590 /*** VADC Bit Fileds *******************/
\r
19591 /***************************************************************************/
\r
19594 /* VADC_G_ARBCFG = Arbitration Configuration Register, Group 0*/
\r
19595 #define VADC_G_ARBCFG_ANONC_Pos (0U)
\r
19596 #define VADC_G_ARBCFG_ANONC_Msk (0x00000003U << VADC_G_ARBCFG_ANONC_Pos)
\r
19598 #define VADC_G_ARBCFG_ARBRND_Pos (4U)
\r
19599 #define VADC_G_ARBCFG_ARBRND_Msk (0x00000003U << VADC_G_ARBCFG_ARBRND_Pos)
\r
19601 #define VADC_G_ARBCFG_ARBM_Pos (7U)
\r
19602 #define VADC_G_ARBCFG_ARBM_Msk (0x00000001U << VADC_G_ARBCFG_ARBM_Pos)
\r
19604 #define VADC_G_ARBCFG_ANONS_Pos (16U)
\r
19605 #define VADC_G_ARBCFG_ANONS_Msk (0x00000003U << VADC_G_ARBCFG_ANONS_Pos)
\r
19607 #define VADC_G_ARBCFG_CAL_Pos (28U)
\r
19608 #define VADC_G_ARBCFG_CAL_Msk (0x00000001U << VADC_G_ARBCFG_CAL_Pos)
\r
19610 #define VADC_G_ARBCFG_BUSY_Pos (30U)
\r
19611 #define VADC_G_ARBCFG_BUSY_Msk (0x00000001U << VADC_G_ARBCFG_BUSY_Pos)
\r
19613 #define VADC_G_ARBCFG_SAMPLE_Pos (31U)
\r
19614 #define VADC_G_ARBCFG_SAMPLE_Msk (0x00000001U << VADC_G_ARBCFG_SAMPLE_Pos)
\r
19616 /* VADC_G_ARBPR = Arbitration Priority Register, Group 0*/
\r
19617 #define VADC_G_ARBPR_PRIO0_Pos (0U)
\r
19618 #define VADC_G_ARBPR_PRIO0_Msk (0x00000003U << VADC_G_ARBPR_PRIO0_Pos)
\r
19620 #define VADC_G_ARBPR_PRIO1_Pos (4U)
\r
19621 #define VADC_G_ARBPR_PRIO1_Msk (0x00000003U << VADC_G_ARBPR_PRIO1_Pos)
\r
19623 #define VADC_G_ARBPR_PRIO2_Pos (8U)
\r
19624 #define VADC_G_ARBPR_PRIO2_Msk (0x00000003U << VADC_G_ARBPR_PRIO2_Pos)
\r
19626 #define VADC_G_ARBPR_CSM0_Pos (3U)
\r
19627 #define VADC_G_ARBPR_CSM0_Msk (0x00000001U << VADC_G_ARBPR_CSM0_Pos)
\r
19629 #define VADC_G_ARBPR_CSM1_Pos (7U)
\r
19630 #define VADC_G_ARBPR_CSM1_Msk (0x00000001U << VADC_G_ARBPR_CSM1_Pos)
\r
19632 #define VADC_G_ARBPR_CSM2_Pos (11U)
\r
19633 #define VADC_G_ARBPR_CSM2_Msk (0x00000001U << VADC_G_ARBPR_CSM2_Pos)
\r
19635 #define VADC_G_ARBPR_ASEN0_Pos (24U)
\r
19636 #define VADC_G_ARBPR_ASEN0_Msk (0x00000001U << VADC_G_ARBPR_ASEN0_Pos)
\r
19638 #define VADC_G_ARBPR_ASEN1_Pos (25U)
\r
19639 #define VADC_G_ARBPR_ASEN1_Msk (0x00000001U << VADC_G_ARBPR_ASEN1_Pos)
\r
19641 #define VADC_G_ARBPR_ASEN2_Pos (26U)
\r
19642 #define VADC_G_ARBPR_ASEN2_Msk (0x00000001U << VADC_G_ARBPR_ASEN2_Pos)
\r
19644 /* VADC_G_CHASS = Channel Assignment Register, Group 0*/
\r
19645 #define VADC_G_CHASS_ASSCH0_Pos (0U)
\r
19646 #define VADC_G_CHASS_ASSCH0_Msk (0x00000001U << VADC_G_CHASS_ASSCH0_Pos)
\r
19648 #define VADC_G_CHASS_ASSCH1_Pos (1U)
\r
19649 #define VADC_G_CHASS_ASSCH1_Msk (0x00000001U << VADC_G_CHASS_ASSCH1_Pos)
\r
19651 #define VADC_G_CHASS_ASSCH2_Pos (2U)
\r
19652 #define VADC_G_CHASS_ASSCH2_Msk (0x00000001U << VADC_G_CHASS_ASSCH2_Pos)
\r
19654 #define VADC_G_CHASS_ASSCH3_Pos (3U)
\r
19655 #define VADC_G_CHASS_ASSCH3_Msk (0x00000001U << VADC_G_CHASS_ASSCH3_Pos)
\r
19657 #define VADC_G_CHASS_ASSCH4_Pos (4U)
\r
19658 #define VADC_G_CHASS_ASSCH4_Msk (0x00000001U << VADC_G_CHASS_ASSCH4_Pos)
\r
19660 #define VADC_G_CHASS_ASSCH5_Pos (5U)
\r
19661 #define VADC_G_CHASS_ASSCH5_Msk (0x00000001U << VADC_G_CHASS_ASSCH5_Pos)
\r
19663 #define VADC_G_CHASS_ASSCH6_Pos (6U)
\r
19664 #define VADC_G_CHASS_ASSCH6_Msk (0x00000001U << VADC_G_CHASS_ASSCH6_Pos)
\r
19666 #define VADC_G_CHASS_ASSCH7_Pos (7U)
\r
19667 #define VADC_G_CHASS_ASSCH7_Msk (0x00000001U << VADC_G_CHASS_ASSCH7_Pos)
\r
19669 /* VADC_G_ICLASS0 = Input Class Register 0, Group 0*/
\r
19670 #define VADC_G_ICLASS_STCS_Pos (0U)
\r
19671 #define VADC_G_ICLASS_STCS_Msk (0x0000001FU << VADC_G_ICLASS_STCS_Pos)
\r
19673 #define VADC_G_ICLASS_CMS_Pos (8U)
\r
19674 #define VADC_G_ICLASS_CMS_Msk (0x00000007U << VADC_G_ICLASS_CMS_Pos)
\r
19676 #define VADC_G_ICLASS_STCE_Pos (16U)
\r
19677 #define VADC_G_ICLASS_STCE_Msk (0x0000001FU << VADC_G_ICLASS_STCE_Pos)
\r
19679 #define VADC_G_ICLASS_CME_Pos (24U)
\r
19680 #define VADC_G_ICLASS_CME_Msk (0x00000007U << VADC_G_ICLASS_CME_Pos)
\r
19682 /* VADC_G_ALIAS = Alias Register, Group 0*/
\r
19683 #define VADC_G_ALIAS_ALIAS0_Pos (0U)
\r
19684 #define VADC_G_ALIAS_ALIAS0_Msk (0x0000001FU << VADC_G_ALIAS_ALIAS0_Pos)
\r
19686 #define VADC_G_ALIAS_ALIAS1_Pos (8U)
\r
19687 #define VADC_G_ALIAS_ALIAS1_Msk (0x0000001FU << VADC_G_ALIAS_ALIAS1_Pos)
\r
19689 /* VADC_G_BOUND = Boundary Select Register, Group 0*/
\r
19690 #define VADC_G_BOUND_BOUNDARY0_Pos (0U)
\r
19691 #define VADC_G_BOUND_BOUNDARY0_Msk (0x00000FFFU << VADC_G_BOUND_BOUNDARY0_Pos)
\r
19693 #define VADC_G_BOUND_BOUNDARY1_Pos (16U)
\r
19694 #define VADC_G_BOUND_BOUNDARY1_Msk (0x00000FFFU << VADC_G_BOUND_BOUNDARY1_Pos)
\r
19696 /* VADC_G_SYNCTR = Synchronization Control Register, Group 0*/
\r
19697 #define VADC_G_SYNCTR_STSEL_Pos (0U)
\r
19698 #define VADC_G_SYNCTR_STSEL_Msk (0x00000003U << VADC_G_SYNCTR_STSEL_Pos)
\r
19700 #define VADC_G_SYNCTR_EVALR1_Pos (4U)
\r
19701 #define VADC_G_SYNCTR_EVALR1_Msk (0x00000001U << VADC_G_SYNCTR_EVALR1_Pos)
\r
19703 #define VADC_G_SYNCTR_EVALR2_Pos (5U)
\r
19704 #define VADC_G_SYNCTR_EVALR2_Msk (0x00000001U << VADC_G_SYNCTR_EVALR2_Pos)
\r
19706 #define VADC_G_SYNCTR_EVALR3_Pos (6U)
\r
19707 #define VADC_G_SYNCTR_EVALR3_Msk (0x00000001U << VADC_G_SYNCTR_EVALR3_Pos)
\r
19709 /* VADC_G_BFL = Boundary Flag Register, Group 0*/
\r
19710 #define VADC_G_BFL_BFL0_Pos (0U)
\r
19711 #define VADC_G_BFL_BFL0_Msk (0x00000001U << VADC_G_BFL_BFL0_Pos)
\r
19713 #define VADC_G_BFL_BFL1_Pos (1U)
\r
19714 #define VADC_G_BFL_BFL1_Msk (0x00000001U << VADC_G_BFL_BFL1_Pos)
\r
19716 #define VADC_G_BFL_BFL2_Pos (2U)
\r
19717 #define VADC_G_BFL_BFL2_Msk (0x00000001U << VADC_G_BFL_BFL2_Pos)
\r
19719 #define VADC_G_BFL_BFL3_Pos (3U)
\r
19720 #define VADC_G_BFL_BFL3_Msk (0x00000001U << VADC_G_BFL_BFL3_Pos)
\r
19722 #define VADC_G_BFL_BFA0_Pos (8U)
\r
19723 #define VADC_G_BFL_BFA0_Msk (0x00000001U << VADC_G_BFL_BFA0_Pos)
\r
19725 #define VADC_G_BFL_BFA1_Pos (9U)
\r
19726 #define VADC_G_BFL_BFA1_Msk (0x00000001U << VADC_G_BFL_BFA1_Pos)
\r
19728 #define VADC_G_BFL_BFA2_Pos (10U)
\r
19729 #define VADC_G_BFL_BFA2_Msk (0x00000001U << VADC_G_BFL_BFA2_Pos)
\r
19731 #define VADC_G_BFL_BFA3_Pos (11U)
\r
19732 #define VADC_G_BFL_BFA3_Msk (0x00000001U << VADC_G_BFL_BFA3_Pos)
\r
19734 #define VADC_G_BFL_BFI0_Pos (16U)
\r
19735 #define VADC_G_BFL_BFI0_Msk (0x00000001U << VADC_G_BFL_BFI0_Pos)
\r
19737 #define VADC_G_BFL_BFI1_Pos (17U)
\r
19738 #define VADC_G_BFL_BFI1_Msk (0x00000001U << VADC_G_BFL_BFI1_Pos)
\r
19740 #define VADC_G_BFL_BFI2_Pos (18U)
\r
19741 #define VADC_G_BFL_BFI2_Msk (0x00000001U << VADC_G_BFL_BFI2_Pos)
\r
19743 #define VADC_G_BFL_BFI3_Pos (19U)
\r
19744 #define VADC_G_BFL_BFI3_Msk (0x00000001U << VADC_G_BFL_BFI3_Pos)
\r
19747 /* VADC_G_QCTRL0 = Queue x Source Control Register, Group 0*/
\r
19748 #define VADC_G_QCTRL0_SRCRESREG_Pos (0U)
\r
19749 #define VADC_G_QCTRL0_SRCRESREG_Msk (0x0000000FU << VADC_G_QCTRL0_SRCRESREG_Pos)
\r
19751 #define VADC_G_QCTRL0_XTSEL_Pos (8U)
\r
19752 #define VADC_G_QCTRL0_XTSEL_Msk (0x0000000FU << VADC_G_QCTRL0_XTSEL_Pos)
\r
19754 #define VADC_G_QCTRL0_XTLVL_Pos (12U)
\r
19755 #define VADC_G_QCTRL0_XTLVL_Msk (0x00000001U << VADC_G_QCTRL0_XTLVL_Pos)
\r
19757 #define VADC_G_QCTRL0_XTMODE_Pos (13U)
\r
19758 #define VADC_G_QCTRL0_XTMODE_Msk (0x00000003U << VADC_G_QCTRL0_XTMODE_Pos)
\r
19760 #define VADC_G_QCTRL0_XTWC_Pos (15U)
\r
19761 #define VADC_G_QCTRL0_XTWC_Msk (0x00000001U << VADC_G_QCTRL0_XTWC_Pos)
\r
19763 #define VADC_G_QCTRL0_GTSEL_Pos (16U)
\r
19764 #define VADC_G_QCTRL0_GTSEL_Msk (0x0000000FU << VADC_G_QCTRL0_GTSEL_Pos)
\r
19766 #define VADC_G_QCTRL0_GTLVL_Pos (20U)
\r
19767 #define VADC_G_QCTRL0_GTLVL_Msk (0x00000001U << VADC_G_QCTRL0_GTLVL_Pos)
\r
19769 #define VADC_G_QCTRL0_GTWC_Pos (23U)
\r
19770 #define VADC_G_QCTRL0_GTWC_Msk (0x00000001U << VADC_G_QCTRL0_GTWC_Pos)
\r
19772 #define VADC_G_QCTRL0_TMEN_Pos (28U)
\r
19773 #define VADC_G_QCTRL0_TMEN_Msk (0x00000001U << VADC_G_QCTRL0_TMEN_Pos)
\r
19775 #define VADC_G_QCTRL0_TMWC_Pos (31U)
\r
19776 #define VADC_G_QCTRL0_TMWC_Msk (0x00000001U << VADC_G_QCTRL0_TMWC_Pos)
\r
19778 /* VADC_G_QMR0 = Queue x Mode Register, Group 0*/
\r
19779 #define VADC_G_QMR0_ENGT_Pos (0U)
\r
19780 #define VADC_G_QMR0_ENGT_Msk (0x00000003U << VADC_G_QMR0_ENGT_Pos)
\r
19782 #define VADC_G_QMR0_ENTR_Pos (2U)
\r
19783 #define VADC_G_QMR0_ENTR_Msk (0x00000001U << VADC_G_QMR0_ENTR_Pos)
\r
19785 #define VADC_G_QMR0_CLRV_Pos (8U)
\r
19786 #define VADC_G_QMR0_CLRV_Msk (0x00000001U << VADC_G_QMR0_CLRV_Pos)
\r
19788 #define VADC_G_QMR0_TREV_Pos (9U)
\r
19789 #define VADC_G_QMR0_TREV_Msk (0x00000001U << VADC_G_QMR0_TREV_Pos)
\r
19791 #define VADC_G_QMR0_FLUSH_Pos (10U)
\r
19792 #define VADC_G_QMR0_FLUSH_Msk (0x00000001U << VADC_G_QMR0_FLUSH_Pos)
\r
19794 #define VADC_G_QMR0_CEV_Pos (11U)
\r
19795 #define VADC_G_QMR0_CEV_Msk (0x00000001U << VADC_G_QMR0_CEV_Pos)
\r
19797 #define VADC_G_QMR0_RPTDIS_Pos (16U)
\r
19798 #define VADC_G_QMR0_RPTDIS_Msk (0x00000001U << VADC_G_QMR0_RPTDIS_Pos)
\r
19800 /* VADC_G_QSR0 = Queue x Status Register, Group 0*/
\r
19801 #define VADC_G_QSR0_FILL_Pos (0U)
\r
19802 #define VADC_G_QSR0_FILL_Msk (0x0000000FU << VADC_G_QSR0_FILL_Pos)
\r
19804 #define VADC_G_QSR0_EMPTY_Pos (5U)
\r
19805 #define VADC_G_QSR0_EMPTY_Msk (0x00000001U << VADC_G_QSR0_EMPTY_Pos)
\r
19807 #define VADC_G_QSR0_REQGT_Pos (7U)
\r
19808 #define VADC_G_QSR0_REQGT_Msk (0x00000001U << VADC_G_QSR0_REQGT_Pos)
\r
19810 #define VADC_G_QSR0_EV_Pos (8U)
\r
19811 #define VADC_G_QSR0_EV_Msk (0x00000001U << VADC_G_QSR0_EV_Pos)
\r
19813 /* VADC_G_Q0R0 = Queue x Register 0, Group 0*/
\r
19814 #define VADC_G_Q0R0_REQCHNR_Pos (0U)
\r
19815 #define VADC_G_Q0R0_REQCHNR_Msk (0x0000001FU << VADC_G_Q0R0_REQCHNR_Pos)
\r
19817 #define VADC_G_Q0R0_RF_Pos (5U)
\r
19818 #define VADC_G_Q0R0_RF_Msk (0x00000001U << VADC_G_Q0R0_RF_Pos)
\r
19820 #define VADC_G_Q0R0_ENSI_Pos (6U)
\r
19821 #define VADC_G_Q0R0_ENSI_Msk (0x00000001U << VADC_G_Q0R0_ENSI_Pos)
\r
19823 #define VADC_G_Q0R0_EXTR_Pos (7U)
\r
19824 #define VADC_G_Q0R0_EXTR_Msk (0x00000001U << VADC_G_Q0R0_EXTR_Pos)
\r
19826 #define VADC_G_Q0R0_V_Pos (8U)
\r
19827 #define VADC_G_Q0R0_V_Msk (0x00000001U << VADC_G_Q0R0_V_Pos)
\r
19829 /* VADC_G_QBUR0 = Queue x Backup Register, Group 0*/
\r
19830 #define VADC_G_QBUR0_REQCHNR_Pos (0U)
\r
19831 #define VADC_G_QBUR0_REQCHNR_Msk (0x0000001FU << VADC_G_QBUR0_REQCHNR_Pos)
\r
19833 #define VADC_G_QBUR0_RF_Pos (5U)
\r
19834 #define VADC_G_QBUR0_RF_Msk (0x00000001U << VADC_G_QBUR0_RF_Pos)
\r
19836 #define VADC_G_QBUR0_ENSI_Pos (6U)
\r
19837 #define VADC_G_QBUR0_ENSI_Msk (0x00000001U << VADC_G_QBUR0_ENSI_Pos)
\r
19839 #define VADC_G_QBUR0_EXTR_Pos (7U)
\r
19840 #define VADC_G_QBUR0_EXTR_Msk (0x00000001U << VADC_G_QBUR0_EXTR_Pos)
\r
19842 #define VADC_G_QBUR0_V_Pos (8U)
\r
19843 #define VADC_G_QBUR0_V_Msk (0x00000001U << VADC_G_QBUR0_V_Pos)
\r
19845 #define VADC_G_QBUR0_r_Pos (9U)
\r
19846 #define VADC_G_QBUR0_r_Msk (0x007FFFFFU << VADC_G_QBUR0_r_Pos)
\r
19848 /* VADC_G_QINR0 = Queue x Input Register, Group 0*/
\r
19849 #define VADC_G_QINR0_REQCHNR_Pos (0U)
\r
19850 #define VADC_G_QINR0_REQCHNR_Msk (0x0000001FU << VADC_G_QINR0_REQCHNR_Pos)
\r
19852 #define VADC_G_QINR0_RF_Pos (5U)
\r
19853 #define VADC_G_QINR0_RF_Msk (0x00000001U << VADC_G_QINR0_RF_Pos)
\r
19855 #define VADC_G_QINR0_ENSI_Pos (6U)
\r
19856 #define VADC_G_QINR0_ENSI_Msk (0x00000001U << VADC_G_QINR0_ENSI_Pos)
\r
19858 #define VADC_G_QINR0_EXTR_Pos (7U)
\r
19859 #define VADC_G_QINR0_EXTR_Msk (0x00000001U << VADC_G_QINR0_EXTR_Pos)
\r
19861 /* VADC_G_ASCTRL = Autoscan Source Control Register, Group 0*/
\r
19862 #define VADC_G_ASCTRL_SRCRESREG_Pos (0U)
\r
19863 #define VADC_G_ASCTRL_SRCRESREG_Msk (0x0000000FU << VADC_G_ASCTRL_SRCRESREG_Pos)
\r
19865 #define VADC_G_ASCTRL_XTSEL_Pos (8U)
\r
19866 #define VADC_G_ASCTRL_XTSEL_Msk (0x0000000FU << VADC_G_ASCTRL_XTSEL_Pos)
\r
19868 #define VADC_G_ASCTRL_XTLVL_Pos (12U)
\r
19869 #define VADC_G_ASCTRL_XTLVL_Msk (0x00000001U << VADC_G_ASCTRL_XTLVL_Pos)
\r
19871 #define VADC_G_ASCTRL_XTMODE_Pos (13U)
\r
19872 #define VADC_G_ASCTRL_XTMODE_Msk (0x00000003U << VADC_G_ASCTRL_XTMODE_Pos)
\r
19874 #define VADC_G_ASCTRL_XTWC_Pos (15U)
\r
19875 #define VADC_G_ASCTRL_XTWC_Msk (0x00000001U << VADC_G_ASCTRL_XTWC_Pos)
\r
19877 #define VADC_G_ASCTRL_GTSEL_Pos (16U)
\r
19878 #define VADC_G_ASCTRL_GTSEL_Msk (0x0000000FU << VADC_G_ASCTRL_GTSEL_Pos)
\r
19880 #define VADC_G_ASCTRL_GTLVL_Pos (20U)
\r
19881 #define VADC_G_ASCTRL_GTLVL_Msk (0x00000001U << VADC_G_ASCTRL_GTLVL_Pos)
\r
19883 #define VADC_G_ASCTRL_GTWC_Pos (23U)
\r
19884 #define VADC_G_ASCTRL_GTWC_Msk (0x00000001U << VADC_G_ASCTRL_GTWC_Pos)
\r
19886 #define VADC_G_ASCTRL_TMEN_Pos (28U)
\r
19887 #define VADC_G_ASCTRL_TMEN_Msk (0x00000001U << VADC_G_ASCTRL_TMEN_Pos)
\r
19889 #define VADC_G_ASCTRL_TMWC_Pos (31U)
\r
19890 #define VADC_G_ASCTRL_TMWC_Msk (0x00000001U << VADC_G_ASCTRL_TMWC_Pos)
\r
19892 /* VADC_G_ASMR = Autoscan Source Mode Register, Group 0*/
\r
19893 #define VADC_G_ASMR_ENGT_Pos (0U)
\r
19894 #define VADC_G_ASMR_ENGT_Msk (0x00000003U << VADC_G_ASMR_ENGT_Pos)
\r
19896 #define VADC_G_ASMR_ENTR_Pos (2U)
\r
19897 #define VADC_G_ASMR_ENTR_Msk (0x00000001U << VADC_G_ASMR_ENTR_Pos)
\r
19899 #define VADC_G_ASMR_ENSI_Pos (3U)
\r
19900 #define VADC_G_ASMR_ENSI_Msk (0x00000001U << VADC_G_ASMR_ENSI_Pos)
\r
19902 #define VADC_G_ASMR_SCAN_Pos (4U)
\r
19903 #define VADC_G_ASMR_SCAN_Msk (0x00000001U << VADC_G_ASMR_SCAN_Pos)
\r
19905 #define VADC_G_ASMR_LDM_Pos (5U)
\r
19906 #define VADC_G_ASMR_LDM_Msk (0x00000001U << VADC_G_ASMR_LDM_Pos)
\r
19908 #define VADC_G_ASMR_REQGT_Pos (7U)
\r
19909 #define VADC_G_ASMR_REQGT_Msk (0x00000001U << VADC_G_ASMR_REQGT_Pos)
\r
19911 #define VADC_G_ASMR_CLRPND_Pos (8U)
\r
19912 #define VADC_G_ASMR_CLRPND_Msk (0x00000001U << VADC_G_ASMR_CLRPND_Pos)
\r
19914 #define VADC_G_ASMR_LDEV_Pos (9U)
\r
19915 #define VADC_G_ASMR_LDEV_Msk (0x00000001U << VADC_G_ASMR_LDEV_Pos)
\r
19917 #define VADC_G_ASMR_RPTDIS_Pos (16U)
\r
19918 #define VADC_G_ASMR_RPTDIS_Msk (0x00000001U << VADC_G_ASMR_RPTDIS_Pos)
\r
19920 /* VADC_G_ASSEL = Autoscan Source Channel Select Register, Group 0*/
\r
19921 #define VADC_G_ASSEL_CHSEL_Pos (0U)
\r
19922 #define VADC_G_ASSEL_CHSEL_Msk (0xFFFFFFFFU << VADC_G_ASSEL_CHSEL_Pos)
\r
19924 /* VADC_G_ASPND = Autoscan Source Pending Register, Group 0*/
\r
19925 #define VADC_G_ASPND_CHPND_Pos (0U)
\r
19926 #define VADC_G_ASPND_CHPND_Msk (0xFFFFFFFFU << VADC_G_ASPND_CHPND_Pos)
\r
19928 /* VADC_G_CEFLAG = Channel Event Flag Register, Group 0*/
\r
19929 #define VADC_G_CEFLAG_CEV0_Pos (0U)
\r
19930 #define VADC_G_CEFLAG_CEV0_Msk (0x00000001U << VADC_G_CEFLAG_CEV0_Pos)
\r
19932 #define VADC_G_CEFLAG_CEV1_Pos (1U)
\r
19933 #define VADC_G_CEFLAG_CEV1_Msk (0x00000001U << VADC_G_CEFLAG_CEV1_Pos)
\r
19935 #define VADC_G_CEFLAG_CEV2_Pos (2U)
\r
19936 #define VADC_G_CEFLAG_CEV2_Msk (0x00000001U << VADC_G_CEFLAG_CEV2_Pos)
\r
19938 #define VADC_G_CEFLAG_CEV3_Pos (3U)
\r
19939 #define VADC_G_CEFLAG_CEV3_Msk (0x00000001U << VADC_G_CEFLAG_CEV3_Pos)
\r
19941 #define VADC_G_CEFLAG_CEV4_Pos (4U)
\r
19942 #define VADC_G_CEFLAG_CEV4_Msk (0x00000001U << VADC_G_CEFLAG_CEV4_Pos)
\r
19944 #define VADC_G_CEFLAG_CEV5_Pos (5U)
\r
19945 #define VADC_G_CEFLAG_CEV5_Msk (0x00000001U << VADC_G_CEFLAG_CEV5_Pos)
\r
19947 #define VADC_G_CEFLAG_CEV6_Pos (6U)
\r
19948 #define VADC_G_CEFLAG_CEV6_Msk (0x00000001U << VADC_G_CEFLAG_CEV6_Pos)
\r
19950 #define VADC_G_CEFLAG_CEV7_Pos (7U)
\r
19951 #define VADC_G_CEFLAG_CEV7_Msk (0x00000001U << VADC_G_CEFLAG_CEV7_Pos)
\r
19953 /* VADC_G_REFLAG = Result Event Flag Register, Group 0*/
\r
19954 #define VADC_G_REFLAG_REV0_Pos (0U)
\r
19955 #define VADC_G_REFLAG_REV0_Msk (0x00000001U << VADC_G_REFLAG_REV0_Pos)
\r
19957 #define VADC_G_REFLAG_REV1_Pos (1U)
\r
19958 #define VADC_G_REFLAG_REV1_Msk (0x00000001U << VADC_G_REFLAG_REV1_Pos)
\r
19960 #define VADC_G_REFLAG_REV2_Pos (2U)
\r
19961 #define VADC_G_REFLAG_REV2_Msk (0x00000001U << VADC_G_REFLAG_REV2_Pos)
\r
19963 #define VADC_G_REFLAG_REV3_Pos (3U)
\r
19964 #define VADC_G_REFLAG_REV3_Msk (0x00000001U << VADC_G_REFLAG_REV3_Pos)
\r
19966 #define VADC_G_REFLAG_REV4_Pos (4U)
\r
19967 #define VADC_G_REFLAG_REV4_Msk (0x00000001U << VADC_G_REFLAG_REV4_Pos)
\r
19969 #define VADC_G_REFLAG_REV5_Pos (5U)
\r
19970 #define VADC_G_REFLAG_REV5_Msk (0x00000001U << VADC_G_REFLAG_REV5_Pos)
\r
19972 #define VADC_G_REFLAG_REV6_Pos (6U)
\r
19973 #define VADC_G_REFLAG_REV6_Msk (0x00000001U << VADC_G_REFLAG_REV6_Pos)
\r
19975 #define VADC_G_REFLAG_REV7_Pos (7U)
\r
19976 #define VADC_G_REFLAG_REV7_Msk (0x00000001U << VADC_G_REFLAG_REV7_Pos)
\r
19978 #define VADC_G_REFLAG_REV8_Pos (8U)
\r
19979 #define VADC_G_REFLAG_REV8_Msk (0x00000001U << VADC_G_REFLAG_REV8_Pos)
\r
19981 #define VADC_G_REFLAG_REV9_Pos (9U)
\r
19982 #define VADC_G_REFLAG_REV9_Msk (0x00000001U << VADC_G_REFLAG_REV9_Pos)
\r
19984 #define VADC_G_REFLAG_REV10_Pos (10U)
\r
19985 #define VADC_G_REFLAG_REV10_Msk (0x00000001U << VADC_G_REFLAG_REV10_Pos)
\r
19987 #define VADC_G_REFLAG_REV11_Pos (11U)
\r
19988 #define VADC_G_REFLAG_REV11_Msk (0x00000001U << VADC_G_REFLAG_REV11_Pos)
\r
19990 #define VADC_G_REFLAG_REV12_Pos (12U)
\r
19991 #define VADC_G_REFLAG_REV12_Msk (0x00000001U << VADC_G_REFLAG_REV12_Pos)
\r
19993 #define VADC_G_REFLAG_REV13_Pos (13U)
\r
19994 #define VADC_G_REFLAG_REV13_Msk (0x00000001U << VADC_G_REFLAG_REV13_Pos)
\r
19996 #define VADC_G_REFLAG_REV14_Pos (14U)
\r
19997 #define VADC_G_REFLAG_REV14_Msk (0x00000001U << VADC_G_REFLAG_REV14_Pos)
\r
19999 #define VADC_G_REFLAG_REV15_Pos (15U)
\r
20000 #define VADC_G_REFLAG_REV15_Msk (0x00000001U << VADC_G_REFLAG_REV15_Pos)
\r
20002 /* VADC_G_SEFLAG = Source Event Flag Register, Group 0*/
\r
20003 #define VADC_G_SEFLAG_SEV0_Pos (0U)
\r
20004 #define VADC_G_SEFLAG_SEV0_Msk (0x00000001U << VADC_G_SEFLAG_SEV0_Pos)
\r
20006 #define VADC_G_SEFLAG_SEV1_Pos (1U)
\r
20007 #define VADC_G_SEFLAG_SEV1_Msk (0x00000001U << VADC_G_SEFLAG_SEV1_Pos)
\r
20009 /* VADC_G_CEFCLR = Channel Event Flag Clear Register, Group 0*/
\r
20010 #define VADC_G_CEFCLR_CEV0_Pos (0U)
\r
20011 #define VADC_G_CEFCLR_CEV0_Msk (0x00000001U << VADC_G_CEFCLR_CEV0_Pos)
\r
20013 #define VADC_G_CEFCLR_CEV1_Pos (1U)
\r
20014 #define VADC_G_CEFCLR_CEV1_Msk (0x00000001U << VADC_G_CEFCLR_CEV1_Pos)
\r
20016 #define VADC_G_CEFCLR_CEV2_Pos (2U)
\r
20017 #define VADC_G_CEFCLR_CEV2_Msk (0x00000001U << VADC_G_CEFCLR_CEV2_Pos)
\r
20019 #define VADC_G_CEFCLR_CEV3_Pos (3U)
\r
20020 #define VADC_G_CEFCLR_CEV3_Msk (0x00000001U << VADC_G_CEFCLR_CEV3_Pos)
\r
20022 #define VADC_G_CEFCLR_CEV4_Pos (4U)
\r
20023 #define VADC_G_CEFCLR_CEV4_Msk (0x00000001U << VADC_G_CEFCLR_CEV4_Pos)
\r
20025 #define VADC_G_CEFCLR_CEV5_Pos (5U)
\r
20026 #define VADC_G_CEFCLR_CEV5_Msk (0x00000001U << VADC_G_CEFCLR_CEV5_Pos)
\r
20028 #define VADC_G_CEFCLR_CEV6_Pos (6U)
\r
20029 #define VADC_G_CEFCLR_CEV6_Msk (0x00000001U << VADC_G_CEFCLR_CEV6_Pos)
\r
20031 #define VADC_G_CEFCLR_CEV7_Pos (7U)
\r
20032 #define VADC_G_CEFCLR_CEV7_Msk (0x00000001U << VADC_G_CEFCLR_CEV7_Pos)
\r
20034 /* VADC_G_REFCLR = Result Event Flag Clear Register, Group 0*/
\r
20035 #define VADC_G_REFCLR_REV0_Pos (0U)
\r
20036 #define VADC_G_REFCLR_REV0_Msk (0x00000001U << VADC_G_REFCLR_REV0_Pos)
\r
20038 #define VADC_G_REFCLR_REV1_Pos (1U)
\r
20039 #define VADC_G_REFCLR_REV1_Msk (0x00000001U << VADC_G_REFCLR_REV1_Pos)
\r
20041 #define VADC_G_REFCLR_REV2_Pos (2U)
\r
20042 #define VADC_G_REFCLR_REV2_Msk (0x00000001U << VADC_G_REFCLR_REV2_Pos)
\r
20044 #define VADC_G_REFCLR_REV3_Pos (3U)
\r
20045 #define VADC_G_REFCLR_REV3_Msk (0x00000001U << VADC_G_REFCLR_REV3_Pos)
\r
20047 #define VADC_G_REFCLR_REV4_Pos (4U)
\r
20048 #define VADC_G_REFCLR_REV4_Msk (0x00000001U << VADC_G_REFCLR_REV4_Pos)
\r
20050 #define VADC_G_REFCLR_REV5_Pos (5U)
\r
20051 #define VADC_G_REFCLR_REV5_Msk (0x00000001U << VADC_G_REFCLR_REV5_Pos)
\r
20053 #define VADC_G_REFCLR_REV6_Pos (6U)
\r
20054 #define VADC_G_REFCLR_REV6_Msk (0x00000001U << VADC_G_REFCLR_REV6_Pos)
\r
20056 #define VADC_G_REFCLR_REV7_Pos (7U)
\r
20057 #define VADC_G_REFCLR_REV7_Msk (0x00000001U << VADC_G_REFCLR_REV7_Pos)
\r
20059 #define VADC_G_REFCLR_REV8_Pos (8U)
\r
20060 #define VADC_G_REFCLR_REV8_Msk (0x00000001U << VADC_G_REFCLR_REV8_Pos)
\r
20062 #define VADC_G_REFCLR_REV9_Pos (9U)
\r
20063 #define VADC_G_REFCLR_REV9_Msk (0x00000001U << VADC_G_REFCLR_REV9_Pos)
\r
20065 #define VADC_G_REFCLR_REV10_Pos (10U)
\r
20066 #define VADC_G_REFCLR_REV10_Msk (0x00000001U << VADC_G_REFCLR_REV10_Pos)
\r
20068 #define VADC_G_REFCLR_REV11_Pos (11U)
\r
20069 #define VADC_G_REFCLR_REV11_Msk (0x00000001U << VADC_G_REFCLR_REV11_Pos)
\r
20071 #define VADC_G_REFCLR_REV12_Pos (12U)
\r
20072 #define VADC_G_REFCLR_REV12_Msk (0x00000001U << VADC_G_REFCLR_REV12_Pos)
\r
20074 #define VADC_G_REFCLR_REV13_Pos (13U)
\r
20075 #define VADC_G_REFCLR_REV13_Msk (0x00000001U << VADC_G_REFCLR_REV13_Pos)
\r
20077 #define VADC_G_REFCLR_REV14_Pos (14U)
\r
20078 #define VADC_G_REFCLR_REV14_Msk (0x00000001U << VADC_G_REFCLR_REV14_Pos)
\r
20080 #define VADC_G_REFCLR_REV15_Pos (15U)
\r
20081 #define VADC_G_REFCLR_REV15_Msk (0x00000001U << VADC_G_REFCLR_REV15_Pos)
\r
20083 /* VADC_G_SEFCLR = Source Event Flag Clear Register, Group 0*/
\r
20084 #define VADC_G_SEFCLR_SEV0_Pos (0U)
\r
20085 #define VADC_G_SEFCLR_SEV0_Msk (0x00000001U << VADC_G_SEFCLR_SEV0_Pos)
\r
20087 #define VADC_G_SEFCLR_SEV1_Pos (1U)
\r
20088 #define VADC_G_SEFCLR_SEV1_Msk (0x00000001U << VADC_G_SEFCLR_SEV1_Pos)
\r
20090 /* VADC_G_CEVNP0 = Channel Event Node Pointer Register 0, Group 0*/
\r
20091 #define VADC_G_CEVNP0_CEV0NP_Pos (0U)
\r
20092 #define VADC_G_CEVNP0_CEV0NP_Msk (0x0000000FU << VADC_G_CEVNP0_CEV0NP_Pos)
\r
20094 #define VADC_G_CEVNP0_CEV1NP_Pos (4U)
\r
20095 #define VADC_G_CEVNP0_CEV1NP_Msk (0x0000000FU << VADC_G_CEVNP0_CEV1NP_Pos)
\r
20097 #define VADC_G_CEVNP0_CEV2NP_Pos (8U)
\r
20098 #define VADC_G_CEVNP0_CEV2NP_Msk (0x0000000FU << VADC_G_CEVNP0_CEV2NP_Pos)
\r
20100 #define VADC_G_CEVNP0_CEV3NP_Pos (12U)
\r
20101 #define VADC_G_CEVNP0_CEV3NP_Msk (0x0000000FU << VADC_G_CEVNP0_CEV3NP_Pos)
\r
20103 #define VADC_G_CEVNP0_CEV4NP_Pos (16U)
\r
20104 #define VADC_G_CEVNP0_CEV4NP_Msk (0x0000000FU << VADC_G_CEVNP0_CEV4NP_Pos)
\r
20106 #define VADC_G_CEVNP0_CEV5NP_Pos (20U)
\r
20107 #define VADC_G_CEVNP0_CEV5NP_Msk (0x0000000FU << VADC_G_CEVNP0_CEV5NP_Pos)
\r
20109 #define VADC_G_CEVNP0_CEV6NP_Pos (24U)
\r
20110 #define VADC_G_CEVNP0_CEV6NP_Msk (0x0000000FU << VADC_G_CEVNP0_CEV6NP_Pos)
\r
20112 #define VADC_G_CEVNP0_CEV7NP_Pos (28U)
\r
20113 #define VADC_G_CEVNP0_CEV7NP_Msk (0x0000000FU << VADC_G_CEVNP0_CEV7NP_Pos)
\r
20115 /* VADC_G_REVNP0 = Result Event Node Pointer Register 0, Group 0*/
\r
20116 #define VADC_G_REVNP0_REV0NP_Pos (0U)
\r
20117 #define VADC_G_REVNP0_REV0NP_Msk (0x0000000FU << VADC_G_REVNP0_REV0NP_Pos)
\r
20119 #define VADC_G_REVNP0_REV1NP_Pos (4U)
\r
20120 #define VADC_G_REVNP0_REV1NP_Msk (0x0000000FU << VADC_G_REVNP0_REV1NP_Pos)
\r
20122 #define VADC_G_REVNP0_REV2NP_Pos (8U)
\r
20123 #define VADC_G_REVNP0_REV2NP_Msk (0x0000000FU << VADC_G_REVNP0_REV2NP_Pos)
\r
20125 #define VADC_G_REVNP0_REV3NP_Pos (12U)
\r
20126 #define VADC_G_REVNP0_REV3NP_Msk (0x0000000FU << VADC_G_REVNP0_REV3NP_Pos)
\r
20128 #define VADC_G_REVNP0_REV4NP_Pos (16U)
\r
20129 #define VADC_G_REVNP0_REV4NP_Msk (0x0000000FU << VADC_G_REVNP0_REV4NP_Pos)
\r
20131 #define VADC_G_REVNP0_REV5NP_Pos (20U)
\r
20132 #define VADC_G_REVNP0_REV5NP_Msk (0x0000000FU << VADC_G_REVNP0_REV5NP_Pos)
\r
20134 #define VADC_G_REVNP0_REV6NP_Pos (24U)
\r
20135 #define VADC_G_REVNP0_REV6NP_Msk (0x0000000FU << VADC_G_REVNP0_REV6NP_Pos)
\r
20137 #define VADC_G_REVNP0_REV7NP_Pos (28U)
\r
20138 #define VADC_G_REVNP0_REV7NP_Msk (0x0000000FU << VADC_G_REVNP0_REV7NP_Pos)
\r
20140 /* VADC_G_REVNP1 = Result Event Node Pointer Register 1, Group 0*/
\r
20141 #define VADC_G_REVNP1_REV8NP_Pos (0U)
\r
20142 #define VADC_G_REVNP1_REV8NP_Msk (0x0000000FU << VADC_G_REVNP1_REV8NP_Pos)
\r
20144 #define VADC_G_REVNP1_REV9NP_Pos (4U)
\r
20145 #define VADC_G_REVNP1_REV9NP_Msk (0x0000000FU << VADC_G_REVNP1_REV9NP_Pos)
\r
20147 #define VADC_G_REVNP1_REV10NP_Pos (8U)
\r
20148 #define VADC_G_REVNP1_REV10NP_Msk (0x0000000FU << VADC_G_REVNP1_REV10NP_Pos)
\r
20150 #define VADC_G_REVNP1_REV11NP_Pos (12U)
\r
20151 #define VADC_G_REVNP1_REV11NP_Msk (0x0000000FU << VADC_G_REVNP1_REV11NP_Pos)
\r
20153 #define VADC_G_REVNP1_REV12NP_Pos (16U)
\r
20154 #define VADC_G_REVNP1_REV12NP_Msk (0x0000000FU << VADC_G_REVNP1_REV12NP_Pos)
\r
20156 #define VADC_G_REVNP1_REV13NP_Pos (20U)
\r
20157 #define VADC_G_REVNP1_REV13NP_Msk (0x0000000FU << VADC_G_REVNP1_REV13NP_Pos)
\r
20159 #define VADC_G_REVNP1_REV14NP_Pos (24U)
\r
20160 #define VADC_G_REVNP1_REV14NP_Msk (0x0000000FU << VADC_G_REVNP1_REV14NP_Pos)
\r
20162 #define VADC_G_REVNP1_REV15NP_Pos (28U)
\r
20163 #define VADC_G_REVNP1_REV15NP_Msk (0x0000000FU << VADC_G_REVNP1_REV15NP_Pos)
\r
20165 /* VADC_G_SEVNP = Source Event Node Pointer Register, Group 0*/
\r
20166 #define VADC_G_SEVNP_SEV0NP_Pos (0U)
\r
20167 #define VADC_G_SEVNP_SEV0NP_Msk (0x0000000FU << VADC_G_SEVNP_SEV0NP_Pos)
\r
20169 #define VADC_G_SEVNP_SEV1NP_Pos (4U)
\r
20170 #define VADC_G_SEVNP_SEV1NP_Msk (0x0000000FU << VADC_G_SEVNP_SEV1NP_Pos)
\r
20172 /* VADC_G_SRACT = Service Request Software Activation Trigger, Group 0*/
\r
20173 #define VADC_G_SRACT_AGSR0_Pos (0U)
\r
20174 #define VADC_G_SRACT_AGSR0_Msk (0x00000001U << VADC_G_SRACT_AGSR0_Pos)
\r
20176 #define VADC_G_SRACT_AGSR1_Pos (1U)
\r
20177 #define VADC_G_SRACT_AGSR1_Msk (0x00000001U << VADC_G_SRACT_AGSR1_Pos)
\r
20179 #define VADC_G_SRACT_AGSR2_Pos (2U)
\r
20180 #define VADC_G_SRACT_AGSR2_Msk (0x00000001U << VADC_G_SRACT_AGSR2_Pos)
\r
20182 #define VADC_G_SRACT_AGSR3_Pos (3U)
\r
20183 #define VADC_G_SRACT_AGSR3_Msk (0x00000001U << VADC_G_SRACT_AGSR3_Pos)
\r
20185 #define VADC_G_SRACT_ASSR0_Pos (8U)
\r
20186 #define VADC_G_SRACT_ASSR0_Msk (0x00000001U << VADC_G_SRACT_ASSR0_Pos)
\r
20188 #define VADC_G_SRACT_ASSR1_Pos (9U)
\r
20189 #define VADC_G_SRACT_ASSR1_Msk (0x00000001U << VADC_G_SRACT_ASSR1_Pos)
\r
20191 #define VADC_G_SRACT_ASSR2_Pos (10U)
\r
20192 #define VADC_G_SRACT_ASSR2_Msk (0x00000001U << VADC_G_SRACT_ASSR2_Pos)
\r
20194 #define VADC_G_SRACT_ASSR3_Pos (11U)
\r
20195 #define VADC_G_SRACT_ASSR3_Msk (0x00000001U << VADC_G_SRACT_ASSR3_Pos)
\r
20197 /* VADC_G_EMUXCTR = E0ternal Multiplexer Control Register, Group x*/
\r
20198 #define VADC_G_EMUXCTR_EMUXSET_Pos (0U)
\r
20199 #define VADC_G_EMUXCTR_EMUXSET_Msk (0x00000007U << VADC_G_EMUXCTR_EMUXSET_Pos)
\r
20201 #define VADC_G_EMUXCTR_EMUXACT_Pos (8U)
\r
20202 #define VADC_G_EMUXCTR_EMUXACT_Msk (0x00000007U << VADC_G_EMUXCTR_EMUXACT_Pos)
\r
20204 #define VADC_G_EMUXCTR_EMUXCH_Pos (16U)
\r
20205 #define VADC_G_EMUXCTR_EMUXCH_Msk (0x000003FFU << VADC_G_EMUXCTR_EMUXCH_Pos)
\r
20207 #define VADC_G_EMUXCTR_EMUXMODE_Pos (26U)
\r
20208 #define VADC_G_EMUXCTR_EMUXMODE_Msk (0x00000003U << VADC_G_EMUXCTR_EMUXMODE_Pos)
\r
20210 #define VADC_G_EMUXCTR_EMXCOD_Pos (28U)
\r
20211 #define VADC_G_EMUXCTR_EMXCOD_Msk (0x00000001U << VADC_G_EMUXCTR_EMXCOD_Pos)
\r
20213 #define VADC_G_EMUXCTR_EMXST_Pos (29U)
\r
20214 #define VADC_G_EMUXCTR_EMXST_Msk (0x00000001U << VADC_G_EMUXCTR_EMXST_Pos)
\r
20216 #define VADC_G_EMUXCTR_EMXCSS_Pos (30U)
\r
20217 #define VADC_G_EMUXCTR_EMXCSS_Msk (0x00000001U << VADC_G_EMUXCTR_EMXCSS_Pos)
\r
20219 #define VADC_G_EMUXCTR_EMXWC_Pos (31U)
\r
20220 #define VADC_G_EMUXCTR_EMXWC_Msk (0x00000001U << VADC_G_EMUXCTR_EMXWC_Pos)
\r
20222 /* VADC_G_VFR = Valid Flag Register, Group 0*/
\r
20223 #define VADC_G_VFR_VF0_Pos (0U)
\r
20224 #define VADC_G_VFR_VF0_Msk (0x00000001U << VADC_G_VFR_VF0_Pos)
\r
20226 #define VADC_G_VFR_VF1_Pos (1U)
\r
20227 #define VADC_G_VFR_VF1_Msk (0x00000001U << VADC_G_VFR_VF1_Pos)
\r
20229 #define VADC_G_VFR_VF2_Pos (2U)
\r
20230 #define VADC_G_VFR_VF2_Msk (0x00000001U << VADC_G_VFR_VF2_Pos)
\r
20232 #define VADC_G_VFR_VF3_Pos (3U)
\r
20233 #define VADC_G_VFR_VF3_Msk (0x00000001U << VADC_G_VFR_VF3_Pos)
\r
20235 #define VADC_G_VFR_VF4_Pos (4U)
\r
20236 #define VADC_G_VFR_VF4_Msk (0x00000001U << VADC_G_VFR_VF4_Pos)
\r
20238 #define VADC_G_VFR_VF5_Pos (5U)
\r
20239 #define VADC_G_VFR_VF5_Msk (0x00000001U << VADC_G_VFR_VF5_Pos)
\r
20241 #define VADC_G_VFR_VF6_Pos (6U)
\r
20242 #define VADC_G_VFR_VF6_Msk (0x00000001U << VADC_G_VFR_VF6_Pos)
\r
20244 #define VADC_G_VFR_VF7_Pos (7U)
\r
20245 #define VADC_G_VFR_VF7_Msk (0x00000001U << VADC_G_VFR_VF7_Pos)
\r
20247 #define VADC_G_VFR_VF8_Pos (8U)
\r
20248 #define VADC_G_VFR_VF8_Msk (0x00000001U << VADC_G_VFR_VF8_Pos)
\r
20250 #define VADC_G_VFR_VF9_Pos (9U)
\r
20251 #define VADC_G_VFR_VF9_Msk (0x00000001U << VADC_G_VFR_VF9_Pos)
\r
20253 #define VADC_G_VFR_VF10_Pos (10U)
\r
20254 #define VADC_G_VFR_VF10_Msk (0x00000001U << VADC_G_VFR_VF10_Pos)
\r
20256 #define VADC_G_VFR_VF11_Pos (11U)
\r
20257 #define VADC_G_VFR_VF11_Msk (0x00000001U << VADC_G_VFR_VF11_Pos)
\r
20259 #define VADC_G_VFR_VF12_Pos (12U)
\r
20260 #define VADC_G_VFR_VF12_Msk (0x00000001U << VADC_G_VFR_VF12_Pos)
\r
20262 #define VADC_G_VFR_VF13_Pos (13U)
\r
20263 #define VADC_G_VFR_VF13_Msk (0x00000001U << VADC_G_VFR_VF13_Pos)
\r
20265 #define VADC_G_VFR_VF14_Pos (14U)
\r
20266 #define VADC_G_VFR_VF14_Msk (0x00000001U << VADC_G_VFR_VF14_Pos)
\r
20268 #define VADC_G_VFR_VF15_Pos (15U)
\r
20269 #define VADC_G_VFR_VF15_Msk (0x00000001U << VADC_G_VFR_VF15_Pos)
\r
20271 /* VADC_G_CHCTRy = Group 0, Channel x Ctrl. Reg.*/
\r
20272 #define VADC_G_CHCTR_ICLSEL_Pos (0U)
\r
20273 #define VADC_G_CHCTR_ICLSEL_Msk (0x00000003U << VADC_G_CHCTR_ICLSEL_Pos)
\r
20275 #define VADC_G_CHCTR_BNDSELL_Pos (4U)
\r
20276 #define VADC_G_CHCTR_BNDSELL_Msk (0x00000003U << VADC_G_CHCTR_BNDSELL_Pos)
\r
20278 #define VADC_G_CHCTR_BNDSELU_Pos (6U)
\r
20279 #define VADC_G_CHCTR_BNDSELU_Msk (0x00000003U << VADC_G_CHCTR_BNDSELU_Pos)
\r
20281 #define VADC_G_CHCTR_CHEVMODE_Pos (8U)
\r
20282 #define VADC_G_CHCTR_CHEVMODE_Msk (0x00000003U << VADC_G_CHCTR_CHEVMODE_Pos)
\r
20284 #define VADC_G_CHCTR_SYNC_Pos (10U)
\r
20285 #define VADC_G_CHCTR_SYNC_Msk (0x00000001U << VADC_G_CHCTR_SYNC_Pos)
\r
20287 #define VADC_G_CHCTR_REFSEL_Pos (11U)
\r
20288 #define VADC_G_CHCTR_REFSEL_Msk (0x00000001U << VADC_G_CHCTR_REFSEL_Pos)
\r
20290 #define VADC_G_CHCTR_BNDSELX_Pos (12U)
\r
20291 #define VADC_G_CHCTR_BNDSELX_Msk (0x0000000FU << VADC_G_CHCTR_BNDSELX_Pos)
\r
20293 #define VADC_G_CHCTR_RESREG_Pos (16U)
\r
20294 #define VADC_G_CHCTR_RESREG_Msk (0x0000000FU << VADC_G_CHCTR_RESREG_Pos)
\r
20296 #define VADC_G_CHCTR_RESTBS_Pos (20U)
\r
20297 #define VADC_G_CHCTR_RESTBS_Msk (0x00000001U << VADC_G_CHCTR_RESTBS_Pos)
\r
20299 #define VADC_G_CHCTR_RESPOS_Pos (21U)
\r
20300 #define VADC_G_CHCTR_RESPOS_Msk (0x00000001U << VADC_G_CHCTR_RESPOS_Pos)
\r
20302 #define VADC_G_CHCTR_BWDCH_Pos (28U)
\r
20303 #define VADC_G_CHCTR_BWDCH_Msk (0x00000003U << VADC_G_CHCTR_BWDCH_Pos)
\r
20305 #define VADC_G_CHCTR_BWDEN_Pos (30U)
\r
20306 #define VADC_G_CHCTR_BWDEN_Msk (0x00000001U << VADC_G_CHCTR_BWDEN_Pos)
\r
20308 /* VADC_G_RCRy = Group x Result Control Reg. 0*/
\r
20309 #define VADC_G_RCR_DRCTR_Pos (16U)
\r
20310 #define VADC_G_RCR_DRCTR_Msk (0x0000000FU << VADC_G_RCR_DRCTR_Pos)
\r
20312 #define VADC_G_RCR_DMM_Pos (20U)
\r
20313 #define VADC_G_RCR_DMM_Msk (0x00000003U << VADC_G_RCR_DMM_Pos)
\r
20315 #define VADC_G_RCR_WFR_Pos (24U)
\r
20316 #define VADC_G_RCR_WFR_Msk (0x00000001U << VADC_G_RCR_WFR_Pos)
\r
20318 #define VADC_G_RCR_FEN_Pos (25U)
\r
20319 #define VADC_G_RCR_FEN_Msk (0x00000003U << VADC_G_RCR_FEN_Pos)
\r
20321 #define VADC_G_RCR_SRGEN_Pos (31U)
\r
20322 #define VADC_G_RCR_SRGEN_Msk (0x00000001U << VADC_G_RCR_SRGEN_Pos)
\r
20324 /* VADC_G_RESy = Group x Result Register 0*/
\r
20325 #define VADC_G_RES_RESULT_Pos (0U)
\r
20326 #define VADC_G_RES_RESULT_Msk (0x0000FFFFU << VADC_G_RES_RESULT_Pos)
\r
20328 #define VADC_G_RES_DRC_Pos (16U)
\r
20329 #define VADC_G_RES_DRC_Msk (0x0000000FU << VADC_G_RES_DRC_Pos)
\r
20331 #define VADC_G_RES_CHNR_Pos (20U)
\r
20332 #define VADC_G_RES_CHNR_Msk (0x0000001FU << VADC_G_RES_CHNR_Pos)
\r
20334 #define VADC_G_RES_EMUX_Pos (25U)
\r
20335 #define VADC_G_RES_EMUX_Msk (0x00000007U << VADC_G_RES_EMUX_Pos)
\r
20337 #define VADC_G_RES_CRS_Pos (28U)
\r
20338 #define VADC_G_RES_CRS_Msk (0x00000003U << VADC_G_RES_CRS_Pos)
\r
20340 #define VADC_G_RES_FCR_Pos (30U)
\r
20341 #define VADC_G_RES_FCR_Msk (0x00000001U << VADC_G_RES_FCR_Pos)
\r
20343 #define VADC_G_RES_VF_Pos (31U)
\r
20344 #define VADC_G_RES_VF_Msk (0x00000001U << VADC_G_RES_VF_Pos)
\r
20346 /* VADC_G_RESDy = Group x Result Reg. 0, Debug*/
\r
20347 #define VADC_G_RESD_RESULT_Pos (0U)
\r
20348 #define VADC_G_RESD_RESULT_Msk (0x0000FFFFU << VADC_G_RESD_RESULT_Pos)
\r
20350 #define VADC_G_RESD_DRC_Pos (16U)
\r
20351 #define VADC_G_RESD_DRC_Msk (0x0000000FU << VADC_G_RESD_DRC_Pos)
\r
20353 #define VADC_G_RESD_CHNR_Pos (20U)
\r
20354 #define VADC_G_RESD_CHNR_Msk (0x0000001FU << VADC_G_RESD_CHNR_Pos)
\r
20356 #define VADC_G_RESD_EMUX_Pos (25U)
\r
20357 #define VADC_G_RESD_EMUX_Msk (0x00000007U << VADC_G_RESD_EMUX_Pos)
\r
20359 #define VADC_G_RESD_CRS_Pos (28U)
\r
20360 #define VADC_G_RESD_CRS_Msk (0x00000003U << VADC_G_RESD_CRS_Pos)
\r
20362 #define VADC_G_RESD_FCR_Pos (30U)
\r
20363 #define VADC_G_RESD_FCR_Msk (0x00000001U << VADC_G_RESD_FCR_Pos)
\r
20365 #define VADC_G_RESD_VF_Pos (31U)
\r
20366 #define VADC_G_RESD_VF_Msk (0x00000001U << VADC_G_RESD_VF_Pos)
\r
20368 /* VADC_CLC = Clock Control Register*/
\r
20369 #define VADC_CLC_DISR_Pos (0U)
\r
20370 #define VADC_CLC_DISR_Msk (0x00000001U << VADC_CLC_DISR_Pos)
\r
20372 #define VADC_CLC_DISS_Pos (1U)
\r
20373 #define VADC_CLC_DISS_Msk (0x00000001U << VADC_CLC_DISS_Pos)
\r
20375 #define VADC_CLC_EDIS_Pos (3U)
\r
20376 #define VADC_CLC_EDIS_Msk (0x00000001U << VADC_CLC_EDIS_Pos)
\r
20378 /* VADC_ID = Module Identification Register*/
\r
20379 #define VADC_ID_MOD_REV_Pos (0U)
\r
20380 #define VADC_ID_MOD_REV_Msk (0x000000FFU << VADC_ID_MOD_REV_Pos)
\r
20382 #define VADC_ID_MOD_TYPE_Pos (8U)
\r
20383 #define VADC_ID_MOD_TYPE_Msk (0x000000FFU << VADC_ID_MOD_TYPE_Pos)
\r
20385 #define VADC_ID_MOD_NUMBER_Pos (16U)
\r
20386 #define VADC_ID_MOD_NUMBER_Msk (0x0000FFFFU << VADC_ID_MOD_NUMBER_Pos)
\r
20388 /* VADC_OCS = OCDS Control and Status Register*/
\r
20389 #define VADC_OCS_TGS_Pos (0U)
\r
20390 #define VADC_OCS_TGS_Msk (0x00000003U << VADC_OCS_TGS_Pos)
\r
20392 #define VADC_OCS_TGB_Pos (2U)
\r
20393 #define VADC_OCS_TGB_Msk (0x00000001U << VADC_OCS_TGB_Pos)
\r
20395 #define VADC_OCS_TG_P_Pos (3U)
\r
20396 #define VADC_OCS_TG_P_Msk (0x00000001U << VADC_OCS_TG_P_Pos)
\r
20398 #define VADC_OCS_SUS_Pos (24U)
\r
20399 #define VADC_OCS_SUS_Msk (0x0000000FU << VADC_OCS_SUS_Pos)
\r
20401 #define VADC_OCS_SUS_P_Pos (28U)
\r
20402 #define VADC_OCS_SUS_P_Msk (0x00000001U << VADC_OCS_SUS_P_Pos)
\r
20404 #define VADC_OCS_SUSSTA_Pos (29U)
\r
20405 #define VADC_OCS_SUSSTA_Msk (0x00000001U << VADC_OCS_SUSSTA_Pos)
\r
20407 /* VADC_GLOBCFG = Global Configuration Register*/
\r
20408 #define VADC_GLOBCFG_DIVA_Pos (0U)
\r
20409 #define VADC_GLOBCFG_DIVA_Msk (0x0000001FU << VADC_GLOBCFG_DIVA_Pos)
\r
20411 #define VADC_GLOBCFG_DCMSB_Pos (7U)
\r
20412 #define VADC_GLOBCFG_DCMSB_Msk (0x00000001U << VADC_GLOBCFG_DCMSB_Pos)
\r
20414 #define VADC_GLOBCFG_DIVD_Pos (8U)
\r
20415 #define VADC_GLOBCFG_DIVD_Msk (0x00000003U << VADC_GLOBCFG_DIVD_Pos)
\r
20417 #define VADC_GLOBCFG_DIVWC_Pos (15U)
\r
20418 #define VADC_GLOBCFG_DIVWC_Msk (0x00000001U << VADC_GLOBCFG_DIVWC_Pos)
\r
20420 #define VADC_GLOBCFG_DPCAL0_Pos (16U)
\r
20421 #define VADC_GLOBCFG_DPCAL0_Msk (0x00000001U << VADC_GLOBCFG_DPCAL0_Pos)
\r
20423 #define VADC_GLOBCFG_DPCAL1_Pos (17U)
\r
20424 #define VADC_GLOBCFG_DPCAL1_Msk (0x00000001U << VADC_GLOBCFG_DPCAL1_Pos)
\r
20426 #define VADC_GLOBCFG_DPCAL2_Pos (18U)
\r
20427 #define VADC_GLOBCFG_DPCAL2_Msk (0x00000001U << VADC_GLOBCFG_DPCAL2_Pos)
\r
20429 #define VADC_GLOBCFG_DPCAL3_Pos (19U)
\r
20430 #define VADC_GLOBCFG_DPCAL3_Msk (0x00000001U << VADC_GLOBCFG_DPCAL3_Pos)
\r
20432 #define VADC_GLOBCFG_SUCAL_Pos (31U)
\r
20433 #define VADC_GLOBCFG_SUCAL_Msk (0x00000001U << VADC_GLOBCFG_SUCAL_Pos)
\r
20435 /* VADC_GLOBICLASSy = Input Class Register 0, Global*/
\r
20436 #define VADC_GLOBICLASS_STCS_Pos (0U)
\r
20437 #define VADC_GLOBICLASS_STCS_Msk (0x0000001FU << VADC_GLOBICLASS_STCS_Pos)
\r
20439 #define VADC_GLOBICLASS_CMS_Pos (8U)
\r
20440 #define VADC_GLOBICLASS_CMS_Msk (0x00000007U << VADC_GLOBICLASS_CMS_Pos)
\r
20442 #define VADC_GLOBICLASS_STCE_Pos (16U)
\r
20443 #define VADC_GLOBICLASS_STCE_Msk (0x0000001FU << VADC_GLOBICLASS_STCE_Pos)
\r
20445 #define VADC_GLOBICLASS_CME_Pos (24U)
\r
20446 #define VADC_GLOBICLASS_CME_Msk (0x00000007U << VADC_GLOBICLASS_CME_Pos)
\r
20448 /* VADC_GLOBBOUND = Global Boundary Select Register*/
\r
20449 #define VADC_GLOBBOUND_BOUNDARY0_Pos (0U)
\r
20450 #define VADC_GLOBBOUND_BOUNDARY0_Msk (0x00000FFFU << VADC_GLOBBOUND_BOUNDARY0_Pos)
\r
20452 #define VADC_GLOBBOUND_BOUNDARY1_Pos (16U)
\r
20453 #define VADC_GLOBBOUND_BOUNDARY1_Msk (0x00000FFFU << VADC_GLOBBOUND_BOUNDARY1_Pos)
\r
20455 /* VADC_GLOBEFLAG = Global Event Flag Register*/
\r
20456 #define VADC_GLOBEFLAG_SEVGLB_Pos (0U)
\r
20457 #define VADC_GLOBEFLAG_SEVGLB_Msk (0x00000001U << VADC_GLOBEFLAG_SEVGLB_Pos)
\r
20459 #define VADC_GLOBEFLAG_REVGLB_Pos (8U)
\r
20460 #define VADC_GLOBEFLAG_REVGLB_Msk (0x00000001U << VADC_GLOBEFLAG_REVGLB_Pos)
\r
20462 #define VADC_GLOBEFLAG_SEVGLBCLR_Pos (16U)
\r
20463 #define VADC_GLOBEFLAG_SEVGLBCLR_Msk (0x00000001U << VADC_GLOBEFLAG_SEVGLBCLR_Pos)
\r
20465 #define VADC_GLOBEFLAG_REVGLBCLR_Pos (24U)
\r
20466 #define VADC_GLOBEFLAG_REVGLBCLR_Msk (0x00000001U << VADC_GLOBEFLAG_REVGLBCLR_Pos)
\r
20468 /* VADC_GLOBEVNP = Global Event Node Pointer Register*/
\r
20469 #define VADC_GLOBEVNP_SEV0NP_Pos (0U)
\r
20470 #define VADC_GLOBEVNP_SEV0NP_Msk (0x0000000FU << VADC_GLOBEVNP_SEV0NP_Pos)
\r
20472 #define VADC_GLOBEVNP_REV0NP_Pos (16U)
\r
20473 #define VADC_GLOBEVNP_REV0NP_Msk (0x0000000FU << VADC_GLOBEVNP_REV0NP_Pos)
\r
20475 /* VADC_GLOBTF = Global Test Functions Register*/
\r
20476 #define VADC_GLOBTF_CDCH_Pos (0U)
\r
20477 #define VADC_GLOBTF_CDCH_Msk (0x0000000FU << VADC_GLOBTF_CDCH_Pos)
\r
20479 #define VADC_GLOBTF_CDGR_Pos (4U)
\r
20480 #define VADC_GLOBTF_CDGR_Msk (0x0000000FU << VADC_GLOBTF_CDGR_Pos)
\r
20482 #define VADC_GLOBTF_CDEN_Pos (8U)
\r
20483 #define VADC_GLOBTF_CDEN_Msk (0x00000001U << VADC_GLOBTF_CDEN_Pos)
\r
20485 #define VADC_GLOBTF_CDSEL_Pos (9U)
\r
20486 #define VADC_GLOBTF_CDSEL_Msk (0x00000003U << VADC_GLOBTF_CDSEL_Pos)
\r
20488 #define VADC_GLOBTF_CDWC_Pos (15U)
\r
20489 #define VADC_GLOBTF_CDWC_Msk (0x00000001U << VADC_GLOBTF_CDWC_Pos)
\r
20491 #define VADC_GLOBTF_PDD_Pos (16U)
\r
20492 #define VADC_GLOBTF_PDD_Msk (0x00000001U << VADC_GLOBTF_PDD_Pos)
\r
20494 #define VADC_GLOBTF_MDPD_Pos (17U)
\r
20495 #define VADC_GLOBTF_MDPD_Msk (0x00000001U << VADC_GLOBTF_MDPD_Pos)
\r
20497 #define VADC_GLOBTF_MDPU_Pos (18U)
\r
20498 #define VADC_GLOBTF_MDPU_Msk (0x00000001U << VADC_GLOBTF_MDPU_Pos)
\r
20500 #define VADC_GLOBTF_MDWC_Pos (23U)
\r
20501 #define VADC_GLOBTF_MDWC_Msk (0x00000001U << VADC_GLOBTF_MDWC_Pos)
\r
20503 #define VADC_GLOBTF_TRSW_Pos (24U)
\r
20504 #define VADC_GLOBTF_TRSW_Msk (0x00000001U << VADC_GLOBTF_TRSW_Pos)
\r
20506 #define VADC_GLOBTF_TREV_Pos (25U)
\r
20507 #define VADC_GLOBTF_TREV_Msk (0x00000001U << VADC_GLOBTF_TREV_Pos)
\r
20509 #define VADC_GLOBTF_SRGMODE_Pos (29U)
\r
20510 #define VADC_GLOBTF_SRGMODE_Msk (0x00000003U << VADC_GLOBTF_SRGMODE_Pos)
\r
20512 #define VADC_GLOBTF_SRGWC_Pos (31U)
\r
20513 #define VADC_GLOBTF_SRGWC_Msk (0x00000001U << VADC_GLOBTF_SRGWC_Pos)
\r
20515 /* VADC_BRSSELy = Background Request Source Channel Select Register, Group 0*/
\r
20516 #define VADC_BRSSEL_CHSELG_Pos (0U)
\r
20517 #define VADC_BRSSEL_CHSELG_Msk (0xFFFFFFFFU << VADC_BRSSEL_CHSELG_Pos)
\r
20519 /* VADC_BRSPNDy = Background Request Source Pending Register, Group 0*/
\r
20520 #define VADC_BRSPND_CHPNDG_Pos (0U)
\r
20521 #define VADC_BRSPND_CHPNDG_Msk (0xFFFFFFFFU << VADC_BRSPND_CHPNDG_Pos)
\r
20523 /* VADC_BRSCTRL = Background Request Source Control Register*/
\r
20524 #define VADC_BRSCTRL_SRCRESREG_Pos (0U)
\r
20525 #define VADC_BRSCTRL_SRCRESREG_Msk (0x0000000FU << VADC_BRSCTRL_SRCRESREG_Pos)
\r
20527 #define VADC_BRSCTRL_XTSEL_Pos (8U)
\r
20528 #define VADC_BRSCTRL_XTSEL_Msk (0x0000000FU << VADC_BRSCTRL_XTSEL_Pos)
\r
20530 #define VADC_BRSCTRL_XTLVL_Pos (12U)
\r
20531 #define VADC_BRSCTRL_XTLVL_Msk (0x00000001U << VADC_BRSCTRL_XTLVL_Pos)
\r
20533 #define VADC_BRSCTRL_XTMODE_Pos (13U)
\r
20534 #define VADC_BRSCTRL_XTMODE_Msk (0x00000003U << VADC_BRSCTRL_XTMODE_Pos)
\r
20536 #define VADC_BRSCTRL_XTWC_Pos (15U)
\r
20537 #define VADC_BRSCTRL_XTWC_Msk (0x00000001U << VADC_BRSCTRL_XTWC_Pos)
\r
20539 #define VADC_BRSCTRL_GTSEL_Pos (16U)
\r
20540 #define VADC_BRSCTRL_GTSEL_Msk (0x0000000FU << VADC_BRSCTRL_GTSEL_Pos)
\r
20542 #define VADC_BRSCTRL_GTLVL_Pos (20U)
\r
20543 #define VADC_BRSCTRL_GTLVL_Msk (0x00000001U << VADC_BRSCTRL_GTLVL_Pos)
\r
20545 #define VADC_BRSCTRL_GTWC_Pos (23U)
\r
20546 #define VADC_BRSCTRL_GTWC_Msk (0x00000001U << VADC_BRSCTRL_GTWC_Pos)
\r
20548 /* VADC_BRSMR = Background Request Source Mode Register*/
\r
20549 #define VADC_BRSMR_ENGT_Pos (0U)
\r
20550 #define VADC_BRSMR_ENGT_Msk (0x00000003U << VADC_BRSMR_ENGT_Pos)
\r
20552 #define VADC_BRSMR_ENTR_Pos (2U)
\r
20553 #define VADC_BRSMR_ENTR_Msk (0x00000001U << VADC_BRSMR_ENTR_Pos)
\r
20555 #define VADC_BRSMR_ENSI_Pos (3U)
\r
20556 #define VADC_BRSMR_ENSI_Msk (0x00000001U << VADC_BRSMR_ENSI_Pos)
\r
20558 #define VADC_BRSMR_SCAN_Pos (4U)
\r
20559 #define VADC_BRSMR_SCAN_Msk (0x00000001U << VADC_BRSMR_SCAN_Pos)
\r
20561 #define VADC_BRSMR_LDM_Pos (5U)
\r
20562 #define VADC_BRSMR_LDM_Msk (0x00000001U << VADC_BRSMR_LDM_Pos)
\r
20564 #define VADC_BRSMR_REQGT_Pos (7U)
\r
20565 #define VADC_BRSMR_REQGT_Msk (0x00000001U << VADC_BRSMR_REQGT_Pos)
\r
20567 #define VADC_BRSMR_CLRPND_Pos (8U)
\r
20568 #define VADC_BRSMR_CLRPND_Msk (0x00000001U << VADC_BRSMR_CLRPND_Pos)
\r
20570 #define VADC_BRSMR_LDEV_Pos (9U)
\r
20571 #define VADC_BRSMR_LDEV_Msk (0x00000001U << VADC_BRSMR_LDEV_Pos)
\r
20573 #define VADC_BRSMR_RPTDIS_Pos (16U)
\r
20574 #define VADC_BRSMR_RPTDIS_Msk (0x00000001U << VADC_BRSMR_RPTDIS_Pos)
\r
20576 /* VADC_GLOBRCR = Global Result Control Register*/
\r
20577 #define VADC_GLOBRCR_DRCTR_Pos (16U)
\r
20578 #define VADC_GLOBRCR_DRCTR_Msk (0x0000000FU << VADC_GLOBRCR_DRCTR_Pos)
\r
20580 #define VADC_GLOBRCR_WFR_Pos (24U)
\r
20581 #define VADC_GLOBRCR_WFR_Msk (0x00000001U << VADC_GLOBRCR_WFR_Pos)
\r
20583 #define VADC_GLOBRCR_SRGEN_Pos (31U)
\r
20584 #define VADC_GLOBRCR_SRGEN_Msk (0x00000001U << VADC_GLOBRCR_SRGEN_Pos)
\r
20586 /* VADC_GLOBRES = Global Result Register*/
\r
20587 #define VADC_GLOBRES_RESULT_Pos (0U)
\r
20588 #define VADC_GLOBRES_RESULT_Msk (0x0000FFFFU << VADC_GLOBRES_RESULT_Pos)
\r
20590 #define VADC_GLOBRES_GNR_Pos (16U)
\r
20591 #define VADC_GLOBRES_GNR_Msk (0x0000000FU << VADC_GLOBRES_GNR_Pos)
\r
20593 #define VADC_GLOBRES_CHNR_Pos (20U)
\r
20594 #define VADC_GLOBRES_CHNR_Msk (0x0000001FU << VADC_GLOBRES_CHNR_Pos)
\r
20596 #define VADC_GLOBRES_EMUX_Pos (25U)
\r
20597 #define VADC_GLOBRES_EMUX_Msk (0x00000007U << VADC_GLOBRES_EMUX_Pos)
\r
20599 #define VADC_GLOBRES_CRS_Pos (28U)
\r
20600 #define VADC_GLOBRES_CRS_Msk (0x00000003U << VADC_GLOBRES_CRS_Pos)
\r
20602 #define VADC_GLOBRES_FCR_Pos (30U)
\r
20603 #define VADC_GLOBRES_FCR_Msk (0x00000001U << VADC_GLOBRES_FCR_Pos)
\r
20605 #define VADC_GLOBRES_VF_Pos (31U)
\r
20606 #define VADC_GLOBRES_VF_Msk (0x00000001U << VADC_GLOBRES_VF_Pos)
\r
20608 /* VADC_GLOBRESD = Global Result Register, Debug*/
\r
20609 #define VADC_GLOBRESD_RESULT_Pos (0U)
\r
20610 #define VADC_GLOBRESD_RESULT_Msk (0x0000FFFFU << VADC_GLOBRESD_RESULT_Pos)
\r
20612 #define VADC_GLOBRESD_GNR_Pos (16U)
\r
20613 #define VADC_GLOBRESD_GNR_Msk (0x0000000FU << VADC_GLOBRESD_GNR_Pos)
\r
20615 #define VADC_GLOBRESD_CHNR_Pos (20U)
\r
20616 #define VADC_GLOBRESD_CHNR_Msk (0x0000001FU << VADC_GLOBRESD_CHNR_Pos)
\r
20618 #define VADC_GLOBRESD_EMUX_Pos (25U)
\r
20619 #define VADC_GLOBRESD_EMUX_Msk (0x00000007U << VADC_GLOBRESD_EMUX_Pos)
\r
20621 #define VADC_GLOBRESD_CRS_Pos (28U)
\r
20622 #define VADC_GLOBRESD_CRS_Msk (0x00000003U << VADC_GLOBRESD_CRS_Pos)
\r
20624 #define VADC_GLOBRESD_FCR_Pos (30U)
\r
20625 #define VADC_GLOBRESD_FCR_Msk (0x00000001U << VADC_GLOBRESD_FCR_Pos)
\r
20627 #define VADC_GLOBRESD_VF_Pos (31U)
\r
20628 #define VADC_GLOBRESD_VF_Msk (0x00000001U << VADC_GLOBRESD_VF_Pos)
\r
20630 /* VADC_EMUXSEL = External Multiplexer Select Register*/
\r
20631 #define VADC_EMUXSEL_EMUXGRP0_Pos (0U)
\r
20632 #define VADC_EMUXSEL_EMUXGRP0_Msk (0x0000000FU << VADC_EMUXSEL_EMUXGRP0_Pos)
\r
20634 #define VADC_EMUXSEL_EMUXGRP1_Pos (4U)
\r
20635 #define VADC_EMUXSEL_EMUXGRP1_Msk (0x0000000FU << VADC_EMUXSEL_EMUXGRP1_Pos)
\r
20639 /*** WDT Bit Fileds *******************/
\r
20640 /***************************************************************************/
\r
20643 /* WDT_ID = WDT ID Register*/
\r
20644 #define WDT_ID_ID_Pos (0U)
\r
20645 #define WDT_ID_ID_Msk (0xFFFFFFFFU << WDT_ID_ID_Pos)
\r
20647 /* WDT_CTR = WDT Control Register*/
\r
20648 #define WDT_CTR_ENB_Pos (0U)
\r
20649 #define WDT_CTR_ENB_Msk (0x00000001U << WDT_CTR_ENB_Pos)
\r
20651 #define WDT_CTR_PRE_Pos (1U)
\r
20652 #define WDT_CTR_PRE_Msk (0x00000001U << WDT_CTR_PRE_Pos)
\r
20654 #define WDT_CTR_DSP_Pos (4U)
\r
20655 #define WDT_CTR_DSP_Msk (0x00000001U << WDT_CTR_DSP_Pos)
\r
20657 #define WDT_CTR_SPW_Pos (8U)
\r
20658 #define WDT_CTR_SPW_Msk (0x000000FFU << WDT_CTR_SPW_Pos)
\r
20660 /* WDT_SRV = WDT Service Register*/
\r
20661 #define WDT_SRV_SRV_Pos (0U)
\r
20662 #define WDT_SRV_SRV_Msk (0xFFFFFFFFU << WDT_SRV_SRV_Pos)
\r
20664 /* WDT_TIM = WDT Timer Register*/
\r
20665 #define WDT_TIM_TIM_Pos (0U)
\r
20666 #define WDT_TIM_TIM_Msk (0xFFFFFFFFU << WDT_TIM_TIM_Pos)
\r
20668 /* WDT_WLB = WDT Window Lower Bound Register*/
\r
20669 #define WDT_WLB_WLB_Pos (0U)
\r
20670 #define WDT_WLB_WLB_Msk (0xFFFFFFFFU << WDT_WLB_WLB_Pos)
\r
20672 /* WDT_WUB = WDT Window Upper Bound Register*/
\r
20673 #define WDT_WUB_WUB_Pos (0U)
\r
20674 #define WDT_WUB_WUB_Msk (0xFFFFFFFFU << WDT_WUB_WUB_Pos)
\r
20676 /* WDT_WDTSTS = WDT Status Register*/
\r
20677 #define WDT_WDTSTS_ALMS_Pos (0U)
\r
20678 #define WDT_WDTSTS_ALMS_Msk (0x00000001U << WDT_WDTSTS_ALMS_Pos)
\r
20680 /* WDT_WDTCLR = WDT Clear Register*/
\r
20681 #define WDT_WDTCLR_ALMC_Pos (0U)
\r
20682 #define WDT_WDTCLR_ALMC_Msk (0x00000001U << WDT_WDTCLR_ALMC_Pos)
\r
20684 /********************************************
\r
20685 ** End of section using anonymous unions **
\r
20686 *********************************************/
\r
20688 #if defined(__CC_ARM)
\r
20690 #elif defined(__ICCARM__)
\r
20691 /* leave anonymous unions enabled */
\r
20692 #elif defined(__GNUC__)
\r
20693 /* anonymous unions are enabled by default */
\r
20694 #elif defined(__TMS470__)
\r
20695 /* anonymous unions are enabled by default */
\r
20696 #elif defined(__TASKING__)
\r
20697 #pragma warning restore
\r
20699 #warning Not supported compiler type
\r
20702 #ifdef __cplusplus
\r
20706 #endif // ifndef __XMC4500_H__
\r
projects / freertos / blob