2 * FreeRTOS Kernel V10.1.0
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3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 * This file initialises the two timers available in the Timer32 peripheral.
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31 * Channels 0 and 1 provide the interrupts that are used with the IntQ
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32 * standard demo tasks, which test interrupt nesting and using queues from
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36 /* Scheduler includes. */
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37 #include "FreeRTOS.h"
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39 /* Demo includes. */
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40 #include "IntQueueTimer.h"
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41 #include "IntQueue.h"
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43 /* The frequencies at which the two timers expire are slightly offset to ensure
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44 they don't remain synchronised. */
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45 #define tmrTIMER_0_FREQUENCY ( 2000UL )
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46 #define tmrTIMER_1_FREQUENCY ( 2003UL )
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48 /* The interrupts use the FreeRTOS API so must be at or below the max syscall
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49 interrupt priority. Counter-intuitively, the higher the numeric number the
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50 lower the logical priority. http://www.freertos.org/RTOS-Cortex-M3-M4.html */
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51 #define tmrLOWER_PRIORITY ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
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52 #define tmrHIGHER_PRIORITY ( configMAX_SYSCALL_INTERRUPT_PRIORITY + 1 )
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53 /*-----------------------------------------------------------*/
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55 /* Handlers for the two timer peripherals - two channels are used in the TC0
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57 void vT32_0_Handler( void );
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58 void vT32_1_Handler( void );
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60 /*-----------------------------------------------------------*/
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62 void vInitialiseTimerForIntQueueTest( void )
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64 /* Configure the timer channels. */
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65 MAP_Timer32_initModule( (uint32_t)TIMER32_0_BASE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
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66 MAP_Timer32_setCount( (uint32_t)TIMER32_0_BASE, CS_getMCLK() / tmrTIMER_0_FREQUENCY );
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67 MAP_Timer32_enableInterrupt( (uint32_t)TIMER32_0_BASE );
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68 MAP_Timer32_startTimer( (uint32_t)TIMER32_0_BASE, false );
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69 MAP_Interrupt_setPriority( INT_T32_INT1, tmrLOWER_PRIORITY );
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70 MAP_Interrupt_enableInterrupt( INT_T32_INT1 );
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72 MAP_Timer32_initModule( (uint32_t)TIMER32_1_BASE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
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73 MAP_Timer32_setCount( (uint32_t)TIMER32_1_BASE, CS_getMCLK() / tmrTIMER_1_FREQUENCY );
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74 MAP_Timer32_enableInterrupt( (uint32_t)TIMER32_1_BASE );
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75 MAP_Timer32_startTimer( (uint32_t)TIMER32_1_BASE, false );
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76 MAP_Interrupt_setPriority( INT_T32_INT2, tmrHIGHER_PRIORITY );
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77 MAP_Interrupt_enableInterrupt( INT_T32_INT2 );
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79 /*-----------------------------------------------------------*/
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81 void vT32_0_Handler( void )
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83 MAP_Timer32_clearInterruptFlag( (uint32_t)TIMER32_0_BASE );
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84 portYIELD_FROM_ISR( xFirstTimerHandler() );
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86 /*-----------------------------------------------------------*/
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88 void vT32_1_Handler( void )
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90 MAP_Timer32_clearInterruptFlag( (uint32_t)TIMER32_1_BASE );
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91 portYIELD_FROM_ISR( xSecondTimerHandler() );
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