2 * FreeRTOS Kernel V10.2.1
\r
3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software.
\r
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
22 * http://www.FreeRTOS.org
\r
23 * http://aws.amazon.com/freertos
\r
25 * 1 tab == 4 spaces!
\r
28 /* FreeRTOS includes. */
\r
29 #include "FreeRTOS.h"
\r
31 /* Utility functions to implement run time stats on Cortex-M CPUs. The collected
\r
32 run time data can be viewed through the CLI interface. See the following URL for
\r
33 more information on run time stats:
\r
34 http://www.freertos.org/rtos-run-time-stats.html */
\r
36 /* Addresses of registers in the Cortex-M debug hardware. */
\r
37 #define rtsDWT_CYCCNT ( *( ( unsigned long * ) 0xE0001004 ) )
\r
38 #define rtsDWT_CONTROL ( *( ( unsigned long * ) 0xE0001000 ) )
\r
39 #define rtsSCB_DEMCR ( *( ( unsigned long * ) 0xE000EDFC ) )
\r
40 #define rtsTRCENA_BIT ( 0x01000000UL )
\r
41 #define rtsCOUNTER_ENABLE_BIT ( 0x01UL )
\r
43 /* Simple shift divide for scaling to avoid an overflow occurring too soon. */
\r
44 #define runtimeSHIFT_13 13
\r
45 #define runtimeOVERFLOW_BIT_13 ( 1UL << ( 32UL - runtimeSHIFT_13 ) )
\r
46 static const uint32_t ulPrescaleBits = runtimeSHIFT_13;
\r
47 static const uint32_t ulOverflowBit = runtimeOVERFLOW_BIT_13;
\r
49 /*-----------------------------------------------------------*/
\r
51 void vConfigureTimerForRunTimeStats( void )
\r
53 /* Enable TRCENA. */
\r
54 rtsSCB_DEMCR = rtsSCB_DEMCR | rtsTRCENA_BIT;
\r
56 /* Reset counter. */
\r
59 /* Enable counter. */
\r
60 rtsDWT_CONTROL = rtsDWT_CONTROL | rtsCOUNTER_ENABLE_BIT;
\r
62 /*-----------------------------------------------------------*/
\r
64 uint32_t ulGetRunTimeCounterValue( void )
\r
66 static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0;
\r
67 unsigned long ulValueNow;
\r
69 ulValueNow = rtsDWT_CYCCNT;
\r
71 /* Has the value overflowed since it was last read. */
\r
72 if( ulValueNow < ulLastCounterValue )
\r
74 ulOverflows += ulOverflowBit;
\r
76 ulLastCounterValue = ulValueNow;
\r
78 /* There is no prescale on the counter, so simulate in software. */
\r
79 ulValueNow = ( ulValueNow >> ulPrescaleBits ) + ulOverflows;
\r
83 /*-----------------------------------------------------------*/
\r