2 * -------------------------------------------
3 * MSP432 DriverLib - v01_04_00_18
4 * -------------------------------------------
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2015, Texas Instruments Incorporated
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <interrupt.h>
43 void DMA_enableModule(void)
46 // Set the master enable bit in the config register.
48 DMA->rCFG.r = DMA_CFG_;
51 void DMA_disableModule(void)
54 // Clear the master enable bit in the config register.
59 uint32_t DMA_getErrorStatus(void)
62 // Return the DMA error status.
64 return DMA->rERRCLR.r;
67 void DMA_clearErrorStatus(void)
70 // Clear the DMA error interrupt.
75 void DMA_enableChannel(uint32_t channelNum)
78 // Check the arguments.
80 ASSERT((channelNum & 0xffff) < 8);
83 // Set the bit for this channel in the enable set register.
85 DMA->rENASET = 1 << (channelNum & 0x0F);
88 void DMA_disableChannel(uint32_t channelNum)
91 // Check the arguments.
93 ASSERT((channelNum & 0xffff) < 8);
96 // Set the bit for this channel in the enable clear register.
98 DMA->rENACLR = 1 << (channelNum & 0x0F);
101 bool DMA_isChannelEnabled(uint32_t channelNum)
104 // Check the arguments.
106 ASSERT((channelNum & 0xffff) < 8);
109 // AND the specified channel bit with the enable register and return the
112 return ((DMA->rENASET & (1 << (channelNum & 0x0F))) ? true : false);
115 void DMA_setControlBase(void *controlTable)
118 // Check the arguments.
120 ASSERT(((uint32_t) controlTable & ~0x3FF) == (uint32_t) controlTable);
121 ASSERT((uint32_t) controlTable >= 0x20000000);
124 // Program the base address into the register.
126 DMA->rCTLBASE.r = (uint32_t) controlTable;
129 void* DMA_getControlBase(void)
132 // Read the current value of the control base register and return it to
135 return ((void *) DMA->rCTLBASE.r);
138 void* DMA_getControlAlternateBase(void)
141 // Read the current value of the control base register and return it to
144 return ((void *) DMA->rATLBASE);
147 void DMA_requestChannel(uint32_t channelNum)
150 // Check the arguments.
152 ASSERT((channelNum & 0xffff) < 8);
155 // Set the bit for this channel in the software DMA request register.
157 DMA->rSWREQ = 1 << (channelNum & 0x0F);
160 void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
163 // Check the arguments.
165 ASSERT((channelNum & 0xffff) < 8);
168 & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT
169 | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK))
173 // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
174 // passed as the channelNum parameter, extract just the channel number
175 // from this parameter.
180 // Set the useburst bit for this channel if set in config.
182 if (attr & UDMA_ATTR_USEBURST)
184 DMA->rUSEBURSTSET = 1 << channelNum;
188 // Set the alternate control select bit for this channel,
191 if (attr & UDMA_ATTR_ALTSELECT)
193 DMA->rALTSET = 1 << channelNum;
197 // Set the high priority bit for this channel, if set in config.
199 if (attr & UDMA_ATTR_HIGH_PRIORITY)
201 DMA->rPRIOSET = 1 << channelNum;
205 // Set the request mask bit for this channel, if set in config.
207 if (attr & UDMA_ATTR_REQMASK)
209 DMA->rREQMASKSET = 1 << channelNum;
213 void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
216 // Check the arguments.
218 ASSERT((channelNum & 0xffff) < 8);
221 & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT
222 | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK))
226 // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
227 // passed as the channelNum parameter, extract just the channel number
228 // from this parameter.
233 // Clear the useburst bit for this channel if set in config.
235 if (attr & UDMA_ATTR_USEBURST)
237 DMA->rUSEBURSTCLR = 1 << channelNum;
241 // Clear the alternate control select bit for this channel, if set in
244 if (attr & UDMA_ATTR_ALTSELECT)
246 DMA->rALTCLR = 1 << channelNum;
250 // Clear the high priority bit for this channel, if set in config.
252 if (attr & UDMA_ATTR_HIGH_PRIORITY)
254 DMA->rPRIOCLR = 1 << channelNum;
258 // Clear the request mask bit for this channel, if set in config.
260 if (attr & UDMA_ATTR_REQMASK)
262 DMA->rREQMASKCLR = 1 << channelNum;
266 uint32_t DMA_getChannelAttribute(uint32_t channelNum)
271 // Check the arguments.
273 ASSERT((channelNum & 0xffff) < 8);
276 // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
277 // passed as the channelNum parameter, extract just the channel number
278 // from this parameter.
283 // Check to see if useburst bit is set for this channel.
285 if (DMA->rUSEBURSTSET & (1 << channelNum))
287 attr |= UDMA_ATTR_USEBURST;
291 // Check to see if the alternate control bit is set for this channel.
293 if (DMA->rALTSET & (1 << channelNum))
295 attr |= UDMA_ATTR_ALTSELECT;
299 // Check to see if the high priority bit is set for this channel.
301 if (DMA->rPRIOSET & (1 << channelNum))
303 attr |= UDMA_ATTR_HIGH_PRIORITY;
307 // Check to see if the request mask bit is set for this channel.
309 if (DMA->rREQMASKSET & (1 << channelNum))
311 attr |= UDMA_ATTR_REQMASK;
315 // Return the configuration flags.
320 void DMA_setChannelControl(uint32_t channelStructIndex, uint32_t control)
322 DMA_ControlTable *pCtl;
325 // Check the arguments.
327 ASSERT((channelStructIndex & 0xffff) < 64);
328 ASSERT(DMA->rCTLBASE != 0);
331 // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
332 // passed as the channelStructIndex parameter, extract just the channel
333 // index from this parameter.
335 channelStructIndex &= 0x3f;
338 // Get the base address of the control table.
340 pCtl = (DMA_ControlTable *) DMA->rCTLBASE.r;
343 // Get the current control word value and mask off the fields to be
344 // changed, then OR in the new settings.
346 pCtl[channelStructIndex].control = ((pCtl[channelStructIndex].control
347 & ~(UDMA_CHCTL_DSTINC_M | UDMA_CHCTL_DSTSIZE_M | UDMA_CHCTL_SRCINC_M
348 | UDMA_CHCTL_SRCSIZE_M | UDMA_CHCTL_ARBSIZE_M
349 | UDMA_CHCTL_NXTUSEBURST)) | control);
352 void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode,
353 void *srcAddr, void *dstAddr, uint32_t transferSize)
355 DMA_ControlTable *controlTable;
358 uint32_t bufferBytes;
361 // Check the arguments.
363 ASSERT((channelStructIndex & 0xffff) < 64);
364 ASSERT(DMA->rCTLBASE != 0);
365 ASSERT(mode <= UDMA_MODE_PER_SCATTER_GATHER);
366 ASSERT((transferSize != 0) && (transferSize <= 1024));
369 // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
370 // passed as the channelStructIndex parameter, extract just the channel
371 // index from this parameter.
373 channelStructIndex &= 0x3f;
376 // Get the base address of the control table.
378 controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
381 // Get the current control word value and mask off the mode and size
384 control = (controlTable[channelStructIndex].control
385 & ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
388 // Adjust the mode if the alt control structure is selected.
390 if (channelStructIndex & UDMA_ALT_SELECT)
392 if ((mode == UDMA_MODE_MEM_SCATTER_GATHER)
393 || (mode == UDMA_MODE_PER_SCATTER_GATHER))
395 mode |= UDMA_MODE_ALT_SELECT;
400 // Set the transfer size and mode in the control word (but don't write the
401 // control word yet as it could kick off a transfer).
403 control |= mode | ((transferSize - 1) << 4);
406 // Get the address increment value for the source, from the control word.
408 increment = (control & UDMA_CHCTL_SRCINC_M);
411 // Compute the ending source address of the transfer. If the source
412 // increment is set to none, then the ending address is the same as the
415 if (increment != UDMA_SRC_INC_NONE)
417 increment = increment >> 26;
418 bufferBytes = transferSize << increment;
419 srcAddr = (void *) ((uint32_t) srcAddr + bufferBytes - 1);
423 // Load the source ending address into the control block.
425 controlTable[channelStructIndex].srcEndAddr = srcAddr;
428 // Get the address increment value for the destination, from the control
431 increment = control & UDMA_CHCTL_DSTINC_M;
434 // Compute the ending destination address of the transfer. If the
435 // destination increment is set to none, then the ending address is the
436 // same as the beginning.
438 if (increment != UDMA_DST_INC_NONE)
441 // There is a special case if this is setting up a scatter-gather
442 // transfer. The destination pointer must point to the end of
443 // the alternate structure for this channel instead of calculating
444 // the end of the buffer in the normal way.
446 if ((mode == UDMA_MODE_MEM_SCATTER_GATHER)
447 || (mode == UDMA_MODE_PER_SCATTER_GATHER))
449 dstAddr = (void *) &controlTable[channelStructIndex
450 | UDMA_ALT_SELECT].spare;
453 // Not a scatter-gather transfer, calculate end pointer normally.
457 increment = increment >> 30;
458 bufferBytes = transferSize << increment;
459 dstAddr = (void *) ((uint32_t) dstAddr + bufferBytes - 1);
464 // Load the destination ending address into the control block.
466 controlTable[channelStructIndex].dstEndAddr = dstAddr;
469 // Write the new control word value.
471 controlTable[channelStructIndex].control = control;
474 void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount,
475 void *taskList, uint32_t isPeriphSG)
477 DMA_ControlTable *controlTable;
478 DMA_ControlTable *pTaskTable;
481 // Check the parameters
483 ASSERT((channelNum & 0xffff) < 8);
484 ASSERT(DMA->rCTLBASE != 0);
485 ASSERT(taskList != 0);
486 ASSERT(taskCount <= 1024);
487 ASSERT(taskCount != 0);
490 // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
491 // passed as the channelNum parameter, extract just the channel number
492 // from this parameter.
497 // Get the base address of the control table.
499 controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
502 // Get a handy pointer to the task list
504 pTaskTable = (DMA_ControlTable *) taskList;
507 // Compute the ending address for the source pointer. This address is the
508 // last element of the last task in the task table
510 controlTable[channelNum].srcEndAddr = &pTaskTable[taskCount - 1].spare;
513 // Compute the ending address for the destination pointer. This address
514 // is the end of the alternate structure for this channel.
516 controlTable[channelNum].dstEndAddr = &controlTable[channelNum
517 | UDMA_ALT_SELECT].spare;
520 // Compute the control word. Most configurable items are fixed for
521 // scatter-gather. Item and increment sizes are all 32-bit and arb
522 // size must be 4. The count is the number of items in the task list
523 // times 4 (4 words per task).
525 controlTable[channelNum].control = (UDMA_CHCTL_DSTINC_32
526 | UDMA_CHCTL_DSTSIZE_32 | UDMA_CHCTL_SRCINC_32
527 | UDMA_CHCTL_SRCSIZE_32 | UDMA_CHCTL_ARBSIZE_4
528 | (((taskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S)
530 UDMA_CHCTL_XFERMODE_PER_SG :
531 UDMA_CHCTL_XFERMODE_MEM_SG));
534 // Scatter-gather operations can leave the alt bit set. So if doing
535 // back to back scatter-gather transfers, the second attempt may not
536 // work correctly because the alt bit is set. Therefore, clear the
537 // alt bit here to ensure that it is always cleared before a new SG
538 // transfer is started.
540 DMA->rALTCLR = 1 << channelNum;
543 uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
545 DMA_ControlTable *controlTable;
549 // Check the arguments.
551 ASSERT((channelStructIndex & 0xffff) < 16);
552 ASSERT(DMA->rCTLBASE != 0);
555 // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
556 // passed as the channelStructIndex parameter, extract just the channel
557 // index from this parameter.
559 channelStructIndex &= 0x3f;
562 // Get the base address of the control table.
564 controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
567 // Get the current control word value and mask off all but the size field
568 // and the mode field.
570 control = (controlTable[channelStructIndex].control
571 & (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
574 // If the size field and mode field are 0 then the transfer is finished
575 // and there are no more items to transfer
583 // Otherwise, if either the size field or more field is non-zero, then
584 // not all the items have been transferred.
589 // Shift the size field and add one, then return to user.
591 return ((control >> 4) + 1);
595 uint32_t DMA_getChannelMode(uint32_t channelStructIndex)
597 DMA_ControlTable *controlTable;
601 // Check the arguments.
603 ASSERT((channelStructIndex & 0xffff) < 64);
604 ASSERT(DMA->rCTLBASE != 0);
607 // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
608 // passed as the channelStructIndex parameter, extract just the channel
609 // index from this parameter.
611 channelStructIndex &= 0x3f;
614 // Get the base address of the control table.
616 controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
619 // Get the current control word value and mask off all but the mode field.
622 (controlTable[channelStructIndex].control & UDMA_CHCTL_XFERMODE_M);
625 // Check if scatter/gather mode, and if so, mask off the alt bit.
627 if (((control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER)
628 || ((control & ~UDMA_MODE_ALT_SELECT)
629 == UDMA_MODE_PER_SCATTER_GATHER))
631 control &= ~UDMA_MODE_ALT_SELECT;
635 // Return the mode to the caller.
640 void DMA_assignChannel(uint32_t mapping)
644 case DMA_CH0_RESERVED0:
645 case DMA_CH0_EUSCIA0TX:
646 case DMA_CH0_EUSCIB0TX0:
647 case DMA_CH0_EUSCIB3TX1:
648 case DMA_CH0_EUSCIB2TX2:
649 case DMA_CH0_EUSCIB1TX3:
650 case DMA_CH0_TIMERA0CCR0:
651 case DMA_CH0_AESTRIGGER0:
652 DMA->rCH0_SRCCFG.r = (mapping >> 24) & 0x1F;
654 case DMA_CH1_RESERVED0:
655 case DMA_CH1_EUSCIA0RX:
656 case DMA_CH1_EUSCIB0RX0:
657 case DMA_CH1_EUSCIB3RX1:
658 case DMA_CH1_EUSCIB2RX2:
659 case DMA_CH1_EUSCIB1RX3:
660 case DMA_CH1_TIMERA0CCR2:
661 case DMA_CH1_AESTRIGGER1:
662 DMA->rCH1_SRCCFG.r = (mapping >> 24) & 0x1F;
664 case DMA_CH2_RESERVED0:
665 case DMA_CH2_EUSCIA1TX:
666 case DMA_CH2_EUSCIB1TX0:
667 case DMA_CH2_EUSCIB0TX1:
668 case DMA_CH2_EUSCIB3TX2:
669 case DMA_CH2_EUSCIB2TX3:
670 case DMA_CH2_TIMERA1CCR0:
671 case DMA_CH2_AESTRIGGER2:
672 DMA->rCH2_SRCCFG.r = (mapping >> 24) & 0x1F;
674 case DMA_CH3_RESERVED0:
675 case DMA_CH3_EUSCIA1RX:
676 case DMA_CH3_EUSCIB1RX0:
677 case DMA_CH3_EUSCIB0RX1:
678 case DMA_CH3_EUSCIB3RX2:
679 case DMA_CH3_EUSCIB2RX3:
680 case DMA_CH3_TIMERA1CCR2:
681 case DMA_CH3_RESERVED1:
682 DMA->rCH3_SRCCFG.r = (mapping >> 24) & 0x1F;
684 case DMA_CH4_RESERVED0:
685 case DMA_CH4_EUSCIA2TX:
686 case DMA_CH4_EUSCIB2TX0:
687 case DMA_CH4_EUSCIB1TX1:
688 case DMA_CH4_EUSCIB0TX2:
689 case DMA_CH4_EUSCIB3TX3:
690 case DMA_CH4_TIMERA2CCR0:
691 case DMA_CH4_RESERVED1:
692 DMA->rCH4_SRCCFG.r = (mapping >> 24) & 0x1F;
694 case DMA_CH5_RESERVED0:
695 case DMA_CH5_EUSCIA2RX:
696 case DMA_CH5_EUSCIB2RX0:
697 case DMA_CH5_EUSCIB1RX1:
698 case DMA_CH5_EUSCIB0RX2:
699 case DMA_CH5_EUSCIB3RX3:
700 case DMA_CH5_TIMERA2CCR2:
701 case DMA_CH5_RESERVED1:
702 DMA->rCH5_SRCCFG.r = (mapping >> 24) & 0x1F;
704 case DMA_CH6_RESERVED0:
705 case DMA_CH6_EUSCIA3TX:
706 case DMA_CH6_EUSCIB3TX0:
707 case DMA_CH6_EUSCIB2TX1:
708 case DMA_CH6_EUSCIB1TX2:
709 case DMA_CH6_EUSCIB0TX3:
710 case DMA_CH6_TIMERA3CCR0:
711 case DMA_CH6_EXTERNALPIN:
712 DMA->rCH6_SRCCFG.r = (mapping >> 24) & 0x1F;
714 case DMA_CH7_RESERVED0:
715 case DMA_CH7_EUSCIA3RX:
716 case DMA_CH7_EUSCIB3RX0:
717 case DMA_CH7_EUSCIB2RX1:
718 case DMA_CH7_EUSCIB1RX2:
719 case DMA_CH7_EUSCIB0RX3:
720 case DMA_CH7_TIMERA3CCR2:
722 DMA->rCH7_SRCCFG.r = (mapping >> 24) & 0x1F;
730 void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel)
733 interruptNumber == DMA_INT1 || interruptNumber == DMA_INT2
734 || interruptNumber == DMA_INT3);
736 if (interruptNumber == DMA_INT1)
738 DMA->rINT1_SRCCFG.r = (DMA->rINT1_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
740 } else if (interruptNumber == DMA_INT2)
742 DMA->rINT2_SRCCFG.r = (DMA->rINT2_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
744 } else if (interruptNumber == DMA_INT3)
746 DMA->rINT3_SRCCFG.r = (DMA->rINT3_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
750 /* Enabling the assigned interrupt */
751 DMA_enableInterrupt(interruptNumber);
754 void DMA_requestSoftwareTransfer(uint32_t channel)
756 DMA->rSW_CHTRIG.r |= (1 << channel);
759 uint32_t DMA_getInterruptStatus(void)
761 return DMA->rINT0_SRCFLG.r;
764 void DMA_clearInterruptFlag(uint32_t channel)
766 DMA->rINT0_CLRFLG.r |= (1 << channel);
769 void DMA_enableInterrupt(uint32_t interruptNumber)
772 (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
773 || (interruptNumber == DMA_INT2)
774 || (interruptNumber == DMA_INT3));
776 if (interruptNumber == DMA_INT1)
778 DMA->rINT1_SRCCFG.r |= DMA_INT1_SRCCFG_EN;
779 } else if (interruptNumber == DMA_INT2)
781 DMA->rINT2_SRCCFG.r |= DMA_INT2_SRCCFG_EN;
782 } else if (interruptNumber == DMA_INT3)
784 DMA->rINT3_SRCCFG.r |= DMA_INT3_SRCCFG_EN;
789 void DMA_disableInterrupt(uint32_t interruptNumber)
792 (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
793 || (interruptNumber == DMA_INT2)
794 || (interruptNumber == DMA_INT3));
796 if (interruptNumber == DMA_INT1)
798 DMA->rINT1_SRCCFG.r &= ~DMA_INT1_SRCCFG_EN;
799 } else if (interruptNumber == DMA_INT2)
801 DMA->rINT2_SRCCFG.r &= ~DMA_INT2_SRCCFG_EN;
802 } else if (interruptNumber == DMA_INT3)
804 DMA->rINT3_SRCCFG.r &= ~DMA_INT3_SRCCFG_EN;
808 void DMA_registerInterrupt(uint32_t interruptNumber, void (*intHandler)(void))
811 // Check the arguments.
815 (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
816 || (interruptNumber == DMA_INT2)
817 || (interruptNumber == DMA_INT3)
818 || (interruptNumber == DMA_INTERR));
821 // Register the interrupt handler.
823 Interrupt_registerInterrupt(interruptNumber, intHandler);
826 // Enable the memory management fault.
828 Interrupt_enableInterrupt(interruptNumber);
832 void DMA_unregisterInterrupt(uint32_t interruptNumber)
835 (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
836 || (interruptNumber == DMA_INT2)
837 || (interruptNumber == DMA_INT3)
838 || (interruptNumber == DMA_INTERR));
841 // Disable the interrupt.
843 Interrupt_disableInterrupt(interruptNumber);
846 // Unregister the interrupt handler.
848 Interrupt_unregisterInterrupt(interruptNumber);