2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2014, Texas Instruments Incorporated
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 /* Standard Includes */
40 /* DriverLib Includes */
43 #include <interrupt.h>
48 #include <hw_memmap.h>
50 static const uint32_t MAX_ERASE_NO_TLV = 50;
51 static const uint32_t MAX_PROGRAM_NO_TLV = 5;
53 static volatile uint32_t* __getBurstProgramRegs[16] =
54 { &FLCTL->PRGBRST_DATA0_0, &FLCTL->PRGBRST_DATA0_1,
55 &FLCTL->PRGBRST_DATA0_2, &FLCTL->PRGBRST_DATA0_3,
56 &FLCTL->PRGBRST_DATA1_0, &FLCTL->PRGBRST_DATA1_1,
57 &FLCTL->PRGBRST_DATA1_2, &FLCTL->PRGBRST_DATA1_3,
58 &FLCTL->PRGBRST_DATA2_0, &FLCTL->PRGBRST_DATA2_1,
59 &FLCTL->PRGBRST_DATA2_2, &FLCTL->PRGBRST_DATA2_3,
60 &FLCTL->PRGBRST_DATA3_0, &FLCTL->PRGBRST_DATA3_1,
61 &FLCTL->PRGBRST_DATA3_2, &FLCTL->PRGBRST_DATA3_3 };
63 static uint32_t getUserFlashSector(uint32_t addr)
67 addr = addr - 0x20000;
93 return FLASH_SECTOR10;
95 return FLASH_SECTOR11;
97 return FLASH_SECTOR12;
99 return FLASH_SECTOR13;
101 return FLASH_SECTOR14;
103 return FLASH_SECTOR15;
105 return FLASH_SECTOR16;
107 return FLASH_SECTOR17;
109 return FLASH_SECTOR18;
111 return FLASH_SECTOR19;
113 return FLASH_SECTOR20;
115 return FLASH_SECTOR21;
117 return FLASH_SECTOR22;
119 return FLASH_SECTOR23;
121 return FLASH_SECTOR24;
123 return FLASH_SECTOR25;
125 return FLASH_SECTOR26;
127 return FLASH_SECTOR27;
129 return FLASH_SECTOR28;
131 return FLASH_SECTOR29;
133 return FLASH_SECTOR30;
135 return FLASH_SECTOR31;
142 void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *sectorNum,
147 bankLimit = SysCtl_getFlashSize() / 2;
149 if (addr > bankLimit)
151 *(sectorNum) = FLASH_BANK1;
152 addr = (addr - bankLimit);
155 *(sectorNum) = FLASH_BANK0;
158 *(bankNum) = (addr - __MAIN_MEMORY_START__) / 4096;
161 static bool _FlashCtl_Program8(uint32_t src, uint32_t dest, uint32_t mTries)
166 /* Enabling the correct verification settings */
167 FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
168 FlashCtl_clearProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE);
172 for (ii = 0; ii < mTries; ii++)
175 FLCTL->CLRIFG |= (FLASH_PROGRAM_ERROR | FLASH_POSTVERIFY_FAILED
176 | FLASH_PREVERIFY_FAILED | FLASH_WRDPRGM_COMPLETE);
180 while (!(FlashCtl_getInterruptStatus() & FLASH_WRDPRGM_COMPLETE))
186 if ((BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PRE_OFS)
187 && BITBAND_PERI(FLCTL->IFG, FLCTL_IFG_AVPRE_OFS)))
189 data = __FlashCtl_remaskData8Pre(data, dest);
193 FlashCtl_clearProgramVerification(FLASH_REGPRE);
200 if ((BITBAND_PERI(FLCTL->IFG, FLCTL_IFG_AVPST_OFS)))
202 data = __FlashCtl_remaskData8Post(data, dest);
204 /* Seeing if we actually need to do another pulse */
208 FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
212 /* If we got this far, return true */
221 static bool _FlashCtl_Program32(uint32_t src, uint32_t dest, uint32_t mTries)
226 /* Enabling the correct verification settings */
227 FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
228 FlashCtl_clearProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE);
232 for (ii = 0; ii < mTries; ii++)
235 FLCTL->CLRIFG |= (FLASH_PROGRAM_ERROR | FLASH_POSTVERIFY_FAILED
236 | FLASH_PREVERIFY_FAILED | FLASH_WRDPRGM_COMPLETE);
238 HWREG32(dest) = data;
240 while (!(FlashCtl_getInterruptStatus() & FLASH_WRDPRGM_COMPLETE))
246 if ((BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PRE_OFS)
247 && BITBAND_PERI(FLCTL->IFG, FLCTL_IFG_AVPRE_OFS)))
249 data = __FlashCtl_remaskData32Pre(data, dest);
251 if (data != 0xFFFFFFFF)
254 FlashCtl_clearProgramVerification(FLASH_REGPRE);
261 if ((BITBAND_PERI(FLCTL->IFG, FLCTL_IFG_AVPST_OFS)))
263 data = __FlashCtl_remaskData32Post(data, dest);
265 /* Seeing if we actually need to do another pulse */
266 if (data == 0xFFFFFFFF)
269 FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
273 /* If we got this far, return true */
282 static bool _FlashCtl_ProgramBurst(uint32_t src, uint32_t dest, uint32_t length,
285 uint32_t bCalc, otpOffset, ii, jj;
288 /* Setting verification */
289 FlashCtl_clearProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
290 FlashCtl_setProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE);
295 /* Waiting for idle status */
296 while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK)
297 != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0)
299 BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
300 FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1;
303 /* Setting/clearing INFO flash flags as appropriate */
304 if (dest > __MAIN_MEMORY_END__)
306 FLCTL->PRGBRST_CTLSTAT = (FLCTL->PRGBRST_CTLSTAT
307 & ~FLCTL_PRGBRST_CTLSTAT_TYPE_MASK) | FLCTL_PRGBRST_CTLSTAT_TYPE_1;
308 otpOffset = __INFO_FLASH_TECH_START__;
311 FLCTL->PRGBRST_CTLSTAT = (FLCTL->PRGBRST_CTLSTAT
312 & ~FLCTL_PRGBRST_CTLSTAT_TYPE_MASK) | FLCTL_PRGBRST_CTLSTAT_TYPE_0;
313 otpOffset = __MAIN_MEMORY_START__;
317 FLCTL->PRGBRST_STARTADDR = (dest - otpOffset);
319 /* Initially populating the burst registers */
320 while (bCalc < 16 && length != 0)
322 HWREG32(__getBurstProgramRegs[bCalc]) = HWREG32(src);
328 for (ii = 0; ii < mTries; ii++)
331 FLCTL->CLRIFG |= (FLASH_BRSTPRGM_COMPLETE | FLASH_POSTVERIFY_FAILED
332 | FLASH_PREVERIFY_FAILED);
334 /* Waiting for idle status */
335 while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK)
336 != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0)
338 BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
339 FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1;
342 /* Start the burst program */
343 FLCTL->PRGBRST_CTLSTAT = (FLCTL->PRGBRST_CTLSTAT
344 & ~(FLCTL_PRGBRST_CTLSTAT_LEN_MASK))
345 | ((bCalc / 4) << FLASH_BURST_PRG_BIT)
346 | FLCTL_PRGBRST_CTLSTAT_START;
348 /* Waiting for the burst to complete */
349 while ((FLCTL->PRGBRST_CTLSTAT &
350 FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK)
351 != FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE)
356 /* Checking for errors and clearing/masking */
359 if (BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
360 FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS))
365 /* Pre-Verify Error */
366 if (BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
367 FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) && BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
368 FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS))
370 __FlashCtl_remaskBurstDataPre(dest, bCalc * 4);
372 for (jj = 0; jj < bCalc; jj++)
374 if (HWREG32(__getBurstProgramRegs[jj])
377 FlashCtl_clearProgramVerification(FLASH_BURSTPRE);
386 /* Post-Verify Error */
387 if (BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
388 FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS))
390 __FlashCtl_remaskBurstDataPost(dest, bCalc * 4);
392 for (jj = 0; jj < bCalc; jj++)
394 if ((HWREG32(__getBurstProgramRegs[jj]))
397 FlashCtl_setProgramVerification(
398 FLASH_BURSTPOST | FLASH_BURSTPRE);
408 /* If we got this far, the program happened */
414 /* Waiting for idle status */
415 while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK)
416 != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0)
418 BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
419 FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1;
424 void FlashCtl_enableReadBuffering(uint_fast8_t memoryBank,
425 uint_fast8_t accessMethod)
427 if (memoryBank == FLASH_BANK0 && accessMethod == FLASH_DATA_READ)
428 BITBAND_PERI(FLCTL->BANK0_RDCTL, FLCTL_BANK0_RDCTL_BUFD_OFS) = 1;
429 else if (memoryBank == FLASH_BANK1 && accessMethod == FLASH_DATA_READ)
430 BITBAND_PERI(FLCTL->BANK1_RDCTL, FLCTL_BANK1_RDCTL_BUFD_OFS) = 1;
431 else if (memoryBank == FLASH_BANK0
432 && accessMethod == FLASH_INSTRUCTION_FETCH)
433 BITBAND_PERI(FLCTL->BANK0_RDCTL, FLCTL_BANK0_RDCTL_BUFI_OFS) = 1;
434 else if (memoryBank == FLASH_BANK1
435 && accessMethod == FLASH_INSTRUCTION_FETCH)
436 BITBAND_PERI(FLCTL->BANK1_RDCTL, FLCTL_BANK1_RDCTL_BUFI_OFS) = 1;
441 void FlashCtl_disableReadBuffering(uint_fast8_t memoryBank,
442 uint_fast8_t accessMethod)
444 if (memoryBank == FLASH_BANK0 && accessMethod == FLASH_DATA_READ)
445 BITBAND_PERI(FLCTL->BANK0_RDCTL, FLCTL_BANK0_RDCTL_BUFD_OFS) = 0;
446 else if (memoryBank == FLASH_BANK1 && accessMethod == FLASH_DATA_READ)
447 BITBAND_PERI(FLCTL->BANK1_RDCTL, FLCTL_BANK1_RDCTL_BUFD_OFS) = 0;
448 else if (memoryBank == FLASH_BANK0
449 && accessMethod == FLASH_INSTRUCTION_FETCH)
450 BITBAND_PERI(FLCTL->BANK0_RDCTL, FLCTL_BANK0_RDCTL_BUFI_OFS) = 0;
451 else if (memoryBank == FLASH_BANK1
452 && accessMethod == FLASH_INSTRUCTION_FETCH)
453 BITBAND_PERI(FLCTL->BANK1_RDCTL, FLCTL_BANK1_RDCTL_BUFI_OFS) = 0;
458 bool FlashCtl_unprotectSector(uint_fast8_t memorySpace, uint32_t sectorMask)
462 case FLASH_MAIN_MEMORY_SPACE_BANK0:
463 FLCTL->BANK0_MAIN_WEPROT &= ~sectorMask;
465 case FLASH_MAIN_MEMORY_SPACE_BANK1:
466 FLCTL->BANK1_MAIN_WEPROT &= ~sectorMask;
468 case FLASH_INFO_MEMORY_SPACE_BANK0:
469 ASSERT(sectorMask <= 0x04);
470 FLCTL->BANK0_INFO_WEPROT &= ~sectorMask;
472 case FLASH_INFO_MEMORY_SPACE_BANK1:
473 ASSERT(sectorMask <= 0x04);
474 FLCTL->BANK1_INFO_WEPROT &= ~sectorMask;
482 return !FlashCtl_isSectorProtected(memorySpace, sectorMask);
485 bool FlashCtl_protectSector(uint_fast8_t memorySpace, uint32_t sectorMask)
489 case FLASH_MAIN_MEMORY_SPACE_BANK0:
490 FLCTL->BANK0_MAIN_WEPROT |= sectorMask;
492 case FLASH_MAIN_MEMORY_SPACE_BANK1:
493 FLCTL->BANK1_MAIN_WEPROT |= sectorMask;
495 case FLASH_INFO_MEMORY_SPACE_BANK0:
496 ASSERT(sectorMask <= 0x04);
497 FLCTL->BANK0_INFO_WEPROT |= sectorMask;
499 case FLASH_INFO_MEMORY_SPACE_BANK1:
500 ASSERT(sectorMask <= 0x04);
501 FLCTL->BANK1_INFO_WEPROT |= sectorMask;
509 return FlashCtl_isSectorProtected(memorySpace, sectorMask);
512 bool FlashCtl_isSectorProtected(uint_fast8_t memorySpace, uint32_t sector)
516 case FLASH_MAIN_MEMORY_SPACE_BANK0:
517 return FLCTL->BANK0_MAIN_WEPROT & sector;
518 case FLASH_MAIN_MEMORY_SPACE_BANK1:
519 return FLCTL->BANK1_MAIN_WEPROT & sector;
520 case FLASH_INFO_MEMORY_SPACE_BANK0:
521 ASSERT(sector <= 0x04);
522 return FLCTL->BANK0_INFO_WEPROT & sector;
523 case FLASH_INFO_MEMORY_SPACE_BANK1:
524 ASSERT(sector <= 0x04);
525 return FLCTL->BANK1_INFO_WEPROT & sector;
531 bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length,
532 uint_fast8_t pattern)
534 uint32_t memoryPattern, addr, otpOffset;
535 uint32_t b0WaitState, b1WaitState, intStatus;
536 uint32_t bankOneStart, startBank, endBank;
537 uint_fast8_t b0readMode, b1readMode;
538 uint_fast8_t memoryType;
541 ASSERT(pattern == FLASH_0_PATTERN || pattern == FLASH_1_PATTERN);
543 /* Saving interrupt context and disabling interrupts for program
546 intStatus = CPU_primask();
547 Interrupt_disableMaster();
549 /* Casting and determining the memory that we need to use */
550 addr = (uint32_t) verifyAddr;
552 (addr > __MAIN_MEMORY_END__) ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
554 /* Assuming Failure */
557 /* Finding out which bank we are in */
558 if(addr > SysCtl_getFlashSize())
560 bankOneStart = __INFO_FLASH_TECH_MIDDLE__;
564 bankOneStart = SysCtl_getFlashSize() / 2;
566 startBank = addr < (bankOneStart) ? FLASH_BANK0 : FLASH_BANK1;
567 endBank = (addr + length) < (bankOneStart) ? FLASH_BANK0 : FLASH_BANK1;
569 /* Saving context and changing read modes */
570 b0WaitState = FlashCtl_getWaitState(startBank);
571 b0readMode = FlashCtl_getReadMode(startBank);
573 /* Setting the wait state to account for the mode */
574 FlashCtl_setWaitState(startBank, (2 * b0WaitState) + 1);
576 if(startBank != endBank)
578 b1WaitState = FlashCtl_getWaitState(endBank);
579 b1readMode = FlashCtl_getReadMode(endBank);
580 FlashCtl_setWaitState(endBank, (2 * b1WaitState) + 1);
583 /* Changing to the relevant VERIFY mode */
584 if (pattern == FLASH_1_PATTERN)
586 FlashCtl_setReadMode(startBank, FLASH_ERASE_VERIFY_READ_MODE);
588 if(startBank != endBank)
590 FlashCtl_setReadMode(endBank, FLASH_ERASE_VERIFY_READ_MODE);
593 memoryPattern = 0xFFFFFFFF;
596 FlashCtl_setReadMode(startBank, FLASH_PROGRAM_VERIFY_READ_MODE);
598 if(startBank != endBank)
600 FlashCtl_setReadMode(endBank, FLASH_PROGRAM_VERIFY_READ_MODE);
606 /* Taking care of byte accesses */
607 while ((addr & 0x03) && (length > 0))
609 if (HWREG8(addr++) != ((uint8_t) memoryPattern))
610 goto FlashVerifyCleanup;
614 /* Making sure we are aligned by 128-bit address */
615 while (((addr & 0x0F)) && (length > 3))
617 if (HWREG32(addr) != memoryPattern)
618 goto FlashVerifyCleanup;
627 /* Setting/clearing INFO flash flags as appropriate */
628 if (addr > __MAIN_MEMORY_END__)
630 FLCTL->RDBRST_CTLSTAT = (FLCTL->RDBRST_CTLSTAT
631 & ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK)
632 | FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1;
633 otpOffset = __INFO_FLASH_TECH_START__;
636 FLCTL->RDBRST_CTLSTAT = (FLCTL->RDBRST_CTLSTAT
637 & ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK)
638 | FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0;
639 otpOffset = __MAIN_MEMORY_START__;
642 /* Clearing any lingering fault flags and preparing burst verify*/
643 BITBAND_PERI(FLCTL->RDBRST_CTLSTAT,
644 FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) = 1;
645 FLCTL->RDBRST_FAILCNT = 0;
646 FLCTL->RDBRST_STARTADDR = addr - otpOffset;
647 FLCTL->RDBRST_LEN = (length & 0xFFFFFFF0);
648 addr += FLCTL->RDBRST_LEN;
649 length = length & 0xF;
651 /* Starting Burst Verify */
652 FLCTL->RDBRST_CTLSTAT = (FLCTL_RDBRST_CTLSTAT_STOP_FAIL | pattern
653 | memoryType | FLCTL_RDBRST_CTLSTAT_START);
655 /* While the burst read hasn't finished */
656 while ((FLCTL->RDBRST_CTLSTAT & FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK)
657 != FLCTL_RDBRST_CTLSTAT_BRST_STAT_3)
662 /* Checking for a verification/access error/failure */
663 if (BITBAND_PERI(FLCTL->RDBRST_CTLSTAT,
664 FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS)
665 || BITBAND_PERI(FLCTL->RDBRST_CTLSTAT,
666 FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS)
667 || FLCTL->RDBRST_FAILCNT)
669 goto FlashVerifyCleanup;
673 /* Remaining Words */
676 if (HWREG32(addr) != memoryPattern)
677 goto FlashVerifyCleanup;
683 /* Remaining Bytes */
686 if (HWREG8(addr++) != ((uint8_t) memoryPattern))
687 goto FlashVerifyCleanup;
691 /* If we got this far, that means it no failure happened */
696 /* Clearing the Read Burst flag and returning */
697 BITBAND_PERI(FLCTL->RDBRST_CTLSTAT,
698 FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) = 1;
700 FlashCtl_setReadMode(startBank, b0readMode);
701 FlashCtl_setWaitState(startBank, b0WaitState);
703 if(startBank != endBank)
705 FlashCtl_setReadMode(endBank, b1readMode);
706 FlashCtl_setWaitState(endBank, b1WaitState);
710 Interrupt_enableMaster();
715 bool FlashCtl_setReadMode(uint32_t flashBank, uint32_t readMode)
718 if (FLCTL->POWER_STAT & FLCTL_POWER_STAT_RD_2T)
721 if (flashBank == FLASH_BANK0)
723 FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL
724 & ~FLCTL_BANK0_RDCTL_RD_MODE_MASK) | readMode;
725 while ((FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_RD_MODE_MASK)
728 } else if (flashBank == FLASH_BANK1)
730 FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL
731 & ~FLCTL_BANK1_RDCTL_RD_MODE_MASK) | readMode;
732 while ((FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_RD_MODE_MASK)
744 uint32_t FlashCtl_getReadMode(uint32_t flashBank)
746 if (flashBank == FLASH_BANK0)
748 return (FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_RD_MODE_MASK);
749 } else if (flashBank == FLASH_BANK1)
751 return (FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_RD_MODE_MASK);
759 void FlashCtl_initiateMassErase(void)
761 /* Clearing old mass erase flags */
762 BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
764 /* Performing the mass erase */
765 FLCTL->ERASE_CTLSTAT |= (FLCTL_ERASE_CTLSTAT_MODE
766 | FLCTL_ERASE_CTLSTAT_START);
769 bool FlashCtl_performMassErase(void)
771 uint32_t userFlash, ii, sector, intStatus;
774 /* Saving interrupt context and disabling interrupts for program
777 intStatus = CPU_primask();
778 Interrupt_disableMaster();
783 /* Clearing old mass erase flags */
784 BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
786 /* Performing the mass erase */
787 FLCTL->ERASE_CTLSTAT |= (FLCTL_ERASE_CTLSTAT_MODE
788 | FLCTL_ERASE_CTLSTAT_START);
790 while ((FLCTL->ERASE_CTLSTAT & FLCTL_ERASE_CTLSTAT_STATUS_MASK)
791 == FLCTL_ERASE_CTLSTAT_STATUS_1
792 || (FLCTL->ERASE_CTLSTAT & FLCTL_ERASE_CTLSTAT_STATUS_MASK)
793 == FLCTL_ERASE_CTLSTAT_STATUS_2)
798 /* Return false if an address error */
799 if (BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS))
800 goto MassEraseCleanup;
802 /* Changing to erase verify */
803 userFlash = SysCtl_getFlashSize() / 2;
805 for (ii = __MAIN_MEMORY_START__; ii < userFlash; ii += 4096)
807 sector = getUserFlashSector(ii);
809 if (!((FLCTL->BANK0_MAIN_WEPROT) & sector))
811 if (!FlashCtl_verifyMemory((void*) ii, 4096, FLASH_1_PATTERN))
813 if (!FlashCtl_eraseSector(ii))
814 goto MassEraseCleanup;
818 if (!(FLCTL->BANK1_MAIN_WEPROT & sector))
820 if (!FlashCtl_verifyMemory((void*) (ii + userFlash), 4096,
823 if (!FlashCtl_eraseSector(ii + userFlash))
824 goto MassEraseCleanup;
828 if (sector < FLCTL_BANK0_MAIN_WEPROT_PROT2)
830 if (!(FLCTL->BANK0_INFO_WEPROT & sector))
832 if (!FlashCtl_verifyMemory(
833 (void*) (ii + __INFO_FLASH_TECH_START__), 4096,
836 if (!FlashCtl_eraseSector(ii + __INFO_FLASH_TECH_START__))
837 goto MassEraseCleanup;
841 if (!(FLCTL->BANK1_INFO_WEPROT & sector))
843 if (!FlashCtl_verifyMemory((void*) (ii + (0x202000)), 4096,
846 if (!FlashCtl_eraseSector(ii + (0x202000)))
847 goto MassEraseCleanup;
854 /* If we got this far, the mass erase happened */
858 BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
861 Interrupt_enableMaster();
866 bool FlashCtl_eraseSector(uint32_t addr)
868 uint_fast8_t memoryType, ii;
869 uint32_t otpOffset = 0;
871 uint_fast8_t mTries, tlvLength;
872 SysCtl_FlashTLV_Info *flInfo;
875 /* Saving interrupt context and disabling interrupts for program
878 intStatus = CPU_primask();
879 Interrupt_disableMaster();
881 /* Assuming Failure */
885 addr > __MAIN_MEMORY_END__ ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
887 /* Parsing the TLV and getting the maximum erase pulses */
888 SysCtl_getTLVInfo(TLV_TAG_FLASHCTL, 0, &tlvLength, (uint32_t**) &flInfo);
890 if (tlvLength == 0 || flInfo->maxErasePulses == 0)
892 mTries = MAX_ERASE_NO_TLV;
895 mTries = flInfo->maxErasePulses;
898 /* We can only erase on 4KB boundaries */
904 /* Clearing the status */
905 BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
907 if (memoryType == FLASH_INFO_SPACE)
909 otpOffset = __INFO_FLASH_TECH_START__;
910 FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT
911 & ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_1;
915 otpOffset = __MAIN_MEMORY_START__;
916 FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT
917 & ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_0;
920 /* Clearing old flags and setting up the erase */
921 BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_MODE_OFS) = 0;
922 FLCTL->ERASE_SECTADDR = addr - otpOffset;
924 for (ii = 0; ii < mTries; ii++)
926 /* Clearing the status */
927 BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) =
930 /* Starting the erase */
931 BITBAND_PERI(FLCTL->ERASE_CTLSTAT,
932 FLCTL_ERASE_CTLSTAT_START_OFS) = 1;
934 while ((FLCTL->ERASE_CTLSTAT & FLCTL_ERASE_CTLSTAT_STATUS_MASK)
935 == FLCTL_ERASE_CTLSTAT_STATUS_1
936 || (FLCTL->ERASE_CTLSTAT & FLCTL_ERASE_CTLSTAT_STATUS_MASK)
937 == FLCTL_ERASE_CTLSTAT_STATUS_2)
942 /* Return false if an address error */
943 if (BITBAND_PERI(FLCTL->ERASE_CTLSTAT,
944 FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS))
946 goto SectorEraseCleanup;
948 /* Erase verifying */
949 if (FlashCtl_verifyMemory((void*) addr, 4096, FLASH_1_PATTERN))
952 goto SectorEraseCleanup;
959 BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
962 Interrupt_enableMaster();
967 void FlashCtl_initiateSectorErase(uint32_t addr)
969 uint_fast8_t memoryType;
970 uint32_t otpOffset = 0;
973 addr > __MAIN_MEMORY_END__ ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
975 /* We can only erase on 4KB boundaries */
981 /* Clearing the status */
982 BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
984 if (memoryType == FLASH_INFO_SPACE)
986 otpOffset = __INFO_FLASH_TECH_START__;
987 FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT
988 & ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_1;
992 otpOffset = __MAIN_MEMORY_START__;
993 FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT
994 & ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_0;
997 /* Clearing old flags and setting up the erase */
998 BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_MODE_OFS) = 0;
999 FLCTL->ERASE_SECTADDR = addr - otpOffset;
1001 /* Starting the erase */
1002 BITBAND_PERI(FLCTL->ERASE_CTLSTAT,
1003 FLCTL_ERASE_CTLSTAT_START_OFS) = 1;
1007 bool FlashCtl_programMemory(void* src, void* dest, uint32_t length)
1009 uint32_t destAddr, srcAddr, burstLength, intStatus;
1011 uint_fast8_t mTries, tlvLength;
1012 SysCtl_FlashTLV_Info *flInfo;
1014 /* Saving interrupt context and disabling interrupts for program
1017 intStatus = CPU_primask();
1018 Interrupt_disableMaster();
1020 /* Parsing the TLV and getting the maximum erase pulses */
1021 SysCtl_getTLVInfo(TLV_TAG_FLASHCTL, 0, &tlvLength, (uint32_t**) &flInfo);
1023 if (tlvLength == 0 || flInfo->maxProgramPulses == 0)
1025 mTries = MAX_PROGRAM_NO_TLV;
1028 mTries = flInfo->maxProgramPulses;
1031 /* Casting to integers */
1032 srcAddr = (uint32_t) src;
1033 destAddr = (uint32_t) dest;
1035 /* Enabling word programming */
1036 FlashCtl_enableWordProgramming(FLASH_IMMEDIATE_WRITE_MODE);
1038 /* Assume failure */
1041 /* Taking care of byte accesses */
1042 while ((destAddr & 0x03) && length > 0)
1044 if (!_FlashCtl_Program8(srcAddr, destAddr, mTries))
1046 goto FlashProgramCleanUp;
1055 /* Taking care of word accesses */
1056 while ((destAddr & 0x0F) && (length > 3))
1058 if (!_FlashCtl_Program32(srcAddr, destAddr, mTries))
1060 goto FlashProgramCleanUp;
1069 /* Taking care of burst programs */
1072 burstLength = length > 63 ? 64 : length & 0xFFFFFFF0;
1074 if (!_FlashCtl_ProgramBurst(srcAddr, destAddr, burstLength, mTries))
1076 goto FlashProgramCleanUp;
1079 srcAddr += burstLength;
1080 destAddr += burstLength;
1081 length -= burstLength;
1085 /* Remaining word accesses */
1088 if (!_FlashCtl_Program32(srcAddr, destAddr, mTries))
1090 goto FlashProgramCleanUp;
1099 /* Remaining byte accesses */
1102 if (!_FlashCtl_Program8(srcAddr, destAddr, mTries))
1104 goto FlashProgramCleanUp;
1113 /* If we got this far that means that we succeeded */
1116 FlashProgramCleanUp:
1119 Interrupt_enableMaster();
1121 FlashCtl_disableWordProgramming();
1125 void FlashCtl_setProgramVerification(uint32_t verificationSetting)
1127 if ((verificationSetting & FLASH_BURSTPOST))
1128 BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
1129 FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS) = 1;
1131 if ((verificationSetting & FLASH_BURSTPRE))
1132 BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
1133 FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) = 1;
1135 if ((verificationSetting & FLASH_REGPRE))
1136 BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) = 1;
1138 if ((verificationSetting & FLASH_REGPOST))
1139 BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PST_OFS) = 1;
1142 void FlashCtl_clearProgramVerification(uint32_t verificationSetting)
1144 if ((verificationSetting & FLASH_BURSTPOST))
1145 BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
1146 FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS) = 0;
1148 if ((verificationSetting & FLASH_BURSTPRE))
1149 BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
1150 FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) = 0;
1152 if ((verificationSetting & FLASH_REGPRE))
1153 BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) = 0;
1155 if ((verificationSetting & FLASH_REGPOST))
1156 BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PST_OFS) = 0;
1160 void FlashCtl_enableWordProgramming(uint32_t mode)
1162 if (mode == FLASH_IMMEDIATE_WRITE_MODE)
1164 BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 1;
1165 BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_MODE_OFS) = 0;
1167 } else if (mode == FLASH_COLLATED_WRITE_MODE)
1169 BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 1;
1170 BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_MODE_OFS) = 1;
1174 void FlashCtl_disableWordProgramming(void)
1176 BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 0;
1179 uint32_t FlashCtl_isWordProgrammingEnabled(void)
1181 if (!BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_ENABLE_OFS))
1184 } else if (BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_MODE_OFS))
1185 return FLASH_COLLATED_WRITE_MODE;
1187 return FLASH_IMMEDIATE_WRITE_MODE;
1190 void FlashCtl_setWaitState(uint32_t flashBank, uint32_t waitState)
1192 if (flashBank == FLASH_BANK0)
1194 FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL
1195 & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | (waitState << FLCTL_BANK0_RDCTL_WAIT_OFS);
1196 } else if (flashBank == FLASH_BANK1)
1198 FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL
1199 & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | (waitState << FLCTL_BANK1_RDCTL_WAIT_OFS);
1206 uint32_t FlashCtl_getWaitState(uint32_t flashBank)
1208 if (flashBank == FLASH_BANK0)
1210 return (FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_WAIT_MASK) >> FLCTL_BANK0_RDCTL_WAIT_OFS;
1211 } else if (flashBank == FLASH_BANK1)
1213 return (FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_WAIT_MASK) >> FLCTL_BANK1_RDCTL_WAIT_OFS;
1221 void FlashCtl_enableInterrupt(uint32_t flags)
1226 void FlashCtl_disableInterrupt(uint32_t flags)
1228 FLCTL->IE &= ~flags;
1231 uint32_t FlashCtl_getInterruptStatus(void)
1236 uint32_t FlashCtl_getEnabledInterruptStatus(void)
1238 return FlashCtl_getInterruptStatus() & FLCTL->IE;
1241 void FlashCtl_clearInterruptFlag(uint32_t flags)
1243 FLCTL->CLRIFG |= flags;
1246 void FlashCtl_registerInterrupt(void (*intHandler)(void))
1249 // Register the interrupt handler, returning an error if an error occurs.
1251 Interrupt_registerInterrupt(INT_FLCTL, intHandler);
1254 // Enable the system control interrupt.
1256 Interrupt_enableInterrupt(INT_FLCTL);
1259 void FlashCtl_unregisterInterrupt(void)
1262 // Disable the interrupt.
1264 Interrupt_disableInterrupt(INT_FLCTL);
1267 // Unregister the interrupt handler.
1269 Interrupt_unregisterInterrupt(INT_FLCTL);
1272 uint8_t __FlashCtl_remaskData8Post(uint8_t data, uint32_t addr)
1274 uint32_t readMode, waitState, bankProgram, bankOneStart;
1276 /* Changing the waitstate and read mode of whichever bank we are in */
1277 /* Finding out which bank we are in */
1278 if(addr > SysCtl_getFlashSize())
1280 bankOneStart = __INFO_FLASH_TECH_MIDDLE__;
1284 bankOneStart = SysCtl_getFlashSize() / 2;
1288 addr < (bankOneStart) ? FLASH_BANK0 : FLASH_BANK1;
1290 /* Saving the current wait states and read mode */
1291 waitState = FlashCtl_getWaitState(bankProgram);
1292 readMode = FlashCtl_getReadMode(bankProgram);
1294 /* Setting the wait state to account for the mode */
1295 FlashCtl_setWaitState(bankProgram, (2 * waitState) + 1);
1297 /* Changing to PROGRAM VERIFY mode */
1298 FlashCtl_setReadMode(bankProgram, FLASH_PROGRAM_VERIFY_READ_MODE);
1300 data = ~(~(data) & HWREG8(addr));
1302 /* Setting the wait state to account for the mode */
1303 FlashCtl_setReadMode(bankProgram, readMode);
1304 FlashCtl_setWaitState(bankProgram, waitState);
1309 uint8_t __FlashCtl_remaskData8Pre(uint8_t data, uint32_t addr)
1311 uint32_t readMode, waitState, bankProgram, bankOneStart;
1313 /* Changing the waitstate and read mode of whichever bank we are in */
1314 /* Finding out which bank we are in */
1315 if(addr > SysCtl_getFlashSize())
1317 bankOneStart = __INFO_FLASH_TECH_MIDDLE__;
1321 bankOneStart = SysCtl_getFlashSize() / 2;
1325 addr < (bankOneStart) ? FLASH_BANK0 : FLASH_BANK1;
1327 /* Saving the current wait states and read mode */
1328 waitState = FlashCtl_getWaitState(bankProgram);
1329 readMode = FlashCtl_getReadMode(bankProgram);
1331 /* Setting the wait state to account for the mode */
1332 FlashCtl_setWaitState(bankProgram, (2 * waitState) + 1);
1334 /* Changing to PROGRAM VERIFY mode */
1335 FlashCtl_setReadMode(bankProgram, FLASH_PROGRAM_VERIFY_READ_MODE);
1337 data |= ~(HWREG8(addr) | data);
1339 /* Setting the wait state to account for the mode */
1340 FlashCtl_setReadMode(bankProgram, readMode);
1341 FlashCtl_setWaitState(bankProgram, waitState);
1346 uint32_t __FlashCtl_remaskData32Post(uint32_t data, uint32_t addr)
1348 uint32_t bankProgramStart, bankProgramEnd, bank1Start;
1349 uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode;
1351 /* Changing the waitstate and read mode of whichever bank we are in */
1352 /* Finding out which bank we are in */
1353 if(addr > SysCtl_getFlashSize())
1355 bank1Start = __INFO_FLASH_TECH_MIDDLE__;
1359 bank1Start = SysCtl_getFlashSize() / 2;
1362 bankProgramStart = addr < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
1363 bankProgramEnd = (addr + 4) < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
1365 /* Saving the current wait states and read mode */
1366 b0WaitState = FlashCtl_getWaitState(bankProgramStart);
1367 b0ReadMode = FlashCtl_getReadMode(bankProgramStart);
1368 FlashCtl_setWaitState(bankProgramStart, (2 * b0WaitState) + 1);
1369 FlashCtl_setReadMode(bankProgramStart, FLASH_PROGRAM_VERIFY_READ_MODE);
1371 if (bankProgramStart != bankProgramEnd)
1373 b1WaitState = FlashCtl_getWaitState(bankProgramEnd);
1374 b1ReadMode = FlashCtl_getReadMode(bankProgramEnd);
1375 FlashCtl_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1);
1376 FlashCtl_setReadMode(bankProgramEnd, FLASH_PROGRAM_VERIFY_READ_MODE);
1379 data = ~(~(data) & HWREG32(addr));
1381 /* Setting the wait state to account for the mode */
1382 FlashCtl_setReadMode(bankProgramStart, b0ReadMode);
1383 FlashCtl_setWaitState(bankProgramStart, b0WaitState);
1385 if (bankProgramStart != bankProgramEnd)
1387 FlashCtl_setReadMode(bankProgramEnd, b1ReadMode);
1388 FlashCtl_setWaitState(bankProgramEnd, b1WaitState);
1394 uint32_t __FlashCtl_remaskData32Pre(uint32_t data, uint32_t addr)
1396 uint32_t bankProgramStart, bankProgramEnd, bank1Start;
1397 uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode;
1399 /* Changing the waitstate and read mode of whichever bank we are in */
1400 /* Finding out which bank we are in */
1401 if(addr > SysCtl_getFlashSize())
1403 bank1Start = __INFO_FLASH_TECH_MIDDLE__;
1407 bank1Start = SysCtl_getFlashSize() / 2;
1410 bankProgramStart = addr < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
1411 bankProgramEnd = (addr + 4) < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
1413 /* Saving the current wait states and read mode */
1414 b0WaitState = FlashCtl_getWaitState(bankProgramStart);
1415 b0ReadMode = FlashCtl_getReadMode(bankProgramStart);
1416 FlashCtl_setWaitState(bankProgramStart, (2 * b0WaitState) + 1);
1417 FlashCtl_setReadMode(bankProgramStart, FLASH_PROGRAM_VERIFY_READ_MODE);
1419 if (bankProgramStart != bankProgramEnd)
1421 b1WaitState = FlashCtl_getWaitState(bankProgramEnd);
1422 b1ReadMode = FlashCtl_getReadMode(bankProgramEnd);
1423 FlashCtl_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1);
1424 FlashCtl_setReadMode(bankProgramEnd, FLASH_PROGRAM_VERIFY_READ_MODE);
1427 data |= ~(HWREG32(addr) | data);
1429 /* Setting the wait state to account for the mode */
1430 FlashCtl_setReadMode(bankProgramStart, b0ReadMode);
1431 FlashCtl_setWaitState(bankProgramStart, b0WaitState);
1433 if (bankProgramStart != bankProgramEnd)
1435 FlashCtl_setReadMode(bankProgramEnd, b1ReadMode);
1436 FlashCtl_setWaitState(bankProgramEnd, b1WaitState);
1442 void __FlashCtl_remaskBurstDataPre(uint32_t addr, uint32_t size)
1445 uint32_t bankProgramStart, bankProgramEnd, bank1Start, ii;
1446 uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode;
1448 /* Waiting for idle status */
1449 while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK)
1450 != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0)
1452 BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
1453 FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1;
1456 /* Changing the waitstate and read mode of whichever bank we are in */
1457 /* Finding out which bank we are in */
1458 if(addr > SysCtl_getFlashSize())
1460 bank1Start = __INFO_FLASH_TECH_MIDDLE__;
1464 bank1Start = SysCtl_getFlashSize() / 2;
1467 bankProgramStart = addr < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
1468 bankProgramEnd = (addr + size) < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
1470 /* Saving the current wait states and read mode */
1471 b0WaitState = FlashCtl_getWaitState(bankProgramStart);
1472 b0ReadMode = FlashCtl_getReadMode(bankProgramStart);
1473 FlashCtl_setWaitState(bankProgramStart, (2 * b0WaitState) + 1);
1474 FlashCtl_setReadMode(bankProgramStart, FLASH_PROGRAM_VERIFY_READ_MODE);
1476 if (bankProgramStart != bankProgramEnd)
1478 b1WaitState = FlashCtl_getWaitState(bankProgramEnd);
1479 b1ReadMode = FlashCtl_getReadMode(bankProgramEnd);
1480 FlashCtl_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1);
1481 FlashCtl_setReadMode(bankProgramEnd, FLASH_PROGRAM_VERIFY_READ_MODE);
1484 /* Going through each BURST program register and masking out for pre
1488 for (ii = 0; ii < size; ii++)
1490 HWREG32(__getBurstProgramRegs[ii]) |=
1491 ~(HWREG32(__getBurstProgramRegs[ii])
1496 /* Setting the wait state to account for the mode */
1497 FlashCtl_setReadMode(bankProgramStart, b0ReadMode);
1498 FlashCtl_setWaitState(bankProgramStart, b0WaitState);
1500 if (bankProgramStart != bankProgramEnd)
1502 FlashCtl_setReadMode(bankProgramEnd, b1ReadMode);
1503 FlashCtl_setWaitState(bankProgramEnd, b1WaitState);
1507 void __FlashCtl_remaskBurstDataPost(uint32_t addr, uint32_t size)
1509 uint32_t bankProgramStart, bankProgramEnd, bank1Start, ii;
1510 uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode;
1512 /* Waiting for idle status */
1513 while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK)
1514 != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0)
1516 BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
1517 FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1;
1520 /* Changing the waitstate and read mode of whichever bank we are in */
1521 /* Finding out which bank we are in */
1522 if(addr > SysCtl_getFlashSize())
1524 bank1Start = __INFO_FLASH_TECH_MIDDLE__;
1528 bank1Start = SysCtl_getFlashSize() / 2;
1531 bankProgramStart = addr < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
1532 bankProgramEnd = (addr + size) < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
1534 /* Saving the current wait states and read mode */
1535 b0WaitState = FlashCtl_getWaitState(bankProgramStart);
1536 b0ReadMode = FlashCtl_getReadMode(bankProgramStart);
1537 FlashCtl_setWaitState(bankProgramStart, (2 * b0WaitState) + 1);
1538 FlashCtl_setReadMode(bankProgramStart, FLASH_PROGRAM_VERIFY_READ_MODE);
1540 if (bankProgramStart != bankProgramEnd)
1542 b1WaitState = FlashCtl_getWaitState(bankProgramEnd);
1543 b1ReadMode = FlashCtl_getReadMode(bankProgramEnd);
1544 FlashCtl_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1);
1545 FlashCtl_setReadMode(bankProgramEnd, FLASH_PROGRAM_VERIFY_READ_MODE);
1548 /* Going through each BURST program register and masking out for post
1549 * verifcation if needed
1552 for (ii = 0; ii < size; ii++)
1554 HWREG32(__getBurstProgramRegs[ii]) = ~(~(HWREG32(
1555 __getBurstProgramRegs[ii])) & HWREG32(addr));
1560 /* Setting the wait state to account for the mode */
1561 FlashCtl_setReadMode(bankProgramStart, b0ReadMode);
1562 FlashCtl_setWaitState(bankProgramStart, b0WaitState);
1564 if (bankProgramStart != bankProgramEnd)
1566 FlashCtl_setReadMode(bankProgramEnd, b1ReadMode);
1567 FlashCtl_setWaitState(bankProgramEnd, b1WaitState);