2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2014, Texas Instruments Incorporated
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11 * modification, are permitted provided that the following conditions
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15 * notice, this list of conditions and the following disclaimer.
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <interrupt.h>
40 #include <hw_memmap.h>
42 void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *config)
44 uint_fast16_t preScalarValue;
47 (EUSCI_B_I2C_CLOCKSOURCE_ACLK == config->selectClockSource)
48 || (EUSCI_B_I2C_CLOCKSOURCE_SMCLK
49 == config->selectClockSource));
52 (EUSCI_B_I2C_SET_DATA_RATE_400KBPS == config->dataRate)
53 || (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == config->dataRate)
54 || (EUSCI_B_I2C_SET_DATA_RATE_1MBPS == config->dataRate));
57 (EUSCI_B_I2C_NO_AUTO_STOP == config->autoSTOPGeneration)
58 || (EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG
59 == config->autoSTOPGeneration)
60 || (EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD
61 == config->autoSTOPGeneration));
63 /* Disable the USCI module and clears the other bits of control register */
64 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
67 /* Configure Automatic STOP condition generation */
68 EUSCI_B_CMSIS(moduleInstance)->CTLW1 =
69 (EUSCI_B_CMSIS(moduleInstance)->CTLW1 & ~EUSCI_B_CTLW1_ASTP_MASK)
70 | (config->autoSTOPGeneration);
72 /* Byte Count Threshold */
73 EUSCI_B_CMSIS(moduleInstance)->TBCNT = config->byteCounterThreshold;
76 * Configure as I2C master mode.
79 * UCSYNC = Synchronous mode
81 EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
82 (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_B_CTLW0_SSEL_MASK)
83 | (config->selectClockSource | EUSCI_B_CTLW0_MST
84 | EUSCI_B_CTLW0_MODE_3 | EUSCI_B_CTLW0_SYNC
85 | EUSCI_B_CTLW0_SWRST);
88 * Compute the clock divider that achieves the fastest speed less than or
89 * equal to the desired speed. The numerator is biased to favor a larger
90 * clock divider so that the resulting clock is always less than or equal
91 * to the desired clock, never greater.
93 preScalarValue = (uint16_t) (config->i2cClk / config->dataRate);
95 EUSCI_B_CMSIS(moduleInstance)->BRW = preScalarValue;
98 void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress,
99 uint_fast8_t slaveAddressOffset, uint32_t slaveOwnAddressEnable)
102 (EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 == slaveAddressOffset)
103 || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 == slaveAddressOffset)
104 || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 == slaveAddressOffset)
105 || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 == slaveAddressOffset));
107 /* Disable the USCI module */
108 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
111 /* Clear USCI master mode */
112 EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
113 (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & (~EUSCI_B_CTLW0_MST))
114 | (EUSCI_B_CTLW0_MODE_3 + EUSCI_B_CTLW0_SYNC);
116 /* Set up the slave address. */
117 HWREG16((uint32_t)&EUSCI_B_CMSIS(moduleInstance)->I2COA0 + slaveAddressOffset) =
118 slaveAddress + slaveOwnAddressEnable;
121 void I2C_enableModule(uint32_t moduleInstance)
123 /* Reset the UCSWRST bit to enable the USCI Module */
124 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
128 void I2C_disableModule(uint32_t moduleInstance)
130 /* Set the UCSWRST bit to disable the USCI Module */
131 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
136 void I2C_setSlaveAddress(uint32_t moduleInstance, uint_fast16_t slaveAddress)
138 /* Set the address of the slave with which the master will communicate */
139 EUSCI_B_CMSIS(moduleInstance)->I2CSA = (slaveAddress);
142 void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode)
145 (EUSCI_B_I2C_TRANSMIT_MODE == mode)
146 || (EUSCI_B_I2C_RECEIVE_MODE == mode));
148 EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
149 (EUSCI_B_CMSIS(moduleInstance)->CTLW0
150 & (~EUSCI_B_I2C_TRANSMIT_MODE)) | mode;
154 uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance)
156 //Set USCI in Receive mode
157 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TR_OFS) = 0;
160 EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= (EUSCI_B_CTLW0_TXSTT + EUSCI_B_CTLW0_TXSTP);
162 //Poll for receive interrupt flag.
163 while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
166 //Send single byte data.
167 return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
170 void I2C_slavePutData(uint32_t moduleInstance, uint8_t transmitData)
172 //Send single byte data.
173 EUSCI_B_CMSIS(moduleInstance)->TXBUF = transmitData;
176 uint8_t I2C_slaveGetData(uint32_t moduleInstance)
179 return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
182 uint8_t I2C_isBusBusy(uint32_t moduleInstance)
184 //Return the bus busy status.
185 return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->STATW,
186 EUSCI_B_STATW_BBUSY_OFS);
189 void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData)
191 //Store current TXIE status
192 uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
194 //Disable transmit interrupt enable
195 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0;
197 //Send start condition.
198 EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
200 //Poll for transmit interrupt flag.
201 while (!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG))
204 //Send single byte data.
205 EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
207 //Poll for transmit interrupt flag.
208 while (!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG))
211 //Send stop condition.
212 EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TXSTP;
214 //Clear transmit interrupt flag before enabling interrupt again
215 EUSCI_B_CMSIS(moduleInstance)->IFG &= ~(EUSCI_B_IFG_TXIFG);
217 //Reinstate transmit interrupt enable
218 EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
221 bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
222 uint8_t txData, uint32_t timeout)
224 uint_fast16_t txieStatus;
225 uint32_t timeout2 = timeout;
229 //Store current TXIE status
230 txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
232 //Disable transmit interrupt enable
233 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE,EUSCI_B_IE_TXIE0_OFS) = 0;
235 //Send start condition.
236 EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
238 //Poll for transmit interrupt flag.
239 while ((!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG)) && --timeout)
242 //Check if transfer timed out
246 //Send single byte data.
247 EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
249 //Poll for transmit interrupt flag.
250 while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
254 //Check if transfer timed out
258 //Send stop condition.
259 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
261 //Clear transmit interrupt flag before enabling interrupt again
262 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,EUSCI_B_IFG_TXIFG0_OFS) = 0;
264 //Reinstate transmit interrupt enable
265 EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
270 void I2C_masterSendMultiByteStart(uint32_t moduleInstance, uint8_t txData)
272 //Store current transmit interrupt enable
273 uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
275 //Disable transmit interrupt enable
276 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0;
278 //Send start condition.
279 EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
281 //Poll for transmit interrupt flag.
282 while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
285 //Send single byte data.
286 EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
288 //Reinstate transmit interrupt enable
289 EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
292 bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance,
293 uint8_t txData, uint32_t timeout)
295 uint_fast16_t txieStatus;
299 //Store current transmit interrupt enable
300 txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
302 //Disable transmit interrupt enable
303 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE,EUSCI_B_IE_TXIE0_OFS) = 0;
305 //Send start condition.
306 EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
308 //Poll for transmit interrupt flag.
309 while ((!(BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
313 //Check if transfer timed out
317 //Send single byte data.
318 EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
320 //Reinstate transmit interrupt enable
321 EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
326 void I2C_masterSendMultiByteNext(uint32_t moduleInstance, uint8_t txData)
328 //If interrupts are not used, poll for flags
329 if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
331 //Poll for transmit interrupt flag.
333 (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
337 //Send single byte data.
338 EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
341 bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
342 uint8_t txData, uint32_t timeout)
346 //If interrupts are not used, poll for flags
347 if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
349 //Poll for transmit interrupt flag.
350 while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
351 EUSCI_B_IFG_TXIFG0_OFS)) && --timeout)
354 //Check if transfer timed out
359 //Send single byte data.
360 EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
365 void I2C_masterSendMultiByteFinish(uint32_t moduleInstance, uint8_t txData)
367 //If interrupts are not used, poll for flags
368 if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
370 //Poll for transmit interrupt flag.
372 (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
376 //Send single byte data.
377 EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
379 //Poll for transmit interrupt flag.
380 while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
383 //Send stop condition.
384 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
387 bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
388 uint8_t txData, uint32_t timeout)
390 uint32_t timeout2 = timeout;
394 //If interrupts are not used, poll for flags
395 if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
397 //Poll for transmit interrupt flag.
398 while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
399 EUSCI_B_IFG_TXIFG0_OFS)) && --timeout)
402 //Check if transfer timed out
407 //Send single byte data.
408 EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
410 //Poll for transmit interrupt flag.
411 while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
415 //Check if transfer timed out
419 //Send stop condition.
420 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
425 void I2C_masterSendMultiByteStop(uint32_t moduleInstance)
427 //If interrupts are not used, poll for flags
428 if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
430 //Poll for transmit interrupt flag.
432 (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
436 //Send stop condition.
437 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
440 bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
445 //If interrupts are not used, poll for flags
446 if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
448 //Poll for transmit interrupt flag.
449 while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
450 EUSCI_B_IFG_TXIFG0_OFS)) && --timeout)
453 //Check if transfer timed out
458 //Send stop condition.
459 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
464 void I2C_masterReceiveStart(uint32_t moduleInstance)
466 //Set USCI in Receive mode
467 EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
468 (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & (~EUSCI_B_CTLW0_TR))
469 | EUSCI_B_CTLW0_TXSTT;
472 uint8_t I2C_masterReceiveMultiByteNext(uint32_t moduleInstance)
474 return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
477 uint8_t I2C_masterReceiveMultiByteFinish(uint32_t moduleInstance)
479 //Send stop condition.
480 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) =
483 //Wait for Stop to finish
484 while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS))
486 // Wait for RX buffer
487 while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
491 /* Capture data from receive buffer after setting stop bit due to
492 MSP430 I2C critical timing. */
493 return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
496 bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
497 uint8_t *txData, uint32_t timeout)
499 uint32_t timeout2 = timeout;
503 //Send stop condition.
504 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
506 //Wait for Stop to finish
507 while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS)
511 //Check if transfer timed out
515 // Wait for RX buffer
516 while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
520 //Check if transfer timed out
524 //Capture data from receive buffer after setting stop bit due to
525 //MSP430 I2C critical timing.
526 *txData = (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
531 void I2C_masterReceiveMultiByteStop(uint32_t moduleInstance)
533 //Send stop condition.
534 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
537 uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance)
539 //Polling RXIFG0 if RXIE is not enabled
540 if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_RXIE0_OFS))
542 while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
543 EUSCI_B_IFG_RXIFG0_OFS))
548 return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK) ;
551 uint32_t I2C_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
553 return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->RXBUF;
556 uint32_t I2C_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
558 return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF;
561 uint8_t I2C_masterIsStopSent(uint32_t moduleInstance)
563 return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
564 EUSCI_B_CTLW0_TXSTP_OFS);
567 bool I2C_masterIsStartSent(uint32_t moduleInstance)
569 return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
570 EUSCI_B_CTLW0_TXSTT_OFS);
573 void I2C_masterSendStart(uint32_t moduleInstance)
575 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTT_OFS) =
579 void I2C_enableMultiMasterMode(uint32_t moduleInstance)
581 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
583 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_MM_OFS) = 1;
586 void I2C_disableMultiMasterMode(uint32_t moduleInstance)
588 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
590 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_MM_OFS) = 0;
593 void I2C_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
598 & ~(EUSCI_B_I2C_STOP_INTERRUPT
599 + EUSCI_B_I2C_START_INTERRUPT
600 + EUSCI_B_I2C_NAK_INTERRUPT
601 + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
602 + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
603 + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
604 + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
605 + EUSCI_B_I2C_TRANSMIT_INTERRUPT0
606 + EUSCI_B_I2C_TRANSMIT_INTERRUPT1
607 + EUSCI_B_I2C_TRANSMIT_INTERRUPT2
608 + EUSCI_B_I2C_TRANSMIT_INTERRUPT3
609 + EUSCI_B_I2C_RECEIVE_INTERRUPT0
610 + EUSCI_B_I2C_RECEIVE_INTERRUPT1
611 + EUSCI_B_I2C_RECEIVE_INTERRUPT2
612 + EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
614 //Enable the interrupt masked bit
615 EUSCI_B_CMSIS(moduleInstance)->IE |= mask;
618 void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
623 & ~(EUSCI_B_I2C_STOP_INTERRUPT
624 + EUSCI_B_I2C_START_INTERRUPT
625 + EUSCI_B_I2C_NAK_INTERRUPT
626 + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
627 + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
628 + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
629 + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
630 + EUSCI_B_I2C_TRANSMIT_INTERRUPT0
631 + EUSCI_B_I2C_TRANSMIT_INTERRUPT1
632 + EUSCI_B_I2C_TRANSMIT_INTERRUPT2
633 + EUSCI_B_I2C_TRANSMIT_INTERRUPT3
634 + EUSCI_B_I2C_RECEIVE_INTERRUPT0
635 + EUSCI_B_I2C_RECEIVE_INTERRUPT1
636 + EUSCI_B_I2C_RECEIVE_INTERRUPT2
637 + EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
639 //Disable the interrupt masked bit
640 EUSCI_B_CMSIS(moduleInstance)->IE &= ~(mask);
643 void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask)
648 & ~(EUSCI_B_I2C_STOP_INTERRUPT
649 + EUSCI_B_I2C_START_INTERRUPT
650 + EUSCI_B_I2C_NAK_INTERRUPT
651 + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
652 + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
653 + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
654 + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
655 + EUSCI_B_I2C_TRANSMIT_INTERRUPT0
656 + EUSCI_B_I2C_TRANSMIT_INTERRUPT1
657 + EUSCI_B_I2C_TRANSMIT_INTERRUPT2
658 + EUSCI_B_I2C_TRANSMIT_INTERRUPT3
659 + EUSCI_B_I2C_RECEIVE_INTERRUPT0
660 + EUSCI_B_I2C_RECEIVE_INTERRUPT1
661 + EUSCI_B_I2C_RECEIVE_INTERRUPT2
662 + EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
663 //Clear the I2C interrupt source.
664 EUSCI_B_CMSIS(moduleInstance)->IFG &= ~(mask);
667 uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
672 & ~(EUSCI_B_I2C_STOP_INTERRUPT
673 + EUSCI_B_I2C_START_INTERRUPT
674 + EUSCI_B_I2C_NAK_INTERRUPT
675 + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
676 + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
677 + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
678 + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
679 + EUSCI_B_I2C_TRANSMIT_INTERRUPT0
680 + EUSCI_B_I2C_TRANSMIT_INTERRUPT1
681 + EUSCI_B_I2C_TRANSMIT_INTERRUPT2
682 + EUSCI_B_I2C_TRANSMIT_INTERRUPT3
683 + EUSCI_B_I2C_RECEIVE_INTERRUPT0
684 + EUSCI_B_I2C_RECEIVE_INTERRUPT1
685 + EUSCI_B_I2C_RECEIVE_INTERRUPT2
686 + EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
687 //Return the interrupt status of the request masked bit.
688 return EUSCI_B_CMSIS(moduleInstance)->IFG & mask;
691 uint_fast16_t I2C_getEnabledInterruptStatus(uint32_t moduleInstance)
693 return I2C_getInterruptStatus(moduleInstance,
694 EUSCI_B_CMSIS(moduleInstance)->IE);
697 uint_fast16_t I2C_getMode(uint32_t moduleInstance)
700 return (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & EUSCI_B_CTLW0_TR);
703 void I2C_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
705 switch (moduleInstance)
708 Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
709 Interrupt_enableInterrupt(INT_EUSCIB0);
712 Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
713 Interrupt_enableInterrupt(INT_EUSCIB1);
717 Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
718 Interrupt_enableInterrupt(INT_EUSCIB2);
723 Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
724 Interrupt_enableInterrupt(INT_EUSCIB3);
732 void I2C_unregisterInterrupt(uint32_t moduleInstance)
734 switch (moduleInstance)
737 Interrupt_disableInterrupt(INT_EUSCIB0);
738 Interrupt_unregisterInterrupt(INT_EUSCIB0);
741 Interrupt_disableInterrupt(INT_EUSCIB1);
742 Interrupt_unregisterInterrupt(INT_EUSCIB1);
746 Interrupt_disableInterrupt(INT_EUSCIB2);
747 Interrupt_unregisterInterrupt(INT_EUSCIB2);
752 Interrupt_disableInterrupt(INT_EUSCIB3);
753 Interrupt_unregisterInterrupt(INT_EUSCIB3);
761 void I2C_slaveSendNAK(uint32_t moduleInstance)
763 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXNACK_OFS)