1 //*****************************************************************************
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3 // Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
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5 // Redistribution and use in source and binary forms, with or without
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6 // modification, are permitted provided that the following conditions
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9 // Redistributions of source code must retain the above copyright
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10 // notice, this list of conditions and the following disclaimer.
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12 // Redistributions in binary form must reproduce the above copyright
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13 // notice, this list of conditions and the following disclaimer in the
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14 // documentation and/or other materials provided with the
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17 // Neither the name of Texas Instruments Incorporated nor the names of
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18 // its contributors may be used to endorse or promote products derived
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19 // from this software without specific prior written permission.
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21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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33 // MSP432 Family CMSIS Definitions
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35 //****************************************************************************
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37 #ifndef CMSIS_CCS_H_
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38 #define CMSIS_CCS_H_
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40 //*****************************************************************************
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41 // CMSIS-compatible instruction calls
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42 //*****************************************************************************
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46 __attribute__( ( always_inline ) ) static inline void __nop(void)
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51 __attribute__( ( always_inline ) ) static inline void __NOP(void)
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56 // Wait For Interrupt
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57 __attribute__( ( always_inline ) ) static inline void __wfi(void)
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63 __attribute__( ( always_inline ) ) static inline void __wfe(void)
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69 // Enable Interrupts
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70 __attribute__( ( always_inline ) ) static inline void __enable_irq(void)
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75 // Disable Interrupts
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76 __attribute__( ( always_inline ) ) static inline void __disable_irq(void)
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81 // Data Synchronization Barrier
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82 __attribute__( ( always_inline ) ) static inline void __DSB(void)
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88 // Get Main Stack Pointer
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89 static inline uint32_t __get_MSP(void)
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91 register uint32_t result;
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92 //__asm (" mrs result, msp");
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96 // Set Main Stack Pointer
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97 static inline void __set_MSP(uint32_t topOfMainStack)
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99 asm(" .global topOfMainStack");
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100 __asm (" msr msp, topOfMainStack");
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104 // Get Priority Mask
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105 static inline uint32_t __get_PRIMASK(void)
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108 __asm (" mrs result, primask");
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113 // Set Priority Mask
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114 static inline void __set_PRIMASK(uint32_t priMask)
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116 __asm (" msr primask, priMask");
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122 // v5e, v6, Cortex-M3, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
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124 #define __CLZ _norm
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125 #define __SXTB _sxtb
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126 #define __SXTH _sxth
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127 #define __UXTB _uxtb
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128 #define __UXTH _uxth
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129 // CCS supports intrinsics to take advantage of the shift operand left/right
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130 // before saturation extension of SSAT, but CMSIS does not take advantage
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131 // of those, so tell the compiler to use a sat & shift left with a shift
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132 // value of 0 whenever it encounters an SSAT
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133 #define __SSAT(VAL, BITPOS) \
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134 _ssatl(VAL , 0, BITPOS)
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137 // Only define M4 based intrinsics if we're not using an M4
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139 #if defined (__TI_TMS470_V7M4__)
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141 // V5E, V6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
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143 #define __QADD _sadd
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144 #define __QDADD _sdadd
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145 #define __QDSUB _sdsub
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146 #define __SMLABB _smlabb
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147 #define __SMLABT _smlabt
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148 #define __SMLALBB _smlalbb
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149 #define __SMLALBT _smlalbt
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150 #define __SMLALTB _smlaltb
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151 #define __SMLALTT _smlaltt
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152 #define __SMLATB _smlatb
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153 #define __SMLATT _smlatt
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154 #define __SMLAWB _smlawb
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155 #define __SMLAWT _smlawt
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157 #define __SMULBB _smulbb
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158 #define __SMULBT _smulbt
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159 #define __SMULTB _smultb
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160 #define __SMULTT _smultt
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161 #define __SMULWB _smulwb
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162 #define __SMULWT _smulwt
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163 #define __QSUB _ssub
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164 #define __SUBC _subc
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167 // v6, Cortex-M4, Cortex-R4, and Cortex-A8 compiler intrinsics
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169 #define __SHASX _shaddsubx
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170 #define __SHSAX _shsubaddx
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171 #define __PKHBT _pkhbt
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172 #define __PKHTB _pkhtb
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173 #define __QADD16 _qadd16
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174 #define __QADD8 _qadd8
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175 #define __QSUB16 _qsub16
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176 #define __QSUB8 _qsub8
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177 #define __QASX _saddsubx
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178 #define __QSAX _qsubaddx
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179 #define __SADD16 _sadd16
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180 #define __SADD8 _sadd8
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181 #define __SASX _saddsubx
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183 #define __SHADD16 _shadd16
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184 #define __SHADD8 _shadd8
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185 #define __SHSUB16 _shsub16
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186 #define __SHSUB8 _shsub8
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187 #define __SMLAD _smlad
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188 #define __SMLADX _smladx
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189 #define __SMLALD _smlald
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190 #define __SMLALDX _smlaldx
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191 #define __SMLSD _smlsd
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192 #define __SMLSDX _smlsdx
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193 #define __SMLSLD _smlsld
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194 #define __SMLSLDX _smlsldx
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195 #define __SMMLA _smmla
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196 #define __SMMLAR _smmlar
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197 #define __SMMLS _smmls
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198 #define __SMMLSR _smmlsr
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199 #define __SMMUL _smmul
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200 #define __SMMULR _smmulr
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201 #define __SMUAD _smuad
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202 #define __SMUADX _smuadx
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203 #define __SMUSD _smusd
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204 #define __SMUSDX _smusdx
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205 #define __SSAT16 _ssat16
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206 #define __SSUB16 _ssub16
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207 #define __SSUB8 _ssub8
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208 #define __SSAX _ssubaddx
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209 #define __SXTAB _sxtab
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210 #define __SXTAB16 _sxtab16
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211 #define __SXTAH _sxtah
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212 #define __UMAAL _umaal
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213 #define __UADD16 _uadd16
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214 #define __UADD8 _uadd8
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215 #define __UHADD16 _uhadd16
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216 #define __UHADD8 _uhadd8
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217 #define __UASX _uaddsubx
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218 #define __UHSUB16 _uhsub16
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219 #define __UHSUB8 _uhsub8
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220 #define __UQADD16 _uqadd16
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221 #define __UQADD8 _uqadd8
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222 #define __UQASX _uqaddsubx
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223 #define __UQSUB16 _uqsub16
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224 #define __UQSUB8 _uqsub8
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225 #define __UQSAX _uqsubaddx
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226 #define __USAD8 _usad8
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227 #define __USAT16 _usat16
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228 #define __USUB16 _usub16
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229 #define __USUB8 _usub8
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230 #define __USAX _usubaddx
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231 #define __UXTAB _uxtab
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232 #define __UXTAB16 _uxtab16
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233 #define __UXTAH _uxtah
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234 #define __UXTB16 _uxtb16
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235 #endif /*__TI_TMS470_V7M4__*/
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237 #endif /*CMSIS_CCS_H_*/
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