1 /**************************************************************************//**
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2 * @file core_cmInstr.h
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3 * @brief CMSIS Cortex-M Core Instruction Access Header File
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5 * @date 05. March 2013
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9 ******************************************************************************/
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10 /* Copyright (c) 2009 - 2013 ARM LIMITED
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12 All rights reserved.
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13 Redistribution and use in source and binary forms, with or without
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14 modification, are permitted provided that the following conditions are met:
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15 - Redistributions of source code must retain the above copyright
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16 notice, this list of conditions and the following disclaimer.
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17 - Redistributions in binary form must reproduce the above copyright
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18 notice, this list of conditions and the following disclaimer in the
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19 documentation and/or other materials provided with the distribution.
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20 - Neither the name of ARM nor the names of its contributors may be used
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21 to endorse or promote products derived from this software without
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22 specific prior written permission.
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24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 POSSIBILITY OF SUCH DAMAGE.
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35 ---------------------------------------------------------------------------*/
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38 #ifndef __CORE_CMINSTR_H
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39 #define __CORE_CMINSTR_H
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42 /* ########################## Core Instruction Access ######################### */
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43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
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44 Access to dedicated instructions
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48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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49 /* ARM armcc specific functions */
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51 #if (__ARMCC_VERSION < 400677)
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52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
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56 /** \brief No Operation
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58 No Operation does nothing. This instruction can be used for code alignment purposes.
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63 /** \brief Wait For Interrupt
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65 Wait For Interrupt is a hint instruction that suspends execution
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66 until one of a number of events occurs.
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71 /** \brief Wait For Event
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73 Wait For Event is a hint instruction that permits the processor to enter
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74 a low-power state until one of a number of events occurs.
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79 /** \brief Send Event
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81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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86 /** \brief Instruction Synchronization Barrier
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88 Instruction Synchronization Barrier flushes the pipeline in the processor,
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89 so that all instructions following the ISB are fetched from cache or
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90 memory, after the instruction has been completed.
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92 #define __ISB() __isb(0xF)
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95 /** \brief Data Synchronization Barrier
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97 This function acts as a special kind of Data Memory Barrier.
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98 It completes when all explicit memory accesses before this instruction complete.
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100 #define __DSB() __dsb(0xF)
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103 /** \brief Data Memory Barrier
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105 This function ensures the apparent order of the explicit memory operations before
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106 and after the instruction, without ensuring their completion.
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108 #define __DMB() __dmb(0xF)
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111 /** \brief Reverse byte order (32 bit)
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113 This function reverses the byte order in integer value.
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115 \param [in] value Value to reverse
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116 \return Reversed value
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118 #define __REV __rev
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121 /** \brief Reverse byte order (16 bit)
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123 This function reverses the byte order in two unsigned short values.
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125 \param [in] value Value to reverse
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126 \return Reversed value
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128 #ifndef __NO_EMBEDDED_ASM
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129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
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136 /** \brief Reverse byte order in signed short value
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138 This function reverses the byte order in a signed short value with sign extension to integer.
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140 \param [in] value Value to reverse
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141 \return Reversed value
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143 #ifndef __NO_EMBEDDED_ASM
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144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
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152 /** \brief Rotate Right in unsigned value (32 bit)
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154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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156 \param [in] value Value to rotate
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157 \param [in] value Number of Bits to rotate
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158 \return Rotated value
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160 #define __ROR __ror
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163 /** \brief Breakpoint
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165 This function causes the processor to enter Debug state.
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166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
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168 \param [in] value is ignored by the processor.
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169 If required, a debugger can use it to store additional information about the breakpoint.
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171 #define __BKPT(value) __breakpoint(value)
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174 #if (__CORTEX_M >= 0x03)
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176 /** \brief Reverse bit order of value
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178 This function reverses the bit order of the given value.
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180 \param [in] value Value to reverse
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181 \return Reversed value
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183 #define __RBIT __rbit
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186 /** \brief LDR Exclusive (8 bit)
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188 This function performs a exclusive LDR command for 8 bit value.
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190 \param [in] ptr Pointer to data
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191 \return value of type uint8_t at (*ptr)
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193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
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196 /** \brief LDR Exclusive (16 bit)
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198 This function performs a exclusive LDR command for 16 bit values.
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200 \param [in] ptr Pointer to data
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201 \return value of type uint16_t at (*ptr)
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203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
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206 /** \brief LDR Exclusive (32 bit)
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208 This function performs a exclusive LDR command for 32 bit values.
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210 \param [in] ptr Pointer to data
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211 \return value of type uint32_t at (*ptr)
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213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
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216 /** \brief STR Exclusive (8 bit)
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218 This function performs a exclusive STR command for 8 bit values.
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220 \param [in] value Value to store
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221 \param [in] ptr Pointer to location
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222 \return 0 Function succeeded
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223 \return 1 Function failed
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225 #define __STREXB(value, ptr) __strex(value, ptr)
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228 /** \brief STR Exclusive (16 bit)
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230 This function performs a exclusive STR command for 16 bit values.
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232 \param [in] value Value to store
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233 \param [in] ptr Pointer to location
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234 \return 0 Function succeeded
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235 \return 1 Function failed
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237 #define __STREXH(value, ptr) __strex(value, ptr)
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240 /** \brief STR Exclusive (32 bit)
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242 This function performs a exclusive STR command for 32 bit values.
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244 \param [in] value Value to store
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245 \param [in] ptr Pointer to location
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246 \return 0 Function succeeded
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247 \return 1 Function failed
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249 #define __STREXW(value, ptr) __strex(value, ptr)
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252 /** \brief Remove the exclusive lock
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254 This function removes the exclusive lock which is created by LDREX.
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257 #define __CLREX __clrex
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260 /** \brief Signed Saturate
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262 This function saturates a signed value.
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264 \param [in] value Value to be saturated
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265 \param [in] sat Bit position to saturate to (1..32)
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266 \return Saturated value
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268 #define __SSAT __ssat
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271 /** \brief Unsigned Saturate
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273 This function saturates an unsigned value.
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275 \param [in] value Value to be saturated
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276 \param [in] sat Bit position to saturate to (0..31)
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277 \return Saturated value
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279 #define __USAT __usat
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282 /** \brief Count leading zeros
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284 This function counts the number of leading zeros of a data value.
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286 \param [in] value Value to count the leading zeros
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287 \return number of leading zeros in value
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289 #define __CLZ __clz
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291 #endif /* (__CORTEX_M >= 0x03) */
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295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
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296 /* IAR iccarm specific functions */
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298 #include <cmsis_iar.h>
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301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
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302 /* TI CCS specific functions */
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304 #include <cmsis_ccs.h>
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307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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308 /* GNU gcc specific functions */
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310 /* Define macros for porting to both thumb1 and thumb2.
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311 * For thumb1, use low register (r0-r7), specified by constrant "l"
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312 * Otherwise, use general registers, specified by constrant "r" */
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313 #if defined (__thumb__) && !defined (__thumb2__)
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314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
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315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
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317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
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318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
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321 /** \brief No Operation
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323 No Operation does nothing. This instruction can be used for code alignment purposes.
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325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
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327 __ASM volatile ("nop");
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331 /** \brief Wait For Interrupt
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333 Wait For Interrupt is a hint instruction that suspends execution
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334 until one of a number of events occurs.
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336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
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338 __ASM volatile ("wfi");
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342 /** \brief Wait For Event
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344 Wait For Event is a hint instruction that permits the processor to enter
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345 a low-power state until one of a number of events occurs.
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347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
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349 __ASM volatile ("wfe");
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353 /** \brief Send Event
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355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
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359 __ASM volatile ("sev");
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363 /** \brief Instruction Synchronization Barrier
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365 Instruction Synchronization Barrier flushes the pipeline in the processor,
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366 so that all instructions following the ISB are fetched from cache or
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367 memory, after the instruction has been completed.
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369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
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371 __ASM volatile ("isb");
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375 /** \brief Data Synchronization Barrier
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377 This function acts as a special kind of Data Memory Barrier.
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378 It completes when all explicit memory accesses before this instruction complete.
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380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
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382 __ASM volatile ("dsb");
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386 /** \brief Data Memory Barrier
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388 This function ensures the apparent order of the explicit memory operations before
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389 and after the instruction, without ensuring their completion.
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391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
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393 __ASM volatile ("dmb");
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397 /** \brief Reverse byte order (32 bit)
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399 This function reverses the byte order in integer value.
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401 \param [in] value Value to reverse
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402 \return Reversed value
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404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
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406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
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407 return __builtin_bswap32(value);
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411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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417 /** \brief Reverse byte order (16 bit)
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419 This function reverses the byte order in two unsigned short values.
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421 \param [in] value Value to reverse
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422 \return Reversed value
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424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
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428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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433 /** \brief Reverse byte order in signed short value
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435 This function reverses the byte order in a signed short value with sign extension to integer.
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437 \param [in] value Value to reverse
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438 \return Reversed value
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440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
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442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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443 return (short)__builtin_bswap16(value);
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447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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453 /** \brief Rotate Right in unsigned value (32 bit)
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455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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457 \param [in] value Value to rotate
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458 \param [in] value Number of Bits to rotate
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459 \return Rotated value
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461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
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463 return (op1 >> op2) | (op1 << (32 - op2));
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467 /** \brief Breakpoint
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469 This function causes the processor to enter Debug state.
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470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
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472 \param [in] value is ignored by the processor.
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473 If required, a debugger can use it to store additional information about the breakpoint.
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475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
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478 #if (__CORTEX_M >= 0x03)
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480 /** \brief Reverse bit order of value
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482 This function reverses the bit order of the given value.
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484 \param [in] value Value to reverse
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485 \return Reversed value
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487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
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491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
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496 /** \brief LDR Exclusive (8 bit)
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498 This function performs a exclusive LDR command for 8 bit value.
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500 \param [in] ptr Pointer to data
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501 \return value of type uint8_t at (*ptr)
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503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
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507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
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510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
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511 accepted by assembler. So has to use following less efficient pattern.
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513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
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519 /** \brief LDR Exclusive (16 bit)
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521 This function performs a exclusive LDR command for 16 bit values.
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523 \param [in] ptr Pointer to data
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524 \return value of type uint16_t at (*ptr)
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526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
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530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
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533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
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534 accepted by assembler. So has to use following less efficient pattern.
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536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
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542 /** \brief LDR Exclusive (32 bit)
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544 This function performs a exclusive LDR command for 32 bit values.
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546 \param [in] ptr Pointer to data
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547 \return value of type uint32_t at (*ptr)
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549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
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553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
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558 /** \brief STR Exclusive (8 bit)
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560 This function performs a exclusive STR command for 8 bit values.
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562 \param [in] value Value to store
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563 \param [in] ptr Pointer to location
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564 \return 0 Function succeeded
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565 \return 1 Function failed
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567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
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571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
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576 /** \brief STR Exclusive (16 bit)
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578 This function performs a exclusive STR command for 16 bit values.
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580 \param [in] value Value to store
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581 \param [in] ptr Pointer to location
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582 \return 0 Function succeeded
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583 \return 1 Function failed
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585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
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589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
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594 /** \brief STR Exclusive (32 bit)
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596 This function performs a exclusive STR command for 32 bit values.
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598 \param [in] value Value to store
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599 \param [in] ptr Pointer to location
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600 \return 0 Function succeeded
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601 \return 1 Function failed
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603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
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607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
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612 /** \brief Remove the exclusive lock
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614 This function removes the exclusive lock which is created by LDREX.
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617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
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619 __ASM volatile ("clrex" ::: "memory");
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623 /** \brief Signed Saturate
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625 This function saturates a signed value.
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627 \param [in] value Value to be saturated
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628 \param [in] sat Bit position to saturate to (1..32)
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629 \return Saturated value
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631 #define __SSAT(ARG1,ARG2) \
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633 uint32_t __RES, __ARG1 = (ARG1); \
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634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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639 /** \brief Unsigned Saturate
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641 This function saturates an unsigned value.
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643 \param [in] value Value to be saturated
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644 \param [in] sat Bit position to saturate to (0..31)
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645 \return Saturated value
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647 #define __USAT(ARG1,ARG2) \
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649 uint32_t __RES, __ARG1 = (ARG1); \
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650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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655 /** \brief Count leading zeros
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657 This function counts the number of leading zeros of a data value.
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659 \param [in] value Value to count the leading zeros
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660 \return number of leading zeros in value
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662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
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666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
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670 #endif /* (__CORTEX_M >= 0x03) */
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675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
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676 /* TASKING carm specific functions */
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679 * The CMSIS functions have been implemented as intrinsics in the compiler.
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680 * Please use "carm -?i" to get an up to date list of all intrinsics,
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681 * Including the CMSIS ones.
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686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
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688 #endif /* __CORE_CMINSTR_H */
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