1 /******************************************************************************
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3 * Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
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5 * Redistribution and use in source and binary forms, with or without
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6 * modification, are permitted provided that the following conditions
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9 * Redistributions of source code must retain the above copyright
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10 * notice, this list of conditions and the following disclaimer.
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12 * Redistributions in binary form must reproduce the above copyright
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13 * notice, this list of conditions and the following disclaimer in the
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14 * documentation and/or other materials provided with the
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17 * Neither the name of Texas Instruments Incorporated nor the names of
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18 * its contributors may be used to endorse or promote products derived
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19 * from this software without specific prior written permission.
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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33 * MSP432P401R Register Definitions
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35 * This file includes CMSIS compliant component and register definitions
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37 * For legacy components the definitions that are compatible with MSP430 code,
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38 * are included with msp432p401r_classic.h
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40 * With CMSIS definitions, the register defines have been reformatted:
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41 * ModuleName[ModuleInstance]->RegisterName
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43 * Writing to CMSIS bit fields can be done through register level
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44 * or via bitband area access:
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45 * - ADC14->CTL0 |= ADC14_CTL0_ENC;
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46 * - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1;
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48 * File creation date: 2015-10-26
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50 ******************************************************************************/
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52 #ifndef __MSP432P401R_H__
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53 #define __MSP432P401R_H__
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55 /* Use standard integer types with explicit width */
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62 #define __MSP432_HEADER_VERSION__ 2000
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64 /* Remap MSP432 intrinsics to ARM equivalents */
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65 #include "msp_compatibility.h"
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67 /******************************************************************************
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68 * include MSP430 legacy definitions to make porting of code from MSP430 *
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69 * code base easier *
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70 * With fully CMSIS compliant code, NO_MSP_CLASSIC_DEFINES may be defined in *
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71 * your project to omit including the classic defines *
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72 ******************************************************************************/
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73 #ifndef NO_MSP_CLASSIC_DEFINES
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74 #include "msp432p401r_classic.h"
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77 #ifndef __CMSIS_CONFIG__
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78 #define __CMSIS_CONFIG__
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80 /** @addtogroup MSP432P401R_Definitions MSP432P401R Definitions
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81 This file defines all structures and symbols for MSP432P401R:
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82 - components and registers
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83 - peripheral base address
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85 - Peripheral definitions
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89 /******************************************************************************
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90 * Processor and Core Peripherals *
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91 ******************************************************************************/
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92 /** @addtogroup MSP432P401R_CMSIS Device CMSIS Definitions
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93 Configuration of the Cortex-M4 Processor and Core Peripherals
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97 /******************************************************************************
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98 * CMSIS-compatible Interrupt Number Definition *
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99 ******************************************************************************/
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102 /* Cortex-M4 Processor Exceptions Numbers */
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103 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
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104 HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */
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105 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
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106 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
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107 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
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108 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
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109 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
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110 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
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111 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
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112 /* Peripheral Exceptions Numbers */
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113 PSS_IRQn = 0, /* 16 PSS Interrupt */
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114 CS_IRQn = 1, /* 17 CS Interrupt */
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115 PCM_IRQn = 2, /* 18 PCM Interrupt */
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116 WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */
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117 FPU_IRQn = 4, /* 20 FPU Interrupt */
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118 FLCTL_IRQn = 5, /* 21 FLCTL Interrupt */
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119 COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */
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120 COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */
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121 TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */
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122 TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */
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123 TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */
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124 TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */
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125 TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */
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126 TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */
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127 TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */
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128 TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */
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129 EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */
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130 EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */
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131 EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */
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132 EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */
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133 EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */
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134 EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */
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135 EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */
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136 EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */
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137 ADC14_IRQn = 24, /* 40 ADC14 Interrupt */
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138 T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */
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139 T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */
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140 T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */
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141 AES256_IRQn = 28, /* 44 AES256 Interrupt */
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142 RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */
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143 DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */
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144 DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */
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145 DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */
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146 DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */
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147 DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */
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148 PORT1_IRQn = 35, /* 51 PORT1 Interrupt */
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149 PORT2_IRQn = 36, /* 52 PORT2 Interrupt */
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150 PORT3_IRQn = 37, /* 53 PORT3 Interrupt */
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151 PORT4_IRQn = 38, /* 54 PORT4 Interrupt */
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152 PORT5_IRQn = 39, /* 55 PORT5 Interrupt */
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153 PORT6_IRQn = 40 /* 56 PORT6 Interrupt */
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156 /******************************************************************************
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157 * Processor and Core Peripheral Section *
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158 ******************************************************************************/
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159 #define __CM4_REV 0x0001 /* Core revision r0p1 */
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160 #define __MPU_PRESENT 1 /* MPU present or not */
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161 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */
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162 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
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163 #define __FPU_PRESENT 1 /* FPU present or not */
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165 /******************************************************************************
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166 * Available Peripherals *
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167 ******************************************************************************/
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168 #define __MCU_HAS_ADC14__ /**< Module ADC14 is available */
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169 #define __MCU_HAS_AES256__ /**< Module AES256 is available */
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170 #define __MCU_HAS_CAPTIO0__ /**< Module CAPTIO0 is available */
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171 #define __MCU_HAS_CAPTIO1__ /**< Module CAPTIO1 is available */
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172 #define __MCU_HAS_COMP_E0__ /**< Module COMP_E0 is available */
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173 #define __MCU_HAS_COMP_E1__ /**< Module COMP_E1 is available */
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174 #define __MCU_HAS_CRC32__ /**< Module CRC32 is available */
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175 #define __MCU_HAS_CS__ /**< Module CS is available */
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176 #define __MCU_HAS_DIO__ /**< Module DIO is available */
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177 #define __MCU_HAS_DMA__ /**< Module DMA is available */
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178 #define __MCU_HAS_EUSCI_A0__ /**< Module EUSCI_A0 is available */
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179 #define __MCU_HAS_EUSCI_A1__ /**< Module EUSCI_A1 is available */
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180 #define __MCU_HAS_EUSCI_A2__ /**< Module EUSCI_A2 is available */
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181 #define __MCU_HAS_EUSCI_A3__ /**< Module EUSCI_A3 is available */
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182 #define __MCU_HAS_EUSCI_B0__ /**< Module EUSCI_B0 is available */
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183 #define __MCU_HAS_EUSCI_B1__ /**< Module EUSCI_B1 is available */
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184 #define __MCU_HAS_EUSCI_B2__ /**< Module EUSCI_B2 is available */
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185 #define __MCU_HAS_EUSCI_B3__ /**< Module EUSCI_B3 is available */
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186 #define __MCU_HAS_FLCTL__ /**< Module FLCTL is available */
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187 #define __MCU_HAS_PCM__ /**< Module PCM is available */
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188 #define __MCU_HAS_PMAP__ /**< Module PMAP is available */
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189 #define __MCU_HAS_PSS__ /**< Module PSS is available */
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190 #define __MCU_HAS_REF_A__ /**< Module REF_A is available */
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191 #define __MCU_HAS_RSTCTL__ /**< Module RSTCTL is available */
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192 #define __MCU_HAS_RTC_C__ /**< Module RTC_C is available */
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193 #define __MCU_HAS_SYSCTL__ /**< Module SYSCTL is available */
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194 #define __MCU_HAS_TIMER32__ /**< Module TIMER32 is available */
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195 #define __MCU_HAS_TIMER_A0__ /**< Module TIMER_A0 is available */
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196 #define __MCU_HAS_TIMER_A1__ /**< Module TIMER_A1 is available */
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197 #define __MCU_HAS_TIMER_A2__ /**< Module TIMER_A2 is available */
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198 #define __MCU_HAS_TIMER_A3__ /**< Module TIMER_A3 is available */
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199 #define __MCU_HAS_TLV__ /**< Module TLV is available */
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200 #define __MCU_HAS_WDT_A__ /**< Module WDT_A is available */
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202 /* Definitions to show that specific ports are available */
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204 #define __MSP432_HAS_PORTA_R__
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205 #define __MSP432_HAS_PORTB_R__
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206 #define __MSP432_HAS_PORTC_R__
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207 #define __MSP432_HAS_PORTD_R__
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208 #define __MSP432_HAS_PORTE_R__
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209 #define __MSP432_HAS_PORTJ_R__
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211 #define __MSP432_HAS_PORT1_R__
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212 #define __MSP432_HAS_PORT2_R__
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213 #define __MSP432_HAS_PORT3_R__
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214 #define __MSP432_HAS_PORT4_R__
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215 #define __MSP432_HAS_PORT5_R__
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216 #define __MSP432_HAS_PORT6_R__
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217 #define __MSP432_HAS_PORT7_R__
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218 #define __MSP432_HAS_PORT8_R__
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219 #define __MSP432_HAS_PORT9_R__
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220 #define __MSP432_HAS_PORT10_R__
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223 /*@}*/ /* end of group MSP432P401R_CMSIS */
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225 /* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */
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227 /* disable the TI ULP advisor check for the core header file definitions */
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229 #pragma CHECK_ULP("none")
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230 #include "core_cm4.h"
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233 #include "core_cm4.h"
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236 /* System Header */
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237 #include "system_msp432p401r.h"
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239 /******************************************************************************
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240 * Definition of standard bits *
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241 ******************************************************************************/
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242 #define BIT0 (uint16_t)(0x0001)
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243 #define BIT1 (uint16_t)(0x0002)
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244 #define BIT2 (uint16_t)(0x0004)
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245 #define BIT3 (uint16_t)(0x0008)
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246 #define BIT4 (uint16_t)(0x0010)
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247 #define BIT5 (uint16_t)(0x0020)
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248 #define BIT6 (uint16_t)(0x0040)
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249 #define BIT7 (uint16_t)(0x0080)
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250 #define BIT8 (uint16_t)(0x0100)
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251 #define BIT9 (uint16_t)(0x0200)
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252 #define BITA (uint16_t)(0x0400)
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253 #define BITB (uint16_t)(0x0800)
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254 #define BITC (uint16_t)(0x1000)
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255 #define BITD (uint16_t)(0x2000)
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256 #define BITE (uint16_t)(0x4000)
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257 #define BITF (uint16_t)(0x8000)
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258 #define BIT(x) ((uint16_t)1 << (x))
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260 /******************************************************************************
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261 * Device and peripheral memory map *
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262 ******************************************************************************/
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263 /** @addtogroup MSP432P401R_MemoryMap MSP432P401R Memory Mapping
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267 #define FLASH_BASE ((uint32_t)0x00000000) /**< Main Flash memory start address */
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268 #define SRAM_BASE ((uint32_t)0x20000000) /**< SRAM memory start address */
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269 #define PERIPH_BASE ((uint32_t)0x40000000) /**< Peripherals start address */
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270 #define PERIPH_BASE2 ((uint32_t)0xE0000000) /**< Peripherals start address */
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272 #define ADC14_BASE (PERIPH_BASE +0x00012000) /**< Base address of module ADC14 registers */
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273 #define AES256_BASE (PERIPH_BASE +0x00003C00) /**< Base address of module AES256 registers */
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274 #define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /**< Base address of module CAPTIO0 registers */
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275 #define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /**< Base address of module CAPTIO1 registers */
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276 #define COMP_E0_BASE (PERIPH_BASE +0x00003400) /**< Base address of module COMP_E0 registers */
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277 #define COMP_E1_BASE (PERIPH_BASE +0x00003800) /**< Base address of module COMP_E1 registers */
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278 #define CRC32_BASE (PERIPH_BASE +0x00004000) /**< Base address of module CRC32 registers */
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279 #define CS_BASE (PERIPH_BASE +0x00010400) /**< Base address of module CS registers */
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280 #define DIO_BASE (PERIPH_BASE +0x00004C00) /**< Base address of module DIO registers */
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281 #define DMA_BASE (PERIPH_BASE +0x0000E000) /**< Base address of module DMA registers */
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282 #define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /**< Base address of module EUSCI_A0 registers */
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283 #define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /**< Base address of module EUSCI_A0 registers */
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284 #define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /**< Base address of module EUSCI_A1 registers */
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285 #define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /**< Base address of module EUSCI_A1 registers */
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286 #define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /**< Base address of module EUSCI_A2 registers */
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287 #define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /**< Base address of module EUSCI_A2 registers */
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288 #define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /**< Base address of module EUSCI_A3 registers */
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289 #define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /**< Base address of module EUSCI_A3 registers */
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290 #define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /**< Base address of module EUSCI_B0 registers */
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291 #define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /**< Base address of module EUSCI_B0 registers */
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292 #define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /**< Base address of module EUSCI_B1 registers */
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293 #define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /**< Base address of module EUSCI_B1 registers */
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294 #define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /**< Base address of module EUSCI_B2 registers */
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295 #define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /**< Base address of module EUSCI_B2 registers */
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296 #define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /**< Base address of module EUSCI_B3 registers */
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297 #define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /**< Base address of module EUSCI_B3 registers */
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298 #define FLCTL_BASE (PERIPH_BASE +0x00011000) /**< Base address of module FLCTL registers */
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299 #define PCM_BASE (PERIPH_BASE +0x00010000) /**< Base address of module PCM registers */
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300 #define PMAP_BASE (PERIPH_BASE +0x00005000) /**< Base address of module PMAP registers */
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301 #define PSS_BASE (PERIPH_BASE +0x00010800) /**< Base address of module PSS registers */
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302 #define REF_A_BASE (PERIPH_BASE +0x00003000) /**< Base address of module REF_A registers */
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303 #define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /**< Base address of module RSTCTL registers */
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304 #define RTC_C_BASE (PERIPH_BASE +0x00004400) /**< Base address of module RTC_C registers */
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305 #define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /**< Base address of module RTC_C registers */
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306 #define SYSCTL_BASE (PERIPH_BASE2+0x00043000) /**< Base address of module SYSCTL registers */
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307 #define TIMER32_BASE (PERIPH_BASE +0x0000C000) /**< Base address of module TIMER32 registers */
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308 #define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /**< Base address of module TIMER_A0 registers */
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309 #define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /**< Base address of module TIMER_A1 registers */
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310 #define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /**< Base address of module TIMER_A2 registers */
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311 #define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /**< Base address of module TIMER_A3 registers */
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312 #define TLV_BASE ((uint32_t)0x00201000) /**< Base address of module TLV registers */
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313 #define WDT_A_BASE (PERIPH_BASE +0x00004800) /**< Base address of module WDT_A registers */
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316 /*@}*/ /* end of group MSP432P401R_MemoryMap */
\r
318 /******************************************************************************
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319 * Definitions for bit band access *
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320 ******************************************************************************/
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321 #define BITBAND_SRAM_BASE ((uint32_t)(0x22000000))
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322 #define BITBAND_PERI_BASE ((uint32_t)(0x42000000))
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324 /* SRAM allows 32 bit bit band access */
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325 #define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(uint32_t *)&x) - SRAM_BASE )*32 + b*4)))
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326 /* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */
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327 #define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(uint32_t *)&x) - PERIPH_BASE)*32 + b*4)))
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329 /******************************************************************************
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330 * Peripheral register definitions *
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331 ******************************************************************************/
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332 /** @addtogroup MSP432P401R_Peripherals MSP432P401R Peripherals
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333 MSP432P401R Device Specific Peripheral registers structures
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337 #if defined ( __CC_ARM )
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338 #pragma anon_unions
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342 /******************************************************************************
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344 ******************************************************************************/
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345 /** @addtogroup ADC14 MSP432P401R (ADC14)
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349 __IO uint32_t CTL0; /**< Control 0 Register */
\r
350 __IO uint32_t CTL1; /**< Control 1 Register */
\r
351 __IO uint32_t LO0; /**< Window Comparator Low Threshold 0 Register */
\r
352 __IO uint32_t HI0; /**< Window Comparator High Threshold 0 Register */
\r
353 __IO uint32_t LO1; /**< Window Comparator Low Threshold 1 Register */
\r
354 __IO uint32_t HI1; /**< Window Comparator High Threshold 1 Register */
\r
355 __IO uint32_t MCTL[32]; /**< Conversion Memory Control Register */
\r
356 __IO uint32_t MEM[32]; /**< Conversion Memory Register */
\r
357 uint32_t RESERVED0[9];
\r
358 __IO uint32_t IER0; /**< Interrupt Enable 0 Register */
\r
359 __IO uint32_t IER1; /**< Interrupt Enable 1 Register */
\r
360 __I uint32_t IFGR0; /**< Interrupt Flag 0 Register */
\r
361 __I uint32_t IFGR1; /**< Interrupt Flag 1 Register */
\r
362 __O uint32_t CLRIFGR0; /**< Clear Interrupt Flag 0 Register */
\r
363 __IO uint32_t CLRIFGR1; /**< Clear Interrupt Flag 1 Register */
\r
364 __IO uint32_t IV; /**< Interrupt Vector Register */
\r
367 /*@}*/ /* end of group ADC14 */
\r
370 /******************************************************************************
\r
372 ******************************************************************************/
\r
373 /** @addtogroup AES256 MSP432P401R (AES256)
\r
377 __IO uint16_t CTL0; /**< AES Accelerator Control Register 0 */
\r
378 __IO uint16_t CTL1; /**< AES Accelerator Control Register 1 */
\r
379 __IO uint16_t STAT; /**< AES Accelerator Status Register */
\r
380 __O uint16_t KEY; /**< AES Accelerator Key Register */
\r
381 __O uint16_t DIN; /**< AES Accelerator Data In Register */
\r
382 __O uint16_t DOUT; /**< AES Accelerator Data Out Register */
\r
383 __O uint16_t XDIN; /**< AES Accelerator XORed Data In Register */
\r
384 __O uint16_t XIN; /**< AES Accelerator XORed Data In Register */
\r
387 /*@}*/ /* end of group AES256 */
\r
390 /******************************************************************************
\r
392 ******************************************************************************/
\r
393 /** @addtogroup CAPTIO MSP432P401R (CAPTIO)
\r
397 uint16_t RESERVED0[7];
\r
398 __IO uint16_t CTL; /**< Capacitive Touch IO x Control Register */
\r
401 /*@}*/ /* end of group CAPTIO */
\r
404 /******************************************************************************
\r
406 ******************************************************************************/
\r
407 /** @addtogroup COMP_E MSP432P401R (COMP_E)
\r
411 __IO uint16_t CTL0; /**< Comparator Control Register 0 */
\r
412 __IO uint16_t CTL1; /**< Comparator Control Register 1 */
\r
413 __IO uint16_t CTL2; /**< Comparator Control Register 2 */
\r
414 __IO uint16_t CTL3; /**< Comparator Control Register 3 */
\r
415 uint16_t RESERVED0[2];
\r
416 __IO uint16_t INT; /**< Comparator Interrupt Control Register */
\r
417 __I uint16_t IV; /**< Comparator Interrupt Vector Word Register */
\r
420 /*@}*/ /* end of group COMP_E */
\r
423 /******************************************************************************
\r
425 ******************************************************************************/
\r
426 /** @addtogroup CRC32 MSP432P401R (CRC32)
\r
430 __IO uint16_t DI32; /**< Data Input for CRC32 Signature Computation */
\r
431 uint16_t RESERVED0;
\r
432 __IO uint16_t DIRB32; /**< Data In Reverse for CRC32 Computation */
\r
433 uint16_t RESERVED1;
\r
434 __IO uint16_t INIRES32_LO; /**< CRC32 Initialization and Result, lower 16 bits */
\r
435 __IO uint16_t INIRES32_HI; /**< CRC32 Initialization and Result, upper 16 bits */
\r
436 __IO uint16_t RESR32_LO; /**< CRC32 Result Reverse, lower 16 bits */
\r
437 __IO uint16_t RESR32_HI; /**< CRC32 Result Reverse, Upper 16 bits */
\r
438 __IO uint16_t DI16; /**< Data Input for CRC16 computation */
\r
439 uint16_t RESERVED2;
\r
440 __IO uint16_t DIRB16; /**< CRC16 Data In Reverse */
\r
441 uint16_t RESERVED3;
\r
442 __IO uint16_t INIRES16; /**< CRC16 Initialization and Result register */
\r
443 uint16_t RESERVED4[2];
\r
444 __IO uint16_t RESR16; /**< CRC16 Result Reverse */
\r
447 /*@}*/ /* end of group CRC32 */
\r
450 /******************************************************************************
\r
452 ******************************************************************************/
\r
453 /** @addtogroup CS MSP432P401R (CS)
\r
457 __IO uint32_t KEY; /**< Key Register */
\r
458 __IO uint32_t CTL0; /**< Control 0 Register */
\r
459 __IO uint32_t CTL1; /**< Control 1 Register */
\r
460 __IO uint32_t CTL2; /**< Control 2 Register */
\r
461 __IO uint32_t CTL3; /**< Control 3 Register */
\r
462 __IO uint32_t CTL4; /**< Control 4 Register */
\r
463 __IO uint32_t CTL5; /**< Control 5 Register */
\r
464 __IO uint32_t CTL6; /**< Control 6 Register */
\r
465 __IO uint32_t CTL7; /**< Control 7 Register */
\r
466 uint32_t RESERVED0[3];
\r
467 __IO uint32_t CLKEN; /**< Clock Enable Register */
\r
468 __I uint32_t STAT; /**< Status Register */
\r
469 uint32_t RESERVED1[2];
\r
470 __IO uint32_t IE; /**< Interrupt Enable Register */
\r
471 uint32_t RESERVED2;
\r
472 __I uint32_t IFG; /**< Interrupt Flag Register */
\r
473 uint32_t RESERVED3;
\r
474 __O uint32_t CLRIFG; /**< Clear Interrupt Flag Register */
\r
475 uint32_t RESERVED4;
\r
476 __O uint32_t SETIFG; /**< Set Interrupt Flag Register */
\r
477 uint32_t RESERVED5;
\r
478 __IO uint32_t DCOERCAL0; /**< DCO External Resistor Cailbration 0 Register */
\r
479 __IO uint32_t DCOERCAL1; /**< DCO External Resistor Calibration 1 Register */
\r
482 /*@}*/ /* end of group CS */
\r
484 /******************************************************************************
\r
486 ******************************************************************************/
\r
487 /** @addtogroup DIO MSP432P401R (DIO)
\r
492 __I uint16_t IN; /**< Port Pair Input */
\r
494 __I uint8_t IN_L; /**< Low Port Input */
\r
495 __I uint8_t IN_H; /**< High Port Input */
\r
499 __IO uint16_t OUT; /**< Port Pair Output */
\r
501 __IO uint8_t OUT_L; /**< Low Port Output */
\r
502 __IO uint8_t OUT_H; /**< High Port Output */
\r
506 __IO uint16_t DIR; /**< Port Pair Direction */
\r
508 __IO uint8_t DIR_L; /**< Low Port Direction */
\r
509 __IO uint8_t DIR_H; /**< High Port Direction */
\r
513 __IO uint16_t REN; /**< Port Pair Resistor Enable */
\r
515 __IO uint8_t REN_L; /**< Low Port Resistor Enable */
\r
516 __IO uint8_t REN_H; /**< High Port Resistor Enable */
\r
520 __IO uint16_t DS; /**< Port Pair Drive Strength */
\r
522 __IO uint8_t DS_L; /**< Low Port Drive Strength */
\r
523 __IO uint8_t DS_H; /**< High Port Drive Strength */
\r
527 __IO uint16_t SEL0; /**< Port Pair Select 0 */
\r
529 __IO uint8_t SEL0_L; /**< Low Port Select 0 */
\r
530 __IO uint8_t SEL0_H; /**< High Port Select 0 */
\r
534 __IO uint16_t SEL1; /**< Port Pair Select 1 */
\r
536 __IO uint8_t SEL1_L; /**< Low Port Select 1 */
\r
537 __IO uint8_t SEL1_H; /**< High Port Select 1 */
\r
540 __I uint16_t IV_L; /**< Low Port Interrupt Vector Value */
\r
541 uint16_t RESERVED0[3];
\r
543 __IO uint16_t SELC; /**< Port Pair Complement Select */
\r
545 __IO uint8_t SELC_L; /**< Low Port Complement Select */
\r
546 __IO uint8_t SELC_H; /**< High Port Complement Select */
\r
550 __IO uint16_t IES; /**< Port Pair Interrupt Edge Select */
\r
552 __IO uint8_t IES_L; /**< Low Port Interrupt Edge Select */
\r
553 __IO uint8_t IES_H; /**< High Port Interrupt Edge Select */
\r
557 __IO uint16_t IE; /**< Port Pair Interrupt Enable */
\r
559 __IO uint8_t IE_L; /**< Low Port Interrupt Enable */
\r
560 __IO uint8_t IE_H; /**< High Port Interrupt Enable */
\r
564 __IO uint16_t IFG; /**< Port Pair Interrupt Flag */
\r
566 __IO uint8_t IFG_L; /**< Low Port Interrupt Flag */
\r
567 __IO uint8_t IFG_H; /**< High Port Interrupt Flag */
\r
570 __I uint16_t IV_H; /**< High Port Interrupt Vector Value */
\r
571 } DIO_PORT_Interruptable_Type;
\r
575 __I uint16_t IN; /**< Port Pair Input */
\r
577 __I uint8_t IN_L; /**< Low Port Input */
\r
578 __I uint8_t IN_H; /**< High Port Input */
\r
582 __IO uint16_t OUT; /**< Port Pair Output */
\r
584 __IO uint8_t OUT_L; /**< Low Port Output */
\r
585 __IO uint8_t OUT_H; /**< High Port Output */
\r
589 __IO uint16_t DIR; /**< Port Pair Direction */
\r
591 __IO uint8_t DIR_L; /**< Low Port Direction */
\r
592 __IO uint8_t DIR_H; /**< High Port Direction */
\r
596 __IO uint16_t REN; /**< Port Pair Resistor Enable */
\r
598 __IO uint8_t REN_L; /**< Low Port Resistor Enable */
\r
599 __IO uint8_t REN_H; /**< High Port Resistor Enable */
\r
603 __IO uint16_t DS; /**< Port Pair Drive Strength */
\r
605 __IO uint8_t DS_L; /**< Low Port Drive Strength */
\r
606 __IO uint8_t DS_H; /**< High Port Drive Strength */
\r
610 __IO uint16_t SEL0; /**< Port Pair Select 0 */
\r
612 __IO uint8_t SEL0_L; /**< Low Port Select 0 */
\r
613 __IO uint8_t SEL0_H; /**< High Port Select 0 */
\r
617 __IO uint16_t SEL1; /**< Port Pair Select 1 */
\r
619 __IO uint8_t SEL1_L; /**< Low Port Select 1 */
\r
620 __IO uint8_t SEL1_H; /**< High Port Select 1 */
\r
623 uint16_t RESERVED0[4];
\r
625 __IO uint16_t SELC; /**< Port Pair Complement Select */
\r
627 __IO uint8_t SELC_L; /**< Low Port Complement Select */
\r
628 __IO uint8_t SELC_H; /**< High Port Complement Select */
\r
631 } DIO_PORT_Not_Interruptable_Type;
\r
635 __I uint8_t IN; /**< Port Input */
\r
637 __IO uint8_t OUT; /**< Port Output */
\r
639 __IO uint8_t DIR; /**< Port Direction */
\r
641 __IO uint8_t REN; /**< Port Resistor Enable */
\r
643 __IO uint8_t DS; /**< Port Drive Strength */
\r
645 __IO uint8_t SEL0; /**< Port Select 0 */
\r
647 __IO uint8_t SEL1; /**< Port Select 1 */
\r
649 __I uint16_t IV; /**< Port Interrupt Vector Value */
\r
650 uint8_t RESERVED7[6];
\r
651 __IO uint8_t SELC; /**< Port Complement Select */
\r
653 __IO uint8_t IES; /**< Port Interrupt Edge Select */
\r
655 __IO uint8_t IE; /**< Port Interrupt Enable */
\r
656 uint8_t RESERVED10;
\r
657 __IO uint8_t IFG; /**< Port Interrupt Flag */
\r
658 } DIO_PORT_Odd_Interruptable_Type;
\r
662 __I uint8_t IN; /**< Port Input */
\r
664 __IO uint8_t OUT; /**< Port Output */
\r
666 __IO uint8_t DIR; /**< Port Direction */
\r
668 __IO uint8_t REN; /**< Port Resistor Enable */
\r
670 __IO uint8_t DS; /**< Port Drive Strength */
\r
672 __IO uint8_t SEL0; /**< Port Select 0 */
\r
674 __IO uint8_t SEL1; /**< Port Select 1 */
\r
675 uint8_t RESERVED7[9];
\r
676 __IO uint8_t SELC; /**< Port Complement Select */
\r
678 __IO uint8_t IES; /**< Port Interrupt Edge Select */
\r
680 __IO uint8_t IE; /**< Port Interrupt Enable */
\r
681 uint8_t RESERVED10;
\r
682 __IO uint8_t IFG; /**< Port Interrupt Flag */
\r
683 __I uint16_t IV; /**< Port Interrupt Vector Value */
\r
684 } DIO_PORT_Even_Interruptable_Type;
\r
686 /*@}*/ /* end of group MSP432P401R_DIO */
\r
689 /******************************************************************************
\r
691 ******************************************************************************/
\r
692 /** @addtogroup DMA MSP432P401R (DMA)
\r
696 __I uint32_t DEVICE_CFG; /**< Device Configuration Status */
\r
697 __IO uint32_t SW_CHTRIG; /**< Software Channel Trigger Register */
\r
698 uint32_t RESERVED0[2];
\r
699 __IO uint32_t CH_SRCCFG[32]; /**< Channel n Source Configuration Register */
\r
700 uint32_t RESERVED1[28];
\r
701 __IO uint32_t INT1_SRCCFG; /**< Interrupt 1 Source Channel Configuration */
\r
702 __IO uint32_t INT2_SRCCFG; /**< Interrupt 2 Source Channel Configuration Register */
\r
703 __IO uint32_t INT3_SRCCFG; /**< Interrupt 3 Source Channel Configuration Register */
\r
704 uint32_t RESERVED2;
\r
705 __I uint32_t INT0_SRCFLG; /**< Interrupt 0 Source Channel Flag Register */
\r
706 __O uint32_t INT0_CLRFLG; /**< Interrupt 0 Source Channel Clear Flag Register */
\r
707 } DMA_Channel_Type;
\r
710 __I uint32_t STAT; /**< Status Register */
\r
711 __O uint32_t CFG; /**< Configuration Register */
\r
712 __IO uint32_t CTLBASE; /**< Channel Control Data Base Pointer Register */
\r
713 __I uint32_t ATLBASE; /**< Channel Alternate Control Data Base Pointer Register */
\r
714 __I uint32_t WAITSTAT; /**< Channel Wait on Request Status Register */
\r
715 __O uint32_t SWREQ; /**< Channel Software Request Register */
\r
716 __IO uint32_t USEBURSTSET; /**< Channel Useburst Set Register */
\r
717 __O uint32_t USEBURSTCLR; /**< Channel Useburst Clear Register */
\r
718 __IO uint32_t REQMASKSET; /**< Channel Request Mask Set Register */
\r
719 __O uint32_t REQMASKCLR; /**< Channel Request Mask Clear Register */
\r
720 __IO uint32_t ENASET; /**< Channel Enable Set Register */
\r
721 __O uint32_t ENACLR; /**< Channel Enable Clear Register */
\r
722 __IO uint32_t ALTSET; /**< Channel Primary-Alternate Set Register */
\r
723 __O uint32_t ALTCLR; /**< Channel Primary-Alternate Clear Register */
\r
724 __IO uint32_t PRIOSET; /**< Channel Priority Set Register */
\r
725 __O uint32_t PRIOCLR; /**< Channel Priority Clear Register */
\r
726 uint32_t RESERVED4[3];
\r
727 __IO uint32_t ERRCLR; /**< Bus Error Clear Register */
\r
728 } DMA_Control_Type;
\r
730 /*@}*/ /* end of group DMA */
\r
733 /******************************************************************************
\r
734 * EUSCI_A Registers
\r
735 ******************************************************************************/
\r
736 /** @addtogroup EUSCI_A MSP432P401R (EUSCI_A)
\r
740 __IO uint16_t CTLW0; /**< eUSCI_Ax Control Word Register 0 */
\r
741 __IO uint16_t CTLW1; /**< eUSCI_Ax Control Word Register 1 */
\r
742 uint16_t RESERVED0;
\r
743 __IO uint16_t BRW; /**< eUSCI_Ax Baud Rate Control Word Register */
\r
744 __IO uint16_t MCTLW; /**< eUSCI_Ax Modulation Control Word Register */
\r
745 __IO uint16_t STATW; /**< eUSCI_Ax Status Register */
\r
746 __I uint16_t RXBUF; /**< eUSCI_Ax Receive Buffer Register */
\r
747 __IO uint16_t TXBUF; /**< eUSCI_Ax Transmit Buffer Register */
\r
748 __IO uint16_t ABCTL; /**< eUSCI_Ax Auto Baud Rate Control Register */
\r
749 __IO uint16_t IRCTL; /**< eUSCI_Ax IrDA Control Word Register */
\r
750 uint16_t RESERVED1[3];
\r
751 __IO uint16_t IE; /**< eUSCI_Ax Interrupt Enable Register */
\r
752 __IO uint16_t IFG; /**< eUSCI_Ax Interrupt Flag Register */
\r
753 __I uint16_t IV; /**< eUSCI_Ax Interrupt Vector Register */
\r
756 /*@}*/ /* end of group EUSCI_A */
\r
758 /** @addtogroup EUSCI_A_SPI MSP432P401R (EUSCI_A_SPI)
\r
762 __IO uint16_t CTLW0; /**< eUSCI_Ax Control Word Register 0 */
\r
763 uint16_t RESERVED0[2];
\r
764 __IO uint16_t BRW; /**< eUSCI_Ax Bit Rate Control Register 1 */
\r
765 uint16_t RESERVED1;
\r
766 __IO uint16_t STATW;
\r
767 __I uint16_t RXBUF; /**< eUSCI_Ax Receive Buffer Register */
\r
768 __IO uint16_t TXBUF; /**< eUSCI_Ax Transmit Buffer Register */
\r
769 uint16_t RESERVED2[5];
\r
770 __IO uint16_t IE; /**< eUSCI_Ax Interrupt Enable Register */
\r
771 __IO uint16_t IFG; /**< eUSCI_Ax Interrupt Flag Register */
\r
772 __I uint16_t IV; /**< eUSCI_Ax Interrupt Vector Register */
\r
773 } EUSCI_A_SPI_Type;
\r
775 /*@}*/ /* end of group EUSCI_A_SPI */
\r
778 /******************************************************************************
\r
779 * EUSCI_B Registers
\r
780 ******************************************************************************/
\r
781 /** @addtogroup EUSCI_B MSP432P401R (EUSCI_B)
\r
785 __IO uint16_t CTLW0; /**< eUSCI_Bx Control Word Register 0 */
\r
786 __IO uint16_t CTLW1; /**< eUSCI_Bx Control Word Register 1 */
\r
787 uint16_t RESERVED0;
\r
788 __IO uint16_t BRW; /**< eUSCI_Bx Baud Rate Control Word Register */
\r
789 __IO uint16_t STATW; /**< eUSCI_Bx Status Register */
\r
790 __IO uint16_t TBCNT; /**< eUSCI_Bx Byte Counter Threshold Register */
\r
791 __I uint16_t RXBUF; /**< eUSCI_Bx Receive Buffer Register */
\r
792 __IO uint16_t TXBUF; /**< eUSCI_Bx Transmit Buffer Register */
\r
793 uint16_t RESERVED1[2];
\r
794 __IO uint16_t I2COA0; /**< eUSCI_Bx I2C Own Address 0 Register */
\r
795 __IO uint16_t I2COA1; /**< eUSCI_Bx I2C Own Address 1 Register */
\r
796 __IO uint16_t I2COA2; /**< eUSCI_Bx I2C Own Address 2 Register */
\r
797 __IO uint16_t I2COA3; /**< eUSCI_Bx I2C Own Address 3 Register */
\r
798 __I uint16_t ADDRX; /**< eUSCI_Bx I2C Received Address Register */
\r
799 __IO uint16_t ADDMASK; /**< eUSCI_Bx I2C Address Mask Register */
\r
800 __IO uint16_t I2CSA; /**< eUSCI_Bx I2C Slave Address Register */
\r
801 uint16_t RESERVED2[4];
\r
802 __IO uint16_t IE; /**< eUSCI_Bx Interrupt Enable Register */
\r
803 __IO uint16_t IFG; /**< eUSCI_Bx Interrupt Flag Register */
\r
804 __I uint16_t IV; /**< eUSCI_Bx Interrupt Vector Register */
\r
807 /*@}*/ /* end of group EUSCI_B */
\r
809 /** @addtogroup EUSCI_B_SPI MSP432P401R (EUSCI_B_SPI)
\r
813 __IO uint16_t CTLW0; /**< eUSCI_Bx Control Word Register 0 */
\r
814 uint16_t RESERVED0[2];
\r
815 __IO uint16_t BRW; /**< eUSCI_Bx Bit Rate Control Register 1 */
\r
816 __IO uint16_t STATW;
\r
817 uint16_t RESERVED1;
\r
818 __I uint16_t RXBUF; /**< eUSCI_Bx Receive Buffer Register */
\r
819 __IO uint16_t TXBUF; /**< eUSCI_Bx Transmit Buffer Register */
\r
820 uint16_t RESERVED2[13];
\r
821 __IO uint16_t IE; /**< eUSCI_Bx Interrupt Enable Register */
\r
822 __IO uint16_t IFG; /**< eUSCI_Bx Interrupt Flag Register */
\r
823 __I uint16_t IV; /**< eUSCI_Bx Interrupt Vector Register */
\r
824 } EUSCI_B_SPI_Type;
\r
826 /*@}*/ /* end of group EUSCI_B_SPI */
\r
829 /******************************************************************************
\r
831 ******************************************************************************/
\r
832 /** @addtogroup FLCTL MSP432P401R (FLCTL)
\r
836 __I uint32_t POWER_STAT; /**< Power Status Register */
\r
837 uint32_t RESERVED0[3];
\r
838 __IO uint32_t BANK0_RDCTL; /**< Bank0 Read Control Register */
\r
839 __IO uint32_t BANK1_RDCTL; /**< Bank1 Read Control Register */
\r
840 uint32_t RESERVED1[2];
\r
841 __IO uint32_t RDBRST_CTLSTAT; /**< Read Burst/Compare Control and Status Register */
\r
842 __IO uint32_t RDBRST_STARTADDR; /**< Read Burst/Compare Start Address Register */
\r
843 __IO uint32_t RDBRST_LEN; /**< Read Burst/Compare Length Register */
\r
844 uint32_t RESERVED2[4];
\r
845 __IO uint32_t RDBRST_FAILADDR; /**< Read Burst/Compare Fail Address Register */
\r
846 __IO uint32_t RDBRST_FAILCNT; /**< Read Burst/Compare Fail Count Register */
\r
847 uint32_t RESERVED3[3];
\r
848 __IO uint32_t PRG_CTLSTAT; /**< Program Control and Status Register */
\r
849 __IO uint32_t PRGBRST_CTLSTAT; /**< Program Burst Control and Status Register */
\r
850 __IO uint32_t PRGBRST_STARTADDR; /**< Program Burst Start Address Register */
\r
851 uint32_t RESERVED4;
\r
852 __IO uint32_t PRGBRST_DATA0_0; /**< Program Burst Data0 Register0 */
\r
853 __IO uint32_t PRGBRST_DATA0_1; /**< Program Burst Data0 Register1 */
\r
854 __IO uint32_t PRGBRST_DATA0_2; /**< Program Burst Data0 Register2 */
\r
855 __IO uint32_t PRGBRST_DATA0_3; /**< Program Burst Data0 Register3 */
\r
856 __IO uint32_t PRGBRST_DATA1_0; /**< Program Burst Data1 Register0 */
\r
857 __IO uint32_t PRGBRST_DATA1_1; /**< Program Burst Data1 Register1 */
\r
858 __IO uint32_t PRGBRST_DATA1_2; /**< Program Burst Data1 Register2 */
\r
859 __IO uint32_t PRGBRST_DATA1_3; /**< Program Burst Data1 Register3 */
\r
860 __IO uint32_t PRGBRST_DATA2_0; /**< Program Burst Data2 Register0 */
\r
861 __IO uint32_t PRGBRST_DATA2_1; /**< Program Burst Data2 Register1 */
\r
862 __IO uint32_t PRGBRST_DATA2_2; /**< Program Burst Data2 Register2 */
\r
863 __IO uint32_t PRGBRST_DATA2_3; /**< Program Burst Data2 Register3 */
\r
864 __IO uint32_t PRGBRST_DATA3_0; /**< Program Burst Data3 Register0 */
\r
865 __IO uint32_t PRGBRST_DATA3_1; /**< Program Burst Data3 Register1 */
\r
866 __IO uint32_t PRGBRST_DATA3_2; /**< Program Burst Data3 Register2 */
\r
867 __IO uint32_t PRGBRST_DATA3_3; /**< Program Burst Data3 Register3 */
\r
868 __IO uint32_t ERASE_CTLSTAT; /**< Erase Control and Status Register */
\r
869 __IO uint32_t ERASE_SECTADDR; /**< Erase Sector Address Register */
\r
870 uint32_t RESERVED5[2];
\r
871 __IO uint32_t BANK0_INFO_WEPROT; /**< Information Memory Bank0 Write/Erase Protection Register */
\r
872 __IO uint32_t BANK0_MAIN_WEPROT; /**< Main Memory Bank0 Write/Erase Protection Register */
\r
873 uint32_t RESERVED6[2];
\r
874 __IO uint32_t BANK1_INFO_WEPROT; /**< Information Memory Bank1 Write/Erase Protection Register */
\r
875 __IO uint32_t BANK1_MAIN_WEPROT; /**< Main Memory Bank1 Write/Erase Protection Register */
\r
876 uint32_t RESERVED7[2];
\r
877 __IO uint32_t BMRK_CTLSTAT; /**< Benchmark Control and Status Register */
\r
878 __IO uint32_t BMRK_IFETCH; /**< Benchmark Instruction Fetch Count Register */
\r
879 __IO uint32_t BMRK_DREAD; /**< Benchmark Data Read Count Register */
\r
880 __IO uint32_t BMRK_CMP; /**< Benchmark Count Compare Register */
\r
881 uint32_t RESERVED8[4];
\r
882 __IO uint32_t IFG; /**< Interrupt Flag Register */
\r
883 __IO uint32_t IE; /**< Interrupt Enable Register */
\r
884 __IO uint32_t CLRIFG; /**< Clear Interrupt Flag Register */
\r
885 __IO uint32_t SETIFG; /**< Set Interrupt Flag Register */
\r
886 __I uint32_t READ_TIMCTL; /**< Read Timing Control Register */
\r
887 __I uint32_t READMARGIN_TIMCTL; /**< Read Margin Timing Control Register */
\r
888 __I uint32_t PRGVER_TIMCTL; /**< Program Verify Timing Control Register */
\r
889 __I uint32_t ERSVER_TIMCTL; /**< Erase Verify Timing Control Register */
\r
890 __I uint32_t LKGVER_TIMCTL; /**< Leakage Verify Timing Control Register */
\r
891 __I uint32_t PROGRAM_TIMCTL; /**< Program Timing Control Register */
\r
892 __I uint32_t ERASE_TIMCTL; /**< Erase Timing Control Register */
\r
893 __I uint32_t MASSERASE_TIMCTL; /**< Mass Erase Timing Control Register */
\r
894 __I uint32_t BURSTPRG_TIMCTL; /**< Burst Program Timing Control Register */
\r
897 /*@}*/ /* end of group FLCTL */
\r
900 /******************************************************************************
\r
902 ******************************************************************************/
\r
903 /** @addtogroup PCM MSP432P401R (PCM)
\r
907 __IO uint32_t CTL0; /**< Control 0 Register */
\r
908 __IO uint32_t CTL1; /**< Control 1 Register */
\r
909 __IO uint32_t IE; /**< Interrupt Enable Register */
\r
910 __I uint32_t IFG; /**< Interrupt Flag Register */
\r
911 __O uint32_t CLRIFG; /**< Clear Interrupt Flag Register */
\r
914 /*@}*/ /* end of group PCM */
\r
916 /******************************************************************************
\r
918 ******************************************************************************/
\r
919 /** @addtogroup PMAP MSP432P401R (PMAP)
\r
923 __IO uint16_t KEYID;
\r
925 } PMAP_COMMON_Type;
\r
929 __IO uint16_t PMAP_REGISTER[4];
\r
931 __IO uint8_t PMAP_REGISTER0;
\r
932 __IO uint8_t PMAP_REGISTER1;
\r
933 __IO uint8_t PMAP_REGISTER2;
\r
934 __IO uint8_t PMAP_REGISTER3;
\r
935 __IO uint8_t PMAP_REGISTER4;
\r
936 __IO uint8_t PMAP_REGISTER5;
\r
937 __IO uint8_t PMAP_REGISTER6;
\r
938 __IO uint8_t PMAP_REGISTER7;
\r
941 } PMAP_REGISTER_Type;
\r
943 /*@}*/ /* end of group PMAP */
\r
946 /******************************************************************************
\r
948 ******************************************************************************/
\r
949 /** @addtogroup PSS MSP432P401R (PSS)
\r
953 __IO uint32_t KEY; /**< Key Register */
\r
954 __IO uint32_t CTL0; /**< Control 0 Register */
\r
955 uint32_t RESERVED0[11];
\r
956 __IO uint32_t IE; /**< Interrupt Enable Register */
\r
957 __I uint32_t IFG; /**< Interrupt Flag Register */
\r
958 __IO uint32_t CLRIFG; /**< Clear Interrupt Flag Register */
\r
961 /*@}*/ /* end of group PSS */
\r
964 /******************************************************************************
\r
966 ******************************************************************************/
\r
967 /** @addtogroup REF_A MSP432P401R (REF_A)
\r
971 __IO uint16_t CTL0; /**< REF Control Register 0 */
\r
974 /*@}*/ /* end of group REF_A */
\r
977 /******************************************************************************
\r
979 ******************************************************************************/
\r
980 /** @addtogroup RSTCTL MSP432P401R (RSTCTL)
\r
984 __IO uint32_t RESET_REQ; /**< Reset Request Register */
\r
985 __I uint32_t HARDRESET_STAT; /**< Hard Reset Status Register */
\r
986 __IO uint32_t HARDRESET_CLR; /**< Hard Reset Status Clear Register */
\r
987 __IO uint32_t HARDRESET_SET; /**< Hard Reset Status Set Register */
\r
988 __I uint32_t SOFTRESET_STAT; /**< Soft Reset Status Register */
\r
989 __IO uint32_t SOFTRESET_CLR; /**< Soft Reset Status Clear Register */
\r
990 __IO uint32_t SOFTRESET_SET; /**< Soft Reset Status Set Register */
\r
991 uint32_t RESERVED0[57];
\r
992 __I uint32_t PSSRESET_STAT; /**< PSS Reset Status Register */
\r
993 __IO uint32_t PSSRESET_CLR; /**< PSS Reset Status Clear Register */
\r
994 __I uint32_t PCMRESET_STAT; /**< PCM Reset Status Register */
\r
995 __IO uint32_t PCMRESET_CLR; /**< PCM Reset Status Clear Register */
\r
996 __I uint32_t PINRESET_STAT; /**< Pin Reset Status Register */
\r
997 __IO uint32_t PINRESET_CLR; /**< Pin Reset Status Clear Register */
\r
998 __I uint32_t REBOOTRESET_STAT; /**< Reboot Reset Status Register */
\r
999 __IO uint32_t REBOOTRESET_CLR; /**< Reboot Reset Status Clear Register */
\r
1000 __I uint32_t CSRESET_STAT; /**< CS Reset Status Register */
\r
1001 __IO uint32_t CSRESET_CLR; /**< CS Reset Status Clear Register */
\r
1004 /*@}*/ /* end of group RSTCTL */
\r
1007 /******************************************************************************
\r
1009 ******************************************************************************/
\r
1010 /** @addtogroup RTC_C MSP432P401R (RTC_C)
\r
1014 __IO uint16_t CTL0; /**< RTCCTL0 Register */
\r
1015 __IO uint16_t CTL13; /**< RTCCTL13 Register */
\r
1016 __IO uint16_t OCAL; /**< RTCOCAL Register */
\r
1017 __IO uint16_t TCMP; /**< RTCTCMP Register */
\r
1018 __IO uint16_t PS0CTL; /**< Real-Time Clock Prescale Timer 0 Control Register */
\r
1019 __IO uint16_t PS1CTL; /**< Real-Time Clock Prescale Timer 1 Control Register */
\r
1020 __IO uint16_t PS; /**< Real-Time Clock Prescale Timer Counter Register */
\r
1021 __I uint16_t IV; /**< Real-Time Clock Interrupt Vector Register */
\r
1022 __IO uint16_t TIM0; /**< RTCTIM0 Register ? Hexadecimal Format */
\r
1023 __IO uint16_t TIM1; /**< Real-Time Clock Hour, Day of Week */
\r
1024 __IO uint16_t DATE; /**< RTCDATE - Hexadecimal Format */
\r
1025 __IO uint16_t YEAR; /**< RTCYEAR Register ? Hexadecimal Format */
\r
1026 __IO uint16_t AMINHR; /**< RTCMINHR - Hexadecimal Format */
\r
1027 __IO uint16_t ADOWDAY; /**< RTCADOWDAY - Hexadecimal Format */
\r
1028 __IO uint16_t BIN2BCD; /**< Binary-to-BCD Conversion Register */
\r
1029 __IO uint16_t BCD2BIN; /**< BCD-to-Binary Conversion Register */
\r
1032 /*@}*/ /* end of group RTC_C */
\r
1034 /** @addtogroup RTC_C_BCD MSP432P401R (RTC_C_BCD)
\r
1038 uint16_t RESERVED0[8];
\r
1039 __IO uint16_t TIM0; /**< RTCTIM0 Register ? BCD Format */
\r
1040 __IO uint16_t TIM1; /**< RTCTIM1 Register ? BCD Format */
\r
1041 __IO uint16_t DATE; /**< Real-Time Clock Date - BCD Format */
\r
1042 __IO uint16_t YEAR; /**< RTCYEAR Register ? BCD Format */
\r
1043 __IO uint16_t AMINHR; /**< RTCMINHR - BCD Format */
\r
1044 __IO uint16_t ADOWDAY; /**< RTCADOWDAY - BCD Format */
\r
1047 /*@}*/ /* end of group RTC_C_BCD */
\r
1050 /******************************************************************************
\r
1051 * SYSCTL Registers
\r
1052 ******************************************************************************/
\r
1053 /** @addtogroup SYSCTL MSP432P401R (SYSCTL)
\r
1057 __IO uint32_t REBOOT_CTL; /**< Reboot Control Register */
\r
1058 __IO uint32_t NMI_CTLSTAT; /**< NMI Control and Status Register */
\r
1059 __IO uint32_t WDTRESET_CTL; /**< Watchdog Reset Control Register */
\r
1060 __IO uint32_t PERIHALT_CTL; /**< Peripheral Halt Control Register */
\r
1061 __I uint32_t SRAM_SIZE; /**< SRAM Size Register */
\r
1062 __IO uint32_t SRAM_BANKEN; /**< SRAM Bank Enable Register */
\r
1063 __IO uint32_t SRAM_BANKRET; /**< SRAM Bank Retention Control Register */
\r
1064 uint32_t RESERVED0;
\r
1065 __I uint32_t FLASH_SIZE; /**< Flash Size Register */
\r
1066 uint32_t RESERVED1[3];
\r
1067 __IO uint32_t DIO_GLTFLT_CTL; /**< Digital I/O Glitch Filter Control Register */
\r
1068 uint32_t RESERVED2[3];
\r
1069 __IO uint32_t SECDATA_UNLOCK; /**< IP Protected Secure Zone Data Access Unlock Register */
\r
1070 uint32_t RESERVED3[175];
\r
1071 __IO uint32_t CSYS_MASTER_UNLOCK; /**< Master Unlock Register */
\r
1072 __IO uint32_t BOOT_CTL; /**< Boot Control Register */
\r
1073 uint32_t RESERVED4[2];
\r
1074 __IO uint32_t SEC_CTL; /**< Security Control Register */
\r
1075 uint32_t RESERVED5[3];
\r
1076 __IO uint32_t SEC_STARTADDR0; /**< Security Zone 0 Start Address Register */
\r
1077 __IO uint32_t SEC_STARTADDR1; /**< Security Zone 1 Start Address Register */
\r
1078 __IO uint32_t SEC_STARTADDR2; /**< Security Zone 2 Start Address Register */
\r
1079 __IO uint32_t SEC_STARTADDR3; /**< Security Zone 3 Start Address Register */
\r
1080 __IO uint32_t SEC_SIZE0; /**< Security Zone 0 Size Register */
\r
1081 __IO uint32_t SEC_SIZE1; /**< Security Zone 1 Size Register */
\r
1082 __IO uint32_t SEC_SIZE2; /**< Security Zone 2 Size Register */
\r
1083 __IO uint32_t SEC_SIZE3; /**< Security Zone 3 Size Register */
\r
1084 __IO uint32_t ETW_CTL; /**< ETW Control Register */
\r
1085 __IO uint32_t FLASH_SIZECFG; /**< Flash Size Configuration Register */
\r
1086 __IO uint32_t SRAM_SIZECFG; /**< SRAM Size Configuration Register */
\r
1087 __IO uint32_t SRAM_NUMBANK; /**< SRAM NUM BANK Configuration Register */
\r
1088 __IO uint32_t TIMER_CFG; /**< Timer Configuration Register */
\r
1089 __IO uint32_t EUSCI_CFG; /**< eUSCI Configuration Register */
\r
1090 __IO uint32_t ADC_CFG; /**< ADC Configuration Register */
\r
1091 __IO uint32_t XTAL_CFG; /**< Crystal Oscillator Configuration Register */
\r
1092 __IO uint32_t BOC_CFG; /**< Bond Out Configuration Register */
\r
1096 __IO uint32_t MASTER_UNLOCK; /**< Master Unlock Register */
\r
1097 __IO uint32_t BOOTOVER_REQ[2]; /**< Boot Override Request Register */
\r
1098 __IO uint32_t BOOTOVER_ACK; /**< Boot Override Acknowledge Register */
\r
1099 __IO uint32_t RESET_REQ; /**< Reset Request Register */
\r
1100 __IO uint32_t RESET_STATOVER; /**< Reset Status and Override Register */
\r
1101 uint32_t RESERVED7[2];
\r
1102 __I uint32_t SYSTEM_STAT; /**< System Status Register */
\r
1103 } SYSCTL_Boot_Type;
\r
1105 /*@}*/ /* end of group SYSCTL */
\r
1108 /******************************************************************************
\r
1109 * Timer32 Registers
\r
1110 ******************************************************************************/
\r
1111 /** @addtogroup Timer32 MSP432P401R (Timer32)
\r
1115 __IO uint32_t LOAD; /**< Timer 1 Load Register */
\r
1116 __I uint32_t VALUE; /**< Timer 1 Current Value Register */
\r
1117 __IO uint32_t CONTROL; /**< Timer 1 Timer Control Register */
\r
1118 __O uint32_t INTCLR; /**< Timer 1 Interrupt Clear Register */
\r
1119 __I uint32_t RIS; /**< Timer 1 Raw Interrupt Status Register */
\r
1120 __I uint32_t MIS; /**< Timer 1 Interrupt Status Register */
\r
1121 __IO uint32_t BGLOAD; /**< Timer 1 Background Load Register */
\r
1124 /*@}*/ /* end of group Timer32 */
\r
1127 /******************************************************************************
\r
1128 * Timer_A Registers
\r
1129 ******************************************************************************/
\r
1130 /** @addtogroup Timer_A MSP432P401R (Timer_A)
\r
1134 __IO uint16_t CTL; /**< TimerAx Control Register */
\r
1135 __IO uint16_t CCTL[7]; /**< Timer_A Capture/Compare Control Register */
\r
1136 __IO uint16_t R; /**< TimerA register */
\r
1137 __IO uint16_t CCR[7]; /**< Timer_A Capture/Compare Register */
\r
1138 __IO uint16_t EX0; /**< TimerAx Expansion 0 Register */
\r
1139 uint16_t RESERVED0[6];
\r
1140 __I uint16_t IV; /**< TimerAx Interrupt Vector Register */
\r
1143 /*@}*/ /* end of group Timer_A */
\r
1146 /******************************************************************************
\r
1148 ******************************************************************************/
\r
1149 /** @addtogroup TLV MSP432P401R (TLV)
\r
1153 __I uint32_t TLV_CHECKSUM; /**< TLV Checksum */
\r
1154 __I uint32_t DEVICE_INFO_TAG; /**< Device Info Tag */
\r
1155 __I uint32_t DEVICE_INFO_LEN; /**< Device Info Length */
\r
1156 __I uint32_t DEVICE_ID; /**< Device ID */
\r
1157 __I uint32_t HWREV; /**< HW Revision */
\r
1158 __I uint32_t BCREV; /**< Boot Code Revision */
\r
1159 __I uint32_t ROM_DRVLIB_REV; /**< ROM Driver Library Revision */
\r
1160 __I uint32_t DIE_REC_TAG; /**< Die Record Tag */
\r
1161 __I uint32_t DIE_REC_LEN; /**< Die Record Length */
\r
1162 __I uint32_t DIE_XPOS; /**< Die X-Position */
\r
1163 __I uint32_t DIE_YPOS; /**< Die Y-Position */
\r
1164 __I uint32_t WAFER_ID; /**< Wafer ID */
\r
1165 __I uint32_t LOT_ID; /**< Lot ID */
\r
1166 __I uint32_t RESERVED0; /**< Reserved */
\r
1167 __I uint32_t RESERVED1; /**< Reserved */
\r
1168 __I uint32_t RESERVED2; /**< Reserved */
\r
1169 __I uint32_t TEST_RESULTS; /**< Test Results */
\r
1170 __I uint32_t CS_CAL_TAG; /**< Clock System Calibration Tag */
\r
1171 __I uint32_t CS_CAL_LEN; /**< Clock System Calibration Length */
\r
1172 __I uint32_t DCOIR_FCAL_RSEL04; /**< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
\r
1173 __I uint32_t DCOIR_FCAL_RSEL5; /**< DCO IR mode: Frequency calibration for DCORSEL 5 */
\r
1174 __I uint32_t DCOIR_MAXPOSTUNE_RSEL04; /**< DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */
\r
1175 __I uint32_t DCOIR_MAXNEGTUNE_RSEL04; /**< DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */
\r
1176 __I uint32_t DCOIR_MAXPOSTUNE_RSEL5; /**< DCO IR mode: Max Positive Tune for DCORSEL 5 */
\r
1177 __I uint32_t DCOIR_MAXNEGTUNE_RSEL5; /**< DCO IR mode: Max Negative Tune for DCORSEL 5 */
\r
1178 __I uint32_t DCOIR_CONSTK_RSEL04; /**< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
\r
1179 __I uint32_t DCOIR_CONSTK_RSEL5; /**< DCO IR mode: DCO Constant (K) for DCORSEL 5 */
\r
1180 __I uint32_t DCOER_FCAL_RSEL04; /**< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
\r
1181 __I uint32_t DCOER_FCAL_RSEL5; /**< DCO ER mode: Frequency calibration for DCORSEL 5 */
\r
1182 __I uint32_t DCOER_MAXPOSTUNE_RSEL04; /**< DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */
\r
1183 __I uint32_t DCOER_MAXNEGTUNE_RSEL04; /**< DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */
\r
1184 __I uint32_t DCOER_MAXPOSTUNE_RSEL5; /**< DCO ER mode: Max Positive Tune for DCORSEL 5 */
\r
1185 __I uint32_t DCOER_MAXNEGTUNE_RSEL5; /**< DCO ER mode: Max Negative Tune for DCORSEL 5 */
\r
1186 __I uint32_t DCOER_CONSTK_RSEL04; /**< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
\r
1187 __I uint32_t DCOER_CONSTK_RSEL5; /**< DCO ER mode: DCO Constant (K) for DCORSEL 5 */
\r
1188 __I uint32_t ADC14_CAL_TAG; /**< ADC14 Calibration Tag */
\r
1189 __I uint32_t ADC14_CAL_LEN; /**< ADC14 Calibration Length */
\r
1190 __I uint32_t ADC14_GF_EXTREF30C; /**< ADC14 Gain Factor for External Reference 30°C */
\r
1191 __I uint32_t ADC14_GF_EXTREF85C; /**< ADC14 Gain Factor for External Reference 85°C */
\r
1192 __I uint32_t ADC14_GF_BUF_EXTREF30C; /**< ADC14 Gain Factor for Buffered External Reference 30°C */
\r
1193 __I uint32_t ADC14_GF_BUF_EXTREF85C; /**< ADC14 Gain Factor for Buffered External Reference 85°C */
\r
1194 __I uint32_t ADC14_GF_BUF1P2V_INTREF30C_REFOUT0; /**< ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 0) */
\r
1195 __I uint32_t ADC14_GF_BUF1P2V_INTREF85C_REFOUT0; /**< ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 0) */
\r
1196 __I uint32_t ADC14_GF_BUF1P2V_INTREF30C_REFOUT1; /**< ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 1) */
\r
1197 __I uint32_t ADC14_GF_BUF1P2V_INTREF85C_REFOUT1; /**< ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 1) */
\r
1198 __I uint32_t ADC14_GF_BUF1P45V_INTREF30C_REFOUT0; /**< ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 0) */
\r
1199 __I uint32_t ADC14_GF_BUF1P45V_INTREF85C_REFOUT0; /**< ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 0) */
\r
1200 __I uint32_t ADC14_GF_BUF1P45V_INTREF30C_REFOUT1; /**< ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 1) */
\r
1201 __I uint32_t ADC14_GF_BUF1P45V_INTREF85C_REFOUT1; /**< ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 1) */
\r
1202 __I uint32_t ADC14_GF_BUF2P5V_INTREF30C_REFOUT0; /**< ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 0) */
\r
1203 __I uint32_t ADC14_GF_BUF2P5V_INTREF85C_REFOUT0; /**< ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 0) */
\r
1204 __I uint32_t ADC14_GF_BUF2P5V_INTREF30C_REFOUT1; /**< ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 1) */
\r
1205 __I uint32_t ADC14_GF_BUF2P5V_INTREF85C_REFOUT1; /**< ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 1) */
\r
1206 __I uint32_t ADC14_OFFSET_VRSEL_1; /**< ADC14 Offset (ADC14VRSEL = 1h) */
\r
1207 __I uint32_t ADC14_OFFSET_VRSEL_E; /**< ADC14 Offset (ADC14VRSEL = Eh) */
\r
1208 __I uint32_t ADC14_REF1P2V_TS30C; /**< ADC14 1.2V Reference Temp. Sensor 30°C */
\r
1209 __I uint32_t ADC14_REF1P2V_TS85C; /**< ADC14 1.2V Reference Temp. Sensor 85°C */
\r
1210 __I uint32_t ADC14_REF1P45V_TS30C; /**< ADC14 1.45V Reference Temp. Sensor 30°C */
\r
1211 __I uint32_t ADC14_REF1P45V_TS85C; /**< ADC14 1.45V Reference Temp. Sensor 85°C */
\r
1212 __I uint32_t ADC14_REF2P5V_TS30C; /**< ADC14 2.5V Reference Temp. Sensor 30°C */
\r
1213 __I uint32_t ADC14_REF2P5V_TS85C; /**< ADC14 2.5V Reference Temp. Sensor 85°C */
\r
1214 __I uint32_t REF_CAL_TAG; /**< REF Calibration Tag */
\r
1215 __I uint32_t REF_CAL_LEN; /**< REF Calibration Length */
\r
1216 __I uint32_t REF_1P2V; /**< REF 1.2V Reference */
\r
1217 __I uint32_t REF_1P45V; /**< REF 1.45V Reference */
\r
1218 __I uint32_t REF_2P5V; /**< REF 2.5V Reference */
\r
1219 __I uint32_t FLASH_INFO_TAG; /**< Flash Info Tag */
\r
1220 __I uint32_t FLASH_INFO_LEN; /**< Flash Info Length */
\r
1221 __I uint32_t FLASH_MAX_PROG_PULSES; /**< Flash Maximum Programming Pulses */
\r
1222 __I uint32_t FLASH_MAX_ERASE_PULSES; /**< Flash Maximum Erase Pulses */
\r
1223 __I uint32_t RANDOM_NUM_TAG; /**< 128-bit Random Number Tag */
\r
1224 __I uint32_t RANDOM_NUM_LEN; /**< 128-bit Random Number Length */
\r
1225 __I uint32_t RANDOM_NUM_1; /**< 32-bit Random Number 1 */
\r
1226 __I uint32_t RANDOM_NUM_2; /**< 32-bit Random Number 2 */
\r
1227 __I uint32_t RANDOM_NUM_3; /**< 32-bit Random Number 3 */
\r
1228 __I uint32_t RANDOM_NUM_4; /**< 32-bit Random Number 4 */
\r
1229 __I uint32_t BSL_CFG_TAG; /**< BSL Configuration Tag */
\r
1230 __I uint32_t BSL_CFG_LEN; /**< BSL Configuration Length */
\r
1231 __I uint32_t BSL_PERIPHIF_SEL; /**< BSL Peripheral Interface Selection */
\r
1232 __I uint32_t BSL_PORTIF_CFG_UART; /**< BSL Port Interface Configuration for UART */
\r
1233 __I uint32_t BSL_PORTIF_CFG_SPI; /**< BSL Port Interface Configuration for SPI */
\r
1234 __I uint32_t BSL_PORTIF_CFG_I2C; /**< BSL Port Interface Configuration for I2C */
\r
1235 __I uint32_t TLV_END; /**< TLV End Word */
\r
1238 /*@}*/ /* end of group TLV */
\r
1241 /******************************************************************************
\r
1243 ******************************************************************************/
\r
1244 /** @addtogroup WDT_A MSP432P401R (WDT_A)
\r
1248 uint16_t RESERVED0[6];
\r
1249 __IO uint16_t CTL; /**< Watchdog Timer Control Register */
\r
1252 /*@}*/ /* end of group WDT_A */
\r
1255 #if defined ( __CC_ARM )
\r
1256 #pragma no_anon_unions
\r
1259 /*@}*/ /* end of group MSP432P401R_Peripherals */
\r
1261 /******************************************************************************
\r
1262 * Peripheral declaration *
\r
1263 ******************************************************************************/
\r
1264 /** @addtogroup MSP432P401R_PeripheralDecl MSP432P401R Peripheral Declaration
\r
1268 #define ADC14 ((ADC14_Type *) ADC14_BASE)
\r
1269 #define AES256 ((AES256_Type *) AES256_BASE)
\r
1270 #define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE)
\r
1271 #define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE)
\r
1272 #define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE)
\r
1273 #define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE)
\r
1274 #define CRC32 ((CRC32_Type *) CRC32_BASE)
\r
1275 #define CS ((CS_Type *) CS_BASE)
\r
1276 #define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000))
\r
1277 #define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020))
\r
1278 #define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040))
\r
1279 #define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060))
\r
1280 #define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080))
\r
1281 #define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120))
\r
1282 #define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000))
\r
1283 #define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000))
\r
1284 #define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020))
\r
1285 #define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020))
\r
1286 #define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040))
\r
1287 #define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040))
\r
1288 #define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060))
\r
1289 #define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060))
\r
1290 #define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080))
\r
1291 #define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080))
\r
1292 #define DMA_Channel ((DMA_Channel_Type *) DMA_BASE)
\r
1293 #define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000))
\r
1294 #define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE)
\r
1295 #define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE)
\r
1296 #define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE)
\r
1297 #define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE)
\r
1298 #define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE)
\r
1299 #define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE)
\r
1300 #define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE)
\r
1301 #define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE)
\r
1302 #define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE)
\r
1303 #define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE)
\r
1304 #define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE)
\r
1305 #define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE)
\r
1306 #define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE)
\r
1307 #define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE)
\r
1308 #define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE)
\r
1309 #define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE)
\r
1310 #define FLCTL ((FLCTL_Type *) FLCTL_BASE)
\r
1311 #define PCM ((PCM_Type *) PCM_BASE)
\r
1312 #define PMAP ((PMAP_COMMON_Type*) PMAP_BASE)
\r
1313 #define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008))
\r
1314 #define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010))
\r
1315 #define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018))
\r
1316 #define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020))
\r
1317 #define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028))
\r
1318 #define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030))
\r
1319 #define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038))
\r
1320 #define PSS ((PSS_Type *) PSS_BASE)
\r
1321 #define REF_A ((REF_A_Type *) REF_A_BASE)
\r
1322 #define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE)
\r
1323 #define RTC_C ((RTC_C_Type *) RTC_C_BASE)
\r
1324 #define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE)
\r
1325 #define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE)
\r
1326 #define SYSCTL_Boot ((SYSCTL_Boot_Type *) (SYSCTL_BASE + 0x1000))
\r
1327 #define TIMER32_1 ((Timer32_Type *) TIMER32_BASE)
\r
1328 #define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020))
\r
1329 #define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE)
\r
1330 #define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE)
\r
1331 #define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE)
\r
1332 #define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE)
\r
1333 #define TLV ((TLV_Type *) TLV_BASE)
\r
1334 #define WDT_A ((WDT_A_Type *) WDT_A_BASE)
\r
1337 /*@}*/ /* end of group MSP432P401R_PeripheralDecl */
\r
1339 /*@}*/ /* end of group MSP432P401R_Definitions */
\r
1341 #endif /* __CMSIS_CONFIG__ */
\r
1343 /******************************************************************************
\r
1344 * Peripheral register control bits *
\r
1345 ******************************************************************************/
\r
1347 /******************************************************************************
\r
1349 ******************************************************************************/
\r
1350 /* ADC14_CTL0[SC] Bits */
\r
1351 #define ADC14_CTL0_SC_OFS ( 0) /**< ADC14SC Bit Offset */
\r
1352 #define ADC14_CTL0_SC ((uint32_t)0x00000001) /**< ADC14 start conversion */
\r
1353 /* ADC14_CTL0[ENC] Bits */
\r
1354 #define ADC14_CTL0_ENC_OFS ( 1) /**< ADC14ENC Bit Offset */
\r
1355 #define ADC14_CTL0_ENC ((uint32_t)0x00000002) /**< ADC14 enable conversion */
\r
1356 /* ADC14_CTL0[ON] Bits */
\r
1357 #define ADC14_CTL0_ON_OFS ( 4) /**< ADC14ON Bit Offset */
\r
1358 #define ADC14_CTL0_ON ((uint32_t)0x00000010) /**< ADC14 on */
\r
1359 /* ADC14_CTL0[MSC] Bits */
\r
1360 #define ADC14_CTL0_MSC_OFS ( 7) /**< ADC14MSC Bit Offset */
\r
1361 #define ADC14_CTL0_MSC ((uint32_t)0x00000080) /**< ADC14 multiple sample and conversion */
\r
1362 /* ADC14_CTL0[SHT0] Bits */
\r
1363 #define ADC14_CTL0_SHT0_OFS ( 8) /**< ADC14SHT0 Bit Offset */
\r
1364 #define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /**< ADC14SHT0 Bit Mask */
\r
1365 #define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /**< SHT0 Bit 0 */
\r
1366 #define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /**< SHT0 Bit 1 */
\r
1367 #define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /**< SHT0 Bit 2 */
\r
1368 #define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /**< SHT0 Bit 3 */
\r
1369 #define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /**< 4 */
\r
1370 #define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /**< 8 */
\r
1371 #define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /**< 16 */
\r
1372 #define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /**< 32 */
\r
1373 #define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /**< 64 */
\r
1374 #define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /**< 96 */
\r
1375 #define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /**< 128 */
\r
1376 #define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /**< 192 */
\r
1377 #define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /**< 4 */
\r
1378 #define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /**< 8 */
\r
1379 #define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /**< 16 */
\r
1380 #define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /**< 32 */
\r
1381 #define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /**< 64 */
\r
1382 #define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /**< 96 */
\r
1383 #define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /**< 128 */
\r
1384 #define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /**< 192 */
\r
1385 /* ADC14_CTL0[SHT1] Bits */
\r
1386 #define ADC14_CTL0_SHT1_OFS (12) /**< ADC14SHT1 Bit Offset */
\r
1387 #define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /**< ADC14SHT1 Bit Mask */
\r
1388 #define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /**< SHT1 Bit 0 */
\r
1389 #define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /**< SHT1 Bit 1 */
\r
1390 #define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /**< SHT1 Bit 2 */
\r
1391 #define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /**< SHT1 Bit 3 */
\r
1392 #define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /**< 4 */
\r
1393 #define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /**< 8 */
\r
1394 #define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /**< 16 */
\r
1395 #define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /**< 32 */
\r
1396 #define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /**< 64 */
\r
1397 #define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /**< 96 */
\r
1398 #define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /**< 128 */
\r
1399 #define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /**< 192 */
\r
1400 #define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /**< 4 */
\r
1401 #define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /**< 8 */
\r
1402 #define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /**< 16 */
\r
1403 #define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /**< 32 */
\r
1404 #define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /**< 64 */
\r
1405 #define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /**< 96 */
\r
1406 #define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /**< 128 */
\r
1407 #define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /**< 192 */
\r
1408 /* ADC14_CTL0[BUSY] Bits */
\r
1409 #define ADC14_CTL0_BUSY_OFS (16) /**< ADC14BUSY Bit Offset */
\r
1410 #define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /**< ADC14 busy */
\r
1411 /* ADC14_CTL0[CONSEQ] Bits */
\r
1412 #define ADC14_CTL0_CONSEQ_OFS (17) /**< ADC14CONSEQ Bit Offset */
\r
1413 #define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /**< ADC14CONSEQ Bit Mask */
\r
1414 #define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /**< CONSEQ Bit 0 */
\r
1415 #define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /**< CONSEQ Bit 1 */
\r
1416 #define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /**< Single-channel, single-conversion */
\r
1417 #define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /**< Sequence-of-channels */
\r
1418 #define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /**< Repeat-single-channel */
\r
1419 #define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /**< Repeat-sequence-of-channels */
\r
1420 /* ADC14_CTL0[SSEL] Bits */
\r
1421 #define ADC14_CTL0_SSEL_OFS (19) /**< ADC14SSEL Bit Offset */
\r
1422 #define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /**< ADC14SSEL Bit Mask */
\r
1423 #define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /**< SSEL Bit 0 */
\r
1424 #define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /**< SSEL Bit 1 */
\r
1425 #define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /**< SSEL Bit 2 */
\r
1426 #define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /**< MODCLK */
\r
1427 #define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /**< SYSCLK */
\r
1428 #define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /**< ACLK */
\r
1429 #define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /**< MCLK */
\r
1430 #define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /**< SMCLK */
\r
1431 #define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /**< HSMCLK */
\r
1432 #define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /**< MODCLK */
\r
1433 #define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /**< SYSCLK */
\r
1434 #define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /**< ACLK */
\r
1435 #define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /**< MCLK */
\r
1436 #define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /**< SMCLK */
\r
1437 #define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /**< HSMCLK */
\r
1438 /* ADC14_CTL0[DIV] Bits */
\r
1439 #define ADC14_CTL0_DIV_OFS (22) /**< ADC14DIV Bit Offset */
\r
1440 #define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /**< ADC14DIV Bit Mask */
\r
1441 #define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /**< DIV Bit 0 */
\r
1442 #define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /**< DIV Bit 1 */
\r
1443 #define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /**< DIV Bit 2 */
\r
1444 #define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /**< /1 */
\r
1445 #define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /**< /2 */
\r
1446 #define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /**< /3 */
\r
1447 #define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /**< /4 */
\r
1448 #define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /**< /5 */
\r
1449 #define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /**< /6 */
\r
1450 #define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /**< /7 */
\r
1451 #define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /**< /8 */
\r
1452 #define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /**< /1 */
\r
1453 #define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /**< /2 */
\r
1454 #define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /**< /3 */
\r
1455 #define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /**< /4 */
\r
1456 #define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /**< /5 */
\r
1457 #define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /**< /6 */
\r
1458 #define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /**< /7 */
\r
1459 #define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /**< /8 */
\r
1460 /* ADC14_CTL0[ISSH] Bits */
\r
1461 #define ADC14_CTL0_ISSH_OFS (25) /**< ADC14ISSH Bit Offset */
\r
1462 #define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /**< ADC14 invert signal sample-and-hold */
\r
1463 /* ADC14_CTL0[SHP] Bits */
\r
1464 #define ADC14_CTL0_SHP_OFS (26) /**< ADC14SHP Bit Offset */
\r
1465 #define ADC14_CTL0_SHP ((uint32_t)0x04000000) /**< ADC14 sample-and-hold pulse-mode select */
\r
1466 /* ADC14_CTL0[SHS] Bits */
\r
1467 #define ADC14_CTL0_SHS_OFS (27) /**< ADC14SHS Bit Offset */
\r
1468 #define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /**< ADC14SHS Bit Mask */
\r
1469 #define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /**< SHS Bit 0 */
\r
1470 #define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /**< SHS Bit 1 */
\r
1471 #define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /**< SHS Bit 2 */
\r
1472 #define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /**< ADC14SC bit */
\r
1473 #define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /**< See device-specific data sheet for source */
\r
1474 #define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /**< See device-specific data sheet for source */
\r
1475 #define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /**< See device-specific data sheet for source */
\r
1476 #define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /**< See device-specific data sheet for source */
\r
1477 #define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /**< See device-specific data sheet for source */
\r
1478 #define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /**< See device-specific data sheet for source */
\r
1479 #define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /**< See device-specific data sheet for source */
\r
1480 /* ADC14_CTL0[PDIV] Bits */
\r
1481 #define ADC14_CTL0_PDIV_OFS (30) /**< ADC14PDIV Bit Offset */
\r
1482 #define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /**< ADC14PDIV Bit Mask */
\r
1483 #define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /**< PDIV Bit 0 */
\r
1484 #define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /**< PDIV Bit 1 */
\r
1485 #define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /**< Predivide by 1 */
\r
1486 #define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /**< Predivide by 4 */
\r
1487 #define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /**< Predivide by 32 */
\r
1488 #define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /**< Predivide by 64 */
\r
1489 #define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /**< Predivide by 1 */
\r
1490 #define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /**< Predivide by 4 */
\r
1491 #define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /**< Predivide by 32 */
\r
1492 #define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /**< Predivide by 64 */
\r
1493 /* ADC14_CTL1[PWRMD] Bits */
\r
1494 #define ADC14_CTL1_PWRMD_OFS ( 0) /**< ADC14PWRMD Bit Offset */
\r
1495 #define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /**< ADC14PWRMD Bit Mask */
\r
1496 #define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /**< PWRMD Bit 0 */
\r
1497 #define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /**< PWRMD Bit 1 */
\r
1498 #define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /**< Regular power mode for use with any resolution setting. Sample rate can be up */
\r
1500 #define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /**< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate */
\r
1501 /* must not exceed 200 ksps. */
\r
1502 /* ADC14_CTL1[REFBURST] Bits */
\r
1503 #define ADC14_CTL1_REFBURST_OFS ( 2) /**< ADC14REFBURST Bit Offset */
\r
1504 #define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /**< ADC14 reference buffer burst */
\r
1505 /* ADC14_CTL1[DF] Bits */
\r
1506 #define ADC14_CTL1_DF_OFS ( 3) /**< ADC14DF Bit Offset */
\r
1507 #define ADC14_CTL1_DF ((uint32_t)0x00000008) /**< ADC14 data read-back format */
\r
1508 /* ADC14_CTL1[RES] Bits */
\r
1509 #define ADC14_CTL1_RES_OFS ( 4) /**< ADC14RES Bit Offset */
\r
1510 #define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /**< ADC14RES Bit Mask */
\r
1511 #define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /**< RES Bit 0 */
\r
1512 #define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /**< RES Bit 1 */
\r
1513 #define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /**< 8 bit (9 clock cycle conversion time) */
\r
1514 #define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /**< 10 bit (11 clock cycle conversion time) */
\r
1515 #define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /**< 12 bit (14 clock cycle conversion time) */
\r
1516 #define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /**< 14 bit (16 clock cycle conversion time) */
\r
1517 #define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /**< 8 bit (9 clock cycle conversion time) */
\r
1518 #define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /**< 10 bit (11 clock cycle conversion time) */
\r
1519 #define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /**< 12 bit (14 clock cycle conversion time) */
\r
1520 #define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /**< 14 bit (16 clock cycle conversion time) */
\r
1521 /* ADC14_CTL1[CSTARTADD] Bits */
\r
1522 #define ADC14_CTL1_CSTARTADD_OFS (16) /**< ADC14CSTARTADD Bit Offset */
\r
1523 #define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /**< ADC14CSTARTADD Bit Mask */
\r
1524 /* ADC14_CTL1[BATMAP] Bits */
\r
1525 #define ADC14_CTL1_BATMAP_OFS (22) /**< ADC14BATMAP Bit Offset */
\r
1526 #define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /**< Controls 1/2 AVCC ADC input channel selection */
\r
1527 /* ADC14_CTL1[TCMAP] Bits */
\r
1528 #define ADC14_CTL1_TCMAP_OFS (23) /**< ADC14TCMAP Bit Offset */
\r
1529 #define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /**< Controls temperature sensor ADC input channel selection */
\r
1530 /* ADC14_CTL1[CH0MAP] Bits */
\r
1531 #define ADC14_CTL1_CH0MAP_OFS (24) /**< ADC14CH0MAP Bit Offset */
\r
1532 #define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /**< Controls internal channel 0 selection to ADC input channel MAX-2 */
\r
1533 /* ADC14_CTL1[CH1MAP] Bits */
\r
1534 #define ADC14_CTL1_CH1MAP_OFS (25) /**< ADC14CH1MAP Bit Offset */
\r
1535 #define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /**< Controls internal channel 1 selection to ADC input channel MAX-3 */
\r
1536 /* ADC14_CTL1[CH2MAP] Bits */
\r
1537 #define ADC14_CTL1_CH2MAP_OFS (26) /**< ADC14CH2MAP Bit Offset */
\r
1538 #define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /**< Controls internal channel 2 selection to ADC input channel MAX-4 */
\r
1539 /* ADC14_CTL1[CH3MAP] Bits */
\r
1540 #define ADC14_CTL1_CH3MAP_OFS (27) /**< ADC14CH3MAP Bit Offset */
\r
1541 #define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /**< Controls internal channel 3 selection to ADC input channel MAX-5 */
\r
1542 /* ADC14_LO0[LO0] Bits */
\r
1543 #define ADC14_LO0_LO0_OFS ( 0) /**< ADC14LO0 Bit Offset */
\r
1544 #define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /**< ADC14LO0 Bit Mask */
\r
1545 /* ADC14_HI0[HI0] Bits */
\r
1546 #define ADC14_HI0_HI0_OFS ( 0) /**< ADC14HI0 Bit Offset */
\r
1547 #define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /**< ADC14HI0 Bit Mask */
\r
1548 /* ADC14_LO1[LO1] Bits */
\r
1549 #define ADC14_LO1_LO1_OFS ( 0) /**< ADC14LO1 Bit Offset */
\r
1550 #define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /**< ADC14LO1 Bit Mask */
\r
1551 /* ADC14_HI1[HI1] Bits */
\r
1552 #define ADC14_HI1_HI1_OFS ( 0) /**< ADC14HI1 Bit Offset */
\r
1553 #define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /**< ADC14HI1 Bit Mask */
\r
1554 /* ADC14_MCTLN[INCH] Bits */
\r
1555 #define ADC14_MCTLN_INCH_OFS ( 0) /**< ADC14INCH Bit Offset */
\r
1556 #define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /**< ADC14INCH Bit Mask */
\r
1557 #define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /**< INCH Bit 0 */
\r
1558 #define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /**< INCH Bit 1 */
\r
1559 #define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /**< INCH Bit 2 */
\r
1560 #define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /**< INCH Bit 3 */
\r
1561 #define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /**< INCH Bit 4 */
\r
1562 #define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /**< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
\r
1563 #define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /**< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
\r
1564 #define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /**< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
\r
1565 #define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /**< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
\r
1566 #define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /**< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
\r
1567 #define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /**< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
\r
1568 #define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /**< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
\r
1569 #define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /**< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
\r
1570 #define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /**< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
\r
1571 #define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /**< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
\r
1572 #define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /**< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
\r
1573 #define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /**< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
\r
1574 #define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /**< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
\r
1575 #define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /**< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
\r
1576 #define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /**< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
\r
1577 #define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /**< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
\r
1578 #define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /**< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
\r
1579 #define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /**< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
\r
1580 #define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /**< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
\r
1581 #define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /**< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
\r
1582 #define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /**< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
\r
1583 #define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /**< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
\r
1584 #define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /**< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
\r
1585 #define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /**< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
\r
1586 #define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /**< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
\r
1587 #define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /**< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
\r
1588 #define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /**< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
\r
1589 #define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /**< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
\r
1590 #define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /**< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
\r
1591 #define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /**< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
\r
1592 #define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /**< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
\r
1593 #define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /**< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
\r
1594 /* ADC14_MCTLN[EOS] Bits */
\r
1595 #define ADC14_MCTLN_EOS_OFS ( 7) /**< ADC14EOS Bit Offset */
\r
1596 #define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /**< End of sequence */
\r
1597 /* ADC14_MCTLN[VRSEL] Bits */
\r
1598 #define ADC14_MCTLN_VRSEL_OFS ( 8) /**< ADC14VRSEL Bit Offset */
\r
1599 #define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /**< ADC14VRSEL Bit Mask */
\r
1600 #define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /**< VRSEL Bit 0 */
\r
1601 #define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /**< VRSEL Bit 1 */
\r
1602 #define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /**< VRSEL Bit 2 */
\r
1603 #define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /**< VRSEL Bit 3 */
\r
1604 #define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /**< V(R+) = AVCC, V(R-) = AVSS */
\r
1605 #define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /**< V(R+) = VREF buffered, V(R-) = AVSS */
\r
1606 #define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /**< V(R+) = VeREF+, V(R-) = VeREF- */
\r
1607 #define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /**< V(R+) = VeREF+ buffered, V(R-) = VeREF */
\r
1608 /* ADC14_MCTLN[DIF] Bits */
\r
1609 #define ADC14_MCTLN_DIF_OFS (13) /**< ADC14DIF Bit Offset */
\r
1610 #define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /**< Differential mode */
\r
1611 /* ADC14_MCTLN[WINC] Bits */
\r
1612 #define ADC14_MCTLN_WINC_OFS (14) /**< ADC14WINC Bit Offset */
\r
1613 #define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /**< Comparator window enable */
\r
1614 /* ADC14_MCTLN[WINCTH] Bits */
\r
1615 #define ADC14_MCTLN_WINCTH_OFS (15) /**< ADC14WINCTH Bit Offset */
\r
1616 #define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /**< Window comparator threshold register selection */
\r
1617 /* ADC14_MEMN[CONVRES] Bits */
\r
1618 #define ADC14_MEMN_CONVRES_OFS ( 0) /**< Conversion_Results Bit Offset */
\r
1619 #define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /**< Conversion_Results Bit Mask */
\r
1620 /* ADC14_IER0[IE0] Bits */
\r
1621 #define ADC14_IER0_IE0_OFS ( 0) /**< ADC14IE0 Bit Offset */
\r
1622 #define ADC14_IER0_IE0 ((uint32_t)0x00000001) /**< Interrupt enable */
\r
1623 /* ADC14_IER0[IE1] Bits */
\r
1624 #define ADC14_IER0_IE1_OFS ( 1) /**< ADC14IE1 Bit Offset */
\r
1625 #define ADC14_IER0_IE1 ((uint32_t)0x00000002) /**< Interrupt enable */
\r
1626 /* ADC14_IER0[IE2] Bits */
\r
1627 #define ADC14_IER0_IE2_OFS ( 2) /**< ADC14IE2 Bit Offset */
\r
1628 #define ADC14_IER0_IE2 ((uint32_t)0x00000004) /**< Interrupt enable */
\r
1629 /* ADC14_IER0[IE3] Bits */
\r
1630 #define ADC14_IER0_IE3_OFS ( 3) /**< ADC14IE3 Bit Offset */
\r
1631 #define ADC14_IER0_IE3 ((uint32_t)0x00000008) /**< Interrupt enable */
\r
1632 /* ADC14_IER0[IE4] Bits */
\r
1633 #define ADC14_IER0_IE4_OFS ( 4) /**< ADC14IE4 Bit Offset */
\r
1634 #define ADC14_IER0_IE4 ((uint32_t)0x00000010) /**< Interrupt enable */
\r
1635 /* ADC14_IER0[IE5] Bits */
\r
1636 #define ADC14_IER0_IE5_OFS ( 5) /**< ADC14IE5 Bit Offset */
\r
1637 #define ADC14_IER0_IE5 ((uint32_t)0x00000020) /**< Interrupt enable */
\r
1638 /* ADC14_IER0[IE6] Bits */
\r
1639 #define ADC14_IER0_IE6_OFS ( 6) /**< ADC14IE6 Bit Offset */
\r
1640 #define ADC14_IER0_IE6 ((uint32_t)0x00000040) /**< Interrupt enable */
\r
1641 /* ADC14_IER0[IE7] Bits */
\r
1642 #define ADC14_IER0_IE7_OFS ( 7) /**< ADC14IE7 Bit Offset */
\r
1643 #define ADC14_IER0_IE7 ((uint32_t)0x00000080) /**< Interrupt enable */
\r
1644 /* ADC14_IER0[IE8] Bits */
\r
1645 #define ADC14_IER0_IE8_OFS ( 8) /**< ADC14IE8 Bit Offset */
\r
1646 #define ADC14_IER0_IE8 ((uint32_t)0x00000100) /**< Interrupt enable */
\r
1647 /* ADC14_IER0[IE9] Bits */
\r
1648 #define ADC14_IER0_IE9_OFS ( 9) /**< ADC14IE9 Bit Offset */
\r
1649 #define ADC14_IER0_IE9 ((uint32_t)0x00000200) /**< Interrupt enable */
\r
1650 /* ADC14_IER0[IE10] Bits */
\r
1651 #define ADC14_IER0_IE10_OFS (10) /**< ADC14IE10 Bit Offset */
\r
1652 #define ADC14_IER0_IE10 ((uint32_t)0x00000400) /**< Interrupt enable */
\r
1653 /* ADC14_IER0[IE11] Bits */
\r
1654 #define ADC14_IER0_IE11_OFS (11) /**< ADC14IE11 Bit Offset */
\r
1655 #define ADC14_IER0_IE11 ((uint32_t)0x00000800) /**< Interrupt enable */
\r
1656 /* ADC14_IER0[IE12] Bits */
\r
1657 #define ADC14_IER0_IE12_OFS (12) /**< ADC14IE12 Bit Offset */
\r
1658 #define ADC14_IER0_IE12 ((uint32_t)0x00001000) /**< Interrupt enable */
\r
1659 /* ADC14_IER0[IE13] Bits */
\r
1660 #define ADC14_IER0_IE13_OFS (13) /**< ADC14IE13 Bit Offset */
\r
1661 #define ADC14_IER0_IE13 ((uint32_t)0x00002000) /**< Interrupt enable */
\r
1662 /* ADC14_IER0[IE14] Bits */
\r
1663 #define ADC14_IER0_IE14_OFS (14) /**< ADC14IE14 Bit Offset */
\r
1664 #define ADC14_IER0_IE14 ((uint32_t)0x00004000) /**< Interrupt enable */
\r
1665 /* ADC14_IER0[IE15] Bits */
\r
1666 #define ADC14_IER0_IE15_OFS (15) /**< ADC14IE15 Bit Offset */
\r
1667 #define ADC14_IER0_IE15 ((uint32_t)0x00008000) /**< Interrupt enable */
\r
1668 /* ADC14_IER0[IE16] Bits */
\r
1669 #define ADC14_IER0_IE16_OFS (16) /**< ADC14IE16 Bit Offset */
\r
1670 #define ADC14_IER0_IE16 ((uint32_t)0x00010000) /**< Interrupt enable */
\r
1671 /* ADC14_IER0[IE17] Bits */
\r
1672 #define ADC14_IER0_IE17_OFS (17) /**< ADC14IE17 Bit Offset */
\r
1673 #define ADC14_IER0_IE17 ((uint32_t)0x00020000) /**< Interrupt enable */
\r
1674 /* ADC14_IER0[IE19] Bits */
\r
1675 #define ADC14_IER0_IE19_OFS (19) /**< ADC14IE19 Bit Offset */
\r
1676 #define ADC14_IER0_IE19 ((uint32_t)0x00080000) /**< Interrupt enable */
\r
1677 /* ADC14_IER0[IE18] Bits */
\r
1678 #define ADC14_IER0_IE18_OFS (18) /**< ADC14IE18 Bit Offset */
\r
1679 #define ADC14_IER0_IE18 ((uint32_t)0x00040000) /**< Interrupt enable */
\r
1680 /* ADC14_IER0[IE20] Bits */
\r
1681 #define ADC14_IER0_IE20_OFS (20) /**< ADC14IE20 Bit Offset */
\r
1682 #define ADC14_IER0_IE20 ((uint32_t)0x00100000) /**< Interrupt enable */
\r
1683 /* ADC14_IER0[IE21] Bits */
\r
1684 #define ADC14_IER0_IE21_OFS (21) /**< ADC14IE21 Bit Offset */
\r
1685 #define ADC14_IER0_IE21 ((uint32_t)0x00200000) /**< Interrupt enable */
\r
1686 /* ADC14_IER0[IE22] Bits */
\r
1687 #define ADC14_IER0_IE22_OFS (22) /**< ADC14IE22 Bit Offset */
\r
1688 #define ADC14_IER0_IE22 ((uint32_t)0x00400000) /**< Interrupt enable */
\r
1689 /* ADC14_IER0[IE23] Bits */
\r
1690 #define ADC14_IER0_IE23_OFS (23) /**< ADC14IE23 Bit Offset */
\r
1691 #define ADC14_IER0_IE23 ((uint32_t)0x00800000) /**< Interrupt enable */
\r
1692 /* ADC14_IER0[IE24] Bits */
\r
1693 #define ADC14_IER0_IE24_OFS (24) /**< ADC14IE24 Bit Offset */
\r
1694 #define ADC14_IER0_IE24 ((uint32_t)0x01000000) /**< Interrupt enable */
\r
1695 /* ADC14_IER0[IE25] Bits */
\r
1696 #define ADC14_IER0_IE25_OFS (25) /**< ADC14IE25 Bit Offset */
\r
1697 #define ADC14_IER0_IE25 ((uint32_t)0x02000000) /**< Interrupt enable */
\r
1698 /* ADC14_IER0[IE26] Bits */
\r
1699 #define ADC14_IER0_IE26_OFS (26) /**< ADC14IE26 Bit Offset */
\r
1700 #define ADC14_IER0_IE26 ((uint32_t)0x04000000) /**< Interrupt enable */
\r
1701 /* ADC14_IER0[IE27] Bits */
\r
1702 #define ADC14_IER0_IE27_OFS (27) /**< ADC14IE27 Bit Offset */
\r
1703 #define ADC14_IER0_IE27 ((uint32_t)0x08000000) /**< Interrupt enable */
\r
1704 /* ADC14_IER0[IE28] Bits */
\r
1705 #define ADC14_IER0_IE28_OFS (28) /**< ADC14IE28 Bit Offset */
\r
1706 #define ADC14_IER0_IE28 ((uint32_t)0x10000000) /**< Interrupt enable */
\r
1707 /* ADC14_IER0[IE29] Bits */
\r
1708 #define ADC14_IER0_IE29_OFS (29) /**< ADC14IE29 Bit Offset */
\r
1709 #define ADC14_IER0_IE29 ((uint32_t)0x20000000) /**< Interrupt enable */
\r
1710 /* ADC14_IER0[IE30] Bits */
\r
1711 #define ADC14_IER0_IE30_OFS (30) /**< ADC14IE30 Bit Offset */
\r
1712 #define ADC14_IER0_IE30 ((uint32_t)0x40000000) /**< Interrupt enable */
\r
1713 /* ADC14_IER0[IE31] Bits */
\r
1714 #define ADC14_IER0_IE31_OFS (31) /**< ADC14IE31 Bit Offset */
\r
1715 #define ADC14_IER0_IE31 ((uint32_t)0x80000000) /**< Interrupt enable */
\r
1716 /* ADC14_IER1[INIE] Bits */
\r
1717 #define ADC14_IER1_INIE_OFS ( 1) /**< ADC14INIE Bit Offset */
\r
1718 #define ADC14_IER1_INIE ((uint32_t)0x00000002) /**< Interrupt enable for ADC14MEMx within comparator window */
\r
1719 /* ADC14_IER1[LOIE] Bits */
\r
1720 #define ADC14_IER1_LOIE_OFS ( 2) /**< ADC14LOIE Bit Offset */
\r
1721 #define ADC14_IER1_LOIE ((uint32_t)0x00000004) /**< Interrupt enable for ADC14MEMx below comparator window */
\r
1722 /* ADC14_IER1[HIIE] Bits */
\r
1723 #define ADC14_IER1_HIIE_OFS ( 3) /**< ADC14HIIE Bit Offset */
\r
1724 #define ADC14_IER1_HIIE ((uint32_t)0x00000008) /**< Interrupt enable for ADC14MEMx above comparator window */
\r
1725 /* ADC14_IER1[OVIE] Bits */
\r
1726 #define ADC14_IER1_OVIE_OFS ( 4) /**< ADC14OVIE Bit Offset */
\r
1727 #define ADC14_IER1_OVIE ((uint32_t)0x00000010) /**< ADC14MEMx overflow-interrupt enable */
\r
1728 /* ADC14_IER1[TOVIE] Bits */
\r
1729 #define ADC14_IER1_TOVIE_OFS ( 5) /**< ADC14TOVIE Bit Offset */
\r
1730 #define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /**< ADC14 conversion-time-overflow interrupt enable */
\r
1731 /* ADC14_IER1[RDYIE] Bits */
\r
1732 #define ADC14_IER1_RDYIE_OFS ( 6) /**< ADC14RDYIE Bit Offset */
\r
1733 #define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /**< ADC14 local buffered reference ready interrupt enable */
\r
1734 /* ADC14_IFGR0[IFG0] Bits */
\r
1735 #define ADC14_IFGR0_IFG0_OFS ( 0) /**< ADC14IFG0 Bit Offset */
\r
1736 #define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /**< ADC14MEM0 interrupt flag */
\r
1737 /* ADC14_IFGR0[IFG1] Bits */
\r
1738 #define ADC14_IFGR0_IFG1_OFS ( 1) /**< ADC14IFG1 Bit Offset */
\r
1739 #define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /**< ADC14MEM1 interrupt flag */
\r
1740 /* ADC14_IFGR0[IFG2] Bits */
\r
1741 #define ADC14_IFGR0_IFG2_OFS ( 2) /**< ADC14IFG2 Bit Offset */
\r
1742 #define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /**< ADC14MEM2 interrupt flag */
\r
1743 /* ADC14_IFGR0[IFG3] Bits */
\r
1744 #define ADC14_IFGR0_IFG3_OFS ( 3) /**< ADC14IFG3 Bit Offset */
\r
1745 #define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /**< ADC14MEM3 interrupt flag */
\r
1746 /* ADC14_IFGR0[IFG4] Bits */
\r
1747 #define ADC14_IFGR0_IFG4_OFS ( 4) /**< ADC14IFG4 Bit Offset */
\r
1748 #define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /**< ADC14MEM4 interrupt flag */
\r
1749 /* ADC14_IFGR0[IFG5] Bits */
\r
1750 #define ADC14_IFGR0_IFG5_OFS ( 5) /**< ADC14IFG5 Bit Offset */
\r
1751 #define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /**< ADC14MEM5 interrupt flag */
\r
1752 /* ADC14_IFGR0[IFG6] Bits */
\r
1753 #define ADC14_IFGR0_IFG6_OFS ( 6) /**< ADC14IFG6 Bit Offset */
\r
1754 #define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /**< ADC14MEM6 interrupt flag */
\r
1755 /* ADC14_IFGR0[IFG7] Bits */
\r
1756 #define ADC14_IFGR0_IFG7_OFS ( 7) /**< ADC14IFG7 Bit Offset */
\r
1757 #define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /**< ADC14MEM7 interrupt flag */
\r
1758 /* ADC14_IFGR0[IFG8] Bits */
\r
1759 #define ADC14_IFGR0_IFG8_OFS ( 8) /**< ADC14IFG8 Bit Offset */
\r
1760 #define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /**< ADC14MEM8 interrupt flag */
\r
1761 /* ADC14_IFGR0[IFG9] Bits */
\r
1762 #define ADC14_IFGR0_IFG9_OFS ( 9) /**< ADC14IFG9 Bit Offset */
\r
1763 #define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /**< ADC14MEM9 interrupt flag */
\r
1764 /* ADC14_IFGR0[IFG10] Bits */
\r
1765 #define ADC14_IFGR0_IFG10_OFS (10) /**< ADC14IFG10 Bit Offset */
\r
1766 #define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /**< ADC14MEM10 interrupt flag */
\r
1767 /* ADC14_IFGR0[IFG11] Bits */
\r
1768 #define ADC14_IFGR0_IFG11_OFS (11) /**< ADC14IFG11 Bit Offset */
\r
1769 #define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /**< ADC14MEM11 interrupt flag */
\r
1770 /* ADC14_IFGR0[IFG12] Bits */
\r
1771 #define ADC14_IFGR0_IFG12_OFS (12) /**< ADC14IFG12 Bit Offset */
\r
1772 #define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /**< ADC14MEM12 interrupt flag */
\r
1773 /* ADC14_IFGR0[IFG13] Bits */
\r
1774 #define ADC14_IFGR0_IFG13_OFS (13) /**< ADC14IFG13 Bit Offset */
\r
1775 #define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /**< ADC14MEM13 interrupt flag */
\r
1776 /* ADC14_IFGR0[IFG14] Bits */
\r
1777 #define ADC14_IFGR0_IFG14_OFS (14) /**< ADC14IFG14 Bit Offset */
\r
1778 #define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /**< ADC14MEM14 interrupt flag */
\r
1779 /* ADC14_IFGR0[IFG15] Bits */
\r
1780 #define ADC14_IFGR0_IFG15_OFS (15) /**< ADC14IFG15 Bit Offset */
\r
1781 #define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /**< ADC14MEM15 interrupt flag */
\r
1782 /* ADC14_IFGR0[IFG16] Bits */
\r
1783 #define ADC14_IFGR0_IFG16_OFS (16) /**< ADC14IFG16 Bit Offset */
\r
1784 #define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /**< ADC14MEM16 interrupt flag */
\r
1785 /* ADC14_IFGR0[IFG17] Bits */
\r
1786 #define ADC14_IFGR0_IFG17_OFS (17) /**< ADC14IFG17 Bit Offset */
\r
1787 #define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /**< ADC14MEM17 interrupt flag */
\r
1788 /* ADC14_IFGR0[IFG18] Bits */
\r
1789 #define ADC14_IFGR0_IFG18_OFS (18) /**< ADC14IFG18 Bit Offset */
\r
1790 #define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /**< ADC14MEM18 interrupt flag */
\r
1791 /* ADC14_IFGR0[IFG19] Bits */
\r
1792 #define ADC14_IFGR0_IFG19_OFS (19) /**< ADC14IFG19 Bit Offset */
\r
1793 #define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /**< ADC14MEM19 interrupt flag */
\r
1794 /* ADC14_IFGR0[IFG20] Bits */
\r
1795 #define ADC14_IFGR0_IFG20_OFS (20) /**< ADC14IFG20 Bit Offset */
\r
1796 #define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /**< ADC14MEM20 interrupt flag */
\r
1797 /* ADC14_IFGR0[IFG21] Bits */
\r
1798 #define ADC14_IFGR0_IFG21_OFS (21) /**< ADC14IFG21 Bit Offset */
\r
1799 #define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /**< ADC14MEM21 interrupt flag */
\r
1800 /* ADC14_IFGR0[IFG22] Bits */
\r
1801 #define ADC14_IFGR0_IFG22_OFS (22) /**< ADC14IFG22 Bit Offset */
\r
1802 #define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /**< ADC14MEM22 interrupt flag */
\r
1803 /* ADC14_IFGR0[IFG23] Bits */
\r
1804 #define ADC14_IFGR0_IFG23_OFS (23) /**< ADC14IFG23 Bit Offset */
\r
1805 #define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /**< ADC14MEM23 interrupt flag */
\r
1806 /* ADC14_IFGR0[IFG24] Bits */
\r
1807 #define ADC14_IFGR0_IFG24_OFS (24) /**< ADC14IFG24 Bit Offset */
\r
1808 #define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /**< ADC14MEM24 interrupt flag */
\r
1809 /* ADC14_IFGR0[IFG25] Bits */
\r
1810 #define ADC14_IFGR0_IFG25_OFS (25) /**< ADC14IFG25 Bit Offset */
\r
1811 #define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /**< ADC14MEM25 interrupt flag */
\r
1812 /* ADC14_IFGR0[IFG26] Bits */
\r
1813 #define ADC14_IFGR0_IFG26_OFS (26) /**< ADC14IFG26 Bit Offset */
\r
1814 #define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /**< ADC14MEM26 interrupt flag */
\r
1815 /* ADC14_IFGR0[IFG27] Bits */
\r
1816 #define ADC14_IFGR0_IFG27_OFS (27) /**< ADC14IFG27 Bit Offset */
\r
1817 #define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /**< ADC14MEM27 interrupt flag */
\r
1818 /* ADC14_IFGR0[IFG28] Bits */
\r
1819 #define ADC14_IFGR0_IFG28_OFS (28) /**< ADC14IFG28 Bit Offset */
\r
1820 #define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /**< ADC14MEM28 interrupt flag */
\r
1821 /* ADC14_IFGR0[IFG29] Bits */
\r
1822 #define ADC14_IFGR0_IFG29_OFS (29) /**< ADC14IFG29 Bit Offset */
\r
1823 #define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /**< ADC14MEM29 interrupt flag */
\r
1824 /* ADC14_IFGR0[IFG30] Bits */
\r
1825 #define ADC14_IFGR0_IFG30_OFS (30) /**< ADC14IFG30 Bit Offset */
\r
1826 #define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /**< ADC14MEM30 interrupt flag */
\r
1827 /* ADC14_IFGR0[IFG31] Bits */
\r
1828 #define ADC14_IFGR0_IFG31_OFS (31) /**< ADC14IFG31 Bit Offset */
\r
1829 #define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /**< ADC14MEM31 interrupt flag */
\r
1830 /* ADC14_IFGR1[INIFG] Bits */
\r
1831 #define ADC14_IFGR1_INIFG_OFS ( 1) /**< ADC14INIFG Bit Offset */
\r
1832 #define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /**< Interrupt flag for ADC14MEMx within comparator window */
\r
1833 /* ADC14_IFGR1[LOIFG] Bits */
\r
1834 #define ADC14_IFGR1_LOIFG_OFS ( 2) /**< ADC14LOIFG Bit Offset */
\r
1835 #define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /**< Interrupt flag for ADC14MEMx below comparator window */
\r
1836 /* ADC14_IFGR1[HIIFG] Bits */
\r
1837 #define ADC14_IFGR1_HIIFG_OFS ( 3) /**< ADC14HIIFG Bit Offset */
\r
1838 #define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /**< Interrupt flag for ADC14MEMx above comparator window */
\r
1839 /* ADC14_IFGR1[OVIFG] Bits */
\r
1840 #define ADC14_IFGR1_OVIFG_OFS ( 4) /**< ADC14OVIFG Bit Offset */
\r
1841 #define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /**< ADC14MEMx overflow interrupt flag */
\r
1842 /* ADC14_IFGR1[TOVIFG] Bits */
\r
1843 #define ADC14_IFGR1_TOVIFG_OFS ( 5) /**< ADC14TOVIFG Bit Offset */
\r
1844 #define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /**< ADC14 conversion time overflow interrupt flag */
\r
1845 /* ADC14_IFGR1[RDYIFG] Bits */
\r
1846 #define ADC14_IFGR1_RDYIFG_OFS ( 6) /**< ADC14RDYIFG Bit Offset */
\r
1847 #define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /**< ADC14 local buffered reference ready interrupt flag */
\r
1848 /* ADC14_CLRIFGR0[CLRIFG0] Bits */
\r
1849 #define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /**< CLRADC14IFG0 Bit Offset */
\r
1850 #define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /**< clear ADC14IFG0 */
\r
1851 /* ADC14_CLRIFGR0[CLRIFG1] Bits */
\r
1852 #define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /**< CLRADC14IFG1 Bit Offset */
\r
1853 #define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /**< clear ADC14IFG1 */
\r
1854 /* ADC14_CLRIFGR0[CLRIFG2] Bits */
\r
1855 #define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /**< CLRADC14IFG2 Bit Offset */
\r
1856 #define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /**< clear ADC14IFG2 */
\r
1857 /* ADC14_CLRIFGR0[CLRIFG3] Bits */
\r
1858 #define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /**< CLRADC14IFG3 Bit Offset */
\r
1859 #define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /**< clear ADC14IFG3 */
\r
1860 /* ADC14_CLRIFGR0[CLRIFG4] Bits */
\r
1861 #define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /**< CLRADC14IFG4 Bit Offset */
\r
1862 #define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /**< clear ADC14IFG4 */
\r
1863 /* ADC14_CLRIFGR0[CLRIFG5] Bits */
\r
1864 #define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /**< CLRADC14IFG5 Bit Offset */
\r
1865 #define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /**< clear ADC14IFG5 */
\r
1866 /* ADC14_CLRIFGR0[CLRIFG6] Bits */
\r
1867 #define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /**< CLRADC14IFG6 Bit Offset */
\r
1868 #define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /**< clear ADC14IFG6 */
\r
1869 /* ADC14_CLRIFGR0[CLRIFG7] Bits */
\r
1870 #define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /**< CLRADC14IFG7 Bit Offset */
\r
1871 #define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /**< clear ADC14IFG7 */
\r
1872 /* ADC14_CLRIFGR0[CLRIFG8] Bits */
\r
1873 #define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /**< CLRADC14IFG8 Bit Offset */
\r
1874 #define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /**< clear ADC14IFG8 */
\r
1875 /* ADC14_CLRIFGR0[CLRIFG9] Bits */
\r
1876 #define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /**< CLRADC14IFG9 Bit Offset */
\r
1877 #define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /**< clear ADC14IFG9 */
\r
1878 /* ADC14_CLRIFGR0[CLRIFG10] Bits */
\r
1879 #define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /**< CLRADC14IFG10 Bit Offset */
\r
1880 #define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /**< clear ADC14IFG10 */
\r
1881 /* ADC14_CLRIFGR0[CLRIFG11] Bits */
\r
1882 #define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /**< CLRADC14IFG11 Bit Offset */
\r
1883 #define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /**< clear ADC14IFG11 */
\r
1884 /* ADC14_CLRIFGR0[CLRIFG12] Bits */
\r
1885 #define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /**< CLRADC14IFG12 Bit Offset */
\r
1886 #define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /**< clear ADC14IFG12 */
\r
1887 /* ADC14_CLRIFGR0[CLRIFG13] Bits */
\r
1888 #define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /**< CLRADC14IFG13 Bit Offset */
\r
1889 #define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /**< clear ADC14IFG13 */
\r
1890 /* ADC14_CLRIFGR0[CLRIFG14] Bits */
\r
1891 #define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /**< CLRADC14IFG14 Bit Offset */
\r
1892 #define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /**< clear ADC14IFG14 */
\r
1893 /* ADC14_CLRIFGR0[CLRIFG15] Bits */
\r
1894 #define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /**< CLRADC14IFG15 Bit Offset */
\r
1895 #define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /**< clear ADC14IFG15 */
\r
1896 /* ADC14_CLRIFGR0[CLRIFG16] Bits */
\r
1897 #define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /**< CLRADC14IFG16 Bit Offset */
\r
1898 #define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /**< clear ADC14IFG16 */
\r
1899 /* ADC14_CLRIFGR0[CLRIFG17] Bits */
\r
1900 #define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /**< CLRADC14IFG17 Bit Offset */
\r
1901 #define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /**< clear ADC14IFG17 */
\r
1902 /* ADC14_CLRIFGR0[CLRIFG18] Bits */
\r
1903 #define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /**< CLRADC14IFG18 Bit Offset */
\r
1904 #define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /**< clear ADC14IFG18 */
\r
1905 /* ADC14_CLRIFGR0[CLRIFG19] Bits */
\r
1906 #define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /**< CLRADC14IFG19 Bit Offset */
\r
1907 #define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /**< clear ADC14IFG19 */
\r
1908 /* ADC14_CLRIFGR0[CLRIFG20] Bits */
\r
1909 #define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /**< CLRADC14IFG20 Bit Offset */
\r
1910 #define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /**< clear ADC14IFG20 */
\r
1911 /* ADC14_CLRIFGR0[CLRIFG21] Bits */
\r
1912 #define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /**< CLRADC14IFG21 Bit Offset */
\r
1913 #define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /**< clear ADC14IFG21 */
\r
1914 /* ADC14_CLRIFGR0[CLRIFG22] Bits */
\r
1915 #define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /**< CLRADC14IFG22 Bit Offset */
\r
1916 #define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /**< clear ADC14IFG22 */
\r
1917 /* ADC14_CLRIFGR0[CLRIFG23] Bits */
\r
1918 #define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /**< CLRADC14IFG23 Bit Offset */
\r
1919 #define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /**< clear ADC14IFG23 */
\r
1920 /* ADC14_CLRIFGR0[CLRIFG24] Bits */
\r
1921 #define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /**< CLRADC14IFG24 Bit Offset */
\r
1922 #define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /**< clear ADC14IFG24 */
\r
1923 /* ADC14_CLRIFGR0[CLRIFG25] Bits */
\r
1924 #define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /**< CLRADC14IFG25 Bit Offset */
\r
1925 #define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /**< clear ADC14IFG25 */
\r
1926 /* ADC14_CLRIFGR0[CLRIFG26] Bits */
\r
1927 #define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /**< CLRADC14IFG26 Bit Offset */
\r
1928 #define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /**< clear ADC14IFG26 */
\r
1929 /* ADC14_CLRIFGR0[CLRIFG27] Bits */
\r
1930 #define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /**< CLRADC14IFG27 Bit Offset */
\r
1931 #define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /**< clear ADC14IFG27 */
\r
1932 /* ADC14_CLRIFGR0[CLRIFG28] Bits */
\r
1933 #define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /**< CLRADC14IFG28 Bit Offset */
\r
1934 #define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /**< clear ADC14IFG28 */
\r
1935 /* ADC14_CLRIFGR0[CLRIFG29] Bits */
\r
1936 #define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /**< CLRADC14IFG29 Bit Offset */
\r
1937 #define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /**< clear ADC14IFG29 */
\r
1938 /* ADC14_CLRIFGR0[CLRIFG30] Bits */
\r
1939 #define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /**< CLRADC14IFG30 Bit Offset */
\r
1940 #define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /**< clear ADC14IFG30 */
\r
1941 /* ADC14_CLRIFGR0[CLRIFG31] Bits */
\r
1942 #define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /**< CLRADC14IFG31 Bit Offset */
\r
1943 #define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /**< clear ADC14IFG31 */
\r
1944 /* ADC14_CLRIFGR1[CLRINIFG] Bits */
\r
1945 #define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /**< CLRADC14INIFG Bit Offset */
\r
1946 #define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /**< clear ADC14INIFG */
\r
1947 /* ADC14_CLRIFGR1[CLRLOIFG] Bits */
\r
1948 #define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /**< CLRADC14LOIFG Bit Offset */
\r
1949 #define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /**< clear ADC14LOIFG */
\r
1950 /* ADC14_CLRIFGR1[CLRHIIFG] Bits */
\r
1951 #define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /**< CLRADC14HIIFG Bit Offset */
\r
1952 #define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /**< clear ADC14HIIFG */
\r
1953 /* ADC14_CLRIFGR1[CLROVIFG] Bits */
\r
1954 #define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /**< CLRADC14OVIFG Bit Offset */
\r
1955 #define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /**< clear ADC14OVIFG */
\r
1956 /* ADC14_CLRIFGR1[CLRTOVIFG] Bits */
\r
1957 #define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /**< CLRADC14TOVIFG Bit Offset */
\r
1958 #define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /**< clear ADC14TOVIFG */
\r
1959 /* ADC14_CLRIFGR1[CLRRDYIFG] Bits */
\r
1960 #define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /**< CLRADC14RDYIFG Bit Offset */
\r
1961 #define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /**< clear ADC14RDYIFG */
\r
1964 /******************************************************************************
\r
1966 ******************************************************************************/
\r
1967 /* AES256_CTL0[OP] Bits */
\r
1968 #define AES256_CTL0_OP_OFS ( 0) /**< AESOPx Bit Offset */
\r
1969 #define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /**< AESOPx Bit Mask */
\r
1970 #define AES256_CTL0_OP0 ((uint16_t)0x0001) /**< OP Bit 0 */
\r
1971 #define AES256_CTL0_OP1 ((uint16_t)0x0002) /**< OP Bit 1 */
\r
1972 #define AES256_CTL0_OP_0 ((uint16_t)0x0000) /**< Encryption */
\r
1973 #define AES256_CTL0_OP_1 ((uint16_t)0x0001) /**< Decryption. The provided key is the same key used for encryption */
\r
1974 #define AES256_CTL0_OP_2 ((uint16_t)0x0002) /**< Generate first round key required for decryption */
\r
1975 #define AES256_CTL0_OP_3 ((uint16_t)0x0003) /**< Decryption. The provided key is the first round key required for decryption */
\r
1976 /* AES256_CTL0[KL] Bits */
\r
1977 #define AES256_CTL0_KL_OFS ( 2) /**< AESKLx Bit Offset */
\r
1978 #define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /**< AESKLx Bit Mask */
\r
1979 #define AES256_CTL0_KL0 ((uint16_t)0x0004) /**< KL Bit 0 */
\r
1980 #define AES256_CTL0_KL1 ((uint16_t)0x0008) /**< KL Bit 1 */
\r
1981 #define AES256_CTL0_KL_0 ((uint16_t)0x0000) /**< AES128. The key size is 128 bit */
\r
1982 #define AES256_CTL0_KL_1 ((uint16_t)0x0004) /**< AES192. The key size is 192 bit. */
\r
1983 #define AES256_CTL0_KL_2 ((uint16_t)0x0008) /**< AES256. The key size is 256 bit */
\r
1984 #define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /**< AES128. The key size is 128 bit */
\r
1985 #define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /**< AES192. The key size is 192 bit. */
\r
1986 #define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /**< AES256. The key size is 256 bit */
\r
1987 /* AES256_CTL0[CM] Bits */
\r
1988 #define AES256_CTL0_CM_OFS ( 5) /**< AESCMx Bit Offset */
\r
1989 #define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /**< AESCMx Bit Mask */
\r
1990 #define AES256_CTL0_CM0 ((uint16_t)0x0020) /**< CM Bit 0 */
\r
1991 #define AES256_CTL0_CM1 ((uint16_t)0x0040) /**< CM Bit 1 */
\r
1992 #define AES256_CTL0_CM_0 ((uint16_t)0x0000) /**< ECB */
\r
1993 #define AES256_CTL0_CM_1 ((uint16_t)0x0020) /**< CBC */
\r
1994 #define AES256_CTL0_CM_2 ((uint16_t)0x0040) /**< OFB */
\r
1995 #define AES256_CTL0_CM_3 ((uint16_t)0x0060) /**< CFB */
\r
1996 #define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /**< ECB */
\r
1997 #define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /**< CBC */
\r
1998 #define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /**< OFB */
\r
1999 #define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /**< CFB */
\r
2000 /* AES256_CTL0[SWRST] Bits */
\r
2001 #define AES256_CTL0_SWRST_OFS ( 7) /**< AESSWRST Bit Offset */
\r
2002 #define AES256_CTL0_SWRST ((uint16_t)0x0080) /**< AES software reset */
\r
2003 /* AES256_CTL0[RDYIFG] Bits */
\r
2004 #define AES256_CTL0_RDYIFG_OFS ( 8) /**< AESRDYIFG Bit Offset */
\r
2005 #define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /**< AES ready interrupt flag */
\r
2006 /* AES256_CTL0[ERRFG] Bits */
\r
2007 #define AES256_CTL0_ERRFG_OFS (11) /**< AESERRFG Bit Offset */
\r
2008 #define AES256_CTL0_ERRFG ((uint16_t)0x0800) /**< AES error flag */
\r
2009 /* AES256_CTL0[RDYIE] Bits */
\r
2010 #define AES256_CTL0_RDYIE_OFS (12) /**< AESRDYIE Bit Offset */
\r
2011 #define AES256_CTL0_RDYIE ((uint16_t)0x1000) /**< AES ready interrupt enable */
\r
2012 /* AES256_CTL0[CMEN] Bits */
\r
2013 #define AES256_CTL0_CMEN_OFS (15) /**< AESCMEN Bit Offset */
\r
2014 #define AES256_CTL0_CMEN ((uint16_t)0x8000) /**< AES cipher mode enable */
\r
2015 /* AES256_CTL1[BLKCNT] Bits */
\r
2016 #define AES256_CTL1_BLKCNT_OFS ( 0) /**< AESBLKCNTx Bit Offset */
\r
2017 #define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /**< AESBLKCNTx Bit Mask */
\r
2018 #define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /**< BLKCNT Bit 0 */
\r
2019 #define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /**< BLKCNT Bit 1 */
\r
2020 #define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /**< BLKCNT Bit 2 */
\r
2021 #define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /**< BLKCNT Bit 3 */
\r
2022 #define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /**< BLKCNT Bit 4 */
\r
2023 #define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /**< BLKCNT Bit 5 */
\r
2024 #define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /**< BLKCNT Bit 6 */
\r
2025 #define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /**< BLKCNT Bit 7 */
\r
2026 /* AES256_STAT[BUSY] Bits */
\r
2027 #define AES256_STAT_BUSY_OFS ( 0) /**< AESBUSY Bit Offset */
\r
2028 #define AES256_STAT_BUSY ((uint16_t)0x0001) /**< AES accelerator module busy */
\r
2029 /* AES256_STAT[KEYWR] Bits */
\r
2030 #define AES256_STAT_KEYWR_OFS ( 1) /**< AESKEYWR Bit Offset */
\r
2031 #define AES256_STAT_KEYWR ((uint16_t)0x0002) /**< All 16 bytes written to AESAKEY */
\r
2032 /* AES256_STAT[DINWR] Bits */
\r
2033 #define AES256_STAT_DINWR_OFS ( 2) /**< AESDINWR Bit Offset */
\r
2034 #define AES256_STAT_DINWR ((uint16_t)0x0004) /**< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */
\r
2035 /* AES256_STAT[DOUTRD] Bits */
\r
2036 #define AES256_STAT_DOUTRD_OFS ( 3) /**< AESDOUTRD Bit Offset */
\r
2037 #define AES256_STAT_DOUTRD ((uint16_t)0x0008) /**< All 16 bytes read from AESADOUT */
\r
2038 /* AES256_STAT[KEYCNT] Bits */
\r
2039 #define AES256_STAT_KEYCNT_OFS ( 4) /**< AESKEYCNTx Bit Offset */
\r
2040 #define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /**< AESKEYCNTx Bit Mask */
\r
2041 #define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /**< KEYCNT Bit 0 */
\r
2042 #define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /**< KEYCNT Bit 1 */
\r
2043 #define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /**< KEYCNT Bit 2 */
\r
2044 #define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /**< KEYCNT Bit 3 */
\r
2045 /* AES256_STAT[DINCNT] Bits */
\r
2046 #define AES256_STAT_DINCNT_OFS ( 8) /**< AESDINCNTx Bit Offset */
\r
2047 #define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /**< AESDINCNTx Bit Mask */
\r
2048 #define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /**< DINCNT Bit 0 */
\r
2049 #define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /**< DINCNT Bit 1 */
\r
2050 #define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /**< DINCNT Bit 2 */
\r
2051 #define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /**< DINCNT Bit 3 */
\r
2052 /* AES256_STAT[DOUTCNT] Bits */
\r
2053 #define AES256_STAT_DOUTCNT_OFS (12) /**< AESDOUTCNTx Bit Offset */
\r
2054 #define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /**< AESDOUTCNTx Bit Mask */
\r
2055 #define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /**< DOUTCNT Bit 0 */
\r
2056 #define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /**< DOUTCNT Bit 1 */
\r
2057 #define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /**< DOUTCNT Bit 2 */
\r
2058 #define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /**< DOUTCNT Bit 3 */
\r
2059 /* AES256_KEY[KEY0] Bits */
\r
2060 #define AES256_KEY_KEY0_OFS ( 0) /**< AESKEY0x Bit Offset */
\r
2061 #define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /**< AESKEY0x Bit Mask */
\r
2062 #define AES256_KEY_KEY00 ((uint16_t)0x0001) /**< KEY0 Bit 0 */
\r
2063 #define AES256_KEY_KEY01 ((uint16_t)0x0002) /**< KEY0 Bit 1 */
\r
2064 #define AES256_KEY_KEY02 ((uint16_t)0x0004) /**< KEY0 Bit 2 */
\r
2065 #define AES256_KEY_KEY03 ((uint16_t)0x0008) /**< KEY0 Bit 3 */
\r
2066 #define AES256_KEY_KEY04 ((uint16_t)0x0010) /**< KEY0 Bit 4 */
\r
2067 #define AES256_KEY_KEY05 ((uint16_t)0x0020) /**< KEY0 Bit 5 */
\r
2068 #define AES256_KEY_KEY06 ((uint16_t)0x0040) /**< KEY0 Bit 6 */
\r
2069 #define AES256_KEY_KEY07 ((uint16_t)0x0080) /**< KEY0 Bit 7 */
\r
2070 /* AES256_KEY[KEY1] Bits */
\r
2071 #define AES256_KEY_KEY1_OFS ( 8) /**< AESKEY1x Bit Offset */
\r
2072 #define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /**< AESKEY1x Bit Mask */
\r
2073 #define AES256_KEY_KEY10 ((uint16_t)0x0100) /**< KEY1 Bit 0 */
\r
2074 #define AES256_KEY_KEY11 ((uint16_t)0x0200) /**< KEY1 Bit 1 */
\r
2075 #define AES256_KEY_KEY12 ((uint16_t)0x0400) /**< KEY1 Bit 2 */
\r
2076 #define AES256_KEY_KEY13 ((uint16_t)0x0800) /**< KEY1 Bit 3 */
\r
2077 #define AES256_KEY_KEY14 ((uint16_t)0x1000) /**< KEY1 Bit 4 */
\r
2078 #define AES256_KEY_KEY15 ((uint16_t)0x2000) /**< KEY1 Bit 5 */
\r
2079 #define AES256_KEY_KEY16 ((uint16_t)0x4000) /**< KEY1 Bit 6 */
\r
2080 #define AES256_KEY_KEY17 ((uint16_t)0x8000) /**< KEY1 Bit 7 */
\r
2081 /* AES256_DIN[DIN0] Bits */
\r
2082 #define AES256_DIN_DIN0_OFS ( 0) /**< AESDIN0x Bit Offset */
\r
2083 #define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /**< AESDIN0x Bit Mask */
\r
2084 #define AES256_DIN_DIN00 ((uint16_t)0x0001) /**< DIN0 Bit 0 */
\r
2085 #define AES256_DIN_DIN01 ((uint16_t)0x0002) /**< DIN0 Bit 1 */
\r
2086 #define AES256_DIN_DIN02 ((uint16_t)0x0004) /**< DIN0 Bit 2 */
\r
2087 #define AES256_DIN_DIN03 ((uint16_t)0x0008) /**< DIN0 Bit 3 */
\r
2088 #define AES256_DIN_DIN04 ((uint16_t)0x0010) /**< DIN0 Bit 4 */
\r
2089 #define AES256_DIN_DIN05 ((uint16_t)0x0020) /**< DIN0 Bit 5 */
\r
2090 #define AES256_DIN_DIN06 ((uint16_t)0x0040) /**< DIN0 Bit 6 */
\r
2091 #define AES256_DIN_DIN07 ((uint16_t)0x0080) /**< DIN0 Bit 7 */
\r
2092 /* AES256_DIN[DIN1] Bits */
\r
2093 #define AES256_DIN_DIN1_OFS ( 8) /**< AESDIN1x Bit Offset */
\r
2094 #define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /**< AESDIN1x Bit Mask */
\r
2095 #define AES256_DIN_DIN10 ((uint16_t)0x0100) /**< DIN1 Bit 0 */
\r
2096 #define AES256_DIN_DIN11 ((uint16_t)0x0200) /**< DIN1 Bit 1 */
\r
2097 #define AES256_DIN_DIN12 ((uint16_t)0x0400) /**< DIN1 Bit 2 */
\r
2098 #define AES256_DIN_DIN13 ((uint16_t)0x0800) /**< DIN1 Bit 3 */
\r
2099 #define AES256_DIN_DIN14 ((uint16_t)0x1000) /**< DIN1 Bit 4 */
\r
2100 #define AES256_DIN_DIN15 ((uint16_t)0x2000) /**< DIN1 Bit 5 */
\r
2101 #define AES256_DIN_DIN16 ((uint16_t)0x4000) /**< DIN1 Bit 6 */
\r
2102 #define AES256_DIN_DIN17 ((uint16_t)0x8000) /**< DIN1 Bit 7 */
\r
2103 /* AES256_DOUT[DOUT0] Bits */
\r
2104 #define AES256_DOUT_DOUT0_OFS ( 0) /**< AESDOUT0x Bit Offset */
\r
2105 #define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /**< AESDOUT0x Bit Mask */
\r
2106 #define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /**< DOUT0 Bit 0 */
\r
2107 #define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /**< DOUT0 Bit 1 */
\r
2108 #define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /**< DOUT0 Bit 2 */
\r
2109 #define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /**< DOUT0 Bit 3 */
\r
2110 #define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /**< DOUT0 Bit 4 */
\r
2111 #define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /**< DOUT0 Bit 5 */
\r
2112 #define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /**< DOUT0 Bit 6 */
\r
2113 #define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /**< DOUT0 Bit 7 */
\r
2114 /* AES256_DOUT[DOUT1] Bits */
\r
2115 #define AES256_DOUT_DOUT1_OFS ( 8) /**< AESDOUT1x Bit Offset */
\r
2116 #define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /**< AESDOUT1x Bit Mask */
\r
2117 #define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /**< DOUT1 Bit 0 */
\r
2118 #define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /**< DOUT1 Bit 1 */
\r
2119 #define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /**< DOUT1 Bit 2 */
\r
2120 #define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /**< DOUT1 Bit 3 */
\r
2121 #define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /**< DOUT1 Bit 4 */
\r
2122 #define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /**< DOUT1 Bit 5 */
\r
2123 #define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /**< DOUT1 Bit 6 */
\r
2124 #define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /**< DOUT1 Bit 7 */
\r
2125 /* AES256_XDIN[XDIN0] Bits */
\r
2126 #define AES256_XDIN_XDIN0_OFS ( 0) /**< AESXDIN0x Bit Offset */
\r
2127 #define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /**< AESXDIN0x Bit Mask */
\r
2128 #define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /**< XDIN0 Bit 0 */
\r
2129 #define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /**< XDIN0 Bit 1 */
\r
2130 #define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /**< XDIN0 Bit 2 */
\r
2131 #define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /**< XDIN0 Bit 3 */
\r
2132 #define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /**< XDIN0 Bit 4 */
\r
2133 #define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /**< XDIN0 Bit 5 */
\r
2134 #define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /**< XDIN0 Bit 6 */
\r
2135 #define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /**< XDIN0 Bit 7 */
\r
2136 /* AES256_XDIN[XDIN1] Bits */
\r
2137 #define AES256_XDIN_XDIN1_OFS ( 8) /**< AESXDIN1x Bit Offset */
\r
2138 #define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /**< AESXDIN1x Bit Mask */
\r
2139 #define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /**< XDIN1 Bit 0 */
\r
2140 #define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /**< XDIN1 Bit 1 */
\r
2141 #define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /**< XDIN1 Bit 2 */
\r
2142 #define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /**< XDIN1 Bit 3 */
\r
2143 #define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /**< XDIN1 Bit 4 */
\r
2144 #define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /**< XDIN1 Bit 5 */
\r
2145 #define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /**< XDIN1 Bit 6 */
\r
2146 #define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /**< XDIN1 Bit 7 */
\r
2147 /* AES256_XIN[XIN0] Bits */
\r
2148 #define AES256_XIN_XIN0_OFS ( 0) /**< AESXIN0x Bit Offset */
\r
2149 #define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /**< AESXIN0x Bit Mask */
\r
2150 #define AES256_XIN_XIN00 ((uint16_t)0x0001) /**< XIN0 Bit 0 */
\r
2151 #define AES256_XIN_XIN01 ((uint16_t)0x0002) /**< XIN0 Bit 1 */
\r
2152 #define AES256_XIN_XIN02 ((uint16_t)0x0004) /**< XIN0 Bit 2 */
\r
2153 #define AES256_XIN_XIN03 ((uint16_t)0x0008) /**< XIN0 Bit 3 */
\r
2154 #define AES256_XIN_XIN04 ((uint16_t)0x0010) /**< XIN0 Bit 4 */
\r
2155 #define AES256_XIN_XIN05 ((uint16_t)0x0020) /**< XIN0 Bit 5 */
\r
2156 #define AES256_XIN_XIN06 ((uint16_t)0x0040) /**< XIN0 Bit 6 */
\r
2157 #define AES256_XIN_XIN07 ((uint16_t)0x0080) /**< XIN0 Bit 7 */
\r
2158 /* AES256_XIN[XIN1] Bits */
\r
2159 #define AES256_XIN_XIN1_OFS ( 8) /**< AESXIN1x Bit Offset */
\r
2160 #define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /**< AESXIN1x Bit Mask */
\r
2161 #define AES256_XIN_XIN10 ((uint16_t)0x0100) /**< XIN1 Bit 0 */
\r
2162 #define AES256_XIN_XIN11 ((uint16_t)0x0200) /**< XIN1 Bit 1 */
\r
2163 #define AES256_XIN_XIN12 ((uint16_t)0x0400) /**< XIN1 Bit 2 */
\r
2164 #define AES256_XIN_XIN13 ((uint16_t)0x0800) /**< XIN1 Bit 3 */
\r
2165 #define AES256_XIN_XIN14 ((uint16_t)0x1000) /**< XIN1 Bit 4 */
\r
2166 #define AES256_XIN_XIN15 ((uint16_t)0x2000) /**< XIN1 Bit 5 */
\r
2167 #define AES256_XIN_XIN16 ((uint16_t)0x4000) /**< XIN1 Bit 6 */
\r
2168 #define AES256_XIN_XIN17 ((uint16_t)0x8000) /**< XIN1 Bit 7 */
\r
2171 /******************************************************************************
\r
2173 ******************************************************************************/
\r
2174 /* CAPTIO_CTL[PISEL] Bits */
\r
2175 #define CAPTIO_CTL_PISEL_OFS ( 1) /**< CAPTIOPISELx Bit Offset */
\r
2176 #define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /**< CAPTIOPISELx Bit Mask */
\r
2177 #define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /**< PISEL Bit 0 */
\r
2178 #define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /**< PISEL Bit 1 */
\r
2179 #define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /**< PISEL Bit 2 */
\r
2180 #define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /**< Px.0 */
\r
2181 #define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /**< Px.1 */
\r
2182 #define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /**< Px.2 */
\r
2183 #define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /**< Px.3 */
\r
2184 #define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /**< Px.4 */
\r
2185 #define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /**< Px.5 */
\r
2186 #define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /**< Px.6 */
\r
2187 #define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /**< Px.7 */
\r
2188 /* CAPTIO_CTL[POSEL] Bits */
\r
2189 #define CAPTIO_CTL_POSEL_OFS ( 4) /**< CAPTIOPOSELx Bit Offset */
\r
2190 #define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /**< CAPTIOPOSELx Bit Mask */
\r
2191 #define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /**< POSEL Bit 0 */
\r
2192 #define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /**< POSEL Bit 1 */
\r
2193 #define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /**< POSEL Bit 2 */
\r
2194 #define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /**< POSEL Bit 3 */
\r
2195 #define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /**< Px = PJ */
\r
2196 #define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /**< Px = P1 */
\r
2197 #define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /**< Px = P2 */
\r
2198 #define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /**< Px = P3 */
\r
2199 #define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /**< Px = P4 */
\r
2200 #define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /**< Px = P5 */
\r
2201 #define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /**< Px = P6 */
\r
2202 #define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /**< Px = P7 */
\r
2203 #define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /**< Px = P8 */
\r
2204 #define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /**< Px = P9 */
\r
2205 #define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /**< Px = P10 */
\r
2206 #define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /**< Px = P11 */
\r
2207 #define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /**< Px = P12 */
\r
2208 #define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /**< Px = P13 */
\r
2209 #define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /**< Px = P14 */
\r
2210 #define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /**< Px = P15 */
\r
2211 #define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /**< Px = PJ */
\r
2212 #define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /**< Px = P1 */
\r
2213 #define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /**< Px = P2 */
\r
2214 #define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /**< Px = P3 */
\r
2215 #define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /**< Px = P4 */
\r
2216 #define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /**< Px = P5 */
\r
2217 #define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /**< Px = P6 */
\r
2218 #define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /**< Px = P7 */
\r
2219 #define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /**< Px = P8 */
\r
2220 #define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /**< Px = P9 */
\r
2221 #define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /**< Px = P10 */
\r
2222 #define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /**< Px = P11 */
\r
2223 #define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /**< Px = P12 */
\r
2224 #define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /**< Px = P13 */
\r
2225 #define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /**< Px = P14 */
\r
2226 #define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /**< Px = P15 */
\r
2227 /* CAPTIO_CTL[EN] Bits */
\r
2228 #define CAPTIO_CTL_EN_OFS ( 8) /**< CAPTIOEN Bit Offset */
\r
2229 #define CAPTIO_CTL_EN ((uint16_t)0x0100) /**< Capacitive Touch IO enable */
\r
2230 /* CAPTIO_CTL[STATE] Bits */
\r
2231 #define CAPTIO_CTL_STATE_OFS ( 9) /**< CAPTIOSTATE Bit Offset */
\r
2232 #define CAPTIO_CTL_STATE ((uint16_t)0x0200) /**< Capacitive Touch IO state */
\r
2235 /******************************************************************************
\r
2237 ******************************************************************************/
\r
2238 /* COMP_E_CTL0[IPSEL] Bits */
\r
2239 #define COMP_E_CTL0_IPSEL_OFS ( 0) /**< CEIPSEL Bit Offset */
\r
2240 #define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /**< CEIPSEL Bit Mask */
\r
2241 #define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /**< IPSEL Bit 0 */
\r
2242 #define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /**< IPSEL Bit 1 */
\r
2243 #define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /**< IPSEL Bit 2 */
\r
2244 #define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /**< IPSEL Bit 3 */
\r
2245 #define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /**< Channel 0 selected */
\r
2246 #define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /**< Channel 1 selected */
\r
2247 #define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /**< Channel 2 selected */
\r
2248 #define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /**< Channel 3 selected */
\r
2249 #define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /**< Channel 4 selected */
\r
2250 #define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /**< Channel 5 selected */
\r
2251 #define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /**< Channel 6 selected */
\r
2252 #define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /**< Channel 7 selected */
\r
2253 #define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /**< Channel 8 selected */
\r
2254 #define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /**< Channel 9 selected */
\r
2255 #define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /**< Channel 10 selected */
\r
2256 #define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /**< Channel 11 selected */
\r
2257 #define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /**< Channel 12 selected */
\r
2258 #define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /**< Channel 13 selected */
\r
2259 #define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /**< Channel 14 selected */
\r
2260 #define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /**< Channel 15 selected */
\r
2261 /* COMP_E_CTL0[IPEN] Bits */
\r
2262 #define COMP_E_CTL0_IPEN_OFS ( 7) /**< CEIPEN Bit Offset */
\r
2263 #define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /**< Channel input enable for the V+ terminal */
\r
2264 /* COMP_E_CTL0[IMSEL] Bits */
\r
2265 #define COMP_E_CTL0_IMSEL_OFS ( 8) /**< CEIMSEL Bit Offset */
\r
2266 #define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /**< CEIMSEL Bit Mask */
\r
2267 #define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /**< IMSEL Bit 0 */
\r
2268 #define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /**< IMSEL Bit 1 */
\r
2269 #define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /**< IMSEL Bit 2 */
\r
2270 #define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /**< IMSEL Bit 3 */
\r
2271 #define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /**< Channel 0 selected */
\r
2272 #define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /**< Channel 1 selected */
\r
2273 #define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /**< Channel 2 selected */
\r
2274 #define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /**< Channel 3 selected */
\r
2275 #define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /**< Channel 4 selected */
\r
2276 #define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /**< Channel 5 selected */
\r
2277 #define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /**< Channel 6 selected */
\r
2278 #define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /**< Channel 7 selected */
\r
2279 #define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /**< Channel 8 selected */
\r
2280 #define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /**< Channel 9 selected */
\r
2281 #define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /**< Channel 10 selected */
\r
2282 #define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /**< Channel 11 selected */
\r
2283 #define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /**< Channel 12 selected */
\r
2284 #define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /**< Channel 13 selected */
\r
2285 #define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /**< Channel 14 selected */
\r
2286 #define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /**< Channel 15 selected */
\r
2287 /* COMP_E_CTL0[IMEN] Bits */
\r
2288 #define COMP_E_CTL0_IMEN_OFS (15) /**< CEIMEN Bit Offset */
\r
2289 #define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /**< Channel input enable for the - terminal */
\r
2290 /* COMP_E_CTL1[OUT] Bits */
\r
2291 #define COMP_E_CTL1_OUT_OFS ( 0) /**< CEOUT Bit Offset */
\r
2292 #define COMP_E_CTL1_OUT ((uint16_t)0x0001) /**< Comparator output value */
\r
2293 /* COMP_E_CTL1[OUTPOL] Bits */
\r
2294 #define COMP_E_CTL1_OUTPOL_OFS ( 1) /**< CEOUTPOL Bit Offset */
\r
2295 #define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /**< Comparator output polarity */
\r
2296 /* COMP_E_CTL1[F] Bits */
\r
2297 #define COMP_E_CTL1_F_OFS ( 2) /**< CEF Bit Offset */
\r
2298 #define COMP_E_CTL1_F ((uint16_t)0x0004) /**< Comparator output filter */
\r
2299 /* COMP_E_CTL1[IES] Bits */
\r
2300 #define COMP_E_CTL1_IES_OFS ( 3) /**< CEIES Bit Offset */
\r
2301 #define COMP_E_CTL1_IES ((uint16_t)0x0008) /**< Interrupt edge select for CEIIFG and CEIFG */
\r
2302 /* COMP_E_CTL1[SHORT] Bits */
\r
2303 #define COMP_E_CTL1_SHORT_OFS ( 4) /**< CESHORT Bit Offset */
\r
2304 #define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /**< Input short */
\r
2305 /* COMP_E_CTL1[EX] Bits */
\r
2306 #define COMP_E_CTL1_EX_OFS ( 5) /**< CEEX Bit Offset */
\r
2307 #define COMP_E_CTL1_EX ((uint16_t)0x0020) /**< Exchange */
\r
2308 /* COMP_E_CTL1[FDLY] Bits */
\r
2309 #define COMP_E_CTL1_FDLY_OFS ( 6) /**< CEFDLY Bit Offset */
\r
2310 #define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /**< CEFDLY Bit Mask */
\r
2311 #define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /**< FDLY Bit 0 */
\r
2312 #define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /**< FDLY Bit 1 */
\r
2313 #define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /**< Typical filter delay of TBD (450) ns */
\r
2314 #define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /**< Typical filter delay of TBD (900) ns */
\r
2315 #define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /**< Typical filter delay of TBD (1800) ns */
\r
2316 #define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /**< Typical filter delay of TBD (3600) ns */
\r
2317 /* COMP_E_CTL1[PWRMD] Bits */
\r
2318 #define COMP_E_CTL1_PWRMD_OFS ( 8) /**< CEPWRMD Bit Offset */
\r
2319 #define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /**< CEPWRMD Bit Mask */
\r
2320 #define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /**< PWRMD Bit 0 */
\r
2321 #define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /**< PWRMD Bit 1 */
\r
2322 #define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /**< High-speed mode */
\r
2323 #define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /**< Normal mode */
\r
2324 #define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /**< Ultra-low power mode */
\r
2325 /* COMP_E_CTL1[ON] Bits */
\r
2326 #define COMP_E_CTL1_ON_OFS (10) /**< CEON Bit Offset */
\r
2327 #define COMP_E_CTL1_ON ((uint16_t)0x0400) /**< Comparator On */
\r
2328 /* COMP_E_CTL1[MRVL] Bits */
\r
2329 #define COMP_E_CTL1_MRVL_OFS (11) /**< CEMRVL Bit Offset */
\r
2330 #define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /**< This bit is valid of CEMRVS is set to 1 */
\r
2331 /* COMP_E_CTL1[MRVS] Bits */
\r
2332 #define COMP_E_CTL1_MRVS_OFS (12) /**< CEMRVS Bit Offset */
\r
2333 #define COMP_E_CTL1_MRVS ((uint16_t)0x1000)
\r
2334 /* COMP_E_CTL2[REF0] Bits */
\r
2335 #define COMP_E_CTL2_REF0_OFS ( 0) /**< CEREF0 Bit Offset */
\r
2336 #define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /**< CEREF0 Bit Mask */
\r
2337 /* COMP_E_CTL2[RSEL] Bits */
\r
2338 #define COMP_E_CTL2_RSEL_OFS ( 5) /**< CERSEL Bit Offset */
\r
2339 #define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /**< Reference select */
\r
2340 /* COMP_E_CTL2[RS] Bits */
\r
2341 #define COMP_E_CTL2_RS_OFS ( 6) /**< CERS Bit Offset */
\r
2342 #define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /**< CERS Bit Mask */
\r
2343 #define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /**< RS Bit 0 */
\r
2344 #define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /**< RS Bit 1 */
\r
2345 #define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /**< No current is drawn by the reference circuitry */
\r
2346 #define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /**< VCC applied to the resistor ladder */
\r
2347 #define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /**< Shared reference voltage applied to the resistor ladder */
\r
2348 #define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /**< Shared reference voltage supplied to V(CREF). Resistor ladder is off */
\r
2349 /* COMP_E_CTL2[REF1] Bits */
\r
2350 #define COMP_E_CTL2_REF1_OFS ( 8) /**< CEREF1 Bit Offset */
\r
2351 #define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /**< CEREF1 Bit Mask */
\r
2352 /* COMP_E_CTL2[REFL] Bits */
\r
2353 #define COMP_E_CTL2_REFL_OFS (13) /**< CEREFL Bit Offset */
\r
2354 #define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /**< CEREFL Bit Mask */
\r
2355 #define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /**< REFL Bit 0 */
\r
2356 #define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /**< REFL Bit 1 */
\r
2357 #define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /**< Reference amplifier is disabled. No reference voltage is requested */
\r
2358 #define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /**< 1.2 V is selected as shared reference voltage input */
\r
2359 #define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /**< 2.0 V is selected as shared reference voltage input */
\r
2360 #define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /**< 2.5 V is selected as shared reference voltage input */
\r
2361 #define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /**< Reference amplifier is disabled. No reference voltage is requested */
\r
2362 #define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /**< 1.2 V is selected as shared reference voltage input */
\r
2363 #define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /**< 2.0 V is selected as shared reference voltage input */
\r
2364 #define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /**< 2.5 V is selected as shared reference voltage input */
\r
2365 /* COMP_E_CTL2[REFACC] Bits */
\r
2366 #define COMP_E_CTL2_REFACC_OFS (15) /**< CEREFACC Bit Offset */
\r
2367 #define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /**< Reference accuracy */
\r
2368 /* COMP_E_CTL3[PD0] Bits */
\r
2369 #define COMP_E_CTL3_PD0_OFS ( 0) /**< CEPD0 Bit Offset */
\r
2370 #define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /**< Port disable */
\r
2371 /* COMP_E_CTL3[PD1] Bits */
\r
2372 #define COMP_E_CTL3_PD1_OFS ( 1) /**< CEPD1 Bit Offset */
\r
2373 #define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /**< Port disable */
\r
2374 /* COMP_E_CTL3[PD2] Bits */
\r
2375 #define COMP_E_CTL3_PD2_OFS ( 2) /**< CEPD2 Bit Offset */
\r
2376 #define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /**< Port disable */
\r
2377 /* COMP_E_CTL3[PD3] Bits */
\r
2378 #define COMP_E_CTL3_PD3_OFS ( 3) /**< CEPD3 Bit Offset */
\r
2379 #define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /**< Port disable */
\r
2380 /* COMP_E_CTL3[PD4] Bits */
\r
2381 #define COMP_E_CTL3_PD4_OFS ( 4) /**< CEPD4 Bit Offset */
\r
2382 #define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /**< Port disable */
\r
2383 /* COMP_E_CTL3[PD5] Bits */
\r
2384 #define COMP_E_CTL3_PD5_OFS ( 5) /**< CEPD5 Bit Offset */
\r
2385 #define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /**< Port disable */
\r
2386 /* COMP_E_CTL3[PD6] Bits */
\r
2387 #define COMP_E_CTL3_PD6_OFS ( 6) /**< CEPD6 Bit Offset */
\r
2388 #define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /**< Port disable */
\r
2389 /* COMP_E_CTL3[PD7] Bits */
\r
2390 #define COMP_E_CTL3_PD7_OFS ( 7) /**< CEPD7 Bit Offset */
\r
2391 #define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /**< Port disable */
\r
2392 /* COMP_E_CTL3[PD8] Bits */
\r
2393 #define COMP_E_CTL3_PD8_OFS ( 8) /**< CEPD8 Bit Offset */
\r
2394 #define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /**< Port disable */
\r
2395 /* COMP_E_CTL3[PD9] Bits */
\r
2396 #define COMP_E_CTL3_PD9_OFS ( 9) /**< CEPD9 Bit Offset */
\r
2397 #define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /**< Port disable */
\r
2398 /* COMP_E_CTL3[PD10] Bits */
\r
2399 #define COMP_E_CTL3_PD10_OFS (10) /**< CEPD10 Bit Offset */
\r
2400 #define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /**< Port disable */
\r
2401 /* COMP_E_CTL3[PD11] Bits */
\r
2402 #define COMP_E_CTL3_PD11_OFS (11) /**< CEPD11 Bit Offset */
\r
2403 #define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /**< Port disable */
\r
2404 /* COMP_E_CTL3[PD12] Bits */
\r
2405 #define COMP_E_CTL3_PD12_OFS (12) /**< CEPD12 Bit Offset */
\r
2406 #define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /**< Port disable */
\r
2407 /* COMP_E_CTL3[PD13] Bits */
\r
2408 #define COMP_E_CTL3_PD13_OFS (13) /**< CEPD13 Bit Offset */
\r
2409 #define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /**< Port disable */
\r
2410 /* COMP_E_CTL3[PD14] Bits */
\r
2411 #define COMP_E_CTL3_PD14_OFS (14) /**< CEPD14 Bit Offset */
\r
2412 #define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /**< Port disable */
\r
2413 /* COMP_E_CTL3[PD15] Bits */
\r
2414 #define COMP_E_CTL3_PD15_OFS (15) /**< CEPD15 Bit Offset */
\r
2415 #define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /**< Port disable */
\r
2416 /* COMP_E_INT[IFG] Bits */
\r
2417 #define COMP_E_INT_IFG_OFS ( 0) /**< CEIFG Bit Offset */
\r
2418 #define COMP_E_INT_IFG ((uint16_t)0x0001) /**< Comparator output interrupt flag */
\r
2419 /* COMP_E_INT[IIFG] Bits */
\r
2420 #define COMP_E_INT_IIFG_OFS ( 1) /**< CEIIFG Bit Offset */
\r
2421 #define COMP_E_INT_IIFG ((uint16_t)0x0002) /**< Comparator output inverted interrupt flag */
\r
2422 /* COMP_E_INT[RDYIFG] Bits */
\r
2423 #define COMP_E_INT_RDYIFG_OFS ( 4) /**< CERDYIFG Bit Offset */
\r
2424 #define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /**< Comparator ready interrupt flag */
\r
2425 /* COMP_E_INT[IE] Bits */
\r
2426 #define COMP_E_INT_IE_OFS ( 8) /**< CEIE Bit Offset */
\r
2427 #define COMP_E_INT_IE ((uint16_t)0x0100) /**< Comparator output interrupt enable */
\r
2428 /* COMP_E_INT[IIE] Bits */
\r
2429 #define COMP_E_INT_IIE_OFS ( 9) /**< CEIIE Bit Offset */
\r
2430 #define COMP_E_INT_IIE ((uint16_t)0x0200) /**< Comparator output interrupt enable inverted polarity */
\r
2431 /* COMP_E_INT[RDYIE] Bits */
\r
2432 #define COMP_E_INT_RDYIE_OFS (12) /**< CERDYIE Bit Offset */
\r
2433 #define COMP_E_INT_RDYIE ((uint16_t)0x1000) /**< Comparator ready interrupt enable */
\r
2436 /******************************************************************************
\r
2438 ******************************************************************************/
\r
2441 /******************************************************************************
\r
2443 ******************************************************************************/
\r
2446 /******************************************************************************
\r
2448 ******************************************************************************/
\r
2449 /* CS_KEY[KEY] Bits */
\r
2450 #define CS_KEY_KEY_OFS ( 0) /**< CSKEY Bit Offset */
\r
2451 #define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /**< CSKEY Bit Mask */
\r
2452 /* CS_CTL0[DCOTUNE] Bits */
\r
2453 #define CS_CTL0_DCOTUNE_OFS ( 0) /**< DCOTUNE Bit Offset */
\r
2454 #define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /**< DCOTUNE Bit Mask */
\r
2455 /* CS_CTL0[DCORSEL] Bits */
\r
2456 #define CS_CTL0_DCORSEL_OFS (16) /**< DCORSEL Bit Offset */
\r
2457 #define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /**< DCORSEL Bit Mask */
\r
2458 #define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /**< DCORSEL Bit 0 */
\r
2459 #define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /**< DCORSEL Bit 1 */
\r
2460 #define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /**< DCORSEL Bit 2 */
\r
2461 #define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /**< Nominal DCO Frequency Range (MHz): 1 to 2 */
\r
2462 #define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /**< Nominal DCO Frequency Range (MHz): 2 to 4 */
\r
2463 #define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /**< Nominal DCO Frequency Range (MHz): 4 to 8 */
\r
2464 #define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /**< Nominal DCO Frequency Range (MHz): 8 to 16 */
\r
2465 #define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /**< Nominal DCO Frequency Range (MHz): 16 to 32 */
\r
2466 #define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /**< Nominal DCO Frequency Range (MHz): 32 to 64 */
\r
2467 /* CS_CTL0[DCORES] Bits */
\r
2468 #define CS_CTL0_DCORES_OFS (22) /**< DCORES Bit Offset */
\r
2469 #define CS_CTL0_DCORES ((uint32_t)0x00400000) /**< Enables the DCO external resistor mode */
\r
2470 /* CS_CTL0[DCOEN] Bits */
\r
2471 #define CS_CTL0_DCOEN_OFS (23) /**< DCOEN Bit Offset */
\r
2472 #define CS_CTL0_DCOEN ((uint32_t)0x00800000) /**< Enables the DCO oscillator */
\r
2473 /* CS_CTL1[SELM] Bits */
\r
2474 #define CS_CTL1_SELM_OFS ( 0) /**< SELM Bit Offset */
\r
2475 #define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /**< SELM Bit Mask */
\r
2476 #define CS_CTL1_SELM0 ((uint32_t)0x00000001) /**< SELM Bit 0 */
\r
2477 #define CS_CTL1_SELM1 ((uint32_t)0x00000002) /**< SELM Bit 1 */
\r
2478 #define CS_CTL1_SELM2 ((uint32_t)0x00000004) /**< SELM Bit 2 */
\r
2479 #define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */
\r
2480 #define CS_CTL1_SELM_1 ((uint32_t)0x00000001)
\r
2481 #define CS_CTL1_SELM_2 ((uint32_t)0x00000002)
\r
2482 #define CS_CTL1_SELM_3 ((uint32_t)0x00000003)
\r
2483 #define CS_CTL1_SELM_4 ((uint32_t)0x00000004)
\r
2484 #define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /**< when HFXT available, otherwise DCOCLK */
\r
2485 #define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /**< when HFXT2 available, otherwise DCOCLK */
\r
2486 #define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */
\r
2487 #define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001)
\r
2488 #define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002)
\r
2489 #define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003)
\r
2490 #define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004)
\r
2491 #define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /**< when HFXT available, otherwise DCOCLK */
\r
2492 #define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /**< when HFXT2 available, otherwise DCOCLK */
\r
2493 #define CS_CTL1_SELM_7 ((uint32_t)0x00000007) /**< for future use. Defaults to DCOCLK. Not recommended for use to ensure future */
\r
2494 /* compatibilities. */
\r
2495 /* CS_CTL1[SELS] Bits */
\r
2496 #define CS_CTL1_SELS_OFS ( 4) /**< SELS Bit Offset */
\r
2497 #define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /**< SELS Bit Mask */
\r
2498 #define CS_CTL1_SELS0 ((uint32_t)0x00000010) /**< SELS Bit 0 */
\r
2499 #define CS_CTL1_SELS1 ((uint32_t)0x00000020) /**< SELS Bit 1 */
\r
2500 #define CS_CTL1_SELS2 ((uint32_t)0x00000040) /**< SELS Bit 2 */
\r
2501 #define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */
\r
2502 #define CS_CTL1_SELS_1 ((uint32_t)0x00000010)
\r
2503 #define CS_CTL1_SELS_2 ((uint32_t)0x00000020)
\r
2504 #define CS_CTL1_SELS_3 ((uint32_t)0x00000030)
\r
2505 #define CS_CTL1_SELS_4 ((uint32_t)0x00000040)
\r
2506 #define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /**< when HFXT available, otherwise DCOCLK */
\r
2507 #define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /**< when HFXT2 available, otherwise DCOCLK */
\r
2508 #define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */
\r
2509 #define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010)
\r
2510 #define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020)
\r
2511 #define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030)
\r
2512 #define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040)
\r
2513 #define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /**< when HFXT available, otherwise DCOCLK */
\r
2514 #define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /**< when HFXT2 available, otherwise DCOCLK */
\r
2515 #define CS_CTL1_SELS_7 ((uint32_t)0x00000070) /**< for furture use. Defaults to DCOCLK. Do not use to ensure future */
\r
2516 /* compatibilities. */
\r
2517 /* CS_CTL1[SELA] Bits */
\r
2518 #define CS_CTL1_SELA_OFS ( 8) /**< SELA Bit Offset */
\r
2519 #define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /**< SELA Bit Mask */
\r
2520 #define CS_CTL1_SELA0 ((uint32_t)0x00000100) /**< SELA Bit 0 */
\r
2521 #define CS_CTL1_SELA1 ((uint32_t)0x00000200) /**< SELA Bit 1 */
\r
2522 #define CS_CTL1_SELA2 ((uint32_t)0x00000400) /**< SELA Bit 2 */
\r
2523 #define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */
\r
2524 #define CS_CTL1_SELA_1 ((uint32_t)0x00000100)
\r
2525 #define CS_CTL1_SELA_2 ((uint32_t)0x00000200)
\r
2526 #define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */
\r
2527 #define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100)
\r
2528 #define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200)
\r
2529 #define CS_CTL1_SELA_3 ((uint32_t)0x00000300) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
\r
2530 /* compatibilities. */
\r
2531 #define CS_CTL1_SELA_4 ((uint32_t)0x00000400) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
\r
2532 /* compatibilities. */
\r
2533 #define CS_CTL1_SELA_5 ((uint32_t)0x00000500) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
\r
2534 /* compatibilities. */
\r
2535 #define CS_CTL1_SELA_6 ((uint32_t)0x00000600) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
\r
2536 /* compatibilities. */
\r
2537 #define CS_CTL1_SELA_7 ((uint32_t)0x00000700) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
\r
2538 /* compatibilities. */
\r
2539 /* CS_CTL1[SELB] Bits */
\r
2540 #define CS_CTL1_SELB_OFS (12) /**< SELB Bit Offset */
\r
2541 #define CS_CTL1_SELB ((uint32_t)0x00001000) /**< Selects the BCLK source */
\r
2542 /* CS_CTL1[DIVM] Bits */
\r
2543 #define CS_CTL1_DIVM_OFS (16) /**< DIVM Bit Offset */
\r
2544 #define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /**< DIVM Bit Mask */
\r
2545 #define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /**< DIVM Bit 0 */
\r
2546 #define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /**< DIVM Bit 1 */
\r
2547 #define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /**< DIVM Bit 2 */
\r
2548 #define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /**< f(MCLK)/1 */
\r
2549 #define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /**< f(MCLK)/2 */
\r
2550 #define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /**< f(MCLK)/4 */
\r
2551 #define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /**< f(MCLK)/8 */
\r
2552 #define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /**< f(MCLK)/16 */
\r
2553 #define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /**< f(MCLK)/32 */
\r
2554 #define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /**< f(MCLK)/64 */
\r
2555 #define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /**< f(MCLK)/128 */
\r
2556 #define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /**< f(MCLK)/1 */
\r
2557 #define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /**< f(MCLK)/2 */
\r
2558 #define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /**< f(MCLK)/4 */
\r
2559 #define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /**< f(MCLK)/8 */
\r
2560 #define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /**< f(MCLK)/16 */
\r
2561 #define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /**< f(MCLK)/32 */
\r
2562 #define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /**< f(MCLK)/64 */
\r
2563 #define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /**< f(MCLK)/128 */
\r
2564 /* CS_CTL1[DIVHS] Bits */
\r
2565 #define CS_CTL1_DIVHS_OFS (20) /**< DIVHS Bit Offset */
\r
2566 #define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /**< DIVHS Bit Mask */
\r
2567 #define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /**< DIVHS Bit 0 */
\r
2568 #define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /**< DIVHS Bit 1 */
\r
2569 #define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /**< DIVHS Bit 2 */
\r
2570 #define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /**< f(HSMCLK)/1 */
\r
2571 #define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /**< f(HSMCLK)/2 */
\r
2572 #define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /**< f(HSMCLK)/4 */
\r
2573 #define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /**< f(HSMCLK)/8 */
\r
2574 #define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /**< f(HSMCLK)/16 */
\r
2575 #define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /**< f(HSMCLK)/32 */
\r
2576 #define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /**< f(HSMCLK)/64 */
\r
2577 #define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /**< f(HSMCLK)/128 */
\r
2578 #define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /**< f(HSMCLK)/1 */
\r
2579 #define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /**< f(HSMCLK)/2 */
\r
2580 #define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /**< f(HSMCLK)/4 */
\r
2581 #define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /**< f(HSMCLK)/8 */
\r
2582 #define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /**< f(HSMCLK)/16 */
\r
2583 #define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /**< f(HSMCLK)/32 */
\r
2584 #define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /**< f(HSMCLK)/64 */
\r
2585 #define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /**< f(HSMCLK)/128 */
\r
2586 /* CS_CTL1[DIVA] Bits */
\r
2587 #define CS_CTL1_DIVA_OFS (24) /**< DIVA Bit Offset */
\r
2588 #define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /**< DIVA Bit Mask */
\r
2589 #define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /**< DIVA Bit 0 */
\r
2590 #define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /**< DIVA Bit 1 */
\r
2591 #define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /**< DIVA Bit 2 */
\r
2592 #define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /**< f(ACLK)/1 */
\r
2593 #define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /**< f(ACLK)/2 */
\r
2594 #define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /**< f(ACLK)/4 */
\r
2595 #define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /**< f(ACLK)/8 */
\r
2596 #define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /**< f(ACLK)/16 */
\r
2597 #define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /**< f(ACLK)/32 */
\r
2598 #define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /**< f(ACLK)/64 */
\r
2599 #define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /**< f(ACLK)/128 */
\r
2600 #define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /**< f(ACLK)/1 */
\r
2601 #define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /**< f(ACLK)/2 */
\r
2602 #define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /**< f(ACLK)/4 */
\r
2603 #define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /**< f(ACLK)/8 */
\r
2604 #define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /**< f(ACLK)/16 */
\r
2605 #define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /**< f(ACLK)/32 */
\r
2606 #define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /**< f(ACLK)/64 */
\r
2607 #define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /**< f(ACLK)/128 */
\r
2608 /* CS_CTL1[DIVS] Bits */
\r
2609 #define CS_CTL1_DIVS_OFS (28) /**< DIVS Bit Offset */
\r
2610 #define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /**< DIVS Bit Mask */
\r
2611 #define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /**< DIVS Bit 0 */
\r
2612 #define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /**< DIVS Bit 1 */
\r
2613 #define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /**< DIVS Bit 2 */
\r
2614 #define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /**< f(SMCLK)/1 */
\r
2615 #define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /**< f(SMCLK)/2 */
\r
2616 #define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /**< f(SMCLK)/4 */
\r
2617 #define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /**< f(SMCLK)/8 */
\r
2618 #define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /**< f(SMCLK)/16 */
\r
2619 #define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /**< f(SMCLK)/32 */
\r
2620 #define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /**< f(SMCLK)/64 */
\r
2621 #define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /**< f(SMCLK)/128 */
\r
2622 #define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /**< f(SMCLK)/1 */
\r
2623 #define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /**< f(SMCLK)/2 */
\r
2624 #define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /**< f(SMCLK)/4 */
\r
2625 #define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /**< f(SMCLK)/8 */
\r
2626 #define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /**< f(SMCLK)/16 */
\r
2627 #define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /**< f(SMCLK)/32 */
\r
2628 #define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /**< f(SMCLK)/64 */
\r
2629 #define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /**< f(SMCLK)/128 */
\r
2630 /* CS_CTL2[LFXTDRIVE] Bits */
\r
2631 #define CS_CTL2_LFXTDRIVE_OFS ( 0) /**< LFXTDRIVE Bit Offset */
\r
2632 #define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /**< LFXTDRIVE Bit Mask */
\r
2633 #define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /**< LFXTDRIVE Bit 0 */
\r
2634 #define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /**< LFXTDRIVE Bit 1 */
\r
2635 #define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /**< Lowest drive strength and current consumption LFXT oscillator. */
\r
2636 #define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /**< Increased drive strength LFXT oscillator. */
\r
2637 #define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /**< Increased drive strength LFXT oscillator. */
\r
2638 #define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /**< Maximum drive strength and maximum current consumption LFXT oscillator. */
\r
2639 /* CS_CTL2[LFXTAGCOFF] Bits */
\r
2640 #define CS_CTL2_LFXTAGCOFF_OFS ( 7) /**< LFXTAGCOFF Bit Offset */
\r
2641 #define CS_CTL2_LFXTAGCOFF ((uint32_t)0x00000080) /**< Disables the automatic gain control of the LFXT crystal */
\r
2642 /* CS_CTL2[LFXT_EN] Bits */
\r
2643 #define CS_CTL2_LFXT_EN_OFS ( 8) /**< LFXT_EN Bit Offset */
\r
2644 #define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /**< Turns on the LFXT oscillator regardless if used as a clock resource */
\r
2645 /* CS_CTL2[LFXTBYPASS] Bits */
\r
2646 #define CS_CTL2_LFXTBYPASS_OFS ( 9) /**< LFXTBYPASS Bit Offset */
\r
2647 #define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /**< LFXT bypass select */
\r
2648 /* CS_CTL2[HFXTDRIVE] Bits */
\r
2649 #define CS_CTL2_HFXTDRIVE_OFS (16) /**< HFXTDRIVE Bit Offset */
\r
2650 #define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /**< HFXT oscillator drive selection */
\r
2651 /* CS_CTL2[HFXTFREQ] Bits */
\r
2652 #define CS_CTL2_HFXTFREQ_OFS (20) /**< HFXTFREQ Bit Offset */
\r
2653 #define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /**< HFXTFREQ Bit Mask */
\r
2654 #define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /**< HFXTFREQ Bit 0 */
\r
2655 #define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /**< HFXTFREQ Bit 1 */
\r
2656 #define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /**< HFXTFREQ Bit 2 */
\r
2657 #define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /**< 1 MHz to 4 MHz */
\r
2658 #define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /**< >4 MHz to 8 MHz */
\r
2659 #define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /**< >8 MHz to 16 MHz */
\r
2660 #define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /**< >16 MHz to 24 MHz */
\r
2661 #define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /**< >24 MHz to 32 MHz */
\r
2662 #define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /**< >32 MHz to 40 MHz */
\r
2663 #define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /**< >40 MHz to 48 MHz */
\r
2664 #define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /**< Reserved for future use. */
\r
2665 /* CS_CTL2[HFXT_EN] Bits */
\r
2666 #define CS_CTL2_HFXT_EN_OFS (24) /**< HFXT_EN Bit Offset */
\r
2667 #define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /**< Turns on the HFXT oscillator regardless if used as a clock resource */
\r
2668 /* CS_CTL2[HFXTBYPASS] Bits */
\r
2669 #define CS_CTL2_HFXTBYPASS_OFS (25) /**< HFXTBYPASS Bit Offset */
\r
2670 #define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /**< HFXT bypass select */
\r
2671 /* CS_CTL3[FCNTLF] Bits */
\r
2672 #define CS_CTL3_FCNTLF_OFS ( 0) /**< FCNTLF Bit Offset */
\r
2673 #define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /**< FCNTLF Bit Mask */
\r
2674 #define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /**< FCNTLF Bit 0 */
\r
2675 #define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /**< FCNTLF Bit 1 */
\r
2676 #define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /**< 4096 cycles */
\r
2677 #define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /**< 8192 cycles */
\r
2678 #define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /**< 16384 cycles */
\r
2679 #define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /**< 32768 cycles */
\r
2680 #define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /**< 4096 cycles */
\r
2681 #define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /**< 8192 cycles */
\r
2682 #define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /**< 16384 cycles */
\r
2683 #define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /**< 32768 cycles */
\r
2684 /* CS_CTL3[RFCNTLF] Bits */
\r
2685 #define CS_CTL3_RFCNTLF_OFS ( 2) /**< RFCNTLF Bit Offset */
\r
2686 #define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /**< Reset start fault counter for LFXT */
\r
2687 /* CS_CTL3[FCNTLF_EN] Bits */
\r
2688 #define CS_CTL3_FCNTLF_EN_OFS ( 3) /**< FCNTLF_EN Bit Offset */
\r
2689 #define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /**< Enable start fault counter for LFXT */
\r
2690 /* CS_CTL3[FCNTHF] Bits */
\r
2691 #define CS_CTL3_FCNTHF_OFS ( 4) /**< FCNTHF Bit Offset */
\r
2692 #define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /**< FCNTHF Bit Mask */
\r
2693 #define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /**< FCNTHF Bit 0 */
\r
2694 #define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /**< FCNTHF Bit 1 */
\r
2695 #define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /**< 2048 cycles */
\r
2696 #define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /**< 4096 cycles */
\r
2697 #define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /**< 8192 cycles */
\r
2698 #define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /**< 16384 cycles */
\r
2699 #define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /**< 2048 cycles */
\r
2700 #define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /**< 4096 cycles */
\r
2701 #define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /**< 8192 cycles */
\r
2702 #define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /**< 16384 cycles */
\r
2703 /* CS_CTL3[RFCNTHF] Bits */
\r
2704 #define CS_CTL3_RFCNTHF_OFS ( 6) /**< RFCNTHF Bit Offset */
\r
2705 #define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /**< Reset start fault counter for HFXT */
\r
2706 /* CS_CTL3[FCNTHF_EN] Bits */
\r
2707 #define CS_CTL3_FCNTHF_EN_OFS ( 7) /**< FCNTHF_EN Bit Offset */
\r
2708 #define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /**< Enable start fault counter for HFXT */
\r
2709 /* CS_CTL3[FCNTHF2] Bits */
\r
2710 #define CS_CTL3_FCNTHF2_OFS ( 8) /**< FCNTHF2 Bit Offset */
\r
2711 #define CS_CTL3_FCNTHF2_MASK ((uint32_t)0x00000300) /**< FCNTHF2 Bit Mask */
\r
2712 #define CS_CTL3_FCNTHF20 ((uint32_t)0x00000100) /**< FCNTHF2 Bit 0 */
\r
2713 #define CS_CTL3_FCNTHF21 ((uint32_t)0x00000200) /**< FCNTHF2 Bit 1 */
\r
2714 #define CS_CTL3_FCNTHF2_0 ((uint32_t)0x00000000) /**< 2048 cycles */
\r
2715 #define CS_CTL3_FCNTHF2_1 ((uint32_t)0x00000100) /**< 4096 cycles */
\r
2716 #define CS_CTL3_FCNTHF2_2 ((uint32_t)0x00000200) /**< 8192 cycles */
\r
2717 #define CS_CTL3_FCNTHF2_3 ((uint32_t)0x00000300) /**< 16384 cycles */
\r
2718 #define CS_CTL3_FCNTHF2__2048 ((uint32_t)0x00000000) /**< 2048 cycles */
\r
2719 #define CS_CTL3_FCNTHF2__4096 ((uint32_t)0x00000100) /**< 4096 cycles */
\r
2720 #define CS_CTL3_FCNTHF2__8192 ((uint32_t)0x00000200) /**< 8192 cycles */
\r
2721 #define CS_CTL3_FCNTHF2__16384 ((uint32_t)0x00000300) /**< 16384 cycles */
\r
2722 /* CS_CTL3[RFCNTHF2] Bits */
\r
2723 #define CS_CTL3_RFCNTHF2_OFS (10) /**< RFCNTHF2 Bit Offset */
\r
2724 #define CS_CTL3_RFCNTHF2 ((uint32_t)0x00000400) /**< Reset start fault counter for HFXT2 */
\r
2725 /* CS_CTL3[FCNTHF2_EN] Bits */
\r
2726 #define CS_CTL3_FCNTHF2_EN_OFS (11) /**< FCNTHF2_EN Bit Offset */
\r
2727 #define CS_CTL3_FCNTHF2_EN ((uint32_t)0x00000800) /**< Enable start fault counter for HFXT2 */
\r
2728 /* CS_CTL4[HFXT2DRIVE] Bits */
\r
2729 #define CS_CTL4_HFXT2DRIVE_OFS ( 0) /**< HFXT2DRIVE Bit Offset */
\r
2730 #define CS_CTL4_HFXT2DRIVE ((uint32_t)0x00000001) /**< HFXT2 oscillator current can be adjusted to its drive needs */
\r
2731 /* CS_CTL4[HFXT2FREQ] Bits */
\r
2732 #define CS_CTL4_HFXT2FREQ_OFS ( 4) /**< HFXT2FREQ Bit Offset */
\r
2733 #define CS_CTL4_HFXT2FREQ_MASK ((uint32_t)0x00000070) /**< HFXT2FREQ Bit Mask */
\r
2734 #define CS_CTL4_HFXT2FREQ0 ((uint32_t)0x00000010) /**< HFXT2FREQ Bit 0 */
\r
2735 #define CS_CTL4_HFXT2FREQ1 ((uint32_t)0x00000020) /**< HFXT2FREQ Bit 1 */
\r
2736 #define CS_CTL4_HFXT2FREQ2 ((uint32_t)0x00000040) /**< HFXT2FREQ Bit 2 */
\r
2737 #define CS_CTL4_HFXT2FREQ_0 ((uint32_t)0x00000000) /**< 1 MHz to 4 MHz */
\r
2738 #define CS_CTL4_HFXT2FREQ_1 ((uint32_t)0x00000010) /**< >4 MHz to 8 MHz */
\r
2739 #define CS_CTL4_HFXT2FREQ_2 ((uint32_t)0x00000020) /**< >8 MHz to 16 MHz */
\r
2740 #define CS_CTL4_HFXT2FREQ_3 ((uint32_t)0x00000030) /**< >16 MHz to 24 MHz */
\r
2741 #define CS_CTL4_HFXT2FREQ_4 ((uint32_t)0x00000040) /**< >24 MHz to 32 MHz */
\r
2742 #define CS_CTL4_HFXT2FREQ_5 ((uint32_t)0x00000050) /**< >32 MHz to 40 MHz */
\r
2743 #define CS_CTL4_HFXT2FREQ_6 ((uint32_t)0x00000060) /**< >40 MHz to 48 MHz */
\r
2744 #define CS_CTL4_HFXT2FREQ_7 ((uint32_t)0x00000070) /**< Reserved for future use. */
\r
2745 /* CS_CTL4[HFXT2_EN] Bits */
\r
2746 #define CS_CTL4_HFXT2_EN_OFS ( 8) /**< HFXT2_EN Bit Offset */
\r
2747 #define CS_CTL4_HFXT2_EN ((uint32_t)0x00000100) /**< Turns on the HFXT2 oscillator */
\r
2748 /* CS_CTL4[HFXT2BYPASS] Bits */
\r
2749 #define CS_CTL4_HFXT2BYPASS_OFS ( 9) /**< HFXT2BYPASS Bit Offset */
\r
2750 #define CS_CTL4_HFXT2BYPASS ((uint32_t)0x00000200) /**< HFXT2 bypass select */
\r
2751 /* CS_CTL5[REFCNTSEL] Bits */
\r
2752 #define CS_CTL5_REFCNTSEL_OFS ( 0) /**< REFCNTSEL Bit Offset */
\r
2753 #define CS_CTL5_REFCNTSEL_MASK ((uint32_t)0x00000007) /**< REFCNTSEL Bit Mask */
\r
2754 /* CS_CTL5[REFCNTPS] Bits */
\r
2755 #define CS_CTL5_REFCNTPS_OFS ( 3) /**< REFCNTPS Bit Offset */
\r
2756 #define CS_CTL5_REFCNTPS_MASK ((uint32_t)0x00000038) /**< REFCNTPS Bit Mask */
\r
2757 /* CS_CTL5[CALSTART] Bits */
\r
2758 #define CS_CTL5_CALSTART_OFS ( 7) /**< CALSTART Bit Offset */
\r
2759 #define CS_CTL5_CALSTART ((uint32_t)0x00000080) /**< Start clock calibration counters */
\r
2760 /* CS_CTL5[PERCNTSEL] Bits */
\r
2761 #define CS_CTL5_PERCNTSEL_OFS ( 8) /**< PERCNTSEL Bit Offset */
\r
2762 #define CS_CTL5_PERCNTSEL_MASK ((uint32_t)0x00000700) /**< PERCNTSEL Bit Mask */
\r
2763 /* CS_CTL6[PERCNT] Bits */
\r
2764 #define CS_CTL6_PERCNT_OFS ( 0) /**< PERCNT Bit Offset */
\r
2765 #define CS_CTL6_PERCNT_MASK ((uint32_t)0x0000FFFF) /**< PERCNT Bit Mask */
\r
2766 /* CS_CTL7[REFCNT] Bits */
\r
2767 #define CS_CTL7_REFCNT_OFS ( 0) /**< REFCNT Bit Offset */
\r
2768 #define CS_CTL7_REFCNT_MASK ((uint32_t)0x0000FFFF) /**< REFCNT Bit Mask */
\r
2769 /* CS_CLKEN[ACLK_EN] Bits */
\r
2770 #define CS_CLKEN_ACLK_EN_OFS ( 0) /**< ACLK_EN Bit Offset */
\r
2771 #define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /**< ACLK system clock conditional request enable */
\r
2772 /* CS_CLKEN[MCLK_EN] Bits */
\r
2773 #define CS_CLKEN_MCLK_EN_OFS ( 1) /**< MCLK_EN Bit Offset */
\r
2774 #define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /**< MCLK system clock conditional request enable */
\r
2775 /* CS_CLKEN[HSMCLK_EN] Bits */
\r
2776 #define CS_CLKEN_HSMCLK_EN_OFS ( 2) /**< HSMCLK_EN Bit Offset */
\r
2777 #define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /**< HSMCLK system clock conditional request enable */
\r
2778 /* CS_CLKEN[SMCLK_EN] Bits */
\r
2779 #define CS_CLKEN_SMCLK_EN_OFS ( 3) /**< SMCLK_EN Bit Offset */
\r
2780 #define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /**< SMCLK system clock conditional request enable */
\r
2781 /* CS_CLKEN[VLO_EN] Bits */
\r
2782 #define CS_CLKEN_VLO_EN_OFS ( 8) /**< VLO_EN Bit Offset */
\r
2783 #define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /**< Turns on the VLO oscillator */
\r
2784 /* CS_CLKEN[REFO_EN] Bits */
\r
2785 #define CS_CLKEN_REFO_EN_OFS ( 9) /**< REFO_EN Bit Offset */
\r
2786 #define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /**< Turns on the REFO oscillator */
\r
2787 /* CS_CLKEN[MODOSC_EN] Bits */
\r
2788 #define CS_CLKEN_MODOSC_EN_OFS (10) /**< MODOSC_EN Bit Offset */
\r
2789 #define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /**< Turns on the MODOSC oscillator */
\r
2790 /* CS_CLKEN[REFOFSEL] Bits */
\r
2791 #define CS_CLKEN_REFOFSEL_OFS (15) /**< REFOFSEL Bit Offset */
\r
2792 #define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /**< Selects REFO nominal frequency */
\r
2793 /* CS_STAT[DCO_ON] Bits */
\r
2794 #define CS_STAT_DCO_ON_OFS ( 0) /**< DCO_ON Bit Offset */
\r
2795 #define CS_STAT_DCO_ON ((uint32_t)0x00000001) /**< DCO status */
\r
2796 /* CS_STAT[DCOBIAS_ON] Bits */
\r
2797 #define CS_STAT_DCOBIAS_ON_OFS ( 1) /**< DCOBIAS_ON Bit Offset */
\r
2798 #define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /**< DCO bias status */
\r
2799 /* CS_STAT[HFXT_ON] Bits */
\r
2800 #define CS_STAT_HFXT_ON_OFS ( 2) /**< HFXT_ON Bit Offset */
\r
2801 #define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /**< HFXT status */
\r
2802 /* CS_STAT[HFXT2_ON] Bits */
\r
2803 #define CS_STAT_HFXT2_ON_OFS ( 3) /**< HFXT2_ON Bit Offset */
\r
2804 #define CS_STAT_HFXT2_ON ((uint32_t)0x00000008) /**< HFXT2 status */
\r
2805 /* CS_STAT[MODOSC_ON] Bits */
\r
2806 #define CS_STAT_MODOSC_ON_OFS ( 4) /**< MODOSC_ON Bit Offset */
\r
2807 #define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /**< MODOSC status */
\r
2808 /* CS_STAT[VLO_ON] Bits */
\r
2809 #define CS_STAT_VLO_ON_OFS ( 5) /**< VLO_ON Bit Offset */
\r
2810 #define CS_STAT_VLO_ON ((uint32_t)0x00000020) /**< VLO status */
\r
2811 /* CS_STAT[LFXT_ON] Bits */
\r
2812 #define CS_STAT_LFXT_ON_OFS ( 6) /**< LFXT_ON Bit Offset */
\r
2813 #define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /**< LFXT status */
\r
2814 /* CS_STAT[REFO_ON] Bits */
\r
2815 #define CS_STAT_REFO_ON_OFS ( 7) /**< REFO_ON Bit Offset */
\r
2816 #define CS_STAT_REFO_ON ((uint32_t)0x00000080) /**< REFO status */
\r
2817 /* CS_STAT[ACLK_ON] Bits */
\r
2818 #define CS_STAT_ACLK_ON_OFS (16) /**< ACLK_ON Bit Offset */
\r
2819 #define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /**< ACLK system clock status */
\r
2820 /* CS_STAT[MCLK_ON] Bits */
\r
2821 #define CS_STAT_MCLK_ON_OFS (17) /**< MCLK_ON Bit Offset */
\r
2822 #define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /**< MCLK system clock status */
\r
2823 /* CS_STAT[HSMCLK_ON] Bits */
\r
2824 #define CS_STAT_HSMCLK_ON_OFS (18) /**< HSMCLK_ON Bit Offset */
\r
2825 #define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /**< HSMCLK system clock status */
\r
2826 /* CS_STAT[SMCLK_ON] Bits */
\r
2827 #define CS_STAT_SMCLK_ON_OFS (19) /**< SMCLK_ON Bit Offset */
\r
2828 #define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /**< SMCLK system clock status */
\r
2829 /* CS_STAT[MODCLK_ON] Bits */
\r
2830 #define CS_STAT_MODCLK_ON_OFS (20) /**< MODCLK_ON Bit Offset */
\r
2831 #define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /**< MODCLK system clock status */
\r
2832 /* CS_STAT[VLOCLK_ON] Bits */
\r
2833 #define CS_STAT_VLOCLK_ON_OFS (21) /**< VLOCLK_ON Bit Offset */
\r
2834 #define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /**< VLOCLK system clock status */
\r
2835 /* CS_STAT[LFXTCLK_ON] Bits */
\r
2836 #define CS_STAT_LFXTCLK_ON_OFS (22) /**< LFXTCLK_ON Bit Offset */
\r
2837 #define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /**< LFXTCLK system clock status */
\r
2838 /* CS_STAT[REFOCLK_ON] Bits */
\r
2839 #define CS_STAT_REFOCLK_ON_OFS (23) /**< REFOCLK_ON Bit Offset */
\r
2840 #define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /**< REFOCLK system clock status */
\r
2841 /* CS_STAT[ACLK_READY] Bits */
\r
2842 #define CS_STAT_ACLK_READY_OFS (24) /**< ACLK_READY Bit Offset */
\r
2843 #define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /**< ACLK Ready status */
\r
2844 /* CS_STAT[MCLK_READY] Bits */
\r
2845 #define CS_STAT_MCLK_READY_OFS (25) /**< MCLK_READY Bit Offset */
\r
2846 #define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /**< MCLK Ready status */
\r
2847 /* CS_STAT[HSMCLK_READY] Bits */
\r
2848 #define CS_STAT_HSMCLK_READY_OFS (26) /**< HSMCLK_READY Bit Offset */
\r
2849 #define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /**< HSMCLK Ready status */
\r
2850 /* CS_STAT[SMCLK_READY] Bits */
\r
2851 #define CS_STAT_SMCLK_READY_OFS (27) /**< SMCLK_READY Bit Offset */
\r
2852 #define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /**< SMCLK Ready status */
\r
2853 /* CS_STAT[BCLK_READY] Bits */
\r
2854 #define CS_STAT_BCLK_READY_OFS (28) /**< BCLK_READY Bit Offset */
\r
2855 #define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /**< BCLK Ready status */
\r
2856 /* CS_IE[LFXTIE] Bits */
\r
2857 #define CS_IE_LFXTIE_OFS ( 0) /**< LFXTIE Bit Offset */
\r
2858 #define CS_IE_LFXTIE ((uint32_t)0x00000001) /**< LFXT oscillator fault flag interrupt enable */
\r
2859 /* CS_IE[HFXTIE] Bits */
\r
2860 #define CS_IE_HFXTIE_OFS ( 1) /**< HFXTIE Bit Offset */
\r
2861 #define CS_IE_HFXTIE ((uint32_t)0x00000002) /**< HFXT oscillator fault flag interrupt enable */
\r
2862 /* CS_IE[HFXT2IE] Bits */
\r
2863 #define CS_IE_HFXT2IE_OFS ( 2) /**< HFXT2IE Bit Offset */
\r
2864 #define CS_IE_HFXT2IE ((uint32_t)0x00000004) /**< HFXT2 oscillator fault flag interrupt enable */
\r
2865 /* CS_IE[DCOR_OPNIE] Bits */
\r
2866 #define CS_IE_DCOR_OPNIE_OFS ( 6) /**< DCOR_OPNIE Bit Offset */
\r
2867 #define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /**< DCO external resistor open circuit fault flag interrupt enable. */
\r
2868 /* CS_IE[FCNTLFIE] Bits */
\r
2869 #define CS_IE_FCNTLFIE_OFS ( 8) /**< FCNTLFIE Bit Offset */
\r
2870 #define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /**< Start fault counter interrupt enable LFXT */
\r
2871 /* CS_IE[FCNTHFIE] Bits */
\r
2872 #define CS_IE_FCNTHFIE_OFS ( 9) /**< FCNTHFIE Bit Offset */
\r
2873 #define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /**< Start fault counter interrupt enable HFXT */
\r
2874 /* CS_IE[FCNTHF2IE] Bits */
\r
2875 #define CS_IE_FCNTHF2IE_OFS (10) /**< FCNTHF2IE Bit Offset */
\r
2876 #define CS_IE_FCNTHF2IE ((uint32_t)0x00000400) /**< Start fault counter interrupt enable HFXT2 */
\r
2877 /* CS_IE[PLLOOLIE] Bits */
\r
2878 #define CS_IE_PLLOOLIE_OFS (12) /**< PLLOOLIE Bit Offset */
\r
2879 #define CS_IE_PLLOOLIE ((uint32_t)0x00001000) /**< PLL out-of-lock interrupt enable */
\r
2880 /* CS_IE[PLLLOSIE] Bits */
\r
2881 #define CS_IE_PLLLOSIE_OFS (13) /**< PLLLOSIE Bit Offset */
\r
2882 #define CS_IE_PLLLOSIE ((uint32_t)0x00002000) /**< PLL loss-of-signal interrupt enable */
\r
2883 /* CS_IE[PLLOORIE] Bits */
\r
2884 #define CS_IE_PLLOORIE_OFS (14) /**< PLLOORIE Bit Offset */
\r
2885 #define CS_IE_PLLOORIE ((uint32_t)0x00004000) /**< PLL out-of-range interrupt enable */
\r
2886 /* CS_IE[CALIE] Bits */
\r
2887 #define CS_IE_CALIE_OFS (15) /**< CALIE Bit Offset */
\r
2888 #define CS_IE_CALIE ((uint32_t)0x00008000) /**< REFCNT period counter interrupt enable */
\r
2889 /* CS_IFG[LFXTIFG] Bits */
\r
2890 #define CS_IFG_LFXTIFG_OFS ( 0) /**< LFXTIFG Bit Offset */
\r
2891 #define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /**< LFXT oscillator fault flag */
\r
2892 /* CS_IFG[HFXTIFG] Bits */
\r
2893 #define CS_IFG_HFXTIFG_OFS ( 1) /**< HFXTIFG Bit Offset */
\r
2894 #define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /**< HFXT oscillator fault flag */
\r
2895 /* CS_IFG[HFXT2IFG] Bits */
\r
2896 #define CS_IFG_HFXT2IFG_OFS ( 2) /**< HFXT2IFG Bit Offset */
\r
2897 #define CS_IFG_HFXT2IFG ((uint32_t)0x00000004) /**< HFXT2 oscillator fault flag */
\r
2898 /* CS_IFG[DCOR_SHTIFG] Bits */
\r
2899 #define CS_IFG_DCOR_SHTIFG_OFS ( 5) /**< DCOR_SHTIFG Bit Offset */
\r
2900 #define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /**< DCO external resistor short circuit fault flag. */
\r
2901 /* CS_IFG[DCOR_OPNIFG] Bits */
\r
2902 #define CS_IFG_DCOR_OPNIFG_OFS ( 6) /**< DCOR_OPNIFG Bit Offset */
\r
2903 #define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /**< DCO external resistor open circuit fault flag. */
\r
2904 /* CS_IFG[FCNTLFIFG] Bits */
\r
2905 #define CS_IFG_FCNTLFIFG_OFS ( 8) /**< FCNTLFIFG Bit Offset */
\r
2906 #define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /**< Start fault counter interrupt flag LFXT */
\r
2907 /* CS_IFG[FCNTHFIFG] Bits */
\r
2908 #define CS_IFG_FCNTHFIFG_OFS ( 9) /**< FCNTHFIFG Bit Offset */
\r
2909 #define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /**< Start fault counter interrupt flag HFXT */
\r
2910 /* CS_IFG[FCNTHF2IFG] Bits */
\r
2911 #define CS_IFG_FCNTHF2IFG_OFS (11) /**< FCNTHF2IFG Bit Offset */
\r
2912 #define CS_IFG_FCNTHF2IFG ((uint32_t)0x00000800) /**< Start fault counter interrupt flag HFXT2 */
\r
2913 /* CS_IFG[PLLOOLIFG] Bits */
\r
2914 #define CS_IFG_PLLOOLIFG_OFS (12) /**< PLLOOLIFG Bit Offset */
\r
2915 #define CS_IFG_PLLOOLIFG ((uint32_t)0x00001000) /**< PLL out-of-lock interrupt flag */
\r
2916 /* CS_IFG[PLLLOSIFG] Bits */
\r
2917 #define CS_IFG_PLLLOSIFG_OFS (13) /**< PLLLOSIFG Bit Offset */
\r
2918 #define CS_IFG_PLLLOSIFG ((uint32_t)0x00002000) /**< PLL loss-of-signal interrupt flag */
\r
2919 /* CS_IFG[PLLOORIFG] Bits */
\r
2920 #define CS_IFG_PLLOORIFG_OFS (14) /**< PLLOORIFG Bit Offset */
\r
2921 #define CS_IFG_PLLOORIFG ((uint32_t)0x00004000) /**< PLL out-of-range interrupt flag */
\r
2922 /* CS_IFG[CALIFG] Bits */
\r
2923 #define CS_IFG_CALIFG_OFS (15) /**< CALIFG Bit Offset */
\r
2924 #define CS_IFG_CALIFG ((uint32_t)0x00008000) /**< REFCNT period counter expired */
\r
2925 /* CS_CLRIFG[CLR_LFXTIFG] Bits */
\r
2926 #define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /**< CLR_LFXTIFG Bit Offset */
\r
2927 #define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /**< Clear LFXT oscillator fault interrupt flag */
\r
2928 /* CS_CLRIFG[CLR_HFXTIFG] Bits */
\r
2929 #define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /**< CLR_HFXTIFG Bit Offset */
\r
2930 #define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /**< Clear HFXT oscillator fault interrupt flag */
\r
2931 /* CS_CLRIFG[CLR_HFXT2IFG] Bits */
\r
2932 #define CS_CLRIFG_CLR_HFXT2IFG_OFS ( 2) /**< CLR_HFXT2IFG Bit Offset */
\r
2933 #define CS_CLRIFG_CLR_HFXT2IFG ((uint32_t)0x00000004) /**< Clear HFXT2 oscillator fault interrupt flag */
\r
2934 /* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */
\r
2935 #define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /**< CLR_DCOR_OPNIFG Bit Offset */
\r
2936 #define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /**< Clear DCO external resistor open circuit fault interrupt flag. */
\r
2937 /* CS_CLRIFG[CLR_CALIFG] Bits */
\r
2938 #define CS_CLRIFG_CLR_CALIFG_OFS (15) /**< CLR_CALIFG Bit Offset */
\r
2939 #define CS_CLRIFG_CLR_CALIFG ((uint32_t)0x00008000) /**< REFCNT period counter clear interrupt flag */
\r
2940 /* CS_CLRIFG[CLR_FCNTLFIFG] Bits */
\r
2941 #define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /**< CLR_FCNTLFIFG Bit Offset */
\r
2942 #define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /**< Start fault counter clear interrupt flag LFXT */
\r
2943 /* CS_CLRIFG[CLR_FCNTHFIFG] Bits */
\r
2944 #define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /**< CLR_FCNTHFIFG Bit Offset */
\r
2945 #define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /**< Start fault counter clear interrupt flag HFXT */
\r
2946 /* CS_CLRIFG[CLR_FCNTHF2IFG] Bits */
\r
2947 #define CS_CLRIFG_CLR_FCNTHF2IFG_OFS (10) /**< CLR_FCNTHF2IFG Bit Offset */
\r
2948 #define CS_CLRIFG_CLR_FCNTHF2IFG ((uint32_t)0x00000400) /**< Start fault counter clear interrupt flag HFXT2 */
\r
2949 /* CS_CLRIFG[CLR_PLLOOLIFG] Bits */
\r
2950 #define CS_CLRIFG_CLR_PLLOOLIFG_OFS (12) /**< CLR_PLLOOLIFG Bit Offset */
\r
2951 #define CS_CLRIFG_CLR_PLLOOLIFG ((uint32_t)0x00001000) /**< PLL out-of-lock clear interrupt flag */
\r
2952 /* CS_CLRIFG[CLR_PLLLOSIFG] Bits */
\r
2953 #define CS_CLRIFG_CLR_PLLLOSIFG_OFS (13) /**< CLR_PLLLOSIFG Bit Offset */
\r
2954 #define CS_CLRIFG_CLR_PLLLOSIFG ((uint32_t)0x00002000) /**< PLL loss-of-signal clear interrupt flag */
\r
2955 /* CS_CLRIFG[CLR_PLLOORIFG] Bits */
\r
2956 #define CS_CLRIFG_CLR_PLLOORIFG_OFS (14) /**< CLR_PLLOORIFG Bit Offset */
\r
2957 #define CS_CLRIFG_CLR_PLLOORIFG ((uint32_t)0x00004000) /**< PLL out-of-range clear interrupt flag */
\r
2958 /* CS_SETIFG[SET_LFXTIFG] Bits */
\r
2959 #define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /**< SET_LFXTIFG Bit Offset */
\r
2960 #define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /**< Set LFXT oscillator fault interrupt flag */
\r
2961 /* CS_SETIFG[SET_HFXTIFG] Bits */
\r
2962 #define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /**< SET_HFXTIFG Bit Offset */
\r
2963 #define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /**< Set HFXT oscillator fault interrupt flag */
\r
2964 /* CS_SETIFG[SET_HFXT2IFG] Bits */
\r
2965 #define CS_SETIFG_SET_HFXT2IFG_OFS ( 2) /**< SET_HFXT2IFG Bit Offset */
\r
2966 #define CS_SETIFG_SET_HFXT2IFG ((uint32_t)0x00000004) /**< Set HFXT2 oscillator fault interrupt flag */
\r
2967 /* CS_SETIFG[SET_DCOR_OPNIFG] Bits */
\r
2968 #define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /**< SET_DCOR_OPNIFG Bit Offset */
\r
2969 #define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /**< Set DCO external resistor open circuit fault interrupt flag. */
\r
2970 /* CS_SETIFG[SET_CALIFG] Bits */
\r
2971 #define CS_SETIFG_SET_CALIFG_OFS (15) /**< SET_CALIFG Bit Offset */
\r
2972 #define CS_SETIFG_SET_CALIFG ((uint32_t)0x00008000) /**< REFCNT period counter set interrupt flag */
\r
2973 /* CS_SETIFG[SET_FCNTHFIFG] Bits */
\r
2974 #define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /**< SET_FCNTHFIFG Bit Offset */
\r
2975 #define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /**< Start fault counter set interrupt flag HFXT */
\r
2976 /* CS_SETIFG[SET_FCNTHF2IFG] Bits */
\r
2977 #define CS_SETIFG_SET_FCNTHF2IFG_OFS (10) /**< SET_FCNTHF2IFG Bit Offset */
\r
2978 #define CS_SETIFG_SET_FCNTHF2IFG ((uint32_t)0x00000400) /**< Start fault counter set interrupt flag HFXT2 */
\r
2979 /* CS_SETIFG[SET_FCNTLFIFG] Bits */
\r
2980 #define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /**< SET_FCNTLFIFG Bit Offset */
\r
2981 #define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /**< Start fault counter set interrupt flag LFXT */
\r
2982 /* CS_SETIFG[SET_PLLOOLIFG] Bits */
\r
2983 #define CS_SETIFG_SET_PLLOOLIFG_OFS (12) /**< SET_PLLOOLIFG Bit Offset */
\r
2984 #define CS_SETIFG_SET_PLLOOLIFG ((uint32_t)0x00001000) /**< PLL out-of-lock set interrupt flag */
\r
2985 /* CS_SETIFG[SET_PLLLOSIFG] Bits */
\r
2986 #define CS_SETIFG_SET_PLLLOSIFG_OFS (13) /**< SET_PLLLOSIFG Bit Offset */
\r
2987 #define CS_SETIFG_SET_PLLLOSIFG ((uint32_t)0x00002000) /**< PLL loss-of-signal set interrupt flag */
\r
2988 /* CS_SETIFG[SET_PLLOORIFG] Bits */
\r
2989 #define CS_SETIFG_SET_PLLOORIFG_OFS (14) /**< SET_PLLOORIFG Bit Offset */
\r
2990 #define CS_SETIFG_SET_PLLOORIFG ((uint32_t)0x00004000) /**< PLL out-of-range set interrupt flag */
\r
2991 /* CS_DCOERCAL0[DCO_TCCAL] Bits */
\r
2992 #define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /**< DCO_TCCAL Bit Offset */
\r
2993 #define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /**< DCO_TCCAL Bit Mask */
\r
2994 /* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */
\r
2995 #define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /**< DCO_FCAL_RSEL04 Bit Offset */
\r
2996 #define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /**< DCO_FCAL_RSEL04 Bit Mask */
\r
2997 /* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */
\r
2998 #define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /**< DCO_FCAL_RSEL5 Bit Offset */
\r
2999 #define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /**< DCO_FCAL_RSEL5 Bit Mask */
\r
3001 /* Pre-defined bitfield values */
\r
3002 #define CS_KEY_VAL ((uint32_t)0x0000695A) /* CS control key value */
\r
3004 /******************************************************************************
\r
3006 ******************************************************************************/
\r
3007 /* DIO_IV[IV] Bits */
\r
3008 #define DIO_PORT_IV_OFS ( 0) /**< DIO Port IV Bit Offset */
\r
3009 #define DIO_PORT_IV_MASK ((uint16_t)0x001F) /**< DIO Port IV Bit Mask */
\r
3010 #define DIO_PORT_IV0 ((uint16_t)0x0001) /**< DIO Port IV Bit 0 */
\r
3011 #define DIO_PORT_IV1 ((uint16_t)0x0002) /**< DIO Port IV Bit 1 */
\r
3012 #define DIO_PORT_IV2 ((uint16_t)0x0004) /**< DIO Port IV Bit 2 */
\r
3013 #define DIO_PORT_IV3 ((uint16_t)0x0008) /**< DIO Port IV Bit 3 */
\r
3014 #define DIO_PORT_IV4 ((uint16_t)0x0010) /**< DIO Port IV Bit 4 */
\r
3015 #define DIO_PORT_IV_0 ((uint16_t)0x0000) /**< No interrupt pending */
\r
3016 #define DIO_PORT_IV_2 ((uint16_t)0x0002) /**< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */
\r
3017 /* Priority: Highest */
\r
3018 #define DIO_PORT_IV_4 ((uint16_t)0x0004) /**< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */
\r
3019 #define DIO_PORT_IV_6 ((uint16_t)0x0006) /**< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */
\r
3020 #define DIO_PORT_IV_8 ((uint16_t)0x0008) /**< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */
\r
3021 #define DIO_PORT_IV_10 ((uint16_t)0x000A) /**< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */
\r
3022 #define DIO_PORT_IV_12 ((uint16_t)0x000C) /**< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */
\r
3023 #define DIO_PORT_IV_14 ((uint16_t)0x000E) /**< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */
\r
3024 #define DIO_PORT_IV_16 ((uint16_t)0x0010) /**< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */
\r
3025 /* Priority: Lowest */
\r
3026 #define DIO_PORT_IV__NONE ((uint16_t)0x0000) /**< No interrupt pending */
\r
3027 #define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /**< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */
\r
3028 /* Priority: Highest */
\r
3029 #define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /**< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */
\r
3030 #define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /**< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */
\r
3031 #define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /**< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */
\r
3032 #define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /**< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */
\r
3033 #define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /**< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */
\r
3034 #define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /**< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */
\r
3035 #define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /**< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */
\r
3036 /* Priority: Lowest */
\r
3039 /******************************************************************************
\r
3041 ******************************************************************************/
\r
3042 /* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */
\r
3043 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /**< NUM_DMA_CHANNELS Bit Offset */
\r
3044 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /**< NUM_DMA_CHANNELS Bit Mask */
\r
3045 /* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */
\r
3046 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /**< NUM_SRC_PER_CHANNEL Bit Offset */
\r
3047 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /**< NUM_SRC_PER_CHANNEL Bit Mask */
\r
3048 /* DMA_SW_CHTRIG[CH0] Bits */
\r
3049 #define DMA_SW_CHTRIG_CH0_OFS ( 0) /**< CH0 Bit Offset */
\r
3050 #define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /**< Write 1, triggers DMA_CHANNEL0 */
\r
3051 /* DMA_SW_CHTRIG[CH1] Bits */
\r
3052 #define DMA_SW_CHTRIG_CH1_OFS ( 1) /**< CH1 Bit Offset */
\r
3053 #define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /**< Write 1, triggers DMA_CHANNEL1 */
\r
3054 /* DMA_SW_CHTRIG[CH2] Bits */
\r
3055 #define DMA_SW_CHTRIG_CH2_OFS ( 2) /**< CH2 Bit Offset */
\r
3056 #define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /**< Write 1, triggers DMA_CHANNEL2 */
\r
3057 /* DMA_SW_CHTRIG[CH3] Bits */
\r
3058 #define DMA_SW_CHTRIG_CH3_OFS ( 3) /**< CH3 Bit Offset */
\r
3059 #define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /**< Write 1, triggers DMA_CHANNEL3 */
\r
3060 /* DMA_SW_CHTRIG[CH4] Bits */
\r
3061 #define DMA_SW_CHTRIG_CH4_OFS ( 4) /**< CH4 Bit Offset */
\r
3062 #define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /**< Write 1, triggers DMA_CHANNEL4 */
\r
3063 /* DMA_SW_CHTRIG[CH5] Bits */
\r
3064 #define DMA_SW_CHTRIG_CH5_OFS ( 5) /**< CH5 Bit Offset */
\r
3065 #define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /**< Write 1, triggers DMA_CHANNEL5 */
\r
3066 /* DMA_SW_CHTRIG[CH6] Bits */
\r
3067 #define DMA_SW_CHTRIG_CH6_OFS ( 6) /**< CH6 Bit Offset */
\r
3068 #define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /**< Write 1, triggers DMA_CHANNEL6 */
\r
3069 /* DMA_SW_CHTRIG[CH7] Bits */
\r
3070 #define DMA_SW_CHTRIG_CH7_OFS ( 7) /**< CH7 Bit Offset */
\r
3071 #define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /**< Write 1, triggers DMA_CHANNEL7 */
\r
3072 /* DMA_SW_CHTRIG[CH8] Bits */
\r
3073 #define DMA_SW_CHTRIG_CH8_OFS ( 8) /**< CH8 Bit Offset */
\r
3074 #define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /**< Write 1, triggers DMA_CHANNEL8 */
\r
3075 /* DMA_SW_CHTRIG[CH9] Bits */
\r
3076 #define DMA_SW_CHTRIG_CH9_OFS ( 9) /**< CH9 Bit Offset */
\r
3077 #define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /**< Write 1, triggers DMA_CHANNEL9 */
\r
3078 /* DMA_SW_CHTRIG[CH10] Bits */
\r
3079 #define DMA_SW_CHTRIG_CH10_OFS (10) /**< CH10 Bit Offset */
\r
3080 #define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /**< Write 1, triggers DMA_CHANNEL10 */
\r
3081 /* DMA_SW_CHTRIG[CH11] Bits */
\r
3082 #define DMA_SW_CHTRIG_CH11_OFS (11) /**< CH11 Bit Offset */
\r
3083 #define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /**< Write 1, triggers DMA_CHANNEL11 */
\r
3084 /* DMA_SW_CHTRIG[CH12] Bits */
\r
3085 #define DMA_SW_CHTRIG_CH12_OFS (12) /**< CH12 Bit Offset */
\r
3086 #define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /**< Write 1, triggers DMA_CHANNEL12 */
\r
3087 /* DMA_SW_CHTRIG[CH13] Bits */
\r
3088 #define DMA_SW_CHTRIG_CH13_OFS (13) /**< CH13 Bit Offset */
\r
3089 #define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /**< Write 1, triggers DMA_CHANNEL13 */
\r
3090 /* DMA_SW_CHTRIG[CH14] Bits */
\r
3091 #define DMA_SW_CHTRIG_CH14_OFS (14) /**< CH14 Bit Offset */
\r
3092 #define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /**< Write 1, triggers DMA_CHANNEL14 */
\r
3093 /* DMA_SW_CHTRIG[CH15] Bits */
\r
3094 #define DMA_SW_CHTRIG_CH15_OFS (15) /**< CH15 Bit Offset */
\r
3095 #define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /**< Write 1, triggers DMA_CHANNEL15 */
\r
3096 /* DMA_SW_CHTRIG[CH16] Bits */
\r
3097 #define DMA_SW_CHTRIG_CH16_OFS (16) /**< CH16 Bit Offset */
\r
3098 #define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /**< Write 1, triggers DMA_CHANNEL16 */
\r
3099 /* DMA_SW_CHTRIG[CH17] Bits */
\r
3100 #define DMA_SW_CHTRIG_CH17_OFS (17) /**< CH17 Bit Offset */
\r
3101 #define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /**< Write 1, triggers DMA_CHANNEL17 */
\r
3102 /* DMA_SW_CHTRIG[CH18] Bits */
\r
3103 #define DMA_SW_CHTRIG_CH18_OFS (18) /**< CH18 Bit Offset */
\r
3104 #define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /**< Write 1, triggers DMA_CHANNEL18 */
\r
3105 /* DMA_SW_CHTRIG[CH19] Bits */
\r
3106 #define DMA_SW_CHTRIG_CH19_OFS (19) /**< CH19 Bit Offset */
\r
3107 #define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /**< Write 1, triggers DMA_CHANNEL19 */
\r
3108 /* DMA_SW_CHTRIG[CH20] Bits */
\r
3109 #define DMA_SW_CHTRIG_CH20_OFS (20) /**< CH20 Bit Offset */
\r
3110 #define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /**< Write 1, triggers DMA_CHANNEL20 */
\r
3111 /* DMA_SW_CHTRIG[CH21] Bits */
\r
3112 #define DMA_SW_CHTRIG_CH21_OFS (21) /**< CH21 Bit Offset */
\r
3113 #define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /**< Write 1, triggers DMA_CHANNEL21 */
\r
3114 /* DMA_SW_CHTRIG[CH22] Bits */
\r
3115 #define DMA_SW_CHTRIG_CH22_OFS (22) /**< CH22 Bit Offset */
\r
3116 #define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /**< Write 1, triggers DMA_CHANNEL22 */
\r
3117 /* DMA_SW_CHTRIG[CH23] Bits */
\r
3118 #define DMA_SW_CHTRIG_CH23_OFS (23) /**< CH23 Bit Offset */
\r
3119 #define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /**< Write 1, triggers DMA_CHANNEL23 */
\r
3120 /* DMA_SW_CHTRIG[CH24] Bits */
\r
3121 #define DMA_SW_CHTRIG_CH24_OFS (24) /**< CH24 Bit Offset */
\r
3122 #define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /**< Write 1, triggers DMA_CHANNEL24 */
\r
3123 /* DMA_SW_CHTRIG[CH25] Bits */
\r
3124 #define DMA_SW_CHTRIG_CH25_OFS (25) /**< CH25 Bit Offset */
\r
3125 #define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /**< Write 1, triggers DMA_CHANNEL25 */
\r
3126 /* DMA_SW_CHTRIG[CH26] Bits */
\r
3127 #define DMA_SW_CHTRIG_CH26_OFS (26) /**< CH26 Bit Offset */
\r
3128 #define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /**< Write 1, triggers DMA_CHANNEL26 */
\r
3129 /* DMA_SW_CHTRIG[CH27] Bits */
\r
3130 #define DMA_SW_CHTRIG_CH27_OFS (27) /**< CH27 Bit Offset */
\r
3131 #define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /**< Write 1, triggers DMA_CHANNEL27 */
\r
3132 /* DMA_SW_CHTRIG[CH28] Bits */
\r
3133 #define DMA_SW_CHTRIG_CH28_OFS (28) /**< CH28 Bit Offset */
\r
3134 #define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /**< Write 1, triggers DMA_CHANNEL28 */
\r
3135 /* DMA_SW_CHTRIG[CH29] Bits */
\r
3136 #define DMA_SW_CHTRIG_CH29_OFS (29) /**< CH29 Bit Offset */
\r
3137 #define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /**< Write 1, triggers DMA_CHANNEL29 */
\r
3138 /* DMA_SW_CHTRIG[CH30] Bits */
\r
3139 #define DMA_SW_CHTRIG_CH30_OFS (30) /**< CH30 Bit Offset */
\r
3140 #define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /**< Write 1, triggers DMA_CHANNEL30 */
\r
3141 /* DMA_SW_CHTRIG[CH31] Bits */
\r
3142 #define DMA_SW_CHTRIG_CH31_OFS (31) /**< CH31 Bit Offset */
\r
3143 #define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /**< Write 1, triggers DMA_CHANNEL31 */
\r
3144 /* DMA_CHN_SRCCFG[DMA_SRC] Bits */
\r
3145 #define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /**< DMA_SRC Bit Offset */
\r
3146 #define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /**< DMA_SRC Bit Mask */
\r
3147 /* DMA_INT1_SRCCFG[INT_SRC] Bits */
\r
3148 #define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /**< INT_SRC Bit Offset */
\r
3149 #define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /**< INT_SRC Bit Mask */
\r
3150 /* DMA_INT1_SRCCFG[EN] Bits */
\r
3151 #define DMA_INT1_SRCCFG_EN_OFS ( 5) /**< EN Bit Offset */
\r
3152 #define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /**< Enables DMA_INT1 mapping */
\r
3153 /* DMA_INT2_SRCCFG[INT_SRC] Bits */
\r
3154 #define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /**< INT_SRC Bit Offset */
\r
3155 #define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /**< INT_SRC Bit Mask */
\r
3156 /* DMA_INT2_SRCCFG[EN] Bits */
\r
3157 #define DMA_INT2_SRCCFG_EN_OFS ( 5) /**< EN Bit Offset */
\r
3158 #define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /**< Enables DMA_INT2 mapping */
\r
3159 /* DMA_INT3_SRCCFG[INT_SRC] Bits */
\r
3160 #define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /**< INT_SRC Bit Offset */
\r
3161 #define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /**< INT_SRC Bit Mask */
\r
3162 /* DMA_INT3_SRCCFG[EN] Bits */
\r
3163 #define DMA_INT3_SRCCFG_EN_OFS ( 5) /**< EN Bit Offset */
\r
3164 #define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /**< Enables DMA_INT3 mapping */
\r
3165 /* DMA_INT0_SRCFLG[CH0] Bits */
\r
3166 #define DMA_INT0_SRCFLG_CH0_OFS ( 0) /**< CH0 Bit Offset */
\r
3167 #define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /**< Channel 0 was the source of DMA_INT0 */
\r
3168 /* DMA_INT0_SRCFLG[CH1] Bits */
\r
3169 #define DMA_INT0_SRCFLG_CH1_OFS ( 1) /**< CH1 Bit Offset */
\r
3170 #define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /**< Channel 1 was the source of DMA_INT0 */
\r
3171 /* DMA_INT0_SRCFLG[CH2] Bits */
\r
3172 #define DMA_INT0_SRCFLG_CH2_OFS ( 2) /**< CH2 Bit Offset */
\r
3173 #define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /**< Channel 2 was the source of DMA_INT0 */
\r
3174 /* DMA_INT0_SRCFLG[CH3] Bits */
\r
3175 #define DMA_INT0_SRCFLG_CH3_OFS ( 3) /**< CH3 Bit Offset */
\r
3176 #define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /**< Channel 3 was the source of DMA_INT0 */
\r
3177 /* DMA_INT0_SRCFLG[CH4] Bits */
\r
3178 #define DMA_INT0_SRCFLG_CH4_OFS ( 4) /**< CH4 Bit Offset */
\r
3179 #define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /**< Channel 4 was the source of DMA_INT0 */
\r
3180 /* DMA_INT0_SRCFLG[CH5] Bits */
\r
3181 #define DMA_INT0_SRCFLG_CH5_OFS ( 5) /**< CH5 Bit Offset */
\r
3182 #define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /**< Channel 5 was the source of DMA_INT0 */
\r
3183 /* DMA_INT0_SRCFLG[CH6] Bits */
\r
3184 #define DMA_INT0_SRCFLG_CH6_OFS ( 6) /**< CH6 Bit Offset */
\r
3185 #define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /**< Channel 6 was the source of DMA_INT0 */
\r
3186 /* DMA_INT0_SRCFLG[CH7] Bits */
\r
3187 #define DMA_INT0_SRCFLG_CH7_OFS ( 7) /**< CH7 Bit Offset */
\r
3188 #define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /**< Channel 7 was the source of DMA_INT0 */
\r
3189 /* DMA_INT0_SRCFLG[CH8] Bits */
\r
3190 #define DMA_INT0_SRCFLG_CH8_OFS ( 8) /**< CH8 Bit Offset */
\r
3191 #define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /**< Channel 8 was the source of DMA_INT0 */
\r
3192 /* DMA_INT0_SRCFLG[CH9] Bits */
\r
3193 #define DMA_INT0_SRCFLG_CH9_OFS ( 9) /**< CH9 Bit Offset */
\r
3194 #define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /**< Channel 9 was the source of DMA_INT0 */
\r
3195 /* DMA_INT0_SRCFLG[CH10] Bits */
\r
3196 #define DMA_INT0_SRCFLG_CH10_OFS (10) /**< CH10 Bit Offset */
\r
3197 #define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /**< Channel 10 was the source of DMA_INT0 */
\r
3198 /* DMA_INT0_SRCFLG[CH11] Bits */
\r
3199 #define DMA_INT0_SRCFLG_CH11_OFS (11) /**< CH11 Bit Offset */
\r
3200 #define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /**< Channel 11 was the source of DMA_INT0 */
\r
3201 /* DMA_INT0_SRCFLG[CH12] Bits */
\r
3202 #define DMA_INT0_SRCFLG_CH12_OFS (12) /**< CH12 Bit Offset */
\r
3203 #define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /**< Channel 12 was the source of DMA_INT0 */
\r
3204 /* DMA_INT0_SRCFLG[CH13] Bits */
\r
3205 #define DMA_INT0_SRCFLG_CH13_OFS (13) /**< CH13 Bit Offset */
\r
3206 #define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /**< Channel 13 was the source of DMA_INT0 */
\r
3207 /* DMA_INT0_SRCFLG[CH14] Bits */
\r
3208 #define DMA_INT0_SRCFLG_CH14_OFS (14) /**< CH14 Bit Offset */
\r
3209 #define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /**< Channel 14 was the source of DMA_INT0 */
\r
3210 /* DMA_INT0_SRCFLG[CH15] Bits */
\r
3211 #define DMA_INT0_SRCFLG_CH15_OFS (15) /**< CH15 Bit Offset */
\r
3212 #define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /**< Channel 15 was the source of DMA_INT0 */
\r
3213 /* DMA_INT0_SRCFLG[CH16] Bits */
\r
3214 #define DMA_INT0_SRCFLG_CH16_OFS (16) /**< CH16 Bit Offset */
\r
3215 #define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /**< Channel 16 was the source of DMA_INT0 */
\r
3216 /* DMA_INT0_SRCFLG[CH17] Bits */
\r
3217 #define DMA_INT0_SRCFLG_CH17_OFS (17) /**< CH17 Bit Offset */
\r
3218 #define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /**< Channel 17 was the source of DMA_INT0 */
\r
3219 /* DMA_INT0_SRCFLG[CH18] Bits */
\r
3220 #define DMA_INT0_SRCFLG_CH18_OFS (18) /**< CH18 Bit Offset */
\r
3221 #define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /**< Channel 18 was the source of DMA_INT0 */
\r
3222 /* DMA_INT0_SRCFLG[CH19] Bits */
\r
3223 #define DMA_INT0_SRCFLG_CH19_OFS (19) /**< CH19 Bit Offset */
\r
3224 #define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /**< Channel 19 was the source of DMA_INT0 */
\r
3225 /* DMA_INT0_SRCFLG[CH20] Bits */
\r
3226 #define DMA_INT0_SRCFLG_CH20_OFS (20) /**< CH20 Bit Offset */
\r
3227 #define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /**< Channel 20 was the source of DMA_INT0 */
\r
3228 /* DMA_INT0_SRCFLG[CH21] Bits */
\r
3229 #define DMA_INT0_SRCFLG_CH21_OFS (21) /**< CH21 Bit Offset */
\r
3230 #define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /**< Channel 21 was the source of DMA_INT0 */
\r
3231 /* DMA_INT0_SRCFLG[CH22] Bits */
\r
3232 #define DMA_INT0_SRCFLG_CH22_OFS (22) /**< CH22 Bit Offset */
\r
3233 #define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /**< Channel 22 was the source of DMA_INT0 */
\r
3234 /* DMA_INT0_SRCFLG[CH23] Bits */
\r
3235 #define DMA_INT0_SRCFLG_CH23_OFS (23) /**< CH23 Bit Offset */
\r
3236 #define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /**< Channel 23 was the source of DMA_INT0 */
\r
3237 /* DMA_INT0_SRCFLG[CH24] Bits */
\r
3238 #define DMA_INT0_SRCFLG_CH24_OFS (24) /**< CH24 Bit Offset */
\r
3239 #define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /**< Channel 24 was the source of DMA_INT0 */
\r
3240 /* DMA_INT0_SRCFLG[CH25] Bits */
\r
3241 #define DMA_INT0_SRCFLG_CH25_OFS (25) /**< CH25 Bit Offset */
\r
3242 #define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /**< Channel 25 was the source of DMA_INT0 */
\r
3243 /* DMA_INT0_SRCFLG[CH26] Bits */
\r
3244 #define DMA_INT0_SRCFLG_CH26_OFS (26) /**< CH26 Bit Offset */
\r
3245 #define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /**< Channel 26 was the source of DMA_INT0 */
\r
3246 /* DMA_INT0_SRCFLG[CH27] Bits */
\r
3247 #define DMA_INT0_SRCFLG_CH27_OFS (27) /**< CH27 Bit Offset */
\r
3248 #define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /**< Channel 27 was the source of DMA_INT0 */
\r
3249 /* DMA_INT0_SRCFLG[CH28] Bits */
\r
3250 #define DMA_INT0_SRCFLG_CH28_OFS (28) /**< CH28 Bit Offset */
\r
3251 #define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /**< Channel 28 was the source of DMA_INT0 */
\r
3252 /* DMA_INT0_SRCFLG[CH29] Bits */
\r
3253 #define DMA_INT0_SRCFLG_CH29_OFS (29) /**< CH29 Bit Offset */
\r
3254 #define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /**< Channel 29 was the source of DMA_INT0 */
\r
3255 /* DMA_INT0_SRCFLG[CH30] Bits */
\r
3256 #define DMA_INT0_SRCFLG_CH30_OFS (30) /**< CH30 Bit Offset */
\r
3257 #define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /**< Channel 30 was the source of DMA_INT0 */
\r
3258 /* DMA_INT0_SRCFLG[CH31] Bits */
\r
3259 #define DMA_INT0_SRCFLG_CH31_OFS (31) /**< CH31 Bit Offset */
\r
3260 #define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /**< Channel 31 was the source of DMA_INT0 */
\r
3261 /* DMA_INT0_CLRFLG[CH0] Bits */
\r
3262 #define DMA_INT0_CLRFLG_CH0_OFS ( 0) /**< CH0 Bit Offset */
\r
3263 #define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3264 /* DMA_INT0_CLRFLG[CH1] Bits */
\r
3265 #define DMA_INT0_CLRFLG_CH1_OFS ( 1) /**< CH1 Bit Offset */
\r
3266 #define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3267 /* DMA_INT0_CLRFLG[CH2] Bits */
\r
3268 #define DMA_INT0_CLRFLG_CH2_OFS ( 2) /**< CH2 Bit Offset */
\r
3269 #define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3270 /* DMA_INT0_CLRFLG[CH3] Bits */
\r
3271 #define DMA_INT0_CLRFLG_CH3_OFS ( 3) /**< CH3 Bit Offset */
\r
3272 #define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3273 /* DMA_INT0_CLRFLG[CH4] Bits */
\r
3274 #define DMA_INT0_CLRFLG_CH4_OFS ( 4) /**< CH4 Bit Offset */
\r
3275 #define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3276 /* DMA_INT0_CLRFLG[CH5] Bits */
\r
3277 #define DMA_INT0_CLRFLG_CH5_OFS ( 5) /**< CH5 Bit Offset */
\r
3278 #define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3279 /* DMA_INT0_CLRFLG[CH6] Bits */
\r
3280 #define DMA_INT0_CLRFLG_CH6_OFS ( 6) /**< CH6 Bit Offset */
\r
3281 #define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3282 /* DMA_INT0_CLRFLG[CH7] Bits */
\r
3283 #define DMA_INT0_CLRFLG_CH7_OFS ( 7) /**< CH7 Bit Offset */
\r
3284 #define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3285 /* DMA_INT0_CLRFLG[CH8] Bits */
\r
3286 #define DMA_INT0_CLRFLG_CH8_OFS ( 8) /**< CH8 Bit Offset */
\r
3287 #define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3288 /* DMA_INT0_CLRFLG[CH9] Bits */
\r
3289 #define DMA_INT0_CLRFLG_CH9_OFS ( 9) /**< CH9 Bit Offset */
\r
3290 #define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3291 /* DMA_INT0_CLRFLG[CH10] Bits */
\r
3292 #define DMA_INT0_CLRFLG_CH10_OFS (10) /**< CH10 Bit Offset */
\r
3293 #define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3294 /* DMA_INT0_CLRFLG[CH11] Bits */
\r
3295 #define DMA_INT0_CLRFLG_CH11_OFS (11) /**< CH11 Bit Offset */
\r
3296 #define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3297 /* DMA_INT0_CLRFLG[CH12] Bits */
\r
3298 #define DMA_INT0_CLRFLG_CH12_OFS (12) /**< CH12 Bit Offset */
\r
3299 #define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3300 /* DMA_INT0_CLRFLG[CH13] Bits */
\r
3301 #define DMA_INT0_CLRFLG_CH13_OFS (13) /**< CH13 Bit Offset */
\r
3302 #define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3303 /* DMA_INT0_CLRFLG[CH14] Bits */
\r
3304 #define DMA_INT0_CLRFLG_CH14_OFS (14) /**< CH14 Bit Offset */
\r
3305 #define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3306 /* DMA_INT0_CLRFLG[CH15] Bits */
\r
3307 #define DMA_INT0_CLRFLG_CH15_OFS (15) /**< CH15 Bit Offset */
\r
3308 #define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3309 /* DMA_INT0_CLRFLG[CH16] Bits */
\r
3310 #define DMA_INT0_CLRFLG_CH16_OFS (16) /**< CH16 Bit Offset */
\r
3311 #define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3312 /* DMA_INT0_CLRFLG[CH17] Bits */
\r
3313 #define DMA_INT0_CLRFLG_CH17_OFS (17) /**< CH17 Bit Offset */
\r
3314 #define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3315 /* DMA_INT0_CLRFLG[CH18] Bits */
\r
3316 #define DMA_INT0_CLRFLG_CH18_OFS (18) /**< CH18 Bit Offset */
\r
3317 #define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3318 /* DMA_INT0_CLRFLG[CH19] Bits */
\r
3319 #define DMA_INT0_CLRFLG_CH19_OFS (19) /**< CH19 Bit Offset */
\r
3320 #define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3321 /* DMA_INT0_CLRFLG[CH20] Bits */
\r
3322 #define DMA_INT0_CLRFLG_CH20_OFS (20) /**< CH20 Bit Offset */
\r
3323 #define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3324 /* DMA_INT0_CLRFLG[CH21] Bits */
\r
3325 #define DMA_INT0_CLRFLG_CH21_OFS (21) /**< CH21 Bit Offset */
\r
3326 #define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3327 /* DMA_INT0_CLRFLG[CH22] Bits */
\r
3328 #define DMA_INT0_CLRFLG_CH22_OFS (22) /**< CH22 Bit Offset */
\r
3329 #define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3330 /* DMA_INT0_CLRFLG[CH23] Bits */
\r
3331 #define DMA_INT0_CLRFLG_CH23_OFS (23) /**< CH23 Bit Offset */
\r
3332 #define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3333 /* DMA_INT0_CLRFLG[CH24] Bits */
\r
3334 #define DMA_INT0_CLRFLG_CH24_OFS (24) /**< CH24 Bit Offset */
\r
3335 #define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3336 /* DMA_INT0_CLRFLG[CH25] Bits */
\r
3337 #define DMA_INT0_CLRFLG_CH25_OFS (25) /**< CH25 Bit Offset */
\r
3338 #define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3339 /* DMA_INT0_CLRFLG[CH26] Bits */
\r
3340 #define DMA_INT0_CLRFLG_CH26_OFS (26) /**< CH26 Bit Offset */
\r
3341 #define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3342 /* DMA_INT0_CLRFLG[CH27] Bits */
\r
3343 #define DMA_INT0_CLRFLG_CH27_OFS (27) /**< CH27 Bit Offset */
\r
3344 #define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3345 /* DMA_INT0_CLRFLG[CH28] Bits */
\r
3346 #define DMA_INT0_CLRFLG_CH28_OFS (28) /**< CH28 Bit Offset */
\r
3347 #define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3348 /* DMA_INT0_CLRFLG[CH29] Bits */
\r
3349 #define DMA_INT0_CLRFLG_CH29_OFS (29) /**< CH29 Bit Offset */
\r
3350 #define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3351 /* DMA_INT0_CLRFLG[CH30] Bits */
\r
3352 #define DMA_INT0_CLRFLG_CH30_OFS (30) /**< CH30 Bit Offset */
\r
3353 #define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3354 /* DMA_INT0_CLRFLG[CH31] Bits */
\r
3355 #define DMA_INT0_CLRFLG_CH31_OFS (31) /**< CH31 Bit Offset */
\r
3356 #define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
\r
3357 /* DMA_STAT[MASTEN] Bits */
\r
3358 #define DMA_STAT_MASTEN_OFS ( 0) /**< MASTEN Bit Offset */
\r
3359 #define DMA_STAT_MASTEN ((uint32_t)0x00000001)
\r
3360 /* DMA_STAT[STATE] Bits */
\r
3361 #define DMA_STAT_STATE_OFS ( 4) /**< STATE Bit Offset */
\r
3362 #define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /**< STATE Bit Mask */
\r
3363 #define DMA_STAT_STATE0 ((uint32_t)0x00000010) /**< STATE Bit 0 */
\r
3364 #define DMA_STAT_STATE1 ((uint32_t)0x00000020) /**< STATE Bit 1 */
\r
3365 #define DMA_STAT_STATE2 ((uint32_t)0x00000040) /**< STATE Bit 2 */
\r
3366 #define DMA_STAT_STATE3 ((uint32_t)0x00000080) /**< STATE Bit 3 */
\r
3367 #define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /**< idle */
\r
3368 #define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /**< reading channel controller data */
\r
3369 #define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /**< reading source data end pointer */
\r
3370 #define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /**< reading destination data end pointer */
\r
3371 #define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /**< reading source data */
\r
3372 #define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /**< writing destination data */
\r
3373 #define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /**< waiting for DMA request to clear */
\r
3374 #define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /**< writing channel controller data */
\r
3375 #define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /**< stalled */
\r
3376 #define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /**< done */
\r
3377 #define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /**< peripheral scatter-gather transition */
\r
3378 #define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /**< Reserved */
\r
3379 #define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /**< Reserved */
\r
3380 #define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /**< Reserved */
\r
3381 #define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /**< Reserved */
\r
3382 #define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /**< Reserved */
\r
3383 /* DMA_STAT[DMACHANS] Bits */
\r
3384 #define DMA_STAT_DMACHANS_OFS (16) /**< DMACHANS Bit Offset */
\r
3385 #define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /**< DMACHANS Bit Mask */
\r
3386 #define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /**< DMACHANS Bit 0 */
\r
3387 #define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /**< DMACHANS Bit 1 */
\r
3388 #define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /**< DMACHANS Bit 2 */
\r
3389 #define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /**< DMACHANS Bit 3 */
\r
3390 #define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /**< DMACHANS Bit 4 */
\r
3391 #define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /**< Controller configured to use 1 DMA channel */
\r
3392 #define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /**< Controller configured to use 2 DMA channels */
\r
3393 #define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /**< Controller configured to use 31 DMA channels */
\r
3394 #define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /**< Controller configured to use 32 DMA channels */
\r
3395 /* DMA_STAT[TESTSTAT] Bits */
\r
3396 #define DMA_STAT_TESTSTAT_OFS (28) /**< TESTSTAT Bit Offset */
\r
3397 #define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /**< TESTSTAT Bit Mask */
\r
3398 #define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /**< TESTSTAT Bit 0 */
\r
3399 #define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /**< TESTSTAT Bit 1 */
\r
3400 #define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /**< TESTSTAT Bit 2 */
\r
3401 #define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /**< TESTSTAT Bit 3 */
\r
3402 #define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /**< Controller does not include the integration test logic */
\r
3403 #define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /**< Controller includes the integration test logic */
\r
3404 /* DMA_CFG[MASTEN] Bits */
\r
3405 #define DMA_CFG_MASTEN_OFS ( 0) /**< MASTEN Bit Offset */
\r
3406 #define DMA_CFG_MASTEN ((uint32_t)0x00000001)
\r
3407 /* DMA_CFG[CHPROTCTRL] Bits */
\r
3408 #define DMA_CFG_CHPROTCTRL_OFS ( 5) /**< CHPROTCTRL Bit Offset */
\r
3409 #define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /**< CHPROTCTRL Bit Mask */
\r
3410 /* DMA_CTLBASE[ADDR] Bits */
\r
3411 #define DMA_CTLBASE_ADDR_OFS ( 5) /**< ADDR Bit Offset */
\r
3412 #define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /**< ADDR Bit Mask */
\r
3413 /* DMA_ERRCLR[ERRCLR] Bits */
\r
3414 #define DMA_ERRCLR_ERRCLR_OFS ( 0) /**< ERRCLR Bit Offset */
\r
3415 #define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001)
\r
3417 /* UDMA_STAT Control Bits */
\r
3418 #define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /* Available uDMA Channels Minus 1 */
\r
3419 #define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /* Control State Machine Status */
\r
3420 #define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /* Idle */
\r
3421 #define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /* Reading channel controller data */
\r
3422 #define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /* Reading source end pointer */
\r
3423 #define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /* Reading destination end pointer */
\r
3424 #define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /* Reading source data */
\r
3425 #define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /* Writing destination data */
\r
3426 #define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /* Waiting for uDMA request to clear */
\r
3427 #define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /* Writing channel controller data */
\r
3428 #define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /* Stalled */
\r
3429 #define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /* Done */
\r
3430 #define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /* Undefined */
\r
3431 #define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /* Master Enable Status */
\r
3432 #define UDMA_STAT_DMACHANS_S (16)
\r
3434 /* UDMA_CFG Control Bits */
\r
3435 #define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /* Controller Master Enable */
\r
3437 /* UDMA_CTLBASE Control Bits */
\r
3438 #define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /* Channel Control Base Address */
\r
3439 #define UDMA_CTLBASE_ADDR_S (10)
\r
3441 /* UDMA_ALTBASE Control Bits */
\r
3442 #define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /* Alternate Channel Address Pointer */
\r
3443 #define UDMA_ALTBASE_ADDR_S ( 0)
\r
3445 /* UDMA_WAITSTAT Control Bits */
\r
3446 #define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Wait Status */
\r
3448 /* UDMA_SWREQ Control Bits */
\r
3449 #define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Software Request */
\r
3451 /* UDMA_USEBURSTSET Control Bits */
\r
3452 #define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Useburst Set */
\r
3454 /* UDMA_USEBURSTCLR Control Bits */
\r
3455 #define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Useburst Clear */
\r
3457 /* UDMA_REQMASKSET Control Bits */
\r
3458 #define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Request Mask Set */
\r
3460 /* UDMA_REQMASKCLR Control Bits */
\r
3461 #define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Request Mask Clear */
\r
3463 /* UDMA_ENASET Control Bits */
\r
3464 #define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Enable Set */
\r
3466 /* UDMA_ENACLR Control Bits */
\r
3467 #define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Clear Channel [n] Enable Clear */
\r
3469 /* UDMA_ALTSET Control Bits */
\r
3470 #define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Alternate Set */
\r
3472 /* UDMA_ALTCLR Control Bits */
\r
3473 #define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Alternate Clear */
\r
3475 /* UDMA_PRIOSET Control Bits */
\r
3476 #define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Priority Set */
\r
3478 /* UDMA_PRIOCLR Control Bits */
\r
3479 #define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Priority Clear */
\r
3481 /* UDMA_ERRCLR Control Bits */
\r
3482 #define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /* uDMA Bus Error Status */
\r
3484 /* UDMA_CHASGN Control Bits */
\r
3485 #define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Assignment Select */
\r
3486 #define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /* Use the primary channel assignment */
\r
3487 #define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /* Use the secondary channel assignment */
\r
3489 /* Micro Direct Memory Access (uDMA) offsets */
\r
3490 #define UDMA_O_SRCENDP ((uint32_t)0x00000000) /* DMA Channel Source Address End Pointer */
\r
3491 #define UDMA_O_DSTENDP ((uint32_t)0x00000004) /* DMA Channel Destination Address End Pointer */
\r
3492 #define UDMA_O_CHCTL ((uint32_t)0x00000008) /* DMA Channel Control Word */
\r
3494 /* UDMA_O_SRCENDP Control Bits */
\r
3495 #define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /* Source Address End Pointer */
\r
3496 #define UDMA_SRCENDP_ADDR_S ( 0)
\r
3498 /* UDMA_O_DSTENDP Control Bits */
\r
3499 #define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /* Destination Address End Pointer */
\r
3500 #define UDMA_DSTENDP_ADDR_S ( 0)
\r
3502 /* UDMA_O_CHCTL Control Bits */
\r
3503 #define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /* Destination Address Increment */
\r
3504 #define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /* Byte */
\r
3505 #define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /* Half-word */
\r
3506 #define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /* Word */
\r
3507 #define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /* No increment */
\r
3508 #define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /* Destination Data Size */
\r
3509 #define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /* Byte */
\r
3510 #define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /* Half-word */
\r
3511 #define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /* Word */
\r
3512 #define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /* Source Address Increment */
\r
3513 #define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /* Byte */
\r
3514 #define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /* Half-word */
\r
3515 #define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /* Word */
\r
3516 #define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /* No increment */
\r
3517 #define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /* Source Data Size */
\r
3518 #define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /* Byte */
\r
3519 #define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /* Half-word */
\r
3520 #define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /* Word */
\r
3521 #define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /* Arbitration Size */
\r
3522 #define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /* 1 Transfer */
\r
3523 #define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /* 2 Transfers */
\r
3524 #define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /* 4 Transfers */
\r
3525 #define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /* 8 Transfers */
\r
3526 #define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /* 16 Transfers */
\r
3527 #define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /* 32 Transfers */
\r
3528 #define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /* 64 Transfers */
\r
3529 #define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /* 128 Transfers */
\r
3530 #define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /* 256 Transfers */
\r
3531 #define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /* 512 Transfers */
\r
3532 #define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /* 1024 Transfers */
\r
3533 #define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /* Transfer Size (minus 1) */
\r
3534 #define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /* Next Useburst */
\r
3535 #define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /* uDMA Transfer Mode */
\r
3536 #define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /* Stop */
\r
3537 #define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /* Basic */
\r
3538 #define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /* Auto-Request */
\r
3539 #define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /* Ping-Pong */
\r
3540 #define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /* Memory Scatter-Gather */
\r
3541 #define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /* Alternate Memory Scatter-Gather */
\r
3542 #define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /* Peripheral Scatter-Gather */
\r
3543 #define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /* Alternate Peripheral Scatter-Gather */
\r
3545 #define UDMA_CHCTL_XFERSIZE_S ( 4)
\r
3548 /******************************************************************************
\r
3550 ******************************************************************************/
\r
3553 /******************************************************************************
\r
3555 ******************************************************************************/
\r
3556 /* EUSCI_A_CTLW0[SWRST] Bits */
\r
3557 #define EUSCI_A_CTLW0_SWRST_OFS ( 0) /**< UCSWRST Bit Offset */
\r
3558 #define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /**< Software reset enable */
\r
3559 /* EUSCI_A_CTLW0[TXBRK] Bits */
\r
3560 #define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /**< UCTXBRK Bit Offset */
\r
3561 #define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /**< Transmit break */
\r
3562 /* EUSCI_A_CTLW0[TXADDR] Bits */
\r
3563 #define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /**< UCTXADDR Bit Offset */
\r
3564 #define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /**< Transmit address */
\r
3565 /* EUSCI_A_CTLW0[DORM] Bits */
\r
3566 #define EUSCI_A_CTLW0_DORM_OFS ( 3) /**< UCDORM Bit Offset */
\r
3567 #define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /**< Dormant */
\r
3568 /* EUSCI_A_CTLW0[BRKIE] Bits */
\r
3569 #define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /**< UCBRKIE Bit Offset */
\r
3570 #define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /**< Receive break character interrupt enable */
\r
3571 /* EUSCI_A_CTLW0[RXEIE] Bits */
\r
3572 #define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /**< UCRXEIE Bit Offset */
\r
3573 #define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /**< Receive erroneous-character interrupt enable */
\r
3574 /* EUSCI_A_CTLW0[SSEL] Bits */
\r
3575 #define EUSCI_A_CTLW0_SSEL_OFS ( 6) /**< UCSSEL Bit Offset */
\r
3576 #define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /**< UCSSEL Bit Mask */
\r
3577 #define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /**< SSEL Bit 0 */
\r
3578 #define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /**< SSEL Bit 1 */
\r
3579 #define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /**< UCLK */
\r
3580 #define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /**< ACLK */
\r
3581 #define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /**< SMCLK */
\r
3582 #define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /**< UCLK */
\r
3583 #define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /**< ACLK */
\r
3584 #define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /**< SMCLK */
\r
3585 /* EUSCI_A_CTLW0[SYNC] Bits */
\r
3586 #define EUSCI_A_CTLW0_SYNC_OFS ( 8) /**< UCSYNC Bit Offset */
\r
3587 #define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /**< Synchronous mode enable */
\r
3588 /* EUSCI_A_CTLW0[MODE] Bits */
\r
3589 #define EUSCI_A_CTLW0_MODE_OFS ( 9) /**< UCMODE Bit Offset */
\r
3590 #define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /**< UCMODE Bit Mask */
\r
3591 #define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /**< MODE Bit 0 */
\r
3592 #define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /**< MODE Bit 1 */
\r
3593 #define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /**< UART mode */
\r
3594 #define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /**< Idle-line multiprocessor mode */
\r
3595 #define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /**< Address-bit multiprocessor mode */
\r
3596 #define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /**< UART mode with automatic baud-rate detection */
\r
3597 /* EUSCI_A_CTLW0[SPB] Bits */
\r
3598 #define EUSCI_A_CTLW0_SPB_OFS (11) /**< UCSPB Bit Offset */
\r
3599 #define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /**< Stop bit select */
\r
3600 /* EUSCI_A_CTLW0[SEVENBIT] Bits */
\r
3601 #define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /**< UC7BIT Bit Offset */
\r
3602 #define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /**< Character length */
\r
3603 /* EUSCI_A_CTLW0[MSB] Bits */
\r
3604 #define EUSCI_A_CTLW0_MSB_OFS (13) /**< UCMSB Bit Offset */
\r
3605 #define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /**< MSB first select */
\r
3606 /* EUSCI_A_CTLW0[PAR] Bits */
\r
3607 #define EUSCI_A_CTLW0_PAR_OFS (14) /**< UCPAR Bit Offset */
\r
3608 #define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /**< Parity select */
\r
3609 /* EUSCI_A_CTLW0[PEN] Bits */
\r
3610 #define EUSCI_A_CTLW0_PEN_OFS (15) /**< UCPEN Bit Offset */
\r
3611 #define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /**< Parity enable */
\r
3612 /* EUSCI_A_CTLW0[STEM] Bits */
\r
3613 #define EUSCI_A_CTLW0_STEM_OFS ( 1) /**< UCSTEM Bit Offset */
\r
3614 #define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /**< STE mode select in master mode. */
\r
3615 /* EUSCI_A_CTLW0[SSEL] Bits */
\r
3618 #define EUSCI_A_CTLW0_SSEL_0 ((uint16_t)0x0000) /**< Reserved */
\r
3621 /* EUSCI_A_CTLW0[MODE] Bits */
\r
3625 /* EUSCI_A_CTLW0[MST] Bits */
\r
3626 #define EUSCI_A_CTLW0_MST_OFS (11) /**< UCMST Bit Offset */
\r
3627 #define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /**< Master mode select */
\r
3628 /* EUSCI_A_CTLW0[CKPL] Bits */
\r
3629 #define EUSCI_A_CTLW0_CKPL_OFS (14) /**< UCCKPL Bit Offset */
\r
3630 #define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /**< Clock polarity select */
\r
3631 /* EUSCI_A_CTLW0[CKPH] Bits */
\r
3632 #define EUSCI_A_CTLW0_CKPH_OFS (15) /**< UCCKPH Bit Offset */
\r
3633 #define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /**< Clock phase select */
\r
3634 /* EUSCI_A_CTLW1[GLIT] Bits */
\r
3635 #define EUSCI_A_CTLW1_GLIT_OFS ( 0) /**< UCGLIT Bit Offset */
\r
3636 #define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /**< UCGLIT Bit Mask */
\r
3637 #define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /**< GLIT Bit 0 */
\r
3638 #define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /**< GLIT Bit 1 */
\r
3639 #define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /**< Approximately 2 ns (equivalent of 1 delay element) */
\r
3640 #define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /**< Approximately 50 ns */
\r
3641 #define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /**< Approximately 100 ns */
\r
3642 #define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /**< Approximately 200 ns */
\r
3643 /* EUSCI_A_MCTLW[OS16] Bits */
\r
3644 #define EUSCI_A_MCTLW_OS16_OFS ( 0) /**< UCOS16 Bit Offset */
\r
3645 #define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /**< Oversampling mode enabled */
\r
3646 /* EUSCI_A_MCTLW[BRF] Bits */
\r
3647 #define EUSCI_A_MCTLW_BRF_OFS ( 4) /**< UCBRF Bit Offset */
\r
3648 #define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /**< UCBRF Bit Mask */
\r
3649 /* EUSCI_A_MCTLW[BRS] Bits */
\r
3650 #define EUSCI_A_MCTLW_BRS_OFS ( 8) /**< UCBRS Bit Offset */
\r
3651 #define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /**< UCBRS Bit Mask */
\r
3652 /* EUSCI_A_STATW[BUSY] Bits */
\r
3653 #define EUSCI_A_STATW_BUSY_OFS ( 0) /**< UCBUSY Bit Offset */
\r
3654 #define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /**< eUSCI_A busy */
\r
3655 /* EUSCI_A_STATW[ADDR_IDLE] Bits */
\r
3656 #define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /**< UCADDR_UCIDLE Bit Offset */
\r
3657 #define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /**< Address received / Idle line detected */
\r
3658 /* EUSCI_A_STATW[RXERR] Bits */
\r
3659 #define EUSCI_A_STATW_RXERR_OFS ( 2) /**< UCRXERR Bit Offset */
\r
3660 #define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /**< Receive error flag */
\r
3661 /* EUSCI_A_STATW[BRK] Bits */
\r
3662 #define EUSCI_A_STATW_BRK_OFS ( 3) /**< UCBRK Bit Offset */
\r
3663 #define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /**< Break detect flag */
\r
3664 /* EUSCI_A_STATW[PE] Bits */
\r
3665 #define EUSCI_A_STATW_PE_OFS ( 4) /**< UCPE Bit Offset */
\r
3666 #define EUSCI_A_STATW_PE ((uint16_t)0x0010)
\r
3667 /* EUSCI_A_STATW[OE] Bits */
\r
3668 #define EUSCI_A_STATW_OE_OFS ( 5) /**< UCOE Bit Offset */
\r
3669 #define EUSCI_A_STATW_OE ((uint16_t)0x0020) /**< Overrun error flag */
\r
3670 /* EUSCI_A_STATW[FE] Bits */
\r
3671 #define EUSCI_A_STATW_FE_OFS ( 6) /**< UCFE Bit Offset */
\r
3672 #define EUSCI_A_STATW_FE ((uint16_t)0x0040) /**< Framing error flag */
\r
3673 /* EUSCI_A_STATW[LISTEN] Bits */
\r
3674 #define EUSCI_A_STATW_LISTEN_OFS ( 7) /**< UCLISTEN Bit Offset */
\r
3675 #define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /**< Listen enable */
\r
3676 /* EUSCI_A_RXBUF[RXBUF] Bits */
\r
3677 #define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /**< UCRXBUF Bit Offset */
\r
3678 #define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /**< UCRXBUF Bit Mask */
\r
3679 /* EUSCI_A_TXBUF[TXBUF] Bits */
\r
3680 #define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /**< UCTXBUF Bit Offset */
\r
3681 #define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /**< UCTXBUF Bit Mask */
\r
3682 /* EUSCI_A_ABCTL[ABDEN] Bits */
\r
3683 #define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /**< UCABDEN Bit Offset */
\r
3684 #define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /**< Automatic baud-rate detect enable */
\r
3685 /* EUSCI_A_ABCTL[BTOE] Bits */
\r
3686 #define EUSCI_A_ABCTL_BTOE_OFS ( 2) /**< UCBTOE Bit Offset */
\r
3687 #define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /**< Break time out error */
\r
3688 /* EUSCI_A_ABCTL[STOE] Bits */
\r
3689 #define EUSCI_A_ABCTL_STOE_OFS ( 3) /**< UCSTOE Bit Offset */
\r
3690 #define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /**< Synch field time out error */
\r
3691 /* EUSCI_A_ABCTL[DELIM] Bits */
\r
3692 #define EUSCI_A_ABCTL_DELIM_OFS ( 4) /**< UCDELIM Bit Offset */
\r
3693 #define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /**< UCDELIM Bit Mask */
\r
3694 #define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /**< DELIM Bit 0 */
\r
3695 #define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /**< DELIM Bit 1 */
\r
3696 #define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /**< 1 bit time */
\r
3697 #define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /**< 2 bit times */
\r
3698 #define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /**< 3 bit times */
\r
3699 #define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /**< 4 bit times */
\r
3700 /* EUSCI_A_IRCTL[IREN] Bits */
\r
3701 #define EUSCI_A_IRCTL_IREN_OFS ( 0) /**< UCIREN Bit Offset */
\r
3702 #define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /**< IrDA encoder/decoder enable */
\r
3703 /* EUSCI_A_IRCTL[IRTXCLK] Bits */
\r
3704 #define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /**< UCIRTXCLK Bit Offset */
\r
3705 #define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /**< IrDA transmit pulse clock select */
\r
3706 /* EUSCI_A_IRCTL[IRTXPL] Bits */
\r
3707 #define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /**< UCIRTXPL Bit Offset */
\r
3708 #define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /**< UCIRTXPL Bit Mask */
\r
3709 /* EUSCI_A_IRCTL[IRRXFE] Bits */
\r
3710 #define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /**< UCIRRXFE Bit Offset */
\r
3711 #define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /**< IrDA receive filter enabled */
\r
3712 /* EUSCI_A_IRCTL[IRRXPL] Bits */
\r
3713 #define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /**< UCIRRXPL Bit Offset */
\r
3714 #define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /**< IrDA receive input UCAxRXD polarity */
\r
3715 /* EUSCI_A_IRCTL[IRRXFL] Bits */
\r
3716 #define EUSCI_A_IRCTL_IRRXFL_OFS (10) /**< UCIRRXFL Bit Offset */
\r
3717 #define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /**< UCIRRXFL Bit Mask */
\r
3718 /* EUSCI_A_IE[RXIE] Bits */
\r
3719 #define EUSCI_A_IE_RXIE_OFS ( 0) /**< UCRXIE Bit Offset */
\r
3720 #define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /**< Receive interrupt enable */
\r
3721 /* EUSCI_A_IE[TXIE] Bits */
\r
3722 #define EUSCI_A_IE_TXIE_OFS ( 1) /**< UCTXIE Bit Offset */
\r
3723 #define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /**< Transmit interrupt enable */
\r
3724 /* EUSCI_A_IE[STTIE] Bits */
\r
3725 #define EUSCI_A_IE_STTIE_OFS ( 2) /**< UCSTTIE Bit Offset */
\r
3726 #define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /**< Start bit interrupt enable */
\r
3727 /* EUSCI_A_IE[TXCPTIE] Bits */
\r
3728 #define EUSCI_A_IE_TXCPTIE_OFS ( 3) /**< UCTXCPTIE Bit Offset */
\r
3729 #define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /**< Transmit complete interrupt enable */
\r
3730 /* EUSCI_A_UCAxIE_SPI[RXIE] Bits */
\r
3731 #define EUSCI_A__RXIE_OFS ( 0) /**< UCRXIE Bit Offset */
\r
3732 #define EUSCI_A__RXIE ((uint16_t)0x0001) /**< Receive interrupt enable */
\r
3733 /* EUSCI_A_UCAxIE_SPI[TXIE] Bits */
\r
3734 #define EUSCI_A__TXIE_OFS ( 1) /**< UCTXIE Bit Offset */
\r
3735 #define EUSCI_A__TXIE ((uint16_t)0x0002) /**< Transmit interrupt enable */
\r
3736 /* EUSCI_A_IFG[RXIFG] Bits */
\r
3737 #define EUSCI_A_IFG_RXIFG_OFS ( 0) /**< UCRXIFG Bit Offset */
\r
3738 #define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /**< Receive interrupt flag */
\r
3739 /* EUSCI_A_IFG[TXIFG] Bits */
\r
3740 #define EUSCI_A_IFG_TXIFG_OFS ( 1) /**< UCTXIFG Bit Offset */
\r
3741 #define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /**< Transmit interrupt flag */
\r
3742 /* EUSCI_A_IFG[STTIFG] Bits */
\r
3743 #define EUSCI_A_IFG_STTIFG_OFS ( 2) /**< UCSTTIFG Bit Offset */
\r
3744 #define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /**< Start bit interrupt flag */
\r
3745 /* EUSCI_A_IFG[TXCPTIFG] Bits */
\r
3746 #define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /**< UCTXCPTIFG Bit Offset */
\r
3747 #define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /**< Transmit ready interrupt enable */
\r
3750 /******************************************************************************
\r
3752 ******************************************************************************/
\r
3753 /* EUSCI_B_CTLW0[SWRST] Bits */
\r
3754 #define EUSCI_B_CTLW0_SWRST_OFS ( 0) /**< UCSWRST Bit Offset */
\r
3755 #define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /**< Software reset enable */
\r
3756 /* EUSCI_B_CTLW0[TXSTT] Bits */
\r
3757 #define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /**< UCTXSTT Bit Offset */
\r
3758 #define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /**< Transmit START condition in master mode */
\r
3759 /* EUSCI_B_CTLW0[TXSTP] Bits */
\r
3760 #define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /**< UCTXSTP Bit Offset */
\r
3761 #define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /**< Transmit STOP condition in master mode */
\r
3762 /* EUSCI_B_CTLW0[TXNACK] Bits */
\r
3763 #define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /**< UCTXNACK Bit Offset */
\r
3764 #define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /**< Transmit a NACK */
\r
3765 /* EUSCI_B_CTLW0[TR] Bits */
\r
3766 #define EUSCI_B_CTLW0_TR_OFS ( 4) /**< UCTR Bit Offset */
\r
3767 #define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /**< Transmitter/receiver */
\r
3768 /* EUSCI_B_CTLW0[TXACK] Bits */
\r
3769 #define EUSCI_B_CTLW0_TXACK_OFS ( 5) /**< UCTXACK Bit Offset */
\r
3770 #define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /**< Transmit ACK condition in slave mode */
\r
3771 /* EUSCI_B_CTLW0[SSEL] Bits */
\r
3772 #define EUSCI_B_CTLW0_SSEL_OFS ( 6) /**< UCSSEL Bit Offset */
\r
3773 #define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /**< UCSSEL Bit Mask */
\r
3774 #define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /**< SSEL Bit 0 */
\r
3775 #define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /**< SSEL Bit 1 */
\r
3776 #define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /**< UCLKI */
\r
3777 #define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /**< ACLK */
\r
3778 #define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /**< SMCLK */
\r
3779 #define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /**< UCLKI */
\r
3780 #define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /**< ACLK */
\r
3781 #define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /**< SMCLK */
\r
3782 #define EUSCI_B_CTLW0_SSEL_3 ((uint16_t)0x00C0) /**< SMCLK */
\r
3783 /* EUSCI_B_CTLW0[SYNC] Bits */
\r
3784 #define EUSCI_B_CTLW0_SYNC_OFS ( 8) /**< UCSYNC Bit Offset */
\r
3785 #define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /**< Synchronous mode enable */
\r
3786 /* EUSCI_B_CTLW0[MODE] Bits */
\r
3787 #define EUSCI_B_CTLW0_MODE_OFS ( 9) /**< UCMODE Bit Offset */
\r
3788 #define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /**< UCMODE Bit Mask */
\r
3789 #define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /**< MODE Bit 0 */
\r
3790 #define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /**< MODE Bit 1 */
\r
3791 #define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /**< 3-pin SPI */
\r
3792 #define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /**< 4-pin SPI (master or slave enabled if STE = 1) */
\r
3793 #define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /**< 4-pin SPI (master or slave enabled if STE = 0) */
\r
3794 #define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /**< I2C mode */
\r
3795 /* EUSCI_B_CTLW0[MST] Bits */
\r
3796 #define EUSCI_B_CTLW0_MST_OFS (11) /**< UCMST Bit Offset */
\r
3797 #define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /**< Master mode select */
\r
3798 /* EUSCI_B_CTLW0[MM] Bits */
\r
3799 #define EUSCI_B_CTLW0_MM_OFS (13) /**< UCMM Bit Offset */
\r
3800 #define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /**< Multi-master environment select */
\r
3801 /* EUSCI_B_CTLW0[SLA10] Bits */
\r
3802 #define EUSCI_B_CTLW0_SLA10_OFS (14) /**< UCSLA10 Bit Offset */
\r
3803 #define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /**< Slave addressing mode select */
\r
3804 /* EUSCI_B_CTLW0[A10] Bits */
\r
3805 #define EUSCI_B_CTLW0_A10_OFS (15) /**< UCA10 Bit Offset */
\r
3806 #define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /**< Own addressing mode select */
\r
3807 /* EUSCI_B_CTLW0[STEM] Bits */
\r
3808 #define EUSCI_B_CTLW0_STEM_OFS ( 1) /**< UCSTEM Bit Offset */
\r
3809 #define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /**< STE mode select in master mode. */
\r
3810 /* EUSCI_B_CTLW0[SSEL] Bits */
\r
3813 #define EUSCI_B_CTLW0_SSEL_0 ((uint16_t)0x0000) /**< Reserved */
\r
3817 /* EUSCI_B_CTLW0[MODE] Bits */
\r
3822 /* EUSCI_B_CTLW0[SEVENBIT] Bits */
\r
3823 #define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /**< UC7BIT Bit Offset */
\r
3824 #define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /**< Character length */
\r
3825 /* EUSCI_B_CTLW0[MSB] Bits */
\r
3826 #define EUSCI_B_CTLW0_MSB_OFS (13) /**< UCMSB Bit Offset */
\r
3827 #define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /**< MSB first select */
\r
3828 /* EUSCI_B_CTLW0[CKPL] Bits */
\r
3829 #define EUSCI_B_CTLW0_CKPL_OFS (14) /**< UCCKPL Bit Offset */
\r
3830 #define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /**< Clock polarity select */
\r
3831 /* EUSCI_B_CTLW0[CKPH] Bits */
\r
3832 #define EUSCI_B_CTLW0_CKPH_OFS (15) /**< UCCKPH Bit Offset */
\r
3833 #define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /**< Clock phase select */
\r
3834 /* EUSCI_B_CTLW1[GLIT] Bits */
\r
3835 #define EUSCI_B_CTLW1_GLIT_OFS ( 0) /**< UCGLIT Bit Offset */
\r
3836 #define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /**< UCGLIT Bit Mask */
\r
3837 #define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /**< GLIT Bit 0 */
\r
3838 #define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /**< GLIT Bit 1 */
\r
3839 #define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /**< 50 ns */
\r
3840 #define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /**< 25 ns */
\r
3841 #define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /**< 12.5 ns */
\r
3842 #define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /**< 6.25 ns */
\r
3843 /* EUSCI_B_CTLW1[ASTP] Bits */
\r
3844 #define EUSCI_B_CTLW1_ASTP_OFS ( 2) /**< UCASTP Bit Offset */
\r
3845 #define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /**< UCASTP Bit Mask */
\r
3846 #define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /**< ASTP Bit 0 */
\r
3847 #define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /**< ASTP Bit 1 */
\r
3848 #define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /**< No automatic STOP generation. The STOP condition is generated after the user */
\r
3849 /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
\r
3850 #define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /**< UCBCNTIFG is set with the byte counter reaches the threshold defined in */
\r
3852 #define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /**< A STOP condition is generated automatically after the byte counter value */
\r
3853 /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */
\r
3855 /* EUSCI_B_CTLW1[SWACK] Bits */
\r
3856 #define EUSCI_B_CTLW1_SWACK_OFS ( 4) /**< UCSWACK Bit Offset */
\r
3857 #define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /**< SW or HW ACK control */
\r
3858 /* EUSCI_B_CTLW1[STPNACK] Bits */
\r
3859 #define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /**< UCSTPNACK Bit Offset */
\r
3860 #define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /**< ACK all master bytes */
\r
3861 /* EUSCI_B_CTLW1[CLTO] Bits */
\r
3862 #define EUSCI_B_CTLW1_CLTO_OFS ( 6) /**< UCCLTO Bit Offset */
\r
3863 #define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /**< UCCLTO Bit Mask */
\r
3864 #define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /**< CLTO Bit 0 */
\r
3865 #define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /**< CLTO Bit 1 */
\r
3866 #define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /**< Disable clock low timeout counter */
\r
3867 #define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /**< 135 000 SYSCLK cycles (approximately 28 ms) */
\r
3868 #define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /**< 150 000 SYSCLK cycles (approximately 31 ms) */
\r
3869 #define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /**< 165 000 SYSCLK cycles (approximately 34 ms) */
\r
3870 /* EUSCI_B_CTLW1[ETXINT] Bits */
\r
3871 #define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /**< UCETXINT Bit Offset */
\r
3872 #define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /**< Early UCTXIFG0 */
\r
3873 /* EUSCI_B_STATW[BBUSY] Bits */
\r
3874 #define EUSCI_B_STATW_BBUSY_OFS ( 4) /**< UCBBUSY Bit Offset */
\r
3875 #define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /**< Bus busy */
\r
3876 /* EUSCI_B_STATW[GC] Bits */
\r
3877 #define EUSCI_B_STATW_GC_OFS ( 5) /**< UCGC Bit Offset */
\r
3878 #define EUSCI_B_STATW_GC ((uint16_t)0x0020) /**< General call address received */
\r
3879 /* EUSCI_B_STATW[SCLLOW] Bits */
\r
3880 #define EUSCI_B_STATW_SCLLOW_OFS ( 6) /**< UCSCLLOW Bit Offset */
\r
3881 #define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /**< SCL low */
\r
3882 /* EUSCI_B_STATW[BCNT] Bits */
\r
3883 #define EUSCI_B_STATW_BCNT_OFS ( 8) /**< UCBCNT Bit Offset */
\r
3884 #define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /**< UCBCNT Bit Mask */
\r
3885 /* EUSCI_B_STATW[BUSY] Bits */
\r
3886 #define EUSCI_B_STATW_BUSY_OFS ( 0) /**< UCBUSY Bit Offset */
\r
3887 #define EUSCI_B_STATW_BUSY ((uint16_t)0x0001) /**< eUSCI_B busy */
\r
3888 /* EUSCI_B_STATW[OE] Bits */
\r
3889 #define EUSCI_B_STATW_OE_OFS ( 5) /**< UCOE Bit Offset */
\r
3890 #define EUSCI_B_STATW_OE ((uint16_t)0x0020) /**< Overrun error flag */
\r
3891 /* EUSCI_B_STATW[FE] Bits */
\r
3892 #define EUSCI_B_STATW_FE_OFS ( 6) /**< UCFE Bit Offset */
\r
3893 #define EUSCI_B_STATW_FE ((uint16_t)0x0040) /**< Framing error flag */
\r
3894 /* EUSCI_B_STATW[LISTEN] Bits */
\r
3895 #define EUSCI_B_STATW_LISTEN_OFS ( 7) /**< UCLISTEN Bit Offset */
\r
3896 #define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /**< Listen enable */
\r
3897 /* EUSCI_B_TBCNT[TBCNT] Bits */
\r
3898 #define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /**< UCTBCNT Bit Offset */
\r
3899 #define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /**< UCTBCNT Bit Mask */
\r
3900 /* EUSCI_B_RXBUF[RXBUF] Bits */
\r
3901 #define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /**< UCRXBUF Bit Offset */
\r
3902 #define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /**< UCRXBUF Bit Mask */
\r
3903 /* EUSCI_B_TXBUF[TXBUF] Bits */
\r
3904 #define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /**< UCTXBUF Bit Offset */
\r
3905 #define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /**< UCTXBUF Bit Mask */
\r
3906 /* EUSCI_B_I2COA0[I2COA0] Bits */
\r
3907 #define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /**< I2COA0 Bit Offset */
\r
3908 #define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /**< I2COA0 Bit Mask */
\r
3909 /* EUSCI_B_I2COA0[OAEN] Bits */
\r
3910 #define EUSCI_B_I2COA0_OAEN_OFS (10) /**< UCOAEN Bit Offset */
\r
3911 #define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /**< Own Address enable register */
\r
3912 /* EUSCI_B_I2COA0[GCEN] Bits */
\r
3913 #define EUSCI_B_I2COA0_GCEN_OFS (15) /**< UCGCEN Bit Offset */
\r
3914 #define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /**< General call response enable */
\r
3915 /* EUSCI_B_I2COA1[I2COA1] Bits */
\r
3916 #define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /**< I2COA1 Bit Offset */
\r
3917 #define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /**< I2COA1 Bit Mask */
\r
3918 /* EUSCI_B_I2COA1[OAEN] Bits */
\r
3919 #define EUSCI_B_I2COA1_OAEN_OFS (10) /**< UCOAEN Bit Offset */
\r
3920 #define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /**< Own Address enable register */
\r
3921 /* EUSCI_B_I2COA2[I2COA2] Bits */
\r
3922 #define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /**< I2COA2 Bit Offset */
\r
3923 #define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /**< I2COA2 Bit Mask */
\r
3924 /* EUSCI_B_I2COA2[OAEN] Bits */
\r
3925 #define EUSCI_B_I2COA2_OAEN_OFS (10) /**< UCOAEN Bit Offset */
\r
3926 #define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /**< Own Address enable register */
\r
3927 /* EUSCI_B_I2COA3[I2COA3] Bits */
\r
3928 #define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /**< I2COA3 Bit Offset */
\r
3929 #define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /**< I2COA3 Bit Mask */
\r
3930 /* EUSCI_B_I2COA3[OAEN] Bits */
\r
3931 #define EUSCI_B_I2COA3_OAEN_OFS (10) /**< UCOAEN Bit Offset */
\r
3932 #define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /**< Own Address enable register */
\r
3933 /* EUSCI_B_ADDRX[ADDRX] Bits */
\r
3934 #define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /**< ADDRX Bit Offset */
\r
3935 #define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /**< ADDRX Bit Mask */
\r
3936 /* EUSCI_B_ADDMASK[ADDMASK] Bits */
\r
3937 #define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /**< ADDMASK Bit Offset */
\r
3938 #define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /**< ADDMASK Bit Mask */
\r
3939 /* EUSCI_B_I2CSA[I2CSA] Bits */
\r
3940 #define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /**< I2CSA Bit Offset */
\r
3941 #define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /**< I2CSA Bit Mask */
\r
3942 /* EUSCI_B_IE[RXIE0] Bits */
\r
3943 #define EUSCI_B_IE_RXIE0_OFS ( 0) /**< UCRXIE0 Bit Offset */
\r
3944 #define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /**< Receive interrupt enable 0 */
\r
3945 /* EUSCI_B_IE[TXIE0] Bits */
\r
3946 #define EUSCI_B_IE_TXIE0_OFS ( 1) /**< UCTXIE0 Bit Offset */
\r
3947 #define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /**< Transmit interrupt enable 0 */
\r
3948 /* EUSCI_B_IE[STTIE] Bits */
\r
3949 #define EUSCI_B_IE_STTIE_OFS ( 2) /**< UCSTTIE Bit Offset */
\r
3950 #define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /**< START condition interrupt enable */
\r
3951 /* EUSCI_B_IE[STPIE] Bits */
\r
3952 #define EUSCI_B_IE_STPIE_OFS ( 3) /**< UCSTPIE Bit Offset */
\r
3953 #define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /**< STOP condition interrupt enable */
\r
3954 /* EUSCI_B_IE[ALIE] Bits */
\r
3955 #define EUSCI_B_IE_ALIE_OFS ( 4) /**< UCALIE Bit Offset */
\r
3956 #define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /**< Arbitration lost interrupt enable */
\r
3957 /* EUSCI_B_IE[NACKIE] Bits */
\r
3958 #define EUSCI_B_IE_NACKIE_OFS ( 5) /**< UCNACKIE Bit Offset */
\r
3959 #define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /**< Not-acknowledge interrupt enable */
\r
3960 /* EUSCI_B_IE[BCNTIE] Bits */
\r
3961 #define EUSCI_B_IE_BCNTIE_OFS ( 6) /**< UCBCNTIE Bit Offset */
\r
3962 #define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /**< Byte counter interrupt enable */
\r
3963 /* EUSCI_B_IE[CLTOIE] Bits */
\r
3964 #define EUSCI_B_IE_CLTOIE_OFS ( 7) /**< UCCLTOIE Bit Offset */
\r
3965 #define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /**< Clock low timeout interrupt enable */
\r
3966 /* EUSCI_B_IE[RXIE1] Bits */
\r
3967 #define EUSCI_B_IE_RXIE1_OFS ( 8) /**< UCRXIE1 Bit Offset */
\r
3968 #define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /**< Receive interrupt enable 1 */
\r
3969 /* EUSCI_B_IE[TXIE1] Bits */
\r
3970 #define EUSCI_B_IE_TXIE1_OFS ( 9) /**< UCTXIE1 Bit Offset */
\r
3971 #define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /**< Transmit interrupt enable 1 */
\r
3972 /* EUSCI_B_IE[RXIE2] Bits */
\r
3973 #define EUSCI_B_IE_RXIE2_OFS (10) /**< UCRXIE2 Bit Offset */
\r
3974 #define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /**< Receive interrupt enable 2 */
\r
3975 /* EUSCI_B_IE[TXIE2] Bits */
\r
3976 #define EUSCI_B_IE_TXIE2_OFS (11) /**< UCTXIE2 Bit Offset */
\r
3977 #define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /**< Transmit interrupt enable 2 */
\r
3978 /* EUSCI_B_IE[RXIE3] Bits */
\r
3979 #define EUSCI_B_IE_RXIE3_OFS (12) /**< UCRXIE3 Bit Offset */
\r
3980 #define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /**< Receive interrupt enable 3 */
\r
3981 /* EUSCI_B_IE[TXIE3] Bits */
\r
3982 #define EUSCI_B_IE_TXIE3_OFS (13) /**< UCTXIE3 Bit Offset */
\r
3983 #define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /**< Transmit interrupt enable 3 */
\r
3984 /* EUSCI_B_IE[BIT9IE] Bits */
\r
3985 #define EUSCI_B_IE_BIT9IE_OFS (14) /**< UCBIT9IE Bit Offset */
\r
3986 #define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /**< Bit position 9 interrupt enable */
\r
3987 /* EUSCI_B_UCBxIE_SPI[RXIE] Bits */
\r
3988 #define EUSCI_B__RXIE_OFS ( 0) /**< UCRXIE Bit Offset */
\r
3989 #define EUSCI_B__RXIE ((uint16_t)0x0001) /**< Receive interrupt enable */
\r
3990 /* EUSCI_B_UCBxIE_SPI[TXIE] Bits */
\r
3991 #define EUSCI_B__TXIE_OFS ( 1) /**< UCTXIE Bit Offset */
\r
3992 #define EUSCI_B__TXIE ((uint16_t)0x0002) /**< Transmit interrupt enable */
\r
3993 /* EUSCI_B_IFG[RXIFG0] Bits */
\r
3994 #define EUSCI_B_IFG_RXIFG0_OFS ( 0) /**< UCRXIFG0 Bit Offset */
\r
3995 #define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /**< eUSCI_B receive interrupt flag 0 */
\r
3996 /* EUSCI_B_IFG[TXIFG0] Bits */
\r
3997 #define EUSCI_B_IFG_TXIFG0_OFS ( 1) /**< UCTXIFG0 Bit Offset */
\r
3998 #define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /**< eUSCI_B transmit interrupt flag 0 */
\r
3999 /* EUSCI_B_IFG[STTIFG] Bits */
\r
4000 #define EUSCI_B_IFG_STTIFG_OFS ( 2) /**< UCSTTIFG Bit Offset */
\r
4001 #define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /**< START condition interrupt flag */
\r
4002 /* EUSCI_B_IFG[STPIFG] Bits */
\r
4003 #define EUSCI_B_IFG_STPIFG_OFS ( 3) /**< UCSTPIFG Bit Offset */
\r
4004 #define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /**< STOP condition interrupt flag */
\r
4005 /* EUSCI_B_IFG[ALIFG] Bits */
\r
4006 #define EUSCI_B_IFG_ALIFG_OFS ( 4) /**< UCALIFG Bit Offset */
\r
4007 #define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /**< Arbitration lost interrupt flag */
\r
4008 /* EUSCI_B_IFG[NACKIFG] Bits */
\r
4009 #define EUSCI_B_IFG_NACKIFG_OFS ( 5) /**< UCNACKIFG Bit Offset */
\r
4010 #define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /**< Not-acknowledge received interrupt flag */
\r
4011 /* EUSCI_B_IFG[BCNTIFG] Bits */
\r
4012 #define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /**< UCBCNTIFG Bit Offset */
\r
4013 #define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /**< Byte counter interrupt flag */
\r
4014 /* EUSCI_B_IFG[CLTOIFG] Bits */
\r
4015 #define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /**< UCCLTOIFG Bit Offset */
\r
4016 #define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /**< Clock low timeout interrupt flag */
\r
4017 /* EUSCI_B_IFG[RXIFG1] Bits */
\r
4018 #define EUSCI_B_IFG_RXIFG1_OFS ( 8) /**< UCRXIFG1 Bit Offset */
\r
4019 #define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /**< eUSCI_B receive interrupt flag 1 */
\r
4020 /* EUSCI_B_IFG[TXIFG1] Bits */
\r
4021 #define EUSCI_B_IFG_TXIFG1_OFS ( 9) /**< UCTXIFG1 Bit Offset */
\r
4022 #define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /**< eUSCI_B transmit interrupt flag 1 */
\r
4023 /* EUSCI_B_IFG[RXIFG2] Bits */
\r
4024 #define EUSCI_B_IFG_RXIFG2_OFS (10) /**< UCRXIFG2 Bit Offset */
\r
4025 #define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /**< eUSCI_B receive interrupt flag 2 */
\r
4026 /* EUSCI_B_IFG[TXIFG2] Bits */
\r
4027 #define EUSCI_B_IFG_TXIFG2_OFS (11) /**< UCTXIFG2 Bit Offset */
\r
4028 #define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /**< eUSCI_B transmit interrupt flag 2 */
\r
4029 /* EUSCI_B_IFG[RXIFG3] Bits */
\r
4030 #define EUSCI_B_IFG_RXIFG3_OFS (12) /**< UCRXIFG3 Bit Offset */
\r
4031 #define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /**< eUSCI_B receive interrupt flag 3 */
\r
4032 /* EUSCI_B_IFG[TXIFG3] Bits */
\r
4033 #define EUSCI_B_IFG_TXIFG3_OFS (13) /**< UCTXIFG3 Bit Offset */
\r
4034 #define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /**< eUSCI_B transmit interrupt flag 3 */
\r
4035 /* EUSCI_B_IFG[BIT9IFG] Bits */
\r
4036 #define EUSCI_B_IFG_BIT9IFG_OFS (14) /**< UCBIT9IFG Bit Offset */
\r
4037 #define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /**< Bit position 9 interrupt flag */
\r
4038 /* EUSCI_B_IFG[RXIFG] Bits */
\r
4039 #define EUSCI_B_IFG_RXIFG_OFS ( 0) /**< UCRXIFG Bit Offset */
\r
4040 #define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /**< Receive interrupt flag */
\r
4041 /* EUSCI_B_IFG[TXIFG] Bits */
\r
4042 #define EUSCI_B_IFG_TXIFG_OFS ( 1) /**< UCTXIFG Bit Offset */
\r
4043 #define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /**< Transmit interrupt flag */
\r
4046 /******************************************************************************
\r
4048 ******************************************************************************/
\r
4049 /* FLCTL_POWER_STAT[PSTAT] Bits */
\r
4050 #define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /**< PSTAT Bit Offset */
\r
4051 #define FLCTL_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /**< PSTAT Bit Mask */
\r
4052 #define FLCTL_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /**< PSTAT Bit 0 */
\r
4053 #define FLCTL_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /**< PSTAT Bit 1 */
\r
4054 #define FLCTL_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /**< PSTAT Bit 2 */
\r
4055 #define FLCTL_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /**< Flash IP in power-down mode */
\r
4056 #define FLCTL_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /**< Flash IP Vdd domain power-up in progress */
\r
4057 #define FLCTL_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /**< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */
\r
4058 #define FLCTL_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /**< Flash IP SAFE_LV check in progress */
\r
4059 #define FLCTL_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /**< Flash IP Active */
\r
4060 #define FLCTL_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /**< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */
\r
4061 #define FLCTL_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /**< Flash IP in Standby mode */
\r
4062 #define FLCTL_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /**< Flash IP in Current mirror boost state */
\r
4063 /* FLCTL_POWER_STAT[LDOSTAT] Bits */
\r
4064 #define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /**< LDOSTAT Bit Offset */
\r
4065 #define FLCTL_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /**< PSS FLDO GOOD status */
\r
4066 /* FLCTL_POWER_STAT[VREFSTAT] Bits */
\r
4067 #define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /**< VREFSTAT Bit Offset */
\r
4068 #define FLCTL_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /**< PSS VREF stable status */
\r
4069 /* FLCTL_POWER_STAT[IREFSTAT] Bits */
\r
4070 #define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /**< IREFSTAT Bit Offset */
\r
4071 #define FLCTL_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /**< PSS IREF stable status */
\r
4072 /* FLCTL_POWER_STAT[TRIMSTAT] Bits */
\r
4073 #define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /**< TRIMSTAT Bit Offset */
\r
4074 #define FLCTL_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /**< PSS trim done status */
\r
4075 /* FLCTL_POWER_STAT[RD_2T] Bits */
\r
4076 #define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /**< RD_2T Bit Offset */
\r
4077 #define FLCTL_POWER_STAT_RD_2T ((uint32_t)0x00000080) /**< Indicates if Flash is being accessed in 2T mode */
\r
4078 /* FLCTL_BANK0_RDCTL[RD_MODE] Bits */
\r
4079 #define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /**< RD_MODE Bit Offset */
\r
4080 #define FLCTL_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /**< RD_MODE Bit Mask */
\r
4081 #define FLCTL_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /**< RD_MODE Bit 0 */
\r
4082 #define FLCTL_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /**< RD_MODE Bit 1 */
\r
4083 #define FLCTL_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /**< RD_MODE Bit 2 */
\r
4084 #define FLCTL_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /**< RD_MODE Bit 3 */
\r
4085 #define FLCTL_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /**< Normal read mode */
\r
4086 #define FLCTL_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /**< Read Margin 0 */
\r
4087 #define FLCTL_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /**< Read Margin 1 */
\r
4088 #define FLCTL_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /**< Program Verify */
\r
4089 #define FLCTL_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /**< Erase Verify */
\r
4090 #define FLCTL_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /**< Leakage Verify */
\r
4091 #define FLCTL_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /**< Read Margin 0B */
\r
4092 #define FLCTL_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /**< Read Margin 1B */
\r
4093 /* FLCTL_BANK0_RDCTL[BUFI] Bits */
\r
4094 #define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /**< BUFI Bit Offset */
\r
4095 #define FLCTL_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /**< Enables read buffering feature for instruction fetches to this Bank */
\r
4096 /* FLCTL_BANK0_RDCTL[BUFD] Bits */
\r
4097 #define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /**< BUFD Bit Offset */
\r
4098 #define FLCTL_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /**< Enables read buffering feature for data reads to this Bank */
\r
4099 /* FLCTL_BANK0_RDCTL[WAIT] Bits */
\r
4100 #define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /**< WAIT Bit Offset */
\r
4101 #define FLCTL_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /**< WAIT Bit Mask */
\r
4102 #define FLCTL_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /**< WAIT Bit 0 */
\r
4103 #define FLCTL_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /**< WAIT Bit 1 */
\r
4104 #define FLCTL_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /**< WAIT Bit 2 */
\r
4105 #define FLCTL_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /**< WAIT Bit 3 */
\r
4106 #define FLCTL_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /**< 0 wait states */
\r
4107 #define FLCTL_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /**< 1 wait states */
\r
4108 #define FLCTL_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /**< 2 wait states */
\r
4109 #define FLCTL_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /**< 3 wait states */
\r
4110 #define FLCTL_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /**< 4 wait states */
\r
4111 #define FLCTL_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /**< 5 wait states */
\r
4112 #define FLCTL_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /**< 6 wait states */
\r
4113 #define FLCTL_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /**< 7 wait states */
\r
4114 #define FLCTL_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /**< 8 wait states */
\r
4115 #define FLCTL_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /**< 9 wait states */
\r
4116 #define FLCTL_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /**< 10 wait states */
\r
4117 #define FLCTL_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /**< 11 wait states */
\r
4118 #define FLCTL_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /**< 12 wait states */
\r
4119 #define FLCTL_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /**< 13 wait states */
\r
4120 #define FLCTL_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /**< 14 wait states */
\r
4121 #define FLCTL_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /**< 15 wait states */
\r
4122 /* FLCTL_BANK0_RDCTL[RD_MODE_STATUS] Bits */
\r
4123 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /**< RD_MODE_STATUS Bit Offset */
\r
4124 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /**< RD_MODE_STATUS Bit Mask */
\r
4125 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /**< RD_MODE_STATUS Bit 0 */
\r
4126 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /**< RD_MODE_STATUS Bit 1 */
\r
4127 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /**< RD_MODE_STATUS Bit 2 */
\r
4128 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /**< RD_MODE_STATUS Bit 3 */
\r
4129 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /**< Normal read mode */
\r
4130 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /**< Read Margin 0 */
\r
4131 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /**< Read Margin 1 */
\r
4132 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /**< Program Verify */
\r
4133 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /**< Erase Verify */
\r
4134 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /**< Leakage Verify */
\r
4135 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /**< Read Margin 0B */
\r
4136 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /**< Read Margin 1B */
\r
4137 /* FLCTL_BANK1_RDCTL[RD_MODE] Bits */
\r
4138 #define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /**< RD_MODE Bit Offset */
\r
4139 #define FLCTL_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /**< RD_MODE Bit Mask */
\r
4140 #define FLCTL_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /**< RD_MODE Bit 0 */
\r
4141 #define FLCTL_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /**< RD_MODE Bit 1 */
\r
4142 #define FLCTL_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /**< RD_MODE Bit 2 */
\r
4143 #define FLCTL_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /**< RD_MODE Bit 3 */
\r
4144 #define FLCTL_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /**< Normal read mode */
\r
4145 #define FLCTL_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /**< Read Margin 0 */
\r
4146 #define FLCTL_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /**< Read Margin 1 */
\r
4147 #define FLCTL_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /**< Program Verify */
\r
4148 #define FLCTL_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /**< Erase Verify */
\r
4149 #define FLCTL_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /**< Leakage Verify */
\r
4150 #define FLCTL_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /**< Read Margin 0B */
\r
4151 #define FLCTL_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /**< Read Margin 1B */
\r
4152 /* FLCTL_BANK1_RDCTL[BUFI] Bits */
\r
4153 #define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /**< BUFI Bit Offset */
\r
4154 #define FLCTL_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /**< Enables read buffering feature for instruction fetches to this Bank */
\r
4155 /* FLCTL_BANK1_RDCTL[BUFD] Bits */
\r
4156 #define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /**< BUFD Bit Offset */
\r
4157 #define FLCTL_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /**< Enables read buffering feature for data reads to this Bank */
\r
4158 /* FLCTL_BANK1_RDCTL[RD_MODE_STATUS] Bits */
\r
4159 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /**< RD_MODE_STATUS Bit Offset */
\r
4160 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /**< RD_MODE_STATUS Bit Mask */
\r
4161 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /**< RD_MODE_STATUS Bit 0 */
\r
4162 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /**< RD_MODE_STATUS Bit 1 */
\r
4163 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /**< RD_MODE_STATUS Bit 2 */
\r
4164 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /**< RD_MODE_STATUS Bit 3 */
\r
4165 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /**< Normal read mode */
\r
4166 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /**< Read Margin 0 */
\r
4167 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /**< Read Margin 1 */
\r
4168 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /**< Program Verify */
\r
4169 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /**< Erase Verify */
\r
4170 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /**< Leakage Verify */
\r
4171 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /**< Read Margin 0B */
\r
4172 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /**< Read Margin 1B */
\r
4173 /* FLCTL_BANK1_RDCTL[WAIT] Bits */
\r
4174 #define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /**< WAIT Bit Offset */
\r
4175 #define FLCTL_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /**< WAIT Bit Mask */
\r
4176 #define FLCTL_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /**< WAIT Bit 0 */
\r
4177 #define FLCTL_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /**< WAIT Bit 1 */
\r
4178 #define FLCTL_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /**< WAIT Bit 2 */
\r
4179 #define FLCTL_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /**< WAIT Bit 3 */
\r
4180 #define FLCTL_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /**< 0 wait states */
\r
4181 #define FLCTL_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /**< 1 wait states */
\r
4182 #define FLCTL_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /**< 2 wait states */
\r
4183 #define FLCTL_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /**< 3 wait states */
\r
4184 #define FLCTL_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /**< 4 wait states */
\r
4185 #define FLCTL_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /**< 5 wait states */
\r
4186 #define FLCTL_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /**< 6 wait states */
\r
4187 #define FLCTL_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /**< 7 wait states */
\r
4188 #define FLCTL_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /**< 8 wait states */
\r
4189 #define FLCTL_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /**< 9 wait states */
\r
4190 #define FLCTL_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /**< 10 wait states */
\r
4191 #define FLCTL_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /**< 11 wait states */
\r
4192 #define FLCTL_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /**< 12 wait states */
\r
4193 #define FLCTL_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /**< 13 wait states */
\r
4194 #define FLCTL_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /**< 14 wait states */
\r
4195 #define FLCTL_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /**< 15 wait states */
\r
4196 /* FLCTL_RDBRST_CTLSTAT[START] Bits */
\r
4197 #define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /**< START Bit Offset */
\r
4198 #define FLCTL_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /**< Start of burst/compare operation */
\r
4199 /* FLCTL_RDBRST_CTLSTAT[MEM_TYPE] Bits */
\r
4200 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /**< MEM_TYPE Bit Offset */
\r
4201 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /**< MEM_TYPE Bit Mask */
\r
4202 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /**< MEM_TYPE Bit 0 */
\r
4203 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /**< MEM_TYPE Bit 1 */
\r
4204 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /**< Main Memory */
\r
4205 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /**< Information Memory */
\r
4206 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /**< Reserved */
\r
4207 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /**< Engineering Memory */
\r
4208 /* FLCTL_RDBRST_CTLSTAT[STOP_FAIL] Bits */
\r
4209 #define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /**< STOP_FAIL Bit Offset */
\r
4210 #define FLCTL_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /**< Terminate burst/compare operation */
\r
4211 /* FLCTL_RDBRST_CTLSTAT[DATA_CMP] Bits */
\r
4212 #define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /**< DATA_CMP Bit Offset */
\r
4213 #define FLCTL_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /**< Data pattern used for comparison against memory read data */
\r
4214 /* FLCTL_RDBRST_CTLSTAT[TEST_EN] Bits */
\r
4215 #define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /**< TEST_EN Bit Offset */
\r
4216 #define FLCTL_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /**< Enable comparison against test data compare registers */
\r
4217 /* FLCTL_RDBRST_CTLSTAT[BRST_STAT] Bits */
\r
4218 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /**< BRST_STAT Bit Offset */
\r
4219 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /**< BRST_STAT Bit Mask */
\r
4220 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /**< BRST_STAT Bit 0 */
\r
4221 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /**< BRST_STAT Bit 1 */
\r
4222 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /**< Idle */
\r
4223 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /**< Burst/Compare START bit written, but operation pending */
\r
4224 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /**< Burst/Compare in progress */
\r
4225 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /**< Burst complete (status of completed burst remains in this state unless */
\r
4226 /* explicitly cleared by SW) */
\r
4227 /* FLCTL_RDBRST_CTLSTAT[CMP_ERR] Bits */
\r
4228 #define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /**< CMP_ERR Bit Offset */
\r
4229 #define FLCTL_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /**< Burst/Compare Operation encountered atleast one data */
\r
4230 /* FLCTL_RDBRST_CTLSTAT[ADDR_ERR] Bits */
\r
4231 #define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /**< ADDR_ERR Bit Offset */
\r
4232 #define FLCTL_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /**< Burst/Compare Operation was terminated due to access to */
\r
4233 /* FLCTL_RDBRST_CTLSTAT[CLR_STAT] Bits */
\r
4234 #define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /**< CLR_STAT Bit Offset */
\r
4235 #define FLCTL_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /**< Clear status bits 19-16 of this register */
\r
4236 /* FLCTL_RDBRST_STARTADDR[START_ADDRESS] Bits */
\r
4237 #define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /**< START_ADDRESS Bit Offset */
\r
4238 #define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /**< START_ADDRESS Bit Mask */
\r
4239 /* FLCTL_RDBRST_LEN[BURST_LENGTH] Bits */
\r
4240 #define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /**< BURST_LENGTH Bit Offset */
\r
4241 #define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /**< BURST_LENGTH Bit Mask */
\r
4242 /* FLCTL_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */
\r
4243 #define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /**< FAIL_ADDRESS Bit Offset */
\r
4244 #define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /**< FAIL_ADDRESS Bit Mask */
\r
4245 /* FLCTL_RDBRST_FAILCNT[FAIL_COUNT] Bits */
\r
4246 #define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /**< FAIL_COUNT Bit Offset */
\r
4247 #define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /**< FAIL_COUNT Bit Mask */
\r
4248 /* FLCTL_PRG_CTLSTAT[ENABLE] Bits */
\r
4249 #define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /**< ENABLE Bit Offset */
\r
4250 #define FLCTL_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /**< Master control for all word program operations */
\r
4251 /* FLCTL_PRG_CTLSTAT[MODE] Bits */
\r
4252 #define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /**< MODE Bit Offset */
\r
4253 #define FLCTL_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /**< Write mode */
\r
4254 /* FLCTL_PRG_CTLSTAT[VER_PRE] Bits */
\r
4255 #define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /**< VER_PRE Bit Offset */
\r
4256 #define FLCTL_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /**< Controls automatic pre program verify operations */
\r
4257 /* FLCTL_PRG_CTLSTAT[VER_PST] Bits */
\r
4258 #define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /**< VER_PST Bit Offset */
\r
4259 #define FLCTL_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /**< Controls automatic post program verify operations */
\r
4260 /* FLCTL_PRG_CTLSTAT[STATUS] Bits */
\r
4261 #define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /**< STATUS Bit Offset */
\r
4262 #define FLCTL_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /**< STATUS Bit Mask */
\r
4263 #define FLCTL_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /**< STATUS Bit 0 */
\r
4264 #define FLCTL_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /**< STATUS Bit 1 */
\r
4265 #define FLCTL_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /**< Idle (no program operation currently active) */
\r
4266 #define FLCTL_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /**< Single word program operation triggered, but pending */
\r
4267 #define FLCTL_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /**< Single word program in progress */
\r
4268 #define FLCTL_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /**< Reserved (Idle) */
\r
4269 /* FLCTL_PRG_CTLSTAT[BNK_ACT] Bits */
\r
4270 #define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /**< BNK_ACT Bit Offset */
\r
4271 #define FLCTL_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /**< Bank active */
\r
4272 /* FLCTL_PRGBRST_CTLSTAT[START] Bits */
\r
4273 #define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /**< START Bit Offset */
\r
4274 #define FLCTL_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /**< Trigger start of burst program operation */
\r
4275 /* FLCTL_PRGBRST_CTLSTAT[TYPE] Bits */
\r
4276 #define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /**< TYPE Bit Offset */
\r
4277 #define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /**< TYPE Bit Mask */
\r
4278 #define FLCTL_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /**< TYPE Bit 0 */
\r
4279 #define FLCTL_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /**< TYPE Bit 1 */
\r
4280 #define FLCTL_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /**< Main Memory */
\r
4281 #define FLCTL_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /**< Information Memory */
\r
4282 #define FLCTL_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /**< Reserved */
\r
4283 #define FLCTL_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /**< Engineering Memory */
\r
4284 /* FLCTL_PRGBRST_CTLSTAT[LEN] Bits */
\r
4285 #define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /**< LEN Bit Offset */
\r
4286 #define FLCTL_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /**< LEN Bit Mask */
\r
4287 #define FLCTL_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /**< LEN Bit 0 */
\r
4288 #define FLCTL_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /**< LEN Bit 1 */
\r
4289 #define FLCTL_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /**< LEN Bit 2 */
\r
4290 #define FLCTL_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /**< No burst operation */
\r
4291 #define FLCTL_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /**< 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR */
\r
4293 #define FLCTL_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /**< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */
\r
4295 #define FLCTL_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /**< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */
\r
4297 #define FLCTL_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /**< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */
\r
4299 /* FLCTL_PRGBRST_CTLSTAT[AUTO_PRE] Bits */
\r
4300 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /**< AUTO_PRE Bit Offset */
\r
4301 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /**< Auto-Verify operation before the Burst Program */
\r
4302 /* FLCTL_PRGBRST_CTLSTAT[AUTO_PST] Bits */
\r
4303 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /**< AUTO_PST Bit Offset */
\r
4304 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /**< Auto-Verify operation after the Burst Program */
\r
4305 /* FLCTL_PRGBRST_CTLSTAT[BURST_STATUS] Bits */
\r
4306 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /**< BURST_STATUS Bit Offset */
\r
4307 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /**< BURST_STATUS Bit Mask */
\r
4308 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /**< BURST_STATUS Bit 0 */
\r
4309 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /**< BURST_STATUS Bit 1 */
\r
4310 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /**< BURST_STATUS Bit 2 */
\r
4311 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /**< Idle (Burst not active) */
\r
4312 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /**< Burst program started but pending */
\r
4313 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /**< Burst active, with 1st 128 bit word being written into Flash */
\r
4314 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /**< Burst active, with 2nd 128 bit word being written into Flash */
\r
4315 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /**< Burst active, with 3rd 128 bit word being written into Flash */
\r
4316 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /**< Burst active, with 4th 128 bit word being written into Flash */
\r
4317 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /**< Reserved (Idle) */
\r
4318 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /**< Burst Complete (status of completed burst remains in this state unless */
\r
4319 /* explicitly cleared by SW) */
\r
4320 /* FLCTL_PRGBRST_CTLSTAT[PRE_ERR] Bits */
\r
4321 #define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /**< PRE_ERR Bit Offset */
\r
4322 #define FLCTL_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /**< Burst Operation encountered preprogram auto-verify errors */
\r
4323 /* FLCTL_PRGBRST_CTLSTAT[PST_ERR] Bits */
\r
4324 #define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /**< PST_ERR Bit Offset */
\r
4325 #define FLCTL_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /**< Burst Operation encountered postprogram auto-verify errors */
\r
4326 /* FLCTL_PRGBRST_CTLSTAT[ADDR_ERR] Bits */
\r
4327 #define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /**< ADDR_ERR Bit Offset */
\r
4328 #define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /**< Burst Operation was terminated due to attempted program of reserved memory */
\r
4329 /* FLCTL_PRGBRST_CTLSTAT[CLR_STAT] Bits */
\r
4330 #define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /**< CLR_STAT Bit Offset */
\r
4331 #define FLCTL_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /**< Clear status bits 21-16 of this register */
\r
4332 /* FLCTL_PRGBRST_STARTADDR[START_ADDRESS] Bits */
\r
4333 #define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /**< START_ADDRESS Bit Offset */
\r
4334 #define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /**< START_ADDRESS Bit Mask */
\r
4335 /* FLCTL_ERASE_CTLSTAT[START] Bits */
\r
4336 #define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /**< START Bit Offset */
\r
4337 #define FLCTL_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /**< Start of Erase operation */
\r
4338 /* FLCTL_ERASE_CTLSTAT[MODE] Bits */
\r
4339 #define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /**< MODE Bit Offset */
\r
4340 #define FLCTL_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /**< Erase mode selected by application */
\r
4341 /* FLCTL_ERASE_CTLSTAT[TYPE] Bits */
\r
4342 #define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /**< TYPE Bit Offset */
\r
4343 #define FLCTL_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /**< TYPE Bit Mask */
\r
4344 #define FLCTL_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /**< TYPE Bit 0 */
\r
4345 #define FLCTL_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /**< TYPE Bit 1 */
\r
4346 #define FLCTL_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /**< Main Memory */
\r
4347 #define FLCTL_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /**< Information Memory */
\r
4348 #define FLCTL_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /**< Reserved */
\r
4349 #define FLCTL_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /**< Engineering Memory */
\r
4350 /* FLCTL_ERASE_CTLSTAT[STATUS] Bits */
\r
4351 #define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /**< STATUS Bit Offset */
\r
4352 #define FLCTL_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /**< STATUS Bit Mask */
\r
4353 #define FLCTL_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /**< STATUS Bit 0 */
\r
4354 #define FLCTL_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /**< STATUS Bit 1 */
\r
4355 #define FLCTL_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /**< Idle (no program operation currently active) */
\r
4356 #define FLCTL_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /**< Erase operation triggered to START but pending */
\r
4357 #define FLCTL_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /**< Erase operation in progress */
\r
4358 #define FLCTL_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /**< Erase operation completed (status of completed erase remains in this state */
\r
4359 /* unless explicitly cleared by SW) */
\r
4360 /* FLCTL_ERASE_CTLSTAT[ADDR_ERR] Bits */
\r
4361 #define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /**< ADDR_ERR Bit Offset */
\r
4362 #define FLCTL_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /**< Erase Operation was terminated due to attempted erase of reserved memory */
\r
4364 /* FLCTL_ERASE_CTLSTAT[CLR_STAT] Bits */
\r
4365 #define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /**< CLR_STAT Bit Offset */
\r
4366 #define FLCTL_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /**< Clear status bits 18-16 of this register */
\r
4367 /* FLCTL_ERASE_SECTADDR[SECT_ADDRESS] Bits */
\r
4368 #define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /**< SECT_ADDRESS Bit Offset */
\r
4369 #define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /**< SECT_ADDRESS Bit Mask */
\r
4370 /* FLCTL_BANK0_INFO_WEPROT[PROT0] Bits */
\r
4371 #define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */
\r
4372 #define FLCTL_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase */
\r
4373 /* FLCTL_BANK0_INFO_WEPROT[PROT1] Bits */
\r
4374 #define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */
\r
4375 #define FLCTL_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase */
\r
4376 /* FLCTL_BANK0_MAIN_WEPROT[PROT0] Bits */
\r
4377 #define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */
\r
4378 #define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase */
\r
4379 /* FLCTL_BANK0_MAIN_WEPROT[PROT1] Bits */
\r
4380 #define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */
\r
4381 #define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase */
\r
4382 /* FLCTL_BANK0_MAIN_WEPROT[PROT2] Bits */
\r
4383 #define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /**< PROT2 Bit Offset */
\r
4384 #define FLCTL_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /**< Protects Sector 2 from program or erase */
\r
4385 /* FLCTL_BANK0_MAIN_WEPROT[PROT3] Bits */
\r
4386 #define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /**< PROT3 Bit Offset */
\r
4387 #define FLCTL_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /**< Protects Sector 3 from program or erase */
\r
4388 /* FLCTL_BANK0_MAIN_WEPROT[PROT4] Bits */
\r
4389 #define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /**< PROT4 Bit Offset */
\r
4390 #define FLCTL_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /**< Protects Sector 4 from program or erase */
\r
4391 /* FLCTL_BANK0_MAIN_WEPROT[PROT5] Bits */
\r
4392 #define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /**< PROT5 Bit Offset */
\r
4393 #define FLCTL_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /**< Protects Sector 5 from program or erase */
\r
4394 /* FLCTL_BANK0_MAIN_WEPROT[PROT6] Bits */
\r
4395 #define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /**< PROT6 Bit Offset */
\r
4396 #define FLCTL_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /**< Protects Sector 6 from program or erase */
\r
4397 /* FLCTL_BANK0_MAIN_WEPROT[PROT7] Bits */
\r
4398 #define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /**< PROT7 Bit Offset */
\r
4399 #define FLCTL_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /**< Protects Sector 7 from program or erase */
\r
4400 /* FLCTL_BANK0_MAIN_WEPROT[PROT8] Bits */
\r
4401 #define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /**< PROT8 Bit Offset */
\r
4402 #define FLCTL_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /**< Protects Sector 8 from program or erase */
\r
4403 /* FLCTL_BANK0_MAIN_WEPROT[PROT9] Bits */
\r
4404 #define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /**< PROT9 Bit Offset */
\r
4405 #define FLCTL_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /**< Protects Sector 9 from program or erase */
\r
4406 /* FLCTL_BANK0_MAIN_WEPROT[PROT10] Bits */
\r
4407 #define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /**< PROT10 Bit Offset */
\r
4408 #define FLCTL_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /**< Protects Sector 10 from program or erase */
\r
4409 /* FLCTL_BANK0_MAIN_WEPROT[PROT11] Bits */
\r
4410 #define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /**< PROT11 Bit Offset */
\r
4411 #define FLCTL_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /**< Protects Sector 11 from program or erase */
\r
4412 /* FLCTL_BANK0_MAIN_WEPROT[PROT12] Bits */
\r
4413 #define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /**< PROT12 Bit Offset */
\r
4414 #define FLCTL_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /**< Protects Sector 12 from program or erase */
\r
4415 /* FLCTL_BANK0_MAIN_WEPROT[PROT13] Bits */
\r
4416 #define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /**< PROT13 Bit Offset */
\r
4417 #define FLCTL_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /**< Protects Sector 13 from program or erase */
\r
4418 /* FLCTL_BANK0_MAIN_WEPROT[PROT14] Bits */
\r
4419 #define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /**< PROT14 Bit Offset */
\r
4420 #define FLCTL_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /**< Protects Sector 14 from program or erase */
\r
4421 /* FLCTL_BANK0_MAIN_WEPROT[PROT15] Bits */
\r
4422 #define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /**< PROT15 Bit Offset */
\r
4423 #define FLCTL_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /**< Protects Sector 15 from program or erase */
\r
4424 /* FLCTL_BANK0_MAIN_WEPROT[PROT16] Bits */
\r
4425 #define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /**< PROT16 Bit Offset */
\r
4426 #define FLCTL_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /**< Protects Sector 16 from program or erase */
\r
4427 /* FLCTL_BANK0_MAIN_WEPROT[PROT17] Bits */
\r
4428 #define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /**< PROT17 Bit Offset */
\r
4429 #define FLCTL_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /**< Protects Sector 17 from program or erase */
\r
4430 /* FLCTL_BANK0_MAIN_WEPROT[PROT18] Bits */
\r
4431 #define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /**< PROT18 Bit Offset */
\r
4432 #define FLCTL_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /**< Protects Sector 18 from program or erase */
\r
4433 /* FLCTL_BANK0_MAIN_WEPROT[PROT19] Bits */
\r
4434 #define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /**< PROT19 Bit Offset */
\r
4435 #define FLCTL_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /**< Protects Sector 19 from program or erase */
\r
4436 /* FLCTL_BANK0_MAIN_WEPROT[PROT20] Bits */
\r
4437 #define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /**< PROT20 Bit Offset */
\r
4438 #define FLCTL_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /**< Protects Sector 20 from program or erase */
\r
4439 /* FLCTL_BANK0_MAIN_WEPROT[PROT21] Bits */
\r
4440 #define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /**< PROT21 Bit Offset */
\r
4441 #define FLCTL_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /**< Protects Sector 21 from program or erase */
\r
4442 /* FLCTL_BANK0_MAIN_WEPROT[PROT22] Bits */
\r
4443 #define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /**< PROT22 Bit Offset */
\r
4444 #define FLCTL_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /**< Protects Sector 22 from program or erase */
\r
4445 /* FLCTL_BANK0_MAIN_WEPROT[PROT23] Bits */
\r
4446 #define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /**< PROT23 Bit Offset */
\r
4447 #define FLCTL_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /**< Protects Sector 23 from program or erase */
\r
4448 /* FLCTL_BANK0_MAIN_WEPROT[PROT24] Bits */
\r
4449 #define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /**< PROT24 Bit Offset */
\r
4450 #define FLCTL_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /**< Protects Sector 24 from program or erase */
\r
4451 /* FLCTL_BANK0_MAIN_WEPROT[PROT25] Bits */
\r
4452 #define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /**< PROT25 Bit Offset */
\r
4453 #define FLCTL_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /**< Protects Sector 25 from program or erase */
\r
4454 /* FLCTL_BANK0_MAIN_WEPROT[PROT26] Bits */
\r
4455 #define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /**< PROT26 Bit Offset */
\r
4456 #define FLCTL_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /**< Protects Sector 26 from program or erase */
\r
4457 /* FLCTL_BANK0_MAIN_WEPROT[PROT27] Bits */
\r
4458 #define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /**< PROT27 Bit Offset */
\r
4459 #define FLCTL_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /**< Protects Sector 27 from program or erase */
\r
4460 /* FLCTL_BANK0_MAIN_WEPROT[PROT28] Bits */
\r
4461 #define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /**< PROT28 Bit Offset */
\r
4462 #define FLCTL_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /**< Protects Sector 28 from program or erase */
\r
4463 /* FLCTL_BANK0_MAIN_WEPROT[PROT29] Bits */
\r
4464 #define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /**< PROT29 Bit Offset */
\r
4465 #define FLCTL_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /**< Protects Sector 29 from program or erase */
\r
4466 /* FLCTL_BANK0_MAIN_WEPROT[PROT30] Bits */
\r
4467 #define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /**< PROT30 Bit Offset */
\r
4468 #define FLCTL_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /**< Protects Sector 30 from program or erase */
\r
4469 /* FLCTL_BANK0_MAIN_WEPROT[PROT31] Bits */
\r
4470 #define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /**< PROT31 Bit Offset */
\r
4471 #define FLCTL_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /**< Protects Sector 31 from program or erase */
\r
4472 /* FLCTL_BANK1_INFO_WEPROT[PROT0] Bits */
\r
4473 #define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */
\r
4474 #define FLCTL_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase operations */
\r
4475 /* FLCTL_BANK1_INFO_WEPROT[PROT1] Bits */
\r
4476 #define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */
\r
4477 #define FLCTL_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase operations */
\r
4478 /* FLCTL_BANK1_MAIN_WEPROT[PROT0] Bits */
\r
4479 #define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */
\r
4480 #define FLCTL_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase operations */
\r
4481 /* FLCTL_BANK1_MAIN_WEPROT[PROT1] Bits */
\r
4482 #define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */
\r
4483 #define FLCTL_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase operations */
\r
4484 /* FLCTL_BANK1_MAIN_WEPROT[PROT2] Bits */
\r
4485 #define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /**< PROT2 Bit Offset */
\r
4486 #define FLCTL_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /**< Protects Sector 2 from program or erase operations */
\r
4487 /* FLCTL_BANK1_MAIN_WEPROT[PROT3] Bits */
\r
4488 #define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /**< PROT3 Bit Offset */
\r
4489 #define FLCTL_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /**< Protects Sector 3 from program or erase operations */
\r
4490 /* FLCTL_BANK1_MAIN_WEPROT[PROT4] Bits */
\r
4491 #define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /**< PROT4 Bit Offset */
\r
4492 #define FLCTL_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /**< Protects Sector 4 from program or erase operations */
\r
4493 /* FLCTL_BANK1_MAIN_WEPROT[PROT5] Bits */
\r
4494 #define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /**< PROT5 Bit Offset */
\r
4495 #define FLCTL_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /**< Protects Sector 5 from program or erase operations */
\r
4496 /* FLCTL_BANK1_MAIN_WEPROT[PROT6] Bits */
\r
4497 #define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /**< PROT6 Bit Offset */
\r
4498 #define FLCTL_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /**< Protects Sector 6 from program or erase operations */
\r
4499 /* FLCTL_BANK1_MAIN_WEPROT[PROT7] Bits */
\r
4500 #define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /**< PROT7 Bit Offset */
\r
4501 #define FLCTL_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /**< Protects Sector 7 from program or erase operations */
\r
4502 /* FLCTL_BANK1_MAIN_WEPROT[PROT8] Bits */
\r
4503 #define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /**< PROT8 Bit Offset */
\r
4504 #define FLCTL_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /**< Protects Sector 8 from program or erase operations */
\r
4505 /* FLCTL_BANK1_MAIN_WEPROT[PROT9] Bits */
\r
4506 #define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /**< PROT9 Bit Offset */
\r
4507 #define FLCTL_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /**< Protects Sector 9 from program or erase operations */
\r
4508 /* FLCTL_BANK1_MAIN_WEPROT[PROT10] Bits */
\r
4509 #define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /**< PROT10 Bit Offset */
\r
4510 #define FLCTL_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /**< Protects Sector 10 from program or erase operations */
\r
4511 /* FLCTL_BANK1_MAIN_WEPROT[PROT11] Bits */
\r
4512 #define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /**< PROT11 Bit Offset */
\r
4513 #define FLCTL_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /**< Protects Sector 11 from program or erase operations */
\r
4514 /* FLCTL_BANK1_MAIN_WEPROT[PROT12] Bits */
\r
4515 #define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /**< PROT12 Bit Offset */
\r
4516 #define FLCTL_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /**< Protects Sector 12 from program or erase operations */
\r
4517 /* FLCTL_BANK1_MAIN_WEPROT[PROT13] Bits */
\r
4518 #define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /**< PROT13 Bit Offset */
\r
4519 #define FLCTL_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /**< Protects Sector 13 from program or erase operations */
\r
4520 /* FLCTL_BANK1_MAIN_WEPROT[PROT14] Bits */
\r
4521 #define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /**< PROT14 Bit Offset */
\r
4522 #define FLCTL_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /**< Protects Sector 14 from program or erase operations */
\r
4523 /* FLCTL_BANK1_MAIN_WEPROT[PROT15] Bits */
\r
4524 #define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /**< PROT15 Bit Offset */
\r
4525 #define FLCTL_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /**< Protects Sector 15 from program or erase operations */
\r
4526 /* FLCTL_BANK1_MAIN_WEPROT[PROT16] Bits */
\r
4527 #define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /**< PROT16 Bit Offset */
\r
4528 #define FLCTL_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /**< Protects Sector 16 from program or erase operations */
\r
4529 /* FLCTL_BANK1_MAIN_WEPROT[PROT17] Bits */
\r
4530 #define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /**< PROT17 Bit Offset */
\r
4531 #define FLCTL_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /**< Protects Sector 17 from program or erase operations */
\r
4532 /* FLCTL_BANK1_MAIN_WEPROT[PROT18] Bits */
\r
4533 #define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /**< PROT18 Bit Offset */
\r
4534 #define FLCTL_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /**< Protects Sector 18 from program or erase operations */
\r
4535 /* FLCTL_BANK1_MAIN_WEPROT[PROT19] Bits */
\r
4536 #define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /**< PROT19 Bit Offset */
\r
4537 #define FLCTL_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /**< Protects Sector 19 from program or erase operations */
\r
4538 /* FLCTL_BANK1_MAIN_WEPROT[PROT20] Bits */
\r
4539 #define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /**< PROT20 Bit Offset */
\r
4540 #define FLCTL_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /**< Protects Sector 20 from program or erase operations */
\r
4541 /* FLCTL_BANK1_MAIN_WEPROT[PROT21] Bits */
\r
4542 #define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /**< PROT21 Bit Offset */
\r
4543 #define FLCTL_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /**< Protects Sector 21 from program or erase operations */
\r
4544 /* FLCTL_BANK1_MAIN_WEPROT[PROT22] Bits */
\r
4545 #define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /**< PROT22 Bit Offset */
\r
4546 #define FLCTL_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /**< Protects Sector 22 from program or erase operations */
\r
4547 /* FLCTL_BANK1_MAIN_WEPROT[PROT23] Bits */
\r
4548 #define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /**< PROT23 Bit Offset */
\r
4549 #define FLCTL_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /**< Protects Sector 23 from program or erase operations */
\r
4550 /* FLCTL_BANK1_MAIN_WEPROT[PROT24] Bits */
\r
4551 #define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /**< PROT24 Bit Offset */
\r
4552 #define FLCTL_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /**< Protects Sector 24 from program or erase operations */
\r
4553 /* FLCTL_BANK1_MAIN_WEPROT[PROT25] Bits */
\r
4554 #define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /**< PROT25 Bit Offset */
\r
4555 #define FLCTL_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /**< Protects Sector 25 from program or erase operations */
\r
4556 /* FLCTL_BANK1_MAIN_WEPROT[PROT26] Bits */
\r
4557 #define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /**< PROT26 Bit Offset */
\r
4558 #define FLCTL_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /**< Protects Sector 26 from program or erase operations */
\r
4559 /* FLCTL_BANK1_MAIN_WEPROT[PROT27] Bits */
\r
4560 #define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /**< PROT27 Bit Offset */
\r
4561 #define FLCTL_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /**< Protects Sector 27 from program or erase operations */
\r
4562 /* FLCTL_BANK1_MAIN_WEPROT[PROT28] Bits */
\r
4563 #define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /**< PROT28 Bit Offset */
\r
4564 #define FLCTL_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /**< Protects Sector 28 from program or erase operations */
\r
4565 /* FLCTL_BANK1_MAIN_WEPROT[PROT29] Bits */
\r
4566 #define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /**< PROT29 Bit Offset */
\r
4567 #define FLCTL_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /**< Protects Sector 29 from program or erase operations */
\r
4568 /* FLCTL_BANK1_MAIN_WEPROT[PROT30] Bits */
\r
4569 #define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /**< PROT30 Bit Offset */
\r
4570 #define FLCTL_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /**< Protects Sector 30 from program or erase operations */
\r
4571 /* FLCTL_BANK1_MAIN_WEPROT[PROT31] Bits */
\r
4572 #define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /**< PROT31 Bit Offset */
\r
4573 #define FLCTL_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /**< Protects Sector 31 from program or erase operations */
\r
4574 /* FLCTL_BMRK_CTLSTAT[I_BMRK] Bits */
\r
4575 #define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /**< I_BMRK Bit Offset */
\r
4576 #define FLCTL_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001)
\r
4577 /* FLCTL_BMRK_CTLSTAT[D_BMRK] Bits */
\r
4578 #define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /**< D_BMRK Bit Offset */
\r
4579 #define FLCTL_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002)
\r
4580 /* FLCTL_BMRK_CTLSTAT[CMP_EN] Bits */
\r
4581 #define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /**< CMP_EN Bit Offset */
\r
4582 #define FLCTL_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004)
\r
4583 /* FLCTL_BMRK_CTLSTAT[CMP_SEL] Bits */
\r
4584 #define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /**< CMP_SEL Bit Offset */
\r
4585 #define FLCTL_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008)
\r
4586 /* FLCTL_IFG[RDBRST] Bits */
\r
4587 #define FLCTL_IFG_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */
\r
4588 #define FLCTL_IFG_RDBRST ((uint32_t)0x00000001)
\r
4589 /* FLCTL_IFG[AVPRE] Bits */
\r
4590 #define FLCTL_IFG_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */
\r
4591 #define FLCTL_IFG_AVPRE ((uint32_t)0x00000002)
\r
4592 /* FLCTL_IFG[AVPST] Bits */
\r
4593 #define FLCTL_IFG_AVPST_OFS ( 2) /**< AVPST Bit Offset */
\r
4594 #define FLCTL_IFG_AVPST ((uint32_t)0x00000004)
\r
4595 /* FLCTL_IFG[PRG] Bits */
\r
4596 #define FLCTL_IFG_PRG_OFS ( 3) /**< PRG Bit Offset */
\r
4597 #define FLCTL_IFG_PRG ((uint32_t)0x00000008)
\r
4598 /* FLCTL_IFG[PRGB] Bits */
\r
4599 #define FLCTL_IFG_PRGB_OFS ( 4) /**< PRGB Bit Offset */
\r
4600 #define FLCTL_IFG_PRGB ((uint32_t)0x00000010)
\r
4601 /* FLCTL_IFG[ERASE] Bits */
\r
4602 #define FLCTL_IFG_ERASE_OFS ( 5) /**< ERASE Bit Offset */
\r
4603 #define FLCTL_IFG_ERASE ((uint32_t)0x00000020)
\r
4604 /* FLCTL_IFG[BMRK] Bits */
\r
4605 #define FLCTL_IFG_BMRK_OFS ( 8) /**< BMRK Bit Offset */
\r
4606 #define FLCTL_IFG_BMRK ((uint32_t)0x00000100)
\r
4607 /* FLCTL_IFG[PRG_ERR] Bits */
\r
4608 #define FLCTL_IFG_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */
\r
4609 #define FLCTL_IFG_PRG_ERR ((uint32_t)0x00000200)
\r
4610 /* FLCTL_IE[RDBRST] Bits */
\r
4611 #define FLCTL_IE_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */
\r
4612 #define FLCTL_IE_RDBRST ((uint32_t)0x00000001)
\r
4613 /* FLCTL_IE[AVPRE] Bits */
\r
4614 #define FLCTL_IE_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */
\r
4615 #define FLCTL_IE_AVPRE ((uint32_t)0x00000002)
\r
4616 /* FLCTL_IE[AVPST] Bits */
\r
4617 #define FLCTL_IE_AVPST_OFS ( 2) /**< AVPST Bit Offset */
\r
4618 #define FLCTL_IE_AVPST ((uint32_t)0x00000004)
\r
4619 /* FLCTL_IE[PRG] Bits */
\r
4620 #define FLCTL_IE_PRG_OFS ( 3) /**< PRG Bit Offset */
\r
4621 #define FLCTL_IE_PRG ((uint32_t)0x00000008)
\r
4622 /* FLCTL_IE[PRGB] Bits */
\r
4623 #define FLCTL_IE_PRGB_OFS ( 4) /**< PRGB Bit Offset */
\r
4624 #define FLCTL_IE_PRGB ((uint32_t)0x00000010)
\r
4625 /* FLCTL_IE[ERASE] Bits */
\r
4626 #define FLCTL_IE_ERASE_OFS ( 5) /**< ERASE Bit Offset */
\r
4627 #define FLCTL_IE_ERASE ((uint32_t)0x00000020)
\r
4628 /* FLCTL_IE[BMRK] Bits */
\r
4629 #define FLCTL_IE_BMRK_OFS ( 8) /**< BMRK Bit Offset */
\r
4630 #define FLCTL_IE_BMRK ((uint32_t)0x00000100)
\r
4631 /* FLCTL_IE[PRG_ERR] Bits */
\r
4632 #define FLCTL_IE_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */
\r
4633 #define FLCTL_IE_PRG_ERR ((uint32_t)0x00000200)
\r
4634 /* FLCTL_CLRIFG[RDBRST] Bits */
\r
4635 #define FLCTL_CLRIFG_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */
\r
4636 #define FLCTL_CLRIFG_RDBRST ((uint32_t)0x00000001)
\r
4637 /* FLCTL_CLRIFG[AVPRE] Bits */
\r
4638 #define FLCTL_CLRIFG_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */
\r
4639 #define FLCTL_CLRIFG_AVPRE ((uint32_t)0x00000002)
\r
4640 /* FLCTL_CLRIFG[AVPST] Bits */
\r
4641 #define FLCTL_CLRIFG_AVPST_OFS ( 2) /**< AVPST Bit Offset */
\r
4642 #define FLCTL_CLRIFG_AVPST ((uint32_t)0x00000004)
\r
4643 /* FLCTL_CLRIFG[PRG] Bits */
\r
4644 #define FLCTL_CLRIFG_PRG_OFS ( 3) /**< PRG Bit Offset */
\r
4645 #define FLCTL_CLRIFG_PRG ((uint32_t)0x00000008)
\r
4646 /* FLCTL_CLRIFG[PRGB] Bits */
\r
4647 #define FLCTL_CLRIFG_PRGB_OFS ( 4) /**< PRGB Bit Offset */
\r
4648 #define FLCTL_CLRIFG_PRGB ((uint32_t)0x00000010)
\r
4649 /* FLCTL_CLRIFG[ERASE] Bits */
\r
4650 #define FLCTL_CLRIFG_ERASE_OFS ( 5) /**< ERASE Bit Offset */
\r
4651 #define FLCTL_CLRIFG_ERASE ((uint32_t)0x00000020)
\r
4652 /* FLCTL_CLRIFG[BMRK] Bits */
\r
4653 #define FLCTL_CLRIFG_BMRK_OFS ( 8) /**< BMRK Bit Offset */
\r
4654 #define FLCTL_CLRIFG_BMRK ((uint32_t)0x00000100)
\r
4655 /* FLCTL_CLRIFG[PRG_ERR] Bits */
\r
4656 #define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */
\r
4657 #define FLCTL_CLRIFG_PRG_ERR ((uint32_t)0x00000200)
\r
4658 /* FLCTL_SETIFG[RDBRST] Bits */
\r
4659 #define FLCTL_SETIFG_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */
\r
4660 #define FLCTL_SETIFG_RDBRST ((uint32_t)0x00000001)
\r
4661 /* FLCTL_SETIFG[AVPRE] Bits */
\r
4662 #define FLCTL_SETIFG_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */
\r
4663 #define FLCTL_SETIFG_AVPRE ((uint32_t)0x00000002)
\r
4664 /* FLCTL_SETIFG[AVPST] Bits */
\r
4665 #define FLCTL_SETIFG_AVPST_OFS ( 2) /**< AVPST Bit Offset */
\r
4666 #define FLCTL_SETIFG_AVPST ((uint32_t)0x00000004)
\r
4667 /* FLCTL_SETIFG[PRG] Bits */
\r
4668 #define FLCTL_SETIFG_PRG_OFS ( 3) /**< PRG Bit Offset */
\r
4669 #define FLCTL_SETIFG_PRG ((uint32_t)0x00000008)
\r
4670 /* FLCTL_SETIFG[PRGB] Bits */
\r
4671 #define FLCTL_SETIFG_PRGB_OFS ( 4) /**< PRGB Bit Offset */
\r
4672 #define FLCTL_SETIFG_PRGB ((uint32_t)0x00000010)
\r
4673 /* FLCTL_SETIFG[ERASE] Bits */
\r
4674 #define FLCTL_SETIFG_ERASE_OFS ( 5) /**< ERASE Bit Offset */
\r
4675 #define FLCTL_SETIFG_ERASE ((uint32_t)0x00000020)
\r
4676 /* FLCTL_SETIFG[BMRK] Bits */
\r
4677 #define FLCTL_SETIFG_BMRK_OFS ( 8) /**< BMRK Bit Offset */
\r
4678 #define FLCTL_SETIFG_BMRK ((uint32_t)0x00000100)
\r
4679 /* FLCTL_SETIFG[PRG_ERR] Bits */
\r
4680 #define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */
\r
4681 #define FLCTL_SETIFG_PRG_ERR ((uint32_t)0x00000200)
\r
4682 /* FLCTL_READ_TIMCTL[SETUP] Bits */
\r
4683 #define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
\r
4684 #define FLCTL_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
\r
4685 /* FLCTL_READ_TIMCTL[IREF_BOOST1] Bits */
\r
4686 #define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /**< IREF_BOOST1 Bit Offset */
\r
4687 #define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /**< IREF_BOOST1 Bit Mask */
\r
4688 /* FLCTL_READ_TIMCTL[SETUP_LONG] Bits */
\r
4689 #define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /**< SETUP_LONG Bit Offset */
\r
4690 #define FLCTL_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /**< SETUP_LONG Bit Mask */
\r
4691 /* FLCTL_READMARGIN_TIMCTL[SETUP] Bits */
\r
4692 #define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
\r
4693 #define FLCTL_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
\r
4694 /* FLCTL_PRGVER_TIMCTL[SETUP] Bits */
\r
4695 #define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
\r
4696 #define FLCTL_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
\r
4697 /* FLCTL_PRGVER_TIMCTL[ACTIVE] Bits */
\r
4698 #define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */
\r
4699 #define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /**< ACTIVE Bit Mask */
\r
4700 /* FLCTL_PRGVER_TIMCTL[HOLD] Bits */
\r
4701 #define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /**< HOLD Bit Offset */
\r
4702 #define FLCTL_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /**< HOLD Bit Mask */
\r
4703 /* FLCTL_ERSVER_TIMCTL[SETUP] Bits */
\r
4704 #define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
\r
4705 #define FLCTL_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
\r
4706 /* FLCTL_LKGVER_TIMCTL[SETUP] Bits */
\r
4707 #define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
\r
4708 #define FLCTL_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
\r
4709 /* FLCTL_PROGRAM_TIMCTL[SETUP] Bits */
\r
4710 #define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
\r
4711 #define FLCTL_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
\r
4712 /* FLCTL_PROGRAM_TIMCTL[ACTIVE] Bits */
\r
4713 #define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */
\r
4714 #define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /**< ACTIVE Bit Mask */
\r
4715 /* FLCTL_PROGRAM_TIMCTL[HOLD] Bits */
\r
4716 #define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /**< HOLD Bit Offset */
\r
4717 #define FLCTL_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /**< HOLD Bit Mask */
\r
4718 /* FLCTL_ERASE_TIMCTL[SETUP] Bits */
\r
4719 #define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
\r
4720 #define FLCTL_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
\r
4721 /* FLCTL_ERASE_TIMCTL[ACTIVE] Bits */
\r
4722 #define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */
\r
4723 #define FLCTL_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /**< ACTIVE Bit Mask */
\r
4724 /* FLCTL_ERASE_TIMCTL[HOLD] Bits */
\r
4725 #define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /**< HOLD Bit Offset */
\r
4726 #define FLCTL_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /**< HOLD Bit Mask */
\r
4727 /* FLCTL_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */
\r
4728 #define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /**< BOOST_ACTIVE Bit Offset */
\r
4729 #define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /**< BOOST_ACTIVE Bit Mask */
\r
4730 /* FLCTL_MASSERASE_TIMCTL[BOOST_HOLD] Bits */
\r
4731 #define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /**< BOOST_HOLD Bit Offset */
\r
4732 #define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /**< BOOST_HOLD Bit Mask */
\r
4733 /* FLCTL_BURSTPRG_TIMCTL[ACTIVE] Bits */
\r
4734 #define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */
\r
4735 #define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /**< ACTIVE Bit Mask */
\r
4738 /******************************************************************************
\r
4740 ******************************************************************************/
\r
4743 /******************************************************************************
\r
4745 ******************************************************************************/
\r
4748 /******************************************************************************
\r
4750 ******************************************************************************/
\r
4753 /******************************************************************************
\r
4755 ******************************************************************************/
\r
4757 /* Pre-defined bitfield values */
\r
4759 /* MPU_RASR_SIZE Bitfield Bits */
\r
4760 #define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /* 32B */
\r
4761 #define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /* 64B */
\r
4762 #define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /* 128B */
\r
4763 #define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /* 256B */
\r
4764 #define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /* 512B */
\r
4765 #define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /* 1KB */
\r
4766 #define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /* 2KB */
\r
4767 #define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /* 4KB */
\r
4768 #define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /* 8KB */
\r
4769 #define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /* 16KB */
\r
4770 #define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /* 32KB */
\r
4771 #define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /* 64KB */
\r
4772 #define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /* 128KB */
\r
4773 #define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /* 256KB */
\r
4774 #define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /* 512KB */
\r
4775 #define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /* 1MB */
\r
4776 #define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /* 2MB */
\r
4777 #define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /* 4MB */
\r
4778 #define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /* 8MB */
\r
4779 #define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /* 16MB */
\r
4780 #define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /* 32MB */
\r
4781 #define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /* 64MB */
\r
4782 #define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /* 128MB */
\r
4783 #define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /* 256MB */
\r
4784 #define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /* 512MB */
\r
4785 #define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /* 1GB */
\r
4786 #define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /* 2GB */
\r
4787 #define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /* 4GB */
\r
4789 /* MPU_RASR_AP Bitfield Bits */
\r
4790 #define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /* Privileged permissions: No access. User permissions: No access. */
\r
4791 #define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /* Privileged permissions: Read-write. User permissions: No access. */
\r
4792 #define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /* Privileged permissions: Read-write. User permissions: Read-only. */
\r
4793 #define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /* Privileged permissions: Read-write. User permissions: Read-write. */
\r
4794 #define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /* Privileged permissions: Read-only. User permissions: No access. */
\r
4795 #define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /* Privileged permissions: Read-only. User permissions: Read-only. */
\r
4797 /* MPU_RASR_XN Bitfield Bits */
\r
4798 #define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /* Instruction access enabled */
\r
4799 #define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /* Instruction access disabled */
\r
4802 /******************************************************************************
\r
4804 ******************************************************************************/
\r
4807 /******************************************************************************
\r
4809 ******************************************************************************/
\r
4810 /* PCM_CTL0[AMR] Bits */
\r
4811 #define PCM_CTL0_AMR_OFS ( 0) /**< AMR Bit Offset */
\r
4812 #define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /**< AMR Bit Mask */
\r
4813 #define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /**< AMR Bit 0 */
\r
4814 #define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /**< AMR Bit 1 */
\r
4815 #define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /**< AMR Bit 2 */
\r
4816 #define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /**< AMR Bit 3 */
\r
4817 #define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /**< LDO based Active Mode at Core voltage setting 0. */
\r
4818 #define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /**< LDO based Active Mode at Core voltage setting 1. */
\r
4819 #define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /**< DC-DC based Active Mode at Core voltage setting 0. */
\r
4820 #define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /**< DC-DC based Active Mode at Core voltage setting 1. */
\r
4821 #define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /**< Low-Frequency Active Mode at Core voltage setting 0. */
\r
4822 #define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /**< Low-Frequency Active Mode at Core voltage setting 1. */
\r
4823 #define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /**< LDO based Active Mode at Core voltage setting 0. */
\r
4824 #define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /**< LDO based Active Mode at Core voltage setting 1. */
\r
4825 #define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /**< DC-DC based Active Mode at Core voltage setting 0. */
\r
4826 #define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /**< DC-DC based Active Mode at Core voltage setting 1. */
\r
4827 #define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /**< Low-Frequency Active Mode at Core voltage setting 0. */
\r
4828 #define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /**< Low-Frequency Active Mode at Core voltage setting 1. */
\r
4829 /* PCM_CTL0[LPMR] Bits */
\r
4830 #define PCM_CTL0_LPMR_OFS ( 4) /**< LPMR Bit Offset */
\r
4831 #define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /**< LPMR Bit Mask */
\r
4832 #define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /**< LPMR Bit 0 */
\r
4833 #define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /**< LPMR Bit 1 */
\r
4834 #define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /**< LPMR Bit 2 */
\r
4835 #define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /**< LPMR Bit 3 */
\r
4836 #define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /**< LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */
\r
4837 #define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /**< LPM3.5. Core voltage setting 0. */
\r
4838 #define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /**< LPM4.5 */
\r
4839 #define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /**< LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */
\r
4840 #define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /**< LPM3.5. Core voltage setting 0. */
\r
4841 #define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /**< LPM4.5 */
\r
4842 /* PCM_CTL0[CPM] Bits */
\r
4843 #define PCM_CTL0_CPM_OFS ( 8) /**< CPM Bit Offset */
\r
4844 #define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /**< CPM Bit Mask */
\r
4845 #define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /**< CPM Bit 0 */
\r
4846 #define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /**< CPM Bit 1 */
\r
4847 #define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /**< CPM Bit 2 */
\r
4848 #define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /**< CPM Bit 3 */
\r
4849 #define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /**< CPM Bit 4 */
\r
4850 #define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /**< CPM Bit 5 */
\r
4851 #define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /**< LDO based Active Mode at Core voltage setting 0. */
\r
4852 #define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /**< LDO based Active Mode at Core voltage setting 1. */
\r
4853 #define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /**< DC-DC based Active Mode at Core voltage setting 0. */
\r
4854 #define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /**< DC-DC based Active Mode at Core voltage setting 1. */
\r
4855 #define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /**< Low-Frequency Active Mode at Core voltage setting 0. */
\r
4856 #define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /**< Low-Frequency Active Mode at Core voltage setting 1. */
\r
4857 #define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /**< LDO based LPM0 at Core voltage setting 0. */
\r
4858 #define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /**< LDO based LPM0 at Core voltage setting 1. */
\r
4859 #define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /**< DC-DC based LPM0 at Core voltage setting 0. */
\r
4860 #define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /**< DC-DC based LPM0 at Core voltage setting 1. */
\r
4861 #define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /**< Low-Frequency LPM0 at Core voltage setting 0. */
\r
4862 #define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /**< Low-Frequency LPM0 at Core voltage setting 1. */
\r
4863 #define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /**< LPM3 */
\r
4864 #define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /**< LDO based Active Mode at Core voltage setting 0. */
\r
4865 #define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /**< LDO based Active Mode at Core voltage setting 1. */
\r
4866 #define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /**< DC-DC based Active Mode at Core voltage setting 0. */
\r
4867 #define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /**< DC-DC based Active Mode at Core voltage setting 1. */
\r
4868 #define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /**< Low-Frequency Active Mode at Core voltage setting 0. */
\r
4869 #define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /**< Low-Frequency Active Mode at Core voltage setting 1. */
\r
4870 #define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /**< LDO based LPM0 at Core voltage setting 0. */
\r
4871 #define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /**< LDO based LPM0 at Core voltage setting 1. */
\r
4872 #define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /**< DC-DC based LPM0 at Core voltage setting 0. */
\r
4873 #define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /**< DC-DC based LPM0 at Core voltage setting 1. */
\r
4874 #define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /**< Low-Frequency LPM0 at Core voltage setting 0. */
\r
4875 #define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /**< Low-Frequency LPM0 at Core voltage setting 1. */
\r
4876 #define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /**< LPM3 */
\r
4877 /* PCM_CTL0[KEY] Bits */
\r
4878 #define PCM_CTL0_KEY_OFS (16) /**< PCMKEY Bit Offset */
\r
4879 #define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /**< PCMKEY Bit Mask */
\r
4880 /* PCM_CTL1[LOCKLPM5] Bits */
\r
4881 #define PCM_CTL1_LOCKLPM5_OFS ( 0) /**< LOCKLPM5 Bit Offset */
\r
4882 #define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /**< Lock LPM5 */
\r
4883 /* PCM_CTL1[LOCKBKUP] Bits */
\r
4884 #define PCM_CTL1_LOCKBKUP_OFS ( 1) /**< LOCKBKUP Bit Offset */
\r
4885 #define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /**< Lock Backup */
\r
4886 /* PCM_CTL1[FORCE_LPM_ENTRY] Bits */
\r
4887 #define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /**< FORCE_LPM_ENTRY Bit Offset */
\r
4888 #define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /**< Force LPM entry */
\r
4889 /* PCM_CTL1[PMR_BUSY] Bits */
\r
4890 #define PCM_CTL1_PMR_BUSY_OFS ( 8) /**< PMR_BUSY Bit Offset */
\r
4891 #define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /**< Power mode request busy flag */
\r
4892 /* PCM_CTL1[KEY] Bits */
\r
4893 #define PCM_CTL1_KEY_OFS (16) /**< PCMKEY Bit Offset */
\r
4894 #define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /**< PCMKEY Bit Mask */
\r
4895 /* PCM_IE[LPM_INVALID_TR_IE] Bits */
\r
4896 #define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /**< LPM_INVALID_TR_IE Bit Offset */
\r
4897 #define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /**< LPM invalid transition interrupt enable */
\r
4898 /* PCM_IE[LPM_INVALID_CLK_IE] Bits */
\r
4899 #define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /**< LPM_INVALID_CLK_IE Bit Offset */
\r
4900 #define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /**< LPM invalid clock interrupt enable */
\r
4901 /* PCM_IE[AM_INVALID_TR_IE] Bits */
\r
4902 #define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /**< AM_INVALID_TR_IE Bit Offset */
\r
4903 #define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /**< Active mode invalid transition interrupt enable */
\r
4904 /* PCM_IE[DCDC_ERROR_IE] Bits */
\r
4905 #define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /**< DCDC_ERROR_IE Bit Offset */
\r
4906 #define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /**< DC-DC error interrupt enable */
\r
4907 /* PCM_IFG[LPM_INVALID_TR_IFG] Bits */
\r
4908 #define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /**< LPM_INVALID_TR_IFG Bit Offset */
\r
4909 #define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /**< LPM invalid transition flag */
\r
4910 /* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */
\r
4911 #define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /**< LPM_INVALID_CLK_IFG Bit Offset */
\r
4912 #define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /**< LPM invalid clock flag */
\r
4913 /* PCM_IFG[AM_INVALID_TR_IFG] Bits */
\r
4914 #define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /**< AM_INVALID_TR_IFG Bit Offset */
\r
4915 #define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /**< Active mode invalid transition flag */
\r
4916 /* PCM_IFG[DCDC_ERROR_IFG] Bits */
\r
4917 #define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /**< DCDC_ERROR_IFG Bit Offset */
\r
4918 #define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /**< DC-DC error flag */
\r
4919 /* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */
\r
4920 #define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /**< CLR_LPM_INVALID_TR_IFG Bit Offset */
\r
4921 #define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /**< Clear LPM invalid transition flag */
\r
4922 /* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */
\r
4923 #define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /**< CLR_LPM_INVALID_CLK_IFG Bit Offset */
\r
4924 #define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /**< Clear LPM invalid clock flag */
\r
4925 /* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */
\r
4926 #define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /**< CLR_AM_INVALID_TR_IFG Bit Offset */
\r
4927 #define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /**< Clear active mode invalid transition flag */
\r
4928 /* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */
\r
4929 #define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /**< CLR_DCDC_ERROR_IFG Bit Offset */
\r
4930 #define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /**< Clear DC-DC error flag */
\r
4932 /* Pre-defined bitfield values */
\r
4933 #define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /* PCM key value */
\r
4934 #define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /* PCM key value */
\r
4937 /******************************************************************************
\r
4939 ******************************************************************************/
\r
4940 /* PMAP_CTL[LOCKED] Bits */
\r
4941 #define PMAP_CTL_LOCKED_OFS ( 0) /**< PMAPLOCKED Bit Offset */
\r
4942 #define PMAP_CTL_LOCKED ((uint16_t)0x0001) /**< Port mapping lock bit */
\r
4943 /* PMAP_CTL[PRECFG] Bits */
\r
4944 #define PMAP_CTL_PRECFG_OFS ( 1) /**< PMAPRECFG Bit Offset */
\r
4945 #define PMAP_CTL_PRECFG ((uint16_t)0x0002) /**< Port mapping reconfiguration control bit */
\r
4947 /* Pre-defined bitfield values */
\r
4948 #define PMAP_NONE 0
\r
4949 #define PMAP_UCA0CLK 1
\r
4950 #define PMAP_UCA0RXD 2
\r
4951 #define PMAP_UCA0SOMI 2
\r
4952 #define PMAP_UCA0TXD 3
\r
4953 #define PMAP_UCA0SIMO 3
\r
4954 #define PMAP_UCB0CLK 4
\r
4955 #define PMAP_UCB0SDA 5
\r
4956 #define PMAP_UCB0SIMO 5
\r
4957 #define PMAP_UCB0SCL 6
\r
4958 #define PMAP_UCB0SOMI 6
\r
4959 #define PMAP_UCA1STE 7
\r
4960 #define PMAP_UCA1CLK 8
\r
4961 #define PMAP_UCA1RXD 9
\r
4962 #define PMAP_UCA1SOMI 9
\r
4963 #define PMAP_UCA1TXD 10
\r
4964 #define PMAP_UCA1SIMO 10
\r
4965 #define PMAP_UCA2STE 11
\r
4966 #define PMAP_UCA2CLK 12
\r
4967 #define PMAP_UCA2RXD 13
\r
4968 #define PMAP_UCA2SOMI 13
\r
4969 #define PMAP_UCA2TXD 14
\r
4970 #define PMAP_UCA2SIMO 14
\r
4971 #define PMAP_UCB2STE 15
\r
4972 #define PMAP_UCB2CLK 16
\r
4973 #define PMAP_UCB2SDA 17
\r
4974 #define PMAP_UCB2SIMO 17
\r
4975 #define PMAP_UCB2SCL 18
\r
4976 #define PMAP_UCB2SOMI 18
\r
4977 #define PMAP_TA0CCR0A 19
\r
4978 #define PMAP_TA0CCR1A 20
\r
4979 #define PMAP_TA0CCR2A 21
\r
4980 #define PMAP_TA0CCR3A 22
\r
4981 #define PMAP_TA0CCR4A 23
\r
4982 #define PMAP_TA1CCR1A 24
\r
4983 #define PMAP_TA1CCR2A 25
\r
4984 #define PMAP_TA1CCR3A 26
\r
4985 #define PMAP_TA1CCR4A 27
\r
4986 #define PMAP_TA0CLK 28
\r
4987 #define PMAP_CE0OUT 28
\r
4988 #define PMAP_TA1CLK 29
\r
4989 #define PMAP_CE1OUT 29
\r
4990 #define PMAP_DMAE0 30
\r
4991 #define PMAP_SMCLK 30
\r
4992 #define PMAP_ANALOG 31
\r
4994 #define PMAP_KEYID_VAL ((uint16_t)0x2D52) /**< Port Mapping Key */
\r
4997 /******************************************************************************
\r
4999 ******************************************************************************/
\r
5000 /* PSS_KEY[KEY] Bits */
\r
5001 #define PSS_KEY_KEY_OFS ( 0) /**< PSSKEY Bit Offset */
\r
5002 #define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /**< PSSKEY Bit Mask */
\r
5003 /* PSS_CTL0[SVSMHOFF] Bits */
\r
5004 #define PSS_CTL0_SVSMHOFF_OFS ( 0) /**< SVSMHOFF Bit Offset */
\r
5005 #define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /**< SVSM high-side off */
\r
5006 /* PSS_CTL0[SVSMHLP] Bits */
\r
5007 #define PSS_CTL0_SVSMHLP_OFS ( 1) /**< SVSMHLP Bit Offset */
\r
5008 #define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /**< SVSM high-side low power normal performance mode */
\r
5009 /* PSS_CTL0[SVSMHS] Bits */
\r
5010 #define PSS_CTL0_SVSMHS_OFS ( 2) /**< SVSMHS Bit Offset */
\r
5011 #define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /**< Supply supervisor or monitor selection for the high-side */
\r
5012 /* PSS_CTL0[SVSMHTH] Bits */
\r
5013 #define PSS_CTL0_SVSMHTH_OFS ( 3) /**< SVSMHTH Bit Offset */
\r
5014 #define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /**< SVSMHTH Bit Mask */
\r
5015 /* PSS_CTL0[SVMHOE] Bits */
\r
5016 #define PSS_CTL0_SVMHOE_OFS ( 6) /**< SVMHOE Bit Offset */
\r
5017 #define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /**< SVSM high-side output enable */
\r
5018 /* PSS_CTL0[SVMHOUTPOLAL] Bits */
\r
5019 #define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /**< SVMHOUTPOLAL Bit Offset */
\r
5020 #define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /**< SVMHOUT pin polarity active low */
\r
5021 /* PSS_CTL0[DCDC_FORCE] Bits */
\r
5022 #define PSS_CTL0_DCDC_FORCE_OFS (10) /**< DCDC_FORCE Bit Offset */
\r
5023 #define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /**< Force DC-DC regulator operation */
\r
5024 /* PSS_CTL0[VCORETRAN] Bits */
\r
5025 #define PSS_CTL0_VCORETRAN_OFS (12) /**< VCORETRAN Bit Offset */
\r
5026 #define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /**< VCORETRAN Bit Mask */
\r
5027 #define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /**< VCORETRAN Bit 0 */
\r
5028 #define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /**< VCORETRAN Bit 1 */
\r
5029 #define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /**< 32 ?s / 100 mV */
\r
5030 #define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /**< 64 ?s / 100 mV */
\r
5031 #define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /**< 128 ?s / 100 mV (default) */
\r
5032 #define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /**< 256 ?s / 100 mV */
\r
5033 #define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /**< 32 ?s / 100 mV */
\r
5034 #define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /**< 64 ?s / 100 mV */
\r
5035 #define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /**< 128 ?s / 100 mV (default) */
\r
5036 #define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /**< 256 ?s / 100 mV */
\r
5037 /* PSS_IE[SVSMHIE] Bits */
\r
5038 #define PSS_IE_SVSMHIE_OFS ( 1) /**< SVSMHIE Bit Offset */
\r
5039 #define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /**< High-side SVSM interrupt enable */
\r
5040 /* PSS_IFG[SVSMHIFG] Bits */
\r
5041 #define PSS_IFG_SVSMHIFG_OFS ( 1) /**< SVSMHIFG Bit Offset */
\r
5042 #define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /**< High-side SVSM interrupt flag */
\r
5043 /* PSS_CLRIFG[CLRSVSMHIFG] Bits */
\r
5044 #define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /**< CLRSVSMHIFG Bit Offset */
\r
5045 #define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /**< SVSMH clear interrupt flag */
\r
5047 /* Pre-defined bitfield values */
\r
5048 #define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /* PSS control key value */
\r
5051 /******************************************************************************
\r
5053 ******************************************************************************/
\r
5054 /* REF_A_CTL0[ON] Bits */
\r
5055 #define REF_A_CTL0_ON_OFS ( 0) /**< REFON Bit Offset */
\r
5056 #define REF_A_CTL0_ON ((uint16_t)0x0001) /**< Reference enable */
\r
5057 /* REF_A_CTL0[OUT] Bits */
\r
5058 #define REF_A_CTL0_OUT_OFS ( 1) /**< REFOUT Bit Offset */
\r
5059 #define REF_A_CTL0_OUT ((uint16_t)0x0002) /**< Reference output buffer */
\r
5060 /* REF_A_CTL0[TCOFF] Bits */
\r
5061 #define REF_A_CTL0_TCOFF_OFS ( 3) /**< REFTCOFF Bit Offset */
\r
5062 #define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /**< Temperature sensor disabled */
\r
5063 /* REF_A_CTL0[VSEL] Bits */
\r
5064 #define REF_A_CTL0_VSEL_OFS ( 4) /**< REFVSEL Bit Offset */
\r
5065 #define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /**< REFVSEL Bit Mask */
\r
5066 #define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /**< VSEL Bit 0 */
\r
5067 #define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /**< VSEL Bit 1 */
\r
5068 #define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /**< 1.2 V available when reference requested or REFON = 1 */
\r
5069 #define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /**< 1.45 V available when reference requested or REFON = 1 */
\r
5070 #define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /**< 2.5 V available when reference requested or REFON = 1 */
\r
5071 /* REF_A_CTL0[GENOT] Bits */
\r
5072 #define REF_A_CTL0_GENOT_OFS ( 6) /**< REFGENOT Bit Offset */
\r
5073 #define REF_A_CTL0_GENOT ((uint16_t)0x0040) /**< Reference generator one-time trigger */
\r
5074 /* REF_A_CTL0[BGOT] Bits */
\r
5075 #define REF_A_CTL0_BGOT_OFS ( 7) /**< REFBGOT Bit Offset */
\r
5076 #define REF_A_CTL0_BGOT ((uint16_t)0x0080) /**< Bandgap and bandgap buffer one-time trigger */
\r
5077 /* REF_A_CTL0[GENACT] Bits */
\r
5078 #define REF_A_CTL0_GENACT_OFS ( 8) /**< REFGENACT Bit Offset */
\r
5079 #define REF_A_CTL0_GENACT ((uint16_t)0x0100) /**< Reference generator active */
\r
5080 /* REF_A_CTL0[BGACT] Bits */
\r
5081 #define REF_A_CTL0_BGACT_OFS ( 9) /**< REFBGACT Bit Offset */
\r
5082 #define REF_A_CTL0_BGACT ((uint16_t)0x0200) /**< Reference bandgap active */
\r
5083 /* REF_A_CTL0[GENBUSY] Bits */
\r
5084 #define REF_A_CTL0_GENBUSY_OFS (10) /**< REFGENBUSY Bit Offset */
\r
5085 #define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /**< Reference generator busy */
\r
5086 /* REF_A_CTL0[BGMODE] Bits */
\r
5087 #define REF_A_CTL0_BGMODE_OFS (11) /**< BGMODE Bit Offset */
\r
5088 #define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /**< Bandgap mode */
\r
5089 /* REF_A_CTL0[GENRDY] Bits */
\r
5090 #define REF_A_CTL0_GENRDY_OFS (12) /**< REFGENRDY Bit Offset */
\r
5091 #define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /**< Variable reference voltage ready status */
\r
5092 /* REF_A_CTL0[BGRDY] Bits */
\r
5093 #define REF_A_CTL0_BGRDY_OFS (13) /**< REFBGRDY Bit Offset */
\r
5094 #define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /**< Buffered bandgap voltage ready status */
\r
5097 /******************************************************************************
\r
5099 ******************************************************************************/
\r
5100 /* RSTCTL_RESET_REQ[SOFT_REQ] Bits */
\r
5101 #define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /**< SOFT_REQ Bit Offset */
\r
5102 #define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /**< Soft Reset request */
\r
5103 /* RSTCTL_RESET_REQ[HARD_REQ] Bits */
\r
5104 #define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /**< HARD_REQ Bit Offset */
\r
5105 #define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /**< Hard Reset request */
\r
5106 /* RSTCTL_RESET_REQ[RSTKEY] Bits */
\r
5107 #define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /**< RSTKEY Bit Offset */
\r
5108 #define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /**< RSTKEY Bit Mask */
\r
5109 /* RSTCTL_HARDRESET_STAT[SRC0] Bits */
\r
5110 #define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /**< SRC0 Bit Offset */
\r
5111 #define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /**< Indicates that SRC0 was the source of the Hard Reset */
\r
5112 /* RSTCTL_HARDRESET_STAT[SRC1] Bits */
\r
5113 #define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /**< SRC1 Bit Offset */
\r
5114 #define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /**< Indicates that SRC1 was the source of the Hard Reset */
\r
5115 /* RSTCTL_HARDRESET_STAT[SRC2] Bits */
\r
5116 #define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /**< SRC2 Bit Offset */
\r
5117 #define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /**< Indicates that SRC2 was the source of the Hard Reset */
\r
5118 /* RSTCTL_HARDRESET_STAT[SRC3] Bits */
\r
5119 #define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /**< SRC3 Bit Offset */
\r
5120 #define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /**< Indicates that SRC3 was the source of the Hard Reset */
\r
5121 /* RSTCTL_HARDRESET_STAT[SRC4] Bits */
\r
5122 #define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /**< SRC4 Bit Offset */
\r
5123 #define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /**< Indicates that SRC4 was the source of the Hard Reset */
\r
5124 /* RSTCTL_HARDRESET_STAT[SRC5] Bits */
\r
5125 #define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /**< SRC5 Bit Offset */
\r
5126 #define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /**< Indicates that SRC5 was the source of the Hard Reset */
\r
5127 /* RSTCTL_HARDRESET_STAT[SRC6] Bits */
\r
5128 #define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /**< SRC6 Bit Offset */
\r
5129 #define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /**< Indicates that SRC6 was the source of the Hard Reset */
\r
5130 /* RSTCTL_HARDRESET_STAT[SRC7] Bits */
\r
5131 #define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /**< SRC7 Bit Offset */
\r
5132 #define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /**< Indicates that SRC7 was the source of the Hard Reset */
\r
5133 /* RSTCTL_HARDRESET_STAT[SRC8] Bits */
\r
5134 #define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /**< SRC8 Bit Offset */
\r
5135 #define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /**< Indicates that SRC8 was the source of the Hard Reset */
\r
5136 /* RSTCTL_HARDRESET_STAT[SRC9] Bits */
\r
5137 #define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /**< SRC9 Bit Offset */
\r
5138 #define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /**< Indicates that SRC9 was the source of the Hard Reset */
\r
5139 /* RSTCTL_HARDRESET_STAT[SRC10] Bits */
\r
5140 #define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /**< SRC10 Bit Offset */
\r
5141 #define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /**< Indicates that SRC10 was the source of the Hard Reset */
\r
5142 /* RSTCTL_HARDRESET_STAT[SRC11] Bits */
\r
5143 #define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /**< SRC11 Bit Offset */
\r
5144 #define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /**< Indicates that SRC11 was the source of the Hard Reset */
\r
5145 /* RSTCTL_HARDRESET_STAT[SRC12] Bits */
\r
5146 #define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /**< SRC12 Bit Offset */
\r
5147 #define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /**< Indicates that SRC12 was the source of the Hard Reset */
\r
5148 /* RSTCTL_HARDRESET_STAT[SRC13] Bits */
\r
5149 #define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /**< SRC13 Bit Offset */
\r
5150 #define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /**< Indicates that SRC13 was the source of the Hard Reset */
\r
5151 /* RSTCTL_HARDRESET_STAT[SRC14] Bits */
\r
5152 #define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /**< SRC14 Bit Offset */
\r
5153 #define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /**< Indicates that SRC14 was the source of the Hard Reset */
\r
5154 /* RSTCTL_HARDRESET_STAT[SRC15] Bits */
\r
5155 #define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /**< SRC15 Bit Offset */
\r
5156 #define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /**< Indicates that SRC15 was the source of the Hard Reset */
\r
5157 /* RSTCTL_HARDRESET_CLR[SRC0] Bits */
\r
5158 #define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /**< SRC0 Bit Offset */
\r
5159 #define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5160 /* RSTCTL_HARDRESET_CLR[SRC1] Bits */
\r
5161 #define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /**< SRC1 Bit Offset */
\r
5162 #define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5163 /* RSTCTL_HARDRESET_CLR[SRC2] Bits */
\r
5164 #define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /**< SRC2 Bit Offset */
\r
5165 #define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5166 /* RSTCTL_HARDRESET_CLR[SRC3] Bits */
\r
5167 #define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /**< SRC3 Bit Offset */
\r
5168 #define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5169 /* RSTCTL_HARDRESET_CLR[SRC4] Bits */
\r
5170 #define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /**< SRC4 Bit Offset */
\r
5171 #define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5172 /* RSTCTL_HARDRESET_CLR[SRC5] Bits */
\r
5173 #define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /**< SRC5 Bit Offset */
\r
5174 #define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5175 /* RSTCTL_HARDRESET_CLR[SRC6] Bits */
\r
5176 #define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /**< SRC6 Bit Offset */
\r
5177 #define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5178 /* RSTCTL_HARDRESET_CLR[SRC7] Bits */
\r
5179 #define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /**< SRC7 Bit Offset */
\r
5180 #define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5181 /* RSTCTL_HARDRESET_CLR[SRC8] Bits */
\r
5182 #define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /**< SRC8 Bit Offset */
\r
5183 #define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5184 /* RSTCTL_HARDRESET_CLR[SRC9] Bits */
\r
5185 #define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /**< SRC9 Bit Offset */
\r
5186 #define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5187 /* RSTCTL_HARDRESET_CLR[SRC10] Bits */
\r
5188 #define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /**< SRC10 Bit Offset */
\r
5189 #define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5190 /* RSTCTL_HARDRESET_CLR[SRC11] Bits */
\r
5191 #define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /**< SRC11 Bit Offset */
\r
5192 #define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5193 /* RSTCTL_HARDRESET_CLR[SRC12] Bits */
\r
5194 #define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /**< SRC12 Bit Offset */
\r
5195 #define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5196 /* RSTCTL_HARDRESET_CLR[SRC13] Bits */
\r
5197 #define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /**< SRC13 Bit Offset */
\r
5198 #define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5199 /* RSTCTL_HARDRESET_CLR[SRC14] Bits */
\r
5200 #define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /**< SRC14 Bit Offset */
\r
5201 #define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
5202 /* RSTCTL_HARDRESET_CLR[SRC15] Bits */
\r
5203 #define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /**< SRC15 Bit Offset */
\r
5204 #define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /**< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */
\r
5205 /* RSTCTL_HARDRESET_SET[SRC0] Bits */
\r
5206 #define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /**< SRC0 Bit Offset */
\r
5207 #define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5208 /* a Hard Reset) */
\r
5209 /* RSTCTL_HARDRESET_SET[SRC1] Bits */
\r
5210 #define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /**< SRC1 Bit Offset */
\r
5211 #define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5212 /* a Hard Reset) */
\r
5213 /* RSTCTL_HARDRESET_SET[SRC2] Bits */
\r
5214 #define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /**< SRC2 Bit Offset */
\r
5215 #define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5216 /* a Hard Reset) */
\r
5217 /* RSTCTL_HARDRESET_SET[SRC3] Bits */
\r
5218 #define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /**< SRC3 Bit Offset */
\r
5219 #define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5220 /* a Hard Reset) */
\r
5221 /* RSTCTL_HARDRESET_SET[SRC4] Bits */
\r
5222 #define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /**< SRC4 Bit Offset */
\r
5223 #define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5224 /* a Hard Reset) */
\r
5225 /* RSTCTL_HARDRESET_SET[SRC5] Bits */
\r
5226 #define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /**< SRC5 Bit Offset */
\r
5227 #define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5228 /* a Hard Reset) */
\r
5229 /* RSTCTL_HARDRESET_SET[SRC6] Bits */
\r
5230 #define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /**< SRC6 Bit Offset */
\r
5231 #define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5232 /* a Hard Reset) */
\r
5233 /* RSTCTL_HARDRESET_SET[SRC7] Bits */
\r
5234 #define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /**< SRC7 Bit Offset */
\r
5235 #define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5236 /* a Hard Reset) */
\r
5237 /* RSTCTL_HARDRESET_SET[SRC8] Bits */
\r
5238 #define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /**< SRC8 Bit Offset */
\r
5239 #define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5240 /* a Hard Reset) */
\r
5241 /* RSTCTL_HARDRESET_SET[SRC9] Bits */
\r
5242 #define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /**< SRC9 Bit Offset */
\r
5243 #define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5244 /* a Hard Reset) */
\r
5245 /* RSTCTL_HARDRESET_SET[SRC10] Bits */
\r
5246 #define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /**< SRC10 Bit Offset */
\r
5247 #define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5248 /* a Hard Reset) */
\r
5249 /* RSTCTL_HARDRESET_SET[SRC11] Bits */
\r
5250 #define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /**< SRC11 Bit Offset */
\r
5251 #define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5252 /* a Hard Reset) */
\r
5253 /* RSTCTL_HARDRESET_SET[SRC12] Bits */
\r
5254 #define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /**< SRC12 Bit Offset */
\r
5255 #define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5256 /* a Hard Reset) */
\r
5257 /* RSTCTL_HARDRESET_SET[SRC13] Bits */
\r
5258 #define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /**< SRC13 Bit Offset */
\r
5259 #define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5260 /* a Hard Reset) */
\r
5261 /* RSTCTL_HARDRESET_SET[SRC14] Bits */
\r
5262 #define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /**< SRC14 Bit Offset */
\r
5263 #define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5264 /* a Hard Reset) */
\r
5265 /* RSTCTL_HARDRESET_SET[SRC15] Bits */
\r
5266 #define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /**< SRC15 Bit Offset */
\r
5267 #define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
\r
5268 /* a Hard Reset) */
\r
5269 /* RSTCTL_SOFTRESET_STAT[SRC0] Bits */
\r
5270 #define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /**< SRC0 Bit Offset */
\r
5271 #define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /**< If 1, indicates that SRC0 was the source of the Soft Reset */
\r
5272 /* RSTCTL_SOFTRESET_STAT[SRC1] Bits */
\r
5273 #define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /**< SRC1 Bit Offset */
\r
5274 #define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /**< If 1, indicates that SRC1 was the source of the Soft Reset */
\r
5275 /* RSTCTL_SOFTRESET_STAT[SRC2] Bits */
\r
5276 #define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /**< SRC2 Bit Offset */
\r
5277 #define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /**< If 1, indicates that SRC2 was the source of the Soft Reset */
\r
5278 /* RSTCTL_SOFTRESET_STAT[SRC3] Bits */
\r
5279 #define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /**< SRC3 Bit Offset */
\r
5280 #define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /**< If 1, indicates that SRC3 was the source of the Soft Reset */
\r
5281 /* RSTCTL_SOFTRESET_STAT[SRC4] Bits */
\r
5282 #define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /**< SRC4 Bit Offset */
\r
5283 #define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /**< If 1, indicates that SRC4 was the source of the Soft Reset */
\r
5284 /* RSTCTL_SOFTRESET_STAT[SRC5] Bits */
\r
5285 #define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /**< SRC5 Bit Offset */
\r
5286 #define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /**< If 1, indicates that SRC5 was the source of the Soft Reset */
\r
5287 /* RSTCTL_SOFTRESET_STAT[SRC6] Bits */
\r
5288 #define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /**< SRC6 Bit Offset */
\r
5289 #define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /**< If 1, indicates that SRC6 was the source of the Soft Reset */
\r
5290 /* RSTCTL_SOFTRESET_STAT[SRC7] Bits */
\r
5291 #define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /**< SRC7 Bit Offset */
\r
5292 #define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /**< If 1, indicates that SRC7 was the source of the Soft Reset */
\r
5293 /* RSTCTL_SOFTRESET_STAT[SRC8] Bits */
\r
5294 #define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /**< SRC8 Bit Offset */
\r
5295 #define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /**< If 1, indicates that SRC8 was the source of the Soft Reset */
\r
5296 /* RSTCTL_SOFTRESET_STAT[SRC9] Bits */
\r
5297 #define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /**< SRC9 Bit Offset */
\r
5298 #define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /**< If 1, indicates that SRC9 was the source of the Soft Reset */
\r
5299 /* RSTCTL_SOFTRESET_STAT[SRC10] Bits */
\r
5300 #define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /**< SRC10 Bit Offset */
\r
5301 #define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /**< If 1, indicates that SRC10 was the source of the Soft Reset */
\r
5302 /* RSTCTL_SOFTRESET_STAT[SRC11] Bits */
\r
5303 #define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /**< SRC11 Bit Offset */
\r
5304 #define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /**< If 1, indicates that SRC11 was the source of the Soft Reset */
\r
5305 /* RSTCTL_SOFTRESET_STAT[SRC12] Bits */
\r
5306 #define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /**< SRC12 Bit Offset */
\r
5307 #define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /**< If 1, indicates that SRC12 was the source of the Soft Reset */
\r
5308 /* RSTCTL_SOFTRESET_STAT[SRC13] Bits */
\r
5309 #define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /**< SRC13 Bit Offset */
\r
5310 #define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /**< If 1, indicates that SRC13 was the source of the Soft Reset */
\r
5311 /* RSTCTL_SOFTRESET_STAT[SRC14] Bits */
\r
5312 #define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /**< SRC14 Bit Offset */
\r
5313 #define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /**< If 1, indicates that SRC14 was the source of the Soft Reset */
\r
5314 /* RSTCTL_SOFTRESET_STAT[SRC15] Bits */
\r
5315 #define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /**< SRC15 Bit Offset */
\r
5316 #define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /**< If 1, indicates that SRC15 was the source of the Soft Reset */
\r
5317 /* RSTCTL_SOFTRESET_CLR[SRC0] Bits */
\r
5318 #define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /**< SRC0 Bit Offset */
\r
5319 #define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5320 /* RSTCTL_SOFTRESET_CLR[SRC1] Bits */
\r
5321 #define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /**< SRC1 Bit Offset */
\r
5322 #define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5323 /* RSTCTL_SOFTRESET_CLR[SRC2] Bits */
\r
5324 #define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /**< SRC2 Bit Offset */
\r
5325 #define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5326 /* RSTCTL_SOFTRESET_CLR[SRC3] Bits */
\r
5327 #define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /**< SRC3 Bit Offset */
\r
5328 #define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5329 /* RSTCTL_SOFTRESET_CLR[SRC4] Bits */
\r
5330 #define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /**< SRC4 Bit Offset */
\r
5331 #define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5332 /* RSTCTL_SOFTRESET_CLR[SRC5] Bits */
\r
5333 #define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /**< SRC5 Bit Offset */
\r
5334 #define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5335 /* RSTCTL_SOFTRESET_CLR[SRC6] Bits */
\r
5336 #define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /**< SRC6 Bit Offset */
\r
5337 #define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5338 /* RSTCTL_SOFTRESET_CLR[SRC7] Bits */
\r
5339 #define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /**< SRC7 Bit Offset */
\r
5340 #define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5341 /* RSTCTL_SOFTRESET_CLR[SRC8] Bits */
\r
5342 #define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /**< SRC8 Bit Offset */
\r
5343 #define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5344 /* RSTCTL_SOFTRESET_CLR[SRC9] Bits */
\r
5345 #define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /**< SRC9 Bit Offset */
\r
5346 #define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5347 /* RSTCTL_SOFTRESET_CLR[SRC10] Bits */
\r
5348 #define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /**< SRC10 Bit Offset */
\r
5349 #define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5350 /* RSTCTL_SOFTRESET_CLR[SRC11] Bits */
\r
5351 #define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /**< SRC11 Bit Offset */
\r
5352 #define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5353 /* RSTCTL_SOFTRESET_CLR[SRC12] Bits */
\r
5354 #define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /**< SRC12 Bit Offset */
\r
5355 #define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5356 /* RSTCTL_SOFTRESET_CLR[SRC13] Bits */
\r
5357 #define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /**< SRC13 Bit Offset */
\r
5358 #define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5359 /* RSTCTL_SOFTRESET_CLR[SRC14] Bits */
\r
5360 #define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /**< SRC14 Bit Offset */
\r
5361 #define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5362 /* RSTCTL_SOFTRESET_CLR[SRC15] Bits */
\r
5363 #define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /**< SRC15 Bit Offset */
\r
5364 #define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
5365 /* RSTCTL_SOFTRESET_SET[SRC0] Bits */
\r
5366 #define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /**< SRC0 Bit Offset */
\r
5367 #define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5368 /* a Soft Reset) */
\r
5369 /* RSTCTL_SOFTRESET_SET[SRC1] Bits */
\r
5370 #define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /**< SRC1 Bit Offset */
\r
5371 #define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5372 /* a Soft Reset) */
\r
5373 /* RSTCTL_SOFTRESET_SET[SRC2] Bits */
\r
5374 #define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /**< SRC2 Bit Offset */
\r
5375 #define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5376 /* a Soft Reset) */
\r
5377 /* RSTCTL_SOFTRESET_SET[SRC3] Bits */
\r
5378 #define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /**< SRC3 Bit Offset */
\r
5379 #define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5380 /* a Soft Reset) */
\r
5381 /* RSTCTL_SOFTRESET_SET[SRC4] Bits */
\r
5382 #define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /**< SRC4 Bit Offset */
\r
5383 #define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5384 /* a Soft Reset) */
\r
5385 /* RSTCTL_SOFTRESET_SET[SRC5] Bits */
\r
5386 #define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /**< SRC5 Bit Offset */
\r
5387 #define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5388 /* a Soft Reset) */
\r
5389 /* RSTCTL_SOFTRESET_SET[SRC6] Bits */
\r
5390 #define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /**< SRC6 Bit Offset */
\r
5391 #define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5392 /* a Soft Reset) */
\r
5393 /* RSTCTL_SOFTRESET_SET[SRC7] Bits */
\r
5394 #define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /**< SRC7 Bit Offset */
\r
5395 #define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5396 /* a Soft Reset) */
\r
5397 /* RSTCTL_SOFTRESET_SET[SRC8] Bits */
\r
5398 #define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /**< SRC8 Bit Offset */
\r
5399 #define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5400 /* a Soft Reset) */
\r
5401 /* RSTCTL_SOFTRESET_SET[SRC9] Bits */
\r
5402 #define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /**< SRC9 Bit Offset */
\r
5403 #define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5404 /* a Soft Reset) */
\r
5405 /* RSTCTL_SOFTRESET_SET[SRC10] Bits */
\r
5406 #define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /**< SRC10 Bit Offset */
\r
5407 #define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5408 /* a Soft Reset) */
\r
5409 /* RSTCTL_SOFTRESET_SET[SRC11] Bits */
\r
5410 #define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /**< SRC11 Bit Offset */
\r
5411 #define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5412 /* a Soft Reset) */
\r
5413 /* RSTCTL_SOFTRESET_SET[SRC12] Bits */
\r
5414 #define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /**< SRC12 Bit Offset */
\r
5415 #define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5416 /* a Soft Reset) */
\r
5417 /* RSTCTL_SOFTRESET_SET[SRC13] Bits */
\r
5418 #define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /**< SRC13 Bit Offset */
\r
5419 #define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5420 /* a Soft Reset) */
\r
5421 /* RSTCTL_SOFTRESET_SET[SRC14] Bits */
\r
5422 #define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /**< SRC14 Bit Offset */
\r
5423 #define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5424 /* a Soft Reset) */
\r
5425 /* RSTCTL_SOFTRESET_SET[SRC15] Bits */
\r
5426 #define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /**< SRC15 Bit Offset */
\r
5427 #define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
\r
5428 /* a Soft Reset) */
\r
5429 /* RSTCTL_PSSRESET_STAT[SVSMH] Bits */
\r
5430 #define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /**< SVSMH Bit Offset */
\r
5431 #define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /**< Indicates if POR was caused by an SVSMH trip condition int the PSS */
\r
5432 /* RSTCTL_PSSRESET_STAT[BGREF] Bits */
\r
5433 #define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /**< BGREF Bit Offset */
\r
5434 #define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /**< Indicates if POR was caused by a BGREF not okay condition in the PSS */
\r
5435 /* RSTCTL_PSSRESET_STAT[VCCDET] Bits */
\r
5436 #define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /**< VCCDET Bit Offset */
\r
5437 #define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /**< Indicates if POR was caused by a VCCDET trip condition in the PSS */
\r
5438 /* RSTCTL_PSSRESET_STAT[SVSL] Bits */
\r
5439 #define RSTCTL_PSSRESET_STAT_SVSL_OFS ( 0) /**< SVSL Bit Offset */
\r
5440 #define RSTCTL_PSSRESET_STAT_SVSL ((uint32_t)0x00000001) /**< Indicates if POR was caused by an SVSL trip condition in the PSS */
\r
5441 /* RSTCTL_PSSRESET_CLR[CLR] Bits */
\r
5442 #define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */
\r
5443 #define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */
\r
5444 /* RSTCTL_PCMRESET_STAT[LPM35] Bits */
\r
5445 #define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /**< LPM35 Bit Offset */
\r
5446 #define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /**< Indicates if POR was caused by PCM due to an exit from LPM3.5 */
\r
5447 /* RSTCTL_PCMRESET_STAT[LPM45] Bits */
\r
5448 #define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /**< LPM45 Bit Offset */
\r
5449 #define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /**< Indicates if POR was caused by PCM due to an exit from LPM4.5 */
\r
5450 /* RSTCTL_PCMRESET_CLR[CLR] Bits */
\r
5451 #define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */
\r
5452 #define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */
\r
5453 /* RSTCTL_PINRESET_STAT[RSTNMI] Bits */
\r
5454 #define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /**< RSTNMI Bit Offset */
\r
5455 #define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /**< POR was caused by RSTn/NMI pin based reset event */
\r
5456 /* RSTCTL_PINRESET_CLR[CLR] Bits */
\r
5457 #define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */
\r
5458 #define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */
\r
5459 /* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */
\r
5460 #define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /**< REBOOT Bit Offset */
\r
5461 #define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /**< Indicates if Reboot reset was caused by the SYSCTL module. */
\r
5462 /* RSTCTL_REBOOTRESET_CLR[CLR] Bits */
\r
5463 #define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */
\r
5464 #define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */
\r
5465 /* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */
\r
5466 #define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /**< DCOR_SHT Bit Offset */
\r
5467 #define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /**< Indicates if POR was caused by DCO short circuit fault in the external */
\r
5468 /* resistor mode */
\r
5469 /* RSTCTL_CSRESET_CLR[CLR] Bits */
\r
5470 #define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */
\r
5471 #define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as DCOR_SHTIFG */
\r
5472 /* flag in CSIFG register of clock system */
\r
5474 /* Pre-defined bitfield values */
\r
5475 #define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /* Key value to enable writes to bits 1-0 */
\r
5478 /******************************************************************************
\r
5480 ******************************************************************************/
\r
5481 /* RTC_C_CTL0[RDYIFG] Bits */
\r
5482 #define RTC_C_CTL0_RDYIFG_OFS ( 0) /**< RTCRDYIFG Bit Offset */
\r
5483 #define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /**< Real-time clock ready interrupt flag */
\r
5484 /* RTC_C_CTL0[AIFG] Bits */
\r
5485 #define RTC_C_CTL0_AIFG_OFS ( 1) /**< RTCAIFG Bit Offset */
\r
5486 #define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /**< Real-time clock alarm interrupt flag */
\r
5487 /* RTC_C_CTL0[TEVIFG] Bits */
\r
5488 #define RTC_C_CTL0_TEVIFG_OFS ( 2) /**< RTCTEVIFG Bit Offset */
\r
5489 #define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /**< Real-time clock time event interrupt flag */
\r
5490 /* RTC_C_CTL0[OFIFG] Bits */
\r
5491 #define RTC_C_CTL0_OFIFG_OFS ( 3) /**< RTCOFIFG Bit Offset */
\r
5492 #define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /**< 32-kHz crystal oscillator fault interrupt flag */
\r
5493 /* RTC_C_CTL0[RDYIE] Bits */
\r
5494 #define RTC_C_CTL0_RDYIE_OFS ( 4) /**< RTCRDYIE Bit Offset */
\r
5495 #define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /**< Real-time clock ready interrupt enable */
\r
5496 /* RTC_C_CTL0[AIE] Bits */
\r
5497 #define RTC_C_CTL0_AIE_OFS ( 5) /**< RTCAIE Bit Offset */
\r
5498 #define RTC_C_CTL0_AIE ((uint16_t)0x0020) /**< Real-time clock alarm interrupt enable */
\r
5499 /* RTC_C_CTL0[TEVIE] Bits */
\r
5500 #define RTC_C_CTL0_TEVIE_OFS ( 6) /**< RTCTEVIE Bit Offset */
\r
5501 #define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /**< Real-time clock time event interrupt enable */
\r
5502 /* RTC_C_CTL0[OFIE] Bits */
\r
5503 #define RTC_C_CTL0_OFIE_OFS ( 7) /**< RTCOFIE Bit Offset */
\r
5504 #define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /**< 32-kHz crystal oscillator fault interrupt enable */
\r
5505 /* RTC_C_CTL0[KEY] Bits */
\r
5506 #define RTC_C_CTL0_KEY_OFS ( 8) /**< RTCKEY Bit Offset */
\r
5507 #define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /**< RTCKEY Bit Mask */
\r
5508 /* RTC_C_CTL13[TEV] Bits */
\r
5509 #define RTC_C_CTL13_TEV_OFS ( 0) /**< RTCTEV Bit Offset */
\r
5510 #define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /**< RTCTEV Bit Mask */
\r
5511 #define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /**< TEV Bit 0 */
\r
5512 #define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /**< TEV Bit 1 */
\r
5513 #define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /**< Minute changed */
\r
5514 #define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /**< Hour changed */
\r
5515 #define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /**< Every day at midnight (00:00) */
\r
5516 #define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /**< Every day at noon (12:00) */
\r
5517 /* RTC_C_CTL13[SSEL] Bits */
\r
5518 #define RTC_C_CTL13_SSEL_OFS ( 2) /**< RTCSSEL Bit Offset */
\r
5519 #define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /**< RTCSSEL Bit Mask */
\r
5520 #define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /**< SSEL Bit 0 */
\r
5521 #define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /**< SSEL Bit 1 */
\r
5522 #define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /**< BCLK */
\r
5523 #define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /**< BCLK */
\r
5524 /* RTC_C_CTL13[RDY] Bits */
\r
5525 #define RTC_C_CTL13_RDY_OFS ( 4) /**< RTCRDY Bit Offset */
\r
5526 #define RTC_C_CTL13_RDY ((uint16_t)0x0010) /**< Real-time clock ready */
\r
5527 /* RTC_C_CTL13[MODE] Bits */
\r
5528 #define RTC_C_CTL13_MODE_OFS ( 5) /**< RTCMODE Bit Offset */
\r
5529 #define RTC_C_CTL13_MODE ((uint16_t)0x0020)
\r
5530 /* RTC_C_CTL13[HOLD] Bits */
\r
5531 #define RTC_C_CTL13_HOLD_OFS ( 6) /**< RTCHOLD Bit Offset */
\r
5532 #define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /**< Real-time clock hold */
\r
5533 /* RTC_C_CTL13[BCD] Bits */
\r
5534 #define RTC_C_CTL13_BCD_OFS ( 7) /**< RTCBCD Bit Offset */
\r
5535 #define RTC_C_CTL13_BCD ((uint16_t)0x0080) /**< Real-time clock BCD select */
\r
5536 /* RTC_C_CTL13[CALF] Bits */
\r
5537 #define RTC_C_CTL13_CALF_OFS ( 8) /**< RTCCALF Bit Offset */
\r
5538 #define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /**< RTCCALF Bit Mask */
\r
5539 #define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /**< CALF Bit 0 */
\r
5540 #define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /**< CALF Bit 1 */
\r
5541 #define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /**< No frequency output to RTCCLK pin */
\r
5542 #define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /**< 512 Hz */
\r
5543 #define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /**< 256 Hz */
\r
5544 #define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /**< 1 Hz */
\r
5545 #define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /**< No frequency output to RTCCLK pin */
\r
5546 #define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /**< 512 Hz */
\r
5547 #define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /**< 256 Hz */
\r
5548 #define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /**< 1 Hz */
\r
5549 /* RTC_C_OCAL[OCAL] Bits */
\r
5550 #define RTC_C_OCAL_OCAL_OFS ( 0) /**< RTCOCAL Bit Offset */
\r
5551 #define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /**< RTCOCAL Bit Mask */
\r
5552 /* RTC_C_OCAL[OCALS] Bits */
\r
5553 #define RTC_C_OCAL_OCALS_OFS (15) /**< RTCOCALS Bit Offset */
\r
5554 #define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /**< Real-time clock offset error calibration sign */
\r
5555 /* RTC_C_TCMP[TCMPX] Bits */
\r
5556 #define RTC_C_TCMP_TCMPX_OFS ( 0) /**< RTCTCMP Bit Offset */
\r
5557 #define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /**< RTCTCMP Bit Mask */
\r
5558 /* RTC_C_TCMP[TCOK] Bits */
\r
5559 #define RTC_C_TCMP_TCOK_OFS (13) /**< RTCTCOK Bit Offset */
\r
5560 #define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /**< Real-time clock temperature compensation write OK */
\r
5561 /* RTC_C_TCMP[TCRDY] Bits */
\r
5562 #define RTC_C_TCMP_TCRDY_OFS (14) /**< RTCTCRDY Bit Offset */
\r
5563 #define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /**< Real-time clock temperature compensation ready */
\r
5564 /* RTC_C_TCMP[TCMPS] Bits */
\r
5565 #define RTC_C_TCMP_TCMPS_OFS (15) /**< RTCTCMPS Bit Offset */
\r
5566 #define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /**< Real-time clock temperature compensation sign */
\r
5567 /* RTC_C_PS0CTL[RT0PSIFG] Bits */
\r
5568 #define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /**< RT0PSIFG Bit Offset */
\r
5569 #define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /**< Prescale timer 0 interrupt flag */
\r
5570 /* RTC_C_PS0CTL[RT0PSIE] Bits */
\r
5571 #define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /**< RT0PSIE Bit Offset */
\r
5572 #define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /**< Prescale timer 0 interrupt enable */
\r
5573 /* RTC_C_PS0CTL[RT0IP] Bits */
\r
5574 #define RTC_C_PS0CTL_RT0IP_OFS ( 2) /**< RT0IP Bit Offset */
\r
5575 #define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /**< RT0IP Bit Mask */
\r
5576 #define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /**< RT0IP Bit 0 */
\r
5577 #define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /**< RT0IP Bit 1 */
\r
5578 #define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /**< RT0IP Bit 2 */
\r
5579 #define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /**< Divide by 2 */
\r
5580 #define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /**< Divide by 4 */
\r
5581 #define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /**< Divide by 8 */
\r
5582 #define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /**< Divide by 16 */
\r
5583 #define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /**< Divide by 32 */
\r
5584 #define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /**< Divide by 64 */
\r
5585 #define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /**< Divide by 128 */
\r
5586 #define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /**< Divide by 256 */
\r
5587 #define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /**< Divide by 2 */
\r
5588 #define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /**< Divide by 4 */
\r
5589 #define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /**< Divide by 8 */
\r
5590 #define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /**< Divide by 16 */
\r
5591 #define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /**< Divide by 32 */
\r
5592 #define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /**< Divide by 64 */
\r
5593 #define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /**< Divide by 128 */
\r
5594 #define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /**< Divide by 256 */
\r
5595 /* RTC_C_PS1CTL[RT1PSIFG] Bits */
\r
5596 #define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /**< RT1PSIFG Bit Offset */
\r
5597 #define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /**< Prescale timer 1 interrupt flag */
\r
5598 /* RTC_C_PS1CTL[RT1PSIE] Bits */
\r
5599 #define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /**< RT1PSIE Bit Offset */
\r
5600 #define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /**< Prescale timer 1 interrupt enable */
\r
5601 /* RTC_C_PS1CTL[RT1IP] Bits */
\r
5602 #define RTC_C_PS1CTL_RT1IP_OFS ( 2) /**< RT1IP Bit Offset */
\r
5603 #define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /**< RT1IP Bit Mask */
\r
5604 #define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /**< RT1IP Bit 0 */
\r
5605 #define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /**< RT1IP Bit 1 */
\r
5606 #define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /**< RT1IP Bit 2 */
\r
5607 #define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /**< Divide by 2 */
\r
5608 #define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /**< Divide by 4 */
\r
5609 #define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /**< Divide by 8 */
\r
5610 #define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /**< Divide by 16 */
\r
5611 #define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /**< Divide by 32 */
\r
5612 #define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /**< Divide by 64 */
\r
5613 #define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /**< Divide by 128 */
\r
5614 #define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /**< Divide by 256 */
\r
5615 #define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /**< Divide by 2 */
\r
5616 #define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /**< Divide by 4 */
\r
5617 #define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /**< Divide by 8 */
\r
5618 #define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /**< Divide by 16 */
\r
5619 #define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /**< Divide by 32 */
\r
5620 #define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /**< Divide by 64 */
\r
5621 #define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /**< Divide by 128 */
\r
5622 #define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /**< Divide by 256 */
\r
5623 /* RTC_C_PS[RT0PS] Bits */
\r
5624 #define RTC_C_PS_RT0PS_OFS ( 0) /**< RT0PS Bit Offset */
\r
5625 #define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /**< RT0PS Bit Mask */
\r
5626 /* RTC_C_PS[RT1PS] Bits */
\r
5627 #define RTC_C_PS_RT1PS_OFS ( 8) /**< RT1PS Bit Offset */
\r
5628 #define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /**< RT1PS Bit Mask */
\r
5629 /* RTC_C_TIM0[SEC] Bits */
\r
5630 #define RTC_C_TIM0_SEC_OFS ( 0) /**< Seconds Bit Offset */
\r
5631 #define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /**< Seconds Bit Mask */
\r
5632 /* RTC_C_TIM0[MIN] Bits */
\r
5633 #define RTC_C_TIM0_MIN_OFS ( 8) /**< Minutes Bit Offset */
\r
5634 #define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /**< Minutes Bit Mask */
\r
5635 /* RTC_C_TIM0[SEC_LD] Bits */
\r
5636 #define RTC_C_TIM0_SEC_LD_OFS ( 0) /**< SecondsLowDigit Bit Offset */
\r
5637 #define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /**< SecondsLowDigit Bit Mask */
\r
5638 /* RTC_C_TIM0[SEC_HD] Bits */
\r
5639 #define RTC_C_TIM0_SEC_HD_OFS ( 4) /**< SecondsHighDigit Bit Offset */
\r
5640 #define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /**< SecondsHighDigit Bit Mask */
\r
5641 /* RTC_C_TIM0[MIN_LD] Bits */
\r
5642 #define RTC_C_TIM0_MIN_LD_OFS ( 8) /**< MinutesLowDigit Bit Offset */
\r
5643 #define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /**< MinutesLowDigit Bit Mask */
\r
5644 /* RTC_C_TIM0[MIN_HD] Bits */
\r
5645 #define RTC_C_TIM0_MIN_HD_OFS (12) /**< MinutesHighDigit Bit Offset */
\r
5646 #define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /**< MinutesHighDigit Bit Mask */
\r
5647 /* RTC_C_TIM1[HOUR] Bits */
\r
5648 #define RTC_C_TIM1_HOUR_OFS ( 0) /**< Hours Bit Offset */
\r
5649 #define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /**< Hours Bit Mask */
\r
5650 /* RTC_C_TIM1[DOW] Bits */
\r
5651 #define RTC_C_TIM1_DOW_OFS ( 8) /**< DayofWeek Bit Offset */
\r
5652 #define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /**< DayofWeek Bit Mask */
\r
5653 /* RTC_C_TIM1[HOUR_LD] Bits */
\r
5654 #define RTC_C_TIM1_HOUR_LD_OFS ( 0) /**< HoursLowDigit Bit Offset */
\r
5655 #define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /**< HoursLowDigit Bit Mask */
\r
5656 /* RTC_C_TIM1[HOUR_HD] Bits */
\r
5657 #define RTC_C_TIM1_HOUR_HD_OFS ( 4) /**< HoursHighDigit Bit Offset */
\r
5658 #define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /**< HoursHighDigit Bit Mask */
\r
5659 /* RTC_C_DATE[DAY] Bits */
\r
5660 #define RTC_C_DATE_DAY_OFS ( 0) /**< Day Bit Offset */
\r
5661 #define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /**< Day Bit Mask */
\r
5662 /* RTC_C_DATE[MON] Bits */
\r
5663 #define RTC_C_DATE_MON_OFS ( 8) /**< Month Bit Offset */
\r
5664 #define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /**< Month Bit Mask */
\r
5665 /* RTC_C_DATE[DAY_LD] Bits */
\r
5666 #define RTC_C_DATE_DAY_LD_OFS ( 0) /**< DayLowDigit Bit Offset */
\r
5667 #define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /**< DayLowDigit Bit Mask */
\r
5668 /* RTC_C_DATE[DAY_HD] Bits */
\r
5669 #define RTC_C_DATE_DAY_HD_OFS ( 4) /**< DayHighDigit Bit Offset */
\r
5670 #define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /**< DayHighDigit Bit Mask */
\r
5671 /* RTC_C_DATE[MON_LD] Bits */
\r
5672 #define RTC_C_DATE_MON_LD_OFS ( 8) /**< MonthLowDigit Bit Offset */
\r
5673 #define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /**< MonthLowDigit Bit Mask */
\r
5674 /* RTC_C_DATE[MON_HD] Bits */
\r
5675 #define RTC_C_DATE_MON_HD_OFS (12) /**< MonthHighDigit Bit Offset */
\r
5676 #define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /**< Month ? high digit (0 or 1) */
\r
5677 /* RTC_C_YEAR[YEAR_LB] Bits */
\r
5678 #define RTC_C_YEAR_YEAR_LB_OFS ( 0) /**< YearLowByte Bit Offset */
\r
5679 #define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /**< YearLowByte Bit Mask */
\r
5680 /* RTC_C_YEAR[YEAR_HB] Bits */
\r
5681 #define RTC_C_YEAR_YEAR_HB_OFS ( 8) /**< YearHighByte Bit Offset */
\r
5682 #define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /**< YearHighByte Bit Mask */
\r
5683 /* RTC_C_YEAR[YEAR] Bits */
\r
5684 #define RTC_C_YEAR_YEAR_OFS ( 0) /**< Year Bit Offset */
\r
5685 #define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /**< Year Bit Mask */
\r
5686 /* RTC_C_YEAR[DEC] Bits */
\r
5687 #define RTC_C_YEAR_DEC_OFS ( 4) /**< Decade Bit Offset */
\r
5688 #define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /**< Decade Bit Mask */
\r
5689 /* RTC_C_YEAR[CENT_LD] Bits */
\r
5690 #define RTC_C_YEAR_CENT_LD_OFS ( 8) /**< CenturyLowDigit Bit Offset */
\r
5691 #define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /**< CenturyLowDigit Bit Mask */
\r
5692 /* RTC_C_YEAR[CENT_HD] Bits */
\r
5693 #define RTC_C_YEAR_CENT_HD_OFS (12) /**< CenturyHighDigit Bit Offset */
\r
5694 #define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /**< CenturyHighDigit Bit Mask */
\r
5695 /* RTC_C_AMINHR[MIN] Bits */
\r
5696 #define RTC_C_AMINHR_MIN_OFS ( 0) /**< Minutes Bit Offset */
\r
5697 #define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /**< Minutes Bit Mask */
\r
5698 /* RTC_C_AMINHR[MINAE] Bits */
\r
5699 #define RTC_C_AMINHR_MINAE_OFS ( 7) /**< MINAE Bit Offset */
\r
5700 #define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /**< Alarm enable */
\r
5701 /* RTC_C_AMINHR[HOUR] Bits */
\r
5702 #define RTC_C_AMINHR_HOUR_OFS ( 8) /**< Hours Bit Offset */
\r
5703 #define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /**< Hours Bit Mask */
\r
5704 /* RTC_C_AMINHR[HOURAE] Bits */
\r
5705 #define RTC_C_AMINHR_HOURAE_OFS (15) /**< HOURAE Bit Offset */
\r
5706 #define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /**< Alarm enable */
\r
5707 /* RTC_C_AMINHR[MIN_LD] Bits */
\r
5708 #define RTC_C_AMINHR_MIN_LD_OFS ( 0) /**< MinutesLowDigit Bit Offset */
\r
5709 #define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /**< MinutesLowDigit Bit Mask */
\r
5710 /* RTC_C_AMINHR[MIN_HD] Bits */
\r
5711 #define RTC_C_AMINHR_MIN_HD_OFS ( 4) /**< MinutesHighDigit Bit Offset */
\r
5712 #define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /**< MinutesHighDigit Bit Mask */
\r
5713 /* RTC_C_AMINHR[HOUR_LD] Bits */
\r
5714 #define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /**< HoursLowDigit Bit Offset */
\r
5715 #define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /**< HoursLowDigit Bit Mask */
\r
5716 /* RTC_C_AMINHR[HOUR_HD] Bits */
\r
5717 #define RTC_C_AMINHR_HOUR_HD_OFS (12) /**< HoursHighDigit Bit Offset */
\r
5718 #define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /**< HoursHighDigit Bit Mask */
\r
5719 /* RTC_C_ADOWDAY[DOW] Bits */
\r
5720 #define RTC_C_ADOWDAY_DOW_OFS ( 0) /**< DayofWeek Bit Offset */
\r
5721 #define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /**< DayofWeek Bit Mask */
\r
5722 /* RTC_C_ADOWDAY[DOWAE] Bits */
\r
5723 #define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /**< DOWAE Bit Offset */
\r
5724 #define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /**< Alarm enable */
\r
5725 /* RTC_C_ADOWDAY[DAY] Bits */
\r
5726 #define RTC_C_ADOWDAY_DAY_OFS ( 8) /**< DayofMonth Bit Offset */
\r
5727 #define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /**< DayofMonth Bit Mask */
\r
5728 /* RTC_C_ADOWDAY[DAYAE] Bits */
\r
5729 #define RTC_C_ADOWDAY_DAYAE_OFS (15) /**< DAYAE Bit Offset */
\r
5730 #define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /**< Alarm enable */
\r
5731 /* RTC_C_ADOWDAY[DAY_LD] Bits */
\r
5732 #define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /**< DayLowDigit Bit Offset */
\r
5733 #define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /**< DayLowDigit Bit Mask */
\r
5734 /* RTC_C_ADOWDAY[DAY_HD] Bits */
\r
5735 #define RTC_C_ADOWDAY_DAY_HD_OFS (12) /**< DayHighDigit Bit Offset */
\r
5736 #define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /**< DayHighDigit Bit Mask */
\r
5738 /* Pre-defined bitfield values */
\r
5739 #define RTC_C_KEY ((uint16_t)0xA500) /* RTC_C Key Value for RTC_C write access */
\r
5740 #define RTC_C_KEY_H ((uint16_t)0x00A5) /* RTC_C Key Value for RTC_C write access */
\r
5741 #define RTC_C_KEY_VAL ((uint16_t)0xA500) /* RTC_C Key Value for RTC_C write access */
\r
5744 /******************************************************************************
\r
5746 ******************************************************************************/
\r
5747 /* SCB_PFR0[STATE0] Bits */
\r
5748 #define SCB_PFR0_STATE0_OFS ( 0) /**< STATE0 Bit Offset */
\r
5749 #define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /**< STATE0 Bit Mask */
\r
5750 #define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /**< STATE0 Bit 0 */
\r
5751 #define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /**< STATE0 Bit 1 */
\r
5752 #define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /**< STATE0 Bit 2 */
\r
5753 #define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /**< STATE0 Bit 3 */
\r
5754 #define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /**< no ARM encoding */
\r
5755 #define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /**< N/A */
\r
5756 /* SCB_PFR0[STATE1] Bits */
\r
5757 #define SCB_PFR0_STATE1_OFS ( 4) /**< STATE1 Bit Offset */
\r
5758 #define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /**< STATE1 Bit Mask */
\r
5759 #define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /**< STATE1 Bit 0 */
\r
5760 #define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /**< STATE1 Bit 1 */
\r
5761 #define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /**< STATE1 Bit 2 */
\r
5762 #define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /**< STATE1 Bit 3 */
\r
5763 #define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /**< N/A */
\r
5764 #define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /**< N/A */
\r
5765 #define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /**< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but */
\r
5766 /* no other 32-bit basic instructions (Note non-basic 32-bit instructions can be */
\r
5767 /* added using the appropriate instruction attribute, but other 32-bit basic */
\r
5768 /* instructions cannot.) */
\r
5769 #define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /**< Thumb-2 encoding with all Thumb-2 basic instructions */
\r
5770 /* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */
\r
5771 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */
\r
5772 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */
\r
5773 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */
\r
5774 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */
\r
5775 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */
\r
5776 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */
\r
5777 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /**< not supported */
\r
5778 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /**< two-stack support */
\r
5779 /* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */
\r
5780 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /**< MICROCONTROLLER_DEBUG_MODEL Bit Offset */
\r
5781 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /**< MICROCONTROLLER_DEBUG_MODEL Bit Mask */
\r
5782 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /**< MICROCONTROLLER_DEBUG_MODEL Bit 0 */
\r
5783 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /**< MICROCONTROLLER_DEBUG_MODEL Bit 1 */
\r
5784 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /**< MICROCONTROLLER_DEBUG_MODEL Bit 2 */
\r
5785 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /**< MICROCONTROLLER_DEBUG_MODEL Bit 3 */
\r
5786 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /**< not supported */
\r
5787 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /**< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */
\r
5788 /* SCB_MMFR0[PMSA_SUPPORT] Bits */
\r
5789 #define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /**< PMSA_SUPPORT Bit Offset */
\r
5790 #define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /**< PMSA_SUPPORT Bit Mask */
\r
5791 #define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /**< PMSA_SUPPORT Bit 0 */
\r
5792 #define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /**< PMSA_SUPPORT Bit 1 */
\r
5793 #define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /**< PMSA_SUPPORT Bit 2 */
\r
5794 #define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /**< PMSA_SUPPORT Bit 3 */
\r
5795 #define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /**< not supported */
\r
5796 #define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /**< IMPLEMENTATION DEFINED (N/A) */
\r
5797 #define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /**< PMSA base (features as defined for ARMv6) (N/A) */
\r
5798 #define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /**< PMSAv7 (base plus subregion support) */
\r
5799 /* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */
\r
5800 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /**< CACHE_COHERENCE_SUPPORT Bit Offset */
\r
5801 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /**< CACHE_COHERENCE_SUPPORT Bit Mask */
\r
5802 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /**< CACHE_COHERENCE_SUPPORT Bit 0 */
\r
5803 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /**< CACHE_COHERENCE_SUPPORT Bit 1 */
\r
5804 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /**< CACHE_COHERENCE_SUPPORT Bit 2 */
\r
5805 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /**< CACHE_COHERENCE_SUPPORT Bit 3 */
\r
5806 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /**< no shared support */
\r
5807 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /**< partial-inner-shared coherency (coherency amongst some - but not all - of the */
\r
5808 /* entities within an inner-coherent domain) */
\r
5809 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /**< full-inner-shared coherency (coherency amongst all of the entities within an */
\r
5810 /* inner-coherent domain) */
\r
5811 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /**< full coherency (coherency amongst all of the entities) */
\r
5812 /* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */
\r
5813 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /**< OUTER_NON_SHARABLE_SUPPORT Bit Offset */
\r
5814 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /**< OUTER_NON_SHARABLE_SUPPORT Bit Mask */
\r
5815 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /**< OUTER_NON_SHARABLE_SUPPORT Bit 0 */
\r
5816 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /**< OUTER_NON_SHARABLE_SUPPORT Bit 1 */
\r
5817 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /**< OUTER_NON_SHARABLE_SUPPORT Bit 2 */
\r
5818 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /**< OUTER_NON_SHARABLE_SUPPORT Bit 3 */
\r
5819 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /**< Outer non-sharable not supported */
\r
5820 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /**< Outer sharable supported */
\r
5821 /* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */
\r
5822 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /**< AUXILIARY_REGISTER_SUPPORT Bit Offset */
\r
5823 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /**< AUXILIARY_REGISTER_SUPPORT Bit Mask */
\r
5824 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /**< AUILIARY_REGISTER_SUPPORT Bit 0 */
\r
5825 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /**< AUILIARY_REGISTER_SUPPORT Bit 1 */
\r
5826 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /**< AUILIARY_REGISTER_SUPPORT Bit 2 */
\r
5827 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /**< AUILIARY_REGISTER_SUPPORT Bit 3 */
\r
5828 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /**< not supported */
\r
5829 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /**< Auxiliary control register */
\r
5830 /* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */
\r
5831 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /**< WAIT_FOR_INTERRUPT_STALLING Bit Offset */
\r
5832 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit Mask */
\r
5833 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit 0 */
\r
5834 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit 1 */
\r
5835 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit 2 */
\r
5836 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit 3 */
\r
5837 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /**< not supported */
\r
5838 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /**< wait for interrupt supported */
\r
5839 /* SCB_ISAR0[BITCOUNT_INSTRS] Bits */
\r
5840 #define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /**< BITCOUNT_INSTRS Bit Offset */
\r
5841 #define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /**< BITCOUNT_INSTRS Bit Mask */
\r
5842 #define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /**< BITCOUNT_INSTRS Bit 0 */
\r
5843 #define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /**< BITCOUNT_INSTRS Bit 1 */
\r
5844 #define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /**< BITCOUNT_INSTRS Bit 2 */
\r
5845 #define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /**< BITCOUNT_INSTRS Bit 3 */
\r
5846 #define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /**< no bit-counting instructions present */
\r
5847 #define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /**< adds CLZ */
\r
5848 /* SCB_ISAR0[BITFIELD_INSTRS] Bits */
\r
5849 #define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /**< BITFIELD_INSTRS Bit Offset */
\r
5850 #define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /**< BITFIELD_INSTRS Bit Mask */
\r
5851 #define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /**< BITFIELD_INSTRS Bit 0 */
\r
5852 #define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /**< BITFIELD_INSTRS Bit 1 */
\r
5853 #define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /**< BITFIELD_INSTRS Bit 2 */
\r
5854 #define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /**< BITFIELD_INSTRS Bit 3 */
\r
5855 #define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /**< no bitfield instructions present */
\r
5856 #define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /**< adds BFC, BFI, SBFX, UBFX */
\r
5857 /* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */
\r
5858 #define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /**< CMPBRANCH_INSTRS Bit Offset */
\r
5859 #define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /**< CMPBRANCH_INSTRS Bit Mask */
\r
5860 #define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /**< CMPBRANCH_INSTRS Bit 0 */
\r
5861 #define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /**< CMPBRANCH_INSTRS Bit 1 */
\r
5862 #define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /**< CMPBRANCH_INSTRS Bit 2 */
\r
5863 #define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /**< CMPBRANCH_INSTRS Bit 3 */
\r
5864 #define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /**< no combined compare-and-branch instructions present */
\r
5865 #define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /**< adds CB{N}Z */
\r
5866 /* SCB_ISAR0[COPROC_INSTRS] Bits */
\r
5867 #define SCB_ISAR0_COPROC_INSTRS_OFS (16) /**< COPROC_INSTRS Bit Offset */
\r
5868 #define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /**< COPROC_INSTRS Bit Mask */
\r
5869 #define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /**< COPROC_INSTRS Bit 0 */
\r
5870 #define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /**< COPROC_INSTRS Bit 1 */
\r
5871 #define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /**< COPROC_INSTRS Bit 2 */
\r
5872 #define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /**< COPROC_INSTRS Bit 3 */
\r
5873 #define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /**< no coprocessor support, other than for separately attributed architectures */
\r
5874 /* such as CP15 or VFP */
\r
5875 #define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /**< adds generic CDP, LDC, MCR, MRC, STC */
\r
5876 #define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /**< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */
\r
5877 #define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /**< adds generic MCRR, MRRC */
\r
5878 #define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /**< adds generic MCRR2, MRRC2 */
\r
5879 /* SCB_ISAR0[DEBUG_INSTRS] Bits */
\r
5880 #define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /**< DEBUG_INSTRS Bit Offset */
\r
5881 #define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /**< DEBUG_INSTRS Bit Mask */
\r
5882 #define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /**< DEBUG_INSTRS Bit 0 */
\r
5883 #define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /**< DEBUG_INSTRS Bit 1 */
\r
5884 #define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /**< DEBUG_INSTRS Bit 2 */
\r
5885 #define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /**< DEBUG_INSTRS Bit 3 */
\r
5886 #define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /**< no debug instructions present */
\r
5887 #define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /**< adds BKPT */
\r
5888 /* SCB_ISAR0[DIVIDE_INSTRS] Bits */
\r
5889 #define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /**< DIVIDE_INSTRS Bit Offset */
\r
5890 #define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /**< DIVIDE_INSTRS Bit Mask */
\r
5891 #define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /**< DIVIDE_INSTRS Bit 0 */
\r
5892 #define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /**< DIVIDE_INSTRS Bit 1 */
\r
5893 #define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /**< DIVIDE_INSTRS Bit 2 */
\r
5894 #define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /**< DIVIDE_INSTRS Bit 3 */
\r
5895 #define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /**< no divide instructions present */
\r
5896 #define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /**< adds SDIV, UDIV (v1 quotient only result) */
\r
5897 /* SCB_ISAR1[ETEND_INSRS] Bits */
\r
5898 #define SCB_ISAR1_ETEND_INSRS_OFS (12) /**< EXTEND_INSRS Bit Offset */
\r
5899 #define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /**< EXTEND_INSRS Bit Mask */
\r
5900 #define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /**< ETEND_INSRS Bit 0 */
\r
5901 #define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /**< ETEND_INSRS Bit 1 */
\r
5902 #define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /**< ETEND_INSRS Bit 2 */
\r
5903 #define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /**< ETEND_INSRS Bit 3 */
\r
5904 #define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /**< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */
\r
5905 #define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /**< adds SXTB, SXTH, UXTB, UXTH */
\r
5906 #define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /**< N/A */
\r
5907 /* SCB_ISAR1[IFTHEN_INSTRS] Bits */
\r
5908 #define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /**< IFTHEN_INSTRS Bit Offset */
\r
5909 #define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /**< IFTHEN_INSTRS Bit Mask */
\r
5910 #define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /**< IFTHEN_INSTRS Bit 0 */
\r
5911 #define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /**< IFTHEN_INSTRS Bit 1 */
\r
5912 #define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /**< IFTHEN_INSTRS Bit 2 */
\r
5913 #define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /**< IFTHEN_INSTRS Bit 3 */
\r
5914 #define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /**< IT instructions not present */
\r
5915 #define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /**< adds IT instructions (and IT bits in PSRs) */
\r
5916 /* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */
\r
5917 #define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /**< IMMEDIATE_INSTRS Bit Offset */
\r
5918 #define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /**< IMMEDIATE_INSTRS Bit Mask */
\r
5919 #define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /**< IMMEDIATE_INSTRS Bit 0 */
\r
5920 #define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /**< IMMEDIATE_INSTRS Bit 1 */
\r
5921 #define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /**< IMMEDIATE_INSTRS Bit 2 */
\r
5922 #define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /**< IMMEDIATE_INSTRS Bit 3 */
\r
5923 #define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /**< no special immediate-generating instructions present */
\r
5924 #define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /**< adds ADDW, MOVW, MOVT, SUBW */
\r
5925 /* SCB_ISAR1[INTERWORK_INSTRS] Bits */
\r
5926 #define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /**< INTERWORK_INSTRS Bit Offset */
\r
5927 #define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /**< INTERWORK_INSTRS Bit Mask */
\r
5928 #define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /**< INTERWORK_INSTRS Bit 0 */
\r
5929 #define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /**< INTERWORK_INSTRS Bit 1 */
\r
5930 #define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /**< INTERWORK_INSTRS Bit 2 */
\r
5931 #define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /**< INTERWORK_INSTRS Bit 3 */
\r
5932 #define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /**< no interworking instructions supported */
\r
5933 #define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /**< adds BX (and T bit in PSRs) */
\r
5934 #define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /**< adds BLX, and PC loads have BX-like behavior */
\r
5935 #define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /**< N/A */
\r
5936 /* SCB_ISAR2[LOADSTORE_INSTRS] Bits */
\r
5937 #define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /**< LOADSTORE_INSTRS Bit Offset */
\r
5938 #define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /**< LOADSTORE_INSTRS Bit Mask */
\r
5939 #define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /**< LOADSTORE_INSTRS Bit 0 */
\r
5940 #define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /**< LOADSTORE_INSTRS Bit 1 */
\r
5941 #define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /**< LOADSTORE_INSTRS Bit 2 */
\r
5942 #define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /**< LOADSTORE_INSTRS Bit 3 */
\r
5943 #define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /**< no additional normal load/store instructions present */
\r
5944 #define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /**< adds LDRD/STRD */
\r
5945 /* SCB_ISAR2[MEMHINT_INSTRS] Bits */
\r
5946 #define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /**< MEMHINT_INSTRS Bit Offset */
\r
5947 #define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /**< MEMHINT_INSTRS Bit Mask */
\r
5948 #define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /**< MEMHINT_INSTRS Bit 0 */
\r
5949 #define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /**< MEMHINT_INSTRS Bit 1 */
\r
5950 #define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /**< MEMHINT_INSTRS Bit 2 */
\r
5951 #define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /**< MEMHINT_INSTRS Bit 3 */
\r
5952 #define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /**< no memory hint instructions presen */
\r
5953 #define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /**< adds PLD */
\r
5954 #define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /**< adds PLD (ie a repeat on value 1) */
\r
5955 #define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /**< adds PLI */
\r
5956 /* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */
\r
5957 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /**< MULTIACCESSINT_INSTRS Bit Offset */
\r
5958 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /**< MULTIACCESSINT_INSTRS Bit Mask */
\r
5959 #define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /**< MULTIACCESSINT_INSTRS Bit 0 */
\r
5960 #define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /**< MULTIACCESSINT_INSTRS Bit 1 */
\r
5961 #define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /**< MULTIACCESSINT_INSTRS Bit 2 */
\r
5962 #define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /**< MULTIACCESSINT_INSTRS Bit 3 */
\r
5963 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /**< the (LDM/STM) instructions are non-interruptible */
\r
5964 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /**< the (LDM/STM) instructions are restartable */
\r
5965 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /**< the (LDM/STM) instructions are continuable */
\r
5966 /* SCB_ISAR2[MULT_INSTRS] Bits */
\r
5967 #define SCB_ISAR2_MULT_INSTRS_OFS (12) /**< MULT_INSTRS Bit Offset */
\r
5968 #define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /**< MULT_INSTRS Bit Mask */
\r
5969 #define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /**< MULT_INSTRS Bit 0 */
\r
5970 #define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /**< MULT_INSTRS Bit 1 */
\r
5971 #define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /**< MULT_INSTRS Bit 2 */
\r
5972 #define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /**< MULT_INSTRS Bit 3 */
\r
5973 #define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /**< only MUL present */
\r
5974 #define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /**< adds MLA */
\r
5975 #define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /**< adds MLS */
\r
5976 /* SCB_ISAR2[MULTS_INSTRS] Bits */
\r
5977 #define SCB_ISAR2_MULTS_INSTRS_OFS (16) /**< MULTS_INSTRS Bit Offset */
\r
5978 #define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /**< MULTS_INSTRS Bit Mask */
\r
5979 #define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /**< MULTS_INSTRS Bit 0 */
\r
5980 #define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /**< MULTS_INSTRS Bit 1 */
\r
5981 #define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /**< MULTS_INSTRS Bit 2 */
\r
5982 #define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /**< MULTS_INSTRS Bit 3 */
\r
5983 #define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /**< no signed multiply instructions present */
\r
5984 #define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /**< adds SMULL, SMLAL */
\r
5985 #define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /**< N/A */
\r
5986 #define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /**< N/A */
\r
5987 /* SCB_ISAR2[MULTU_INSTRS] Bits */
\r
5988 #define SCB_ISAR2_MULTU_INSTRS_OFS (20) /**< MULTU_INSTRS Bit Offset */
\r
5989 #define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /**< MULTU_INSTRS Bit Mask */
\r
5990 #define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /**< MULTU_INSTRS Bit 0 */
\r
5991 #define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /**< MULTU_INSTRS Bit 1 */
\r
5992 #define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /**< MULTU_INSTRS Bit 2 */
\r
5993 #define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /**< MULTU_INSTRS Bit 3 */
\r
5994 #define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /**< no unsigned multiply instructions present */
\r
5995 #define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /**< adds UMULL, UMLAL */
\r
5996 #define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /**< N/A */
\r
5997 /* SCB_ISAR2[REVERSAL_INSTRS] Bits */
\r
5998 #define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /**< REVERSAL_INSTRS Bit Offset */
\r
5999 #define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /**< REVERSAL_INSTRS Bit Mask */
\r
6000 #define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /**< REVERSAL_INSTRS Bit 0 */
\r
6001 #define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /**< REVERSAL_INSTRS Bit 1 */
\r
6002 #define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /**< REVERSAL_INSTRS Bit 2 */
\r
6003 #define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /**< REVERSAL_INSTRS Bit 3 */
\r
6004 #define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /**< no reversal instructions present */
\r
6005 #define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /**< adds REV, REV16, REVSH */
\r
6006 #define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /**< adds RBIT */
\r
6007 /* SCB_ISAR3[SATRUATE_INSTRS] Bits */
\r
6008 #define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /**< SATRUATE_INSTRS Bit Offset */
\r
6009 #define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /**< SATRUATE_INSTRS Bit Mask */
\r
6010 #define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /**< SATRUATE_INSTRS Bit 0 */
\r
6011 #define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /**< SATRUATE_INSTRS Bit 1 */
\r
6012 #define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /**< SATRUATE_INSTRS Bit 2 */
\r
6013 #define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /**< SATRUATE_INSTRS Bit 3 */
\r
6014 #define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /**< no non-SIMD saturate instructions present */
\r
6015 #define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /**< N/A */
\r
6016 /* SCB_ISAR3[SIMD_INSTRS] Bits */
\r
6017 #define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /**< SIMD_INSTRS Bit Offset */
\r
6018 #define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /**< SIMD_INSTRS Bit Mask */
\r
6019 #define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /**< SIMD_INSTRS Bit 0 */
\r
6020 #define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /**< SIMD_INSTRS Bit 1 */
\r
6021 #define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /**< SIMD_INSTRS Bit 2 */
\r
6022 #define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /**< SIMD_INSTRS Bit 3 */
\r
6023 #define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /**< no SIMD instructions present */
\r
6024 #define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /**< adds SSAT, USAT (and the Q flag in the PSRs) */
\r
6025 #define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /**< N/A */
\r
6026 /* SCB_ISAR3[SVC_INSTRS] Bits */
\r
6027 #define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /**< SVC_INSTRS Bit Offset */
\r
6028 #define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /**< SVC_INSTRS Bit Mask */
\r
6029 #define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /**< SVC_INSTRS Bit 0 */
\r
6030 #define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /**< SVC_INSTRS Bit 1 */
\r
6031 #define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /**< SVC_INSTRS Bit 2 */
\r
6032 #define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /**< SVC_INSTRS Bit 3 */
\r
6033 #define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /**< no SVC (SWI) instructions present */
\r
6034 #define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /**< adds SVC (SWI) */
\r
6035 /* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */
\r
6036 #define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /**< SYNCPRIM_INSTRS Bit Offset */
\r
6037 #define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /**< SYNCPRIM_INSTRS Bit Mask */
\r
6038 #define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /**< SYNCPRIM_INSTRS Bit 0 */
\r
6039 #define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /**< SYNCPRIM_INSTRS Bit 1 */
\r
6040 #define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /**< SYNCPRIM_INSTRS Bit 2 */
\r
6041 #define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /**< SYNCPRIM_INSTRS Bit 3 */
\r
6042 #define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /**< no synchronization primitives present */
\r
6043 #define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /**< adds LDREX, STREX */
\r
6044 #define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /**< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */
\r
6045 /* SCB_ISAR3[TABBRANCH_INSTRS] Bits */
\r
6046 #define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /**< TABBRANCH_INSTRS Bit Offset */
\r
6047 #define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /**< TABBRANCH_INSTRS Bit Mask */
\r
6048 #define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /**< TABBRANCH_INSTRS Bit 0 */
\r
6049 #define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /**< TABBRANCH_INSTRS Bit 1 */
\r
6050 #define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /**< TABBRANCH_INSTRS Bit 2 */
\r
6051 #define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /**< TABBRANCH_INSTRS Bit 3 */
\r
6052 #define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /**< no table-branch instructions present */
\r
6053 #define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /**< adds TBB, TBH */
\r
6054 /* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */
\r
6055 #define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /**< THUMBCOPY_INSTRS Bit Offset */
\r
6056 #define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /**< THUMBCOPY_INSTRS Bit Mask */
\r
6057 #define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /**< THUMBCOPY_INSTRS Bit 0 */
\r
6058 #define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /**< THUMBCOPY_INSTRS Bit 1 */
\r
6059 #define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /**< THUMBCOPY_INSTRS Bit 2 */
\r
6060 #define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /**< THUMBCOPY_INSTRS Bit 3 */
\r
6061 #define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /**< Thumb MOV(register) instruction does not allow low reg -> low reg */
\r
6062 #define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /**< adds Thumb MOV(register) low reg -> low reg and the CPY alias */
\r
6063 /* SCB_ISAR3[TRUENOP_INSTRS] Bits */
\r
6064 #define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /**< TRUENOP_INSTRS Bit Offset */
\r
6065 #define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /**< TRUENOP_INSTRS Bit Mask */
\r
6066 #define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /**< TRUENOP_INSTRS Bit 0 */
\r
6067 #define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /**< TRUENOP_INSTRS Bit 1 */
\r
6068 #define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /**< TRUENOP_INSTRS Bit 2 */
\r
6069 #define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /**< TRUENOP_INSTRS Bit 3 */
\r
6070 #define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /**< true NOP instructions not present - that is, NOP instructions with no register */
\r
6071 /* dependencies */
\r
6072 #define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /**< adds "true NOP", and the capability of additional "NOP compatible hints" */
\r
6073 /* SCB_ISAR4[UNPRIV_INSTRS] Bits */
\r
6074 #define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /**< UNPRIV_INSTRS Bit Offset */
\r
6075 #define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /**< UNPRIV_INSTRS Bit Mask */
\r
6076 #define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /**< UNPRIV_INSTRS Bit 0 */
\r
6077 #define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /**< UNPRIV_INSTRS Bit 1 */
\r
6078 #define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /**< UNPRIV_INSTRS Bit 2 */
\r
6079 #define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /**< UNPRIV_INSTRS Bit 3 */
\r
6080 #define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /**< no "T variant" instructions exist */
\r
6081 #define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /**< adds LDRBT, LDRT, STRBT, STRT */
\r
6082 #define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /**< adds LDRHT, LDRSBT, LDRSHT, STRHT */
\r
6083 /* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */
\r
6084 #define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /**< WITHSHIFTS_INSTRS Bit Offset */
\r
6085 #define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /**< WITHSHIFTS_INSTRS Bit Mask */
\r
6086 #define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /**< WITHSHIFTS_INSTRS Bit 0 */
\r
6087 #define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /**< WITHSHIFTS_INSTRS Bit 1 */
\r
6088 #define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /**< WITHSHIFTS_INSTRS Bit 2 */
\r
6089 #define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /**< WITHSHIFTS_INSTRS Bit 3 */
\r
6090 #define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /**< non-zero shifts only support MOV and shift instructions (see notes) */
\r
6091 #define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /**< shifts of loads/stores over the range LSL 0-3 */
\r
6092 #define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /**< adds other constant shift options. */
\r
6093 #define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /**< adds register-controlled shift options. */
\r
6094 /* SCB_ISAR4[WRITEBACK_INSTRS] Bits */
\r
6095 #define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /**< WRITEBACK_INSTRS Bit Offset */
\r
6096 #define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /**< WRITEBACK_INSTRS Bit Mask */
\r
6097 #define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /**< WRITEBACK_INSTRS Bit 0 */
\r
6098 #define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /**< WRITEBACK_INSTRS Bit 1 */
\r
6099 #define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /**< WRITEBACK_INSTRS Bit 2 */
\r
6100 #define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /**< WRITEBACK_INSTRS Bit 3 */
\r
6101 #define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /**< only non-writeback addressing modes present, except that LDMIA/STMDB/PUSH/POP */
\r
6102 /* instructions support writeback addressing. */
\r
6103 #define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /**< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */
\r
6104 /* SCB_ISAR4[BARRIER_INSTRS] Bits */
\r
6105 #define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /**< BARRIER_INSTRS Bit Offset */
\r
6106 #define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /**< BARRIER_INSTRS Bit Mask */
\r
6107 #define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /**< BARRIER_INSTRS Bit 0 */
\r
6108 #define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /**< BARRIER_INSTRS Bit 1 */
\r
6109 #define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /**< BARRIER_INSTRS Bit 2 */
\r
6110 #define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /**< BARRIER_INSTRS Bit 3 */
\r
6111 #define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /**< no barrier instructions supported */
\r
6112 #define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /**< adds DMB, DSB, ISB barrier instructions */
\r
6113 /* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */
\r
6114 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /**< SYNCPRIM_INSTRS_FRAC Bit Offset */
\r
6115 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /**< SYNCPRIM_INSTRS_FRAC Bit Mask */
\r
6116 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /**< SYNCPRIM_INSTRS_FRAC Bit 0 */
\r
6117 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /**< SYNCPRIM_INSTRS_FRAC Bit 1 */
\r
6118 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /**< SYNCPRIM_INSTRS_FRAC Bit 2 */
\r
6119 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /**< SYNCPRIM_INSTRS_FRAC Bit 3 */
\r
6120 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /**< no additional support */
\r
6121 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /**< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */
\r
6122 /* SCB_ISAR4[PSR_M_INSTRS] Bits */
\r
6123 #define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /**< PSR_M_INSTRS Bit Offset */
\r
6124 #define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /**< PSR_M_INSTRS Bit Mask */
\r
6125 #define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /**< PSR_M_INSTRS Bit 0 */
\r
6126 #define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /**< PSR_M_INSTRS Bit 1 */
\r
6127 #define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /**< PSR_M_INSTRS Bit 2 */
\r
6128 #define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /**< PSR_M_INSTRS Bit 3 */
\r
6129 #define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /**< instructions not present */
\r
6130 #define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /**< adds CPS, MRS, and MSR instructions (M-profile forms) */
\r
6131 /* SCB_CPACR[CP11] Bits */
\r
6132 #define SCB_CPACR_CP11_OFS (22) /**< CP11 Bit Offset */
\r
6133 #define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /**< CP11 Bit Mask */
\r
6134 /* SCB_CPACR[CP10] Bits */
\r
6135 #define SCB_CPACR_CP10_OFS (20) /**< CP10 Bit Offset */
\r
6136 #define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /**< CP10 Bit Mask */
\r
6139 /******************************************************************************
\r
6141 ******************************************************************************/
\r
6144 /******************************************************************************
\r
6146 ******************************************************************************/
\r
6147 /* SYSCTL_REBOOT_CTL[REBOOT] Bits */
\r
6148 #define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /**< REBOOT Bit Offset */
\r
6149 #define SYSCTL_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /**< Write 1 initiates a Reboot of the device */
\r
6150 /* SYSCTL_REBOOT_CTL[WKEY] Bits */
\r
6151 #define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /**< WKEY Bit Offset */
\r
6152 #define SYSCTL_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /**< WKEY Bit Mask */
\r
6153 /* SYSCTL_NMI_CTLSTAT[CS_SRC] Bits */
\r
6154 #define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /**< CS_SRC Bit Offset */
\r
6155 #define SYSCTL_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /**< CS interrupt as a source of NMI */
\r
6156 /* SYSCTL_NMI_CTLSTAT[PSS_SRC] Bits */
\r
6157 #define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /**< PSS_SRC Bit Offset */
\r
6158 #define SYSCTL_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /**< PSS interrupt as a source of NMI */
\r
6159 /* SYSCTL_NMI_CTLSTAT[PCM_SRC] Bits */
\r
6160 #define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /**< PCM_SRC Bit Offset */
\r
6161 #define SYSCTL_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /**< PCM interrupt as a source of NMI */
\r
6162 /* SYSCTL_NMI_CTLSTAT[PIN_SRC] Bits */
\r
6163 #define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /**< PIN_SRC Bit Offset */
\r
6164 #define SYSCTL_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008)
\r
6165 /* SYSCTL_NMI_CTLSTAT[CS_FLG] Bits */
\r
6166 #define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /**< CS_FLG Bit Offset */
\r
6167 #define SYSCTL_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /**< CS interrupt was the source of NMI */
\r
6168 /* SYSCTL_NMI_CTLSTAT[PSS_FLG] Bits */
\r
6169 #define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /**< PSS_FLG Bit Offset */
\r
6170 #define SYSCTL_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /**< PSS interrupt was the source of NMI */
\r
6171 /* SYSCTL_NMI_CTLSTAT[PCM_FLG] Bits */
\r
6172 #define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /**< PCM_FLG Bit Offset */
\r
6173 #define SYSCTL_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /**< PCM interrupt was the source of NMI */
\r
6174 /* SYSCTL_NMI_CTLSTAT[PIN_FLG] Bits */
\r
6175 #define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /**< PIN_FLG Bit Offset */
\r
6176 #define SYSCTL_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /**< RSTn/NMI pin was the source of NMI */
\r
6177 /* SYSCTL_WDTRESET_CTL[TIMEOUT] Bits */
\r
6178 #define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /**< TIMEOUT Bit Offset */
\r
6179 #define SYSCTL_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /**< WDT timeout reset type */
\r
6180 /* SYSCTL_WDTRESET_CTL[VIOLATION] Bits */
\r
6181 #define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /**< VIOLATION Bit Offset */
\r
6182 #define SYSCTL_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /**< WDT password violation reset type */
\r
6183 /* SYSCTL_PERIHALT_CTL[HALT_T16_0] Bits */
\r
6184 #define SYSCTL_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /**< HALT_T16_0 Bit Offset */
\r
6185 #define SYSCTL_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /**< Freezes IP operation when CPU is halted */
\r
6186 /* SYSCTL_PERIHALT_CTL[HALT_T16_1] Bits */
\r
6187 #define SYSCTL_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /**< HALT_T16_1 Bit Offset */
\r
6188 #define SYSCTL_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /**< Freezes IP operation when CPU is halted */
\r
6189 /* SYSCTL_PERIHALT_CTL[HALT_T16_2] Bits */
\r
6190 #define SYSCTL_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /**< HALT_T16_2 Bit Offset */
\r
6191 #define SYSCTL_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /**< Freezes IP operation when CPU is halted */
\r
6192 /* SYSCTL_PERIHALT_CTL[HALT_T16_3] Bits */
\r
6193 #define SYSCTL_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /**< HALT_T16_3 Bit Offset */
\r
6194 #define SYSCTL_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /**< Freezes IP operation when CPU is halted */
\r
6195 /* SYSCTL_PERIHALT_CTL[HALT_T32_0] Bits */
\r
6196 #define SYSCTL_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /**< HALT_T32_0 Bit Offset */
\r
6197 #define SYSCTL_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /**< Freezes IP operation when CPU is halted */
\r
6198 /* SYSCTL_PERIHALT_CTL[HALT_EUA0] Bits */
\r
6199 #define SYSCTL_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /**< HALT_eUA0 Bit Offset */
\r
6200 #define SYSCTL_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /**< Freezes IP operation when CPU is halted */
\r
6201 /* SYSCTL_PERIHALT_CTL[HALT_EUA1] Bits */
\r
6202 #define SYSCTL_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /**< HALT_eUA1 Bit Offset */
\r
6203 #define SYSCTL_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /**< Freezes IP operation when CPU is halted */
\r
6204 /* SYSCTL_PERIHALT_CTL[HALT_EUA2] Bits */
\r
6205 #define SYSCTL_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /**< HALT_eUA2 Bit Offset */
\r
6206 #define SYSCTL_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /**< Freezes IP operation when CPU is halted */
\r
6207 /* SYSCTL_PERIHALT_CTL[HALT_EUA3] Bits */
\r
6208 #define SYSCTL_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /**< HALT_eUA3 Bit Offset */
\r
6209 #define SYSCTL_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /**< Freezes IP operation when CPU is halted */
\r
6210 /* SYSCTL_PERIHALT_CTL[HALT_EUB0] Bits */
\r
6211 #define SYSCTL_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /**< HALT_eUB0 Bit Offset */
\r
6212 #define SYSCTL_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /**< Freezes IP operation when CPU is halted */
\r
6213 /* SYSCTL_PERIHALT_CTL[HALT_EUB1] Bits */
\r
6214 #define SYSCTL_PERIHALT_CTL_HALT_EUB1_OFS (10) /**< HALT_eUB1 Bit Offset */
\r
6215 #define SYSCTL_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /**< Freezes IP operation when CPU is halted */
\r
6216 /* SYSCTL_PERIHALT_CTL[HALT_EUB2] Bits */
\r
6217 #define SYSCTL_PERIHALT_CTL_HALT_EUB2_OFS (11) /**< HALT_eUB2 Bit Offset */
\r
6218 #define SYSCTL_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /**< Freezes IP operation when CPU is halted */
\r
6219 /* SYSCTL_PERIHALT_CTL[HALT_EUB3] Bits */
\r
6220 #define SYSCTL_PERIHALT_CTL_HALT_EUB3_OFS (12) /**< HALT_eUB3 Bit Offset */
\r
6221 #define SYSCTL_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /**< Freezes IP operation when CPU is halted */
\r
6222 /* SYSCTL_PERIHALT_CTL[HALT_ADC] Bits */
\r
6223 #define SYSCTL_PERIHALT_CTL_HALT_ADC_OFS (13) /**< HALT_ADC Bit Offset */
\r
6224 #define SYSCTL_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /**< Freezes IP operation when CPU is halted */
\r
6225 /* SYSCTL_PERIHALT_CTL[HALT_WDT] Bits */
\r
6226 #define SYSCTL_PERIHALT_CTL_HALT_WDT_OFS (14) /**< HALT_WDT Bit Offset */
\r
6227 #define SYSCTL_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /**< Freezes IP operation when CPU is halted */
\r
6228 /* SYSCTL_PERIHALT_CTL[HALT_DMA] Bits */
\r
6229 #define SYSCTL_PERIHALT_CTL_HALT_DMA_OFS (15) /**< HALT_DMA Bit Offset */
\r
6230 #define SYSCTL_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /**< Freezes IP operation when CPU is halted */
\r
6231 /* SYSCTL_SRAM_BANKEN[BNK0_EN] Bits */
\r
6232 #define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /**< BNK0_EN Bit Offset */
\r
6233 #define SYSCTL_SRAM_BANKEN_BNK0_EN ((uint32_t)0x00000001) /**< SRAM Bank0 enable */
\r
6234 /* SYSCTL_SRAM_BANKEN[BNK1_EN] Bits */
\r
6235 #define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /**< BNK1_EN Bit Offset */
\r
6236 #define SYSCTL_SRAM_BANKEN_BNK1_EN ((uint32_t)0x00000002) /**< SRAM Bank1 enable */
\r
6237 /* SYSCTL_SRAM_BANKEN[BNK2_EN] Bits */
\r
6238 #define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /**< BNK2_EN Bit Offset */
\r
6239 #define SYSCTL_SRAM_BANKEN_BNK2_EN ((uint32_t)0x00000004) /**< SRAM Bank1 enable */
\r
6240 /* SYSCTL_SRAM_BANKEN[BNK3_EN] Bits */
\r
6241 #define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /**< BNK3_EN Bit Offset */
\r
6242 #define SYSCTL_SRAM_BANKEN_BNK3_EN ((uint32_t)0x00000008) /**< SRAM Bank1 enable */
\r
6243 /* SYSCTL_SRAM_BANKEN[BNK4_EN] Bits */
\r
6244 #define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /**< BNK4_EN Bit Offset */
\r
6245 #define SYSCTL_SRAM_BANKEN_BNK4_EN ((uint32_t)0x00000010) /**< SRAM Bank1 enable */
\r
6246 /* SYSCTL_SRAM_BANKEN[BNK5_EN] Bits */
\r
6247 #define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /**< BNK5_EN Bit Offset */
\r
6248 #define SYSCTL_SRAM_BANKEN_BNK5_EN ((uint32_t)0x00000020) /**< SRAM Bank1 enable */
\r
6249 /* SYSCTL_SRAM_BANKEN[BNK6_EN] Bits */
\r
6250 #define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /**< BNK6_EN Bit Offset */
\r
6251 #define SYSCTL_SRAM_BANKEN_BNK6_EN ((uint32_t)0x00000040) /**< SRAM Bank1 enable */
\r
6252 /* SYSCTL_SRAM_BANKEN[BNK7_EN] Bits */
\r
6253 #define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /**< BNK7_EN Bit Offset */
\r
6254 #define SYSCTL_SRAM_BANKEN_BNK7_EN ((uint32_t)0x00000080) /**< SRAM Bank1 enable */
\r
6255 /* SYSCTL_SRAM_BANKEN[SRAM_RDY] Bits */
\r
6256 #define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /**< SRAM_RDY Bit Offset */
\r
6257 #define SYSCTL_SRAM_BANKEN_SRAM_RDY ((uint32_t)0x00010000) /**< SRAM ready */
\r
6258 /* SYSCTL_SRAM_BANKRET[BNK0_RET] Bits */
\r
6259 #define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /**< BNK0_RET Bit Offset */
\r
6260 #define SYSCTL_SRAM_BANKRET_BNK0_RET ((uint32_t)0x00000001) /**< Bank0 retention */
\r
6261 /* SYSCTL_SRAM_BANKRET[BNK1_RET] Bits */
\r
6262 #define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /**< BNK1_RET Bit Offset */
\r
6263 #define SYSCTL_SRAM_BANKRET_BNK1_RET ((uint32_t)0x00000002) /**< Bank1 retention */
\r
6264 /* SYSCTL_SRAM_BANKRET[BNK2_RET] Bits */
\r
6265 #define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /**< BNK2_RET Bit Offset */
\r
6266 #define SYSCTL_SRAM_BANKRET_BNK2_RET ((uint32_t)0x00000004) /**< Bank2 retention */
\r
6267 /* SYSCTL_SRAM_BANKRET[BNK3_RET] Bits */
\r
6268 #define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /**< BNK3_RET Bit Offset */
\r
6269 #define SYSCTL_SRAM_BANKRET_BNK3_RET ((uint32_t)0x00000008) /**< Bank3 retention */
\r
6270 /* SYSCTL_SRAM_BANKRET[BNK4_RET] Bits */
\r
6271 #define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /**< BNK4_RET Bit Offset */
\r
6272 #define SYSCTL_SRAM_BANKRET_BNK4_RET ((uint32_t)0x00000010) /**< Bank4 retention */
\r
6273 /* SYSCTL_SRAM_BANKRET[BNK5_RET] Bits */
\r
6274 #define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /**< BNK5_RET Bit Offset */
\r
6275 #define SYSCTL_SRAM_BANKRET_BNK5_RET ((uint32_t)0x00000020) /**< Bank5 retention */
\r
6276 /* SYSCTL_SRAM_BANKRET[BNK6_RET] Bits */
\r
6277 #define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /**< BNK6_RET Bit Offset */
\r
6278 #define SYSCTL_SRAM_BANKRET_BNK6_RET ((uint32_t)0x00000040) /**< Bank6 retention */
\r
6279 /* SYSCTL_SRAM_BANKRET[BNK7_RET] Bits */
\r
6280 #define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /**< BNK7_RET Bit Offset */
\r
6281 #define SYSCTL_SRAM_BANKRET_BNK7_RET ((uint32_t)0x00000080) /**< Bank7 retention */
\r
6282 /* SYSCTL_SRAM_BANKRET[SRAM_RDY] Bits */
\r
6283 #define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /**< SRAM_RDY Bit Offset */
\r
6284 #define SYSCTL_SRAM_BANKRET_SRAM_RDY ((uint32_t)0x00010000) /**< SRAM ready */
\r
6285 /* SYSCTL_DIO_GLTFLT_CTL[GLTCH_EN] Bits */
\r
6286 #define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /**< GLTCH_EN Bit Offset */
\r
6287 #define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /**< Glitch filter enable */
\r
6288 /* SYSCTL_SECDATA_UNLOCK[UNLKEY] Bits */
\r
6289 #define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /**< UNLKEY Bit Offset */
\r
6290 #define SYSCTL_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /**< UNLKEY Bit Mask */
\r
6291 /* SYSCTL_CSYS_MASTER_UNLOCK[UNLKEY] Bits */
\r
6292 #define SYSCTL_CSYS_MASTER_UNLOCK_UNLKEY_OFS ( 0) /**< UNLKEY Bit Offset */
\r
6293 #define SYSCTL_CSYS_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /**< UNLKEY Bit Mask */
\r
6294 /* SYSCTL_BOOT_CTL[BOOT_SECEN] Bits */
\r
6295 #define SYSCTL_BOOT_CTL_BOOT_SECEN_OFS ( 0) /**< BOOT_SECEN Bit Offset */
\r
6296 #define SYSCTL_BOOT_CTL_BOOT_SECEN ((uint32_t)0x00000001)
\r
6297 /* SYSCTL_BOOT_CTL[BOOTACT] Bits */
\r
6298 #define SYSCTL_BOOT_CTL_BOOTACT_OFS ( 1) /**< BOOTACT Bit Offset */
\r
6299 #define SYSCTL_BOOT_CTL_BOOTACT ((uint32_t)0x00000002)
\r
6300 /* SYSCTL_BOOT_CTL[BOOTCMPL] Bits */
\r
6301 #define SYSCTL_BOOT_CTL_BOOTCMPL_OFS ( 2) /**< BOOTCMPL Bit Offset */
\r
6302 #define SYSCTL_BOOT_CTL_BOOTCMPL ((uint32_t)0x00000004)
\r
6303 /* SYSCTL_BOOT_CTL[BOOT_REMAPEN] Bits */
\r
6304 #define SYSCTL_BOOT_CTL_BOOT_REMAPEN_OFS ( 3) /**< BOOT_REMAPEN Bit Offset */
\r
6305 #define SYSCTL_BOOT_CTL_BOOT_REMAPEN ((uint32_t)0x00000008)
\r
6306 /* SYSCTL_BOOT_CTL[ENGR_DIS] Bits */
\r
6307 #define SYSCTL_BOOT_CTL_ENGR_DIS_OFS ( 4) /**< ENGR_DIS Bit Offset */
\r
6308 #define SYSCTL_BOOT_CTL_ENGR_DIS ((uint32_t)0x00000010)
\r
6309 /* SYSCTL_BOOT_CTL[WKEY] Bits */
\r
6310 #define SYSCTL_BOOT_CTL_WKEY_OFS ( 8) /**< WKEY Bit Offset */
\r
6311 #define SYSCTL_BOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /**< WKEY Bit Mask */
\r
6312 /* SYSCTL_SEC_CTL[JTAG_SWD_LOCK_EN] Bits */
\r
6313 #define SYSCTL_SEC_CTL_JTAG_SWD_LOCK_EN_OFS ( 0) /**< JTAG_SWD_LOCK_EN Bit Offset */
\r
6314 #define SYSCTL_SEC_CTL_JTAG_SWD_LOCK_EN ((uint32_t)0x00000001)
\r
6315 /* SYSCTL_SEC_CTL[IP_PROT_EN] Bits */
\r
6316 #define SYSCTL_SEC_CTL_IP_PROT_EN_OFS ( 1) /**< IP_PROT_EN Bit Offset */
\r
6317 #define SYSCTL_SEC_CTL_IP_PROT_EN ((uint32_t)0x00000002)
\r
6318 /* SYSCTL_SEC_CTL[DLOCK_EN] Bits */
\r
6319 #define SYSCTL_SEC_CTL_DLOCK_EN_OFS ( 2) /**< DLOCK_EN Bit Offset */
\r
6320 #define SYSCTL_SEC_CTL_DLOCK_EN ((uint32_t)0x00000004)
\r
6321 /* SYSCTL_SEC_CTL[SBUS_IF_DIS] Bits */
\r
6322 #define SYSCTL_SEC_CTL_SBUS_IF_DIS_OFS ( 3) /**< SBUS_IF_DIS Bit Offset */
\r
6323 #define SYSCTL_SEC_CTL_SBUS_IF_DIS ((uint32_t)0x00000008)
\r
6324 /* SYSCTL_SEC_CTL[SEC_ZONE0_EN] Bits */
\r
6325 #define SYSCTL_SEC_CTL_SEC_ZONE0_EN_OFS ( 8) /**< SEC_ZONE0_EN Bit Offset */
\r
6326 #define SYSCTL_SEC_CTL_SEC_ZONE0_EN ((uint32_t)0x00000100)
\r
6327 /* SYSCTL_SEC_CTL[SEC_ZONE1_EN] Bits */
\r
6328 #define SYSCTL_SEC_CTL_SEC_ZONE1_EN_OFS ( 9) /**< SEC_ZONE1_EN Bit Offset */
\r
6329 #define SYSCTL_SEC_CTL_SEC_ZONE1_EN ((uint32_t)0x00000200)
\r
6330 /* SYSCTL_SEC_CTL[SEC_ZONE2_EN] Bits */
\r
6331 #define SYSCTL_SEC_CTL_SEC_ZONE2_EN_OFS (10) /**< SEC_ZONE2_EN Bit Offset */
\r
6332 #define SYSCTL_SEC_CTL_SEC_ZONE2_EN ((uint32_t)0x00000400)
\r
6333 /* SYSCTL_SEC_CTL[SEC_ZONE3_EN] Bits */
\r
6334 #define SYSCTL_SEC_CTL_SEC_ZONE3_EN_OFS (11) /**< SEC_ZONE3_EN Bit Offset */
\r
6335 #define SYSCTL_SEC_CTL_SEC_ZONE3_EN ((uint32_t)0x00000800)
\r
6336 /* SYSCTL_SEC_CTL[SEC_ZONE0_DATAEN] Bits */
\r
6337 #define SYSCTL_SEC_CTL_SEC_ZONE0_DATAEN_OFS (16) /**< SEC_ZONE0_DATAEN Bit Offset */
\r
6338 #define SYSCTL_SEC_CTL_SEC_ZONE0_DATAEN ((uint32_t)0x00010000)
\r
6339 /* SYSCTL_SEC_CTL[SEC_ZONE1_DATAEN] Bits */
\r
6340 #define SYSCTL_SEC_CTL_SEC_ZONE1_DATAEN_OFS (17) /**< SEC_ZONE1_DATAEN Bit Offset */
\r
6341 #define SYSCTL_SEC_CTL_SEC_ZONE1_DATAEN ((uint32_t)0x00020000)
\r
6342 /* SYSCTL_SEC_CTL[SEC_ZONE2_DATAEN] Bits */
\r
6343 #define SYSCTL_SEC_CTL_SEC_ZONE2_DATAEN_OFS (18) /**< SEC_ZONE2_DATAEN Bit Offset */
\r
6344 #define SYSCTL_SEC_CTL_SEC_ZONE2_DATAEN ((uint32_t)0x00040000)
\r
6345 /* SYSCTL_SEC_CTL[SEC_ZONE3_DATAEN] Bits */
\r
6346 #define SYSCTL_SEC_CTL_SEC_ZONE3_DATAEN_OFS (19) /**< SEC_ZONE3_DATAEN Bit Offset */
\r
6347 #define SYSCTL_SEC_CTL_SEC_ZONE3_DATAEN ((uint32_t)0x00080000)
\r
6348 /* SYSCTL_SEC_STARTADDR0[START_ADDR] Bits */
\r
6349 #define SYSCTL_SEC_STARTADDR0_START_ADDR_OFS ( 0) /**< START_ADDR Bit Offset */
\r
6350 #define SYSCTL_SEC_STARTADDR0_START_ADDR_MASK ((uint32_t)0x0003FFFF) /**< START_ADDR Bit Mask */
\r
6351 /* SYSCTL_SEC_STARTADDR1[START_ADDR] Bits */
\r
6352 #define SYSCTL_SEC_STARTADDR1_START_ADDR_OFS ( 0) /**< START_ADDR Bit Offset */
\r
6353 #define SYSCTL_SEC_STARTADDR1_START_ADDR_MASK ((uint32_t)0x0003FFFF) /**< START_ADDR Bit Mask */
\r
6354 /* SYSCTL_SEC_STARTADDR2[START_ADDR] Bits */
\r
6355 #define SYSCTL_SEC_STARTADDR2_START_ADDR_OFS ( 0) /**< START_ADDR Bit Offset */
\r
6356 #define SYSCTL_SEC_STARTADDR2_START_ADDR_MASK ((uint32_t)0x0003FFFF) /**< START_ADDR Bit Mask */
\r
6357 /* SYSCTL_SEC_STARTADDR3[START_ADDR] Bits */
\r
6358 #define SYSCTL_SEC_STARTADDR3_START_ADDR_OFS ( 0) /**< START_ADDR Bit Offset */
\r
6359 #define SYSCTL_SEC_STARTADDR3_START_ADDR_MASK ((uint32_t)0x0003FFFF) /**< START_ADDR Bit Mask */
\r
6360 /* SYSCTL_SEC_SIZE0[SIZE] Bits */
\r
6361 #define SYSCTL_SEC_SIZE0_SIZE_OFS ( 0) /**< SIZE Bit Offset */
\r
6362 #define SYSCTL_SEC_SIZE0_SIZE_MASK ((uint32_t)0x0003FFFF) /**< SIZE Bit Mask */
\r
6363 /* SYSCTL_SEC_SIZE1[SIZE] Bits */
\r
6364 #define SYSCTL_SEC_SIZE1_SIZE_OFS ( 0) /**< SIZE Bit Offset */
\r
6365 #define SYSCTL_SEC_SIZE1_SIZE_MASK ((uint32_t)0x0003FFFF) /**< SIZE Bit Mask */
\r
6366 /* SYSCTL_SEC_SIZE2[SIZE] Bits */
\r
6367 #define SYSCTL_SEC_SIZE2_SIZE_OFS ( 0) /**< SIZE Bit Offset */
\r
6368 #define SYSCTL_SEC_SIZE2_SIZE_MASK ((uint32_t)0x0003FFFF) /**< SIZE Bit Mask */
\r
6369 /* SYSCTL_SEC_SIZE3[SIZE] Bits */
\r
6370 #define SYSCTL_SEC_SIZE3_SIZE_OFS ( 0) /**< SIZE Bit Offset */
\r
6371 #define SYSCTL_SEC_SIZE3_SIZE_MASK ((uint32_t)0x0003FFFF) /**< SIZE Bit Mask */
\r
6372 /* SYSCTL_ETW_CTL[ETSEL] Bits */
\r
6373 #define SYSCTL_ETW_CTL_ETSEL_OFS ( 0) /**< ETSEL Bit Offset */
\r
6374 #define SYSCTL_ETW_CTL_ETSEL ((uint32_t)0x00000001)
\r
6375 /* SYSCTL_ETW_CTL[DBGEN] Bits */
\r
6376 #define SYSCTL_ETW_CTL_DBGEN_OFS ( 1) /**< DBGEN Bit Offset */
\r
6377 #define SYSCTL_ETW_CTL_DBGEN ((uint32_t)0x00000002)
\r
6378 /* SYSCTL_ETW_CTL[WKEY] Bits */
\r
6379 #define SYSCTL_ETW_CTL_WKEY_OFS ( 8) /**< WKEY Bit Offset */
\r
6380 #define SYSCTL_ETW_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /**< WKEY Bit Mask */
\r
6381 /* SYSCTL_FLASH_SIZECFG[SIZE] Bits */
\r
6382 #define SYSCTL_FLASH_SIZECFG_SIZE_OFS ( 0) /**< SIZE Bit Offset */
\r
6383 #define SYSCTL_FLASH_SIZECFG_SIZE_MASK ((uint32_t)0x0007FFFF) /**< SIZE Bit Mask */
\r
6384 /* SYSCTL_SRAM_SIZECFG[SIZE] Bits */
\r
6385 #define SYSCTL_SRAM_SIZECFG_SIZE_OFS ( 0) /**< SIZE Bit Offset */
\r
6386 #define SYSCTL_SRAM_SIZECFG_SIZE_MASK ((uint32_t)0x0001FFFF) /**< SIZE Bit Mask */
\r
6387 /* SYSCTL_SRAM_NUMBANK[NUM_BANK] Bits */
\r
6388 #define SYSCTL_SRAM_NUMBANK_NUM_BANK_OFS ( 0) /**< NUM_BANK Bit Offset */
\r
6389 #define SYSCTL_SRAM_NUMBANK_NUM_BANK_MASK ((uint32_t)0x0000001F) /**< NUM_BANK Bit Mask */
\r
6390 /* SYSCTL_TIMER_CFG[T0_EN] Bits */
\r
6391 #define SYSCTL_TIMER_CFG_T0_EN_OFS ( 0) /**< T0_EN Bit Offset */
\r
6392 #define SYSCTL_TIMER_CFG_T0_EN ((uint32_t)0x00000001) /**< Enable bit for Timer0 */
\r
6393 /* SYSCTL_TIMER_CFG[T1_EN] Bits */
\r
6394 #define SYSCTL_TIMER_CFG_T1_EN_OFS ( 1) /**< T1_EN Bit Offset */
\r
6395 #define SYSCTL_TIMER_CFG_T1_EN ((uint32_t)0x00000002) /**< Enable bit for Timer1 */
\r
6396 /* SYSCTL_TIMER_CFG[T2_EN] Bits */
\r
6397 #define SYSCTL_TIMER_CFG_T2_EN_OFS ( 2) /**< T2_EN Bit Offset */
\r
6398 #define SYSCTL_TIMER_CFG_T2_EN ((uint32_t)0x00000004) /**< Enable bit for Timer2 */
\r
6399 /* SYSCTL_TIMER_CFG[T3_EN] Bits */
\r
6400 #define SYSCTL_TIMER_CFG_T3_EN_OFS ( 3) /**< T3_EN Bit Offset */
\r
6401 #define SYSCTL_TIMER_CFG_T3_EN ((uint32_t)0x00000008) /**< Enable bit for Timer3 */
\r
6402 /* SYSCTL_TIMER_CFG[T32_EN] Bits */
\r
6403 #define SYSCTL_TIMER_CFG_T32_EN_OFS (16) /**< T32_EN Bit Offset */
\r
6404 #define SYSCTL_TIMER_CFG_T32_EN ((uint32_t)0x00010000) /**< Enable bit for Timer32 */
\r
6405 /* SYSCTL_EUSCI_CFG[EUA0_EN] Bits */
\r
6406 #define SYSCTL_EUSCI_CFG_EUA0_EN_OFS ( 0) /**< eUA0_EN Bit Offset */
\r
6407 #define SYSCTL_EUSCI_CFG_EUA0_EN ((uint32_t)0x00000001) /**< Enable bit for eUSCI_A0 */
\r
6408 /* SYSCTL_EUSCI_CFG[EUA1_EN] Bits */
\r
6409 #define SYSCTL_EUSCI_CFG_EUA1_EN_OFS ( 1) /**< eUA1_EN Bit Offset */
\r
6410 #define SYSCTL_EUSCI_CFG_EUA1_EN ((uint32_t)0x00000002) /**< Enable bit for eUSCI_A1 */
\r
6411 /* SYSCTL_EUSCI_CFG[EUA2_EN] Bits */
\r
6412 #define SYSCTL_EUSCI_CFG_EUA2_EN_OFS ( 2) /**< eUA2_EN Bit Offset */
\r
6413 #define SYSCTL_EUSCI_CFG_EUA2_EN ((uint32_t)0x00000004) /**< Enable bit for eUSCI_A2 */
\r
6414 /* SYSCTL_EUSCI_CFG[EUA3_EN] Bits */
\r
6415 #define SYSCTL_EUSCI_CFG_EUA3_EN_OFS ( 3) /**< eUA3_EN Bit Offset */
\r
6416 #define SYSCTL_EUSCI_CFG_EUA3_EN ((uint32_t)0x00000008) /**< Enable bit for eUSCI_A3 */
\r
6417 /* SYSCTL_EUSCI_CFG[EUB0_EN] Bits */
\r
6418 #define SYSCTL_EUSCI_CFG_EUB0_EN_OFS (16) /**< eUB0_EN Bit Offset */
\r
6419 #define SYSCTL_EUSCI_CFG_EUB0_EN ((uint32_t)0x00010000) /**< Enable bit for eUSCI_B0 */
\r
6420 /* SYSCTL_EUSCI_CFG[EUB1_EN] Bits */
\r
6421 #define SYSCTL_EUSCI_CFG_EUB1_EN_OFS (17) /**< eUB1_EN Bit Offset */
\r
6422 #define SYSCTL_EUSCI_CFG_EUB1_EN ((uint32_t)0x00020000) /**< Enable bit for eUSCI_B1 */
\r
6423 /* SYSCTL_EUSCI_CFG[EUB2_EN] Bits */
\r
6424 #define SYSCTL_EUSCI_CFG_EUB2_EN_OFS (18) /**< eUB2_EN Bit Offset */
\r
6425 #define SYSCTL_EUSCI_CFG_EUB2_EN ((uint32_t)0x00040000) /**< Enable bit for eUSCI_B2 */
\r
6426 /* SYSCTL_EUSCI_CFG[EUB3_EN] Bits */
\r
6427 #define SYSCTL_EUSCI_CFG_EUB3_EN_OFS (19) /**< eUB3_EN Bit Offset */
\r
6428 #define SYSCTL_EUSCI_CFG_EUB3_EN ((uint32_t)0x00080000) /**< Enable bit for eUSCI_B3 */
\r
6429 /* SYSCTL_ADC_CFG[ADC_EN] Bits */
\r
6430 #define SYSCTL_ADC_CFG_ADC_EN_OFS ( 0) /**< ADC_EN Bit Offset */
\r
6431 #define SYSCTL_ADC_CFG_ADC_EN ((uint32_t)0x00000001) /**< Enable bit for ADC */
\r
6432 /* SYSCTL_XTAL_CFG[LFXT_EN] Bits */
\r
6433 #define SYSCTL_XTAL_CFG_LFXT_EN_OFS ( 0) /**< LFXT_EN Bit Offset */
\r
6434 #define SYSCTL_XTAL_CFG_LFXT_EN ((uint32_t)0x00000001) /**< Enable bit for LFXT */
\r
6435 /* SYSCTL_XTAL_CFG[HFXT_EN] Bits */
\r
6436 #define SYSCTL_XTAL_CFG_HFXT_EN_OFS ( 1) /**< HFXT_EN Bit Offset */
\r
6437 #define SYSCTL_XTAL_CFG_HFXT_EN ((uint32_t)0x00000002) /**< Enable bit for HFXT */
\r
6438 /* SYSCTL_XTAL_CFG[HFXT2_EN] Bits */
\r
6439 #define SYSCTL_XTAL_CFG_HFXT2_EN_OFS ( 2) /**< HFXT2_EN Bit Offset */
\r
6440 #define SYSCTL_XTAL_CFG_HFXT2_EN ((uint32_t)0x00000004) /**< Enable bit for HFXT2 */
\r
6441 /* SYSCTL_BOC_CFG[BOC_CTL] Bits */
\r
6442 #define SYSCTL_BOC_CFG_BOC_CTL_OFS ( 0) /**< BOC_CTL Bit Offset */
\r
6443 #define SYSCTL_BOC_CFG_BOC_CTL_MASK ((uint32_t)0x00000007) /**< BOC_CTL Bit Mask */
\r
6444 #define SYSCTL_BOC_CFG_BOC_CTL0 ((uint32_t)0x00000001) /**< BOC_CTL Bit 0 */
\r
6445 #define SYSCTL_BOC_CFG_BOC_CTL1 ((uint32_t)0x00000002) /**< BOC_CTL Bit 1 */
\r
6446 #define SYSCTL_BOC_CFG_BOC_CTL2 ((uint32_t)0x00000004) /**< BOC_CTL Bit 2 */
\r
6447 #define SYSCTL_BOC_CFG_BOC_CTL_0 ((uint32_t)0x00000000) /**< 100pin package */
\r
6448 #define SYSCTL_BOC_CFG_BOC_CTL_1 ((uint32_t)0x00000001) /**< 80pin package */
\r
6449 #define SYSCTL_BOC_CFG_BOC_CTL_2 ((uint32_t)0x00000002) /**< 64pin package */
\r
6450 #define SYSCTL_BOC_CFG_BOC_CTL_3 ((uint32_t)0x00000003) /**< 64pin package */
\r
6451 #define SYSCTL_BOC_CFG_BOC_CTL__PIN_100 ((uint32_t)0x00000000) /**< 100pin package */
\r
6452 #define SYSCTL_BOC_CFG_BOC_CTL__PIN_80 ((uint32_t)0x00000001) /**< 80pin package */
\r
6453 #define SYSCTL_BOC_CFG_BOC_CTL__PIN_64 ((uint32_t)0x00000002) /**< 64pin package */
\r
6455 #define SYSCTL_BOC_CFG_BOC_CTL_4 ((uint32_t)0x00000004) /**< Reserved for future use */
\r
6456 #define SYSCTL_BOC_CFG_BOC_CTL_5 ((uint32_t)0x00000005) /**< Reserved for future use */
\r
6457 #define SYSCTL_BOC_CFG_BOC_CTL_6 ((uint32_t)0x00000006) /**< Reserved for future use */
\r
6458 #define SYSCTL_BOC_CFG_BOC_CTL_7 ((uint32_t)0x00000007) /**< Reserved for future use */
\r
6459 /* SYSCTL_MASTER_UNLOCK[UNLKEY] Bits */
\r
6460 #define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /**< UNLKEY Bit Offset */
\r
6461 #define SYSCTL_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /**< UNLKEY Bit Mask */
\r
6462 /* SYSCTL_RESET_REQ[POR] Bits */
\r
6463 #define SYSCTL_RESET_REQ_POR_OFS ( 0) /**< POR Bit Offset */
\r
6464 #define SYSCTL_RESET_REQ_POR ((uint32_t)0x00000001) /**< Generate POR */
\r
6465 /* SYSCTL_RESET_REQ[REBOOT] Bits */
\r
6466 #define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /**< REBOOT Bit Offset */
\r
6467 #define SYSCTL_RESET_REQ_REBOOT ((uint32_t)0x00000002) /**< Generate Reboot_Reset */
\r
6468 /* SYSCTL_RESET_REQ[WKEY] Bits */
\r
6469 #define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /**< WKEY Bit Offset */
\r
6470 #define SYSCTL_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /**< WKEY Bit Mask */
\r
6471 /* SYSCTL_RESET_STATOVER[SOFT] Bits */
\r
6472 #define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /**< SOFT Bit Offset */
\r
6473 #define SYSCTL_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /**< Indicates if SOFT Reset is active */
\r
6474 /* SYSCTL_RESET_STATOVER[HARD] Bits */
\r
6475 #define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /**< HARD Bit Offset */
\r
6476 #define SYSCTL_RESET_STATOVER_HARD ((uint32_t)0x00000002) /**< Indicates if HARD Reset is active */
\r
6477 /* SYSCTL_RESET_STATOVER[REBOOT] Bits */
\r
6478 #define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /**< REBOOT Bit Offset */
\r
6479 #define SYSCTL_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /**< Indicates if Reboot Reset is active */
\r
6480 /* SYSCTL_RESET_STATOVER[SOFT_OVER] Bits */
\r
6481 #define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /**< SOFT_OVER Bit Offset */
\r
6482 #define SYSCTL_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /**< SOFT_Reset overwrite request */
\r
6483 /* SYSCTL_RESET_STATOVER[HARD_OVER] Bits */
\r
6484 #define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /**< HARD_OVER Bit Offset */
\r
6485 #define SYSCTL_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /**< HARD_Reset overwrite request */
\r
6486 /* SYSCTL_RESET_STATOVER[RBT_OVER] Bits */
\r
6487 #define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /**< RBT_OVER Bit Offset */
\r
6488 #define SYSCTL_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /**< Reboot Reset overwrite request */
\r
6489 /* SYSCTL_SYSTEM_STAT[DBG_SEC_ACT] Bits */
\r
6490 #define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS ( 3) /**< DBG_SEC_ACT Bit Offset */
\r
6491 #define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT ((uint32_t)0x00000008) /**< Debug Security active */
\r
6492 /* SYSCTL_SYSTEM_STAT[JTAG_SWD_LOCK_ACT] Bits */
\r
6493 #define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS ( 4) /**< JTAG_SWD_LOCK_ACT Bit Offset */
\r
6494 #define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT ((uint32_t)0x00000010) /**< Indicates if JTAG and SWD Lock is active */
\r
6495 /* SYSCTL_SYSTEM_STAT[IP_PROT_ACT] Bits */
\r
6496 #define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS ( 5) /**< IP_PROT_ACT Bit Offset */
\r
6497 #define SYSCTL_SYSTEM_STAT_IP_PROT_ACT ((uint32_t)0x00000020) /**< Indicates if IP protection is active */
\r
6499 /* Pre-defined bitfield values */
\r
6500 #define SYSCTL_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /* Key value to enable writes to bit 0 */
\r
6504 /******************************************************************************
\r
6506 ******************************************************************************/
\r
6508 /******************************************************************************
\r
6510 ******************************************************************************/
\r
6511 /* TIMER32_CONTROL[ONESHOT] Bits */
\r
6512 #define TIMER32_CONTROL_ONESHOT_OFS ( 0) /**< ONESHOT Bit Offset */
\r
6513 #define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /**< Selects one-shot or wrapping counter mode */
\r
6514 /* TIMER32_CONTROL[SIZE] Bits */
\r
6515 #define TIMER32_CONTROL_SIZE_OFS ( 1) /**< SIZE Bit Offset */
\r
6516 #define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /**< Selects 16 or 32 bit counter operation */
\r
6517 /* TIMER32_CONTROL[PRESCALE] Bits */
\r
6518 #define TIMER32_CONTROL_PRESCALE_OFS ( 2) /**< PRESCALE Bit Offset */
\r
6519 #define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /**< PRESCALE Bit Mask */
\r
6520 #define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /**< PRESCALE Bit 0 */
\r
6521 #define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /**< PRESCALE Bit 1 */
\r
6522 #define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /**< 0 stages of prescale, clock is divided by 1 */
\r
6523 #define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /**< 4 stages of prescale, clock is divided by 16 */
\r
6524 #define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /**< 8 stages of prescale, clock is divided by 256 */
\r
6525 /* TIMER32_CONTROL[IE] Bits */
\r
6526 #define TIMER32_CONTROL_IE_OFS ( 5) /**< IE Bit Offset */
\r
6527 #define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /**< Interrupt enable bit */
\r
6528 /* TIMER32_CONTROL[MODE] Bits */
\r
6529 #define TIMER32_CONTROL_MODE_OFS ( 6) /**< MODE Bit Offset */
\r
6530 #define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /**< Mode bit */
\r
6531 /* TIMER32_CONTROL[ENABLE] Bits */
\r
6532 #define TIMER32_CONTROL_ENABLE_OFS ( 7) /**< ENABLE Bit Offset */
\r
6533 #define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080)
\r
6534 /* TIMER32_RIS[RAW_IFG] Bits */
\r
6535 #define TIMER32_RIS_RAW_IFG_OFS ( 0) /**< RAW_IFG Bit Offset */
\r
6536 #define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /**< Raw interrupt status */
\r
6537 /* TIMER32_MIS[IFG] Bits */
\r
6538 #define TIMER32_MIS_IFG_OFS ( 0) /**< IFG Bit Offset */
\r
6539 #define TIMER32_MIS_IFG ((uint32_t)0x00000001) /**< Enabled interrupt status */
\r
6543 /******************************************************************************
\r
6545 ******************************************************************************/
\r
6546 /* TIMER_A_CTL[IFG] Bits */
\r
6547 #define TIMER_A_CTL_IFG_OFS ( 0) /**< TAIFG Bit Offset */
\r
6548 #define TIMER_A_CTL_IFG ((uint16_t)0x0001) /**< TimerA interrupt flag */
\r
6549 /* TIMER_A_CTL[IE] Bits */
\r
6550 #define TIMER_A_CTL_IE_OFS ( 1) /**< TAIE Bit Offset */
\r
6551 #define TIMER_A_CTL_IE ((uint16_t)0x0002) /**< TimerA interrupt enable */
\r
6552 /* TIMER_A_CTL[CLR] Bits */
\r
6553 #define TIMER_A_CTL_CLR_OFS ( 2) /**< TACLR Bit Offset */
\r
6554 #define TIMER_A_CTL_CLR ((uint16_t)0x0004) /**< TimerA clear */
\r
6555 /* TIMER_A_CTL[MC] Bits */
\r
6556 #define TIMER_A_CTL_MC_OFS ( 4) /**< MC Bit Offset */
\r
6557 #define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /**< MC Bit Mask */
\r
6558 #define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /**< MC Bit 0 */
\r
6559 #define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /**< MC Bit 1 */
\r
6560 #define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /**< Stop mode: Timer is halted */
\r
6561 #define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /**< Up mode: Timer counts up to TAxCCR0 */
\r
6562 #define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /**< Continuous mode: Timer counts up to 0FFFFh */
\r
6563 #define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /**< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
\r
6564 #define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /**< Stop mode: Timer is halted */
\r
6565 #define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /**< Up mode: Timer counts up to TAxCCR0 */
\r
6566 #define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /**< Continuous mode: Timer counts up to 0FFFFh */
\r
6567 #define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /**< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
\r
6568 /* TIMER_A_CTL[ID] Bits */
\r
6569 #define TIMER_A_CTL_ID_OFS ( 6) /**< ID Bit Offset */
\r
6570 #define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /**< ID Bit Mask */
\r
6571 #define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /**< ID Bit 0 */
\r
6572 #define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /**< ID Bit 1 */
\r
6573 #define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /**< /1 */
\r
6574 #define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /**< /2 */
\r
6575 #define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /**< /4 */
\r
6576 #define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /**< /8 */
\r
6577 #define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /**< /1 */
\r
6578 #define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /**< /2 */
\r
6579 #define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /**< /4 */
\r
6580 #define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /**< /8 */
\r
6581 /* TIMER_A_CTL[SSEL] Bits */
\r
6582 #define TIMER_A_CTL_SSEL_OFS ( 8) /**< TASSEL Bit Offset */
\r
6583 #define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /**< TASSEL Bit Mask */
\r
6584 #define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /**< SSEL Bit 0 */
\r
6585 #define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /**< SSEL Bit 1 */
\r
6586 #define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /**< TAxCLK */
\r
6587 #define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /**< ACLK */
\r
6588 #define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /**< SMCLK */
\r
6589 #define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /**< INCLK */
\r
6590 #define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /**< TAxCLK */
\r
6591 #define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /**< ACLK */
\r
6592 #define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /**< SMCLK */
\r
6593 #define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /**< INCLK */
\r
6594 /* TIMER_A_CCTLN[CCIFG] Bits */
\r
6595 #define TIMER_A_CCTLN_CCIFG_OFS ( 0) /**< CCIFG Bit Offset */
\r
6596 #define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /**< Capture/compare interrupt flag */
\r
6597 /* TIMER_A_CCTLN[COV] Bits */
\r
6598 #define TIMER_A_CCTLN_COV_OFS ( 1) /**< COV Bit Offset */
\r
6599 #define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /**< Capture overflow */
\r
6600 /* TIMER_A_CCTLN[OUT] Bits */
\r
6601 #define TIMER_A_CCTLN_OUT_OFS ( 2) /**< OUT Bit Offset */
\r
6602 #define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /**< Output */
\r
6603 /* TIMER_A_CCTLN[CCI] Bits */
\r
6604 #define TIMER_A_CCTLN_CCI_OFS ( 3) /**< CCI Bit Offset */
\r
6605 #define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /**< Capture/compare input */
\r
6606 /* TIMER_A_CCTLN[CCIE] Bits */
\r
6607 #define TIMER_A_CCTLN_CCIE_OFS ( 4) /**< CCIE Bit Offset */
\r
6608 #define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /**< Capture/compare interrupt enable */
\r
6609 /* TIMER_A_CCTLN[OUTMOD] Bits */
\r
6610 #define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /**< OUTMOD Bit Offset */
\r
6611 #define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /**< OUTMOD Bit Mask */
\r
6612 #define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /**< OUTMOD Bit 0 */
\r
6613 #define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /**< OUTMOD Bit 1 */
\r
6614 #define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /**< OUTMOD Bit 2 */
\r
6615 #define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /**< OUT bit value */
\r
6616 #define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /**< Set */
\r
6617 #define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /**< Toggle/reset */
\r
6618 #define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /**< Set/reset */
\r
6619 #define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /**< Toggle */
\r
6620 #define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /**< Reset */
\r
6621 #define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /**< Toggle/set */
\r
6622 #define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /**< Reset/set */
\r
6623 /* TIMER_A_CCTLN[CAP] Bits */
\r
6624 #define TIMER_A_CCTLN_CAP_OFS ( 8) /**< CAP Bit Offset */
\r
6625 #define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /**< Capture mode */
\r
6626 /* TIMER_A_CCTLN[SCCI] Bits */
\r
6627 #define TIMER_A_CCTLN_SCCI_OFS (10) /**< SCCI Bit Offset */
\r
6628 #define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /**< Synchronized capture/compare input */
\r
6629 /* TIMER_A_CCTLN[SCS] Bits */
\r
6630 #define TIMER_A_CCTLN_SCS_OFS (11) /**< SCS Bit Offset */
\r
6631 #define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /**< Synchronize capture source */
\r
6632 /* TIMER_A_CCTLN[CCIS] Bits */
\r
6633 #define TIMER_A_CCTLN_CCIS_OFS (12) /**< CCIS Bit Offset */
\r
6634 #define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /**< CCIS Bit Mask */
\r
6635 #define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /**< CCIS Bit 0 */
\r
6636 #define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /**< CCIS Bit 1 */
\r
6637 #define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /**< CCIxA */
\r
6638 #define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /**< CCIxB */
\r
6639 #define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /**< GND */
\r
6640 #define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /**< VCC */
\r
6641 #define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /**< CCIxA */
\r
6642 #define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /**< CCIxB */
\r
6643 #define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /**< GND */
\r
6644 #define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /**< VCC */
\r
6645 /* TIMER_A_CCTLN[CM] Bits */
\r
6646 #define TIMER_A_CCTLN_CM_OFS (14) /**< CM Bit Offset */
\r
6647 #define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /**< CM Bit Mask */
\r
6648 #define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /**< CM Bit 0 */
\r
6649 #define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /**< CM Bit 1 */
\r
6650 #define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /**< No capture */
\r
6651 #define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /**< Capture on rising edge */
\r
6652 #define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /**< Capture on falling edge */
\r
6653 #define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /**< Capture on both rising and falling edges */
\r
6654 #define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /**< No capture */
\r
6655 #define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /**< Capture on rising edge */
\r
6656 #define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /**< Capture on falling edge */
\r
6657 #define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /**< Capture on both rising and falling edges */
\r
6658 /* TIMER_A_EX0[IDEX] Bits */
\r
6659 #define TIMER_A_EX0_IDEX_OFS ( 0) /**< TAIDEX Bit Offset */
\r
6660 #define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /**< TAIDEX Bit Mask */
\r
6661 #define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /**< IDEX Bit 0 */
\r
6662 #define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /**< IDEX Bit 1 */
\r
6663 #define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /**< IDEX Bit 2 */
\r
6664 #define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /**< Divide by 1 */
\r
6665 #define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /**< Divide by 2 */
\r
6666 #define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /**< Divide by 3 */
\r
6667 #define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /**< Divide by 4 */
\r
6668 #define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /**< Divide by 5 */
\r
6669 #define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /**< Divide by 6 */
\r
6670 #define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /**< Divide by 7 */
\r
6671 #define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /**< Divide by 8 */
\r
6672 #define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /**< Divide by 1 */
\r
6673 #define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /**< Divide by 2 */
\r
6674 #define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /**< Divide by 3 */
\r
6675 #define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /**< Divide by 4 */
\r
6676 #define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /**< Divide by 5 */
\r
6677 #define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /**< Divide by 6 */
\r
6678 #define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /**< Divide by 7 */
\r
6679 #define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /**< Divide by 8 */
\r
6682 /******************************************************************************
\r
6684 ******************************************************************************/
\r
6686 /******************************************************************************
\r
6687 * TLV table start and TLV tags *
\r
6688 ******************************************************************************/
\r
6689 #define TLV_START_ADDR (TLV_BASE + 0x0004) /* Start Address of the TLV structure */
\r
6691 #define TLV_TAG_RESERVED1 1
\r
6692 #define TLV_TAG_RESERVED2 2
\r
6693 #define TLV_TAG_CS 3
\r
6694 #define TLV_TAG_FLASHCTL 4
\r
6695 #define TLV_TAG_ADC14 5
\r
6696 #define TLV_TAG_RESERVED6 6
\r
6697 #define TLV_TAG_RESERVED7 7
\r
6698 #define TLV_TAG_REF 8
\r
6699 #define TLV_TAG_RESERVED9 9
\r
6700 #define TLV_TAG_RESERVED10 10
\r
6701 #define TLV_TAG_DEVINFO 11
\r
6702 #define TLV_TAG_DIEREC 12
\r
6703 #define TLV_TAG_RANDNUM 13
\r
6704 #define TLV_TAG_RESERVED14 14
\r
6705 #define TLV_TAG_BSL 15
\r
6706 #define TLV_TAG_END (0x0BD0E11D)
\r
6709 /******************************************************************************
\r
6711 ******************************************************************************/
\r
6712 /* WDT_A_CTL[IS] Bits */
\r
6713 #define WDT_A_CTL_IS_OFS ( 0) /**< WDTIS Bit Offset */
\r
6714 #define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /**< WDTIS Bit Mask */
\r
6715 #define WDT_A_CTL_IS0 ((uint16_t)0x0001) /**< IS Bit 0 */
\r
6716 #define WDT_A_CTL_IS1 ((uint16_t)0x0002) /**< IS Bit 1 */
\r
6717 #define WDT_A_CTL_IS2 ((uint16_t)0x0004) /**< IS Bit 2 */
\r
6718 #define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /**< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */
\r
6719 #define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /**< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */
\r
6720 #define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /**< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */
\r
6721 #define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /**< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */
\r
6722 #define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /**< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */
\r
6723 #define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /**< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */
\r
6724 #define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /**< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */
\r
6725 #define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /**< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */
\r
6726 /* WDT_A_CTL[CNTCL] Bits */
\r
6727 #define WDT_A_CTL_CNTCL_OFS ( 3) /**< WDTCNTCL Bit Offset */
\r
6728 #define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /**< Watchdog timer counter clear */
\r
6729 /* WDT_A_CTL[TMSEL] Bits */
\r
6730 #define WDT_A_CTL_TMSEL_OFS ( 4) /**< WDTTMSEL Bit Offset */
\r
6731 #define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /**< Watchdog timer mode select */
\r
6732 /* WDT_A_CTL[SSEL] Bits */
\r
6733 #define WDT_A_CTL_SSEL_OFS ( 5) /**< WDTSSEL Bit Offset */
\r
6734 #define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /**< WDTSSEL Bit Mask */
\r
6735 #define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /**< SSEL Bit 0 */
\r
6736 #define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /**< SSEL Bit 1 */
\r
6737 #define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /**< SMCLK */
\r
6738 #define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /**< ACLK */
\r
6739 #define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /**< VLOCLK */
\r
6740 #define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /**< BCLK */
\r
6741 #define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /**< SMCLK */
\r
6742 #define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /**< ACLK */
\r
6743 #define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /**< VLOCLK */
\r
6744 #define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /**< BCLK */
\r
6745 /* WDT_A_CTL[HOLD] Bits */
\r
6746 #define WDT_A_CTL_HOLD_OFS ( 7) /**< WDTHOLD Bit Offset */
\r
6747 #define WDT_A_CTL_HOLD ((uint16_t)0x0080) /**< Watchdog timer hold */
\r
6748 /* WDT_A_CTL[PW] Bits */
\r
6749 #define WDT_A_CTL_PW_OFS ( 8) /**< WDTPW Bit Offset */
\r
6750 #define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /**< WDTPW Bit Mask */
\r
6752 /* Pre-defined bitfield values */
\r
6753 #define WDT_A_CTL_PW ((uint16_t)0x5A00) /* WDT Key Value for WDT write access */
\r
6756 /******************************************************************************
\r
6758 ******************************************************************************/
\r
6759 #define BSL_DEFAULT_PARAM (0xFC48FFFF) /* I2C slave address = 0x48, Interface selection = Auto */
\r
6760 #define BSL_API_TABLE_ADDR (0x00202000) /* Address of BSL API table */
\r
6761 #define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR))
\r
6763 #define BSL_AUTO_INTERFACE (0x0000E0000) /* Auto detect interface */
\r
6764 #define BSL_UART_INTERFACE (0x0000C0000) /* UART interface */
\r
6765 #define BSL_SPI_INTERFACE (0x0000A0000) /* SPI interface */
\r
6766 #define BSL_I2C_INTERFACE (0x000080000) /* I2C interface */
\r
6768 #define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /* Invoke the BSL with paramters */
\r
6770 /******************************************************************************
\r
6772 ******************************************************************************/
\r
6774 #pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8})
\r
6775 #pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8})
\r
6776 #pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8})
\r
6777 #pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8})
\r
6778 #pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8})
\r
6779 #pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8})
\r
6780 #pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8})
\r
6781 #pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8})
\r
6782 #pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8})
\r
6783 #pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8})
\r
6786 #ifdef __cplusplus
\r
6790 #endif /* __MSP432P401R_H__ */
\r
projects / freertos / blob