git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.c

   1 /*
   2  * -------------------------------------------
   3  *    MSP432 DriverLib - v3_10_00_09
   4  * -------------------------------------------
   5  *
   6  * --COPYRIGHT--,BSD,BSD
   7  * Copyright (c) 2014, Texas Instruments Incorporated
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  *
  14  * *  Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  *
  17  * *  Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  *
  21  * *  Neither the name of Texas Instruments Incorporated nor the names of
  22  *    its contributors may be used to endorse or promote products derived
  23  *    from this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  32  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  33  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  34  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  35  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  * --/COPYRIGHT--*/
  37 #include <spi.h>
  38 #include <interrupt.h>
  39 #include <debug.h>
  40 #include <eusci.h>
  41
  42 static bool is_A_Module(uint32_t module)
  43 {
  44     if (module == EUSCI_A0_BASE || module == EUSCI_A1_BASE
  45 #ifdef EUSCI_A2_BASE
  46             || module == EUSCI_A2_BASE
  47 #endif
  48 #ifdef EUSCI_A3_BASE
  49             || module == EUSCI_A3_BASE
  50 #endif
  51     )
  52         return true;
  53     else
  54         return false;
  55 }
  56
  57 bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
  58 {
  59     /* Returning false if we are not divisible */
  60     if((config->clockSourceFrequency
  61                 % config->desiredSpiClock) != 0)
  62     {
  63         return false;
  64     }
  65
  66     if (is_A_Module(moduleInstance))
  67     {
  68         ASSERT(
  69                 (EUSCI_A_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
  70                 || (EUSCI_A_SPI_CLOCKSOURCE_SMCLK
  71                         == config->selectClockSource));
  72
  73         ASSERT(
  74                 (EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
  75                 || (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
  76
  77         ASSERT(
  78                 (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
  79                         == config->clockPhase)
  80                 || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
  81                         == config->clockPhase));
  82
  83         ASSERT(
  84                 (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
  85                         == config->clockPolarity)
  86                 || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
  87                         == config->clockPolarity));
  88
  89         ASSERT(
  90                 (EUSCI_A_SPI_3PIN == config->spiMode)
  91                 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
  92                         == config->spiMode)
  93                 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
  94                         == config->spiMode));
  95
  96         //Disable the USCI Module
  97         BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
  98
  99         /*
 100          * Configure as SPI master mode.
 101          * Clock phase select, polarity, msb
 102          * EUSCI_A_CTLW0_MST = Master mode
 103          * EUSCI_A_CTLW0_SYNC = Synchronous mode
 104          * UCMODE_0 = 3-pin SPI
 105          */
 106         EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
 107                 (EUSCI_A_CMSIS(moduleInstance)->CTLW0
 108                         & ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
 109                                 + EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
 110                         | (config->selectClockSource + config->msbFirst
 111                                 + config->clockPhase + config->clockPolarity
 112                                 + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
 113
 114         EUSCI_A_CMSIS(moduleInstance)->BRW =
 115                 (uint16_t) (config->clockSourceFrequency
 116                         / config->desiredSpiClock);
 117
 118         //No modulation
 119         EUSCI_A_CMSIS(moduleInstance)->MCTLW = 0;
 120
 121         return true;
 122     } else
 123     {
 124         ASSERT(
 125                 (EUSCI_B_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
 126                 || (EUSCI_B_SPI_CLOCKSOURCE_SMCLK
 127                         == config->selectClockSource));
 128
 129         ASSERT(
 130                 (EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
 131                 || (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
 132
 133         ASSERT(
 134                 (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 135                         == config->clockPhase)
 136                 || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 137                         == config->clockPhase));
 138
 139         ASSERT(
 140                 (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
 141                         == config->clockPolarity)
 142                 || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
 143                         == config->clockPolarity));
 144
 145         ASSERT(
 146                 (EUSCI_B_SPI_3PIN == config->spiMode)
 147                 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
 148                         == config->spiMode)
 149                 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
 150                         == config->spiMode));
 151
 152         //Disable the USCI Module
 153         BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
 154
 155         /*
 156          * Configure as SPI master mode.
 157          * Clock phase select, polarity, msb
 158          * EUSCI_A_CTLW0_MST = Master mode
 159          * EUSCI_A_CTLW0_SYNC = Synchronous mode
 160          * UCMODE_0 = 3-pin SPI
 161          */
 162         EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
 163                 (EUSCI_B_CMSIS(moduleInstance)->CTLW0
 164                         & ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
 165                                 + EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
 166                         | (config->selectClockSource + config->msbFirst
 167                                 + config->clockPhase + config->clockPolarity
 168                                 + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
 169
 170         EUSCI_B_CMSIS(moduleInstance)->BRW =
 171                 (uint16_t) (config->clockSourceFrequency
 172                         / config->desiredSpiClock);
 173
 174         return true;
 175     }
 176
 177 }
 178
 179 void SPI_selectFourPinFunctionality(uint32_t moduleInstance,
 180         uint_fast8_t select4PinFunctionality)
 181 {
 182     if (is_A_Module(moduleInstance))
 183     {
 184         EUSCI_A_SPI_select4PinFunctionality(moduleInstance,
 185                 select4PinFunctionality);
 186     } else
 187     {
 188         EUSCI_B_SPI_select4PinFunctionality(moduleInstance,
 189                 select4PinFunctionality);
 190     }
 191
 192 }
 193
 194 void SPI_changeMasterClock(uint32_t moduleInstance,
 195         uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
 196 {
 197     if (is_A_Module(moduleInstance))
 198     {
 199         EUSCI_A_SPI_masterChangeClock(moduleInstance, clockSourceFrequency,
 200                 desiredSpiClock);
 201     } else
 202     {
 203         EUSCI_B_SPI_masterChangeClock(moduleInstance, clockSourceFrequency,
 204                 desiredSpiClock);
 205     }
 206
 207 }
 208
 209 bool SPI_initSlave(uint32_t moduleInstance, const eUSCI_SPI_SlaveConfig *config)
 210 {
 211     if (is_A_Module(moduleInstance))
 212     {
 213         ASSERT(
 214                 (EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
 215                 || (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
 216
 217         ASSERT(
 218                 (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 219                         == config->clockPhase)
 220                 || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 221                         == config->clockPhase));
 222
 223         ASSERT(
 224                 (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
 225                         == config->clockPolarity)
 226                 || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
 227                         == config->clockPolarity));
 228
 229         ASSERT(
 230                 (EUSCI_A_SPI_3PIN == config->spiMode)
 231                 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
 232                         == config->spiMode)
 233                 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
 234                         == config->spiMode));
 235
 236         //Disable USCI Module
 237         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
 238
 239         //Reset OFS_UCAxCTLW0 register
 240         EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
 241                 (EUSCI_A_CMSIS(moduleInstance)->CTLW0
 242                         & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
 243                         | (config->clockPhase + config->clockPolarity
 244                                 + config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode);
 245
 246         return true;
 247     } else
 248     {
 249         ASSERT(
 250                 (EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
 251                 || (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
 252
 253         ASSERT(
 254                 (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 255                         == config->clockPhase)
 256                 || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 257                         == config->clockPhase));
 258
 259         ASSERT(
 260                 (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
 261                         == config->clockPolarity)
 262                 || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
 263                         == config->clockPolarity));
 264
 265         ASSERT(
 266                 (EUSCI_B_SPI_3PIN == config->spiMode)
 267                 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
 268                         == config->spiMode)
 269                 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
 270                         == config->spiMode));
 271
 272         //Disable USCI Module
 273         BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
 274
 275         //Reset OFS_UCBxCTLW0 register
 276         EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
 277                 (EUSCI_B_CMSIS(moduleInstance)->CTLW0
 278                         & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
 279                         | (config->clockPhase + config->clockPolarity
 280                                 + config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode);
 281
 282         return true;
 283     }
 284
 285 }
 286
 287 void SPI_changeClockPhasePolarity(uint32_t moduleInstance,
 288         uint_fast16_t clockPhase, uint_fast16_t clockPolarity)
 289 {
 290     if (is_A_Module(moduleInstance))
 291     {
 292         EUSCI_A_SPI_changeClockPhasePolarity(moduleInstance, clockPhase,
 293                 clockPolarity);
 294     } else
 295     {
 296         EUSCI_B_SPI_changeClockPhasePolarity(moduleInstance, clockPhase,
 297                 clockPolarity);
 298     }
 299
 300 }
 301
 302 void SPI_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
 303 {
 304     if (is_A_Module(moduleInstance))
 305     {
 306         EUSCI_A_SPI_transmitData(moduleInstance, transmitData);
 307     } else
 308     {
 309         EUSCI_B_SPI_transmitData(moduleInstance, transmitData);
 310     }
 311
 312 }
 313
 314 uint8_t SPI_receiveData(uint32_t moduleInstance)
 315 {
 316     if (is_A_Module(moduleInstance))
 317     {
 318         return EUSCI_A_SPI_receiveData(moduleInstance);
 319     } else
 320     {
 321         return EUSCI_B_SPI_receiveData(moduleInstance);
 322     }
 323
 324 }
 325
 326 void SPI_enableModule(uint32_t moduleInstance)
 327 {
 328     if (is_A_Module(moduleInstance))
 329     {
 330         EUSCI_A_SPI_enable(moduleInstance);
 331     } else
 332     {
 333         EUSCI_B_SPI_enable(moduleInstance);
 334     }
 335
 336 }
 337
 338 void SPI_disableModule(uint32_t moduleInstance)
 339 {
 340     if (is_A_Module(moduleInstance))
 341     {
 342         EUSCI_A_SPI_disable(moduleInstance);
 343     } else
 344     {
 345         EUSCI_B_SPI_disable(moduleInstance);
 346     }
 347
 348 }
 349
 350 uint32_t SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
 351 {
 352     if (is_A_Module(moduleInstance))
 353     {
 354         return EUSCI_A_SPI_getReceiveBufferAddressForDMA(moduleInstance);
 355     } else
 356     {
 357         return EUSCI_B_SPI_getReceiveBufferAddressForDMA(moduleInstance);
 358     }
 359
 360 }
 361
 362 uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
 363 {
 364     if (is_A_Module(moduleInstance))
 365     {
 366         return EUSCI_A_SPI_getTransmitBufferAddressForDMA(moduleInstance);
 367     } else
 368     {
 369         return EUSCI_B_SPI_getTransmitBufferAddressForDMA(moduleInstance);
 370     }
 371
 372 }
 373
 374 uint_fast8_t SPI_isBusy(uint32_t moduleInstance)
 375 {
 376     if (is_A_Module(moduleInstance))
 377     {
 378         return EUSCI_A_SPI_isBusy(moduleInstance);
 379     } else
 380     {
 381         return EUSCI_B_SPI_isBusy(moduleInstance);
 382     }
 383
 384 }
 385
 386 void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
 387 {
 388     if (is_A_Module(moduleInstance))
 389     {
 390         EUSCI_A_SPI_enableInterrupt(moduleInstance, mask);
 391     } else
 392     {
 393         EUSCI_B_SPI_enableInterrupt(moduleInstance, mask);
 394     }
 395
 396 }
 397
 398 void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
 399 {
 400     if (is_A_Module(moduleInstance))
 401     {
 402         EUSCI_A_SPI_disableInterrupt(moduleInstance, mask);
 403     } else
 404     {
 405         EUSCI_B_SPI_disableInterrupt(moduleInstance, mask);
 406     }
 407
 408 }
 409
 410 uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
 411 {
 412     if (is_A_Module(moduleInstance))
 413     {
 414         return EUSCI_A_SPI_getInterruptStatus(moduleInstance, mask);
 415     } else
 416     {
 417         return EUSCI_B_SPI_getInterruptStatus(moduleInstance, mask);
 418     }
 419
 420 }
 421
 422 uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance)
 423 {
 424     if (is_A_Module(moduleInstance))
 425     {
 426         return SPI_getInterruptStatus(moduleInstance,
 427                 EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
 428                 & EUSCI_A_CMSIS(moduleInstance)->IE;
 429
 430     } else
 431     {
 432         return SPI_getInterruptStatus(moduleInstance,
 433                 EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
 434                 & EUSCI_B_CMSIS(moduleInstance)->IE;
 435
 436     }
 437 }
 438
 439 void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
 440 {
 441     if (is_A_Module(moduleInstance))
 442     {
 443         EUSCI_A_SPI_clearInterruptFlag(moduleInstance, mask);
 444     } else
 445     {
 446         EUSCI_B_SPI_clearInterruptFlag(moduleInstance, mask);
 447     }
 448
 449 }
 450
 451 void SPI_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
 452 {
 453     switch (moduleInstance)
 454     {
 455     case EUSCI_A0_BASE:
 456         Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
 457         Interrupt_enableInterrupt(INT_EUSCIA0);
 458         break;
 459     case EUSCI_A1_BASE:
 460         Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
 461         Interrupt_enableInterrupt(INT_EUSCIA1);
 462         break;
 463 #ifdef EUSCI_A2_BASE
 464     case EUSCI_A2_BASE:
 465         Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
 466         Interrupt_enableInterrupt(INT_EUSCIA2);
 467         break;
 468 #endif
 469 #ifdef EUSCI_A3_BASE
 470     case EUSCI_A3_BASE:
 471         Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
 472         Interrupt_enableInterrupt(INT_EUSCIA3);
 473         break;
 474 #endif
 475     case EUSCI_B0_BASE:
 476         Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
 477         Interrupt_enableInterrupt(INT_EUSCIB0);
 478         break;
 479     case EUSCI_B1_BASE:
 480         Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
 481         Interrupt_enableInterrupt(INT_EUSCIB1);
 482         break;
 483 #ifdef EUSCI_B2_BASE
 484     case EUSCI_B2_BASE:
 485         Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
 486         Interrupt_enableInterrupt(INT_EUSCIB2);
 487         break;
 488 #endif
 489 #ifdef EUSCI_B3_BASE
 490     case EUSCI_B3_BASE:
 491         Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
 492         Interrupt_enableInterrupt(INT_EUSCIB3);
 493         break;
 494 #endif
 495     default:
 496         ASSERT(false);
 497     }
 498 }
 499
 500 void SPI_unregisterInterrupt(uint32_t moduleInstance)
 501 {
 502     switch (moduleInstance)
 503     {
 504     case EUSCI_A0_BASE:
 505         Interrupt_disableInterrupt(INT_EUSCIA0);
 506         Interrupt_unregisterInterrupt(INT_EUSCIA0);
 507         break;
 508     case EUSCI_A1_BASE:
 509         Interrupt_disableInterrupt(INT_EUSCIA1);
 510         Interrupt_unregisterInterrupt(INT_EUSCIA1);
 511         break;
 512 #ifdef EUSCI_A2_BASE
 513     case EUSCI_A2_BASE:
 514         Interrupt_disableInterrupt(INT_EUSCIA2);
 515         Interrupt_unregisterInterrupt(INT_EUSCIA2);
 516         break;
 517 #endif
 518 #ifdef EUSCI_A3_BASE
 519     case EUSCI_A3_BASE:
 520         Interrupt_disableInterrupt(INT_EUSCIA3);
 521         Interrupt_unregisterInterrupt(INT_EUSCIA3);
 522         break;
 523 #endif
 524     case EUSCI_B0_BASE:
 525         Interrupt_disableInterrupt(INT_EUSCIB0);
 526         Interrupt_unregisterInterrupt(INT_EUSCIB0);
 527         break;
 528     case EUSCI_B1_BASE:
 529         Interrupt_disableInterrupt(INT_EUSCIB1);
 530         Interrupt_unregisterInterrupt(INT_EUSCIB1);
 531         break;
 532 #ifdef EUSCI_B2_BASE
 533     case EUSCI_B2_BASE:
 534         Interrupt_disableInterrupt(INT_EUSCIB2);
 535         Interrupt_unregisterInterrupt(INT_EUSCIB2);
 536         break;
 537 #endif
 538 #ifdef EUSCI_B3_BASE
 539     case EUSCI_B3_BASE:
 540         Interrupt_disableInterrupt(INT_EUSCIB3);
 541         Interrupt_unregisterInterrupt(INT_EUSCIB3);
 542         break;
 543 #endif
 544     default:
 545         ASSERT(false);
 546     }
 547
 548 }
 549
 550 /* Backwards Compatibility Layer */
 551
 552 //*****************************************************************************
 553 //
 554 //! \brief Selects 4Pin Functionality
 555 //!
 556 //! This function should be invoked only in 4-wire mode. Invoking this function
 557 //! has no effect in 3-wire mode.
 558 //!
 559 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 560 //! \param select4PinFunctionality selects 4 pin functionality
 561 //!        Valid values are:
 562 //!        - \b EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
 563 //!        - \b EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
 564 //!
 565 //! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.
 566 //!
 567 //! \return None
 568 //
 569 //*****************************************************************************
 570 void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress,
 571         uint8_t select4PinFunctionality)
 572 {
 573     ASSERT(
 574             (EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
 575                     == select4PinFunctionality)
 576             || (EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
 577                     == select4PinFunctionality));
 578
 579     EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
 580             & ~EUSCI_B_CTLW0_STEM) | select4PinFunctionality;
 581 }
 582
 583 //*****************************************************************************
 584 //
 585 //! \brief Initializes the SPI Master clock. At the end of this function call,
 586 //! SPI module is left enabled.
 587 //!
 588 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 589 //! \param clockSourceFrequency is the frequency of the slected clock source
 590 //! \param desiredSpiClock is the desired clock rate for SPI communication
 591 //!
 592 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
 593 //!
 594 //! \return None
 595 //
 596 //*****************************************************************************
 597 void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress,
 598         uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
 599 {
 600     //Disable the USCI Module
 601     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
 602
 603     EUSCI_B_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency
 604             / desiredSpiClock);
 605
 606     //Reset the UCSWRST bit to enable the USCI Module
 607     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
 608 }
 609
 610 //*****************************************************************************
 611 //
 612 //! \brief Initializes the SPI Slave block.
 613 //!
 614 //! Upon successful initialization of the SPI slave block, this function will
 615 //! have initailized the slave block, but the SPI Slave block still remains
 616 //! disabled and must be enabled with EUSCI_B_SPI_enable()
 617 //!
 618 //! \param baseAddress is the base address of the EUSCI_B_SPI Slave module.
 619 //! \param msbFirst controls the direction of the receive and transmit shift
 620 //!        register.
 621 //!        Valid values are:
 622 //!        - \b EUSCI_B_SPI_MSB_FIRST
 623 //!        - \b EUSCI_B_SPI_LSB_FIRST [Default]
 624 //! \param clockPhase is clock phase select.
 625 //!        Valid values are:
 626 //!        - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 627 //!           [Default]
 628 //!        - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 629 //! \param clockPolarity is clock polarity select
 630 //!        Valid values are:
 631 //!        - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
 632 //!        - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
 633 //! \param spiMode is SPI mode select
 634 //!        Valid values are:
 635 //!        - \b EUSCI_B_SPI_3PIN
 636 //!        - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
 637 //!        - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
 638 //!
 639 //! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
 640 //! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
 641 //!
 642 //! \return STATUS_SUCCESS
 643 //
 644 //*****************************************************************************
 645 bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
 646         uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode)
 647 {
 648     ASSERT(
 649             (EUSCI_B_SPI_MSB_FIRST == msbFirst)
 650             || (EUSCI_B_SPI_LSB_FIRST == msbFirst));
 651
 652     ASSERT(
 653             (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 654                     == clockPhase)
 655             || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 656                     == clockPhase));
 657
 658     ASSERT(
 659             (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
 660             || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
 661                     == clockPolarity));
 662
 663     ASSERT(
 664             (EUSCI_B_SPI_3PIN == spiMode)
 665             || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode)
 666             || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
 667
 668     //Disable USCI Module
 669     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
 670
 671     //Reset OFS_UCBxCTLW0 register
 672     EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
 673             & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
 674             | (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode);
 675
 676     return true;
 677 }
 678
 679 //*****************************************************************************
 680 //
 681 //! \brief Changes the SPI colock phase and polarity. At the end of this
 682 //! function call, SPI module is left enabled.
 683 //!
 684 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 685 //! \param clockPhase is clock phase select.
 686 //!        Valid values are:
 687 //!        - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 688 //!           [Default]
 689 //!        - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 690 //! \param clockPolarity is clock polarity select
 691 //!        Valid values are:
 692 //!        - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
 693 //!        - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
 694 //!
 695 //! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0
 696 //! register.
 697 //!
 698 //! \return None
 699 //
 700 //*****************************************************************************
 701 void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress,
 702         uint16_t clockPhase, uint16_t clockPolarity)
 703 {
 704
 705     ASSERT(
 706             (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
 707             || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
 708                     == clockPolarity));
 709
 710     ASSERT(
 711             (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 712                     == clockPhase)
 713             || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 714                     == clockPhase));
 715
 716     //Disable the USCI Module
 717     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
 718
 719     EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
 720             & ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity);
 721
 722     //Reset the UCSWRST bit to enable the USCI Module
 723     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
 724 }
 725
 726 //*****************************************************************************
 727 //
 728 //! \brief Transmits a byte from the SPI Module.
 729 //!
 730 //! This function will place the supplied data into SPI trasmit data register
 731 //! to start transmission.
 732 //!
 733 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 734 //! \param transmitData data to be transmitted from the SPI module
 735 //!
 736 //! \return None
 737 //
 738 //*****************************************************************************
 739 void EUSCI_B_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
 740 {
 741     EUSCI_B_CMSIS(baseAddress)->TXBUF = transmitData;
 742 }
 743
 744 //*****************************************************************************
 745 //
 746 //! \brief Receives a byte that has been sent to the SPI Module.
 747 //!
 748 //! This function reads a byte of data from the SPI receive data Register.
 749 //!
 750 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 751 //!
 752 //! \return Returns the byte received from by the SPI module, cast as an
 753 //!         uint8_t.
 754 //
 755 //*****************************************************************************
 756 uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress)
 757 {
 758     return EUSCI_B_CMSIS(baseAddress)->RXBUF;
 759 }
 760
 761 //*****************************************************************************
 762 //
 763 //! \brief Enables individual SPI interrupt sources.
 764 //!
 765 //! Enables the indicated SPI interrupt sources.  Only the sources that are
 766 //! enabled can be reflected to the processor interrupt; disabled sources have
 767 //! no effect on the processor. Does not clear interrupt flags.
 768 //!
 769 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 770 //! \param mask is the bit mask of the interrupt sources to be enabled.
 771 //!        Mask value is the logical OR of any of the following:
 772 //!        - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
 773 //!        - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
 774 //!
 775 //! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register.
 776 //!
 777 //! \return None
 778 //
 779 //*****************************************************************************
 780 void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
 781 {
 782     ASSERT(
 783             !(mask
 784                     & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
 785                             | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
 786
 787     EUSCI_B_CMSIS(baseAddress)->IE |= mask;
 788 }
 789
 790 //*****************************************************************************
 791 //
 792 //! \brief Disables individual SPI interrupt sources.
 793 //!
 794 //! Disables the indicated SPI interrupt sources. Only the sources that are
 795 //! enabled can be reflected to the processor interrupt; disabled sources have
 796 //! no effect on the processor.
 797 //!
 798 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 799 //! \param mask is the bit mask of the interrupt sources to be disabled.
 800 //!        Mask value is the logical OR of any of the following:
 801 //!        - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
 802 //!        - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
 803 //!
 804 //! Modified bits of \b UCAxIE register.
 805 //!
 806 //! \return None
 807 //
 808 //*****************************************************************************
 809 void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
 810 {
 811     ASSERT(
 812             !(mask
 813                     & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
 814                             | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
 815
 816     EUSCI_B_CMSIS(baseAddress)->IE &= ~mask;
 817 }
 818
 819 //*****************************************************************************
 820 //
 821 //! \brief Gets the current SPI interrupt status.
 822 //!
 823 //! This returns the interrupt status for the SPI module based on which flag is
 824 //! passed.
 825 //!
 826 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 827 //! \param mask is the masked interrupt flag status to be returned.
 828 //!        Mask value is the logical OR of any of the following:
 829 //!        - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
 830 //!        - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
 831 //!
 832 //! \return Logical OR of any of the following:
 833 //!         - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
 834 //!         - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
 835 //!         \n indicating the status of the masked interrupts
 836 //
 837 //*****************************************************************************
 838 uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
 839 {
 840     ASSERT(
 841             !(mask
 842                     & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
 843                             | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
 844
 845     return EUSCI_B_CMSIS(baseAddress)->IFG & mask;
 846 }
 847
 848 //*****************************************************************************
 849 //
 850 //! \brief Clears the selected SPI interrupt status flag.
 851 //!
 852 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 853 //! \param mask is the masked interrupt flag to be cleared.
 854 //!        Mask value is the logical OR of any of the following:
 855 //!        - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
 856 //!        - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
 857 //!
 858 //! Modified bits of \b UCAxIFG register.
 859 //!
 860 //! \return None
 861 //
 862 //*****************************************************************************
 863 void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
 864 {
 865     ASSERT(
 866             !(mask
 867                     & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
 868                             | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
 869
 870     EUSCI_B_CMSIS(baseAddress)->IFG &= ~mask;
 871 }
 872
 873 //*****************************************************************************
 874 //
 875 //! \brief Enables the SPI block.
 876 //!
 877 //! This will enable operation of the SPI block.
 878 //!
 879 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 880 //!
 881 //! Modified bits are \b UCSWRST of \b UCBxCTLW0 register.
 882 //!
 883 //! \return None
 884 //
 885 //*****************************************************************************
 886 void EUSCI_B_SPI_enable(uint32_t baseAddress)
 887 {
 888     //Reset the UCSWRST bit to enable the USCI Module
 889     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
 890 }
 891
 892 //*****************************************************************************
 893 //
 894 //! \brief Disables the SPI block.
 895 //!
 896 //! This will disable operation of the SPI block.
 897 //!
 898 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 899 //!
 900 //! Modified bits are \b UCSWRST of \b UCBxCTLW0 register.
 901 //!
 902 //! \return None
 903 //
 904 //*****************************************************************************
 905 void EUSCI_B_SPI_disable(uint32_t baseAddress)
 906 {
 907     //Set the UCSWRST bit to disable the USCI Module
 908     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
 909 }
 910
 911 //*****************************************************************************
 912 //
 913 //! \brief Returns the address of the RX Buffer of the SPI for the DMA module.
 914 //!
 915 //! Returns the address of the SPI RX Buffer. This can be used in conjunction
 916 //! with the DMA to store the received data directly to memory.
 917 //!
 918 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 919 //!
 920 //! \return the address of the RX Buffer
 921 //
 922 //*****************************************************************************
 923 uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
 924 {
 925     return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->RXBUF));
 926 }
 927
 928 //*****************************************************************************
 929 //
 930 //! \brief Returns the address of the TX Buffer of the SPI for the DMA module.
 931 //!
 932 //! Returns the address of the SPI TX Buffer. This can be used in conjunction
 933 //! with the DMA to obtain transmitted data directly from memory.
 934 //!
 935 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 936 //!
 937 //! \return the address of the TX Buffer
 938 //
 939 //*****************************************************************************
 940 uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
 941 {
 942     return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->TXBUF));
 943 }
 944
 945 //*****************************************************************************
 946 //
 947 //! \brief Indicates whether or not the SPI bus is busy.
 948 //!
 949 //! This function returns an indication of whether or not the SPI bus is
 950 //! busy.This function checks the status of the bus via UCBBUSY bit
 951 //!
 952 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 953 //!
 954 //! \return true if busy, false otherwise
 955 //
 956 //*****************************************************************************
 957 bool EUSCI_B_SPI_isBusy(uint32_t baseAddress)
 958 {
 959     //Return the bus busy status.
 960     return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
 961 }
 962
 963 //*****************************************************************************
 964 //
 965 //! \brief Selects 4Pin Functionality
 966 //!
 967 //! This function should be invoked only in 4-wire mode. Invoking this function
 968 //! has no effect in 3-wire mode.
 969 //!
 970 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
 971 //! \param select4PinFunctionality selects 4 pin functionality
 972 //!        Valid values are:
 973 //!        - \b EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
 974 //!        - \b EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
 975 //!
 976 //! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.
 977 //!
 978 //! \return None
 979 //
 980 //*****************************************************************************
 981 void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress,
 982         uint8_t select4PinFunctionality)
 983 {
 984     ASSERT(
 985             (EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
 986                     == select4PinFunctionality)
 987             || (EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
 988                     == select4PinFunctionality));
 989
 990     EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
 991             & ~EUSCI_A_CTLW0_STEM) | select4PinFunctionality;
 992 }
 993
 994 //*****************************************************************************
 995 //
 996 //! \brief Initializes the SPI Master clock. At the end of this function call,
 997 //! SPI module is left enabled.
 998 //!
 999 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1000 //! \param clockSourceFrequency is the frequency of the slected clock source
1001 //! \param desiredSpiClock is the desired clock rate for SPI communication
1002 //!
1003 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
1004 //!
1005 //! \return None
1006 //
1007 //*****************************************************************************
1008 void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
1009         uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
1010 {
1011     //Disable the USCI Module
1012     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
1013
1014     EUSCI_A_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency
1015             / desiredSpiClock);
1016
1017     //Reset the UCSWRST bit to enable the USCI Module
1018     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
1019 }
1020
1021 //*****************************************************************************
1022 //
1023 //! \brief Initializes the SPI Slave block.
1024 //!
1025 //! Upon successful initialization of the SPI slave block, this function will
1026 //! have initailized the slave block, but the SPI Slave block still remains
1027 //! disabled and must be enabled with EUSCI_A_SPI_enable()
1028 //!
1029 //! \param baseAddress is the base address of the EUSCI_A_SPI Slave module.
1030 //! \param msbFirst controls the direction of the receive and transmit shift
1031 //!        register.
1032 //!        Valid values are:
1033 //!        - \b EUSCI_A_SPI_MSB_FIRST
1034 //!        - \b EUSCI_A_SPI_LSB_FIRST [Default]
1035 //! \param clockPhase is clock phase select.
1036 //!        Valid values are:
1037 //!        - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1038 //!           [Default]
1039 //!        - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1040 //! \param clockPolarity is clock polarity select
1041 //!        Valid values are:
1042 //!        - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
1043 //!        - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
1044 //! \param spiMode is SPI mode select
1045 //!        Valid values are:
1046 //!        - \b EUSCI_A_SPI_3PIN
1047 //!        - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
1048 //!        - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
1049 //!
1050 //! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
1051 //! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
1052 //!
1053 //! \return STATUS_SUCCESS
1054 //
1055 //*****************************************************************************
1056 bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
1057         uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode)
1058 {
1059     ASSERT(
1060             (EUSCI_A_SPI_MSB_FIRST == msbFirst)
1061             || (EUSCI_A_SPI_LSB_FIRST == msbFirst));
1062
1063     ASSERT(
1064             (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1065                     == clockPhase)
1066             || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1067                     == clockPhase));
1068
1069     ASSERT(
1070             (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
1071             || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
1072                     == clockPolarity));
1073
1074     ASSERT(
1075             (EUSCI_A_SPI_3PIN == spiMode)
1076             || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode)
1077             || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
1078
1079     //Disable USCI Module
1080     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
1081
1082     //Reset OFS_UCAxCTLW0 register
1083     EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
1084             & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
1085             | (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode);
1086
1087     return true;
1088 }
1089
1090 //*****************************************************************************
1091 //
1092 //! \brief Changes the SPI colock phase and polarity. At the end of this
1093 //! function call, SPI module is left enabled.
1094 //!
1095 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1096 //! \param clockPhase is clock phase select.
1097 //!        Valid values are:
1098 //!        - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1099 //!           [Default]
1100 //!        - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1101 //! \param clockPolarity is clock polarity select
1102 //!        Valid values are:
1103 //!        - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
1104 //!        - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
1105 //!
1106 //! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0
1107 //! register.
1108 //!
1109 //! \return None
1110 //
1111 //*****************************************************************************
1112 void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,
1113         uint16_t clockPhase, uint16_t clockPolarity)
1114 {
1115
1116     ASSERT(
1117             (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
1118             || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
1119                     == clockPolarity));
1120
1121     ASSERT(
1122             (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1123                     == clockPhase)
1124             || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1125                     == clockPhase));
1126
1127     //Disable the USCI Module
1128     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
1129
1130     EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
1131             & ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity);
1132
1133     //Reset the UCSWRST bit to enable the USCI Module
1134     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
1135 }
1136
1137 //*****************************************************************************
1138 //
1139 //! \brief Transmits a byte from the SPI Module.
1140 //!
1141 //! This function will place the supplied data into SPI trasmit data register
1142 //! to start transmission.
1143 //!
1144 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1145 //! \param transmitData data to be transmitted from the SPI module
1146 //!
1147 //! \return None
1148 //
1149 //*****************************************************************************
1150 void EUSCI_A_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
1151 {
1152     EUSCI_A_CMSIS(baseAddress)->TXBUF = transmitData;
1153 }
1154
1155 //*****************************************************************************
1156 //
1157 //! \brief Receives a byte that has been sent to the SPI Module.
1158 //!
1159 //! This function reads a byte of data from the SPI receive data Register.
1160 //!
1161 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1162 //!
1163 //! \return Returns the byte received from by the SPI module, cast as an
1164 //!         uint8_t.
1165 //
1166 //*****************************************************************************
1167 uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress)
1168 {
1169     return EUSCI_A_CMSIS(baseAddress)->RXBUF;
1170 }
1171
1172 //*****************************************************************************
1173 //
1174 //! \brief Enables individual SPI interrupt sources.
1175 //!
1176 //! Enables the indicated SPI interrupt sources.  Only the sources that are
1177 //! enabled can be reflected to the processor interrupt; disabled sources have
1178 //! no effect on the processor. Does not clear interrupt flags.
1179 //!
1180 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1181 //! \param mask is the bit mask of the interrupt sources to be enabled.
1182 //!        Mask value is the logical OR of any of the following:
1183 //!        - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1184 //!        - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1185 //!
1186 //! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register.
1187 //!
1188 //! \return None
1189 //
1190 //*****************************************************************************
1191 void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
1192 {
1193     ASSERT(
1194             !(mask
1195                     & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1196                             | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1197
1198     EUSCI_A_CMSIS(baseAddress)->IE |= mask;
1199 }
1200
1201 //*****************************************************************************
1202 //
1203 //! \brief Disables individual SPI interrupt sources.
1204 //!
1205 //! Disables the indicated SPI interrupt sources. Only the sources that are
1206 //! enabled can be reflected to the processor interrupt; disabled sources have
1207 //! no effect on the processor.
1208 //!
1209 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1210 //! \param mask is the bit mask of the interrupt sources to be disabled.
1211 //!        Mask value is the logical OR of any of the following:
1212 //!        - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1213 //!        - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1214 //!
1215 //! Modified bits of \b UCAxIE register.
1216 //!
1217 //! \return None
1218 //
1219 //*****************************************************************************
1220 void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
1221 {
1222     ASSERT(
1223             !(mask
1224                     & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1225                             | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1226
1227     EUSCI_A_CMSIS(baseAddress)->IE &= ~mask;
1228 }
1229
1230 //*****************************************************************************
1231 //
1232 //! \brief Gets the current SPI interrupt status.
1233 //!
1234 //! This returns the interrupt status for the SPI module based on which flag is
1235 //! passed.
1236 //!
1237 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1238 //! \param mask is the masked interrupt flag status to be returned.
1239 //!        Mask value is the logical OR of any of the following:
1240 //!        - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1241 //!        - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1242 //!
1243 //! \return Logical OR of any of the following:
1244 //!         - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1245 //!         - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1246 //!         \n indicating the status of the masked interrupts
1247 //
1248 //*****************************************************************************
1249 uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
1250 {
1251     ASSERT(
1252             !(mask
1253                     & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1254                             | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1255
1256     return EUSCI_A_CMSIS(baseAddress)->IFG & mask;
1257 }
1258
1259 //*****************************************************************************
1260 //
1261 //! \brief Clears the selected SPI interrupt status flag.
1262 //!
1263 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1264 //! \param mask is the masked interrupt flag to be cleared.
1265 //!        Mask value is the logical OR of any of the following:
1266 //!        - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1267 //!        - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1268 //!
1269 //! Modified bits of \b UCAxIFG register.
1270 //!
1271 //! \return None
1272 //
1273 //*****************************************************************************
1274 void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
1275 {
1276     ASSERT(
1277             !(mask
1278                     & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1279                             | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1280
1281     EUSCI_A_CMSIS(baseAddress)->IFG &= ~mask;
1282 }
1283
1284 //*****************************************************************************
1285 //
1286 //! \brief Enables the SPI block.
1287 //!
1288 //! This will enable operation of the SPI block.
1289 //!
1290 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1291 //!
1292 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
1293 //!
1294 //! \return None
1295 //
1296 //*****************************************************************************
1297 void EUSCI_A_SPI_enable(uint32_t baseAddress)
1298 {
1299     //Reset the UCSWRST bit to enable the USCI Module
1300     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
1301 }
1302
1303 //*****************************************************************************
1304 //
1305 //! \brief Disables the SPI block.
1306 //!
1307 //! This will disable operation of the SPI block.
1308 //!
1309 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1310 //!
1311 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
1312 //!
1313 //! \return None
1314 //
1315 //*****************************************************************************
1316 void EUSCI_A_SPI_disable(uint32_t baseAddress)
1317 {
1318     //Set the UCSWRST bit to disable the USCI Module
1319     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
1320 }
1321
1322 //*****************************************************************************
1323 //
1324 //! \brief Returns the address of the RX Buffer of the SPI for the DMA module.
1325 //!
1326 //! Returns the address of the SPI RX Buffer. This can be used in conjunction
1327 //! with the DMA to store the received data directly to memory.
1328 //!
1329 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1330 //!
1331 //! \return the address of the RX Buffer
1332 //
1333 //*****************************************************************************
1334 uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
1335 {
1336     return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->RXBUF;
1337 }
1338
1339 //*****************************************************************************
1340 //
1341 //! \brief Returns the address of the TX Buffer of the SPI for the DMA module.
1342 //!
1343 //! Returns the address of the SPI TX Buffer. This can be used in conjunction
1344 //! with the DMA to obtain transmitted data directly from memory.
1345 //!
1346 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1347 //!
1348 //! \return the address of the TX Buffer
1349 //
1350 //*****************************************************************************
1351 uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
1352 {
1353     return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->TXBUF;
1354 }
1355
1356 //*****************************************************************************
1357 //
1358 //! \brief Indicates whether or not the SPI bus is busy.
1359 //!
1360 //! This function returns an indication of whether or not the SPI bus is
1361 //! busy.This function checks the status of the bus via UCBBUSY bit
1362 //!
1363 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1364 //!
1365 //! \return true if busy, false otherwise
1366 //*****************************************************************************
1367 bool EUSCI_A_SPI_isBusy(uint32_t baseAddress)
1368 {
1369     //Return the bus busy status.
1370     return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
1371 }