2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
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7 * Copyright (c) 2014, Texas Instruments Incorporated
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38 #include <interrupt.h>
42 static bool is_A_Module(uint32_t module)
44 if (module == EUSCI_A0_BASE || module == EUSCI_A1_BASE
46 || module == EUSCI_A2_BASE
49 || module == EUSCI_A3_BASE
57 bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
59 /* Returning false if we are not divisible */
60 if((config->clockSourceFrequency
61 % config->desiredSpiClock) != 0)
66 if (is_A_Module(moduleInstance))
69 (EUSCI_A_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
70 || (EUSCI_A_SPI_CLOCKSOURCE_SMCLK
71 == config->selectClockSource));
74 (EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
75 || (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
78 (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
79 == config->clockPhase)
80 || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
81 == config->clockPhase));
84 (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
85 == config->clockPolarity)
86 || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
87 == config->clockPolarity));
90 (EUSCI_A_SPI_3PIN == config->spiMode)
91 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
93 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
96 //Disable the USCI Module
97 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
100 * Configure as SPI master mode.
101 * Clock phase select, polarity, msb
102 * EUSCI_A_CTLW0_MST = Master mode
103 * EUSCI_A_CTLW0_SYNC = Synchronous mode
104 * UCMODE_0 = 3-pin SPI
106 EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
107 (EUSCI_A_CMSIS(moduleInstance)->CTLW0
108 & ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
109 + EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
110 | (config->selectClockSource + config->msbFirst
111 + config->clockPhase + config->clockPolarity
112 + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
114 EUSCI_A_CMSIS(moduleInstance)->BRW =
115 (uint16_t) (config->clockSourceFrequency
116 / config->desiredSpiClock);
119 EUSCI_A_CMSIS(moduleInstance)->MCTLW = 0;
125 (EUSCI_B_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
126 || (EUSCI_B_SPI_CLOCKSOURCE_SMCLK
127 == config->selectClockSource));
130 (EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
131 || (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
134 (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
135 == config->clockPhase)
136 || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
137 == config->clockPhase));
140 (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
141 == config->clockPolarity)
142 || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
143 == config->clockPolarity));
146 (EUSCI_B_SPI_3PIN == config->spiMode)
147 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
149 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
150 == config->spiMode));
152 //Disable the USCI Module
153 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
156 * Configure as SPI master mode.
157 * Clock phase select, polarity, msb
158 * EUSCI_A_CTLW0_MST = Master mode
159 * EUSCI_A_CTLW0_SYNC = Synchronous mode
160 * UCMODE_0 = 3-pin SPI
162 EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
163 (EUSCI_B_CMSIS(moduleInstance)->CTLW0
164 & ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
165 + EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
166 | (config->selectClockSource + config->msbFirst
167 + config->clockPhase + config->clockPolarity
168 + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
170 EUSCI_B_CMSIS(moduleInstance)->BRW =
171 (uint16_t) (config->clockSourceFrequency
172 / config->desiredSpiClock);
179 void SPI_selectFourPinFunctionality(uint32_t moduleInstance,
180 uint_fast8_t select4PinFunctionality)
182 if (is_A_Module(moduleInstance))
184 EUSCI_A_SPI_select4PinFunctionality(moduleInstance,
185 select4PinFunctionality);
188 EUSCI_B_SPI_select4PinFunctionality(moduleInstance,
189 select4PinFunctionality);
194 void SPI_changeMasterClock(uint32_t moduleInstance,
195 uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
197 if (is_A_Module(moduleInstance))
199 EUSCI_A_SPI_masterChangeClock(moduleInstance, clockSourceFrequency,
203 EUSCI_B_SPI_masterChangeClock(moduleInstance, clockSourceFrequency,
209 bool SPI_initSlave(uint32_t moduleInstance, const eUSCI_SPI_SlaveConfig *config)
211 if (is_A_Module(moduleInstance))
214 (EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
215 || (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
218 (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
219 == config->clockPhase)
220 || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
221 == config->clockPhase));
224 (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
225 == config->clockPolarity)
226 || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
227 == config->clockPolarity));
230 (EUSCI_A_SPI_3PIN == config->spiMode)
231 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
233 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
234 == config->spiMode));
236 //Disable USCI Module
237 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
239 //Reset OFS_UCAxCTLW0 register
240 EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
241 (EUSCI_A_CMSIS(moduleInstance)->CTLW0
242 & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
243 | (config->clockPhase + config->clockPolarity
244 + config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode);
250 (EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
251 || (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
254 (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
255 == config->clockPhase)
256 || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
257 == config->clockPhase));
260 (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
261 == config->clockPolarity)
262 || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
263 == config->clockPolarity));
266 (EUSCI_B_SPI_3PIN == config->spiMode)
267 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
269 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
270 == config->spiMode));
272 //Disable USCI Module
273 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
275 //Reset OFS_UCBxCTLW0 register
276 EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
277 (EUSCI_B_CMSIS(moduleInstance)->CTLW0
278 & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
279 | (config->clockPhase + config->clockPolarity
280 + config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode);
287 void SPI_changeClockPhasePolarity(uint32_t moduleInstance,
288 uint_fast16_t clockPhase, uint_fast16_t clockPolarity)
290 if (is_A_Module(moduleInstance))
292 EUSCI_A_SPI_changeClockPhasePolarity(moduleInstance, clockPhase,
296 EUSCI_B_SPI_changeClockPhasePolarity(moduleInstance, clockPhase,
302 void SPI_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
304 if (is_A_Module(moduleInstance))
306 EUSCI_A_SPI_transmitData(moduleInstance, transmitData);
309 EUSCI_B_SPI_transmitData(moduleInstance, transmitData);
314 uint8_t SPI_receiveData(uint32_t moduleInstance)
316 if (is_A_Module(moduleInstance))
318 return EUSCI_A_SPI_receiveData(moduleInstance);
321 return EUSCI_B_SPI_receiveData(moduleInstance);
326 void SPI_enableModule(uint32_t moduleInstance)
328 if (is_A_Module(moduleInstance))
330 EUSCI_A_SPI_enable(moduleInstance);
333 EUSCI_B_SPI_enable(moduleInstance);
338 void SPI_disableModule(uint32_t moduleInstance)
340 if (is_A_Module(moduleInstance))
342 EUSCI_A_SPI_disable(moduleInstance);
345 EUSCI_B_SPI_disable(moduleInstance);
350 uint32_t SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
352 if (is_A_Module(moduleInstance))
354 return EUSCI_A_SPI_getReceiveBufferAddressForDMA(moduleInstance);
357 return EUSCI_B_SPI_getReceiveBufferAddressForDMA(moduleInstance);
362 uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
364 if (is_A_Module(moduleInstance))
366 return EUSCI_A_SPI_getTransmitBufferAddressForDMA(moduleInstance);
369 return EUSCI_B_SPI_getTransmitBufferAddressForDMA(moduleInstance);
374 uint_fast8_t SPI_isBusy(uint32_t moduleInstance)
376 if (is_A_Module(moduleInstance))
378 return EUSCI_A_SPI_isBusy(moduleInstance);
381 return EUSCI_B_SPI_isBusy(moduleInstance);
386 void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
388 if (is_A_Module(moduleInstance))
390 EUSCI_A_SPI_enableInterrupt(moduleInstance, mask);
393 EUSCI_B_SPI_enableInterrupt(moduleInstance, mask);
398 void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
400 if (is_A_Module(moduleInstance))
402 EUSCI_A_SPI_disableInterrupt(moduleInstance, mask);
405 EUSCI_B_SPI_disableInterrupt(moduleInstance, mask);
410 uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
412 if (is_A_Module(moduleInstance))
414 return EUSCI_A_SPI_getInterruptStatus(moduleInstance, mask);
417 return EUSCI_B_SPI_getInterruptStatus(moduleInstance, mask);
422 uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance)
424 if (is_A_Module(moduleInstance))
426 return SPI_getInterruptStatus(moduleInstance,
427 EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
428 & EUSCI_A_CMSIS(moduleInstance)->IE;
432 return SPI_getInterruptStatus(moduleInstance,
433 EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
434 & EUSCI_B_CMSIS(moduleInstance)->IE;
439 void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
441 if (is_A_Module(moduleInstance))
443 EUSCI_A_SPI_clearInterruptFlag(moduleInstance, mask);
446 EUSCI_B_SPI_clearInterruptFlag(moduleInstance, mask);
451 void SPI_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
453 switch (moduleInstance)
456 Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
457 Interrupt_enableInterrupt(INT_EUSCIA0);
460 Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
461 Interrupt_enableInterrupt(INT_EUSCIA1);
465 Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
466 Interrupt_enableInterrupt(INT_EUSCIA2);
471 Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
472 Interrupt_enableInterrupt(INT_EUSCIA3);
476 Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
477 Interrupt_enableInterrupt(INT_EUSCIB0);
480 Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
481 Interrupt_enableInterrupt(INT_EUSCIB1);
485 Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
486 Interrupt_enableInterrupt(INT_EUSCIB2);
491 Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
492 Interrupt_enableInterrupt(INT_EUSCIB3);
500 void SPI_unregisterInterrupt(uint32_t moduleInstance)
502 switch (moduleInstance)
505 Interrupt_disableInterrupt(INT_EUSCIA0);
506 Interrupt_unregisterInterrupt(INT_EUSCIA0);
509 Interrupt_disableInterrupt(INT_EUSCIA1);
510 Interrupt_unregisterInterrupt(INT_EUSCIA1);
514 Interrupt_disableInterrupt(INT_EUSCIA2);
515 Interrupt_unregisterInterrupt(INT_EUSCIA2);
520 Interrupt_disableInterrupt(INT_EUSCIA3);
521 Interrupt_unregisterInterrupt(INT_EUSCIA3);
525 Interrupt_disableInterrupt(INT_EUSCIB0);
526 Interrupt_unregisterInterrupt(INT_EUSCIB0);
529 Interrupt_disableInterrupt(INT_EUSCIB1);
530 Interrupt_unregisterInterrupt(INT_EUSCIB1);
534 Interrupt_disableInterrupt(INT_EUSCIB2);
535 Interrupt_unregisterInterrupt(INT_EUSCIB2);
540 Interrupt_disableInterrupt(INT_EUSCIB3);
541 Interrupt_unregisterInterrupt(INT_EUSCIB3);
550 /* Backwards Compatibility Layer */
552 //*****************************************************************************
554 //! \brief Selects 4Pin Functionality
556 //! This function should be invoked only in 4-wire mode. Invoking this function
557 //! has no effect in 3-wire mode.
559 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
560 //! \param select4PinFunctionality selects 4 pin functionality
561 //! Valid values are:
562 //! - \b EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
563 //! - \b EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
565 //! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.
569 //*****************************************************************************
570 void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress,
571 uint8_t select4PinFunctionality)
574 (EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
575 == select4PinFunctionality)
576 || (EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
577 == select4PinFunctionality));
579 EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
580 & ~EUSCI_B_CTLW0_STEM) | select4PinFunctionality;
583 //*****************************************************************************
585 //! \brief Initializes the SPI Master clock. At the end of this function call,
586 //! SPI module is left enabled.
588 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
589 //! \param clockSourceFrequency is the frequency of the slected clock source
590 //! \param desiredSpiClock is the desired clock rate for SPI communication
592 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
596 //*****************************************************************************
597 void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress,
598 uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
600 //Disable the USCI Module
601 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
603 EUSCI_B_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency
606 //Reset the UCSWRST bit to enable the USCI Module
607 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
610 //*****************************************************************************
612 //! \brief Initializes the SPI Slave block.
614 //! Upon successful initialization of the SPI slave block, this function will
615 //! have initailized the slave block, but the SPI Slave block still remains
616 //! disabled and must be enabled with EUSCI_B_SPI_enable()
618 //! \param baseAddress is the base address of the EUSCI_B_SPI Slave module.
619 //! \param msbFirst controls the direction of the receive and transmit shift
621 //! Valid values are:
622 //! - \b EUSCI_B_SPI_MSB_FIRST
623 //! - \b EUSCI_B_SPI_LSB_FIRST [Default]
624 //! \param clockPhase is clock phase select.
625 //! Valid values are:
626 //! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
628 //! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
629 //! \param clockPolarity is clock polarity select
630 //! Valid values are:
631 //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
632 //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
633 //! \param spiMode is SPI mode select
634 //! Valid values are:
635 //! - \b EUSCI_B_SPI_3PIN
636 //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
637 //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
639 //! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
640 //! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
642 //! \return STATUS_SUCCESS
644 //*****************************************************************************
645 bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
646 uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode)
649 (EUSCI_B_SPI_MSB_FIRST == msbFirst)
650 || (EUSCI_B_SPI_LSB_FIRST == msbFirst));
653 (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
655 || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
659 (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
660 || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
664 (EUSCI_B_SPI_3PIN == spiMode)
665 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode)
666 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
668 //Disable USCI Module
669 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
671 //Reset OFS_UCBxCTLW0 register
672 EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
673 & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
674 | (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode);
679 //*****************************************************************************
681 //! \brief Changes the SPI colock phase and polarity. At the end of this
682 //! function call, SPI module is left enabled.
684 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
685 //! \param clockPhase is clock phase select.
686 //! Valid values are:
687 //! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
689 //! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
690 //! \param clockPolarity is clock polarity select
691 //! Valid values are:
692 //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
693 //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
695 //! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0
700 //*****************************************************************************
701 void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress,
702 uint16_t clockPhase, uint16_t clockPolarity)
706 (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
707 || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
711 (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
713 || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
716 //Disable the USCI Module
717 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
719 EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
720 & ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity);
722 //Reset the UCSWRST bit to enable the USCI Module
723 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
726 //*****************************************************************************
728 //! \brief Transmits a byte from the SPI Module.
730 //! This function will place the supplied data into SPI trasmit data register
731 //! to start transmission.
733 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
734 //! \param transmitData data to be transmitted from the SPI module
738 //*****************************************************************************
739 void EUSCI_B_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
741 EUSCI_B_CMSIS(baseAddress)->TXBUF = transmitData;
744 //*****************************************************************************
746 //! \brief Receives a byte that has been sent to the SPI Module.
748 //! This function reads a byte of data from the SPI receive data Register.
750 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
752 //! \return Returns the byte received from by the SPI module, cast as an
755 //*****************************************************************************
756 uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress)
758 return EUSCI_B_CMSIS(baseAddress)->RXBUF;
761 //*****************************************************************************
763 //! \brief Enables individual SPI interrupt sources.
765 //! Enables the indicated SPI interrupt sources. Only the sources that are
766 //! enabled can be reflected to the processor interrupt; disabled sources have
767 //! no effect on the processor. Does not clear interrupt flags.
769 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
770 //! \param mask is the bit mask of the interrupt sources to be enabled.
771 //! Mask value is the logical OR of any of the following:
772 //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
773 //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
775 //! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register.
779 //*****************************************************************************
780 void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
784 & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
785 | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
787 EUSCI_B_CMSIS(baseAddress)->IE |= mask;
790 //*****************************************************************************
792 //! \brief Disables individual SPI interrupt sources.
794 //! Disables the indicated SPI interrupt sources. Only the sources that are
795 //! enabled can be reflected to the processor interrupt; disabled sources have
796 //! no effect on the processor.
798 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
799 //! \param mask is the bit mask of the interrupt sources to be disabled.
800 //! Mask value is the logical OR of any of the following:
801 //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
802 //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
804 //! Modified bits of \b UCAxIE register.
808 //*****************************************************************************
809 void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
813 & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
814 | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
816 EUSCI_B_CMSIS(baseAddress)->IE &= ~mask;
819 //*****************************************************************************
821 //! \brief Gets the current SPI interrupt status.
823 //! This returns the interrupt status for the SPI module based on which flag is
826 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
827 //! \param mask is the masked interrupt flag status to be returned.
828 //! Mask value is the logical OR of any of the following:
829 //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
830 //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
832 //! \return Logical OR of any of the following:
833 //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
834 //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
835 //! \n indicating the status of the masked interrupts
837 //*****************************************************************************
838 uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
842 & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
843 | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
845 return EUSCI_B_CMSIS(baseAddress)->IFG & mask;
848 //*****************************************************************************
850 //! \brief Clears the selected SPI interrupt status flag.
852 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
853 //! \param mask is the masked interrupt flag to be cleared.
854 //! Mask value is the logical OR of any of the following:
855 //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
856 //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
858 //! Modified bits of \b UCAxIFG register.
862 //*****************************************************************************
863 void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
867 & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
868 | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
870 EUSCI_B_CMSIS(baseAddress)->IFG &= ~mask;
873 //*****************************************************************************
875 //! \brief Enables the SPI block.
877 //! This will enable operation of the SPI block.
879 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
881 //! Modified bits are \b UCSWRST of \b UCBxCTLW0 register.
885 //*****************************************************************************
886 void EUSCI_B_SPI_enable(uint32_t baseAddress)
888 //Reset the UCSWRST bit to enable the USCI Module
889 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
892 //*****************************************************************************
894 //! \brief Disables the SPI block.
896 //! This will disable operation of the SPI block.
898 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
900 //! Modified bits are \b UCSWRST of \b UCBxCTLW0 register.
904 //*****************************************************************************
905 void EUSCI_B_SPI_disable(uint32_t baseAddress)
907 //Set the UCSWRST bit to disable the USCI Module
908 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
911 //*****************************************************************************
913 //! \brief Returns the address of the RX Buffer of the SPI for the DMA module.
915 //! Returns the address of the SPI RX Buffer. This can be used in conjunction
916 //! with the DMA to store the received data directly to memory.
918 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
920 //! \return the address of the RX Buffer
922 //*****************************************************************************
923 uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
925 return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->RXBUF));
928 //*****************************************************************************
930 //! \brief Returns the address of the TX Buffer of the SPI for the DMA module.
932 //! Returns the address of the SPI TX Buffer. This can be used in conjunction
933 //! with the DMA to obtain transmitted data directly from memory.
935 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
937 //! \return the address of the TX Buffer
939 //*****************************************************************************
940 uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
942 return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->TXBUF));
945 //*****************************************************************************
947 //! \brief Indicates whether or not the SPI bus is busy.
949 //! This function returns an indication of whether or not the SPI bus is
950 //! busy.This function checks the status of the bus via UCBBUSY bit
952 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
954 //! \return true if busy, false otherwise
956 //*****************************************************************************
957 bool EUSCI_B_SPI_isBusy(uint32_t baseAddress)
959 //Return the bus busy status.
960 return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
963 //*****************************************************************************
965 //! \brief Selects 4Pin Functionality
967 //! This function should be invoked only in 4-wire mode. Invoking this function
968 //! has no effect in 3-wire mode.
970 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
971 //! \param select4PinFunctionality selects 4 pin functionality
972 //! Valid values are:
973 //! - \b EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
974 //! - \b EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
976 //! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.
980 //*****************************************************************************
981 void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress,
982 uint8_t select4PinFunctionality)
985 (EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
986 == select4PinFunctionality)
987 || (EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
988 == select4PinFunctionality));
990 EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
991 & ~EUSCI_A_CTLW0_STEM) | select4PinFunctionality;
994 //*****************************************************************************
996 //! \brief Initializes the SPI Master clock. At the end of this function call,
997 //! SPI module is left enabled.
999 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1000 //! \param clockSourceFrequency is the frequency of the slected clock source
1001 //! \param desiredSpiClock is the desired clock rate for SPI communication
1003 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
1007 //*****************************************************************************
1008 void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
1009 uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
1011 //Disable the USCI Module
1012 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
1014 EUSCI_A_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency
1017 //Reset the UCSWRST bit to enable the USCI Module
1018 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
1021 //*****************************************************************************
1023 //! \brief Initializes the SPI Slave block.
1025 //! Upon successful initialization of the SPI slave block, this function will
1026 //! have initailized the slave block, but the SPI Slave block still remains
1027 //! disabled and must be enabled with EUSCI_A_SPI_enable()
1029 //! \param baseAddress is the base address of the EUSCI_A_SPI Slave module.
1030 //! \param msbFirst controls the direction of the receive and transmit shift
1032 //! Valid values are:
1033 //! - \b EUSCI_A_SPI_MSB_FIRST
1034 //! - \b EUSCI_A_SPI_LSB_FIRST [Default]
1035 //! \param clockPhase is clock phase select.
1036 //! Valid values are:
1037 //! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1039 //! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1040 //! \param clockPolarity is clock polarity select
1041 //! Valid values are:
1042 //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
1043 //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
1044 //! \param spiMode is SPI mode select
1045 //! Valid values are:
1046 //! - \b EUSCI_A_SPI_3PIN
1047 //! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
1048 //! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
1050 //! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
1051 //! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
1053 //! \return STATUS_SUCCESS
1055 //*****************************************************************************
1056 bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
1057 uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode)
1060 (EUSCI_A_SPI_MSB_FIRST == msbFirst)
1061 || (EUSCI_A_SPI_LSB_FIRST == msbFirst));
1064 (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1066 || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1070 (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
1071 || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
1075 (EUSCI_A_SPI_3PIN == spiMode)
1076 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode)
1077 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
1079 //Disable USCI Module
1080 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
1082 //Reset OFS_UCAxCTLW0 register
1083 EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
1084 & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
1085 | (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode);
1090 //*****************************************************************************
1092 //! \brief Changes the SPI colock phase and polarity. At the end of this
1093 //! function call, SPI module is left enabled.
1095 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1096 //! \param clockPhase is clock phase select.
1097 //! Valid values are:
1098 //! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1100 //! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1101 //! \param clockPolarity is clock polarity select
1102 //! Valid values are:
1103 //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
1104 //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
1106 //! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0
1111 //*****************************************************************************
1112 void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,
1113 uint16_t clockPhase, uint16_t clockPolarity)
1117 (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
1118 || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
1122 (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1124 || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1127 //Disable the USCI Module
1128 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
1130 EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
1131 & ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity);
1133 //Reset the UCSWRST bit to enable the USCI Module
1134 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
1137 //*****************************************************************************
1139 //! \brief Transmits a byte from the SPI Module.
1141 //! This function will place the supplied data into SPI trasmit data register
1142 //! to start transmission.
1144 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1145 //! \param transmitData data to be transmitted from the SPI module
1149 //*****************************************************************************
1150 void EUSCI_A_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
1152 EUSCI_A_CMSIS(baseAddress)->TXBUF = transmitData;
1155 //*****************************************************************************
1157 //! \brief Receives a byte that has been sent to the SPI Module.
1159 //! This function reads a byte of data from the SPI receive data Register.
1161 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1163 //! \return Returns the byte received from by the SPI module, cast as an
1166 //*****************************************************************************
1167 uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress)
1169 return EUSCI_A_CMSIS(baseAddress)->RXBUF;
1172 //*****************************************************************************
1174 //! \brief Enables individual SPI interrupt sources.
1176 //! Enables the indicated SPI interrupt sources. Only the sources that are
1177 //! enabled can be reflected to the processor interrupt; disabled sources have
1178 //! no effect on the processor. Does not clear interrupt flags.
1180 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1181 //! \param mask is the bit mask of the interrupt sources to be enabled.
1182 //! Mask value is the logical OR of any of the following:
1183 //! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1184 //! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1186 //! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register.
1190 //*****************************************************************************
1191 void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
1195 & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1196 | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1198 EUSCI_A_CMSIS(baseAddress)->IE |= mask;
1201 //*****************************************************************************
1203 //! \brief Disables individual SPI interrupt sources.
1205 //! Disables the indicated SPI interrupt sources. Only the sources that are
1206 //! enabled can be reflected to the processor interrupt; disabled sources have
1207 //! no effect on the processor.
1209 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1210 //! \param mask is the bit mask of the interrupt sources to be disabled.
1211 //! Mask value is the logical OR of any of the following:
1212 //! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1213 //! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1215 //! Modified bits of \b UCAxIE register.
1219 //*****************************************************************************
1220 void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
1224 & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1225 | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1227 EUSCI_A_CMSIS(baseAddress)->IE &= ~mask;
1230 //*****************************************************************************
1232 //! \brief Gets the current SPI interrupt status.
1234 //! This returns the interrupt status for the SPI module based on which flag is
1237 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1238 //! \param mask is the masked interrupt flag status to be returned.
1239 //! Mask value is the logical OR of any of the following:
1240 //! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1241 //! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1243 //! \return Logical OR of any of the following:
1244 //! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1245 //! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1246 //! \n indicating the status of the masked interrupts
1248 //*****************************************************************************
1249 uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
1253 & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1254 | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1256 return EUSCI_A_CMSIS(baseAddress)->IFG & mask;
1259 //*****************************************************************************
1261 //! \brief Clears the selected SPI interrupt status flag.
1263 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1264 //! \param mask is the masked interrupt flag to be cleared.
1265 //! Mask value is the logical OR of any of the following:
1266 //! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1267 //! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1269 //! Modified bits of \b UCAxIFG register.
1273 //*****************************************************************************
1274 void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
1278 & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1279 | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1281 EUSCI_A_CMSIS(baseAddress)->IFG &= ~mask;
1284 //*****************************************************************************
1286 //! \brief Enables the SPI block.
1288 //! This will enable operation of the SPI block.
1290 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1292 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
1296 //*****************************************************************************
1297 void EUSCI_A_SPI_enable(uint32_t baseAddress)
1299 //Reset the UCSWRST bit to enable the USCI Module
1300 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
1303 //*****************************************************************************
1305 //! \brief Disables the SPI block.
1307 //! This will disable operation of the SPI block.
1309 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1311 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
1315 //*****************************************************************************
1316 void EUSCI_A_SPI_disable(uint32_t baseAddress)
1318 //Set the UCSWRST bit to disable the USCI Module
1319 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
1322 //*****************************************************************************
1324 //! \brief Returns the address of the RX Buffer of the SPI for the DMA module.
1326 //! Returns the address of the SPI RX Buffer. This can be used in conjunction
1327 //! with the DMA to store the received data directly to memory.
1329 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1331 //! \return the address of the RX Buffer
1333 //*****************************************************************************
1334 uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
1336 return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->RXBUF;
1339 //*****************************************************************************
1341 //! \brief Returns the address of the TX Buffer of the SPI for the DMA module.
1343 //! Returns the address of the SPI TX Buffer. This can be used in conjunction
1344 //! with the DMA to obtain transmitted data directly from memory.
1346 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1348 //! \return the address of the TX Buffer
1350 //*****************************************************************************
1351 uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
1353 return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->TXBUF;
1356 //*****************************************************************************
1358 //! \brief Indicates whether or not the SPI bus is busy.
1360 //! This function returns an indication of whether or not the SPI bus is
1361 //! busy.This function checks the status of the bus via UCBBUSY bit
1363 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1365 //! \return true if busy, false otherwise
1366 //*****************************************************************************
1367 bool EUSCI_A_SPI_isBusy(uint32_t baseAddress)
1369 //Return the bus busy status.
1370 return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);