2 * -------------------------------------------
3 * MSP432 DriverLib - v01_04_00_18
4 * -------------------------------------------
6 * --COPYRIGHT--,BSD,BSD
7 * Copyright (c) 2015, Texas Instruments Incorporated
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11 * modification, are permitted provided that the following conditions
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19 * documentation and/or other materials provided with the distribution.
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23 * from this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 /* Standard Includes */
41 /* DriverLib Includes */
47 static bool SysCtlSRAMBankValid(uint8_t sramBank)
50 sramBank == SYSCTL_SRAM_BANK7 ||
51 sramBank == SYSCTL_SRAM_BANK6 ||
52 sramBank == SYSCTL_SRAM_BANK5 ||
53 sramBank == SYSCTL_SRAM_BANK4 ||
54 sramBank == SYSCTL_SRAM_BANK3 ||
55 sramBank == SYSCTL_SRAM_BANK2 ||
56 sramBank == SYSCTL_SRAM_BANK1
60 static bool SysCtlSRAMBankValidRet(uint8_t sramBank)
62 sramBank &= ~(SYSCTL_SRAM_BANK7 & SYSCTL_SRAM_BANK6 &
63 SYSCTL_SRAM_BANK5 & SYSCTL_SRAM_BANK4 &
64 SYSCTL_SRAM_BANK3 & SYSCTL_SRAM_BANK2 &
67 return (sramBank == 0);
70 static bool SysCtlPeripheralIsValid (uint16_t hwPeripheral)
72 hwPeripheral &= ~(SYSCTL_PERIPH_DMA & SYSCTL_PERIPH_WDT &
73 SYSCTL_PERIPH_ADC & SYSCTL_PERIPH_EUSCIB3 &
74 SYSCTL_PERIPH_EUSCIB2 & SYSCTL_PERIPH_EUSCIB1 &
75 SYSCTL_PERIPH_EUSCIB0 & SYSCTL_PERIPH_EUSCIA3 &
76 SYSCTL_PERIPH_EUSCIA2 & SYSCTL_PERIPH_EUSCIA1 &
77 SYSCTL_PERIPH_EUSCIA0 & SYSCTL_PERIPH_TIMER32_0_MODULE &
78 SYSCTL_PERIPH_TIMER16_3 & SYSCTL_PERIPH_TIMER16_2 &
79 SYSCTL_PERIPH_TIMER16_2 & SYSCTL_PERIPH_TIMER16_1 &
80 SYSCTL_PERIPH_TIMER16_0);
82 return (hwPeripheral == 0);
86 uint_least32_t SysCtl_getSRAMSize(void)
88 return SYSCTL->rSRAM_SIZE;
91 uint_least32_t SysCtl_getFlashSize(void)
93 return SYSCTL->rFLASH_SIZE;
96 void SysCtl_disableNMISource(uint_fast8_t flags)
98 SYSCTL->rNMI_CTLSTAT.r &= ~(flags);
101 void SysCtl_enableNMISource(uint_fast8_t flags)
103 SYSCTL->rNMI_CTLSTAT.r |= flags;
106 uint_fast8_t SysCtl_getNMISourceStatus(void)
108 return SYSCTL->rNMI_CTLSTAT.r;
111 void SysCtl_enableSRAMBank(uint_fast8_t sramBank)
113 ASSERT(SysCtlSRAMBankValid(sramBank));
115 /* Waiting for SRAM Ready Bit to be set */
116 while (!SYSCTL->rSRAM_BANKEN.b.bSRAM_RDY)
119 SYSCTL->rSRAM_BANKEN.r = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
122 void SysCtl_disableSRAMBank(uint_fast8_t sramBank)
124 ASSERT(SysCtlSRAMBankValid(sramBank));
126 /* Waiting for SRAM Ready Bit to be set */
127 while (!SYSCTL->rSRAM_BANKEN.b.bSRAM_RDY)
132 case SYSCTL_SRAM_BANK7:
133 sramBank = SYSCTL_SRAM_BANK6 + SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4
134 + SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
137 case SYSCTL_SRAM_BANK6:
138 sramBank = SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4
139 + SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
142 case SYSCTL_SRAM_BANK5:
143 sramBank = SYSCTL_SRAM_BANK4 + SYSCTL_SRAM_BANK3
144 + SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1;
146 case SYSCTL_SRAM_BANK4:
147 sramBank = SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2
150 case SYSCTL_SRAM_BANK3:
151 sramBank = SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1;
153 case SYSCTL_SRAM_BANK2:
154 sramBank = SYSCTL_SRAM_BANK1;
156 case SYSCTL_SRAM_BANK1:
163 SYSCTL->rSRAM_BANKEN.r = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
166 void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank)
168 ASSERT(SysCtlSRAMBankValidRet(sramBank));
170 /* Waiting for SRAM Ready Bit to be set */
171 while (!SYSCTL->rSRAM_BANKRET.b.bSRAM_RDY)
174 SYSCTL->rSRAM_BANKRET.r |= sramBank;
177 void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank)
179 ASSERT(SysCtlSRAMBankValidRet(sramBank));
181 /* Waiting for SRAM Ready Bit to be set */
182 while (!SYSCTL->rSRAM_BANKRET.b.bSRAM_RDY)
185 SYSCTL->rSRAM_BANKRET.r &= ~sramBank;
188 void SysCtl_rebootDevice(void)
190 SYSCTL->rREBOOT_CTL.r = (SYSCTL_REBOOT_CTL_REBOOT | SYSCTL_REBOOT_KEY);
193 void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices)
195 ASSERT(SysCtlPeripheralIsValid(devices));
196 SYSCTL->rPERIHALT_CTL.r &= ~devices;
199 void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices)
201 ASSERT(SysCtlPeripheralIsValid(devices));
202 SYSCTL->rPERIHALT_CTL.r |= devices;
205 void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType)
208 SYSCTL->rWDTRESET_CTL.r |=
209 SYSCTL_WDTRESET_CTL_TIMEOUT;
211 SYSCTL->rWDTRESET_CTL.r &= ~SYSCTL_WDTRESET_CTL_TIMEOUT;
214 void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType)
216 ASSERT(resetType <= SYSCTL_HARD_RESET);
219 SYSCTL->rWDTRESET_CTL.r |=
220 SYSCTL_WDTRESET_CTL_VIOLATION;
222 SYSCTL->rWDTRESET_CTL.r &= ~SYSCTL_WDTRESET_CTL_VIOLATION;
225 void SysCtl_enableGlitchFilter(void)
227 SYSCTL->rDIO_GLTFLT_CTL.r |= SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
230 void SysCtl_disableGlitchFilter(void)
232 SYSCTL->rDIO_GLTFLT_CTL.r &= ~SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
235 uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
236 uint32_t temperature)
238 return HWREG16(TLV_BASE + refVoltage + temperature);