2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
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7 * Copyright (c) 2014, Texas Instruments Incorporated
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11 * modification, are permitted provided that the following conditions
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40 //*****************************************************************************
42 //! \addtogroup sysctl_api
45 //*****************************************************************************
47 //*****************************************************************************
49 // If building with a C++ compiler, make all of the definitions in this header
52 //*****************************************************************************
61 //*****************************************************************************
63 // Control specific variables
65 //*****************************************************************************
66 #define SYSCTL_SRAM_BANK7 SYSCTL_SRAM_BANKEN_BNK7_EN
67 #define SYSCTL_SRAM_BANK6 SYSCTL_SRAM_BANKEN_BNK6_EN
68 #define SYSCTL_SRAM_BANK5 SYSCTL_SRAM_BANKEN_BNK5_EN
69 #define SYSCTL_SRAM_BANK4 SYSCTL_SRAM_BANKEN_BNK4_EN
70 #define SYSCTL_SRAM_BANK3 SYSCTL_SRAM_BANKEN_BNK3_EN
71 #define SYSCTL_SRAM_BANK2 SYSCTL_SRAM_BANKEN_BNK2_EN
72 #define SYSCTL_SRAM_BANK1 SYSCTL_SRAM_BANKEN_BNK1_EN
74 #define SYSCTL_HARD_RESET 1
75 #define SYSCTL_SOFT_RESET 0
77 #define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_HALT_DMA
78 #define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_HALT_WDT
79 #define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_HALT_ADC
80 #define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_HALT_EUB3
81 #define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_HALT_EUB2
82 #define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_HALT_EUB1
83 #define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_HALT_EUB0
84 #define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_HALT_EUA3
85 #define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_HALT_EUA2
86 #define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_HALT_EUA1
87 #define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_HALT_EUA0
88 #define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_HALT_T32_0
89 #define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_HALT_T16_3
90 #define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_HALT_T16_2
91 #define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_HALT_T16_1
92 #define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_HALT_T16_0
94 #define SYSCTL_NMIPIN_SRC SYSCTL_NMI_CTLSTAT_PIN_SRC
95 #define SYSCTL_PCM_SRC SYSCTL_NMI_CTLSTAT_PCM_SRC
96 #define SYSCTL_PSS_SRC SYSCTL_NMI_CTLSTAT_PSS_SRC
97 #define SYSCTL_CS_SRC SYSCTL_NMI_CTLSTAT_CS_SRC
99 #define SYSCTL_REBOOT_KEY 0x6900
101 #define SYSCTL_1_2V_REF (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE
102 #define SYSCTL_1_45V_REF (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE
103 #define SYSCTL_2_5V_REF (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE
105 #define SYSCTL_85_DEGREES_C 4
106 #define SYSCTL_30_DEGREES_C 0
109 #define TLV_START 0x00201004
110 #define TLV_TAG_RESERVED1 1
111 #define TLV_TAG_RESERVED2 2
113 #define TLV_TAG_FLASHCTL 4
114 #define TLV_TAG_ADC14 5
115 #define TLV_TAG_RESERVED6 6
116 #define TLV_TAG_RESERVED7 7
117 #define TLV_TAG_REF 8
118 #define TLV_TAG_RESERVED9 9
119 #define TLV_TAG_RESERVED10 10
120 #define TLV_TAG_DEVINFO 11
121 #define TLV_TAG_DIEREC 12
122 #define TLV_TAG_RANDNUM 13
123 #define TLV_TAG_RESERVED14 14
124 #define TLV_TAG_BSL 15
125 #define TLV_TAGEND 0x0BD0E11D
127 //*****************************************************************************
129 // Structures for TLV definitions
131 //*****************************************************************************
134 uint32_t maxProgramPulses;
135 uint32_t maxErasePulses;
136 } SysCtl_FlashTLV_Info;
140 uint32_t rDCOIR_FCAL_RSEL04;
141 uint32_t rDCOIR_FCAL_RSEL5;
142 uint32_t rDCOIR_MAXPOSTUNE_RSEL04;
143 uint32_t rDCOIR_MAXNEGTUNE_RSEL04;
144 uint32_t rDCOIR_MAXPOSTUNE_RSEL5;
145 uint32_t rDCOIR_MAXNEGTUNE_RSEL5;
146 uint32_t rDCOIR_CONSTK_RSEL04;
147 uint32_t rDCOIR_CONSTK_RSEL5;
148 uint32_t rDCOER_FCAL_RSEL04;
149 uint32_t rDCOER_FCAL_RSEL5;
150 uint32_t rDCOER_MAXPOSTUNE_RSEL04;
151 uint32_t rDCOER_MAXNEGTUNE_RSEL04;
152 uint32_t rDCOER_MAXPOSTUNE_RSEL5;
153 uint32_t rDCOER_MAXNEGTUNE_RSEL5;
154 uint32_t rDCOER_CONSTK_RSEL04;
155 uint32_t rDCOER_CONSTK_RSEL5;
157 } SysCtl_CSCalTLV_Info;
159 //*****************************************************************************
161 // Prototypes for the APIs.
163 //*****************************************************************************
165 //*****************************************************************************
167 //! Gets the size of the SRAM.
169 //! \return The total number of bytes of SRAM.
171 //*****************************************************************************
172 extern uint_least32_t SysCtl_getSRAMSize(void);
174 //*****************************************************************************
176 //! Gets the size of the flash.
178 //! \return The total number of bytes of flash.
180 //*****************************************************************************
181 extern uint_least32_t SysCtl_getFlashSize(void);
183 //*****************************************************************************
185 //! Reboots the device and causes the device to re-initialize itself.
187 //! \return This function does not return.
189 //*****************************************************************************
190 extern void SysCtl_rebootDevice(void);
192 //*****************************************************************************
194 //! The TLV structure uses a tag or base address to identify segments of the
195 //! table where information is stored. Some examples of TLV tags are Peripheral
196 //! Descriptor, Interrupts, Info Block and Die Record. This function retrieves
197 //! the value of a tag and the length of the tag.
199 //! \param tag represents the tag for which the information needs to be
201 //! Valid values are:
202 //! - \b TLV_TAG_RESERVED1
203 //! - \b TLV_TAG_RESERVED2
205 //! - \b TLV_TAG_FLASHCTL
206 //! - \b TLV_TAG_ADC14
207 //! - \b TLV_TAG_RESERVED6
208 //! - \b TLV_TAG_RESERVED7
210 //! - \b TLV_TAG_RESERVED9
211 //! - \b TLV_TAG_RESERVED10
212 //! - \b TLV_TAG_DEVINFO
213 //! - \b TLV_TAG_DIEREC
214 //! - \b TLV_TAG_RANDNUM
215 //! - \b TLV_TAG_RESERVED14
216 //! \param instance In some cases a specific tag may have more than one
217 //! instance. For example there may be multiple instances of timer
218 //! calibration data present under a single Timer Cal tag. This variable
219 //! specifies the instance for which information is to be retrieved (0,
220 //! 1, etc.). When only one instance exists; 0 is passed.
221 //! \param length Acts as a return through indirect reference. The function
222 //! retrieves the value of the TLV tag length. This value is pointed to
223 //! by *length and can be used by the application level once the
224 //! function is called. If the specified tag is not found then the
225 //! pointer is null 0.
226 //! \param data_address acts as a return through indirect reference. Once the
227 //! function is called data_address points to the pointer that holds the
228 //! value retrieved from the specified TLV tag. If the specified tag is
229 //! not found then the pointer is null 0.
233 //*****************************************************************************
234 extern void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
235 uint_fast8_t *length, uint32_t **data_address);
237 //*****************************************************************************
239 //! Enables a set of banks in the SRAM. This can be used to optimize power
240 //! consumption when every SRAM bank isn't needed. It is important to note
241 //! that when a higher bank is enabled, all of the SRAM banks below that bank
242 //! are also enabled. For example, if the user enables SYSCTL_SRAM_BANK7,
243 //! the banks SYSCTL_SRAM_BANK1 through SYSCTL_SRAM_BANK7 will be enabled
244 //! (SRAM_BANK0 is reserved and always enabled).
246 //! \param sramBank The SRAM bank tier to enable.
247 //! Must be only one of the following values:
248 //! - \b SYSCTL_SRAM_BANK1,
249 //! - \b SYSCTL_SRAM_BANK2,
250 //! - \b SYSCTL_SRAM_BANK3,
251 //! - \b SYSCTL_SRAM_BANK4,
252 //! - \b SYSCTL_SRAM_BANK5,
253 //! - \b SYSCTL_SRAM_BANK6,
254 //! - \b SYSCTL_SRAM_BANK7
256 //! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled.
260 //*****************************************************************************
261 extern void SysCtl_enableSRAMBank(uint_fast8_t sramBank);
263 //*****************************************************************************
265 //! Disables a set of banks in the SRAM. This can be used to optimize power
266 //! consumption when every SRAM bank isn't needed. It is important to note
267 //! that when a higher bank is disabled, all of the SRAM banks above that bank
268 //! are also disabled. For example, if the user disables SYSCTL_SRAM_BANK5,
269 //! the banks SYSCTL_SRAM_BANK6 through SYSCTL_SRAM_BANK7 will be disabled.
271 //! \param sramBank The SRAM bank tier to disable.
272 //! Must be only one of the following values:
273 //! - \b SYSCTL_SRAM_BANK1,
274 //! - \b SYSCTL_SRAM_BANK2,
275 //! - \b SYSCTL_SRAM_BANK3,
276 //! - \b SYSCTL_SRAM_BANK4,
277 //! - \b SYSCTL_SRAM_BANK5,
278 //! - \b SYSCTL_SRAM_BANK6,
279 //! - \b SYSCTL_SRAM_BANK7
281 //! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled.
285 //*****************************************************************************
286 extern void SysCtl_disableSRAMBank(uint_fast8_t sramBank);
288 //*****************************************************************************
290 //! Enables retention of the specified SRAM bank register when the device goes
291 //! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
292 //! banks specified with this function will be placed into retention mode. By
293 //! default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved) is
294 //! disabled. Retention of individual banks can be set without the restrictions
295 //! of the enable/disable functions.
297 //! \param sramBank The SRAM banks to enable retention
298 //! Can be a bitwise OR of the following values:
299 //! - \b SYSCTL_SRAM_BANK1,
300 //! - \b SYSCTL_SRAM_BANK2,
301 //! - \b SYSCTL_SRAM_BANK3,
302 //! - \b SYSCTL_SRAM_BANK4,
303 //! - \b SYSCTL_SRAM_BANK5,
304 //! - \b SYSCTL_SRAM_BANK6,
305 //! - \b SYSCTL_SRAM_BANK7
306 //! \note \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled.
311 //*****************************************************************************
312 extern void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank);
314 //*****************************************************************************
316 //! Disables retention of the specified SRAM bank register when the device goes
317 //! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
318 //! banks specified with this function will not be placed into retention mode.
319 //! By default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved)
320 //! is disabled. Retention of individual banks can be set without the
321 //! restrictions of the enable/disable SRAM bank functions.
323 //! \param sramBank The SRAM banks to disable retention
324 //! Can be a bitwise OR of the following values:
325 //! - \b SYSCTL_SRAM_BANK1,
326 //! - \b SYSCTL_SRAM_BANK2,
327 //! - \b SYSCTL_SRAM_BANK3,
328 //! - \b SYSCTL_SRAM_BANK4,
329 //! - \b SYSCTL_SRAM_BANK5,
330 //! - \b SYSCTL_SRAM_BANK6,
331 //! - \b SYSCTL_SRAM_BANK7
332 //! \note \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled.
337 //*****************************************************************************
338 extern void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank);
340 //*****************************************************************************
342 //! Makes it so that the provided peripherals will either halt execution after
343 //! a CPU HALT. Parameters in this function can be combined to account for
344 //! multiple peripherals. By default, all peripherals keep running after a
347 //! \param devices The peripherals to continue running after a CPU HALT
348 //! This can be a bitwise OR of the following values:
349 //! - \b SYSCTL_PERIPH_DMA,
350 //! - \b SYSCTL_PERIPH_WDT,
351 //! - \b SYSCTL_PERIPH_ADC,
352 //! - \b SYSCTL_PERIPH_EUSCIB3,
353 //! - \b SYSCTL_PERIPH_EUSCIB2,
354 //! - \b SYSCTL_PERIPH_EUSCIB1
355 //! - \b SYSCTL_PERIPH_EUSCIB0,
356 //! - \b SYSCTL_PERIPH_EUSCIA3,
357 //! - \b SYSCTL_PERIPH_EUSCIA2
358 //! - \b SYSCTL_PERIPH_EUSCIA1,
359 //! - \b SYSCTL_PERIPH_EUSCIA0,
360 //! - \b SYSCTL_PERIPH_TIMER32_0_MODULE,
361 //! - \b SYSCTL_PERIPH_TIMER16_3,
362 //! - \b SYSCTL_PERIPH_TIMER16_2,
363 //! - \b SYSCTL_PERIPH_TIMER16_1,
364 //! - \b SYSCTL_PERIPH_TIMER16_0
369 //*****************************************************************************
370 extern void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices);
372 //*****************************************************************************
374 //! Makes it so that the provided peripherals will either halt execution after
375 //! a CPU HALT. Parameters in this function can be combined to account for
376 //! multiple peripherals. By default, all peripherals keep running after a
379 //! \param devices The peripherals to disable after a CPU HALT
381 //! The \e devices parameter can be a bitwise OR of the following values:
382 //! This can be a bitwise OR of the following values:
383 //! - \b SYSCTL_PERIPH_DMA,
384 //! - \b SYSCTL_PERIPH_WDT,
385 //! - \b SYSCTL_PERIPH_ADC,
386 //! - \b SYSCTL_PERIPH_EUSCIB3,
387 //! - \b SYSCTL_PERIPH_EUSCIB2,
388 //! - \b SYSCTL_PERIPH_EUSCIB1
389 //! - \b SYSCTL_PERIPH_EUSCIB0,
390 //! - \b SYSCTL_PERIPH_EUSCIA3,
391 //! - \b SYSCTL_PERIPH_EUSCIA2
392 //! - \b SYSCTL_PERIPH_EUSCIA1,
393 //! - \b SYSCTL_PERIPH_EUSCIA0,
394 //! - \b SYSCTL_PERIPH_TIMER32_0_MODULE,
395 //! - \b SYSCTL_PERIPH_TIMER16_3,
396 //! - \b SYSCTL_PERIPH_TIMER16_2,
397 //! - \b SYSCTL_PERIPH_TIMER16_1,
398 //! - \b SYSCTL_PERIPH_TIMER16_0
403 //*****************************************************************************
404 extern void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices);
406 //*****************************************************************************
408 //! Sets the type of RESET that happens when a watchdog timeout occurs.
410 //! \param resetType The type of reset to set
412 //! The \e resetType parameter must be only one of the following values:
413 //! - \b SYSCTL_HARD_RESET,
414 //! - \b SYSCTL_SOFT_RESET
419 //*****************************************************************************
420 extern void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType);
422 //*****************************************************************************
424 //! Sets the type of RESET that happens when a watchdog password violation
427 //! \param resetType The type of reset to set
429 //! The \e resetType parameter must be only one of the following values:
430 //! - \b SYSCTL_HARD_RESET,
431 //! - \b SYSCTL_SOFT_RESET
436 //*****************************************************************************
437 extern void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType);
439 //*****************************************************************************
441 //! Disables NMIs for the provided modules. When disabled, a NMI flag will not
442 //! occur when a fault condition comes from the corresponding modules.
444 //! \param flags The NMI sources to disable
445 //! Can be a bitwise OR of the following parameters:
446 //! - \b SYSCTL_NMIPIN_SRC,
447 //! - \b SYSCTL_PCM_SRC,
448 //! - \b SYSCTL_PSS_SRC,
449 //! - \b SYSCTL_CS_SRC
452 //*****************************************************************************
453 extern void SysCtl_disableNMISource(uint_fast8_t flags);
455 //*****************************************************************************
457 //! Enables NMIs for the provided modules. When enabled, a NMI flag will
458 //! occur when a fault condition comes from the corresponding modules.
460 //! \param flags The NMI sources to enable
461 //! Can be a bitwise OR of the following parameters:
462 //! - \b SYSCTL_NMIPIN_SRC,
463 //! - \b SYSCTL_PCM_SRC,
464 //! - \b SYSCTL_PSS_SRC,
465 //! - \b SYSCTL_CS_SRC
468 //*****************************************************************************
469 extern void SysCtl_enableNMISource(uint_fast8_t flags);
471 //*****************************************************************************
473 //! Returns the current sources of NMIs that are enabled
475 //! \return Bitwise OR of NMI flags that are enabled
477 //*****************************************************************************
478 extern uint_fast8_t SysCtl_getNMISourceStatus(void);
480 //*****************************************************************************
482 //! Enables glitch suppression on the reset pin of the device. Refer to the
483 //! device data sheet for specific information about glitch suppression
488 //*****************************************************************************
489 extern void SysCtl_enableGlitchFilter(void);
491 //*****************************************************************************
493 //! Disables glitch suppression on the reset pin of the device. Refer to the
494 //! device data sheet for specific information about glitch suppression
499 //*****************************************************************************
500 extern void SysCtl_disableGlitchFilter(void);
502 //*****************************************************************************
504 //! Retrieves the calibration constant of the temperature sensor to be used
505 //! in temperature calculation.
507 //! \param refVoltage Reference voltage being used.
509 //! The \e refVoltage parameter must be only one of the following values:
510 //! - \b SYSCTL_1_2V_REF
511 //! - \b SYSCTL_1_45V_REF
512 //! - \b SYSCTL_2_5V_REF
514 //! \param temperature is the calibration temperature that the user wants to be
517 //! The \e temperature parameter must be only one of the following values:
518 //! - \b SYSCTL_30_DEGREES_C
519 //! - \b SYSCTL_85_DEGREES_C
524 //*****************************************************************************
525 extern uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
526 uint32_t temperature);
528 //*****************************************************************************
530 // Mark the end of the C bindings section for C++ compilers.
532 //*****************************************************************************
537 //*****************************************************************************
539 // Close the Doxygen group.
542 //*****************************************************************************
544 #endif // __SYSCTL_H__