2 * -------------------------------------------
3 * MSP432 DriverLib - v3_10_00_09
4 * -------------------------------------------
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7 * Copyright (c) 2014, Texas Instruments Incorporated
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38 #include <interrupt.h>
42 bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
47 (EUSCI_A_UART_MODE == config->uartMode)
48 || (EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE
50 || (EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE
52 || (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
53 == config->uartMode));
56 (EUSCI_A_UART_CLOCKSOURCE_ACLK == config->selectClockSource)
57 || (EUSCI_A_UART_CLOCKSOURCE_SMCLK
58 == config->selectClockSource));
61 (EUSCI_A_UART_MSB_FIRST == config->msborLsbFirst)
62 || (EUSCI_A_UART_LSB_FIRST == config->msborLsbFirst));
65 (EUSCI_A_UART_ONE_STOP_BIT == config->numberofStopBits)
66 || (EUSCI_A_UART_TWO_STOP_BITS == config->numberofStopBits));
69 (EUSCI_A_UART_NO_PARITY == config->parity)
70 || (EUSCI_A_UART_ODD_PARITY == config->parity)
71 || (EUSCI_A_UART_EVEN_PARITY == config->parity));
73 /* Disable the USCI Module */
74 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
76 /* Clock source select */
77 EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
78 (EUSCI_A_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_A_CTLW0_SSEL_MASK)
79 | config->selectClockSource;
82 if (config->msborLsbFirst)
83 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 1;
85 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 0;
87 /* UCSPB = 0(1 stop bit) OR 1(2 stop bits) */
88 if (config->numberofStopBits)
89 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 1;
91 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 0;
94 switch (config->parity)
96 case EUSCI_A_UART_NO_PARITY:
97 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 0;
99 case EUSCI_A_UART_ODD_PARITY:
100 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
101 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 0;
103 case EUSCI_A_UART_EVEN_PARITY:
104 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
105 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 1;
109 /* BaudRate Control Register */
110 EUSCI_A_CMSIS(moduleInstance)->BRW = config->clockPrescalar;
111 EUSCI_A_CMSIS(moduleInstance)->MCTLW = ((config->secondModReg << 8)
112 + (config->firstModReg << 4) + config->overSampling);
114 /* Asynchronous mode & 8 bit character select & clear mode */
115 EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
116 (EUSCI_A_CMSIS(moduleInstance)->CTLW0
117 & ~(EUSCI_A_CTLW0_SYNC | EUSCI_A_CTLW0_SEVENBIT | EUSCI_A_CTLW0_MODE_3 | EUSCI_A_CTLW0_RXEIE | EUSCI_A_CTLW0_BRKIE | EUSCI_A_CTLW0_DORM
118 | EUSCI_A_CTLW0_TXADDR | EUSCI_A_CTLW0_TXBRK)) | config->uartMode;
123 void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
125 /* If interrupts are not used, poll for flags */
126 if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
127 while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
130 EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitData;
133 uint8_t UART_receiveData(uint32_t moduleInstance)
135 /* If interrupts are not used, poll for flags */
136 if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__RXIE_OFS))
137 while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_RXIFG_OFS))
140 return EUSCI_A_CMSIS(moduleInstance)->RXBUF;
143 void UART_enableModule(uint32_t moduleInstance)
145 /* Reset the UCSWRST bit to enable the USCI Module */
146 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
149 void UART_disableModule(uint32_t moduleInstance)
151 /* Set the UCSWRST bit to disable the USCI Module */
152 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
155 uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, uint_fast8_t mask)
159 && (EUSCI_A_UART_LISTEN_ENABLE + EUSCI_A_UART_FRAMING_ERROR
160 + EUSCI_A_UART_OVERRUN_ERROR
161 + EUSCI_A_UART_PARITY_ERROR
162 + EUSCI_A_UART_BREAK_DETECT
163 + EUSCI_A_UART_RECEIVE_ERROR
164 + EUSCI_A_UART_ADDRESS_RECEIVED
165 + EUSCI_A_UART_IDLELINE + EUSCI_A_UART_BUSY));
167 return EUSCI_A_CMSIS(moduleInstance)->STATW & mask;
170 void UART_setDormant(uint32_t moduleInstance)
172 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 1;
175 void UART_resetDormant(uint32_t moduleInstance)
177 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 0;
180 void UART_transmitAddress(uint32_t moduleInstance, uint_fast8_t transmitAddress)
182 /* Set UCTXADDR bit */
183 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXADDR_OFS) = 1;
185 /* Place next byte to be sent into the transmit buffer */
186 EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitAddress;
189 void UART_transmitBreak(uint32_t moduleInstance)
191 /* Set UCTXADDR bit */
192 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXBRK_OFS) = 1;
194 /* If current mode is automatic baud-rate detection */
195 if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
196 == (EUSCI_A_CMSIS(moduleInstance)->CTLW0
197 & EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))
198 EUSCI_A_CMSIS(moduleInstance)->TXBUF =
199 EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;
201 EUSCI_A_CMSIS(moduleInstance)->TXBUF = DEFAULT_SYNC;
203 /* If interrupts are not used, poll for flags */
204 if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
205 while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
209 uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
211 return (uint32_t)&EUSCI_A_CMSIS(moduleInstance)->RXBUF;
214 uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
216 return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF;
219 void UART_selectDeglitchTime(uint32_t moduleInstance, uint32_t deglitchTime)
222 (EUSCI_A_UART_DEGLITCH_TIME_2ns == deglitchTime)
223 || (EUSCI_A_UART_DEGLITCH_TIME_50ns == deglitchTime)
224 || (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime)
225 || (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime));
227 EUSCI_A_CMSIS(moduleInstance)->CTLW1 =
228 (EUSCI_A_CMSIS(moduleInstance)->CTLW1 & ~(EUSCI_A_CTLW1_GLIT_MASK))
233 void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
235 uint_fast8_t locMask;
239 & ~(EUSCI_A_UART_RECEIVE_INTERRUPT
240 | EUSCI_A_UART_TRANSMIT_INTERRUPT
241 | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
242 | EUSCI_A_UART_BREAKCHAR_INTERRUPT
243 | EUSCI_A_UART_STARTBIT_INTERRUPT
244 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
247 & (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
248 | EUSCI_A_UART_STARTBIT_INTERRUPT
249 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
251 EUSCI_A_CMSIS(moduleInstance)->IE |= locMask;
254 & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
255 | EUSCI_A_UART_BREAKCHAR_INTERRUPT));
256 EUSCI_A_CMSIS(moduleInstance)->CTLW0 |= locMask;
259 void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
261 uint_fast8_t locMask;
265 & ~(EUSCI_A_UART_RECEIVE_INTERRUPT
266 | EUSCI_A_UART_TRANSMIT_INTERRUPT
267 | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
268 | EUSCI_A_UART_BREAKCHAR_INTERRUPT
269 | EUSCI_A_UART_STARTBIT_INTERRUPT
270 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
273 & (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
274 | EUSCI_A_UART_STARTBIT_INTERRUPT
275 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
276 EUSCI_A_CMSIS(moduleInstance)->IE &= ~locMask;
279 & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
280 | EUSCI_A_UART_BREAKCHAR_INTERRUPT));
281 EUSCI_A_CMSIS(moduleInstance)->CTLW0 &= ~locMask;
284 uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask)
288 & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
289 | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
290 | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
291 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
293 return EUSCI_A_CMSIS(moduleInstance)->IFG & mask;
296 uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance)
298 uint_fast8_t intStatus = UART_getInterruptStatus(moduleInstance,
299 EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG);
300 uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->IE;
302 if (!(intEnabled & EUSCI_A_UART_RECEIVE_INTERRUPT))
304 intStatus &= ~EUSCI_A_UART_RECEIVE_INTERRUPT;
307 if (!(intEnabled & EUSCI_A_UART_TRANSMIT_INTERRUPT))
309 intStatus &= ~EUSCI_A_UART_TRANSMIT_INTERRUPT;
312 intEnabled = EUSCI_A_CMSIS(moduleInstance)->CTLW0;
314 if (!(intEnabled & EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT))
316 intStatus &= ~EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT;
319 if (!(intEnabled & EUSCI_A_UART_BREAKCHAR_INTERRUPT))
321 intStatus &= ~EUSCI_A_UART_BREAKCHAR_INTERRUPT;
327 void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
331 & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
332 | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
333 | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
334 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
336 //Clear the UART interrupt source.
337 EUSCI_A_CMSIS(moduleInstance)->IFG &= ~(mask);
340 void UART_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
342 switch (moduleInstance)
345 Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
346 Interrupt_enableInterrupt(INT_EUSCIA0);
349 Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
350 Interrupt_enableInterrupt(INT_EUSCIA1);
354 Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
355 Interrupt_enableInterrupt(INT_EUSCIA2);
360 Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
361 Interrupt_enableInterrupt(INT_EUSCIA3);
369 void UART_unregisterInterrupt(uint32_t moduleInstance)
371 switch (moduleInstance)
374 Interrupt_disableInterrupt(INT_EUSCIA0);
375 Interrupt_unregisterInterrupt(INT_EUSCIA0);
378 Interrupt_disableInterrupt(INT_EUSCIA1);
379 Interrupt_unregisterInterrupt(INT_EUSCIA1);
383 Interrupt_disableInterrupt(INT_EUSCIA2);
384 Interrupt_unregisterInterrupt(INT_EUSCIA2);
389 Interrupt_disableInterrupt(INT_EUSCIA3);
390 Interrupt_unregisterInterrupt(INT_EUSCIA3);