1 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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5 ; <h> Stack Configuration
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6 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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9 Stack_Size EQU 0x00000200
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11 AREA STACK, NOINIT, READWRITE, ALIGN=3
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12 Stack_Mem SPACE Stack_Size
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16 ; <h> Heap Configuration
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17 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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20 Heap_Size EQU 0x00000000
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22 AREA HEAP, NOINIT, READWRITE, ALIGN=3
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24 Heap_Mem SPACE Heap_Size
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32 ; Vector Table Mapped to Address 0 at Reset
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34 AREA RESET, DATA, READONLY
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36 EXPORT __Vectors_End
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37 EXPORT __Vectors_Size
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38 IMPORT vUART_Handler
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39 IMPORT vT32_0_Handler
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40 IMPORT vT32_1_Handler
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42 __Vectors DCD __initial_sp ; Top of Stack
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43 DCD Reset_Handler ; Reset Handler
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44 DCD NMI_Handler ; NMI Handler
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45 DCD HardFault_Handler ; Hard Fault Handler
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53 DCD SVC_Handler ; SVCall Handler
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56 DCD PendSV_Handler ; PendSV Handler
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57 DCD SysTick_Handler ; SysTick Handler
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59 ; External Interrupts
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60 DCD IntDefault_Handler ; PSS ISR
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61 DCD IntDefault_Handler ; CS ISR
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62 DCD IntDefault_Handler ; PCM ISR
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63 DCD IntDefault_Handler ; WDT ISR
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64 DCD IntDefault_Handler ; FPU ISR
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65 DCD IntDefault_Handler ; FLCTL ISR
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66 DCD IntDefault_Handler ; COMP0 ISR
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67 DCD IntDefault_Handler ; COMP1 ISR
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68 DCD IntDefault_Handler ; TA0_0 ISR
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69 DCD IntDefault_Handler ; TA0_N ISR
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70 DCD IntDefault_Handler ; TA1_0 ISR
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71 DCD IntDefault_Handler ; TA1_N ISR
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72 DCD IntDefault_Handler ; TA2_0 ISR
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73 DCD IntDefault_Handler ; TA2_N ISR
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74 DCD IntDefault_Handler ; TA3_0 ISR
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75 DCD IntDefault_Handler ; TA3_N ISR
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76 DCD vUART_Handler ; EUSCIA0 ISR
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77 DCD IntDefault_Handler ; EUSCIA1 ISR
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78 DCD IntDefault_Handler ; EUSCIA2 ISR
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79 DCD IntDefault_Handler ; EUSCIA3 ISR
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80 DCD IntDefault_Handler ; EUSCIB0 ISR
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81 DCD IntDefault_Handler ; EUSCIB1 ISR
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82 DCD IntDefault_Handler ; EUSCIB2 ISR
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83 DCD IntDefault_Handler ; EUSCIB3 ISR
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84 DCD IntDefault_Handler ; ADC12 ISR
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85 DCD vT32_0_Handler ; T32_INT1 ISR
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86 DCD vT32_1_Handler ; T32_INT2 ISR
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87 DCD IntDefault_Handler ; T32_INTC ISR
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88 DCD IntDefault_Handler ; AES ISR
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89 DCD IntDefault_Handler ; RTC ISR
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90 DCD IntDefault_Handler ; DMA_ERR ISR
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91 DCD IntDefault_Handler ; DMA_INT3 ISR
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92 DCD IntDefault_Handler ; DMA_INT2 ISR
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93 DCD IntDefault_Handler ; DMA_INT1 ISR
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94 DCD IntDefault_Handler ; DMA_INT0 ISR
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95 DCD IntDefault_Handler ; PORT1 ISR
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96 DCD IntDefault_Handler ; PORT2 ISR
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97 DCD IntDefault_Handler ; PORT3 ISR
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98 DCD IntDefault_Handler ; PORT4 ISR
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99 DCD IntDefault_Handler ; PORT5 ISR
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100 DCD IntDefault_Handler ; PORT6 ISR
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101 DCD IntDefault_Handler ; Reserved 41
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102 DCD IntDefault_Handler ; Reserved 42
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103 DCD IntDefault_Handler ; Reserved 43
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104 DCD IntDefault_Handler ; Reserved 44
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105 DCD IntDefault_Handler ; Reserved 45
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106 DCD IntDefault_Handler ; Reserved 46
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107 DCD IntDefault_Handler ; Reserved 47
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108 DCD IntDefault_Handler ; Reserved 48
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109 DCD IntDefault_Handler ; Reserved 49
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110 DCD IntDefault_Handler ; Reserved 50
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111 DCD IntDefault_Handler ; Reserved 51
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112 DCD IntDefault_Handler ; Reserved 52
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113 DCD IntDefault_Handler ; Reserved 53
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114 DCD IntDefault_Handler ; Reserved 54
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115 DCD IntDefault_Handler ; Reserved 55
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116 DCD IntDefault_Handler ; Reserved 56
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117 DCD IntDefault_Handler ; Reserved 57
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118 DCD IntDefault_Handler ; Reserved 58
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119 DCD IntDefault_Handler ; Reserved 59
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120 DCD IntDefault_Handler ; Reserved 60
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121 DCD IntDefault_Handler ; Reserved 61
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122 DCD IntDefault_Handler ; Reserved 62
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123 DCD IntDefault_Handler ; Reserved 63
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124 DCD IntDefault_Handler ; Reserved 64
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127 __Vectors_Size EQU __Vectors_End - __Vectors
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129 AREA |.text|, CODE, READONLY
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135 EXPORT Reset_Handler [WEAK]
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138 LDR R0, =SystemInit
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145 ; Dummy Exception Handlers (infinite loops which can be modified)
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148 EXPORT NMI_Handler [WEAK]
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153 EXPORT HardFault_Handler [WEAK]
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157 EXPORT SVC_Handler [WEAK]
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160 PendSV_Handler PROC
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161 EXPORT PendSV_Handler [WEAK]
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164 SysTick_Handler PROC
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165 EXPORT SysTick_Handler [WEAK]
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168 IntDefault_Handler PROC
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169 EXPORT IntDefault_Handler [WEAK]
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176 ; User Initial Stack & Heap
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180 EXPORT __initial_sp
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182 EXPORT __heap_limit
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186 IMPORT __use_two_region_memory
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187 EXPORT __user_initial_stackheap
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188 __user_initial_stackheap
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191 LDR R1, =(Stack_Mem + Stack_Size)
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192 LDR R2, = (Heap_Mem + Heap_Size)
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193 LDR R3, = Stack_Mem
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