1 /**************************************************************************//**
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2 * @file system_msp432p401r.c
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3 * @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
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8 * @note View configuration instructions embedded in comments
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10 ******************************************************************************/
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11 //*****************************************************************************
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13 // Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
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15 // Redistribution and use in source and binary forms, with or without
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16 // modification, are permitted provided that the following conditions
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19 // Redistributions of source code must retain the above copyright
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20 // notice, this list of conditions and the following disclaimer.
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22 // Redistributions in binary form must reproduce the above copyright
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23 // notice, this list of conditions and the following disclaimer in the
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24 // documentation and/or other materials provided with the
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27 // Neither the name of Texas Instruments Incorporated nor the names of
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28 // its contributors may be used to endorse or promote products derived
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29 // from this software without specific prior written permission.
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31 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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32 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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34 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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35 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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36 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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37 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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39 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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40 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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41 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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43 //*****************************************************************************
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48 /*--------------------- Configuration Instructions ----------------------------
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49 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
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50 #define __HALT_WDT 1
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51 2. Insert your desired CPU frequency in Hz at:
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52 #define __SYSTEM_CLOCK 3000000
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53 3. If you prefer the DC-DC power regulator (more efficient at higher
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54 frequencies), set the __REGULATOR to 1:
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55 #define __REGULATOR 1
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56 *---------------------------------------------------------------------------*/
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58 /*--------------------- Watchdog Timer Configuration ------------------------*/
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59 // Halt the Watchdog Timer
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60 // <0> Do not halt the WDT
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62 #define __HALT_WDT 1
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64 /*--------------------- CPU Frequency Configuration -------------------------*/
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66 // <1500000> 1.5 MHz
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68 // <12000000> 12 MHz
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69 // <24000000> 24 MHz
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70 // <48000000> 48 MHz
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71 #define __SYSTEM_CLOCK 1500000
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73 /*--------------------- Power Regulator Configuration -----------------------*/
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74 // Power Regulator Mode
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77 #define __REGULATOR 1
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79 /*----------------------------------------------------------------------------
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80 Define clocks, used for SystemCoreClockUpdate()
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81 *---------------------------------------------------------------------------*/
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82 #define __VLOCLK 10000
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83 #define __MODCLK 24000000
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84 #define __LFXT 32768
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85 #define __HFXT 48000000
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87 /*----------------------------------------------------------------------------
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88 Clock Variable definitions
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89 *---------------------------------------------------------------------------*/
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90 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
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93 * Update SystemCoreClock variable
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98 * @brief Updates the SystemCoreClock with current core Clock
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99 * retrieved from cpu registers.
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101 void SystemCoreClockUpdate(void)
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103 uint32_t source, divider;
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104 uint8_t dividerValue;
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108 uint32_t centeredFreq;
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111 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
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112 dividerValue = 1 << divider;
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113 source = CS->CTL1 & CS_CTL1_SELM_MASK;
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117 case CS_CTL1_SELM__LFXTCLK:
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118 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
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120 // Clear interrupt flag
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121 CS->KEY = CS_KEY_VAL;
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122 CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
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125 if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
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127 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
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129 SystemCoreClock = (128000 / dividerValue);
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133 SystemCoreClock = (32000 / dividerValue);
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138 SystemCoreClock = __LFXT / dividerValue;
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143 SystemCoreClock = __LFXT / dividerValue;
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146 case CS_CTL1_SELM__VLOCLK:
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147 SystemCoreClock = __VLOCLK / dividerValue;
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149 case CS_CTL1_SELM__REFOCLK:
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150 if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
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152 SystemCoreClock = (128000 / dividerValue);
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156 SystemCoreClock = (32000 / dividerValue);
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159 case CS_CTL1_SELM__DCOCLK:
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160 dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
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162 switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
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164 case CS_CTL0_DCORSEL_0:
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165 centeredFreq = 1500000;
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167 case CS_CTL0_DCORSEL_1:
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168 centeredFreq = 3000000;
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170 case CS_CTL0_DCORSEL_2:
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171 centeredFreq = 6000000;
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173 case CS_CTL0_DCORSEL_3:
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174 centeredFreq = 12000000;
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176 case CS_CTL0_DCORSEL_4:
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177 centeredFreq = 24000000;
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179 case CS_CTL0_DCORSEL_5:
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180 centeredFreq = 48000000;
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186 SystemCoreClock = centeredFreq;
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191 if(dcoTune & 0x1000)
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193 dcoTune = dcoTune | 0xF000;
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196 if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
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198 dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
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199 calVal = TLV->DCOER_FCAL_RSEL04;
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201 /* Internal Resistor */
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204 dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
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205 calVal = TLV->DCOIR_FCAL_RSEL04;
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208 SystemCoreClock = (uint32_t) ((centeredFreq)
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210 - ((dcoConst * dcoTune)
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211 / (8 * (1 + dcoConst * (768 - calVal))))));
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214 case CS_CTL1_SELM__MODOSC:
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215 SystemCoreClock = __MODCLK / dividerValue;
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217 case CS_CTL1_SELM__HFXTCLK:
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218 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
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220 // Clear interrupt flag
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221 CS->KEY = CS_KEY_VAL;
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222 CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
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225 if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
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227 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
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229 SystemCoreClock = (128000 / dividerValue);
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233 SystemCoreClock = (32000 / dividerValue);
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238 SystemCoreClock = __HFXT / dividerValue;
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243 SystemCoreClock = __HFXT / dividerValue;
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250 * Initialize the system
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255 * @brief Setup the microcontroller system.
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257 * Performs the following initialization steps:
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258 * 1. Enables the FPU
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259 * 2. Halts the WDT if requested
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260 * 3. Enables all SRAM banks
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261 * 4. Sets up power regulator and VCORE
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262 * 5. Enable Flash wait states if needed
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263 * 6. Change MCLK to desired frequency
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264 * 7. Enable Flash read buffering
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266 void SystemInit(void)
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268 // Enable FPU if used
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269 #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
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270 SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
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271 (3UL << 11 * 2)); /* Set CP11 Full Access */
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274 #if (__HALT_WDT == 1)
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275 WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
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278 SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
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280 #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
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281 // Default VCORE is LDO VCORE0 so no change necessary
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283 // Switches LDO VCORE0 to DCDC VCORE0 if requested
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285 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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286 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
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287 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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290 // No flash wait states necessary
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292 // DCO = 1.5 MHz; MCLK = source
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293 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
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294 CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
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295 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
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298 // Set Flash Bank read buffering
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299 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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300 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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302 #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
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303 // Default VCORE is LDO VCORE0 so no change necessary
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305 // Switches LDO VCORE0 to DCDC VCORE0 if requested
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307 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
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308 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
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309 while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
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312 // No flash wait states necessary
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314 // DCO = 3 MHz; MCLK = source
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315 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
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316 CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
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317 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
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320 // Set Flash Bank read buffering
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321 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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322 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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324 #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
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325 // Default VCORE is LDO VCORE0 so no change necessary
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327 // Switches LDO VCORE0 to DCDC VCORE0 if requested
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329 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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330 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
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331 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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334 // No flash wait states necessary
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336 // DCO = 12 MHz; MCLK = source
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337 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
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338 CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
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339 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
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342 // Set Flash Bank read buffering
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343 FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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344 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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346 #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
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347 // Default VCORE is LDO VCORE0 so no change necessary
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349 // Switches LDO VCORE0 to DCDC VCORE0 if requested
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351 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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352 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
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353 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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356 // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
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357 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
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358 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
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360 // DCO = 24 MHz; MCLK = source
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361 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
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362 CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
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363 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
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366 // Set Flash Bank read buffering
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367 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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368 FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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370 #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
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371 // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
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372 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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373 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
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374 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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376 // Switches LDO VCORE1 to DCDC VCORE1 if requested
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378 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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379 PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
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380 while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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383 // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
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384 FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
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385 FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
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387 // DCO = 48 MHz; MCLK = source
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388 CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
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389 CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
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390 CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
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393 // Set Flash Bank read buffering
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394 FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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395 FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
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