2 ******************************************************************************
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3 * @file system_stm32f4xx.c
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4 * @author MCD Application Team
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6 * @date 30-September-2011
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7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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8 * This file contains the system clock configuration for STM32F4xx devices,
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9 * and is generated by the clock configuration tool
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10 * stm32f4xx_Clock_Configuration_V1.0.0.xls
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12 * 1. This file provides two functions and one global variable to be called from
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14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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15 * and Divider factors, AHB/APBx prescalers and Flash settings),
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16 * depending on the configuration made in the clock xls tool.
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17 * This function is called at startup just after reset and
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18 * before branch to main program. This call is made inside
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19 * the "startup_stm32f4xx.s" file.
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21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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22 * by the user application to setup the SysTick
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23 * timer or configure other parameters.
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25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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26 * be called whenever the core clock is changed
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27 * during program execution.
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29 * 2. After each device reset the HSI (16 MHz) is used as system clock source.
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30 * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
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31 * configure the system clock before to branch to main program.
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33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
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34 * function will do nothing and HSI still used as system clock source. User can
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35 * add some code to deal with this issue inside the SetSysClock() function.
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37 * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
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38 * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
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39 * through PLL, and you are using different crystal you have to adapt the HSE
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40 * value to your own configuration.
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42 * 5. This file configures the system clock as follows:
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43 *=============================================================================
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44 *=============================================================================
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45 * Supported STM32F4xx device revision | Rev A
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46 *-----------------------------------------------------------------------------
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47 * System Clock source | PLL (HSE)
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48 *-----------------------------------------------------------------------------
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49 * SYSCLK(Hz) | 168000000
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50 *-----------------------------------------------------------------------------
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51 * HCLK(Hz) | 168000000
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52 *-----------------------------------------------------------------------------
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54 *-----------------------------------------------------------------------------
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55 * APB1 Prescaler | 4
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56 *-----------------------------------------------------------------------------
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57 * APB2 Prescaler | 2
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58 *-----------------------------------------------------------------------------
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59 * HSE Frequency(Hz) | 25000000
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60 *-----------------------------------------------------------------------------
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62 *-----------------------------------------------------------------------------
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64 *-----------------------------------------------------------------------------
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66 *-----------------------------------------------------------------------------
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68 *-----------------------------------------------------------------------------
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70 *-----------------------------------------------------------------------------
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72 *-----------------------------------------------------------------------------
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73 * I2S input clock | NA
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74 *-----------------------------------------------------------------------------
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76 *-----------------------------------------------------------------------------
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77 * Main regulator output voltage | Scale1 mode
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78 *-----------------------------------------------------------------------------
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79 * Flash Latency(WS) | 5
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80 *-----------------------------------------------------------------------------
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81 * Prefetch Buffer | OFF
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82 *-----------------------------------------------------------------------------
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83 * Instruction cache | ON
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84 *-----------------------------------------------------------------------------
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86 *-----------------------------------------------------------------------------
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87 * Require 48MHz for USB OTG FS, | Enabled
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88 * SDIO and RNG clock |
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89 *-----------------------------------------------------------------------------
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90 *=============================================================================
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91 ******************************************************************************
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94 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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95 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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96 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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97 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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98 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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99 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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101 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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102 ******************************************************************************
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105 /** @addtogroup CMSIS
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109 /** @addtogroup stm32f4xx_system
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113 /** @addtogroup STM32F4xx_System_Private_Includes
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117 #include "stm32f4xx.h"
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123 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
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131 /** @addtogroup STM32F4xx_System_Private_Defines
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135 /************************* Miscellaneous Configuration ************************/
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136 /*!< Uncomment the following line if you need to use external SRAM mounted
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137 on STM324xG_EVAL board as data memory */
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138 /* #define DATA_IN_ExtSRAM */
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140 /*!< Uncomment the following line if you need to relocate your vector Table in
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142 /* #define VECT_TAB_SRAM */
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143 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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144 This value must be a multiple of 0x200. */
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145 /******************************************************************************/
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147 /************************* PLL Parameters *************************************/
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148 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
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152 /* SYSCLK = PLL_VCO / PLL_P */
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155 /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
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158 /******************************************************************************/
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164 /** @addtogroup STM32F4xx_System_Private_Macros
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172 /** @addtogroup STM32F4xx_System_Private_Variables
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176 uint32_t SystemCoreClock = 168000000;
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178 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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184 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
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188 static void SetSysClock(void);
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189 #ifdef DATA_IN_ExtSRAM
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190 static void SystemInit_ExtMemCtl(void);
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191 #endif /* DATA_IN_ExtSRAM */
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197 /** @addtogroup STM32F4xx_System_Private_Functions
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202 * @brief Setup the microcontroller system
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203 * Initialize the Embedded Flash Interface, the PLL and update the
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204 * SystemFrequency variable.
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208 void SystemInit(void)
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210 /* FPU settings ------------------------------------------------------------*/
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211 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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212 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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215 /* Reset the RCC clock configuration to the default reset state ------------*/
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216 /* Set HSION bit */
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217 RCC->CR |= (uint32_t)0x00000001;
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219 /* Reset CFGR register */
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220 RCC->CFGR = 0x00000000;
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222 /* Reset HSEON, CSSON and PLLON bits */
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223 RCC->CR &= (uint32_t)0xFEF6FFFF;
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225 /* Reset PLLCFGR register */
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226 RCC->PLLCFGR = 0x24003010;
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228 /* Reset HSEBYP bit */
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229 RCC->CR &= (uint32_t)0xFFFBFFFF;
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231 /* Disable all interrupts */
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232 RCC->CIR = 0x00000000;
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234 #ifdef DATA_IN_ExtSRAM
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235 SystemInit_ExtMemCtl();
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236 #endif /* DATA_IN_ExtSRAM */
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238 /* Configure the System clock source, PLL Multiplier and Divider factors,
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239 AHB/APBx prescalers and Flash settings ----------------------------------*/
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242 /* Configure the Vector Table location add offset address ------------------*/
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243 #ifdef VECT_TAB_SRAM
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244 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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246 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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251 * @brief Update SystemCoreClock variable according to Clock Register Values.
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252 * The SystemCoreClock variable contains the core clock (HCLK), it can
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253 * be used by the user application to setup the SysTick timer or configure
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254 * other parameters.
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256 * @note Each time the core clock (HCLK) changes, this function must be called
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257 * to update SystemCoreClock variable value. Otherwise, any configuration
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258 * based on this variable will be incorrect.
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260 * @note - The system frequency computed by this function is not the real
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261 * frequency in the chip. It is calculated based on the predefined
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262 * constant and the selected clock source:
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264 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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266 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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268 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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269 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
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271 * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
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272 * 16 MHz) but the real value may vary depending on the variations
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273 * in voltage and temperature.
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275 * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
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276 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
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277 * frequency of the crystal used. Otherwise, this function may
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278 * have wrong result.
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280 * - The result of this function could be not correct when using fractional
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281 * value for HSE crystal.
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286 void SystemCoreClockUpdate(void)
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288 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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290 /* Get SYSCLK source -------------------------------------------------------*/
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291 tmp = RCC->CFGR & RCC_CFGR_SWS;
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295 case 0x00: /* HSI used as system clock source */
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296 SystemCoreClock = HSI_VALUE;
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298 case 0x04: /* HSE used as system clock source */
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299 SystemCoreClock = HSE_VALUE;
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301 case 0x08: /* PLL used as system clock source */
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303 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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304 SYSCLK = PLL_VCO / PLL_P
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306 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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307 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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309 if (pllsource != 0)
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311 /* HSE used as PLL clock source */
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312 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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316 /* HSI used as PLL clock source */
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317 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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320 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
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321 SystemCoreClock = pllvco/pllp;
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324 SystemCoreClock = HSI_VALUE;
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327 /* Compute HCLK frequency --------------------------------------------------*/
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328 /* Get HCLK prescaler */
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329 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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330 /* HCLK frequency */
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331 SystemCoreClock >>= tmp;
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335 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
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336 * AHB/APBx prescalers and Flash settings
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337 * @Note This function should be called only once the RCC clock configuration
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338 * is reset to the default reset state (done in SystemInit() function).
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342 static void SetSysClock(void)
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344 /******************************************************************************/
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345 /* PLL (clocked by HSE) used as System clock source */
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346 /******************************************************************************/
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347 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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350 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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352 /* Wait till HSE is ready and if Time out is reached exit */
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355 HSEStatus = RCC->CR & RCC_CR_HSERDY;
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357 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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359 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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361 HSEStatus = (uint32_t)0x01;
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365 HSEStatus = (uint32_t)0x00;
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368 if (HSEStatus == (uint32_t)0x01)
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370 /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
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371 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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372 PWR->CR |= PWR_CR_VOS;
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374 /* HCLK = SYSCLK / 1*/
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375 RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
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377 /* PCLK2 = HCLK / 2*/
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378 RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
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380 /* PCLK1 = HCLK / 4*/
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381 RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
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383 /* Configure the main PLL */
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384 RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
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385 (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
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387 /* Enable the main PLL */
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388 RCC->CR |= RCC_CR_PLLON;
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390 /* Wait till the main PLL is ready */
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391 while((RCC->CR & RCC_CR_PLLRDY) == 0)
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395 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
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396 FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
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398 /* Select the main PLL as system clock source */
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399 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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400 RCC->CFGR |= RCC_CFGR_SW_PLL;
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402 /* Wait till the main PLL is used as system clock source */
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403 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
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408 { /* If HSE fails to start-up, the application will have wrong clock
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409 configuration. User can add here some code to deal with this error */
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415 * @brief Setup the external memory controller. Called in startup_stm32f4xx.s
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416 * before jump to __main
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420 #ifdef DATA_IN_ExtSRAM
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422 * @brief Setup the external memory controller.
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423 * Called in startup_stm32f4xx.s before jump to main.
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424 * This function configures the external SRAM mounted on STM324xG_EVAL board
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425 * This SRAM will be used as program data memory (including heap and stack).
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429 void SystemInit_ExtMemCtl(void)
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431 /*-- GPIOs Configuration -----------------------------------------------------*/
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433 +-------------------+--------------------+------------------+------------------+
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434 + SRAM pins assignment +
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435 +-------------------+--------------------+------------------+------------------+
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436 | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
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437 | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
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438 | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
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439 | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
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440 | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
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441 | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
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442 | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
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443 | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+
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444 | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 |
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445 | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 |
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446 | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+
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447 | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
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448 | | PE15 <-> FSMC_D12 |
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449 +-------------------+--------------------+
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451 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
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452 RCC->AHB1ENR = 0x00000078;
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454 /* Connect PDx pins to FSMC Alternate function */
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455 GPIOD->AFR[0] = 0x00cc00cc;
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456 GPIOD->AFR[1] = 0xcc0ccccc;
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457 /* Configure PDx pins in Alternate function mode */
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458 GPIOD->MODER = 0xaaaa0a0a;
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459 /* Configure PDx pins speed to 100 MHz */
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460 GPIOD->OSPEEDR = 0xffff0f0f;
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461 /* Configure PDx pins Output type to push-pull */
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462 GPIOD->OTYPER = 0x00000000;
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463 /* No pull-up, pull-down for PDx pins */
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464 GPIOD->PUPDR = 0x00000000;
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466 /* Connect PEx pins to FSMC Alternate function */
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467 GPIOE->AFR[0] = 0xc00cc0cc;
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468 GPIOE->AFR[1] = 0xcccccccc;
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469 /* Configure PEx pins in Alternate function mode */
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470 GPIOE->MODER = 0xaaaa828a;
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471 /* Configure PEx pins speed to 100 MHz */
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472 GPIOE->OSPEEDR = 0xffffc3cf;
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473 /* Configure PEx pins Output type to push-pull */
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474 GPIOE->OTYPER = 0x00000000;
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475 /* No pull-up, pull-down for PEx pins */
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476 GPIOE->PUPDR = 0x00000000;
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478 /* Connect PFx pins to FSMC Alternate function */
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479 GPIOF->AFR[0] = 0x00cccccc;
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480 GPIOF->AFR[1] = 0xcccc0000;
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481 /* Configure PFx pins in Alternate function mode */
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482 GPIOF->MODER = 0xaa000aaa;
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483 /* Configure PFx pins speed to 100 MHz */
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484 GPIOF->OSPEEDR = 0xff000fff;
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485 /* Configure PFx pins Output type to push-pull */
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486 GPIOF->OTYPER = 0x00000000;
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487 /* No pull-up, pull-down for PFx pins */
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488 GPIOF->PUPDR = 0x00000000;
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490 /* Connect PGx pins to FSMC Alternate function */
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491 GPIOG->AFR[0] = 0x00cccccc;
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492 GPIOG->AFR[1] = 0x000000c0;
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493 /* Configure PGx pins in Alternate function mode */
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494 GPIOG->MODER = 0x00080aaa;
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495 /* Configure PGx pins speed to 100 MHz */
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496 GPIOG->OSPEEDR = 0x000c0fff;
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497 /* Configure PGx pins Output type to push-pull */
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498 GPIOG->OTYPER = 0x00000000;
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499 /* No pull-up, pull-down for PGx pins */
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500 GPIOG->PUPDR = 0x00000000;
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502 /*-- FSMC Configuration ------------------------------------------------------*/
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503 /* Enable the FSMC interface clock */
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504 RCC->AHB3ENR = 0x00000001;
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506 /* Configure and enable Bank1_SRAM2 */
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507 FSMC_Bank1->BTCR[2] = 0x00001015;
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508 FSMC_Bank1->BTCR[3] = 0x00010603;
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509 FSMC_Bank1E->BWTR[2] = 0x0fffffff;
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511 Bank1_SRAM2 is configured as follow:
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513 p.FSMC_AddressSetupTime = 3;
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514 p.FSMC_AddressHoldTime = 0;
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515 p.FSMC_DataSetupTime = 6;
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516 p.FSMC_BusTurnAroundDuration = 1;
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517 p.FSMC_CLKDivision = 0;
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518 p.FSMC_DataLatency = 0;
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519 p.FSMC_AccessMode = FSMC_AccessMode_A;
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521 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
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522 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
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523 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
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524 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
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525 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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526 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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527 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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528 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
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529 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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530 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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531 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
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532 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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533 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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534 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
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535 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
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539 #endif /* DATA_IN_ExtSRAM */
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553 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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