2 ******************************************************************************
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3 * @file stm32f4xx_dma.h
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4 * @author MCD Application Team
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6 * @date 30-September-2011
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7 * @brief This file contains all the functions prototypes for the DMA firmware
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9 ******************************************************************************
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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19 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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20 ******************************************************************************
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23 /* Define to prevent recursive inclusion -------------------------------------*/
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24 #ifndef __STM32F4xx_DMA_H
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25 #define __STM32F4xx_DMA_H
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31 /* Includes ------------------------------------------------------------------*/
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32 #include "stm32f4xx.h"
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34 /** @addtogroup STM32F4xx_StdPeriph_Driver
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42 /* Exported types ------------------------------------------------------------*/
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45 * @brief DMA Init structure definition
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50 uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream.
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51 This parameter can be a value of @ref DMA_channel */
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53 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
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55 uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx.
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56 This memory is the default memory used when double buffer mode is
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59 uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral,
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60 from memory to memory or from peripheral to memory.
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61 This parameter can be a value of @ref DMA_data_transfer_direction */
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63 uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream.
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64 The data unit is equal to the configuration set in DMA_PeripheralDataSize
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65 or DMA_MemoryDataSize members depending in the transfer direction. */
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67 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
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68 This parameter can be a value of @ref DMA_peripheral_incremented_mode */
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70 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.
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71 This parameter can be a value of @ref DMA_memory_incremented_mode */
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73 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
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74 This parameter can be a value of @ref DMA_peripheral_data_size */
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76 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
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77 This parameter can be a value of @ref DMA_memory_data_size */
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79 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.
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80 This parameter can be a value of @ref DMA_circular_normal_mode
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81 @note The circular buffer mode cannot be used if the memory-to-memory
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82 data transfer is configured on the selected Stream */
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84 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.
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85 This parameter can be a value of @ref DMA_priority_level */
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87 uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
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88 This parameter can be a value of @ref DMA_fifo_direct_mode
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89 @note The Direct mode (FIFO mode disabled) cannot be used if the
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90 memory-to-memory data transfer is configured on the selected Stream */
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92 uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.
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93 This parameter can be a value of @ref DMA_fifo_threshold_level */
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95 uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
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96 It specifies the amount of data to be transferred in a single non interruptable
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97 transaction. This parameter can be a value of @ref DMA_memory_burst
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98 @note The burst mode is possible only if the address Increment mode is enabled. */
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100 uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
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101 It specifies the amount of data to be transferred in a single non interruptable
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102 transaction. This parameter can be a value of @ref DMA_peripheral_burst
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103 @note The burst mode is possible only if the address Increment mode is enabled. */
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106 /* Exported constants --------------------------------------------------------*/
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108 /** @defgroup DMA_Exported_Constants
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112 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
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113 ((PERIPH) == DMA1_Stream1) || \
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114 ((PERIPH) == DMA1_Stream2) || \
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115 ((PERIPH) == DMA1_Stream3) || \
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116 ((PERIPH) == DMA1_Stream4) || \
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117 ((PERIPH) == DMA1_Stream5) || \
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118 ((PERIPH) == DMA1_Stream6) || \
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119 ((PERIPH) == DMA1_Stream7) || \
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120 ((PERIPH) == DMA2_Stream0) || \
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121 ((PERIPH) == DMA2_Stream1) || \
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122 ((PERIPH) == DMA2_Stream2) || \
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123 ((PERIPH) == DMA2_Stream3) || \
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124 ((PERIPH) == DMA2_Stream4) || \
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125 ((PERIPH) == DMA2_Stream5) || \
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126 ((PERIPH) == DMA2_Stream6) || \
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127 ((PERIPH) == DMA2_Stream7))
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129 #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
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130 ((CONTROLLER) == DMA2))
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132 /** @defgroup DMA_channel
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135 #define DMA_Channel_0 ((uint32_t)0x00000000)
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136 #define DMA_Channel_1 ((uint32_t)0x02000000)
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137 #define DMA_Channel_2 ((uint32_t)0x04000000)
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138 #define DMA_Channel_3 ((uint32_t)0x06000000)
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139 #define DMA_Channel_4 ((uint32_t)0x08000000)
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140 #define DMA_Channel_5 ((uint32_t)0x0A000000)
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141 #define DMA_Channel_6 ((uint32_t)0x0C000000)
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142 #define DMA_Channel_7 ((uint32_t)0x0E000000)
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144 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
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145 ((CHANNEL) == DMA_Channel_1) || \
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146 ((CHANNEL) == DMA_Channel_2) || \
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147 ((CHANNEL) == DMA_Channel_3) || \
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148 ((CHANNEL) == DMA_Channel_4) || \
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149 ((CHANNEL) == DMA_Channel_5) || \
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150 ((CHANNEL) == DMA_Channel_6) || \
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151 ((CHANNEL) == DMA_Channel_7))
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157 /** @defgroup DMA_data_transfer_direction
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160 #define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)
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161 #define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040)
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162 #define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)
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164 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
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165 ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \
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166 ((DIRECTION) == DMA_DIR_MemoryToMemory))
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172 /** @defgroup DMA_data_buffer_size
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175 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
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181 /** @defgroup DMA_peripheral_incremented_mode
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184 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000200)
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185 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
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187 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
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188 ((STATE) == DMA_PeripheralInc_Disable))
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194 /** @defgroup DMA_memory_incremented_mode
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197 #define DMA_MemoryInc_Enable ((uint32_t)0x00000400)
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198 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
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200 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
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201 ((STATE) == DMA_MemoryInc_Disable))
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207 /** @defgroup DMA_peripheral_data_size
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210 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
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211 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800)
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212 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)
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214 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
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215 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
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216 ((SIZE) == DMA_PeripheralDataSize_Word))
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222 /** @defgroup DMA_memory_data_size
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225 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
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226 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000)
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227 #define DMA_MemoryDataSize_Word ((uint32_t)0x00004000)
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229 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
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230 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
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231 ((SIZE) == DMA_MemoryDataSize_Word ))
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237 /** @defgroup DMA_circular_normal_mode
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240 #define DMA_Mode_Normal ((uint32_t)0x00000000)
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241 #define DMA_Mode_Circular ((uint32_t)0x00000100)
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243 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
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244 ((MODE) == DMA_Mode_Circular))
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250 /** @defgroup DMA_priority_level
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253 #define DMA_Priority_Low ((uint32_t)0x00000000)
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254 #define DMA_Priority_Medium ((uint32_t)0x00010000)
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255 #define DMA_Priority_High ((uint32_t)0x00020000)
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256 #define DMA_Priority_VeryHigh ((uint32_t)0x00030000)
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258 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \
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259 ((PRIORITY) == DMA_Priority_Medium) || \
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260 ((PRIORITY) == DMA_Priority_High) || \
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261 ((PRIORITY) == DMA_Priority_VeryHigh))
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267 /** @defgroup DMA_fifo_direct_mode
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270 #define DMA_FIFOMode_Disable ((uint32_t)0x00000000)
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271 #define DMA_FIFOMode_Enable ((uint32_t)0x00000004)
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273 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
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274 ((STATE) == DMA_FIFOMode_Enable))
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280 /** @defgroup DMA_fifo_threshold_level
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283 #define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)
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284 #define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001)
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285 #define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)
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286 #define DMA_FIFOThreshold_Full ((uint32_t)0x00000003)
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288 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
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289 ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \
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290 ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
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291 ((THRESHOLD) == DMA_FIFOThreshold_Full))
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297 /** @defgroup DMA_memory_burst
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300 #define DMA_MemoryBurst_Single ((uint32_t)0x00000000)
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301 #define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000)
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302 #define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000)
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303 #define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)
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305 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
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306 ((BURST) == DMA_MemoryBurst_INC4) || \
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307 ((BURST) == DMA_MemoryBurst_INC8) || \
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308 ((BURST) == DMA_MemoryBurst_INC16))
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314 /** @defgroup DMA_peripheral_burst
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317 #define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)
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318 #define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000)
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319 #define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)
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320 #define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)
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322 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
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323 ((BURST) == DMA_PeripheralBurst_INC4) || \
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324 ((BURST) == DMA_PeripheralBurst_INC8) || \
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325 ((BURST) == DMA_PeripheralBurst_INC16))
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331 /** @defgroup DMA_fifo_status_level
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334 #define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)
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335 #define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)
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336 #define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3)
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337 #define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)
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338 #define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)
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339 #define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)
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341 #define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
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342 ((STATUS) == DMA_FIFOStatus_HalfFull) || \
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343 ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \
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344 ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \
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345 ((STATUS) == DMA_FIFOStatus_Full) || \
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346 ((STATUS) == DMA_FIFOStatus_Empty))
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351 /** @defgroup DMA_flags_definition
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354 #define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)
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355 #define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)
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356 #define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)
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357 #define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)
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358 #define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)
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359 #define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)
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360 #define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)
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361 #define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)
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362 #define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)
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363 #define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)
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364 #define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)
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365 #define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)
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366 #define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)
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367 #define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)
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368 #define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)
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369 #define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)
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370 #define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)
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371 #define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)
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372 #define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)
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373 #define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)
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374 #define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)
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375 #define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)
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376 #define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)
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377 #define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)
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378 #define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)
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379 #define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)
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380 #define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)
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381 #define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)
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382 #define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)
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383 #define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)
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384 #define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)
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385 #define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)
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386 #define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)
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387 #define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)
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388 #define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)
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389 #define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)
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390 #define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)
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391 #define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)
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392 #define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)
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393 #define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
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395 #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
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396 (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00))
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398 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
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399 ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
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400 ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \
\r
401 ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \
\r
402 ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \
\r
403 ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \
\r
404 ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \
\r
405 ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \
\r
406 ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \
\r
407 ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \
\r
408 ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \
\r
409 ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \
\r
410 ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \
\r
411 ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \
\r
412 ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \
\r
413 ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \
\r
414 ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \
\r
415 ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \
\r
416 ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \
\r
417 ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
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423 /** @defgroup DMA_interrupt_enable_definitions
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426 #define DMA_IT_TC ((uint32_t)0x00000010)
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427 #define DMA_IT_HT ((uint32_t)0x00000008)
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428 #define DMA_IT_TE ((uint32_t)0x00000004)
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429 #define DMA_IT_DME ((uint32_t)0x00000002)
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430 #define DMA_IT_FE ((uint32_t)0x00000080)
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432 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
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438 /** @defgroup DMA_interrupts_definitions
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441 #define DMA_IT_FEIF0 ((uint32_t)0x90000001)
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442 #define DMA_IT_DMEIF0 ((uint32_t)0x10001004)
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443 #define DMA_IT_TEIF0 ((uint32_t)0x10002008)
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444 #define DMA_IT_HTIF0 ((uint32_t)0x10004010)
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445 #define DMA_IT_TCIF0 ((uint32_t)0x10008020)
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446 #define DMA_IT_FEIF1 ((uint32_t)0x90000040)
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447 #define DMA_IT_DMEIF1 ((uint32_t)0x10001100)
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448 #define DMA_IT_TEIF1 ((uint32_t)0x10002200)
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449 #define DMA_IT_HTIF1 ((uint32_t)0x10004400)
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450 #define DMA_IT_TCIF1 ((uint32_t)0x10008800)
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451 #define DMA_IT_FEIF2 ((uint32_t)0x90010000)
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452 #define DMA_IT_DMEIF2 ((uint32_t)0x10041000)
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453 #define DMA_IT_TEIF2 ((uint32_t)0x10082000)
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454 #define DMA_IT_HTIF2 ((uint32_t)0x10104000)
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455 #define DMA_IT_TCIF2 ((uint32_t)0x10208000)
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456 #define DMA_IT_FEIF3 ((uint32_t)0x90400000)
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457 #define DMA_IT_DMEIF3 ((uint32_t)0x11001000)
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458 #define DMA_IT_TEIF3 ((uint32_t)0x12002000)
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459 #define DMA_IT_HTIF3 ((uint32_t)0x14004000)
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460 #define DMA_IT_TCIF3 ((uint32_t)0x18008000)
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461 #define DMA_IT_FEIF4 ((uint32_t)0xA0000001)
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462 #define DMA_IT_DMEIF4 ((uint32_t)0x20001004)
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463 #define DMA_IT_TEIF4 ((uint32_t)0x20002008)
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464 #define DMA_IT_HTIF4 ((uint32_t)0x20004010)
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465 #define DMA_IT_TCIF4 ((uint32_t)0x20008020)
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466 #define DMA_IT_FEIF5 ((uint32_t)0xA0000040)
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467 #define DMA_IT_DMEIF5 ((uint32_t)0x20001100)
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468 #define DMA_IT_TEIF5 ((uint32_t)0x20002200)
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469 #define DMA_IT_HTIF5 ((uint32_t)0x20004400)
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470 #define DMA_IT_TCIF5 ((uint32_t)0x20008800)
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471 #define DMA_IT_FEIF6 ((uint32_t)0xA0010000)
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472 #define DMA_IT_DMEIF6 ((uint32_t)0x20041000)
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473 #define DMA_IT_TEIF6 ((uint32_t)0x20082000)
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474 #define DMA_IT_HTIF6 ((uint32_t)0x20104000)
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475 #define DMA_IT_TCIF6 ((uint32_t)0x20208000)
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476 #define DMA_IT_FEIF7 ((uint32_t)0xA0400000)
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477 #define DMA_IT_DMEIF7 ((uint32_t)0x21001000)
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478 #define DMA_IT_TEIF7 ((uint32_t)0x22002000)
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479 #define DMA_IT_HTIF7 ((uint32_t)0x24004000)
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480 #define DMA_IT_TCIF7 ((uint32_t)0x28008000)
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482 #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
\r
483 (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
\r
484 (((IT) & 0x40820082) == 0x00))
\r
486 #define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
\r
487 ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
\r
488 ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \
\r
489 ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \
\r
490 ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \
\r
491 ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \
\r
492 ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
\r
493 ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \
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494 ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \
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495 ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \
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496 ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \
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497 ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
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498 ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \
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499 ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \
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500 ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \
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501 ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \
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502 ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
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503 ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \
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504 ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \
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505 ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
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511 /** @defgroup DMA_peripheral_increment_offset
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514 #define DMA_PINCOS_Psize ((uint32_t)0x00000000)
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515 #define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)
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517 #define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
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518 ((SIZE) == DMA_PINCOS_WordAligned))
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524 /** @defgroup DMA_flow_controller_definitions
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527 #define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)
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528 #define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)
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530 #define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
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531 ((CTRL) == DMA_FlowCtrl_Peripheral))
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537 /** @defgroup DMA_memory_targets_definitions
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540 #define DMA_Memory_0 ((uint32_t)0x00000000)
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541 #define DMA_Memory_1 ((uint32_t)0x00080000)
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543 #define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
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552 /* Exported macro ------------------------------------------------------------*/
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553 /* Exported functions --------------------------------------------------------*/
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555 /* Function used to set the DMA configuration to the default reset state *****/
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556 void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
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558 /* Initialization and Configuration functions *********************************/
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559 void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
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560 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
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561 void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
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563 /* Optional Configuration functions *******************************************/
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564 void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
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565 void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
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567 /* Data Counter functions *****************************************************/
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568 void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
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569 uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
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571 /* Double Buffer mode functions ***********************************************/
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572 void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
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573 uint32_t DMA_CurrentMemory);
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574 void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
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575 void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
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576 uint32_t DMA_MemoryTarget);
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577 uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
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579 /* Interrupts and flags management functions **********************************/
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580 FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
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581 uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
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582 FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
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583 void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
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584 void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
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585 ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
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586 void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
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592 #endif /*__STM32F4xx_DMA_H */
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603 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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