4 * Copyright (c) 2013 Atmel Corporation. All rights reserved.
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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20 * 3. The name of Atmel may not be used to endorse or promote products derived
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21 * from this software without specific prior written permission.
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23 * 4. This software may only be redistributed and used in connection with an
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24 * Atmel microcontroller product.
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26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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36 * POSSIBILITY OF SUCH DAMAGE.
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45 /** \addtogroup SAM4E16E_definitions SAM4E16E definitions
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46 This file defines all structures and symbols for SAM4E16E:
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47 - registers and bitfields
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48 - peripheral base address
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58 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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61 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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63 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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65 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
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66 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
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69 /* ************************************************************************** */
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70 /* CMSIS DEFINITIONS FOR SAM4E16E */
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71 /* ************************************************************************** */
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72 /** \addtogroup SAM4E16E_cmsis CMSIS Definitions */
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75 /**< Interrupt Number Definition */
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78 /****** Cortex-M4 Processor Exceptions Numbers ******************************/
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79 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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80 MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
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81 BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
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82 UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
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83 SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
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84 DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
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85 PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
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86 SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
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87 /****** SAM4E16E specific Interrupt Numbers *********************************/
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89 SUPC_IRQn = 0, /**< 0 SAM4E16E Supply Controller (SUPC) */
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90 RSTC_IRQn = 1, /**< 1 SAM4E16E Reset Controller (RSTC) */
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91 RTC_IRQn = 2, /**< 2 SAM4E16E Real Time Clock (RTC) */
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92 RTT_IRQn = 3, /**< 3 SAM4E16E Real Time Timer (RTT) */
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93 WDT_IRQn = 4, /**< 4 SAM4E16E Watchdog/Dual Watchdog Timer (WDT) */
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94 PMC_IRQn = 5, /**< 5 SAM4E16E Power Management Controller (PMC) */
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95 EFC_IRQn = 6, /**< 6 SAM4E16E Enhanced Embedded Flash Controller (EFC) */
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96 UART0_IRQn = 7, /**< 7 SAM4E16E UART 0 (UART0) */
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97 PIOA_IRQn = 9, /**< 9 SAM4E16E Parallel I/O Controller A (PIOA) */
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98 PIOB_IRQn = 10, /**< 10 SAM4E16E Parallel I/O Controller B (PIOB) */
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99 PIOC_IRQn = 11, /**< 11 SAM4E16E Parallel I/O Controller C (PIOC) */
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100 PIOD_IRQn = 12, /**< 12 SAM4E16E Parallel I/O Controller D (PIOD) */
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101 PIOE_IRQn = 13, /**< 13 SAM4E16E Parallel I/O Controller E (PIOE) */
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102 USART0_IRQn = 14, /**< 14 SAM4E16E USART 0 (USART0) */
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103 USART1_IRQn = 15, /**< 15 SAM4E16E USART 1 (USART1) */
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104 HSMCI_IRQn = 16, /**< 16 SAM4E16E Multimedia Card Interface (HSMCI) */
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105 TWI0_IRQn = 17, /**< 17 SAM4E16E Two Wire Interface 0 (TWI0) */
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106 TWI1_IRQn = 18, /**< 18 SAM4E16E Two Wire Interface 1 (TWI1) */
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107 SPI_IRQn = 19, /**< 19 SAM4E16E Serial Peripheral Interface (SPI) */
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108 DMAC_IRQn = 20, /**< 20 SAM4E16E DMAC (DMAC) */
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109 TC0_IRQn = 21, /**< 21 SAM4E16E Timer/Counter 0 (TC0) */
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110 TC1_IRQn = 22, /**< 22 SAM4E16E Timer/Counter 1 (TC1) */
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111 TC2_IRQn = 23, /**< 23 SAM4E16E Timer/Counter 2 (TC2) */
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112 TC3_IRQn = 24, /**< 24 SAM4E16E Timer/Counter 3 (TC3) */
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113 TC4_IRQn = 25, /**< 25 SAM4E16E Timer/Counter 4 (TC4) */
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114 TC5_IRQn = 26, /**< 26 SAM4E16E Timer/Counter 5 (TC5) */
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115 TC6_IRQn = 27, /**< 27 SAM4E16E Timer/Counter 6 (TC6) */
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116 TC7_IRQn = 28, /**< 28 SAM4E16E Timer/Counter 7 (TC7) */
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117 TC8_IRQn = 29, /**< 29 SAM4E16E Timer/Counter 8 (TC8) */
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118 AFEC0_IRQn = 30, /**< 30 SAM4E16E Analog Front End 0 (AFEC0) */
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119 AFEC1_IRQn = 31, /**< 31 SAM4E16E Analog Front End 1 (AFEC1) */
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120 DACC_IRQn = 32, /**< 32 SAM4E16E Digital To Analog Converter (DACC) */
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121 ACC_IRQn = 33, /**< 33 SAM4E16E Analog Comparator (ACC) */
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122 ARM_IRQn = 34, /**< 34 SAM4E16E FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */
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123 UDP_IRQn = 35, /**< 35 SAM4E16E USB DEVICE (UDP) */
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124 PWM_IRQn = 36, /**< 36 SAM4E16E PWM (PWM) */
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125 CAN0_IRQn = 37, /**< 37 SAM4E16E CAN0 (CAN0) */
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126 CAN1_IRQn = 38, /**< 38 SAM4E16E CAN1 (CAN1) */
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127 AES_IRQn = 39, /**< 39 SAM4E16E AES (AES) */
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128 GMAC_IRQn = 44, /**< 44 SAM4E16E EMAC (GMAC) */
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129 UART1_IRQn = 45, /**< 45 SAM4E16E UART (UART1) */
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131 PERIPH_COUNT_IRQn = 46 /**< Number of peripheral IDs */
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134 typedef struct _DeviceVectors
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136 /* Stack pointer */
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139 /* Cortex-M handlers */
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140 void* pfnReset_Handler;
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141 void* pfnNMI_Handler;
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142 void* pfnHardFault_Handler;
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143 void* pfnMemManage_Handler;
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144 void* pfnBusFault_Handler;
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145 void* pfnUsageFault_Handler;
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146 void* pfnReserved1_Handler;
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147 void* pfnReserved2_Handler;
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148 void* pfnReserved3_Handler;
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149 void* pfnReserved4_Handler;
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150 void* pfnSVC_Handler;
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151 void* pfnDebugMon_Handler;
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152 void* pfnReserved5_Handler;
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153 void* pfnPendSV_Handler;
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154 void* pfnSysTick_Handler;
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156 /* Peripheral handlers */
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157 void* pfnSUPC_Handler; /* 0 Supply Controller */
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158 void* pfnRSTC_Handler; /* 1 Reset Controller */
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159 void* pfnRTC_Handler; /* 2 Real Time Clock */
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160 void* pfnRTT_Handler; /* 3 Real Time Timer */
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161 void* pfnWDT_Handler; /* 4 Watchdog/Dual Watchdog Timer */
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162 void* pfnPMC_Handler; /* 5 Power Management Controller */
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163 void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
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164 void* pfnUART0_Handler; /* 7 UART 0 */
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166 void* pfnPIOA_Handler; /* 9 Parallel I/O Controller A */
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167 void* pfnPIOB_Handler; /* 10 Parallel I/O Controller B */
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168 void* pfnPIOC_Handler; /* 11 Parallel I/O Controller C */
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169 void* pfnPIOD_Handler; /* 12 Parallel I/O Controller D */
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170 void* pfnPIOE_Handler; /* 13 Parallel I/O Controller E */
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171 void* pfnUSART0_Handler; /* 14 USART 0 */
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172 void* pfnUSART1_Handler; /* 15 USART 1 */
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173 void* pfnHSMCI_Handler; /* 16 Multimedia Card Interface */
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174 void* pfnTWI0_Handler; /* 17 Two Wire Interface 0 */
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175 void* pfnTWI1_Handler; /* 18 Two Wire Interface 1 */
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176 void* pfnSPI_Handler; /* 19 Serial Peripheral Interface */
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177 void* pfnDMAC_Handler; /* 20 DMAC */
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178 void* pfnTC0_Handler; /* 21 Timer/Counter 0 */
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179 void* pfnTC1_Handler; /* 22 Timer/Counter 1 */
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180 void* pfnTC2_Handler; /* 23 Timer/Counter 2 */
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181 void* pfnTC3_Handler; /* 24 Timer/Counter 3 */
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182 void* pfnTC4_Handler; /* 25 Timer/Counter 4 */
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183 void* pfnTC5_Handler; /* 26 Timer/Counter 5 */
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184 void* pfnTC6_Handler; /* 27 Timer/Counter 6 */
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185 void* pfnTC7_Handler; /* 28 Timer/Counter 7 */
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186 void* pfnTC8_Handler; /* 29 Timer/Counter 8 */
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187 void* pfnAFEC0_Handler; /* 30 Analog Front End 0 */
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188 void* pfnAFEC1_Handler; /* 31 Analog Front End 1 */
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189 void* pfnDACC_Handler; /* 32 Digital To Analog Converter */
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190 void* pfnACC_Handler; /* 33 Analog Comparator */
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191 void* pfnARM_Handler; /* 34 FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */
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192 void* pfnUDP_Handler; /* 35 USB DEVICE */
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193 void* pfnPWM_Handler; /* 36 PWM */
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194 void* pfnCAN0_Handler; /* 37 CAN0 */
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195 void* pfnCAN1_Handler; /* 38 CAN1 */
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196 void* pfnAES_Handler; /* 39 AES */
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197 void* pvReserved40;
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198 void* pvReserved41;
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199 void* pvReserved42;
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200 void* pvReserved43;
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201 void* pfnGMAC_Handler; /* 44 EMAC */
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202 void* pfnUART1_Handler; /* 45 UART */
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205 /* Cortex-M4 core handlers */
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206 void Reset_Handler ( void );
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207 void NMI_Handler ( void );
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208 void HardFault_Handler ( void );
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209 void MemManage_Handler ( void );
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210 void BusFault_Handler ( void );
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211 void UsageFault_Handler ( void );
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212 void SVC_Handler ( void );
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213 void DebugMon_Handler ( void );
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214 void PendSV_Handler ( void );
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215 void SysTick_Handler ( void );
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217 /* Peripherals handlers */
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218 void ACC_Handler ( void );
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219 void AES_Handler ( void );
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220 void AFEC0_Handler ( void );
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221 void AFEC1_Handler ( void );
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222 void ARM_Handler ( void );
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223 void CAN0_Handler ( void );
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224 void CAN1_Handler ( void );
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225 void DACC_Handler ( void );
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226 void DMAC_Handler ( void );
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227 void EFC_Handler ( void );
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228 void GMAC_Handler ( void );
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229 void HSMCI_Handler ( void );
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230 void PIOA_Handler ( void );
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231 void PIOB_Handler ( void );
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232 void PIOC_Handler ( void );
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233 void PIOD_Handler ( void );
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234 void PIOE_Handler ( void );
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235 void PMC_Handler ( void );
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236 void PWM_Handler ( void );
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237 void RSTC_Handler ( void );
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238 void RTC_Handler ( void );
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239 void RTT_Handler ( void );
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240 void SPI_Handler ( void );
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241 void SUPC_Handler ( void );
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242 void TC0_Handler ( void );
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243 void TC1_Handler ( void );
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244 void TC2_Handler ( void );
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245 void TC3_Handler ( void );
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246 void TC4_Handler ( void );
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247 void TC5_Handler ( void );
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248 void TC6_Handler ( void );
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249 void TC7_Handler ( void );
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250 void TC8_Handler ( void );
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251 void TWI0_Handler ( void );
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252 void TWI1_Handler ( void );
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253 void UART0_Handler ( void );
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254 void UART1_Handler ( void );
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255 void UDP_Handler ( void );
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256 void USART0_Handler ( void );
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257 void USART1_Handler ( void );
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258 void WDT_Handler ( void );
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261 * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
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264 #define __CM4_REV 0x0000 /**< SAM4E16E core revision number ([15:8] revision number, [7:0] patch number) */
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265 #define __MPU_PRESENT 0 /**< SAM4E16E does not provide a MPU */
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266 #define __FPU_PRESENT 1 /**< SAM4E16E does provide a FPU */
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267 #define __NVIC_PRIO_BITS 4 /**< SAM4E16E uses 4 Bits for the Priority Levels */
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268 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
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271 * \brief CMSIS includes
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274 #include <core_cm4.h>
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275 #if !defined DONT_USE_CMSIS_INIT
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276 #include "system_sam4e.h"
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277 #endif /* DONT_USE_CMSIS_INIT */
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281 /* ************************************************************************** */
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282 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4E16E */
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283 /* ************************************************************************** */
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284 /** \addtogroup SAM4E16E_api Peripheral Software API */
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287 #include "component/acc.h"
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288 #include "component/aes.h"
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289 #include "component/afec.h"
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290 #include "component/can.h"
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291 #include "component/chipid.h"
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292 #include "component/cmcc.h"
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293 #include "component/crccu.h"
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294 #include "component/dacc.h"
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295 #include "component/dmac.h"
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296 #include "component/efc.h"
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297 #include "component/gmac.h"
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298 #include "component/gpbr.h"
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299 #include "component/hsmci.h"
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300 #include "component/matrix.h"
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301 #include "component/pdc.h"
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302 #include "component/pio.h"
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303 #include "component/pmc.h"
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304 #include "component/pwm.h"
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305 #include "component/rstc.h"
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306 #include "component/rswdt.h"
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307 #include "component/rtc.h"
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308 #include "component/rtt.h"
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309 #include "component/smc.h"
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310 #include "component/spi.h"
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311 #include "component/supc.h"
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312 #include "component/tc.h"
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313 #include "component/twi.h"
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314 #include "component/uart.h"
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315 #include "component/udp.h"
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316 #include "component/usart.h"
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317 #include "component/wdt.h"
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320 /* ************************************************************************** */
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321 /* REGISTER ACCESS DEFINITIONS FOR SAM4E16E */
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322 /* ************************************************************************** */
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323 /** \addtogroup SAM4E16E_reg Registers Access Definitions */
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326 #include "instance/pwm.h"
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327 #include "instance/aes.h"
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328 #include "instance/can0.h"
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329 #include "instance/can1.h"
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330 #include "instance/gmac.h"
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331 #include "instance/crccu.h"
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332 #include "instance/smc.h"
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333 #include "instance/uart1.h"
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334 #include "instance/hsmci.h"
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335 #include "instance/udp.h"
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336 #include "instance/spi.h"
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337 #include "instance/tc0.h"
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338 #include "instance/tc1.h"
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339 #include "instance/tc2.h"
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340 #include "instance/usart0.h"
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341 #include "instance/usart1.h"
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342 #include "instance/twi0.h"
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343 #include "instance/twi1.h"
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344 #include "instance/afec0.h"
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345 #include "instance/afec1.h"
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346 #include "instance/dacc.h"
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347 #include "instance/acc.h"
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348 #include "instance/dmac.h"
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349 #include "instance/cmcc.h"
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350 #include "instance/matrix.h"
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351 #include "instance/pmc.h"
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352 #include "instance/uart0.h"
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353 #include "instance/chipid.h"
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354 #include "instance/efc.h"
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355 #include "instance/pioa.h"
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356 #include "instance/piob.h"
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357 #include "instance/pioc.h"
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358 #include "instance/piod.h"
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359 #include "instance/pioe.h"
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360 #include "instance/rstc.h"
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361 #include "instance/supc.h"
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362 #include "instance/rtt.h"
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363 #include "instance/wdt.h"
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364 #include "instance/rtc.h"
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365 #include "instance/gpbr.h"
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366 #include "instance/rswdt.h"
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369 /* ************************************************************************** */
\r
370 /* PERIPHERAL ID DEFINITIONS FOR SAM4E16E */
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371 /* ************************************************************************** */
\r
372 /** \addtogroup SAM4E16E_id Peripheral Ids Definitions */
\r
375 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
\r
376 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
\r
377 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
\r
378 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
\r
379 #define ID_WDT ( 4) /**< \brief Watchdog/Dual Watchdog Timer (WDT) */
\r
380 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
\r
381 #define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
\r
382 #define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
\r
383 #define ID_SMC ( 8) /**< \brief Static Memory Controller (SMC) */
\r
384 #define ID_PIOA ( 9) /**< \brief Parallel I/O Controller A (PIOA) */
\r
385 #define ID_PIOB (10) /**< \brief Parallel I/O Controller B (PIOB) */
\r
386 #define ID_PIOC (11) /**< \brief Parallel I/O Controller C (PIOC) */
\r
387 #define ID_PIOD (12) /**< \brief Parallel I/O Controller D (PIOD) */
\r
388 #define ID_PIOE (13) /**< \brief Parallel I/O Controller E (PIOE) */
\r
389 #define ID_USART0 (14) /**< \brief USART 0 (USART0) */
\r
390 #define ID_USART1 (15) /**< \brief USART 1 (USART1) */
\r
391 #define ID_HSMCI (16) /**< \brief Multimedia Card Interface (HSMCI) */
\r
392 #define ID_TWI0 (17) /**< \brief Two Wire Interface 0 (TWI0) */
\r
393 #define ID_TWI1 (18) /**< \brief Two Wire Interface 1 (TWI1) */
\r
394 #define ID_SPI (19) /**< \brief Serial Peripheral Interface (SPI) */
\r
395 #define ID_DMAC (20) /**< \brief DMAC (DMAC) */
\r
396 #define ID_TC0 (21) /**< \brief Timer/Counter 0 (TC0) */
\r
397 #define ID_TC1 (22) /**< \brief Timer/Counter 1 (TC1) */
\r
398 #define ID_TC2 (23) /**< \brief Timer/Counter 2 (TC2) */
\r
399 #define ID_TC3 (24) /**< \brief Timer/Counter 3 (TC3) */
\r
400 #define ID_TC4 (25) /**< \brief Timer/Counter 4 (TC4) */
\r
401 #define ID_TC5 (26) /**< \brief Timer/Counter 5 (TC5) */
\r
402 #define ID_TC6 (27) /**< \brief Timer/Counter 6 (TC6) */
\r
403 #define ID_TC7 (28) /**< \brief Timer/Counter 7 (TC7) */
\r
404 #define ID_TC8 (29) /**< \brief Timer/Counter 8 (TC8) */
\r
405 #define ID_AFEC0 (30) /**< \brief Analog Front End 0 (AFEC0) */
\r
406 #define ID_AFEC1 (31) /**< \brief Analog Front End 1 (AFEC1) */
\r
407 #define ID_DACC (32) /**< \brief Digital To Analog Converter (DACC) */
\r
408 #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
\r
409 #define ID_ARM (34) /**< \brief FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */
\r
410 #define ID_UDP (35) /**< \brief USB DEVICE (UDP) */
\r
411 #define ID_PWM (36) /**< \brief PWM (PWM) */
\r
412 #define ID_CAN0 (37) /**< \brief CAN0 (CAN0) */
\r
413 #define ID_CAN1 (38) /**< \brief CAN1 (CAN1) */
\r
414 #define ID_AES (39) /**< \brief AES (AES) */
\r
415 #define ID_GMAC (44) /**< \brief EMAC (GMAC) */
\r
416 #define ID_UART1 (45) /**< \brief UART (UART1) */
\r
418 #define ID_PERIPH_COUNT (46) /**< \brief Number of peripheral IDs */
\r
421 /* ************************************************************************** */
\r
422 /* BASE ADDRESS DEFINITIONS FOR SAM4E16E */
\r
423 /* ************************************************************************** */
\r
424 /** \addtogroup SAM4E16E_base Peripheral Base Address Definitions */
\r
427 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
428 #define PWM (0x40000000U) /**< \brief (PWM ) Base Address */
\r
429 #define PDC_PWM (0x40000100U) /**< \brief (PDC_PWM ) Base Address */
\r
430 #define AES (0x40004000U) /**< \brief (AES ) Base Address */
\r
431 #define CAN0 (0x40010000U) /**< \brief (CAN0 ) Base Address */
\r
432 #define CAN1 (0x40014000U) /**< \brief (CAN1 ) Base Address */
\r
433 #define GMAC (0x40034000U) /**< \brief (GMAC ) Base Address */
\r
434 #define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */
\r
435 #define SMC (0x40060000U) /**< \brief (SMC ) Base Address */
\r
436 #define UART1 (0x40060600U) /**< \brief (UART1 ) Base Address */
\r
437 #define PDC_UART1 (0x40060700U) /**< \brief (PDC_UART1 ) Base Address */
\r
438 #define HSMCI (0x40080000U) /**< \brief (HSMCI ) Base Address */
\r
439 #define PDC_HSMCI (0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */
\r
440 #define UDP (0x40084000U) /**< \brief (UDP ) Base Address */
\r
441 #define SPI (0x40088000U) /**< \brief (SPI ) Base Address */
\r
442 #define PDC_SPI (0x40088100U) /**< \brief (PDC_SPI ) Base Address */
\r
443 #define TC0 (0x40090000U) /**< \brief (TC0 ) Base Address */
\r
444 #define PDC_TC0 (0x40090100U) /**< \brief (PDC_TC0 ) Base Address */
\r
445 #define TC1 (0x40094000U) /**< \brief (TC1 ) Base Address */
\r
446 #define PDC_TC1 (0x40094100U) /**< \brief (PDC_TC1 ) Base Address */
\r
447 #define TC2 (0x40098000U) /**< \brief (TC2 ) Base Address */
\r
448 #define USART0 (0x400A0000U) /**< \brief (USART0 ) Base Address */
\r
449 #define PDC_USART0 (0x400A0100U) /**< \brief (PDC_USART0) Base Address */
\r
450 #define USART1 (0x400A4000U) /**< \brief (USART1 ) Base Address */
\r
451 #define PDC_USART1 (0x400A4100U) /**< \brief (PDC_USART1) Base Address */
\r
452 #define TWI0 (0x400A8000U) /**< \brief (TWI0 ) Base Address */
\r
453 #define PDC_TWI0 (0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */
\r
454 #define TWI1 (0x400AC000U) /**< \brief (TWI1 ) Base Address */
\r
455 #define PDC_TWI1 (0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */
\r
456 #define AFEC0 (0x400B0000U) /**< \brief (AFEC0 ) Base Address */
\r
457 #define PDC_AFEC0 (0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */
\r
458 #define AFEC1 (0x400B4000U) /**< \brief (AFEC1 ) Base Address */
\r
459 #define PDC_AFEC1 (0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */
\r
460 #define DACC (0x400B8000U) /**< \brief (DACC ) Base Address */
\r
461 #define PDC_DACC (0x400B8100U) /**< \brief (PDC_DACC ) Base Address */
\r
462 #define ACC (0x400BC000U) /**< \brief (ACC ) Base Address */
\r
463 #define DMAC (0x400C0000U) /**< \brief (DMAC ) Base Address */
\r
464 #define CMCC (0x400C4000U) /**< \brief (CMCC ) Base Address */
\r
465 #define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */
\r
466 #define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */
\r
467 #define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */
\r
468 #define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
\r
469 #define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */
\r
470 #define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */
\r
471 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
\r
472 #define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */
\r
473 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
\r
474 #define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */
\r
475 #define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
\r
476 #define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */
\r
477 #define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
\r
478 #define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
\r
479 #define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
\r
480 #define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
\r
481 #define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
\r
482 #define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
\r
483 #define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
\r
485 #define PWM ((Pwm *)0x40000000U) /**< \brief (PWM ) Base Address */
\r
486 #define PDC_PWM ((Pdc *)0x40000100U) /**< \brief (PDC_PWM ) Base Address */
\r
487 #define AES ((Aes *)0x40004000U) /**< \brief (AES ) Base Address */
\r
488 #define CAN0 ((Can *)0x40010000U) /**< \brief (CAN0 ) Base Address */
\r
489 #define CAN1 ((Can *)0x40014000U) /**< \brief (CAN1 ) Base Address */
\r
490 #define GMAC ((Gmac *)0x40034000U) /**< \brief (GMAC ) Base Address */
\r
491 #define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */
\r
492 #define SMC ((Smc *)0x40060000U) /**< \brief (SMC ) Base Address */
\r
493 #define UART1 ((Uart *)0x40060600U) /**< \brief (UART1 ) Base Address */
\r
494 #define PDC_UART1 ((Pdc *)0x40060700U) /**< \brief (PDC_UART1 ) Base Address */
\r
495 #define HSMCI ((Hsmci *)0x40080000U) /**< \brief (HSMCI ) Base Address */
\r
496 #define PDC_HSMCI ((Pdc *)0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */
\r
497 #define UDP ((Udp *)0x40084000U) /**< \brief (UDP ) Base Address */
\r
498 #define SPI ((Spi *)0x40088000U) /**< \brief (SPI ) Base Address */
\r
499 #define PDC_SPI ((Pdc *)0x40088100U) /**< \brief (PDC_SPI ) Base Address */
\r
500 #define TC0 ((Tc *)0x40090000U) /**< \brief (TC0 ) Base Address */
\r
501 #define PDC_TC0 ((Pdc *)0x40090100U) /**< \brief (PDC_TC0 ) Base Address */
\r
502 #define TC1 ((Tc *)0x40094000U) /**< \brief (TC1 ) Base Address */
\r
503 #define PDC_TC1 ((Pdc *)0x40094100U) /**< \brief (PDC_TC1 ) Base Address */
\r
504 #define TC2 ((Tc *)0x40098000U) /**< \brief (TC2 ) Base Address */
\r
505 #define USART0 ((Usart *)0x400A0000U) /**< \brief (USART0 ) Base Address */
\r
506 #define PDC_USART0 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART0) Base Address */
\r
507 #define USART1 ((Usart *)0x400A4000U) /**< \brief (USART1 ) Base Address */
\r
508 #define PDC_USART1 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART1) Base Address */
\r
509 #define TWI0 ((Twi *)0x400A8000U) /**< \brief (TWI0 ) Base Address */
\r
510 #define PDC_TWI0 ((Pdc *)0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */
\r
511 #define TWI1 ((Twi *)0x400AC000U) /**< \brief (TWI1 ) Base Address */
\r
512 #define PDC_TWI1 ((Pdc *)0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */
\r
513 #define AFEC0 ((Afec *)0x400B0000U) /**< \brief (AFEC0 ) Base Address */
\r
514 #define PDC_AFEC0 ((Pdc *)0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */
\r
515 #define AFEC1 ((Afec *)0x400B4000U) /**< \brief (AFEC1 ) Base Address */
\r
516 #define PDC_AFEC1 ((Pdc *)0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */
\r
517 #define DACC ((Dacc *)0x400B8000U) /**< \brief (DACC ) Base Address */
\r
518 #define PDC_DACC ((Pdc *)0x400B8100U) /**< \brief (PDC_DACC ) Base Address */
\r
519 #define ACC ((Acc *)0x400BC000U) /**< \brief (ACC ) Base Address */
\r
520 #define DMAC ((Dmac *)0x400C0000U) /**< \brief (DMAC ) Base Address */
\r
521 #define CMCC ((Cmcc *)0x400C4000U) /**< \brief (CMCC ) Base Address */
\r
522 #define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */
\r
523 #define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */
\r
524 #define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */
\r
525 #define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
\r
526 #define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */
\r
527 #define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */
\r
528 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
\r
529 #define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */
\r
530 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
\r
531 #define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */
\r
532 #define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
\r
533 #define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */
\r
534 #define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
\r
535 #define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
\r
536 #define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
\r
537 #define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
\r
538 #define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
\r
539 #define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
\r
540 #define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
\r
541 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
544 /* ************************************************************************** */
\r
545 /* PIO DEFINITIONS FOR SAM4E16E */
\r
546 /* ************************************************************************** */
\r
547 /** \addtogroup SAM4E16E_pio Peripheral Pio Definitions */
\r
550 #include "pio/sam4e16e.h"
\r
553 /* ************************************************************************** */
\r
554 /* MEMORY MAPPING DEFINITIONS FOR SAM4E16E */
\r
555 /* ************************************************************************** */
\r
557 #define IFLASH_SIZE (0x100000u)
\r
558 #define IFLASH_PAGE_SIZE (512u)
\r
559 #define IFLASH_LOCK_REGION_SIZE (8192u)
\r
560 #define IFLASH_NB_OF_PAGES (2048u)
\r
561 #define IFLASH_NB_OF_LOCK_BITS (128u)
\r
562 #define IRAM_SIZE (0x20000u)
\r
564 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
\r
565 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
\r
566 #define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
\r
567 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
\r
568 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
\r
569 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
\r
570 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
\r
572 /* ************************************************************************** */
\r
573 /* MISCELLANEOUS DEFINITIONS FOR SAM4E16E */
\r
574 /* ************************************************************************** */
\r
576 #define CHIP_JTAGID (0x05B3703FUL)
\r
577 #define CHIP_CIDR (0xA3CC0CE0UL)
\r
578 #define CHIP_EXID (0x00120200UL)
\r
579 #define NB_CH_AFE0 (16UL)
\r
580 #define NB_CH_AFE1 (8UL)
\r
582 /* ************************************************************************** */
\r
583 /* ELECTRICAL DEFINITIONS FOR SAM4E16E */
\r
584 /* ************************************************************************** */
\r
586 /* Device characteristics */
\r
587 #define CHIP_FREQ_SLCK_RC_MIN (20000UL)
\r
588 #define CHIP_FREQ_SLCK_RC (32000UL)
\r
589 #define CHIP_FREQ_SLCK_RC_MAX (44000UL)
\r
590 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
\r
591 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
\r
592 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
\r
593 #define CHIP_FREQ_CPU_MAX (120000000UL)
\r
594 #define CHIP_FREQ_XTAL_32K (32768UL)
\r
595 #define CHIP_FREQ_XTAL_12M (12000000UL)
\r
597 /* Embedded Flash Write Wait State */
\r
598 #define CHIP_FLASH_WRITE_WAIT_STATE (6U)
\r
600 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
\r
601 #define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
\r
602 #define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
\r
603 #define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
\r
604 #define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
\r
605 #define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
\r
606 #define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
\r
614 #endif /* _SAM4E16E_ */
\r