2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /* Standard includes. */
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32 /* FreeRTOS includes. */
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33 #include "FreeRTOS.h"
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36 /* Library includes. */
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41 * When configCREATE_LOW_POWER_DEMO is set to 1 then the tick interrupt
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42 * is generated by the AST. The AST configuration and handling functions are
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43 * defined in this file.
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45 * When configCREATE_LOW_POWER_DEMO is set to 0 the tick interrupt is
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46 * generated by the standard FreeRTOS Cortex-M port layer, which uses the
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49 #if configCREATE_LOW_POWER_DEMO == 1
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51 /* Constants required to pend a PendSV interrupt from the tick ISR if the
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52 preemptive scheduler is being used. These are just standard bits and registers
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53 within the Cortex-M core itself. */
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54 #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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56 /* The alarm used to generate interrupts in the asynchronous timer. */
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57 #define portAST_ALARM_CHANNEL 0
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59 /*-----------------------------------------------------------*/
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62 * The tick interrupt is generated by the asynchronous timer. The default tick
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63 * interrupt handler cannot be used (even with the AST being handled from the
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64 * tick hook function) because the default tick interrupt accesses the SysTick
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65 * registers when configUSE_TICKLESS_IDLE set to 1. AST_ALARM_Handler() is the
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66 * default name for the AST alarm interrupt. This definition overrides the
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67 * default implementation that is weakly defined in the interrupt vector table
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70 void AST_ALARM_Handler(void);
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73 * Functions that disable and enable the AST respectively, not returning until
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74 * the operation is known to have taken effect.
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76 static void prvDisableAST( void );
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77 static void prvEnableAST( void );
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79 /*-----------------------------------------------------------*/
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81 /* Calculate how many clock increments make up a single tick period. */
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82 static const uint32_t ulAlarmValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
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84 /* Holds the maximum number of ticks that can be suppressed - which is
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85 basically how far into the future an interrupt can be generated. Set
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86 during initialisation. */
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87 static TickType_t xMaximumPossibleSuppressedTicks = 0;
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89 /* Flag set from the tick interrupt to allow the sleep processing to know if
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90 sleep mode was exited because of an AST interrupt or a different interrupt. */
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91 static volatile uint32_t ulTickFlag = pdFALSE;
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93 /* The AST counter is stopped temporarily each time it is re-programmed. The
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94 following variable offsets the AST counter alarm value by the number of AST
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95 counts that would typically be missed while the counter was stopped to compensate
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96 for the lost time. _RB_ Value needs calculating correctly. */
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97 static uint32_t ulStoppedTimerCompensation = 2 / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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99 /*-----------------------------------------------------------*/
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101 /* The tick interrupt handler. This is always the same other than the part that
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102 clears the interrupt, which is specific to the clock being used to generate the
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104 void AST_ALARM_Handler(void)
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106 /* Protect incrementing the tick with an interrupt safe critical section. */
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107 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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109 if( xTaskIncrementTick() != pdFALSE )
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111 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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114 /* Just completely clear the interrupt mask on exit by passing 0 because
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115 it is known that this interrupt will only ever execute with the lowest
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116 possible interrupt priority. */
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118 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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120 /* The CPU woke because of a tick. */
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121 ulTickFlag = pdTRUE;
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123 /* If this is the first tick since exiting tickless mode then the AST needs
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124 to be reconfigured to generate interrupts at the defined tick frequency. */
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125 ast_write_alarm0_value( AST, ulAlarmValueForOneTick );
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127 /* Ensure the interrupt is clear before exiting. */
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128 ast_clear_interrupt_flag( AST, AST_INTERRUPT_ALARM );
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130 /*-----------------------------------------------------------*/
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132 /* Override the default definition of vPortSetupTimerInterrupt() that is weakly
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133 defined in the FreeRTOS Cortex-M3 port layer with a version that configures the
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134 asynchronous timer (AST) to generate the tick interrupt. */
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135 void vPortSetupTimerInterrupt( void )
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137 struct ast_config ast_conf;
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139 /* Ensure the AST can bring the CPU out of sleep mode. */
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140 sleepmgr_lock_mode( SLEEPMGR_RET );
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142 /* Ensure the 32KHz oscillator is enabled. */
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143 if( osc_is_ready( OSC_ID_OSC32 ) == pdFALSE )
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145 osc_enable( OSC_ID_OSC32 );
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146 osc_wait_ready( OSC_ID_OSC32 );
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149 /* Enable the AST itself. */
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152 ast_conf.mode = AST_COUNTER_MODE; /* Simple up counter. */
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153 ast_conf.osc_type = AST_OSC_32KHZ;
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154 ast_conf.psel = 0; /* No prescale so the actual frequency is 32KHz/2. */
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155 ast_conf.counter = 0;
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156 ast_set_config( AST, &ast_conf );
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158 /* The AST alarm interrupt is used as the tick interrupt. Ensure the alarm
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159 status starts clear. */
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160 ast_clear_interrupt_flag( AST, AST_INTERRUPT_ALARM );
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162 /* Enable wakeup from alarm 0 in the AST and power manager. */
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163 ast_enable_wakeup( AST, AST_WAKEUP_ALARM );
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164 bpm_enable_wakeup_source( BPM, ( 1 << BPM_BKUPWEN_AST ) );
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166 /* Tick interrupt MUST execute at the lowest interrupt priority. */
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167 NVIC_SetPriority( AST_ALARM_IRQn, configLIBRARY_LOWEST_INTERRUPT_PRIORITY);
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168 ast_enable_interrupt( AST, AST_INTERRUPT_ALARM );
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169 NVIC_ClearPendingIRQ( AST_ALARM_IRQn );
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170 NVIC_EnableIRQ( AST_ALARM_IRQn );
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172 /* Automatically clear the counter on interrupt. */
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173 ast_enable_counter_clear_on_alarm( AST, portAST_ALARM_CHANNEL );
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175 /* Start with the tick active and generating a tick with regular period. */
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176 ast_write_alarm0_value( AST, ulAlarmValueForOneTick );
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177 ast_write_counter_value( AST, 0 );
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179 /* See the comments where xMaximumPossibleSuppressedTicks is declared. */
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180 xMaximumPossibleSuppressedTicks = ULONG_MAX / ulAlarmValueForOneTick;
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182 /*-----------------------------------------------------------*/
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184 static void prvDisableAST( void )
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186 while( ast_is_busy( AST ) )
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188 /* Nothing to do here, just waiting. */
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190 AST->AST_CR &= ~( AST_CR_EN );
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191 while( ast_is_busy( AST ) )
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193 /* Nothing to do here, just waiting. */
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196 /*-----------------------------------------------------------*/
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198 static void prvEnableAST( void )
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200 while( ast_is_busy( AST ) )
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202 /* Nothing to do here, just waiting. */
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204 AST->AST_CR |= AST_CR_EN;
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205 while( ast_is_busy( AST ) )
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207 /* Nothing to do here, just waiting. */
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210 /*-----------------------------------------------------------*/
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212 /* Override the default definition of vPortSuppressTicksAndSleep() that is weakly
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213 defined in the FreeRTOS Cortex-M3 port layer with a version that manages the
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214 asynchronous timer (AST), as the tick is generated from the low power AST and
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215 not the SysTick as would normally be the case on a Cortex-M. */
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216 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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218 uint32_t ulAlarmValue, ulCompleteTickPeriods, ulInterruptStatus;
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219 eSleepModeStatus eSleepAction;
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220 TickType_t xModifiableIdleTime;
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221 enum sleepmgr_mode xSleepMode;
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223 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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225 /* Make sure the AST reload value does not overflow the counter. */
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226 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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228 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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231 /* Calculate the reload value required to wait xExpectedIdleTime tick
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233 ulAlarmValue = ulAlarmValueForOneTick * xExpectedIdleTime;
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234 if( ulAlarmValue > ulStoppedTimerCompensation )
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236 /* Compensate for the fact that the AST is going to be stopped
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238 ulAlarmValue -= ulStoppedTimerCompensation;
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241 /* Stop the AST momentarily. The time the AST is stopped for is accounted
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242 for as best it can be, but using the tickless mode will inevitably result in
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243 some tiny drift of the time maintained by the kernel with respect to
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247 /* Enter a critical section but don't use the taskENTER_CRITICAL() method as
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248 that will mask interrupts that should exit sleep mode. */
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249 ulInterruptStatus = cpu_irq_save();
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251 /* The tick flag is set to false before sleeping. If it is true when sleep
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252 mode is exited then sleep mode was probably exited because the tick was
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253 suppressed for the entire xExpectedIdleTime period. */
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254 ulTickFlag = pdFALSE;
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256 /* If a context switch is pending then abandon the low power entry as
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257 the context switch might have been pended by an external interrupt that
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258 requires processing. */
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259 eSleepAction = eTaskConfirmSleepModeStatus();
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260 if( eSleepAction == eAbortSleep )
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262 /* Restart tick. */
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265 /* Re-enable interrupts - see comments above the cpsid instruction()
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267 cpu_irq_restore( ulInterruptStatus );
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271 /* Adjust the alarm value to take into account that the current time
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272 slice is already partially complete. */
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273 ulAlarmValue -= ast_read_counter_value( AST );
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274 ast_write_alarm0_value( AST, ulAlarmValue );
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276 /* Restart the AST. */
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279 /* Allow the application to define some pre-sleep processing. */
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280 xModifiableIdleTime = xExpectedIdleTime;
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281 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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283 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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284 means the application defined code has already executed the WAIT
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286 if( xModifiableIdleTime > 0 )
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288 /* Find the deepest allowable sleep mode. */
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289 xSleepMode = sleepmgr_get_sleep_mode();
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291 if( xSleepMode != SLEEPMGR_ACTIVE )
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293 /* Sleep until something happens. */
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294 bpm_sleep( BPM, xSleepMode );
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298 /* Allow the application to define some post sleep processing. */
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299 configPOST_SLEEP_PROCESSING( xModifiableIdleTime );
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301 /* Stop AST. Again, the time the SysTick is stopped for is accounted
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302 for as best it can be, but using the tickless mode will inevitably
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303 result in some tiny drift of the time maintained by the kernel with
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304 respect to calendar time. */
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307 /* Re-enable interrupts - see comments above the cpsid instruction()
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309 cpu_irq_restore( ulInterruptStatus );
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311 if( ulTickFlag != pdFALSE )
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313 /* The tick interrupt has already executed, although because this
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314 function is called with the scheduler suspended the actual tick
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315 processing will not occur until after this function has exited.
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316 Reset the alarm value with whatever remains of this tick period. */
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317 ulAlarmValue = ulAlarmValueForOneTick - ast_read_counter_value( AST );
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318 ast_write_alarm0_value( AST, ulAlarmValue );
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320 /* The tick interrupt handler will already have pended the tick
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321 processing in the kernel. As the pending tick will be processed as
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322 soon as this function exits, the tick value maintained by the tick
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323 is stepped forward by one less than the time spent sleeping. The
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324 actual stepping of the tick appears later in this function. */
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325 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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329 /* Something other than the tick interrupt ended the sleep. How
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330 many complete tick periods passed while the processor was
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332 ulCompleteTickPeriods = ast_read_counter_value( AST ) / ulAlarmValueForOneTick;
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334 /* The alarm value is set to whatever fraction of a single tick
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336 ulAlarmValue = ast_read_counter_value( AST ) - ( ulCompleteTickPeriods * ulAlarmValueForOneTick );
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337 if( ulAlarmValue == 0 )
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339 /* There is no fraction remaining. */
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340 ulAlarmValue = ulAlarmValueForOneTick;
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341 ulCompleteTickPeriods++;
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343 ast_write_counter_value( AST, 0 );
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344 ast_write_alarm0_value( AST, ulAlarmValue );
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347 /* Restart the AST so it runs up to the alarm value. The alarm value
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348 will get set to the value required to generate exactly one tick period
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349 the next time the AST interrupt executes. */
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352 /* Wind the tick forward by the number of tick periods that the CPU
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353 remained in a low power state. */
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354 vTaskStepTick( ulCompleteTickPeriods );
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359 #endif /* configCREATE_LOW_POWER_DEMO == 1 */
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