2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 * Provides the two timers sources for the standard demo IntQueue test. Also
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30 * includes a high frequency timer to maximise the interrupt nesting achieved.
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33 /* Standard includes. */
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36 /* Scheduler includes. */
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37 #include "FreeRTOS.h"
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40 /* Demo includes. */
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41 #include "IntQueueTimer.h"
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42 #include "IntQueue.h"
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44 /* System includes. */
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48 /* The frequencies at which the first two timers expire are slightly offset to
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49 ensure they don't remain synchronised. The frequency of the highest priority
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50 interrupt is 20 times faster so really hammers the interrupt entry and exit
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52 #define tmrTIMER_0_FREQUENCY ( 2000UL )
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53 #define tmrTIMER_1_FREQUENCY ( 1003UL )
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54 #define tmrTIMER_2_FREQUENCY ( 5000UL )
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56 /* Priorities used by the timer interrupts - these are set differently to make
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57 nesting likely/common. The high frequency timer operates above the max
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58 system call interrupt priority, but does not use the RTOS API. */
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59 #define tmrTIMER_0_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY )
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60 #define tmrTIMER_1_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1 )
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61 #define tmrTIMER_2_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 )
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63 /* The channels used within the TC0 timer. */
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64 #define tmrTIMER_0_CHANNEL ( 0 )
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65 #define tmrTIMER_1_CHANNEL ( 1 )
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66 #define tmrTIMER_2_CHANNEL ( 2 )
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68 /* TC register bit specifics. */
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69 #define tmrTRIGGER_ON_RC ( 1UL << 4UL )
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70 #define trmDIVIDER ( 128 )
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72 /*-----------------------------------------------------------*/
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74 /* Handers for the timer interrupts. */
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75 void TC0_Handler( void );
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76 void TC1_Handler( void );
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77 void TC2_Handler( void );
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79 /*-----------------------------------------------------------*/
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81 /* Incremented by the high frequency timer, which operates above the max
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82 syscall interrupt priority. This is just for inspection. */
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83 volatile uint32_t ulHighFrequencyTimerInterrupts = 0;
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85 /*-----------------------------------------------------------*/
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87 void vInitialiseTimerForIntQueueTest( void )
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89 uint32_t ulInputFrequency;
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91 /* Calculate the frequency of the clock that feeds the TC. */
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92 ulInputFrequency = configCPU_CLOCK_HZ;
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93 ulInputFrequency /= trmDIVIDER;
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95 /* Three channels are used - two that run at or under
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96 configMAX_SYSCALL_INTERRUPT_PRIORITY, and one that runs over
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97 configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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98 sysclk_enable_peripheral_clock( ID_TC0 );
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99 sysclk_enable_peripheral_clock( ID_TC1 );
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100 sysclk_enable_peripheral_clock( ID_TC2 );
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102 /* Init TC channels to waveform mode - up mode clean on RC match. */
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103 tc_init( TC0, tmrTIMER_0_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK4 | TC_CMR_WAVE | TC_CMR_ACPC_CLEAR | TC_CMR_CPCTRG );
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104 tc_init( TC0, tmrTIMER_1_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK4 | TC_CMR_WAVE | TC_CMR_ACPC_CLEAR | TC_CMR_CPCTRG );
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105 tc_init( TC0, tmrTIMER_2_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK4 | TC_CMR_WAVE | TC_CMR_ACPC_CLEAR | TC_CMR_CPCTRG );
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107 tc_enable_interrupt( TC0, tmrTIMER_0_CHANNEL, tmrTRIGGER_ON_RC );
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108 tc_enable_interrupt( TC0, tmrTIMER_1_CHANNEL, tmrTRIGGER_ON_RC );
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109 tc_enable_interrupt( TC0, tmrTIMER_2_CHANNEL, tmrTRIGGER_ON_RC );
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111 tc_write_rc( TC0, tmrTIMER_0_CHANNEL, ( ulInputFrequency / tmrTIMER_0_FREQUENCY ) );
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112 tc_write_rc( TC0, tmrTIMER_1_CHANNEL, ( ulInputFrequency / tmrTIMER_1_FREQUENCY ) );
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113 tc_write_rc( TC0, tmrTIMER_2_CHANNEL, ( ulInputFrequency / tmrTIMER_2_FREQUENCY ) );
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115 NVIC_SetPriority( TC0_IRQn, tmrTIMER_0_PRIORITY );
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116 NVIC_SetPriority( TC1_IRQn, tmrTIMER_1_PRIORITY );
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117 NVIC_SetPriority( TC2_IRQn, tmrTIMER_2_PRIORITY );
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119 NVIC_EnableIRQ( TC0_IRQn );
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120 NVIC_EnableIRQ( TC1_IRQn );
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121 NVIC_EnableIRQ( TC2_IRQn );
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123 tc_start( TC0, tmrTIMER_0_CHANNEL );
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124 tc_start( TC0, tmrTIMER_1_CHANNEL );
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125 tc_start( TC0, tmrTIMER_2_CHANNEL );
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127 /*-----------------------------------------------------------*/
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129 void TC0_Handler( void )
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131 /* Handler for the first timer in the IntQueue test. Was the interrupt
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132 caused by a compare on RC? */
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133 if( ( tc_get_status( TC0, tmrTIMER_0_CHANNEL ) & ~TC_SR_CPCS ) != 0 )
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135 portYIELD_FROM_ISR( xFirstTimerHandler() );
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138 /*-----------------------------------------------------------*/
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140 void TC1_Handler( void )
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142 /* Handler for the second timer in the IntQueue test. Was the interrupt
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143 caused by a compare on RC? */
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144 if( ( tc_get_status( TC0, tmrTIMER_1_CHANNEL ) & ~TC_SR_CPCS ) != 0 )
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146 portYIELD_FROM_ISR( xSecondTimerHandler() );
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149 /*-----------------------------------------------------------*/
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151 void TC2_Handler( void )
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153 /* Handler for the high frequency timer that does nothing but increment a
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154 variable to give an indication that it is running. Was the interrupt caused
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155 by a compare on RC? */
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156 if( ( tc_get_status( TC0, tmrTIMER_2_CHANNEL ) & ~TC_SR_CPCS ) != 0 )
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158 ulHighFrequencyTimerInterrupts++;
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