4 * \brief SAM4S clock configuration.
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6 * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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20 * 3. The name of Atmel may not be used to endorse or promote products derived
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21 * from this software without specific prior written permission.
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23 * 4. This software may only be redistributed and used in connection with an
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24 * Atmel microcontroller product.
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26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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36 * POSSIBILITY OF SUCH DAMAGE.
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42 #ifndef CONF_CLOCK_H_INCLUDED
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43 #define CONF_CLOCK_H_INCLUDED
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45 // ===== System Clock (MCK) Source Options
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46 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC
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47 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL
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48 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS
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49 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
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50 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC
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51 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC
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52 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL
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53 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS
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54 #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
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55 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLBCK
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57 // ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES))
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58 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
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59 #define CONFIG_SYSCLK_PRES SYSCLK_PRES_2
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60 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4
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61 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8
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62 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16
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63 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32
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64 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64
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65 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3
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67 // ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div)
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68 // Use mul and div effective values here.
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69 #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
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70 #define CONFIG_PLL0_MUL 20
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71 #define CONFIG_PLL0_DIV 1
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73 // ===== PLL1 (B) Options (Fpll = (Fclk * PLL_mul) / PLL_div)
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74 // Use mul and div effective values here.
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75 //#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL
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76 //#define CONFIG_PLL1_MUL 16
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77 //#define CONFIG_PLL1_DIV 2
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79 // ===== USB Clock Source Options (Fusb = FpllX / USB_div)
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80 // Use div effective value here.
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81 //#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
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82 //#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
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83 //#define CONFIG_USBCLK_DIV 2
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85 // ===== Target frequency (System clock)
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86 // - XTAL frequency: 12MHz
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87 // - System clock source: PLLA
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88 // - System clock prescaler: 2 (divided by 2)
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89 // - PLLA source: XTAL
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90 // - PLLA output: XTAL * 20 / 1
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91 // - System clock: 12 * 20 / 1 / 2 = 120MHz
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92 // ===== Target frequency (USB Clock)
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93 // - USB clock source: PLLB
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94 // - USB clock devider: 2 (devided by 2)
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95 // - PLLB output: XTAL * 16 / 2
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96 // - USB clock: 12 * 16 / 2 / 2 = 48MHz
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99 #endif /* CONF_CLOCK_H_INCLUDED */
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