2 * -------------------------------------------
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3 * CC3220 SDK - v0.10.00.00
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4 * -------------------------------------------
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6 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions
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12 * Redistributions of source code must retain the above copyright
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13 * notice, this list of conditions and the following disclaimer.
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15 * Redistributions in binary form must reproduce the above copyright
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16 * notice, this list of conditions and the following disclaimer in the
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17 * documentation and/or other materials provided with the
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20 * Neither the name of Texas Instruments Incorporated nor the names of
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21 * its contributors may be used to endorse or promote products derived
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22 * from this software without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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38 #ifndef __HW_CAMERA_H__
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39 #define __HW_CAMERA_H__
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41 //*****************************************************************************
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43 // The following are defines for the CAMERA register offsets.
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45 //*****************************************************************************
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46 #define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP
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47 // revision code ( Parallel Mode)
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48 #define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the
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49 // various parameters of the OCP
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50 // interface (CCP and Parallel Mode)
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51 #define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status
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52 // information about the module
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53 // excluding the interrupt status
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54 // information (CCP and Parallel
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56 #define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups
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57 // all the status of the module
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58 // internal events that can generate
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59 // an interrupt (CCP & Parallel
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61 #define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register
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62 // allows to enable/disable the
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63 // module internal sources of
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64 // interrupt on an event-by-event
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65 // basis (CCP & Parallel Mode)
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66 #define CAMERA_O_CC_CTRL 0x00000040 // This register controls the
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67 // various parameters of the Camera
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68 // Core block (CCP & Parallel Mode)
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69 #define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA
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70 // interface of the Camera Core
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71 // block (CCP & Parallel Mode)
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72 #define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value
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73 // of the clock divisor used to
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74 // generate the external clock
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76 #define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to
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77 // the FIFO and read from the FIFO
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78 // (CCP & Parallel Mode)
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79 #define CAMERA_O_CC_TEST 0x00000050 // This register shows the status
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80 // of some important variables of
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81 // the camera core module (CCP &
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83 #define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values
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84 // of the generic parameters of the
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89 //******************************************************************************
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91 // The following are defines for the bit fields in the
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92 // CAMERA_O_CC_REVISION register.
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94 //******************************************************************************
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95 #define CAMERA_CC_REVISION_REV_M \
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96 0x000000FF // IP revision [7:4] Major revision
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97 // [3:0] Minor revision Examples:
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98 // 0x10 for 1.0 0x21 for 2.1
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100 #define CAMERA_CC_REVISION_REV_S 0
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101 //******************************************************************************
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103 // The following are defines for the bit fields in the
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104 // CAMERA_O_CC_SYSCONFIG register.
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106 //******************************************************************************
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107 #define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \
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108 0x00000018 // Slave interface power management
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109 // req/ack control """00""
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110 // Force-idle. An idle request is
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111 // acknoledged unconditionally"
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112 // """01"" No-idle. An idle request
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113 // is never acknowledged" """10""
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114 // reserved (Smart-idle not
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117 #define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3
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118 #define CAMERA_CC_SYSCONFIG_SOFT_RESET \
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119 0x00000002 // Software reset. Set this bit to
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120 // 1 to trigger a module reset. The
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121 // bit is automatically reset by the
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122 // hardware. During reset it always
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123 // returns 0. 0 Normal mode 1 The
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126 #define CAMERA_CC_SYSCONFIG_AUTO_IDLE \
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127 0x00000001 // Internal OCP clock gating
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128 // strategy 0 OCP clock is
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129 // free-running 1 Automatic OCP
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130 // clock gating strategy is applied
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131 // based on the OCP interface
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134 //******************************************************************************
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136 // The following are defines for the bit fields in the
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137 // CAMERA_O_CC_SYSSTATUS register.
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139 //******************************************************************************
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140 #define CAMERA_CC_SYSSTATUS_RESET_DONE2 \
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141 0x00000001 // Internal Reset Monitoring 0
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142 // Internal module reset is on-going
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143 // 1 Reset completed
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145 //******************************************************************************
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147 // The following are defines for the bit fields in the
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148 // CAMERA_O_CC_IRQSTATUS register.
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150 //******************************************************************************
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151 #define CAMERA_CC_IRQSTATUS_FS_IRQ \
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152 0x00080000 // Frame Start has occurred 0 Event
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153 // false "1 Event is true
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154 // (""pending"")" 0 Event status bit
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155 // unchanged 1 Event status bit is
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158 #define CAMERA_CC_IRQSTATUS_LE_IRQ \
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159 0x00040000 // Line End has occurred 0 Event
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160 // false "1 Event is true
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161 // (""pending"")" 0 Event status bit
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162 // unchanged 1 Event status bit is
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165 #define CAMERA_CC_IRQSTATUS_LS_IRQ \
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166 0x00020000 // Line Start has occurred 0 Event
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167 // false "1 Event is true
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168 // (""pending"")" 0 Event status bit
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169 // unchanged 1 Event status bit is
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172 #define CAMERA_CC_IRQSTATUS_FE_IRQ \
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173 0x00010000 // Frame End has occurred 0 Event
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174 // false "1 Event is true
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175 // (""pending"")" 0 Event status bit
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176 // unchanged 1 Event status bit is
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179 #define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \
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180 0x00000800 // FSP code error 0 Event false "1
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181 // Event is true (""pending"")" 0
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182 // Event status bit unchanged 1
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183 // Event status bit is reset
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185 #define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \
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186 0x00000400 // Frame Height Error 0 Event false
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187 // "1 Event is true (""pending"")" 0
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188 // Event status bit unchanged 1
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189 // Event status bit is reset
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191 #define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \
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192 0x00000200 // False Synchronization Code 0
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193 // Event false "1 Event is true
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194 // (""pending"")" 0 Event status bit
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195 // unchanged 1 Event status bit is
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198 #define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \
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199 0x00000100 // Shifted Synchronization Code 0
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200 // Event false "1 Event is true
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201 // (""pending"")" 0 Event status bit
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202 // unchanged 1 Event status bit is
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205 #define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \
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206 0x00000010 // FIFO is not empty 0 Event false
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207 // "1 Event is true (""pending"")" 0
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208 // Event status bit unchanged 1
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209 // Event status bit is reset
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211 #define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \
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212 0x00000008 // FIFO is full 0 Event false "1
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213 // Event is true (""pending"")" 0
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214 // Event status bit unchanged 1
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215 // Event status bit is reset
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217 #define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \
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218 0x00000004 // FIFO threshold has been reached
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219 // 0 Event false "1 Event is true
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220 // (""pending"")" 0 Event status bit
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221 // unchanged 1 Event status bit is
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224 #define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \
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225 0x00000002 // FIFO overflow has occurred 0
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226 // Event false "1 Event is true
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227 // (""pending"")" 0 Event status bit
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228 // unchanged 1 Event status bit is
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231 #define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \
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232 0x00000001 // FIFO underflow has occurred 0
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233 // Event false "1 Event is true
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234 // (""pending"")" 0 Event status bit
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235 // unchanged 1 Event status bit is
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238 //******************************************************************************
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240 // The following are defines for the bit fields in the
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241 // CAMERA_O_CC_IRQENABLE register.
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243 //******************************************************************************
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244 #define CAMERA_CC_IRQENABLE_FS_IRQ_EN \
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245 0x00080000 // Frame Start Interrupt Enable 0
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246 // Event is masked 1 Event generates
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247 // an interrupt when it occurs
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249 #define CAMERA_CC_IRQENABLE_LE_IRQ_EN \
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250 0x00040000 // Line End Interrupt Enable 0
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251 // Event is masked 1 Event generates
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252 // an interrupt when it occurs
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254 #define CAMERA_CC_IRQENABLE_LS_IRQ_EN \
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255 0x00020000 // Line Start Interrupt Enable 0
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256 // Event is masked 1 Event generates
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257 // an interrupt when it occurs
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259 #define CAMERA_CC_IRQENABLE_FE_IRQ_EN \
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260 0x00010000 // Frame End Interrupt Enable 0
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261 // Event is masked 1 Event generates
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262 // an interrupt when it occurs
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264 #define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \
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265 0x00000800 // FSP code Interrupt Enable 0
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266 // Event is masked 1 Event generates
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267 // an interrupt when it occurs
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269 #define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \
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270 0x00000400 // Frame Height Error Interrupt
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271 // Enable 0 Event is masked 1 Event
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272 // generates an interrupt when it
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275 #define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \
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276 0x00000200 // False Synchronization Code
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277 // Interrupt Enable 0 Event is
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278 // masked 1 Event generates an
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279 // interrupt when it occurs
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281 #define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \
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282 0x00000100 // False Synchronization Code
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283 // Interrupt Enable 0 Event is
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284 // masked 1 Event generates an
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285 // interrupt when it occurs
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287 #define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \
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288 0x00000010 // FIFO Threshold Interrupt Enable
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289 // 0 Event is masked 1 Event
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290 // generates an interrupt when it
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293 #define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \
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294 0x00000008 // FIFO Threshold Interrupt Enable
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295 // 0 Event is masked 1 Event
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296 // generates an interrupt when it
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299 #define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \
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300 0x00000004 // FIFO Threshold Interrupt Enable
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301 // 0 Event is masked 1 Event
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302 // generates an interrupt when it
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305 #define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \
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306 0x00000002 // FIFO Overflow Interrupt Enable 0
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307 // Event is masked 1 Event generates
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308 // an interrupt when it occurs
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310 #define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \
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311 0x00000001 // FIFO Underflow Interrupt Enable
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312 // 0 Event is masked 1 Event
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313 // generates an interrupt when it
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316 //******************************************************************************
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318 // The following are defines for the bit fields in the CAMERA_O_CC_CTRL register.
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320 //******************************************************************************
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321 #define CAMERA_CC_CTRL_CC_IF_SYNCHRO \
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322 0x00080000 // Synchronize all camera sensor
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323 // inputs This must be set during
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324 // the configuration phase before
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325 // CC_EN set to '1'. This can be
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326 // used in very high frequency to
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327 // avoid dependancy to the IO
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328 // timings. 0 No synchro (most of
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329 // applications) 1 Synchro enabled
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330 // (should never be required)
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332 #define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite
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333 // states machines of the camera
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334 // core module - by writing a 1 to
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335 // this bit. must be applied when
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336 // CC_EN = 0 Reads returns 0
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337 #define CAMERA_CC_CTRL_CC_FRAME_TRIG \
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338 0x00020000 // Set the modality in which CC_EN
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339 // works when a disabling of the
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340 // sensor camera core is wanted "If
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341 // CC_FRAME_TRIG = 1 by writing
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342 // ""0"" to CC_EN" the module is
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343 // disabled at the end of the frame
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344 // "If CC_FRAME_TRIG = 0 by writing
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345 // ""0"" to CC_EN" the module is
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346 // disabled immediately
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348 #define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of
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349 // the camera core module "By
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350 // writing ""1"" to this field the
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351 // module is enabled." "By writing
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352 // ""0"" to this field the module is
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353 // disabled at" the end of the frame
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354 // if CC_FRAM_TRIG =1 and is
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355 // disabled immediately if
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356 // CC_FRAM_TRIG = 0
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357 #define CAMERA_CC_CTRL_NOBT_SYNCHRO \
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358 0x00002000 // Enables to start at the
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359 // beginning of the frame or not in
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360 // NoBT 0 Acquisition starts when
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361 // Vertical synchro is high 1
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362 // Acquisition starts when Vertical
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363 // synchro goes from low to high
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364 // (beginning of the frame) -
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367 #define CAMERA_CC_CTRL_BT_CORRECT \
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368 0x00001000 // Enables the correction within
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369 // the sync codes in BT mode 0
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370 // correction is not enabled 1
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371 // correction is enabled
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373 #define CAMERA_CC_CTRL_PAR_ORDERCAM \
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374 0x00000800 // Enables swap between image-data
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375 // in parallel mode 0 swap is not
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376 // enabled 1 swap is enabled
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378 #define CAMERA_CC_CTRL_PAR_CLK_POL \
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379 0x00000400 // Inverts the clock coming from
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380 // the sensor in parallel mode 0
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381 // clock not inverted - data sampled
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382 // on rising edge 1 clock inverted -
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383 // data sampled on falling edge
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385 #define CAMERA_CC_CTRL_NOBT_HS_POL \
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386 0x00000200 // Sets the polarity of the
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387 // synchronization signals in NOBT
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388 // parallel mode 0 CAM_P_HS is
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389 // active high 1 CAM_P_HS is active
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392 #define CAMERA_CC_CTRL_NOBT_VS_POL \
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393 0x00000100 // Sets the polarity of the
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394 // synchronization signals in NOBT
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395 // parallel mode 0 CAM_P_VS is
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396 // active high 1 CAM_P_VS is active
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399 #define CAMERA_CC_CTRL_PAR_MODE_M \
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400 0x0000000E // Sets the Protocol Mode of the
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401 // Camera Core module in parallel
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402 // mode (when CCP_MODE = 0) """000""
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403 // Parallel NOBT 8-bit" """001""
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404 // Parallel NOBT 10-bit" """010""
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405 // Parallel NOBT 12-bit" """011""
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406 // reserved" """100"" Parallet BT
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407 // 8-bit" """101"" Parallel BT
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408 // 10-bit" """110"" reserved"
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409 // """111"" FIFO test mode. Refer to
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410 // Table 12 - FIFO Write and Read
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413 #define CAMERA_CC_CTRL_PAR_MODE_S 1
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414 #define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode
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415 // 0 CCP mode disabled 1 CCP mode
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417 //******************************************************************************
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419 // The following are defines for the bit fields in the
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420 // CAMERA_O_CC_CTRL_DMA register.
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422 //******************************************************************************
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423 #define CAMERA_CC_CTRL_DMA_DMA_EN \
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424 0x00000100 // Sets the number of dma request
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425 // lines 0 DMA interface disabled
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426 // The DMA request line stays
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427 // inactive 1 DMA interface enabled
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428 // The DMA request line is
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431 #define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \
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432 0x0000007F // Sets the threshold of the FIFO
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433 // the assertion of the dmarequest
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434 // line takes place when the
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435 // threshold is reached.
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436 // """0000000"" threshold set to 1"
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437 // """0000001"" threshold set to 2"
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438 // … """1111111"" threshold set to
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441 #define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0
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442 //******************************************************************************
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444 // The following are defines for the bit fields in the
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445 // CAMERA_O_CC_CTRL_XCLK register.
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447 //******************************************************************************
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448 #define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \
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449 0x0000001F // Sets the clock divisor value for
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450 // CAM_XCLK generation. based on
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451 // CAM_MCK (value of CAM_MCLK is
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452 // 96MHz) """00000"" CAM_XCLK Stable
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453 // Low Level" Divider not enabled
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454 // """00001"" CAM_XCLK Stable High
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455 // Level" Divider not enabled from 2
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456 // to 30 CAM_XCLK = CAM_MCLK /
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457 // XCLK_DIV """11111"" Bypass -
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458 // CAM_XCLK = CAM_MCLK"
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460 #define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0
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461 //******************************************************************************
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463 // The following are defines for the bit fields in the
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464 // CAMERA_O_CC_FIFO_DATA register.
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466 //******************************************************************************
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467 #define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \
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468 0xFFFFFFFF // Writes the 32-bit word into the
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469 // FIFO Reads the 32-bit word from
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472 #define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0
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473 //******************************************************************************
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475 // The following are defines for the bit fields in the CAMERA_O_CC_TEST register.
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477 //******************************************************************************
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478 #define CAMERA_CC_TEST_FIFO_RD_POINTER_M \
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479 0xFF000000 // FIFO READ Pointer This field
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480 // shows the value of the FIFO read
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481 // pointer Expected value ranges
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484 #define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24
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485 #define CAMERA_CC_TEST_FIFO_WR_POINTER_M \
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486 0x00FF0000 // FIFO WRITE pointer This field
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487 // shows the value of the FIFO write
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488 // pointer Expected value ranges
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491 #define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16
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492 #define CAMERA_CC_TEST_FIFO_LEVEL_M \
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493 0x0000FF00 // FIFO level (how many 32-bit
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494 // words the FIFO contains) This
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495 // field shows the value of the FIFO
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496 // level and can assume values from
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499 #define CAMERA_CC_TEST_FIFO_LEVEL_S 8
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500 #define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \
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501 0x000000FF // FIFO level peak This field shows
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502 // the max value of the FIFO level
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503 // and can assume values from 0 to
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506 #define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0
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507 //******************************************************************************
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509 // The following are defines for the bit fields in the
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510 // CAMERA_O_CC_GEN_PAR register.
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512 //******************************************************************************
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513 #define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \
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514 0x00000007 // Camera Core FIFO DEPTH generic
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517 #define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0
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521 #endif // __HW_CAMERA_H__
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