4 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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20 * 3. The name of Atmel may not be used to endorse or promote products derived
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21 * from this software without specific prior written permission.
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23 * 4. This software may only be redistributed and used in connection with an
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24 * Atmel microcontroller product.
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26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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36 * POSSIBILITY OF SUCH DAMAGE.
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42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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45 #ifndef _SAME70_USBHS_COMPONENT_
\r
46 #define _SAME70_USBHS_COMPONENT_
\r
48 /* ============================================================================= */
\r
49 /** SOFTWARE API DEFINITION FOR USB High-Speed Interface */
\r
50 /* ============================================================================= */
\r
51 /** \addtogroup SAME70_USBHS USB High-Speed Interface */
\r
54 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
55 /** \brief UsbhsDevdma hardware registers */
\r
57 __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */
\r
58 __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */
\r
59 __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */
\r
60 __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */
\r
62 /** \brief UsbhsHstdma hardware registers */
\r
64 __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */
\r
65 __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */
\r
66 __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */
\r
67 __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */
\r
69 /** \brief Usbhs hardware registers */
\r
70 #define USBHSDEVDMA_NUMBER 7
\r
71 #define USBHSHSTDMA_NUMBER 7
\r
73 __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */
\r
74 __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */
\r
75 __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */
\r
76 __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */
\r
77 __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */
\r
78 __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */
\r
79 __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */
\r
80 __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */
\r
81 __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */
\r
82 __I uint32_t Reserved1[55];
\r
83 __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */
\r
84 __I uint32_t Reserved2[2];
\r
85 __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */
\r
86 __I uint32_t Reserved3[2];
\r
87 __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */
\r
88 __I uint32_t Reserved4[2];
\r
89 __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */
\r
90 __I uint32_t Reserved5[2];
\r
91 __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */
\r
92 __I uint32_t Reserved6[2];
\r
93 __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */
\r
94 __I uint32_t Reserved7[2];
\r
95 __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */
\r
96 __I uint32_t Reserved8[50];
\r
97 UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */
\r
98 __I uint32_t Reserved9[32];
\r
99 __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */
\r
100 __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */
\r
101 __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */
\r
102 __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */
\r
103 __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */
\r
104 __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */
\r
105 __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */
\r
106 __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */
\r
107 __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */
\r
108 __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */
\r
109 __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */
\r
110 __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */
\r
111 __I uint32_t Reserved10[52];
\r
112 __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */
\r
113 __I uint32_t Reserved11[2];
\r
114 __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */
\r
115 __I uint32_t Reserved12[2];
\r
116 __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */
\r
117 __I uint32_t Reserved13[2];
\r
118 __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */
\r
119 __I uint32_t Reserved14[2];
\r
120 __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */
\r
121 __I uint32_t Reserved15[2];
\r
122 __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */
\r
123 __I uint32_t Reserved16[2];
\r
124 __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */
\r
125 __I uint32_t Reserved17[2];
\r
126 __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */
\r
127 __I uint32_t Reserved18[2];
\r
128 __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */
\r
129 __I uint32_t Reserved19[26];
\r
130 UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */
\r
131 __I uint32_t Reserved20[32];
\r
132 __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */
\r
133 __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */
\r
134 __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */
\r
135 __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */
\r
136 __IO uint32_t USBHS_TSTA1; /**< \brief (Usbhs Offset: 0x0810) General Test A1 Register */
\r
137 __IO uint32_t USBHS_TSTA2; /**< \brief (Usbhs Offset: 0x0814) General Test A2 Register */
\r
138 __I uint32_t USBHS_VERSION; /**< \brief (Usbhs Offset: 0x0818) General Version Register */
\r
139 __I uint32_t Reserved21[4];
\r
140 __I uint32_t USBHS_FSM; /**< \brief (Usbhs Offset: 0x082C) General Finite State Machine Register */
\r
142 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
143 /* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */
\r
144 #define USBHS_DEVCTRL_UADD_Pos 0
\r
145 #define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */
\r
146 #define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)))
\r
147 #define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */
\r
148 #define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */
\r
149 #define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */
\r
150 #define USBHS_DEVCTRL_SPDCONF_Pos 10
\r
151 #define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */
\r
152 #define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)))
\r
153 #define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */
\r
154 #define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */
\r
155 #define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (USBHS_DEVCTRL) Forced high speed. */
\r
156 #define USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */
\r
157 #define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */
\r
158 #define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */
\r
159 #define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */
\r
160 #define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */
\r
161 #define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */
\r
162 /* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */
\r
163 #define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */
\r
164 #define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */
\r
165 #define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */
\r
166 #define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */
\r
167 #define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */
\r
168 #define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */
\r
169 #define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */
\r
170 #define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */
\r
171 #define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */
\r
172 #define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */
\r
173 #define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */
\r
174 #define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */
\r
175 #define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */
\r
176 #define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */
\r
177 #define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */
\r
178 #define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */
\r
179 #define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */
\r
180 #define USBHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVISR) Endpoint 10 Interrupt */
\r
181 #define USBHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVISR) Endpoint 11 Interrupt */
\r
182 #define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */
\r
183 #define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */
\r
184 #define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */
\r
185 #define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */
\r
186 #define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */
\r
187 #define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */
\r
188 #define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */
\r
189 /* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */
\r
190 #define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */
\r
191 #define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */
\r
192 #define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */
\r
193 #define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */
\r
194 #define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */
\r
195 #define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */
\r
196 #define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */
\r
197 /* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */
\r
198 #define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */
\r
199 #define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */
\r
200 #define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */
\r
201 #define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */
\r
202 #define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */
\r
203 #define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */
\r
204 #define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */
\r
205 #define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */
\r
206 #define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */
\r
207 #define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */
\r
208 #define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */
\r
209 #define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */
\r
210 #define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */
\r
211 #define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */
\r
212 /* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */
\r
213 #define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */
\r
214 #define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */
\r
215 #define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */
\r
216 #define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */
\r
217 #define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */
\r
218 #define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */
\r
219 #define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */
\r
220 #define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */
\r
221 #define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */
\r
222 #define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */
\r
223 #define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */
\r
224 #define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */
\r
225 #define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */
\r
226 #define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */
\r
227 #define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */
\r
228 #define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */
\r
229 #define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */
\r
230 #define USBHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIMR) Endpoint 10 Interrupt Mask */
\r
231 #define USBHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIMR) Endpoint 11 Interrupt Mask */
\r
232 #define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */
\r
233 #define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */
\r
234 #define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */
\r
235 #define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */
\r
236 #define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */
\r
237 #define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */
\r
238 #define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */
\r
239 /* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */
\r
240 #define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */
\r
241 #define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */
\r
242 #define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */
\r
243 #define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */
\r
244 #define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */
\r
245 #define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */
\r
246 #define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */
\r
247 #define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */
\r
248 #define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */
\r
249 #define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */
\r
250 #define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */
\r
251 #define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */
\r
252 #define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */
\r
253 #define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */
\r
254 #define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */
\r
255 #define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */
\r
256 #define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */
\r
257 #define USBHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIDR) Endpoint 10 Interrupt Disable */
\r
258 #define USBHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIDR) Endpoint 11 Interrupt Disable */
\r
259 #define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */
\r
260 #define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */
\r
261 #define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */
\r
262 #define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */
\r
263 #define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */
\r
264 #define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */
\r
265 #define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */
\r
266 /* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */
\r
267 #define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */
\r
268 #define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */
\r
269 #define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */
\r
270 #define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */
\r
271 #define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */
\r
272 #define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */
\r
273 #define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */
\r
274 #define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */
\r
275 #define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */
\r
276 #define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */
\r
277 #define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */
\r
278 #define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */
\r
279 #define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */
\r
280 #define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */
\r
281 #define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */
\r
282 #define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */
\r
283 #define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */
\r
284 #define USBHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIER) Endpoint 10 Interrupt Enable */
\r
285 #define USBHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIER) Endpoint 11 Interrupt Enable */
\r
286 #define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */
\r
287 #define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */
\r
288 #define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */
\r
289 #define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */
\r
290 #define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */
\r
291 #define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */
\r
292 #define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */
\r
293 /* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */
\r
294 #define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */
\r
295 #define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */
\r
296 #define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */
\r
297 #define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */
\r
298 #define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */
\r
299 #define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */
\r
300 #define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */
\r
301 #define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */
\r
302 #define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */
\r
303 #define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */
\r
304 #define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */
\r
305 #define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */
\r
306 #define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */
\r
307 #define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */
\r
308 #define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */
\r
309 #define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */
\r
310 #define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */
\r
311 #define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */
\r
312 /* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */
\r
313 #define USBHS_DEVFNUM_MFNUM_Pos 0
\r
314 #define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */
\r
315 #define USBHS_DEVFNUM_FNUM_Pos 3
\r
316 #define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */
\r
317 #define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */
\r
318 /* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */
\r
319 #define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */
\r
320 #define USBHS_DEVEPTCFG_EPBK_Pos 2
\r
321 #define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */
\r
322 #define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)))
\r
323 #define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */
\r
324 #define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */
\r
325 #define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */
\r
326 #define USBHS_DEVEPTCFG_EPSIZE_Pos 4
\r
327 #define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */
\r
328 #define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)))
\r
329 #define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */
\r
330 #define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */
\r
331 #define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */
\r
332 #define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */
\r
333 #define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */
\r
334 #define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */
\r
335 #define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */
\r
336 #define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */
\r
337 #define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */
\r
338 #define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */
\r
339 #define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */
\r
340 #define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */
\r
341 #define USBHS_DEVEPTCFG_EPTYPE_Pos 11
\r
342 #define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */
\r
343 #define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)))
\r
344 #define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */
\r
345 #define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */
\r
346 #define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */
\r
347 #define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */
\r
348 #define USBHS_DEVEPTCFG_NBTRANS_Pos 13
\r
349 #define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */
\r
350 #define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)))
\r
351 #define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */
\r
352 #define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */
\r
353 #define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */
\r
354 #define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */
\r
355 /* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */
\r
356 #define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */
\r
357 #define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */
\r
358 #define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */
\r
359 #define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */
\r
360 #define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */
\r
361 #define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */
\r
362 #define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */
\r
363 #define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */
\r
364 #define USBHS_DEVEPTISR_DTSEQ_Pos 8
\r
365 #define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */
\r
366 #define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */
\r
367 #define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */
\r
368 #define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */
\r
369 #define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */
\r
370 #define USBHS_DEVEPTISR_NBUSYBK_Pos 12
\r
371 #define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */
\r
372 #define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */
\r
373 #define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */
\r
374 #define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */
\r
375 #define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */
\r
376 #define USBHS_DEVEPTISR_CURRBK_Pos 14
\r
377 #define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */
\r
378 #define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */
\r
379 #define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */
\r
380 #define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */
\r
381 #define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */
\r
382 #define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */
\r
383 #define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */
\r
384 #define USBHS_DEVEPTISR_BYCT_Pos 20
\r
385 #define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */
\r
386 #define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */
\r
387 #define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */
\r
388 #define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */
\r
389 #define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */
\r
390 #define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */
\r
391 /* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */
\r
392 #define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */
\r
393 #define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */
\r
394 #define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */
\r
395 #define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */
\r
396 #define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */
\r
397 #define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */
\r
398 #define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */
\r
399 #define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */
\r
400 #define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */
\r
401 #define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */
\r
402 #define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
\r
403 #define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */
\r
404 /* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */
\r
405 #define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */
\r
406 #define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */
\r
407 #define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */
\r
408 #define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */
\r
409 #define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */
\r
410 #define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */
\r
411 #define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */
\r
412 #define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */
\r
413 #define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */
\r
414 #define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */
\r
415 #define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */
\r
416 #define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */
\r
417 #define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */
\r
418 /* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */
\r
419 #define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */
\r
420 #define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */
\r
421 #define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */
\r
422 #define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */
\r
423 #define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */
\r
424 #define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */
\r
425 #define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */
\r
426 #define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */
\r
427 #define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */
\r
428 #define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */
\r
429 #define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */
\r
430 #define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */
\r
431 #define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */
\r
432 #define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */
\r
433 #define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */
\r
434 #define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */
\r
435 #define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */
\r
436 #define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */
\r
437 #define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */
\r
438 #define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */
\r
439 #define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */
\r
440 #define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */
\r
441 /* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */
\r
442 #define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */
\r
443 #define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */
\r
444 #define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */
\r
445 #define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */
\r
446 #define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */
\r
447 #define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */
\r
448 #define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */
\r
449 #define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */
\r
450 #define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */
\r
451 #define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */
\r
452 #define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */
\r
453 #define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */
\r
454 #define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */
\r
455 #define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */
\r
456 #define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */
\r
457 #define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */
\r
458 #define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */
\r
459 #define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */
\r
460 #define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */
\r
461 #define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */
\r
462 #define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */
\r
463 #define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */
\r
464 /* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */
\r
465 #define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */
\r
466 #define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */
\r
467 #define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */
\r
468 #define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */
\r
469 #define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */
\r
470 #define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */
\r
471 #define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */
\r
472 #define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */
\r
473 #define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */
\r
474 #define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */
\r
475 #define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */
\r
476 #define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */
\r
477 #define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */
\r
478 #define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */
\r
479 #define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */
\r
480 #define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
\r
481 #define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */
\r
482 #define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */
\r
483 #define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */
\r
484 #define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */
\r
485 /* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */
\r
486 #define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0
\r
487 #define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */
\r
488 #define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))
\r
489 /* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */
\r
490 #define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0
\r
491 #define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */
\r
492 #define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)))
\r
493 /* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */
\r
494 #define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */
\r
495 #define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
\r
496 #define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */
\r
497 #define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */
\r
498 #define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */
\r
499 #define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */
\r
500 #define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */
\r
501 #define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */
\r
502 #define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16
\r
503 #define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */
\r
504 #define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))
\r
505 /* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */
\r
506 #define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */
\r
507 #define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */
\r
508 #define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */
\r
509 #define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */
\r
510 #define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */
\r
511 #define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16
\r
512 #define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */
\r
513 #define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)))
\r
514 /* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */
\r
515 #define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */
\r
516 #define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */
\r
517 #define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */
\r
518 #define USBHS_HSTCTRL_SPDCONF_Pos 12
\r
519 #define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */
\r
520 #define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)))
\r
521 #define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */
\r
522 #define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */
\r
523 #define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (USBHS_HSTCTRL) Forced high speed. */
\r
524 #define USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */
\r
525 /* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */
\r
526 #define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */
\r
527 #define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */
\r
528 #define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */
\r
529 #define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */
\r
530 #define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */
\r
531 #define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */
\r
532 #define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */
\r
533 #define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */
\r
534 #define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */
\r
535 #define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */
\r
536 #define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */
\r
537 #define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */
\r
538 #define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */
\r
539 #define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */
\r
540 #define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */
\r
541 #define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */
\r
542 #define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */
\r
543 #define USBHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTISR) Pipe 10 Interrupt */
\r
544 #define USBHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTISR) Pipe 11 Interrupt */
\r
545 #define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */
\r
546 #define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */
\r
547 #define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */
\r
548 #define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */
\r
549 #define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */
\r
550 #define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */
\r
551 #define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */
\r
552 /* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */
\r
553 #define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */
\r
554 #define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */
\r
555 #define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */
\r
556 #define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */
\r
557 #define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */
\r
558 #define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */
\r
559 #define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */
\r
560 /* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */
\r
561 #define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */
\r
562 #define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */
\r
563 #define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */
\r
564 #define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */
\r
565 #define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */
\r
566 #define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */
\r
567 #define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */
\r
568 #define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */
\r
569 #define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */
\r
570 #define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */
\r
571 #define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */
\r
572 #define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */
\r
573 #define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */
\r
574 #define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */
\r
575 /* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */
\r
576 #define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */
\r
577 #define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */
\r
578 #define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */
\r
579 #define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */
\r
580 #define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */
\r
581 #define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */
\r
582 #define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */
\r
583 #define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */
\r
584 #define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */
\r
585 #define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */
\r
586 #define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */
\r
587 #define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */
\r
588 #define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */
\r
589 #define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */
\r
590 #define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */
\r
591 #define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */
\r
592 #define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */
\r
593 #define USBHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIMR) Pipe 10 Interrupt Enable */
\r
594 #define USBHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIMR) Pipe 11 Interrupt Enable */
\r
595 #define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */
\r
596 #define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */
\r
597 #define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */
\r
598 #define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */
\r
599 #define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */
\r
600 #define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */
\r
601 #define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */
\r
602 /* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */
\r
603 #define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */
\r
604 #define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */
\r
605 #define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */
\r
606 #define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */
\r
607 #define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */
\r
608 #define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */
\r
609 #define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */
\r
610 #define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */
\r
611 #define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */
\r
612 #define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */
\r
613 #define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */
\r
614 #define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */
\r
615 #define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */
\r
616 #define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */
\r
617 #define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */
\r
618 #define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */
\r
619 #define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */
\r
620 #define USBHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIDR) Pipe 10 Interrupt Disable */
\r
621 #define USBHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIDR) Pipe 11 Interrupt Disable */
\r
622 #define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */
\r
623 #define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */
\r
624 #define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */
\r
625 #define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */
\r
626 #define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */
\r
627 #define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */
\r
628 #define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */
\r
629 /* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */
\r
630 #define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */
\r
631 #define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */
\r
632 #define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */
\r
633 #define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */
\r
634 #define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */
\r
635 #define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */
\r
636 #define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */
\r
637 #define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */
\r
638 #define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */
\r
639 #define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */
\r
640 #define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */
\r
641 #define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */
\r
642 #define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */
\r
643 #define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */
\r
644 #define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */
\r
645 #define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */
\r
646 #define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */
\r
647 #define USBHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIER) Pipe 10 Interrupt Enable */
\r
648 #define USBHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIER) Pipe 11 Interrupt Enable */
\r
649 #define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */
\r
650 #define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */
\r
651 #define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */
\r
652 #define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */
\r
653 #define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */
\r
654 #define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */
\r
655 #define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */
\r
656 /* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */
\r
657 #define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */
\r
658 #define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */
\r
659 #define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */
\r
660 #define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */
\r
661 #define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */
\r
662 #define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */
\r
663 #define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */
\r
664 #define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */
\r
665 #define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */
\r
666 #define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */
\r
667 #define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */
\r
668 #define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */
\r
669 #define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */
\r
670 #define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */
\r
671 #define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */
\r
672 #define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */
\r
673 #define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */
\r
674 #define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */
\r
675 /* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */
\r
676 #define USBHS_HSTFNUM_MFNUM_Pos 0
\r
677 #define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */
\r
678 #define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)))
\r
679 #define USBHS_HSTFNUM_FNUM_Pos 3
\r
680 #define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */
\r
681 #define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)))
\r
682 #define USBHS_HSTFNUM_FLENHIGH_Pos 16
\r
683 #define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */
\r
684 #define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)))
\r
685 /* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */
\r
686 #define USBHS_HSTADDR1_HSTADDRP0_Pos 0
\r
687 #define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */
\r
688 #define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)))
\r
689 #define USBHS_HSTADDR1_HSTADDRP1_Pos 8
\r
690 #define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */
\r
691 #define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)))
\r
692 #define USBHS_HSTADDR1_HSTADDRP2_Pos 16
\r
693 #define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */
\r
694 #define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)))
\r
695 #define USBHS_HSTADDR1_HSTADDRP3_Pos 24
\r
696 #define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */
\r
697 #define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)))
\r
698 /* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */
\r
699 #define USBHS_HSTADDR2_HSTADDRP4_Pos 0
\r
700 #define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */
\r
701 #define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)))
\r
702 #define USBHS_HSTADDR2_HSTADDRP5_Pos 8
\r
703 #define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */
\r
704 #define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)))
\r
705 #define USBHS_HSTADDR2_HSTADDRP6_Pos 16
\r
706 #define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */
\r
707 #define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)))
\r
708 #define USBHS_HSTADDR2_HSTADDRP7_Pos 24
\r
709 #define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */
\r
710 #define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)))
\r
711 /* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */
\r
712 #define USBHS_HSTADDR3_HSTADDRP8_Pos 0
\r
713 #define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */
\r
714 #define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)))
\r
715 #define USBHS_HSTADDR3_HSTADDRP9_Pos 8
\r
716 #define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */
\r
717 #define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)))
\r
718 /* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */
\r
719 #define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */
\r
720 #define USBHS_HSTPIPCFG_PBK_Pos 2
\r
721 #define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */
\r
722 #define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)))
\r
723 #define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */
\r
724 #define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */
\r
725 #define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */
\r
726 #define USBHS_HSTPIPCFG_PSIZE_Pos 4
\r
727 #define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */
\r
728 #define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)))
\r
729 #define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */
\r
730 #define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */
\r
731 #define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */
\r
732 #define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */
\r
733 #define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */
\r
734 #define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */
\r
735 #define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */
\r
736 #define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */
\r
737 #define USBHS_HSTPIPCFG_PTOKEN_Pos 8
\r
738 #define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */
\r
739 #define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)))
\r
740 #define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */
\r
741 #define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */
\r
742 #define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */
\r
743 #define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */
\r
744 #define USBHS_HSTPIPCFG_PTYPE_Pos 12
\r
745 #define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */
\r
746 #define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)))
\r
747 #define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */
\r
748 #define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */
\r
749 #define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */
\r
750 #define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */
\r
751 #define USBHS_HSTPIPCFG_PEPNUM_Pos 16
\r
752 #define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */
\r
753 #define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)))
\r
754 #define USBHS_HSTPIPCFG_INTFRQ_Pos 24
\r
755 #define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */
\r
756 #define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)))
\r
757 #define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */
\r
758 #define USBHS_HSTPIPCFG_BINTERVAL_Pos 24
\r
759 #define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */
\r
760 #define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos)))
\r
761 /* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */
\r
762 #define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */
\r
763 #define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */
\r
764 #define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */
\r
765 #define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */
\r
766 #define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */
\r
767 #define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */
\r
768 #define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */
\r
769 #define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */
\r
770 #define USBHS_HSTPIPISR_DTSEQ_Pos 8
\r
771 #define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */
\r
772 #define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */
\r
773 #define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */
\r
774 #define USBHS_HSTPIPISR_NBUSYBK_Pos 12
\r
775 #define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */
\r
776 #define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */
\r
777 #define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */
\r
778 #define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */
\r
779 #define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */
\r
780 #define USBHS_HSTPIPISR_CURRBK_Pos 14
\r
781 #define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */
\r
782 #define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */
\r
783 #define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */
\r
784 #define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */
\r
785 #define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */
\r
786 #define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */
\r
787 #define USBHS_HSTPIPISR_PBYCT_Pos 20
\r
788 #define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */
\r
789 #define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */
\r
790 #define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */
\r
791 /* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */
\r
792 #define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */
\r
793 #define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */
\r
794 #define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */
\r
795 #define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */
\r
796 #define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */
\r
797 #define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */
\r
798 #define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */
\r
799 #define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */
\r
800 #define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */
\r
801 /* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */
\r
802 #define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */
\r
803 #define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */
\r
804 #define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */
\r
805 #define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */
\r
806 #define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */
\r
807 #define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */
\r
808 #define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */
\r
809 #define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */
\r
810 #define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */
\r
811 #define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */
\r
812 #define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */
\r
813 /* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */
\r
814 #define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */
\r
815 #define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */
\r
816 #define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */
\r
817 #define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */
\r
818 #define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */
\r
819 #define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */
\r
820 #define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */
\r
821 #define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */
\r
822 #define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */
\r
823 #define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */
\r
824 #define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */
\r
825 #define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */
\r
826 #define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */
\r
827 #define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */
\r
828 #define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */
\r
829 /* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */
\r
830 #define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */
\r
831 #define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */
\r
832 #define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */
\r
833 #define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */
\r
834 #define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */
\r
835 #define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */
\r
836 #define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */
\r
837 #define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */
\r
838 #define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */
\r
839 #define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */
\r
840 #define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */
\r
841 #define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */
\r
842 #define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */
\r
843 #define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */
\r
844 /* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */
\r
845 #define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */
\r
846 #define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */
\r
847 #define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */
\r
848 #define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */
\r
849 #define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */
\r
850 #define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */
\r
851 #define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */
\r
852 #define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */
\r
853 #define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */
\r
854 #define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */
\r
855 #define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */
\r
856 #define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */
\r
857 #define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */
\r
858 #define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */
\r
859 /* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */
\r
860 #define USBHS_HSTPIPINRQ_INRQ_Pos 0
\r
861 #define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */
\r
862 #define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)))
\r
863 #define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */
\r
864 /* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */
\r
865 #define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */
\r
866 #define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */
\r
867 #define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */
\r
868 #define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */
\r
869 #define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */
\r
870 #define USBHS_HSTPIPERR_COUNTER_Pos 5
\r
871 #define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */
\r
872 #define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)))
\r
873 /* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */
\r
874 #define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0
\r
875 #define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */
\r
876 #define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))
\r
877 /* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */
\r
878 #define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0
\r
879 #define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */
\r
880 #define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)))
\r
881 /* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */
\r
882 #define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */
\r
883 #define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
\r
884 #define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */
\r
885 #define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */
\r
886 #define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */
\r
887 #define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */
\r
888 #define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */
\r
889 #define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */
\r
890 #define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16
\r
891 #define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */
\r
892 #define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))
\r
893 /* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */
\r
894 #define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */
\r
895 #define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */
\r
896 #define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */
\r
897 #define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */
\r
898 #define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */
\r
899 #define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16
\r
900 #define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */
\r
901 #define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)))
\r
902 /* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */
\r
903 #define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */
\r
904 #define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */
\r
905 #define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */
\r
906 #define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */
\r
907 #define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */
\r
908 #define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */
\r
909 /* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */
\r
910 #define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */
\r
911 #define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBus Request (Host mode only) */
\r
912 #define USBHS_SR_SPEED_Pos 12
\r
913 #define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */
\r
914 #define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */
\r
915 #define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */
\r
916 #define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */
\r
917 #define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */
\r
918 /* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */
\r
919 #define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */
\r
920 #define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBus Request Clear */
\r
921 /* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */
\r
922 #define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */
\r
923 #define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBus Request Set */
\r
924 /* -------- USBHS_TSTA1 : (USBHS Offset: 0x0810) General Test A1 Register -------- */
\r
925 #define USBHS_TSTA1_CounterA_Pos 0
\r
926 #define USBHS_TSTA1_CounterA_Msk (0x7fffu << USBHS_TSTA1_CounterA_Pos) /**< \brief (USBHS_TSTA1) Counter A */
\r
927 #define USBHS_TSTA1_CounterA(value) ((USBHS_TSTA1_CounterA_Msk & ((value) << USBHS_TSTA1_CounterA_Pos)))
\r
928 #define USBHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (USBHS_TSTA1) Load CounterA */
\r
929 #define USBHS_TSTA1_CounterB_Pos 16
\r
930 #define USBHS_TSTA1_CounterB_Msk (0x3fu << USBHS_TSTA1_CounterB_Pos) /**< \brief (USBHS_TSTA1) Counter B */
\r
931 #define USBHS_TSTA1_CounterB(value) ((USBHS_TSTA1_CounterB_Msk & ((value) << USBHS_TSTA1_CounterB_Pos)))
\r
932 #define USBHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (USBHS_TSTA1) Load CounterB */
\r
933 #define USBHS_TSTA1_SOFCntMa1_Pos 24
\r
934 #define USBHS_TSTA1_SOFCntMa1_Msk (0x7fu << USBHS_TSTA1_SOFCntMa1_Pos) /**< \brief (USBHS_TSTA1) SOF Counter Max */
\r
935 #define USBHS_TSTA1_SOFCntMa1(value) ((USBHS_TSTA1_SOFCntMa1_Msk & ((value) << USBHS_TSTA1_SOFCntMa1_Pos)))
\r
936 #define USBHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (USBHS_TSTA1) Load SOF Counter */
\r
937 /* -------- USBHS_TSTA2 : (USBHS Offset: 0x0814) General Test A2 Register -------- */
\r
938 #define USBHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (USBHS_TSTA2) Full Detach Enable */
\r
939 #define USBHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (USBHS_TSTA2) HS Serial Mode */
\r
940 #define USBHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (USBHS_TSTA2) Loop-back Mode */
\r
941 #define USBHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (USBHS_TSTA2) Disable Gated Clock */
\r
942 #define USBHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (USBHS_TSTA2) Force SuspendM to 1 */
\r
943 #define USBHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (USBHS_TSTA2) Bypass DPLL */
\r
944 #define USBHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (USBHS_TSTA2) Host HS Disconnect Disable */
\r
945 #define USBHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (USBHS_TSTA2) Force HS Reset to 50 ms */
\r
946 #define USBHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (USBHS_TSTA2) Remove Pull-up When TX */
\r
947 /* -------- USBHS_VERSION : (USBHS Offset: 0x0818) General Version Register -------- */
\r
948 #define USBHS_VERSION_VERSION_Pos 0
\r
949 #define USBHS_VERSION_VERSION_Msk (0xfffu << USBHS_VERSION_VERSION_Pos) /**< \brief (USBHS_VERSION) Version Number */
\r
950 #define USBHS_VERSION_MFN_Pos 16
\r
951 #define USBHS_VERSION_MFN_Msk (0xfu << USBHS_VERSION_MFN_Pos) /**< \brief (USBHS_VERSION) Metal Fix Number */
\r
952 /* -------- USBHS_FSM : (USBHS Offset: 0x082C) General Finite State Machine Register -------- */
\r
953 #define USBHS_FSM_DRDSTATE_Pos 0
\r
954 #define USBHS_FSM_DRDSTATE_Msk (0xfu << USBHS_FSM_DRDSTATE_Pos) /**< \brief (USBHS_FSM) Dual Role Device State */
\r
955 #define USBHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (USBHS_FSM) This is the start state for A-devices (when the ID pin is 0) */
\r
956 #define USBHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */
\r
957 #define USBHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */
\r
958 #define USBHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (USBHS_FSM) In this state, the A-device that operates in Host mode is operational. */
\r
959 #define USBHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (USBHS_FSM) The A-device operating as a host is in the Suspend mode. */
\r
960 #define USBHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (USBHS_FSM) The A-device operates as a peripheral. */
\r
961 #define USBHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */
\r
962 #define USBHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */
\r
963 #define USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */
\r
964 #define USBHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (USBHS_FSM) This is the start state for B-device (when the ID pin is 1). */
\r
965 #define USBHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the peripheral. */
\r
966 #define USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (USBHS_FSM) In this state, the B-device is in Suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */
\r
967 #define USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us)) before becoming Host. */
\r
968 #define USBHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */
\r
969 #define USBHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the Host. */
\r
970 #define USBHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (USBHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */
\r
975 #endif /* _SAME70_USBHS_COMPONENT_ */
\r
projects / freertos / blob