4 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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20 * 3. The name of Atmel may not be used to endorse or promote products derived
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21 * from this software without specific prior written permission.
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23 * 4. This software may only be redistributed and used in connection with an
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24 * Atmel microcontroller product.
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26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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36 * POSSIBILITY OF SUCH DAMAGE.
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42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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48 /** \addtogroup SAME70Q21_definitions SAME70Q21 definitions
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49 This file defines all structures and symbols for SAME70Q21:
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50 - registers and bitfields
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51 - peripheral base address
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61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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65 /* ************************************************************************** */
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66 /* CMSIS DEFINITIONS FOR SAME70Q21 */
\r
67 /* ************************************************************************** */
\r
68 /** \addtogroup SAME70Q21_cmsis CMSIS Definitions */
\r
71 /**< Interrupt Number Definition */
\r
74 /****** Cortex-M7 Processor Exceptions Numbers ******************************/
\r
75 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
\r
76 HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
\r
77 MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
\r
78 BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
\r
79 UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
\r
80 SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
\r
81 DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
\r
82 PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
\r
83 SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
\r
84 /****** SAME70Q21 specific Interrupt Numbers *********************************/
\r
86 SUPC_IRQn = 0, /**< 0 SAME70Q21 Supply Controller (SUPC) */
\r
87 RSTC_IRQn = 1, /**< 1 SAME70Q21 Reset Controller (RSTC) */
\r
88 RTC_IRQn = 2, /**< 2 SAME70Q21 Real Time Clock (RTC) */
\r
89 RTT_IRQn = 3, /**< 3 SAME70Q21 Real Time Timer (RTT) */
\r
90 WDT_IRQn = 4, /**< 4 SAME70Q21 Watchdog Timer (WDT) */
\r
91 PMC_IRQn = 5, /**< 5 SAME70Q21 Power Management Controller (PMC) */
\r
92 EFC_IRQn = 6, /**< 6 SAME70Q21 Enhanced Embedded Flash Controller (EFC) */
\r
93 UART0_IRQn = 7, /**< 7 SAME70Q21 UART 0 (UART0) */
\r
94 UART1_IRQn = 8, /**< 8 SAME70Q21 UART 1 (UART1) */
\r
95 PIOA_IRQn = 10, /**< 10 SAME70Q21 Parallel I/O Controller A (PIOA) */
\r
96 PIOB_IRQn = 11, /**< 11 SAME70Q21 Parallel I/O Controller B (PIOB) */
\r
97 PIOC_IRQn = 12, /**< 12 SAME70Q21 Parallel I/O Controller C (PIOC) */
\r
98 USART0_IRQn = 13, /**< 13 SAME70Q21 USART 0 (USART0) */
\r
99 USART1_IRQn = 14, /**< 14 SAME70Q21 USART 1 (USART1) */
\r
100 USART2_IRQn = 15, /**< 15 SAME70Q21 USART 2 (USART2) */
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101 PIOD_IRQn = 16, /**< 16 SAME70Q21 Parallel I/O Controller D (PIOD) */
\r
102 PIOE_IRQn = 17, /**< 17 SAME70Q21 Parallel I/O Controller E (PIOE) */
\r
103 HSMCI_IRQn = 18, /**< 18 SAME70Q21 Multimedia Card Interface (HSMCI) */
\r
104 TWIHS0_IRQn = 19, /**< 19 SAME70Q21 Two Wire Interface 0 HS (TWIHS0) */
\r
105 TWIHS1_IRQn = 20, /**< 20 SAME70Q21 Two Wire Interface 1 HS (TWIHS1) */
\r
106 SPI0_IRQn = 21, /**< 21 SAME70Q21 Serial Peripheral Interface 0 (SPI0) */
\r
107 SSC_IRQn = 22, /**< 22 SAME70Q21 Synchronous Serial Controller (SSC) */
\r
108 TC0_IRQn = 23, /**< 23 SAME70Q21 Timer/Counter 0 (TC0) */
\r
109 TC1_IRQn = 24, /**< 24 SAME70Q21 Timer/Counter 1 (TC1) */
\r
110 TC2_IRQn = 25, /**< 25 SAME70Q21 Timer/Counter 2 (TC2) */
\r
111 TC3_IRQn = 26, /**< 26 SAME70Q21 Timer/Counter 3 (TC3) */
\r
112 TC4_IRQn = 27, /**< 27 SAME70Q21 Timer/Counter 4 (TC4) */
\r
113 TC5_IRQn = 28, /**< 28 SAME70Q21 Timer/Counter 5 (TC5) */
\r
114 AFEC0_IRQn = 29, /**< 29 SAME70Q21 Analog Front End 0 (AFEC0) */
\r
115 DACC_IRQn = 30, /**< 30 SAME70Q21 Digital To Analog Converter (DACC) */
\r
116 PWM0_IRQn = 31, /**< 31 SAME70Q21 Pulse Width Modulation 0 (PWM0) */
\r
117 ICM_IRQn = 32, /**< 32 SAME70Q21 Integrity Check Monitor (ICM) */
\r
118 ACC_IRQn = 33, /**< 33 SAME70Q21 Analog Comparator (ACC) */
\r
119 USBHS_IRQn = 34, /**< 34 SAME70Q21 USB Host / Device Controller (USBHS) */
\r
120 MCAN0_IRQn = 35, /**< 35 SAME70Q21 MCAN Controller 0 (MCAN0) */
\r
121 MCAN1_IRQn = 37, /**< 37 SAME70Q21 MCAN Controller 1 (MCAN1) */
\r
122 GMAC_IRQn = 39, /**< 39 SAME70Q21 Ethernet MAC (GMAC) */
\r
123 AFEC1_IRQn = 40, /**< 40 SAME70Q21 Analog Front End 1 (AFEC1) */
\r
124 TWIHS2_IRQn = 41, /**< 41 SAME70Q21 Two Wire Interface 2 HS (TWIHS2) */
\r
125 SPI1_IRQn = 42, /**< 42 SAME70Q21 Serial Peripheral Interface 1 (SPI1) */
\r
126 QSPI_IRQn = 43, /**< 43 SAME70Q21 Quad I/O Serial Peripheral Interface (QSPI) */
\r
127 UART2_IRQn = 44, /**< 44 SAME70Q21 UART 2 (UART2) */
\r
128 UART3_IRQn = 45, /**< 45 SAME70Q21 UART 3 (UART3) */
\r
129 UART4_IRQn = 46, /**< 46 SAME70Q21 UART 4 (UART4) */
\r
130 TC6_IRQn = 47, /**< 47 SAME70Q21 Timer/Counter 6 (TC6) */
\r
131 TC7_IRQn = 48, /**< 48 SAME70Q21 Timer/Counter 7 (TC7) */
\r
132 TC8_IRQn = 49, /**< 49 SAME70Q21 Timer/Counter 8 (TC8) */
\r
133 TC9_IRQn = 50, /**< 50 SAME70Q21 Timer/Counter 9 (TC9) */
\r
134 TC10_IRQn = 51, /**< 51 SAME70Q21 Timer/Counter 10 (TC10) */
\r
135 TC11_IRQn = 52, /**< 52 SAME70Q21 Timer/Counter 11 (TC11) */
\r
136 AES_IRQn = 56, /**< 56 SAME70Q21 AES (AES) */
\r
137 TRNG_IRQn = 57, /**< 57 SAME70Q21 True Random Generator (TRNG) */
\r
138 XDMAC_IRQn = 58, /**< 58 SAME70Q21 DMA (XDMAC) */
\r
139 ISI_IRQn = 59, /**< 59 SAME70Q21 Camera Interface (ISI) */
\r
140 PWM1_IRQn = 60, /**< 60 SAME70Q21 Pulse Width Modulation 1 (PWM1) */
\r
141 SDRAMC_IRQn = 62, /**< 62 SAME70Q21 SDRAM Controller (SDRAMC) */
\r
142 RSWDT_IRQn = 63, /**< 63 SAME70Q21 Reinforced Secure Watchdog Timer (RSWDT) */
\r
144 PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
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147 typedef struct _DeviceVectors
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149 /* Stack pointer */
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152 /* Cortex-M handlers */
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153 void* pfnReset_Handler;
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154 void* pfnNMI_Handler;
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155 void* pfnHardFault_Handler;
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156 void* pfnMemManage_Handler;
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157 void* pfnBusFault_Handler;
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158 void* pfnUsageFault_Handler;
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159 void* pfnReserved1_Handler;
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160 void* pfnReserved2_Handler;
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161 void* pfnReserved3_Handler;
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162 void* pfnReserved4_Handler;
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163 void* pfnSVC_Handler;
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164 void* pfnDebugMon_Handler;
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165 void* pfnReserved5_Handler;
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166 void* pfnPendSV_Handler;
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167 void* pfnSysTick_Handler;
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169 /* Peripheral handlers */
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170 void* pfnSUPC_Handler; /* 0 Supply Controller */
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171 void* pfnRSTC_Handler; /* 1 Reset Controller */
\r
172 void* pfnRTC_Handler; /* 2 Real Time Clock */
\r
173 void* pfnRTT_Handler; /* 3 Real Time Timer */
\r
174 void* pfnWDT_Handler; /* 4 Watchdog Timer */
\r
175 void* pfnPMC_Handler; /* 5 Power Management Controller */
\r
176 void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
\r
177 void* pfnUART0_Handler; /* 7 UART 0 */
\r
178 void* pfnUART1_Handler; /* 8 UART 1 */
\r
180 void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
\r
181 void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
\r
182 void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */
\r
183 void* pfnUSART0_Handler; /* 13 USART 0 */
\r
184 void* pfnUSART1_Handler; /* 14 USART 1 */
\r
185 void* pfnUSART2_Handler; /* 15 USART 2 */
\r
186 void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
\r
187 void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */
\r
188 void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
\r
189 void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
\r
190 void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
\r
191 void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
\r
192 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
\r
193 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
\r
194 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
\r
195 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
\r
196 void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
\r
197 void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
\r
198 void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
\r
199 void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
\r
200 void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
\r
201 void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
\r
202 void* pfnICM_Handler; /* 32 Integrity Check Monitor */
\r
203 void* pfnACC_Handler; /* 33 Analog Comparator */
\r
204 void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
\r
205 void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */
\r
206 void* pvReserved36;
\r
207 void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */
\r
208 void* pvReserved38;
\r
209 void* pfnGMAC_Handler; /* 39 Ethernet MAC */
\r
210 void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
\r
211 void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
\r
212 void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
\r
213 void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
\r
214 void* pfnUART2_Handler; /* 44 UART 2 */
\r
215 void* pfnUART3_Handler; /* 45 UART 3 */
\r
216 void* pfnUART4_Handler; /* 46 UART 4 */
\r
217 void* pfnTC6_Handler; /* 47 Timer/Counter 6 */
\r
218 void* pfnTC7_Handler; /* 48 Timer/Counter 7 */
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219 void* pfnTC8_Handler; /* 49 Timer/Counter 8 */
\r
220 void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
\r
221 void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
\r
222 void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
\r
223 void* pvReserved53;
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224 void* pvReserved54;
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225 void* pvReserved55;
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226 void* pfnAES_Handler; /* 56 AES */
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227 void* pfnTRNG_Handler; /* 57 True Random Generator */
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228 void* pfnXDMAC_Handler; /* 58 DMA */
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229 void* pfnISI_Handler; /* 59 Camera Interface */
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230 void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
\r
231 void* pvReserved61;
\r
232 void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
\r
233 void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
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236 /* Cortex-M7 core handlers */
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237 void Reset_Handler ( void );
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238 void NMI_Handler ( void );
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239 void HardFault_Handler ( void );
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240 void MemManage_Handler ( void );
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241 void BusFault_Handler ( void );
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242 void UsageFault_Handler ( void );
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243 void SVC_Handler ( void );
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244 void DebugMon_Handler ( void );
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245 void PendSV_Handler ( void );
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246 void SysTick_Handler ( void );
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248 /* Peripherals handlers */
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249 void ACC_Handler ( void );
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250 void AES_Handler ( void );
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251 void AFEC0_Handler ( void );
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252 void AFEC1_Handler ( void );
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253 void DACC_Handler ( void );
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254 void EFC_Handler ( void );
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255 void GMAC_Handler ( void );
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256 void HSMCI_Handler ( void );
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257 void ICM_Handler ( void );
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258 void ISI_Handler ( void );
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259 void MCAN0_Handler ( void );
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260 void MCAN1_Handler ( void );
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261 void PIOA_Handler ( void );
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262 void PIOB_Handler ( void );
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263 void PIOC_Handler ( void );
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264 void PIOD_Handler ( void );
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265 void PIOE_Handler ( void );
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266 void PMC_Handler ( void );
\r
267 void PWM0_Handler ( void );
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268 void PWM1_Handler ( void );
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269 void QSPI_Handler ( void );
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270 void RSTC_Handler ( void );
\r
271 void RSWDT_Handler ( void );
\r
272 void RTC_Handler ( void );
\r
273 void RTT_Handler ( void );
\r
274 void SDRAMC_Handler ( void );
\r
275 void SPI0_Handler ( void );
\r
276 void SPI1_Handler ( void );
\r
277 void SSC_Handler ( void );
\r
278 void SUPC_Handler ( void );
\r
279 void TC0_Handler ( void );
\r
280 void TC1_Handler ( void );
\r
281 void TC2_Handler ( void );
\r
282 void TC3_Handler ( void );
\r
283 void TC4_Handler ( void );
\r
284 void TC5_Handler ( void );
\r
285 void TC6_Handler ( void );
\r
286 void TC7_Handler ( void );
\r
287 void TC8_Handler ( void );
\r
288 void TC9_Handler ( void );
\r
289 void TC10_Handler ( void );
\r
290 void TC11_Handler ( void );
\r
291 void TRNG_Handler ( void );
\r
292 void TWIHS0_Handler ( void );
\r
293 void TWIHS1_Handler ( void );
\r
294 void TWIHS2_Handler ( void );
\r
295 void UART0_Handler ( void );
\r
296 void UART1_Handler ( void );
\r
297 void UART2_Handler ( void );
\r
298 void UART3_Handler ( void );
\r
299 void UART4_Handler ( void );
\r
300 void USART0_Handler ( void );
\r
301 void USART1_Handler ( void );
\r
302 void USART2_Handler ( void );
\r
303 void USBHS_Handler ( void );
\r
304 void WDT_Handler ( void );
\r
305 void XDMAC_Handler ( void );
\r
308 * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
\r
311 #define __CM7_REV 0x0000 /**< SAME70Q21 core revision number ([15:8] revision number, [7:0] patch number) */
\r
312 #define __MPU_PRESENT 1 /**< SAME70Q21 does provide a MPU */
\r
313 #define __NVIC_PRIO_BITS 3 /**< SAME70Q21 uses 3 Bits for the Priority Levels */
\r
314 #define __FPU_PRESENT 1 /**< SAME70Q21 does provide a FPU */
\r
315 #define __FPU_DP 1 /**< SAME70Q21 Double precision FPU */
\r
316 #define __ICACHE_PRESENT 1 /**< SAME70Q21 does provide an Instruction Cache */
\r
317 #define __DCACHE_PRESENT 1 /**< SAME70Q21 does provide a Data Cache */
\r
318 #define __DTCM_PRESENT 1 /**< SAME70Q21 does provide a Data TCM */
\r
319 #define __ITCM_PRESENT 1 /**< SAME70Q21 does provide an Instruction TCM */
\r
320 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
\r
323 * \brief CMSIS includes
\r
326 #include <core_cm7.h>
\r
327 #if !defined DONT_USE_CMSIS_INIT
\r
328 #include "system_same70.h"
\r
329 #endif /* DONT_USE_CMSIS_INIT */
\r
333 /* ************************************************************************** */
\r
334 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q21 */
\r
335 /* ************************************************************************** */
\r
336 /** \addtogroup SAME70Q21_api Peripheral Software API */
\r
339 #include "component/acc.h"
\r
340 #include "component/aes.h"
\r
341 #include "component/afec.h"
\r
342 #include "component/chipid.h"
\r
343 #include "component/dacc.h"
\r
344 #include "component/efc.h"
\r
345 #include "component/gmac.h"
\r
346 #include "component/gpbr.h"
\r
347 #include "component/hsmci.h"
\r
348 #include "component/icm.h"
\r
349 #include "component/isi.h"
\r
350 #include "component/matrix.h"
\r
351 #include "component/mcan.h"
\r
352 #include "component/pio.h"
\r
353 #include "component/pmc.h"
\r
354 #include "component/pwm.h"
\r
355 #include "component/qspi.h"
\r
356 #include "component/rstc.h"
\r
357 #include "component/rswdt.h"
\r
358 #include "component/rtc.h"
\r
359 #include "component/rtt.h"
\r
360 #include "component/sdramc.h"
\r
361 #include "component/smc.h"
\r
362 #include "component/spi.h"
\r
363 #include "component/ssc.h"
\r
364 #include "component/supc.h"
\r
365 #include "component/tc.h"
\r
366 #include "component/trng.h"
\r
367 #include "component/twihs.h"
\r
368 #include "component/uart.h"
\r
369 #include "component/usart.h"
\r
370 #include "component/usbhs.h"
\r
371 #include "component/utmi.h"
\r
372 #include "component/wdt.h"
\r
373 #include "component/xdmac.h"
\r
376 /* ************************************************************************** */
\r
377 /* REGISTER ACCESS DEFINITIONS FOR SAME70Q21 */
\r
378 /* ************************************************************************** */
\r
379 /** \addtogroup SAME70Q21_reg Registers Access Definitions */
\r
382 #include "instance/hsmci.h"
\r
383 #include "instance/ssc.h"
\r
384 #include "instance/spi0.h"
\r
385 #include "instance/tc0.h"
\r
386 #include "instance/tc1.h"
\r
387 #include "instance/tc2.h"
\r
388 #include "instance/twihs0.h"
\r
389 #include "instance/twihs1.h"
\r
390 #include "instance/pwm0.h"
\r
391 #include "instance/usart0.h"
\r
392 #include "instance/usart1.h"
\r
393 #include "instance/usart2.h"
\r
394 #include "instance/mcan0.h"
\r
395 #include "instance/mcan1.h"
\r
396 #include "instance/usbhs.h"
\r
397 #include "instance/afec0.h"
\r
398 #include "instance/dacc.h"
\r
399 #include "instance/acc.h"
\r
400 #include "instance/icm.h"
\r
401 #include "instance/isi.h"
\r
402 #include "instance/gmac.h"
\r
403 #include "instance/tc3.h"
\r
404 #include "instance/spi1.h"
\r
405 #include "instance/pwm1.h"
\r
406 #include "instance/twihs2.h"
\r
407 #include "instance/afec1.h"
\r
408 #include "instance/aes.h"
\r
409 #include "instance/trng.h"
\r
410 #include "instance/xdmac.h"
\r
411 #include "instance/qspi.h"
\r
412 #include "instance/smc.h"
\r
413 #include "instance/sdramc.h"
\r
414 #include "instance/matrix.h"
\r
415 #include "instance/utmi.h"
\r
416 #include "instance/pmc.h"
\r
417 #include "instance/uart0.h"
\r
418 #include "instance/chipid.h"
\r
419 #include "instance/uart1.h"
\r
420 #include "instance/efc.h"
\r
421 #include "instance/pioa.h"
\r
422 #include "instance/piob.h"
\r
423 #include "instance/pioc.h"
\r
424 #include "instance/piod.h"
\r
425 #include "instance/pioe.h"
\r
426 #include "instance/rstc.h"
\r
427 #include "instance/supc.h"
\r
428 #include "instance/rtt.h"
\r
429 #include "instance/wdt.h"
\r
430 #include "instance/rtc.h"
\r
431 #include "instance/gpbr.h"
\r
432 #include "instance/rswdt.h"
\r
433 #include "instance/uart2.h"
\r
434 #include "instance/uart3.h"
\r
435 #include "instance/uart4.h"
\r
438 /* ************************************************************************** */
\r
439 /* PERIPHERAL ID DEFINITIONS FOR SAME70Q21 */
\r
440 /* ************************************************************************** */
\r
441 /** \addtogroup SAME70Q21_id Peripheral Ids Definitions */
\r
444 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
\r
445 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
\r
446 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
\r
447 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
\r
448 #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
\r
449 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
\r
450 #define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
\r
451 #define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
\r
452 #define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
\r
453 #define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
\r
454 #define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
\r
455 #define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
\r
456 #define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
\r
457 #define ID_USART0 (13) /**< \brief USART 0 (USART0) */
\r
458 #define ID_USART1 (14) /**< \brief USART 1 (USART1) */
\r
459 #define ID_USART2 (15) /**< \brief USART 2 (USART2) */
\r
460 #define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
\r
461 #define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */
\r
462 #define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
\r
463 #define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
\r
464 #define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
\r
465 #define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
\r
466 #define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
\r
467 #define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
\r
468 #define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
\r
469 #define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
\r
470 #define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
\r
471 #define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
\r
472 #define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
\r
473 #define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
\r
474 #define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
\r
475 #define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
\r
476 #define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
\r
477 #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
\r
478 #define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
\r
479 #define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */
\r
480 #define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */
\r
481 #define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */
\r
482 #define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
\r
483 #define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
\r
484 #define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
\r
485 #define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
\r
486 #define ID_UART2 (44) /**< \brief UART 2 (UART2) */
\r
487 #define ID_UART3 (45) /**< \brief UART 3 (UART3) */
\r
488 #define ID_UART4 (46) /**< \brief UART 4 (UART4) */
\r
489 #define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */
\r
490 #define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */
\r
491 #define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */
\r
492 #define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
\r
493 #define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
\r
494 #define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
\r
495 #define ID_AES (56) /**< \brief AES (AES) */
\r
496 #define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
\r
497 #define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
\r
498 #define ID_ISI (59) /**< \brief Camera Interface (ISI) */
\r
499 #define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
\r
500 #define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */
\r
501 #define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
\r
503 #define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
\r
506 /* ************************************************************************** */
\r
507 /* BASE ADDRESS DEFINITIONS FOR SAME70Q21 */
\r
508 /* ************************************************************************** */
\r
509 /** \addtogroup SAME70Q21_base Peripheral Base Address Definitions */
\r
512 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
513 #define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
\r
514 #define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
\r
515 #define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
\r
516 #define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
\r
517 #define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */
\r
518 #define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */
\r
519 #define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
\r
520 #define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
\r
521 #define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
\r
522 #define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
\r
523 #define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
\r
524 #define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
\r
525 #define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */
\r
526 #define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */
\r
527 #define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
\r
528 #define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
\r
529 #define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
\r
530 #define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
\r
531 #define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
\r
532 #define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
\r
533 #define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */
\r
534 #define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
\r
535 #define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
\r
536 #define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
\r
537 #define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
\r
538 #define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
\r
539 #define AES (0x4006C000U) /**< \brief (AES ) Base Address */
\r
540 #define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
\r
541 #define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
\r
542 #define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
\r
543 #define SMC (0x40080000U) /**< \brief (SMC ) Base Address */
\r
544 #define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */
\r
545 #define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
\r
546 #define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
\r
547 #define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
\r
548 #define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
\r
549 #define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
\r
550 #define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
\r
551 #define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
\r
552 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
\r
553 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
\r
554 #define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */
\r
555 #define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
\r
556 #define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */
\r
557 #define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
\r
558 #define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
\r
559 #define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
\r
560 #define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
\r
561 #define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
\r
562 #define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
\r
563 #define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
\r
564 #define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
\r
565 #define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
\r
566 #define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
\r
568 #define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
\r
569 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
\r
570 #define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
\r
571 #define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
\r
572 #define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */
\r
573 #define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */
\r
574 #define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
\r
575 #define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
\r
576 #define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
\r
577 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
\r
578 #define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
\r
579 #define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
\r
580 #define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */
\r
581 #define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */
\r
582 #define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
\r
583 #define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
\r
584 #define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
\r
585 #define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
\r
586 #define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
\r
587 #define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
\r
588 #define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */
\r
589 #define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
\r
590 #define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
\r
591 #define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
\r
592 #define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
\r
593 #define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
\r
594 #define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
\r
595 #define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
\r
596 #define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
\r
597 #define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
\r
598 #define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */
\r
599 #define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */
\r
600 #define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
\r
601 #define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
\r
602 #define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
\r
603 #define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
\r
604 #define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
\r
605 #define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
\r
606 #define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
\r
607 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
\r
608 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
\r
609 #define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */
\r
610 #define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
\r
611 #define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */
\r
612 #define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
\r
613 #define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
\r
614 #define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
\r
615 #define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
\r
616 #define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
\r
617 #define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
\r
618 #define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
\r
619 #define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
\r
620 #define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
\r
621 #define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
\r
622 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
625 /* ************************************************************************** */
\r
626 /* PIO DEFINITIONS FOR SAME70Q21 */
\r
627 /* ************************************************************************** */
\r
628 /** \addtogroup SAME70Q21_pio Peripheral Pio Definitions */
\r
631 #include "pio/same70q21.h"
\r
634 /* ************************************************************************** */
\r
635 /* MEMORY MAPPING DEFINITIONS FOR SAME70Q21 */
\r
636 /* ************************************************************************** */
\r
638 #define IFLASH_SIZE (0x200000u)
\r
639 #define IFLASH_PAGE_SIZE (512u)
\r
640 #define IFLASH_LOCK_REGION_SIZE (8192u)
\r
641 #define IFLASH_NB_OF_PAGES (4096u)
\r
642 #define IFLASH_NB_OF_LOCK_BITS (128u)
\r
643 #define IRAM_SIZE (0x60000u)
\r
645 #define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
\r
646 #define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
\r
647 #define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
\r
648 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
\r
649 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
\r
650 #define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
\r
651 #define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
\r
652 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
\r
653 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
\r
654 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
\r
655 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
\r
656 #define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
\r
658 /* ************************************************************************** */
\r
659 /* MISCELLANEOUS DEFINITIONS FOR SAME70Q21 */
\r
660 /* ************************************************************************** */
\r
662 #define CHIP_JTAGID (0x05B3D03FUL)
\r
663 #define CHIP_CIDR (0xA1020E00UL)
\r
664 #define CHIP_EXID (0x00000002UL)
\r
666 /* ************************************************************************** */
\r
667 /* ELECTRICAL DEFINITIONS FOR SAME70Q21 */
\r
668 /* ************************************************************************** */
\r
670 /* %ATMEL_ELECTRICAL% */
\r
672 /* Device characteristics */
\r
673 #define CHIP_FREQ_SLCK_RC_MIN (20000UL)
\r
674 #define CHIP_FREQ_SLCK_RC (32000UL)
\r
675 #define CHIP_FREQ_SLCK_RC_MAX (44000UL)
\r
676 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
\r
677 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
\r
678 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
\r
679 #define CHIP_FREQ_CPU_MAX (300000000UL)
\r
680 #define CHIP_FREQ_XTAL_32K (32768UL)
\r
681 #define CHIP_FREQ_XTAL_12M (12000000UL)
\r
683 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
\r
684 #define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
\r
685 #define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
\r
686 #define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
\r
687 #define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
\r
688 #define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
\r
689 #define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
\r
697 #endif /* _SAME70Q21_ */
\r