1 /**************************************************************************//**
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2 * @file core_cmFunc.h
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3 * @brief CMSIS Cortex-M Core Function Access Header File
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5 * @date 28. August 2014
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9 ******************************************************************************/
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10 /* Copyright (c) 2009 - 2014 ARM LIMITED
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12 All rights reserved.
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13 Redistribution and use in source and binary forms, with or without
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14 modification, are permitted provided that the following conditions are met:
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15 - Redistributions of source code must retain the above copyright
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16 notice, this list of conditions and the following disclaimer.
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17 - Redistributions in binary form must reproduce the above copyright
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18 notice, this list of conditions and the following disclaimer in the
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19 documentation and/or other materials provided with the distribution.
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20 - Neither the name of ARM nor the names of its contributors may be used
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21 to endorse or promote products derived from this software without
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22 specific prior written permission.
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24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 POSSIBILITY OF SUCH DAMAGE.
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35 ---------------------------------------------------------------------------*/
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38 #ifndef __CORE_CMFUNC_H
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39 #define __CORE_CMFUNC_H
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42 /* ########################### Core Function Access ########################### */
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43 /** \ingroup CMSIS_Core_FunctionInterface
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44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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49 /* ARM armcc specific functions */
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51 #if (__ARMCC_VERSION < 400677)
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52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
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55 /* intrinsic void __enable_irq(); */
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56 /* intrinsic void __disable_irq(); */
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58 /** \brief Get Control Register
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60 This function returns the content of the Control Register.
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62 \return Control Register value
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64 __STATIC_INLINE uint32_t __get_CONTROL(void)
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66 register uint32_t __regControl __ASM("control");
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67 return(__regControl);
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71 /** \brief Set Control Register
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73 This function writes the given value to the Control Register.
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75 \param [in] control Control Register value to set
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77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
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79 register uint32_t __regControl __ASM("control");
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80 __regControl = control;
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84 /** \brief Get IPSR Register
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86 This function returns the content of the IPSR Register.
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88 \return IPSR Register value
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90 __STATIC_INLINE uint32_t __get_IPSR(void)
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92 register uint32_t __regIPSR __ASM("ipsr");
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97 /** \brief Get APSR Register
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99 This function returns the content of the APSR Register.
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101 \return APSR Register value
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103 __STATIC_INLINE uint32_t __get_APSR(void)
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105 register uint32_t __regAPSR __ASM("apsr");
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110 /** \brief Get xPSR Register
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112 This function returns the content of the xPSR Register.
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114 \return xPSR Register value
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116 __STATIC_INLINE uint32_t __get_xPSR(void)
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118 register uint32_t __regXPSR __ASM("xpsr");
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123 /** \brief Get Process Stack Pointer
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125 This function returns the current value of the Process Stack Pointer (PSP).
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127 \return PSP Register value
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129 __STATIC_INLINE uint32_t __get_PSP(void)
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131 register uint32_t __regProcessStackPointer __ASM("psp");
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132 return(__regProcessStackPointer);
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136 /** \brief Set Process Stack Pointer
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138 This function assigns the given value to the Process Stack Pointer (PSP).
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140 \param [in] topOfProcStack Process Stack Pointer value to set
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142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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144 register uint32_t __regProcessStackPointer __ASM("psp");
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145 __regProcessStackPointer = topOfProcStack;
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149 /** \brief Get Main Stack Pointer
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151 This function returns the current value of the Main Stack Pointer (MSP).
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153 \return MSP Register value
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155 __STATIC_INLINE uint32_t __get_MSP(void)
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157 register uint32_t __regMainStackPointer __ASM("msp");
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158 return(__regMainStackPointer);
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162 /** \brief Set Main Stack Pointer
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164 This function assigns the given value to the Main Stack Pointer (MSP).
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166 \param [in] topOfMainStack Main Stack Pointer value to set
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168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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170 register uint32_t __regMainStackPointer __ASM("msp");
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171 __regMainStackPointer = topOfMainStack;
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175 /** \brief Get Priority Mask
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177 This function returns the current state of the priority mask bit from the Priority Mask Register.
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179 \return Priority Mask value
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181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
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183 register uint32_t __regPriMask __ASM("primask");
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184 return(__regPriMask);
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188 /** \brief Set Priority Mask
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190 This function assigns the given value to the Priority Mask Register.
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192 \param [in] priMask Priority Mask
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194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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196 register uint32_t __regPriMask __ASM("primask");
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197 __regPriMask = (priMask);
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201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
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203 /** \brief Enable FIQ
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205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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206 Can only be executed in Privileged modes.
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208 #define __enable_fault_irq __enable_fiq
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211 /** \brief Disable FIQ
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213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
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214 Can only be executed in Privileged modes.
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216 #define __disable_fault_irq __disable_fiq
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219 /** \brief Get Base Priority
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221 This function returns the current value of the Base Priority register.
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223 \return Base Priority register value
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225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
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227 register uint32_t __regBasePri __ASM("basepri");
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228 return(__regBasePri);
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232 /** \brief Set Base Priority
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234 This function assigns the given value to the Base Priority register.
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236 \param [in] basePri Base Priority value to set
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238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
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240 register uint32_t __regBasePri __ASM("basepri");
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241 __regBasePri = (basePri & 0xff);
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245 /** \brief Get Fault Mask
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247 This function returns the current value of the Fault Mask register.
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249 \return Fault Mask register value
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251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
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253 register uint32_t __regFaultMask __ASM("faultmask");
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254 return(__regFaultMask);
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258 /** \brief Set Fault Mask
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260 This function assigns the given value to the Fault Mask register.
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262 \param [in] faultMask Fault Mask value to set
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264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
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266 register uint32_t __regFaultMask __ASM("faultmask");
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267 __regFaultMask = (faultMask & (uint32_t)1);
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270 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
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273 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
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275 /** \brief Get FPSCR
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277 This function returns the current value of the Floating Point Status/Control register.
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279 \return Floating Point Status/Control register value
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281 __STATIC_INLINE uint32_t __get_FPSCR(void)
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283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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284 register uint32_t __regfpscr __ASM("fpscr");
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285 return(__regfpscr);
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292 /** \brief Set FPSCR
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294 This function assigns the given value to the Floating Point Status/Control register.
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296 \param [in] fpscr Floating Point Status/Control value to set
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298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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301 register uint32_t __regfpscr __ASM("fpscr");
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302 __regfpscr = (fpscr);
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306 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
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309 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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310 /* GNU gcc specific functions */
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312 /** \brief Enable IRQ Interrupts
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314 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
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315 Can only be executed in Privileged modes.
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317 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
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319 __ASM volatile ("cpsie i" : : : "memory");
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323 /** \brief Disable IRQ Interrupts
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325 This function disables IRQ interrupts by setting the I-bit in the CPSR.
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326 Can only be executed in Privileged modes.
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328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
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330 __ASM volatile ("cpsid i" : : : "memory");
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334 /** \brief Get Control Register
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336 This function returns the content of the Control Register.
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338 \return Control Register value
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340 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
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344 __ASM volatile ("MRS %0, control" : "=r" (result) );
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349 /** \brief Set Control Register
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351 This function writes the given value to the Control Register.
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353 \param [in] control Control Register value to set
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355 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
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357 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
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361 /** \brief Get IPSR Register
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363 This function returns the content of the IPSR Register.
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365 \return IPSR Register value
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367 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
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371 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
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376 /** \brief Get APSR Register
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378 This function returns the content of the APSR Register.
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380 \return APSR Register value
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382 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
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386 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
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391 /** \brief Get xPSR Register
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393 This function returns the content of the xPSR Register.
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395 \return xPSR Register value
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397 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
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401 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
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406 /** \brief Get Process Stack Pointer
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408 This function returns the current value of the Process Stack Pointer (PSP).
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410 \return PSP Register value
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412 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
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414 register uint32_t result;
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416 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
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421 /** \brief Set Process Stack Pointer
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423 This function assigns the given value to the Process Stack Pointer (PSP).
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425 \param [in] topOfProcStack Process Stack Pointer value to set
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427 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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429 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
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433 /** \brief Get Main Stack Pointer
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435 This function returns the current value of the Main Stack Pointer (MSP).
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437 \return MSP Register value
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439 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
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441 register uint32_t result;
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443 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
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448 /** \brief Set Main Stack Pointer
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450 This function assigns the given value to the Main Stack Pointer (MSP).
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452 \param [in] topOfMainStack Main Stack Pointer value to set
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454 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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456 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
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460 /** \brief Get Priority Mask
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462 This function returns the current state of the priority mask bit from the Priority Mask Register.
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464 \return Priority Mask value
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466 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
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470 __ASM volatile ("MRS %0, primask" : "=r" (result) );
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475 /** \brief Set Priority Mask
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477 This function assigns the given value to the Priority Mask Register.
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479 \param [in] priMask Priority Mask
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481 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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483 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
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487 #if (__CORTEX_M >= 0x03)
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489 /** \brief Enable FIQ
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491 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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492 Can only be executed in Privileged modes.
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494 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
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496 __ASM volatile ("cpsie f" : : : "memory");
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500 /** \brief Disable FIQ
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502 This function disables FIQ interrupts by setting the F-bit in the CPSR.
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503 Can only be executed in Privileged modes.
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505 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
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507 __ASM volatile ("cpsid f" : : : "memory");
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511 /** \brief Get Base Priority
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513 This function returns the current value of the Base Priority register.
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515 \return Base Priority register value
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517 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
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521 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
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526 /** \brief Set Base Priority
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528 This function assigns the given value to the Base Priority register.
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530 \param [in] basePri Base Priority value to set
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532 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
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534 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
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538 /** \brief Get Fault Mask
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540 This function returns the current value of the Fault Mask register.
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542 \return Fault Mask register value
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544 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
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548 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
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553 /** \brief Set Fault Mask
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555 This function assigns the given value to the Fault Mask register.
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557 \param [in] faultMask Fault Mask value to set
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559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
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561 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
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564 #endif /* (__CORTEX_M >= 0x03) */
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567 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
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569 /** \brief Get FPSCR
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571 This function returns the current value of the Floating Point Status/Control register.
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573 \return Floating Point Status/Control register value
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575 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
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577 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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580 /* Empty asm statement works as a scheduling barrier */
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581 __ASM volatile ("");
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582 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
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583 __ASM volatile ("");
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591 /** \brief Set FPSCR
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593 This function assigns the given value to the Floating Point Status/Control register.
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595 \param [in] fpscr Floating Point Status/Control value to set
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597 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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599 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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600 /* Empty asm statement works as a scheduling barrier */
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601 __ASM volatile ("");
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602 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
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603 __ASM volatile ("");
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607 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
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610 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
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611 /* IAR iccarm specific functions */
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612 #include <cmsis_iar.h>
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615 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
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616 /* TI CCS specific functions */
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617 #include <cmsis_ccs.h>
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620 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
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621 /* TASKING carm specific functions */
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623 * The CMSIS functions have been implemented as intrinsics in the compiler.
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624 * Please use "carm -?i" to get an up to date list of all intrinsics,
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625 * Including the CMSIS ones.
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629 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
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630 /* Cosmic specific functions */
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631 #include <cmsis_csm.h>
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635 /*@} end of CMSIS_Core_RegAccFunctions */
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637 #endif /* __CORE_CMFUNC_H */
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