1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2013, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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33 * Interface for the S25fl1 Serialflash driver.
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40 /*----------------------------------------------------------------------------
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42 *----------------------------------------------------------------------------*/
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44 #define Size(pAt25) ((pAt25)->pDesc->size)
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45 #define PageSize(pAt25) ((pAt25)->pDesc->pageSize)
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46 #define BlockSize(pAt25) ((pAt25)->pDesc->blockSize)
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47 #define Name(pAt25) ((pAt25)->pDesc->name)
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48 #define ManId(pAt25) (((pAt25)->pDesc->jedecId) & 0xFF)
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49 #define PageNumber(pAt25) (Size(pAt25) / PageSize(pAt25))
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50 #define BlockNumber(pAt25) (Size(pAt25) / BlockSize(pAt25))
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51 #define PagePerBlock(pAt25) (BlockSize(pAt25) / PageSize(pAt25))
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52 #define BlockEraseCmd(pAt25) ((pAt25)->pDesc->blockEraseCmd)
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54 /*----------------------------------------------------------------------------
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56 *----------------------------------------------------------------------------*/
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58 /** Device is protected, operation cannot be carried out. */
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59 #define ERROR_PROTECTED 1
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60 /** Device is busy executing a command. */
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61 #define ERROR_BUSY 2
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62 /** There was a problem while trying to program page data. */
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63 #define ERROR_PROGRAM 3
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64 /** There was an SPI communication error. */
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67 /** Device ready/busy status bit. */
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68 #define STATUS_RDYBSY (1 << 0)
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69 /** Device is ready. */
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70 #define STATUS_RDYBSY_READY (0 << 0)
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71 /** Device is busy with internal operations. */
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72 #define STATUS_RDYBSY_BUSY (1 << 0)
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73 /** Write enable latch status bit. */
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74 #define STATUS_WEL (1 << 1)
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75 /** Device is not write enabled. */
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76 #define STATUS_WEL_DISABLED (0 << 1)
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77 /** Device is write enabled. */
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78 #define STATUS_WEL_ENABLED (1 << 1)
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79 /** Software protection status bitfield. */
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80 #define STATUS_SWP (3 << 2)
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81 /** All sectors are software protected. */
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82 #define STATUS_SWP_PROTALL (3 << 2)
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83 /** Some sectors are software protected. */
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84 #define STATUS_SWP_PROTSOME (1 << 2)
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85 /** No sector is software protected. */
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86 #define STATUS_SWP_PROTNONE (0 << 2)
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87 /** Write protect pin status bit. */
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88 #define STATUS_WPP (1 << 4)
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89 /** Write protect signal is not asserted. */
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90 #define STATUS_WPP_NOTASSERTED (0 << 4)
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91 /** Write protect signal is asserted. */
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92 #define STATUS_WPP_ASSERTED (1 << 4)
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93 /** Erase/program error bit. */
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94 #define STATUS_EPE (1 << 5)
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95 /** Erase or program operation was successful. */
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96 #define STATUS_EPE_SUCCESS (0 << 5)
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97 /** Erase or program error detected. */
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98 #define STATUS_EPE_ERROR (1 << 5)
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99 /** Sector protection registers locked bit. */
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100 #define STATUS_SPRL (1 << 7)
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101 /** Sector protection registers are unlocked. */
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102 #define STATUS_SPRL_UNLOCKED (0 << 7)
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103 /** Sector protection registers are locked. */
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104 #define STATUS_SPRL_LOCKED (1 << 7)
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106 /** Quad enable bit */
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107 #define STATUS_QUAD_ENABLE (1 << 1)
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108 /** Quad enable bit */
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109 #define STATUS_WRAP_ENABLE (0 << 4)
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111 #define STATUS_WRAP_BYTE (1 << 5)
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113 /** Read array command code. */
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114 #define READ_ARRAY 0x0B
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115 /** Read array (low frequency) command code. */
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116 #define READ_ARRAY_LF 0x03
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117 /** Fast Read array command code. */
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118 #define READ_ARRAY_DUAL 0x3B
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119 /** Fast Read array command code. */
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120 #define READ_ARRAY_QUAD 0x6B
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121 /** Fast Read array command code. */
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122 #define READ_ARRAY_DUAL_IO 0xBB
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123 /** Fast Read array command code. */
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124 #define READ_ARRAY_QUAD_IO 0xEB
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125 /** Block erase command code (4K block). */
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126 #define BLOCK_ERASE_4K 0x20
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127 /** Block erase command code (32K block). */
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128 #define BLOCK_ERASE_32K 0x52
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129 /** Block erase command code (64K block). */
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130 #define BLOCK_ERASE_64K 0xD8
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131 /** Chip erase command code 1. */
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132 #define CHIP_ERASE_1 0x60
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133 /** Chip erase command code 2. */
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134 #define CHIP_ERASE_2 0xC7
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135 /** Byte/page program command code. */
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136 #define BYTE_PAGE_PROGRAM 0x02
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137 /** Sequential program mode command code 1. */
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138 #define SEQUENTIAL_PROGRAM_1 0xAD
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139 /** Sequential program mode command code 2. */
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140 #define SEQUENTIAL_PROGRAM_2 0xAF
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141 /** Write enable command code. */
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142 #define WRITE_ENABLE 0x06
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143 /** Write disable command code. */
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144 #define WRITE_DISABLE 0x04
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145 /** Protect sector command code. */
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146 #define PROTECT_SECTOR 0x36
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147 /** Unprotect sector command code. */
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148 #define UNPROTECT_SECTOR 0x39
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149 /** Read sector protection registers command code. */
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150 #define READ_SECTOR_PROT 0x3C
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151 /** Read status register command code. */
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152 #define READ_STATUS 0x05
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153 /** Write status register command code. */
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154 #define WRITE_STATUS 0x01
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155 /** Read manufacturer and device ID command code. */
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156 #define READ_JEDEC_ID 0x9F
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157 /** Deep power-down command code. */
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158 #define DEEP_PDOWN 0xB9
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159 /** Resume from deep power-down command code. */
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160 #define RES_DEEP_PDOWN 0xAB
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161 /** Resume from deep power-down command code. */
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162 #define SOFT_RESET_ENABLE 0x66
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163 /** Resume from deep power-down command code. */
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164 #define SOFT_RESET 0x99
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165 /** Resume from deep power-down command code. */
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166 #define WRAP_ENABLE 0x77
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170 /** SPI Flash Manufacturer JEDEC ID */
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171 #define ATMEL_SPI_FLASH 0x1F
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172 #define ST_SPI_FLASH 0x20
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173 #define WINBOND_SPI_FLASH 0xEF
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174 #define MACRONIX_SPI_FLASH 0xC2
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175 #define SST_SPI_FLASH 0xBF
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184 /*----------------------------------------------------------------------------
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185 * Exported functions
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186 *----------------------------------------------------------------------------*/
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188 extern unsigned int S25FL1D_ReadJedecId(void);
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190 extern void S25FL1D_InitFlashInterface(void);
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192 extern void S25FL1D_SoftReset(void);
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194 extern unsigned char S25FL1D_Unprotect(void);
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196 extern unsigned char S25FL1D_Protect(uint32_t StartAddr, uint32_t Size);
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198 extern void S25FL1D_EnableQuadMode(void);
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200 extern void S25FL1D_EnableWrap(uint8_t ByetAlign);
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202 extern unsigned char S25FL1D_EraseChip(void);
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204 extern unsigned char S25FL1D_EraseSector( unsigned int address);
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206 extern unsigned char S25FL1D_Erase64KBlock( unsigned int address);
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208 extern unsigned char S25FL1D_Write(
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213 extern unsigned char S25FL1D_Read(
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218 extern unsigned char S25FL1D_ReadDual(
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223 extern unsigned char S25FL1D_ReadQuad(
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228 extern unsigned char S25FL1D_ReadQuadIO(
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234 #endif // #ifndef S25FL1_H
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